Owner's Manual for onsemi models including: FDD10AN06A0 N Channel Powertrench Mosfet, FDD10AN06A0, N Channel Powertrench Mosfet, Powertrench Mosfet, Mosfet
[ON SEMICONDUCTOR] FDD10AN06A0 반도체 > TR/FET/IGBT > MOSFET (주)엘레파츠 - 엘레파츠
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DocumentDocumentMOSFET N-Channel, POWERTRENCH)
60 V, 50 A, 10.5 mW
FDD10AN06A0
Features
· RDS(on) = 9.4 mW (Typ.), VGS = 10 V, ID = 50 A · Qg(tot) = 28 nC (Typ.), VGS = 10 V · Low Miller Charge · Low Qrr Body Diode · UIS Capability (Single Pulse and Repetitive Pulse) · This Device is Pb-Free, Halide Free and is RoHS Compliant
Applications
· Motor / Body Load Control · ABS Systems · Powertrain Management · Injection Systems · DC-DC Converters and Off-line UPS · Distributed Power Architectures and VRMs · Primary Switch for 12 V and 24 V Systems
MOSFET MAXIMUM RATINGS (TC = 25°C, unless otherwise noted)
Symbol
Parameter
Ratings Unit
VDSS VGS ID
Drain to Source Voltage
Gate to Source Voltage
Drain Current Continuous (TC < 115°C, VGS = 10 V) Continuous (Tamb = 25°C, VGS = 10 V,
RqJA = 52°C/W) Pulsed
60
V
±20
V
A 50 11
Figure 4
EAS Single Pulse Avalanche Energy (Note 1) PD Power Dissipation
Derate above 25°C
429
mJ
135
W
0.9
W/°C
TJ, TSTG Operating and Storage Temperature
-55 to 175 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Starting TJ = 25°C, L = 8.58 mH, IAS = 10 A.
DATA SHEET www.onsemi.com
VDSS 60 V
RDS(on) MAX 10.5 mW @ 10 V
ID MAX 50 A
DRAIN (FLANGE)
GATE
SOURCE DPAK3 (TO-252 3 LD)
CASE 369AS
MARKING DIAGRAM
&Z&3&K FDD10AN0
6A0
&Z
= Assembly Plant Code
&3
= 3-Digit Date Code
&K
= 2-Digits Lot Run Traceability Code
FDD10AN06A0 = Specific Device Code
D
G S
N-Channel MOSFET
ORDERING INFORMATION
See detailed ordering and shipping information on page 12 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
1
June, 2023 - Rev. 4
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Publication Order Number: FDD10AN06A0/D
FDD10AN06A0
THERMAL CHARACTERISTICS (TC = 25°C, unless otherwise noted)
Symbol
Parameter
RqJC RqJA RqJA
Thermal Resistance Junction to Case, TO-252 Thermal Resistance Junction to Ambient, TO-252 Thermal Resistance Junction to Ambient, TO-252, 1 in2 Copper Pad Area
Ratings 1.11 100 52
Unit °C/W
°C/W
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Symbol
Parameter
Test Condition
Min
Typ
Max Unit
OFF CHARACTERISTICS
BVDSS IDSS
Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ON CHARACTERISTICS
ID = 250 mA, VGS = 0 V VDS = 50 V, VGS = 0 V VDS = 50 V, VGS = 0 V, TC = 150°C VGS = ±20 V
60
-
-
V
-
-
1
mA
-
-
250
-
-
±100
nA
VGS(TH) RDS(on)
Gate to Source Threshold Voltage Drain to Source On Resistance
DYNAMIC CHARACTERISTICS
VGS = VDS, ID = 250 mA ID = 50 A, VGS = 10 V ID = 50 A, VGS = 10 V, TJ = 175°C
2
-
4
V
-
0.0094 0.0105
W
-
0.020 0.023
CISS COSS CRSS
Input Capacitance Output Capacitance Reverse Transfer Capacitance
VDS = 25 V, VGS = 0 V, f = 1 MHz
-
1840
-
pF
-
340
-
pF
-
110
-
pF
Qg(TOT) Total Gate Charge at 10 V
VGS = 0 V to 10 V, VDD = 30 V, ID = 50 A,
-
Ig = 1.0 mA
28
37
nC
Qg(TH) Threshold Gate Charge
VGS = 0 V to 2 V, VDD = 30 V, ID = 50 A,
-
Ig = 1.0 mA
3.5
4.6
nC
Qgs
Gate to Source Gate Charge
VDD = 30 V, ID = 50 A, Ig = 1.0 mA
-
9.8
-
nC
Qgs2
Gate Charge Threshold to Plateau
Qgd
Gate to Drain "Miller" Charge
SWITCHING CHARACTERISTICS (VGS = 10 V)
tON
Turn-On Time
td(ON)
Turn-On Delay Time
tr
Rise Time
td(OFF) Turn-Off Delay Time
tf
Fall Time
VDD = 30 V, ID = 50 A VGS = 10 V, RGS = 10 W
-
6.4
-
nC
-
7.8
-
nC
-
-
131
ns
-
8
-
ns
-
79
-
ns
-
32
-
ns
-
32
-
ns
tOFF
Turn-Off Time
DRAIN-SOURCE DIODE CHARACTERISTICS
-
-
97
ns
VSD
Source to Drain Diode Voltage
ISD = 50 A
-
-
1.25
V
ISD = 25 A
-
-
1.0
V
trr
Reverse Recovery Time
ISD = 50 A, dISD/dt = 100 A/ms
-
-
27
ns
QRR
Reverse Recovered Charge
ISD = 50 A, dISD/dt = 100 A/ms
-
-
23
nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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POWER DISSIPATION MULTIPLIER
ZqJC, NORMALIZED THERMAL IMPEDANCE
FDD10AN06A0
TYPICAL CHARACTERISTICS (TC = 25°C, unless otherwise noted)
1.2
1.0
0.8
0.6 0.4
0.2
0
0
25 50 75 100 125 150 175
TC, CASE TEMPERATURE (°C)
Figure 1. Normalized Power Dissipation vs. Ambient Temperature
ID, DRAIN CURRENT (A)
80 CURRENT LIMITED BY PACKAGE
60
40
20
0
25
50
75
100 125 150 175
TC, CASE TEMPERATURE (°C)
Figure 2. Maximum Continuous Drain Current vs. Case Temperature
2 DUTY CYCLE - DESCENDING ORDER
1 0.5
0.2
0.1
0.05
0.02
0.01 0.1
PDM
0.01 10 -5
SINGLE PULSE 10 -4
10 -3
10 -2
t1 t2
NOTES:
DUTY FACTOR: D = t1 / t2 PEAK TJ = PDM x ZqJC x RqJC + TC
10 -1
10 0
10 1
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
1000
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION
VGS = 10 V 100
TC = 25°C FOR TEMPERATURES
ABOVE 25°C DERATE PEAK
CURRENT AS FOLLOWS:
I + I25
175 * TC 150
40
10 -5
10 -4
10 -3
10 -2
10 -1
10 0
10 1
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
IDM, PEAK CURRENT (A)
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ID, DRAIN CURRENT (A)
FDD10AN06A0
TYPICAL CHARACTERISTICS (TC = 25°C, unless otherwise noted) (continued)
IAS, AVALANCHE CURRENT (A)
500
500
If R = 0
100
10 ms 100 ms
100
tAV = (L) (IAS) / (1.3 x RATED BVDSS - VDD) If R 0
tAV = (L / R) ln [(IAS x R) / (1.3 x RATED BVDSS - VDD) + 1]
10 OPERATION IN THIS
1 ms
AREA MAY BE LIMITED
BY RDS(on)
1 SINGLE PULSE
10 ms DC
TJ = MAX RATED
TC = 25°C
0.1
1
10
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 5. Forward Bias Safe Operating Area
STARTING TJ = 25°C 10
STARTING TJ = 150°C
1
0.01
0.1
1
10
tAV, TIME IN AVALANCHE (ms) NOTE: Refer to onsemi Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching Capability
100 PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX
75 VDD = 15 V
50 TJ = 25°C
25
TJ = 175°C
TJ = -55°C
0
3
4
5
6
7
VGS, GATE TO SOURCE VOLTAGE (V) Figure 7. Transfer Characteristics
ID, DRAIN CURRENT (A)
100 VGS = 10 V
75
50
VGS = 7 V VGS = 6 V
25
VGS = 5 V
PULSE DURATION = 80 ms TC = 25°C DUTY CYCLE = 0.5% MAX 0
0
0.5
1.0
1.5
2.0
VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 8. Saturation Characteristics
ID, DRAIN CURRENT (A)
DRAIN TO SOURCE ON RESISTANCE(mW)
18 PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX
16
14
VGS = 6 V
12
10
VGS = 10 V
8
0
10
20
30
40
50
ID, DRAIN CURRENT (A)
Figure 9. Drain to Source On Resistance vs. Drain Current
NORMALIZED DRAIN TO SOURCE ON RESISTANCE
2.5 PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX
2.0
1.5
1.0
0.5 -80 -40 0
VGS = 10 V, ID = 50 A 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (°C)
Figure 10. Normalized Drain to Source On Resistance vs. Junction Temperature
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NORMALIZED GATE THRESHOLD VOLTAGE
FDD10AN06A0
TYPICAL CHARACTERISTICS (TC = 25°C, unless otherwise noted) (continued)
NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE
1.4
1.2
VGS = VDS, ID = 250 mA
ID = 250 mA
1.2
1.1 1.0
0.8 1.0
0.6
0.4 -80 -40 0
40 80 120 160 200
TJ, JUNCTION TEMPERATURE (°C)
Figure 11. Normalized Gate Threshold Voltage vs. Junction Temperature
0.9 -80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (°C)
Figure 12. Normalized Drain to Source Breakdown Voltage vs. Junction Temperature
VGS, GATE TO SOURCE VOLTAGE (V)
3000 1000 COSS @ CDS + CGD
CRSS = CGD
CISS = CGS + CGD
100
VGS = 0 V, f = 1 MHz 50
0.1
1
10
60
VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 13. Capacitance vs. Drain to Source Voltage
10 VDD = 30 V
8
6
4
WAVEFORMS IN
2
DESCENDING ORDER:
ID = 50 A
ID = 11 A 0
0
5
10
15
20
25
30
Qg, GATE CHARGE (nC)
Figure 14. Gate Charge Waveforms for Constant Gate Currents
C, CAPACITANCE (pF)
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FDD10AN06A0
TEST CIRCUITS AND WAVEFORMS
VARY tP TO OBTAIN
REQUIRED PEAK IAS
RG
VGS
tP 0 V
VDS
L
DUT
+
VDD -
IAS 0.01 W
Figure 15. Unclamped Energy Test Circuit
tP IAS
BVDSS
VDS
VDD
0 t AV
Figure 16. Unclamped Energy Waveforms
VGS Ig(REF)
VDS L
DUT
+
VDD -
Figure 17. Gate Charge Test Circuit
VDD Qgs2
Qg(TOT)
VDS
VGS
VGS = 10 V
VGS = 2 V
0
Qg(TH)
Qgs
Qgd
Ig(REF) 0
Figure 18. Gate Charge Waveforms
V DS RL
VGS RGS
DUT
+
V DD -
VGS
Figure 19. Switching Time Test Circuit
V DS
tON td(ON)
tr 90%
t OFF td(OFF)
tf
90%
10% 0
10%
VGS 10%
0
50%
PULSE WIDTH
90% 50%
Figure 20. Switching Time Waveforms
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FDD10AN06A0
THERMAL RESISTANCE VS. MOUNTING PAD AREA
The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an application. Therefore the application's ambient
temperature, TA (°C), and thermal resistance RqJA (°C/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
TJM * TA
PDM +
RqJA
(eq. 1)
In using surface mount devices such as the TO-252
package, the environment in which it is applied will have a
significant influence on the part's current and maximum
power dissipation ratings. Precise determination of PDM is complex and influenced by many factors:
1. Mounting pad area onto which the device is
attached and whether there is copper on one side
or both sides of the board.
2. The number of copper layers and the thickness of
the board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width,
the duty cycle and the transient thermal response of
the part, the board and the environment they are in.
onsemi provides thermal information to assist the
designer's preliminary application evaluation. Figure 21
defines the RqJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned
FR-4 board with 1 oz copper after 1000 seconds of steady
state power with no air flow. This graph provides the
necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse applications
can be evaluated using the onsemi device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and Equation 3 is for area in centimeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads.
23.84 RqJA + 33.32 ) (0.268 ) Area)
(eq. 2)
Area in Inches Squared
RqJA
+
33.32
)
154 (1.73 ) Area)
(eq. 3) Area in Centimeters Squared
125 RqJA = 33.32 + 23.84 / (0.268 + Area) eq.2 RqJA = 33.32 + 154 / (1.73 + Area) eq.3
100
RqJA (°C/W)
75
50
25 0.01
(0.0645)
0.1 (0.645)
1 (6.45)
AREA, TOP COPPER AREA in2 (cm2)
10 (64.5)
Figure 21. Thermal Resistance vs. Mounting Pad Area
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FDD10AN06A0
.SUBCKT FDD10AN06A0 2 1 3 ; Ca 12 8 7e-10 Cb 15 14 7e-10 Cin 6 8 1.8e-9
PSPICE ELECTRICAL MODEL rev July 2002
Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 67.2 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 3.2e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 1.2e-9
RLgate 1 9 32 RLdrain 2 5 10 RLsource 3 7 12
Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 1.35e-3 Rgate 9 20 3.6 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 6e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),7))}
.MODEL DbodyMOD D (IS=2E-11 N=1.06 RS=3.3e-3 TRS1=2.4e-3 TRS2=1.1e-6 + CJO=1.25e-9 M=5.3e-1 TT=4.2e-8 XTI=3.9) .MODEL DbreakMOD D (RS=2.7e-1 TRS1=1e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=4.7e-10 IS=1e-30 N=10 M=0.44)
.MODEL MmedMOD NMOS (VTO=3.5 KP=5.5 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.6) .MODEL MstroMOD NMOS (VTO=4.25 KP=80 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=2.92 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=36 RS=0.1)
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FDD10AN06A0
.MODEL RbreakMOD RES (TC1=9e-4 TC2=5e-7) .MODEL RdrainMOD RES (TC1=2.5e-2 TC2=7.8e-5) .MODEL RSLCMOD RES (TC1=1e-3 TC2=3.5e-5) .MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-5.3e-3 TC2=-1.3e-5) .MODEL RvtempMOD RES (TC1=-2.6e-3 TC2=1.3e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-8 VOFF=-5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5 VOFF=-8) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-1.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-2) .ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
GATE 1
DPLCAP 5
10
RSLC2
RSLC1 51
5 51
ESLC
DBREAK 11
LDRAIN
DRAIN 2
RLDRAIN
- +
LGATE RLGATE
-
ESG
6 8
+
EVTEMP
RGATE + 18 - 6
9
20 22
EVTHRES
+ 19 - 8
CIN
S1A
12 13 8
S2A
14
15
13
50 RDRAIN
16 21
+ 17 EBREAK 18 -
MWEAK
DBODY
MMED MSTRO
8
7
RSOURCE
LSOURCE SOURCE 3
RLSOURCE
RBREAK
17
18
S1B
S2B
CA
13
CB
+
+ 14
EGS
6 8
-
EDS
5 8
-
RVTEMP
19
IT
-
VBAT
+
8 22
RVTHRES
Figure 22.
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FDD10AN06A0
SABER ELECTRICAL MODEL
REV July 2002 template FDD10AN06A0 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=2e-11,nl=1.06,rs=3.3e-3,trs1=2.4e-3,trs2=1.1e-6,cjo=1.25e-9,m=5.3e-1,tt=4.2e-8,xti=3.9) dp..model dbreakmod = (rs=2.7e-1,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=4.7e-10,isl=10e-30,nl=10,m=0.44) m..model mmedmod = (type=_n,vto=3.5,kp=5.5,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.25,kp=80,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=2.92,kp=0.03,is=1e-30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-8,voff=-5) sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-5,voff=-8) sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2,voff=-1.5) sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-1.5,voff=-2) c.ca n12 n8 = 7e-10 c.cb n15 n14 = 7e-10 c.cin n6 n8 = 1.8e-9
dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11 n7 n17 n18 = 67.2 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1
l.lgate n1 n9 = 3.2e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 1.2e-9
res.rlgate n1 n9 = 32 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 12
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1=9e-4,tc2=5e-7 res.rdrain n50 n16 = 1.35e-3, tc1=2.5e-2,tc2=7.8e-5 res.rgate n9 n20 = 3.6 res.rslc1 n5 n51 = 1e-6, tc1=1e-3,tc2=3.5e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 6e-3, tc1=1e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-5.3e-3,tc2=-1.3e-5 res.rvtemp n18 n19 = 1, tc1=-2.6e-3,tc2=1.3e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
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FDD10AN06A0
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 7)) }
GATE 1
DPLCAP 10
RSLC2
5
RSLC1 51
ISCL
LDRAIN RLDRAIN
DRAIN 2
LGATE RLGATE
-
ESG
6 8
+
EVTEMP
RGATE + 18 - 6
9
20 22
EVTHRES
+ 19 - 8
CIN
S1A
12 13 8
S2A
14
15
13
50 RDRAIN
16 21
DBREAK 11
MWEAK
DBODY
MMED MSTRO
8
EBREAK +
17 18 -
7
RSOURCE
LSOURCE SOURCE 3
RLSOURCE
RBREAK
17
18
S1B
S2B
CA
13
CB
+
+ 14
EGS
6 8
EDS
5 8
-
-
RVTEMP
19
IT
-
VBAT
+
8 22
RVTHRES
Figure 23.
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SPICE ELECTRICAL MODEL
REV 23 July 2002 FDD10AN06A0T
CTHERM1 TH 6 3.2e-3 CTHERM2 6 5 3.3e-3 CTHERM3 5 4 3.4e-3 CTHERM4 4 3 3.5e-3 CTHERM5 3 2 6.4e-3 CTHERM6 2 TL 1.9e-2
RTHERM1 TH 6 5.5e-4 RTHERM2 6 5 5.0e-3 RTHERM3 5 4 4.5e-2 RTHERM4 4 3 1.5e-1 RTHERM5 3 2 3.37e-1 RTHERM6 2 TL 3.5e-1
SABER ELECTRICAL MODEL
SABER thermal model FDD10AN06A0T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =3.2e-3 ctherm.ctherm2 6 5 =3.3e-3 ctherm.ctherm3 5 4 =3.4e-3 ctherm.ctherm4 4 3 =3.5e-3 ctherm.ctherm5 3 2 =6.4e-3 ctherm.ctherm6 2 tl =1.9e-2
rtherm.rtherm1 th 6 =5.5e-4 rtherm.rtherm2 6 5 =5.0e-3 rtherm.rtherm3 5 4 =4.5e-2 rtherm.rtherm4 4 3 =1.5e-1 rtherm.rtherm5 3 2 =3.37e-1 rtherm.rtherm6 2 tl =3.5e-1 }
FDD10AN06A0
th
JUNCTION
RTHERM1 6
RTHERM2 5
RTHERM3 4
RTHERM4 3
RTHERM5 2
RTHERM6
CTHERM1 CTHERM2 CTHERM3 CTHERM4 CTHERM5 CTHERM6
tl
CASE
Figure 24.
ORDERING INFORMATION
Device
Device Marking
Package
Reel Size
Tape Width
Shipping
FDD10AN06A0 FDD10AN06A0
DPAK3 (TO-252 3 LD) (Pb-Free, Halide Free)
330 mm
16 mm
2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK3 6.10x6.54x2.29, 4.57P CASE 369AS ISSUE B
DATE 20 DEC 2023
q q
GENERIC MARKING DIAGRAM*
XXXXXX XXXXXX AYWWZZ
DOCUMENT NUMBER: DESCRIPTION:
98AON13810G
*This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G" or microdot "G", may or may not be present. Some products may not follow the Generic Marking.
XXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week ZZ = Assembly Lot Code
Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red.
DPAK3 6.10x6.54x2.29, 4.57P
PAGE 1 OF 1
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