Intel Quartus Prime Pro Edition 用户指南：设计优化

user guide for Intel models including: Intel, Quartus Prime, Pro Edition, 设计优化, FPGA, 性能提升, 器件考量, 初始编译, I/O 约束, 时序约束, 权衡, 减少面积, 关键路径延迟, 降低功耗, 减少运行时间, Design Visualization Tool, RTL Viewer, Technology Map Viewer, Design Partition Planner, Chip Planner, Advisors, Timing Optimization Advisor, Power Optimization Advisor, Compilation Time Advisor, Design Management, Design Space Explorer II, DSE II, 网表优化, 物理综合, 区域优化, 资源使用, 布线, 时序收敛, 关键路径, 关键链, 设计分析, 亚稳定性, 外设到内核寄存器布局, 工程变更命令, ECO

Intel Quartus Prime Pro Edition用户指南: 设计优化

所作的更新针对于 Intel Quartus Prime设计套件: 19.3. 介绍可用于实现 Intel FPGA中最高设计性能的 Intel Quartus Prime Pro Edition设置，工具和技术。可使用的技术包括优化设计网表，解决限制重定时和时序收敛的关键链以及优化器件资源使用，器件平面布局规划以及实现工程变更命令（ECO）。

chip planner, 物理综合, eco（生态）, 工程变更命令, technology map viewer（查看FPGA中的实际连线情况）, 状态机查看器, 网表查看器, design space explorer（设计空间管理器）, 设计优化, 设计向导

. Intel Corporation

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Intel® Quartus® Prime Pro Edition

Intel® Quartus® Prime 19.3

UG-20133 | 2019.09.30 PDF | HTML

1. ...................................................................................................................... 6 1.1. ................................................................................................................6 1.1.1. .............................................................................................. 6 1.2. .................................................................................................. 6 1.2.1. I/O .............................................................................................. 7 1.2.2. .............................................................................................. 7 1.3. ............................................................................................................. 7 1.3.1. ....................................................................................................8 1.3.2. .........................................................................................8 1.3.3. ....................................................................................................8 1.3.4. .............................................................................................. 8 1.4. Intel Quartus Prime .................................................................. 9 1.4.1. Design Visualization Tool.................................................... 9 1.4.2. Advisors........................................................................................ 9 1.4.3. .................................................................................................. 10 1.5. Design Space Explorer II...................................................................................... 10 1.5.1. DSE II ........................................................................................ 11 1.5.2. DSE II Utility ....................................................................12 1.6. ............................................................................................. 13
2. .................................................................................................................... 14 2.1. Netlist Viewer....................................................................... 14 2.2. Netlist Viewers Intel Quartus Prime ................................................... 15 2.3. RTL Viewer ................................................................................................... 16 2.3.1. RTL Viewer ..........................................................................16 2.3.2. RTL Viewer....................................................................................... 16 2.4. Technology Map Viewer .................................................................................. 17 2.5. Netlist Viewer .......................................................................................... 17 2.5.1. Netlist Navigator ................................................................................20 2.5.2. Properties ......................................................................................... 20 2.5.3. Netlist Viewer .............................................................................. 22 2.6. ........................................................................................................... 22 2.6.1. ............................................................................ 22 2.6.2. ............................................................................................... 22 2.6.3. Schematic View ..................................................................... 27 2.6.4. Schematic View .................................................................27 2.6.5. ....................................................................................... 27 2.6.6. Schematic View ................................................................ 28 2.6.7. Schematic View ..................................................................... 29 2.6.8. Technology Map Viewer LUT .................................................... 30 2.6.9. .................................................................................................. 30 2.6.10. Bird's Eye View ................................................................................ 31 2.6.11. ............................................................................................. 31 2.6.12. ............................................................................. 31

Intel Quartus Prime Pro Edition : 2

2.6.13. Resource Property Viewer ......................................................32 2.7. Source Design File Intel Quartus Prime Windows................................. 33 2.8. Intel Quartus Prime Netlist Viewer................................................34 2.9. ........................................................................................................ 34 2.10. ............................................................................................35
3. ............................................................................................................ 37
3.1. ........................................................................................................ 37 3.1.1. ....................................................................................... 37 3.1.2. ............................................................................................ 38
3.2. ........................................................................................................ 38 3.2.1. WYSIWYG Primitive ResynthesisWYSIWYG ...............................38
3.3. .............................................................................................................. 39 3.3.1. ............................................................................................ 40 3.3.2. ............................................................................................ 40
3.4. ..................................................................................... 40
4. .......................................................................................................................... 42
4.1. ........................................................................................................ 42 4.1.1. Flow Summary .................................................................................. 42 4.1.2. Fitter ............................................................................................... 43 4.1.3. Analysis Synthesis .......................................................................... 43 4.1.4. .................................................................................................. 43
4.2. ......................................................................................................43 4.2.1. ....................................................................................... 44 4.2.2. I/O ............................................................................... 44 4.2.3. .................................................................................... 44 4.2.4. ....................................................................................................... 48
4.3. .............................................................................................................. 49 4.3.1. ............................................................................................ 50 4.3.2. ....................................................................................... 50
4.4. ................................................................................................... 51
5. .................................................................................................................. 52
5.1. Multi Corner ............................................................................................52 5.2. .............................................................................................................. 52
5.2.1. ............................................................................................ 53 5.3. .................................................................................................................53
5.3.1. ............................................................................................... 53 5.4. ................................................................................................ 54
5.4.1. ............................................................................................ 54 5.4.2. ................................................................................. 63 5.4.3. ..........................................................................................65 5.5. .............................................................................................................. 66 5.5.1. ....................................................................................... 66 5.5.2. I/O .................................................................................................. 66 5.5.3. Register-to-Register ......................................................................67 5.6. .............................................................................................................. 71 5.6.1. ......................................................................... 71

Intel Quartus Prime Pro Edition : 3

5.6.2. ............................................................................................ 71 5.6.3. Fitter ......................................................................................... 72 5.6.4. I/O ....................................................................................... 74 5.6.5. Register-to-Register ................................................................ 77 5.6.6. .................................................................................................. 85 5.6.7. ...............................................................................85 5.6.8. Intel Stratix 10 ...................................................................... 86 5.7. P2C..................................................................... 88 5.7.1. Advanced Fitter Setting .....................................89 5.7.2. Assignment Editor .................................................... 89 5.7.3. Fitter Report ............................................................ 90 5.8. .............................................................................................................. 91 5.8.1. ............................................................................................ 91 5.8.2. I/O ....................................................................................... 92 5.8.3. Register-to-Register ................................................................ 92 5.9. ...........................................................................................93
6. ................................................................................................. 96
6.1. Chip Planner ........................................................................... 96 6.1.1. Chip Planner..................................................................................... 97 6.1.2. Chip Planner GUI ............................................................................... 97 6.1.3. Chip Planner .................................................................... 98 6.1.4. Chip Planner ........................................................................ 105 6.1.5. Chip Planner ........................................................................ 108 6.1.6. Chip Planner Tile....................................................... 108
6.2. Design Partition Planner Chip Planner Logic Lock .................... 109 6.2.1. .......................................................................... 110
6.3. Chip Planner Logic Lock .................................................................... 111 6.3.1. Chip Planner Logic Lock .......................................... 111 6.3.3. Logic Lock ......................................................................................112 6.3.4. Logic Lock ..............................................................................112 6.3.5. Intel Quartus Prime Standard Edition Intel Quartus Prime Pro Edition ..............................................................................................113 6.3.6. Logic Lock .................................................................................113 6.3.7. Logic Lock ........................................................................ 115 6.3.8. Logic Lock ...................................................................117 6.3.9. ............................................................................................. 121 6.3.10. Intel Quartus Prime Logic Lock ............................................. 121 6.3.11. Logic Lock ...............................................................................121 6.3.12. Snapping to a Region........................................................... 122
6.4. Chip Planner ................................................................... 123 6.4.1. Chip Planner Clock Assignment.................................................... 123 6.4.2. Clock Assignment.............................................................................124 6.4.3. Clock Assignment.............................................................................124 6.4.4. Clock Region Assignment.................................................................. 125 6.4.5. .......................................................................... 125 6.4.6. Clock Assignment .............................................................................125
6.5. ............................................................................................................ 126

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6.5.1. Tcl Logic Lock .................................................................126 6.5.2. Tcl ...........................................................................127 6.5.3. Logic Lock ...........................................................................127 6.6. .............................................................................. 128
7. ............................................................................................................. 131 7.1. ................................................................................................. 131 7.2. ECO Tcl ................................................................................................. 132 7.3. ECO ........................................................................................................... 132 7.3.1. make_connection................................................................................... 133 7.3.2. remove_connection................................................................................ 133 7.3.3. modify_lutmask..................................................................................... 134 7.3.4. adjust_pll_refclk.................................................................................... 134 7.3.5. modify_io_slew_rate...............................................................................135 7.3.6. modify_io_current_strength.....................................................................135 7.3.7. modify_io_delay_chain........................................................................... 135 7.4. ECO ............................................................................................... 136 7.5. ECO ......................................................................................................136 7.6. ...................................................................................... 137
8. Intel Quartus Prime Pro Edition ..................................................... 138
A. Intel Quartus Prime Pro Edition ..................................................................... 139

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1.
Intel® Quartus® Prime
FPGA Intel Quartus Prime
·
Intel Quartus Prime Pro Edition · Intel Quartus Prime -
1.1.
Intel FPGA FPGA
FPGA
Intel FPGA (PDF)
1.1.1.

Intel Quartus Prime Device Migration Devices

Intel Quartus Prime Help
1.2.
Intel Quartus Prime Intel Quartus Prime

Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.

ISO 9001:2015 Registered

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1.2.1. I/O
FPGA I/O I/O
· I/O Intel Quartus Prime I/O Fitter
· PCB Compiler
I/O
In Intel Quartus Prime Pro Edition User Guide: Design Constraints
1.2.2.
Compiler
·
· Intel Quartus Prime
Intel Quartus Prime Timing Analyzer Compilation Report
· ( 52 ) · Intel Quartus Prime Timing Analyzer
In Intel Quartus Prime Pro Edition User Guide: Timing Analyzer · Intel Quartus Prime Timing Analyzer · Fitter
Intel Quartus Prime Help

1.3.

Trade-off

tile

Fitter HDL

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1.3.1.
Intel Quartus Prime Fitter
· ( 42 ) · ( 37 )
1.3.2.
Intel Quartus Prime
Intel Quartus Prime Fitter
Fitter
Intel Quartus Prime Fitter Fitter
Intel Quartus Prime Fitter Timing Optimization Advisor
FPGA Fitter Intel Quartus Prime HDL
( 52 )
1.3.3.
Intel Quartus Prime Synthesis and the Fitter

In Intel Quartus Prime Pro Edition User Guide: Power Analysis and Optimization
1.3.4.
Fitter Intel Quartus Prime
Intel Quartus Prime 15%

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Intel Quartus Prime Pro Edition

1.4. Intel Quartus Prime
Intel Quartus Prime

1.4.1. Design Visualization Tool
Intel Quartus Prime

Visualization Tool

RTL Viewer

technology map viewer FPGA

Design Partition Planner

Design Partition Planner Chip Planner

Chip Planner

· Chip Planner ( 96 ) · Design Partition Planner Chip Planner Logic Lock ( 109 ) · ( 14 ) · RTL Viewer ( 16 )

1.4.2. Advisors
Intel Quartus Prime

· Timing Optimization Advisor · Power Optimization Advisor · Compilation Time Advisor
·
Intel Quartus Prime Pro Edition · Intel Quartus Prime
Intel Quartus Prime Help

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· ( 71 ) · Power Optimization Advisor
In Intel Quartus Prime Pro Edition User Guide: Power Analysis and Optimization
1.4.3.
Design Space Explorer II DSE II PC compute farm
Design Space Explorer II ( 10 )

1.5. Design Space Explorer II

Design Space Explorer II Tools > Launch Design Space Explorer II Design Space Explorer IIDSE II DSE II

DSE II seed seed

Design Space Explorer II

DSE II Intel FPGA DSE II

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· Design Space Explorer II Intel Quartus Prime Help
· Design Space Explorer 21

1.5.1. DSE II
DSE II exploration point Analysis & SynthesisFitter exploration point design exploration fitterseed
DSE II DSE II DSE II
· Fitter Seed ( 84 ) · Design Space Explorer II
In Intel Quartus Prime Pro Edition User Guide: Power Analysis and Optimization

1.5.1.1.
DSE II DSE II GUI Setup Status
DSE II LSF, SSH Torque SSH

DSE II
SSH ssh quartus_dse

Windows Cygwin sshd PuTTY

· Design Space Explorer II Intel Quartus Prime Help
· Design Space Explorer II Intel Quartus Prime Help

1.5.1.2.

DSE II seed seed

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DSE GUI Exploration
Design Space Explorer II
Intel Quartus Prime Help

1.5.1.3.
DSE II Intel Quartus Prime Report
DSE II slack Intel Quartus Prime

DSE II Exploration Results

DSE II
DSE II projectname.dse.rpt DSE II Intel Quartus Prime Archive Files .qar
Design Space Explorer II
Intel Quartus Prime Help

1.5.2. DSE II Utility

DSE II
GUI Intel Quartus Prime Help
DSE II 1. DSE II
Intel Quartus Prime DSE II Intel Quartus Prime Yes 2. Project 3. Setup 4. Exploration 5. Start

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· Design Space Explorer II Intel Quartus Prime Help
· Design Space Explorer 21

1.6.

Intel Quartus Prime

2018.05.07

18.0.0

2017.11.06 2016.10.31 2016.05.03 2015.11.02 2014.12.15

17.1.0 16.1.0 16.0.0 15.1.0 14.1.0

2014 6 2013 11 2013 5
2012 6 2011 11 2010 12 2010 8 2010 7

14.0.0 13.1.0 13.0.0
12.0.0 10.0.3 10.0.2 10.0.1 10.0.0

· · DSE II · Design Partition Planner · Intel Quartus II Quartus Prime · Fitter SettingAnalysis & Synthesis Physical Synthesis
Optimizations Setting Compiler Setting · DSE II Intel Quartus Prime Area Optimization III

Intel Quartus Prime

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Intel Quartus Prime Netlist Viewer
FPGA Intel Quartus Prime RTL Viewer Technology Map Viewer
· Netlist Viewers Intel Quartus Prime ( 15 ) · RTL Viewer ( 16 ) · Technology Map Viewer ( 17 ) · ( 27 ) · ( 34 )

2.1. Netlist Viewer
Netlist Viewer RTL Viewer Technology Map Viewer
RTL Viewer RTL Viewer
RTL Viewer RTL Viewer
Technology Map Viewer Analysis Synthesis Fitter Technology Map ViewerPost-Mapping"" post-mapping Technology Map Viewer Analysis Synthesis Netlist Viewer ""post-mapping
RTL Viewer Technology Map Viewer
Technology Map Viewer I/O
FPGA

ISO 9001:2015 Registered

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· Netlist Viewers Intel Quartus Prime ( 15 ) · RTL Viewer ( 16 ) · Technology Map Viewer ( 17 )

2.2. Netlist Viewers Intel Quartus Prime

Netlist Viewer Netlist Viewer

Settings > Compilation Process Settings Run Netlist Viewers preprocessing during compilation Netlist Viewer

Intel Quartus Prime RTL Viewer Technology Map Viewer

Netlist Viewer Intel Quartus Prime

HDL or Schematic Design Files

VQM or EDIF Netlist Files

Analysis and Elaboration
Synthesis (Logic Synthesis and Technology Mapping)
Fitter (Place and Route)
Timing Analyzer

RTL Viewer
Technology Map Viewer and Technology Map Viewer (Post-Mapping)
Technology Map Viewer
Technology Map Viewer

RTL Viewer Preprocessor (Once per Analysis and Elaboration)
Technology Map Viewer Preprocessor (Once per Synthesis)
Technology Map Viewer Preprocessor (Once per Fitting)
Technology Map Viewer Preprocessor (Once per Timing Analysis)

Netlist Viewer
· RTL Viewer Analysis Elaboration
· Technology Map Viewer (Post-Fitting) Technology Map Viewer (Post-Mapping) Analysis Synthesis
Netlist Viewer
· Analysis Elaboration
· Netlist Viewer Netlist Viewer Intel Quartus Prime

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Netlist Viewer Netlist Viewer Netlist Viewer

2.3. RTL Viewer
RTL Viewer Intel Quartus Prime Intel Quartus Prime Pro Edition synthesis RTL
Analysis Elaboration Intel Quartus Prime Verilog HDL Design Files (.v)SystemVerilog Design Files (.sv)VHDL Design Files (.vhd)AHDL Text Design Files (.tdf) Block Design Files (.bdf)
Verilog Quartus Mapping File (.vqm) Electronic Design Interchange Format (.edf) I/O
RTL Viewer Analysis Elaboration Intel Quartus Prime · the Intel Quartus Prime Pro Edition synthesis
Intel Quartus Prime ·
Intel Quartus Prime RTL Viewer RTL RTL Processing > Start > Start Analysis & Elaboration Intel Quartus Prime Analysis Elaboration
Tools > Netlist Viewers > RTL Viewer RTL Viewer
Netlist Viewer ( 17 )
2.3.1. RTL Viewer
RTL Viewer · · VCC GND · · · · NOT gate · 2-input AND gate 2-input
AND gate 3-input AND gate
2.3.2. RTL Viewer
Intel Quartus Prime RTL Viewer

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1. Processing > Start > Start Analysis & Elaboration RTL Intel Quartus Prime Analysis Elaboration
2. Tools > Netlist Viewers > RTL Viewer RTL Viewer
2.4. Technology Map Viewer
Intel Quartus Prime Technology Map Viewer Analysis Synthesis Fitter FPGA
Technology Map Viewer I/O LCELLLUT I/O
Intel Quartus Prime GND VCC IN1 or OUT1
Intel Quartus Prime Intel Quartus Prime Technology Map Viewer Processing Start Start Analysis & Synthesis Technology Map Viewer "" Technology Map Viewer (Post-Mapping)
Fitter Technology Map Viewer Fitter Technology Map Viewer (Post-Mapping)""post-mapping Timing Analysis Technology Map Viewer Timing Analyzer
Technology Map Viewer Tools > Netlist Viewers > Technology Map Viewer (Post-Fitting) Technology Map Viewer (Post Mapping)
· ( 34 ) · Schematic View ( 28 ) · Netlist Viewer ( 17 )
2.5. Netlist Viewer
Netlist Viewer
RTL Viewer Technology Map Viewer · Netlist Navigator -- · Find -- · Properties -- Properties · --

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RTL Viewer

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Netlist Viewer
· Back Forward Netlist Viewer 10
· Refresh Refresh
· Find Find
· Selection Tool Zoom Tool
· Fit in Page
· Hand Tool
· Area Selection Tool
· Netlist Navigator Netlist Navigator
· Color Settings Colors Netlist Viewer

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· Display Settings Display -- Show full name Show only <n> characters Node name Port namePin name Bus name -- Show timing info -- Show node type -- Show constant value -- Show flat nets
Display

· Bird's Eye View Bird's Eye View
· Show/Hide Instance Pins Netlist Viewer Timing Analyzer cross-probing Netlist Viewer
· Netlist Viewer Show Netlist on One Page
RTL Viewer Technology Map Viewer (Post-Fitting) Technology Map Viewer (Post-Mapping) RTL Viewer

· RTL Viewer ( 16 )
· Technology Map Viewer ( 17 )

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· Netlist Navigator ( 20 ) · Netlist Viewer ( 22 ) · Properties ( 20 )

2.5.1. Netlist Navigator

Netlist Navigator
Netlist Navigator Netlist Navigator

Netlist Navigator

Netlist Navigator "+"

Netlist Navigator

Instances Primitives

· Intel Quartus Prime Pro Edition RTL Viewer · VQM EDIF Technology Map Viewer RTL Viewer
Technology Map Viewer

Ports

I/O · I/O I/O ·

2.5.2. Properties
Properties

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Properties
RTL Viewer Technology Map Viewer Properties.

Properties · Fan-in Input port Fan-in Node · Fan-out Output port Fan-out Node · Parameters Parameter Name Values · Ports Port Name ConstantVCC GND

VCC GND -Unconnected

VCC VCC GND GND VCC GND

Properties

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2.5.3. Netlist Viewer
Find · Find Browse Select Hierarchy Level
· Include subentities · Options Find Options InstancesNodesPorts

List Find

2.6.
RTL Viewer Technology Map Viewer RTL Viewer Technology Map Viewer
RTL Viewer Technology Map Viewer

2.6.1.
RTL Viewer Technology Map Viewer
Netlist Navigator
New Tab Netlist Navigator
· New Tab · Duplicate Tab · Cascade Tabs · Tile Tabs · Close Tab · Close Other Tabs

2.6.2.

Intel

RTL Viewer Technology Map Viewer LCELL

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5.
I/O

RTL Viewer Technology Map Viewer

CLK_SEL[1:0]

RESET_N

I/O

MEM_OE_N [1,15]

[1,3]

OR, AND, XOR

always1

ORAND XOR

always0

MULTIPLEXER

Mux5

SEL[2:0] DATA[7:0]

OUT

BUFFER

DATAIN

OUT0

0 1
LCELLSOFT GLOBALNOT EXP
...

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LATCH

latch PRE DQ ENA CLR

F DATAA DATABCOMBOUT LOGIC_CELL_DACOTAMCB (7F7F7F7F7F7F7F7F)

CPU_D[10]

PADIN

PADIO

BIDIRPADOUT

speed_ch:speed

accel_in clk
reset

get_ticket

streaming_cont IN0 OUT0 IN1 OUT1 IN2 OUT2 IN3 OUT3 IN4 OUT4 IN5 OUT5 IN6 IN7 IN8

RAM

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/DFFDFF · DFFEA ALOAD
ADATA · DFFEAS
ASDATA

Stratix M-RAM
...

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my_20k_sdp

CLK0 CLK1 CLR0 PORTAADDRSTALL PORTAADDR[8:0] PORTABYTEENMASK[3:0] PORTADATAIN[35:0] PORTAWE PORTBADDRSTALL PORTBADDR[8:0] PORTBRE

PORTBDATAOUT[35:0]

RAM

8'h80

RTL Viewer Schematic View
RTL Viewer

A[3:0] Add0 OUT[3:0]
B[3:0]

OUT = A + B

A[0] Mult0 OUT[0]
B[0]

OUT = A ¥ B

A[0] Div0 OUT[0]
B[0]

OUT = A / B

...

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A[1:0] Equal3 OUT
B[1:0]

A[0] ShiftLeft0 OUT[0]
COUNT[0]

A[0] ShiftRight0 OUT[0]
COUNT[0]

A[0] Mod0 OUT[0]
B[0]

A[0] LessThan0 OUT
B[0]

Mux5

SEL[2:0] DATA[7:0]

OUT

Selector1

SEL[2:0] DATA[2:0]

OUT

Decoder0

IN[5:0]

OUT[63:0]

OUT = (A << COUNT)
OUT = (A >> COUNT)
OUT = (A%B)
OUT = (A<:B:A>B)
OUT = DATA [SEL] 2sel range size

OUT = (binary_number (IN) == x) for x = 0 x=2 n+1 -1

· ( 31 )

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· ( 31 )
2.6.3. Schematic View
Netlist Viewer Selection Tool Shift
Netlist Navigator Schematic View Schematic View
Netlist Navigator ( 20 )
2.6.4. Schematic View
Netlist Viewer
· Expand to Upper Hierarchy · Copy ToolTip · Hide Selection
· Filtering
2.6.5.
· Sources-- · Destinations-- · Sources & Destinations-- · Selected Nodes--

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· Between Selected Nodes-- · Bus Index-- · Filtering Options-- Filtering Options
-- Stop filtering at register-- Netlist Viewer
-- Filter across hierarchies-- Netlist Viewer -- Maximum number of hierarchy levels--
Filter Netlist Viewer

2.6.6. Schematic View

RTL Viewer Technology Map Viewer

LUT RTL Viewer Technology Map Viewer RAM DSP Technology Map Viewer

Wrapping Unwrapping
unwrap

: 7.

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Connectivity Details

Connectivity Details
2.6.7. Schematic View

Shift

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10.

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Refresh
2.6.8. Technology Map Viewer LUT
LUT Properties LUT
Properties LUT · Schematic -- LUT · Truth Table --
Properties ( 20 )
2.6.9.
Zoom Tool View
Netlist Viewer Zoom In Zoom Out Zoom 100%
Netlist Viewer Zoom Tool Zoom Tool Zoom Tool

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· zoom in-- · Zoom -0.5-- 0.5 · zoom 0.5-- 0.5 · zoom fit--
( 27 )

2.6.10. Bird's Eye View
Bird's Eye View View Bird's Eye View Bird's Eye View
Intel Quartus Prime RTL Viewer Technology Map Viewer
Bird's Eye View · · ·

2.6.11.
RTL Viewer Technology Map Viewer
Page<> of <>
Netlist Viewer ( 17 )

2.6.12.

Netlist Viewer Intel

( 22 )

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2.6.13. Resource Property Viewer
19.1 Resource Property Viewer itermoterm
19.1 Connectivity

The oterm-iterm dependency path is highlighted

· Chip Planner Resource Property Viewer
· Go To Destination Node Go To Source Node Node Selection Chip Planner
· Chip Planner Node Properties
Resource Property Viewer

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2.7. Source Design File Intel Quartus Prime Windows
Intel Quartus Prime RTL Viewer Technology Map Viewer
Netlist Viewer Intel Quartus Prime
Netlist Viewer Locate · Locate in Assignment Editor
· Locate in Pin Planner
· Locate in Chip Planner
· Locate in Resource Property Editor
· Locate in Technology Map Viewer
· Locate in RTL Viewer
· Locate in Design File
Locate in Assignment Editor
Netlist Viewer Window Netlist Viewer

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2.8. Intel Quartus Prime Netlist Viewer

Intel Quartus Prime RTL Viewer Technology Map Viewer 1 Netlist Viewer
RTL Viewer Technology Map Viewer Intel Quartus Prime RTL Viewer Technology Map Viewer
· Project Navigator
· Timing Closure Floorplan
· Chip Planner
· Resource Property Editor
· Node Finder
· Assignment Editor
· Messages Window
· Compilation Report
· Timing Analyzer Technology Map Viewer
Intel Quartus Prime Netlist Viewer Project Navigator Hierarchy Entity Timing Closure Floorplan Assignment Editor From To Locate Locate in RTL Viewer Locate in Technology Map ViewerNetlist Viewer Netlist Viewer

Netlist Viewer

Netlist Viewer Filter > Selected Nodes Filter across hierarchy Netlist Viewer Can't find requested location

2.9.
Intel Quartus Prime Pro Edition User Guide: Timing Analyzer
Timing Analyzer Technology Map Viewer slack Page Title
1. Contents Compilation Report Table Timing Analyzer GUI > Report Timing timing corner
2. Timing Analyzer Report Report Timing timing corner
3. Summary of Paths Locate Path > Locate in Technology Map ViewerTechnology Map Viewer

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In Intel Quartus Prime Pro Edition User Guide: Timing Analyzer

2.10.

Intel Quartus Prime

2019.07.01

19.1

2018.09.24

18.1.0

2016.10.31 2016.05.03 2015.11.02

16.1.0 16.0.0 15.1.0

2014.06.30 2013 11
2012 11 2012 6 2011 11 2010 12 2010 7 2009 11 2009 3
2008 11 2008 5

14.0.0 13.1.0
12.1.0 12.0.0 10.0.2 10.0.1 10.0.0 9.1.0 9.0.0
8.1.0 8.0.0

Resource Property Viewer iterm-oterm

· · "" CARRY

· Intel

Schematic Viewer

Schematic Viewer · "" · Connection Details · Display Settings · Hand Tool · Area Selection Tool · New default behavior for Show/Hide Instance Pins
/

One Page Show/Hide Instance Pins Show Netlist

HardCopy Netlist viewer

Global Net Routing

· · Intel Quartus Prime 10.0

· ·

· 13 8.1.0 12 · 13-2 13-3 13-4 13-14 13-30 · "" 1315 · 13-44 ""

8.5" × 11"

· Arria GX · ·

...

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Intel Quartus Prime

· · Signal Tap Analyzer · · .png .gif · · "Enabling and Disabling the Radial Menu"
Radial Menu, "Changing the Time Interval" "Changing the Constant Signal Value Formatting" "Logic Clouds in the RTL Viewer"RTL Viewer "Logic Clouds in the Technology Map Viewer"Technology Map Viewer "Manually Group and Ungroup Logic Clouds" "Customizing the Shortcut Commands" · · "Customizing the Radial Menu" Radial Menu · "Grouping Combinational Logic into Logic Clouds" · Intel Quartus Prime 8.0

Intel Quartus Prime

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Intel Quartus Prime back-annotation
Compiler Settings

Enable synthesis netlist optimization settings
Enable physical synthesis options

Advanced Synthesis Settings Synthesis Effort Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis)
Advanced Synthesis Settings Advanced Physical Synthesis Assignments > Settings > Compiler Settings > Advanced Settings (Fitter)

Signal Tap Logic Analyzer
Logic Lock legacy

3.1.
Intel Quartus Prime Fitter Fitter
Intel Quartus Prime
Compiler Settings Page (Settings Dialog Box)
Intel Quartus Prime Help
3.1.1.

ISO 9001:2015 Registered

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1. Assignments > Settings > Compiler Settings
2. Advanced Settings (Fitter) Physical Synthesis
3. Netlist Optimizations

3.1.2.

Intel Quartus Prime Assignments > Settings > Compiler Settings > Advanced Settings (Fitter)

Netlist Optimizations Never Allow

Advanced Physical Synthesis

Netlist Optimizations Assignment Editor Netlist Optimizations

Allow Register Duplication

Compiler Compiler Analysis & Synthesis Fitter

Allow Register Duplication

Compiler Compiler Compiler
Compiler
Analysis & Synthesis Fitter

3.2.

Signal Tap Logic Analyzer
Intel Quartus Prime Design Space Explorer II (DSE)
Design Space Explorer II ( 10 )
3.2.1. WYSIWYG Primitive ResynthesisWYSIWYG
Perform WYSIWYG primitive resynthesis

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: 11.

Perform WYSIWYG primitive resynthesis Intel Quartus Prime LE Intel Intel .edf .vqm Perform WYSIWYG primitive resynthesis Intel Quartus Prime SpeedArea Balanced Optimization Technique
Perform WYSIWYG primitive resynthesis LCELL LE I/O DDRI/O DSP.vqm .edf IP
Perform WYSIWYG primitive resynthesis .vqm .edf Intel Quartus Prime
Netlist Optimizations Never Allow WYSIWYG Assignment Editor Netlist Optimizations WYSIWYG
HDL Intel Quartus Prime
Intel Quartus Prime Preserve Register (preserve) Keep Combinational Logic (keep)
Intel Quartus Prime WYSIWYG Primitive Resynthesis

3.3.
Tcl Intel Quartus Prime Command-Line Tcl API Help Help
quartus_sh --qhelp
/

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Tcl set_global_assignment -name <QSF variable name> <value>

Tcl set_instance_assignment -name <QSF variable name> <value> \ -to <instance name>

· Command Line Scripting
· Tcl Scripting
· API Functions for Tcl Intel Quartus Prime Help
· Intel Quartus Prime Pro Edition Intel Quartus Prime

3.3.1.

.qsf GUI .qsf.qsf Type

Intel Quartus Prime

Perform WYSIWYG ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Primitive Resynthesis

OPTIMIZATION_MODE

Power-Up Don't Care

ALLOW_POWER_UP_DONT_CARE

ON, OFF
BALANCED HIGH PERFORMANCE EFFOR AGGRESSIVE PERFORMANCE
ON, OFF

Global, Instance Global, Instance
Global

3.3.2.

.qsf GUI .qsf.qsf Type

10.

Intel Quartus Prime

Advanced Physical Synthesis

ADVANCED_PHYSICAL_SYNTHESIS

ON, OFF

Global

3.4.

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2019.04.24 2019.04.18 2018.09.24 2018.05.07 2017.11.06 2016.10.31 2016.05.02 2015.11.02 2014.12.15
2014 6 2013 11 2012 6 2011 11 2010 12 2010 7
2009 11
2009 3
2008 11 2008 5

Intel Quartus Prime 18.1.0 18.1.0 18.1.0 18.0.0 17.1.0 16.1.0 16.0.0 15.1.0 14.1.0
14.0.0 13.1.0 12.0.0 10.0.2 10.0.1 10.0.0
9.1.0
9.0.0
8.1.0 8.0.0

""
""
" IOC " CASCADE
· .vqm ·
· Intel ·
·
· Quartus II Intel Quartus Prime ·
· Fitter SettingAnalysis & Synthesis Settings Physical Synthesis Optimizations Setting Compiler Setting
· DSE II

HardCopy

· Intel Quartus Prime Help · "" ·
· "--" · "" ·
· 8.1.0 11 · " --"" Fitting " · "" · "" ·
"8½ × 11"
· 11-9 "" · 11-16 " Fitting "

Intel Quartus Prime

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Intel

4.1.

Compilation Report
( 101 )

4.1.1. Flow Summary

Flow Summary DSPPLL

12.

Flow Summary

Fitter
Fitter ALM

ISO 9001:2015 Registered

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4.1.2. Fitter
Fitter Resource Section
Fitter Resource Usage Summary PLL DSP
Fitter Resources Reports
4.1.3. Analysis Synthesis
Intel Quartus Prime
Analysis & Synthesis Optimization Results
Synthesis Optimization Results Reports
4.1.4.
100% Compiler Messages Processing
Fitter
Intel Quartus Prime Compiler Compilation Report
Chip Planner
Viewing Messages
4.2.
1. -- 2. I/O -- I/O 3. Register-to-register
· ( 6 )

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· ( 52 )
4.2.1.
· I/O I/O PLL LVDS · LUT
DSP ·
4.2.2. I/O
I/O
4.2.2.1.
Intel Quartus Prime

I/O I/O
Managing Device I/O Pins
In Intel Quartus Prime Pro Edition User Guide: Design Constraints
4.2.3.
LUT DSP
4.2.3.1.

LE ALM DSP DSP DSP
Intel Quartus Prime Compilation Report Analysis & Synthesis State Machine
· AN 584 FPGA

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· Recommended HDL Coding Styles In Intel Quartus Prime Pro Edition User Guide: Design Recommendations

4.2.3.2.
Fitter

· Intel Quartus Prime Assignments > Settings > Compiler
Settings > Advanced Settings (Synthesis) Optimization Technique Balanced Area
· Area Speed Optimization Technique Balanced Assignment Editor
· Speed Optimization Technique for Clock Domains
· fMAX
register-to-register

Intel Quartus Prime Balanced Area Area

Intel Quartus Prime

4.2.3.3.
FPGA Intel
·
Restructure Multiplexers
· HDL

4.2.3.4. Balanced Area WYSIWYG
Perform WYSIWYG Primitive Resynthesis WYSIWYG Optimization Technique Perform WYSIWYG Primitive Resynthesis WYSIWYG WYSIWYG

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Balanced Area Area WYSIWYG register-toregister

WYSIWYG

4.2.3.5.
Auto Packed Registers LUT LUT

Auto Packed Register

4.2.3.6. Fitter
Logic Lock
Logic Lock Chip Planner Routing Congestion Logic Lock Logic Lock Assignment Editor Chip Planner Chip PlannerLogic Lock Regions Window Assignments Logic Lock Remove Assignments Available assignment categories

( 96 )

4.2.3.7.
Intel Quartus Prime

4.2.3.8.
Fitter
Parameter Editor RAM
Compiler HDL ROM RAM Shift RAMIP RAM

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RAM Intel Quartus Prime ramstyle RAM logic
Entity Resource Utilization Intel Quartus Prime RAM bank RAM Compiler bank bank RAM

· Inferring Shift Registers in HDL Code
· Fitter Resource Utilization by Entity Report

4.2.3.9.

Assignments > Settings > Compiler Settings > Advanced Settings (Fitter) Intel Quartus Prime Intel

Fitter

4.2.3.10. DSP
DSP DSP DSP
DSP DSP Intel Quartus Prime DEDICATED_MULTIPLIER_CIRCUITRY IP
HDL DSP Intel Quartus Prime Auto DSP Block Replacement Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis) Auto DSP Block Replacement Assignment Editor
Intel Quartus Prime DSP Block Balancing DSP DSP Auto DSP DSP Intel Quartus Prime DSP DSP Auto Off IP DEDICATED_MULTIPLIER_CIRCUITRY

4.2.3.11.

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4.2.4.

4.2.4.1. Auto Packed Register Sparse Sparse Auto
Auto Packed Registers LE ALM Assignment > Settings > Compiler Settings > Advanced Settings (Fitter)

4.2.4.2. Fitter Aggressive Routability Optimizations Always
Fitter Aggressive Routability Optimization
Fitter Aggressive Routability Optimizations
6% 4%
Fitter

4.2.4.3. Router Effort Multiplier
Router Effort Multiplier 1.0 0
· 1 · 0 0.1 3.0 2% Router Effort Multiplier Router Effort Multiplier

4 Router Effort Multiplier 1 10% 10 4.6

4.2.4.4. Fitter
Logic Lock
Logic Lock Chip Planner Routing Congestion Logic Lock Logic Lock Assignment Editor Chip Planner Chip PlannerLogic Lock Regions Window Assignments Logic Lock Remove Assignments Available assignment categories

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( 96 )

4.2.4.5.

Intel Quartus Prime Balanced Area Area

Intel Quartus Prime

4.2.4.6.

4.2.4.7.

4.3.
Tcl Intel Quartus Prime Tcl API Help "Help" 1. Help
quartus_sh --qhelp
/

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2. Tcl
set_global_assignment -name <QSF variable name> <value> 3. Tcl
set_instance_assignment -name <QSF variable name> <value> \ -to <instance name>

<value>`Standard Fit'
· Intel Quartus Prime Pro
Intel Quartus Prime
· Tcl Scripting In Intel Quartus Prime Pro Edition
· Command Line Scripting In Intel Quartus Prime Pro Edition

4.3.1.

Tcl Intel Quartus Prime Settings File (.qsf) Type

11.

Placement Effort Multiplier

.qsf PLACEMENT_EFFORT_MULTIPLIER

Global

Router Effort Multiplier

ROUTER_EFFORT_MULTIPLIER

Global

Router Timing Optimization level ROUTER_TIMING_OPTIMIZATION_LEVEL NORMAL, MINIMUM, MAXIMUM

Global

Final Placement Optimization

FINAL_PLACEMENT_OPTIMIZATION

ALWAYS, AUTOMATICALLY, NEVER Global

4.3.2.

Resource Utilization Optimization QSF

12.

Auto Packed Registers

.qsf QII_AUTO_PACKED_REGISTERS

AUTO, OFF, NORMAL, MINIMIZE AREA, MINIMIZE AREA WITH CHAINS,SPARSE, SPARSE AUTO

Global, Instance

Perform WYSIWYG Primitive Resynthesis

ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON, OFF

Global, Instance

Optimization Technique

OPTIMIZATION_TECHNIQUE

AREA, SPEED, BALANCED

Global, Instance
...

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Speed Optimization Technique for Clock Domains
State Machine Encoding

.qsf SYNTH_CRITICAL_CLOCK
STATE_MACHINE_PROCESSING

Auto RAM Replacement

AUTO_RAM_RECOGNITION

Auto ROM Replacement

AUTO_ROM_RECOGNITION

Auto Shift Register Replacement

AUTO_SHIFT_REGISTER_RECOGNITION

Auto Block Replacement

AUTO_DSP_RECOGNITION

Number of Processors NUM_PARALLEL_PROCESSORS for Parallel Compilation

ON, OFF

Instance

AUTO, ONE-HOT, GRAY, JOHNSON, MINIMAL BITS, ONE-HOT, SEQUENTIAL, USER-ENCODE ON, OFF
ON, OFF
ON, OFF
ON, OFF
1 16 ALL

Global, Instance
Global, Instance Global, Instance Global, Instance Global, Instance Global

4.4.

Intel Quartus Prime

2018.1018

18.1.0

2018.09.24

18.1.0

2018.07.03 2017.05.08

18.00 17.0.0

2016.10.31 2016.05.02 2015.11.02 2014.12.15
2014 6

16.1.0 16.0.0 15.1.0 14.1.0
14.0.0

2013 5

13.0.0

· Help · Fitter
· · , · Intel
·
Quartus II Quartus Prime
Fitter SettingAnalysis & Synthesis Physical Synthesis Optimizations Setting Compiler Setting
· Cyclone III Stratix III · Macrocell CPLD ·

Intel Quartus Prime

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Intel
Intel Quartus Prime

5.1. Multi Corner
slow corner timing
Intel Quartus Prime timing corner --Slow 85°C cornerSlow 0°C corner Fast 0°C corner 2 timing corner --Fast 0°C Slow 85°C corner
Optimize multi-corner timing Fitter process corner 10%
Fitter slow-corner slow-corner

5.2.
I/O I/O
Timing Analyzer
Chip Planner
· ( 8 ) · Timing Analyzer Path Report ( 67 )

ISO 9001:2015 Registered

5. UG-20133 | 2019.09.30
5.2.1.
Chip Planner floorplan Timing Analyzer
5.3.
Intel Stratix® 10 Hyper-Aware HyperAware Fast Forward Hyper-Registers Intel Stratix 10
Intel Quartus Prime Pro Edition Hyper-Retimer HyperRetimer Hyper-Register
Hyper-Retimer Intel Stratix 10
Running the Hyper-Aware Design Flow
In Intel Stratix 10
5.3.1.
RTL Intel Quartus Prime Pro Edition 1
Hyper Aware Design Flow · Retiming Limit Details Report
Hyper Aware Design Flow · Fast Forward Compilation Report
Fast Forward Compilation Compilation Dashboard Compilations Fast Forward Timing Closure Recommendations · Technology Map Viewer Intel Stratix 10
· Locate Critical Chains
In Intel Stratix 10 · Intel Stratix 10 HyperFlex OS10CRCHNS

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5.4.
RTL RTL
5.4.1.
5.4.1.1.
Fitter

5.4.1.2. Fitter Fitter Fitter Netlist Optimizations
5.4.1.3. RTL RTL
5.4.1.4.
5.4.1.4.1. Compilation Report Fitter Resource

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13.

Regional Clock Global Clock Global Line Name
Non-Global High Fan-Out Signal
Reset enable

Chip Planner

5.4.1.4.2. Fitter Resource Usage Summary

14.

Fitter

Average interconnect usage Peak interconnect usage
50% 50-65% 65% RTL 90% 100%

Intel Quartus Prime Pro Edition : 55

15.

Report Routing Utilization

5. UG-20133 | 2019.09.30

5.4.1.4.3. ""
Fitter Fitter Estimated Delay Added for Hold Timing
Estimated Delay Added for Hold Timing Fitter

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16.

Hold Timing Report

17.

1x 2x
set_multicycle_path -from 1x -to 2x -setup -end 2
2x

set_multicycle_path -from 1x -to 2x -setup -end 2 set_multicycle_path -from 1x -to 2x -hold -end 1

Intel Quartus Prime Pro Edition : 57

18.

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Fitter

Global
Timing Analyzer
Optimize hold timing Fitter Assignments > Settings > Compiler Settings > Advanced Settings (Fitter) > Optimize hold timing Optimize hold timing

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19.

Optimize hold timing

5.4.1.5.

5.4.1.5.1.
Fitter Resource Section , Resource Usage Summary Difficulty Packing Design Difficulty Packing Design Fitter Logic Lock
Difficulty Packing Design

5.4.1.5.2.
Compilation Report Fitter

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5.4.1.5.3.
Synthesis Fitter

5.4.1.5.4.
Chip Planner Chip Planner
I/O I/O IP IP

20.

Floorplan with Color-Coded Entities
·
·
· I/O

· Fitter
· Fitter

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5.4.1.5.5.
Fitter

5.4.1.5.6.
Assignments > Settings > Compiler Settings > Advanced Settings (Fitter) > Placement Effort Multiplier Fitter Place
RTL 4

21.

Placement Effort Multiplier

5.4.1.5.7. Fitter
Fitter Optimization mode Compiler
Fitter Optimization mode Balanced (Normal flow) Fitter Optimization mode

Intel Quartus Prime Pro Edition : 61

22.

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Fitter Assignments > Settings > Compiler Settings > Advanced Settings (Fitter) > Fitter Effort Auto Fit Fitter Standard Fit (highest effort)
Fitter

5.4.1.5.8.
derive_pll_clocks Timing Analyzer SDC Task Diagnostic Report Ignored Constraints Report Unconstrained Paths
5.4.1.6.

· ·

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5.4.2.

5.4.2.1.

Timing Analyzer Report Timing Report panel name Show routing Report Timing

23.

Report Show Routing

Extra Fitter Information Extra Fitter Information Intel Stratix 10
Chip Planner
Chip Planner ( 105 )

5.4.2.2.
· CLK_CTRL_Gn-- Global · CLk_CTRL_Rn-- Regional

5.4.2.2.1.

5.4.2.2.2.

24.

Negative-Edge

Intel Quartus Prime Pro Edition : 63

25.

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set_multicycle_path -from <generating_register> -setup -end 2

5.4.2.2.3.
MAX_FANOUT

5.4.2.2.4.
Global Signal Global Signal OFF

26.

5.4.2.3.
5.4.2.4. Suspicious Setup
Suspicious setup
10Mhz/3 = 33.33 ns/ 99.999 ns 100.000 ns
· FIFO ·
Fitter false
5.4.2.5. Timing Analyzer Statistics
5.4.2.6. SynthesisCompiler RAM RAM "altshift_taps"

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· Auto Shift Register Replacement
· RAM / · RAM
AUTO OFF
5.4.2.7.
Chip Planner
I/Q I/O
-logic - global I/O I/O Logic Lock DSPIP
Timing Analyzer Extra Fitter Information Extra Fitter Information Intel Stratix 10
( 99 )
5.4.2.8.
Timing Analyzer Report Timing Closure Recommendation
5.4.3.
Compiler 5 seed
RTL Seed seed
RTL Logic Lock

5.4.3.1.

1. Design Partition Planner View > Show Timing Data

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Design Partition Planner 2.
-- Create Design Partition
3.
4. Empty Intel Quartus Prime Pro Edition
5. Fitter 6.
· ( 110 ) ·
Intel Quartus Prime Pro Edition ·
In Intel Quartus Prime Pro Edition
5.5.
Intel Quartus Prime
5.5.1.
Intel Quartus Prime
Reports > Report Ignored Constraints Timing Analyzer GUI
report_sdc -ignored -panel_name "Ignored Constraints"
Intel Quartus Prime
Fitter Ignored Assignment Report
I/O
5.5.2. I/O
Timing Analyzer Synopsys* Design Constraints (SDC) Timing Analyzer set_input_delay set_output_delay report_timing Tcl I/O

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I/O Timing Analyzer Report I/O I/O Intel Quartus Prime Actual
I/O
In Intel Quartus Prime Pro Edition User Guide: Timing Analyzer
5.5.3. Register-to-Register
register-to-register
5.5.3.1. Timing Analyzer Path Report
Timing Analyzer register-to-register Tasks Report All Summaries
Report Clocks Summary Report Timing
Summary of Paths Extra Fitter Information Extra Fitter Information Intel Stratix 10
Data Path Data Arrival Path Data Required Path Waveform
Technology Map Viewer Locate Path Locate in Technology Map Viewer Chip Planner
· Netlist Viewer ( 14 ) ·
In Intel Quartus Prime Pro Edition User Guide: Timing Analyzer
5.5.3.2.
Fitter

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· Fitter Fitter
·
· From To Intel Quartus Prime

· Chip Planner ( 105 )
· ( 54 )

5.5.3.3.

·
From Clock To Clock

27.

From Clock To Clock

·
·

· report_timing

· Timing Report

· PLL
PLL
· FIFO
·
Fitter

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report_clock_transfers Intel Quartus Prime Help

5.5.3.4. /

report_timing
1. report_timing
2. .tcl From Node To Node

set wrst_src <insert_source_of_worst_path_here> set wrst_dst <insert_destination_of_worst_path_here> report_timing -setup -npaths 50 -detail path_only -from $wrst_src \ -panel_name "Worst Path||wrst_src -> *" report_timing -setup -npaths 50 -detail path_only -to $wrst_dst \ -panel_name "Worst Path||* -> wrst_dst" report_timing -setup -npaths 50 -detail path_only -to $wrst_src \ -panel_name "Worst Path||* -> wrst_src" report_timing -setup -npaths 50 -detail path_only -from $wrst_dst \ -panel_name "Worst Path||wrst_dst -> *"

3. Script .tcl
4. Chip Planner

28.

Source Register of Worst Path

LUT LUT

LUT

Legend wrst_src -> * * -> wrst_dst * -> wrst_src wrst_dst -> * Critical Path
.tcl

Destination Register of Worst Path
LUT

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· -- report_timing -- report_timing
· report_timing
Fitter
5.5.3.5. .tcl

report_timing setup npaths 50 detail path_only \ to "main_system: main_system_inst|app_cpu:cpu|*" \ panel_name "Critical Paths||s: * -> app_cpu"
3. *count_sync*
report_timing setup npaths 50 detail path_only \ from "main_system: main_system_inst|egress_count_sm:egress_inst|
update" \ to "*count_sync*" panel_name "Critical Paths||s: egress_sm|
update -> count_sync"
4. Timing Analyzer report_timing
5.5.3.6.
Intel Quartus Prime

Compilation Report Fitter Resource Section Global & Other Fast Signals NonGlobal High Fan-out Signals
/ Assignment Editor Global Signal

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5.6.

5.6.1.
Timing Closure Recommendations Intel Stratix 10 Fast Forward Timing Closure Recommendations 1. Timing Analyzerde Tasks Report Timing Closure
Recommendations Report Timing Closure Recommendations 2. 3. Timing Analyzer Report Timing Closure Recommendations Timing Analyzer GUI Report Report Timing Closure Recommendations *

report_timing Path Extra Fitter Information Extra Fitter Information Intel Stratix 10
· Fast Forward ( 87 ) ·
Intel Quartus Prime Help
5.6.2.
Timing Analyzer Report Timing Closure Recommendations Timing Optimization Advisor
Timing Optimization Advisor Timing Optimization Advisor Tools > Advisors > Timing Optimization Advisor
Timing Optimization Advisor
Timing Optimization Advisor

Intel Quartus Prime Pro Edition : 71

29.

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Timing Optimization Advisor Maximum Frequency (fmax) I/O Timing (tsu, tco, tpd)

Stage 1 Timing Optimization Advisor"How to use"
Intel Quartus Prime GUI Settings Synthesis Netlist Optimizations Assignment Editor Global Signals category Correct the Settings
Timing Optimization Advisor

5.6.3. Fitter

Fitter Optimize Hold TimingOptimize MultiCorner Timing Fitter Aggressive Routability Optimization

Fitter Intel Quartus Prime Help

5.6.3.1. Optimize Hold Timing Intel Quartus Prime

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30.

Advanced Fitter Settings Optimize Hold Timing Intel Quartus Prime I/O Paths Minimum TPD Paths Fitter
· (tH) · I/O I/O I/O I/O
· (tCO)
All PathsFitter

Fitter

clk

Logic

LCELL

In Intel Quartus Prime Pro Edition User Guide: Design Recommendations

5.6.3.2. Fitter

Fitter Aggressive Routability Optimizations Fitter

Fitter Aggressive Routability Optimizations

13.

Fitter

Always Never Automatically

Fitter Fitter Aggressive Routability Optimizations Always
Fitter Automatically Never
Fitter Automatically Never

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5.6.4. I/O

I/O tSUtH-tCO
I/O · Design Optimization Overview Initial
Compilation: Required Settings ·

-register-to-register I/O register-to-register

tSU tCO tSU tH

14.
1 2 3 4 5
6
7
8
9 10

I/O
I/O
OCT
Input Delay from Pin to Input Register Decrease Input Delay to Input Register = ON
Input Delay from Pin to Internal Cells Decrease Input Delay to Internal Cells = ON
Delay from Output Register to Output Pin Increase Delay to Output Pin = OFF
Input Delay from Dual-Purpose Clock Pin to Fan-Out Destinations
Use PLLs to shift clock edges
Delay to output enable pin Increase delay to output enable pin PLL

tSU Yes Yes Yes N/A Yes
Yes
N/A
Yes
Yes N/A

tCO Yes Yes N/A Yes N/A
N/A
Yes
N/A
Yes Yes

IOC ( 75 ) ( 75 ) ( 75 ) PLL ( 76 ) Fast Regional Clock Network Regional Clocks Network ( 76 ) ( 77 )
( 6 )

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5.6.4.1. IOC

I/O tSU tCO

Optimize IOC Register Placement for Timing tSU tCO I/O

Intel Quartus Prime Fitter

· · · · 1
IOC
Intel Quartus Prime Help

5.6.4.2.
Assignment Editor I/O I/O Fitter I/O
I/O I/O I/O I/O Optimize IOC Register Placement for Timing I/O Optimize IOC Register Placement for Timing Intel Quartus Prime I/O
4 I/O Fast Input RegisterFast Output RegisterFast Output Enable Register Fast OCT Register Logic Lock I/O Fitter I/O
Fast Input Register Fast Output Register Fast Output Enable Register Fast OCT (on-chip termination) Register Intel Quartus Prime Help
·
·
·
· OCT

5.6.4.3.
tSU tCO I/O

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Compilation Report Delay Chain Summary I/O
Assignment Editor Chip Planner Resource Property Editor Resource Property Editor
Intel Intel Quartus Prime Fitter
Intel Intel Quartus Prime Help
·
·
·
·
· Intel Quartus Prime Help

5.6.4.4. PLL

PLL I/O PLL
I/O tSU tH tH tSU PLL

31.

tH tSU

Original

With PLL

Input Delay from Dual Purpose Clock Pin to Fan-Out Destinations

5.6.4.5. Fast Regional Clock Network Regional Clocks Network
regional clock fast regional clock I/O tCO
Intel Intel

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5.6.4.6.
Intel Quartus Prime spine clockHSSI PMA Direct
spine clockSpine clock spine clock Spine clock
spine clock
· Logic Lock Logic Lock Logic Lock
· Periphery Logic Lock I/O
· Intel FPGA IP "" Regional Dual-Regional
· ( 99 )
· ( 97 )
· Report Spine Clock Utilization dialog box (Chip Planner) Intel Quartus Prime Help

5.6.5. Register-to-Register

Timing Analyzer register-to-register

In Intel Quartus Prime Pro Edition User Guide: Design Recommendations

5.6.5.1.
Logic Lock

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DSP RAM/DSP
Intel Quartus Prime Compilation Report Analysis & Synthesis State Machine
AN 584 FPGA
5.6.5.2. Register-to-Register
slack register-to-register 1.
2. 3. 4.
-- Optimize Synthesis for Speed, Not Area -- Flatten the Hierarchy During Synthesis -- Set the Synthesis Effort to HighSynthesis Effort High -- Prevent Shift Register Inference Shift Register -- Use Other Synthesis Options Available in Your Synthesis Tool Synthesis
Tool 5. Advanced Physical Optimization 6. Fitter seed
seed Fitter seed : 7. Logic Lock 8. 9. Design Space Explorer II (DSE)
· Design Space Explorer II ( 10 ) · ( 6 )

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5.6.5.3.
Intel Quartus Prime
Intel Quartus Prime EDA
Assignments > Settings > Compiler Settings > Advanced Settings (Fitter)
EDA Intel Quartus Prime Perform WYSIWYG Primitive Resynthesis Intel Quartus Prime LE Intel Intel Fitter
Intel Quartus Prime Optimization Technique Speed Balanced
Intel Quartus Prime Fitter Intel
· WYSIWYG ·
Intel Quartus Prime Help
5.6.5.4. Extra-Effort Power
Extra Effort Normal
· ·
Intel Quartus Prime Help
5.6.5.5.

Assignment Editor Optimization Technique Balanced Area Assignment Editor Speed Optimization Technique for Clock Domains

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DSE II Intel Quartus Prime

Intel Quartus Prime Help
5.6.5.6.

5.6.5.7. Synthesis Effort High
Synthesis high
5.6.5.8.
off-critical nets

RTL ( 80 )
· ·

5.6.5.8.1.
Intel Quartus Prime Assignment Editor Maximum Fan-Out HDL maxfan
Maximum Fan-Out

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Maximum Fan-Out Maximum FanOut Fitter Manual Logic Duplication
Maximum Fan-Out """"
Intel Quartus Prime Assignment Editor Manual Logic Duplication

Fitter Maximum Fan-Out

5.6.5.8.2. DUPLICATE_REGISTER
set_instance_assignment -name DUPLICATE_REGISTER -to <register_name> <num_duplicates>

· register_name DUPLICATE_REGISTER
· num_duplicates M M/N
Fitter DUPLICATE_REGISTER "" 100 DUPLICATE_REGISTER
Fit Fitter Duplication Summary Intel Quartus Prime Pro Edition DUPLICATE_REGISTER 1000 DUPLICATE_REGISTER

· PHYSICAL_SYNTHESIS OFF DUPLICATE_REGISTER · DUPLICATE_REGISTER
· DUPLICATE_REGISTER
-- -- -- preserve PRESERVE_REGISTER -- don't touch --

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5.6.5.8.3.
DUPLICATE_HIERARCHY_DEPTH
set_instance_assignment -name DUPLICATE_HIERARCHY_DEPTH -to <register_name> <num_levels>

· register_name
· num_levels
DUPLICATE_HIERARCHY_DEPTH

· · · · · preserve PRESERVE_REGISTER ·

32.

DUPLICATE_HIERARCHY_DEPTH 35 ( 84 )

4
inst_a

inst_b

regA regX regY regZ

inst_c inst_d

inst_e

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33.

regZ 4 regZregY regX 3 1 3 regA 100 DUPLICATE_HIERARCHY_DEPTH

regZ Hierarchy Level One

set_instance_assignment -name DUPLICATE_HIERARCHY_DEPTH -to regZ 1

inst_a

inst_b

num_levels=1 regA regX regY regZ

inst_c inst_d

inst_e

34.

num_levels 1 regZ

regZ Hierarchy Level Two

set_instance_assignment -name DUPLICATE_HIERARCHY_DEPTH -to regZ 2

inst_a

inst_b

num_levels=2 regA regX regY regZ

inst_c inst_d

inst_e

num_levels 2 regY regZ regZ 2 regY 1

Intel Quartus Prime Pro Edition : 83

35.

5. UG-20133 | 2019.09.30

set_instance_assignment -name DUPLICATE_HIERARCHY_DEPTH -to regZ 3

inst_a

inst_b

num_levels=3 regA regX regY regZ

inst_c inst_d

inst_e

num_levels 3 3 regZregY regZ 32 1
Synthesis Hierarchical Tree Duplication Summary DUPLICATE_HIERARCHY_DEPTH Synthesis Hierarchical Tree Duplication Details
5.6.5.9. Shift Register
ALTSHIFT_TAPS IP
5.6.5.10. Synthesis Tool
· Turn on register balancing or retiming · Turn on register pipelining · Turn off resource sharing

5.6.5.11. Fitter Seed
Fitter seed Fitter seed seed
seed

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Fitter seed Compiler Settings Timing Analyzer Settings Fitter
register-to-register Fitter seed sweep seed
seed seed
Assignments > Compiler Settings seed DSE II seed
Tcl Fitter seed
set_global_assignment -name SEED <value>

Design Space Explorer II ( 10 )

5.6.5.12. Router Timing Optimization Maximum
Router Timing Optimization Level Maximum Maximum Minimum Normal

Intel Quartus Prime Help

5.6.6.

Intel Quartus Prime Fitter Logic Lock

Arria® Stratix Fitter

5.6.7.
MTBF
MTBF Intel Quartus Prime MTBF Timing Analyzer

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MTBF Timing Optimization Advisor Metastability Optimization

· FPGA
· Managing Metastability with the Intel Quartus Prime Software In Intel Quartus Prime Pro Edition User Guide: Design Recommendations

5.6.8. Intel Stratix 10

Intel Stratix 10
FPGA Intel Stratix 10 Hyper Retimer Retiming Limit Report

In Intel Stratix 10

5.6.8.1.
Retiming Limit Details report Hyper Retimer
Retiming Limit Details report · Clock Transfer · Limiting Reason · Critical Chain Details
5.6.8.1.1. Retiming Limit Details
Retiming Limit Details 1. Reports Fitter > Retime Stage Retiming Limit Details 2. Technology Map Viewer Locate Critical
Chain in Technology Map Viewer Technology Map Viewer

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36.

Technology Map Viewer

5.6.8.2. Fast Forward
Fast Forward Compiler Fast Forward
Fast Forward RTL Fast Forward
Fast Forward Details Report

15.

Fast Forward

Step

Fast Forward Optimization Estimated fMAX
Optimization Analyzed Recommendation for Critical Chain

Fast Forward · ·

fMAX n fMAX

· Fast Forward Compile In Intel Stratix 10
· Fast Forward In Hyper-Optimization for Intel Stratix 10 Designs

5.6.8.2.1. Fast Forward
Fast Forward 1. Compilation Dashboard Fast Forward Timing Closure
Recommendations

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Compiler Fitter Compilation Report 2. Compilation Report RTL
Intel Quartus Prime Pro Edition Fast Forward · Fast Forward Assignments > Settings > Compiler
Settings > HyperFlex Run Fast Forward Timing Closure Recommendations during compilation · Fast Forward I/O Assignments > Settings > Compiler Settings > HyperFlex Advanced Settings
5.6.8.2.2. Fast Forward
Retime
RTL
Fast Forward Intel Stratix 10 Fast Forwar
Fast Forward
In Intel Stratix 10

5.7. P2C

Periphery to Core Register Placement and Routing OptimizationP2C Fitter FPGA P2C

Periphery to Core Register Placement and Routing Optimization

I/O FPGA Fitter P2C

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37.

P2C
P2C P2C/C2P
User Design

Synthesis

Periphery Placement

P2C Core Placement

Routing

Design Implementation

Advanced Fitter Setting ( 89 ) Assignment Editor ( 89 ) Fitter Report ( 90 )
5.7.1. Advanced Fitter Setting
Periphery to Core Placement and Routing Optimization Fitter FPGA
Assignment Editor 1. Intel Quartus Prime Assignments > Settings > Compiler
Settings > Advanced Settings (Fitter) 2. Advanced Fitter Settings Periphery to Core Placement and
Routing Optimization a. Auto
b. On
: Advanced Fitter Settings On Assignment Editor
c. Off
5.7.2. Assignment Editor
Assignment Editor Periphery to Core Placement and Routing Optimization (P2C/C2P) Intel Quartus Prime

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Advanced Fitter Settings 1. Intel Quartus Prime Assignments > Assignment Editor 2. Assignment Name Periphery to core
register placement and routing optimization 3. To P2C/C2P From
Assignments Editor Analysis & Synthesis

5.7.3. Fitter Report

Intel Quartus Prime Fitter (Place & Route) 1. Intel Quartus Prime 2. Tasks Compilation 3. Fitter (Place & Route) View Report 4. Fitter Place Stage 5. Periphery to Core Transfer Optimization Summary

16.

Fitter Report --P2C

Node 1

Node 2

Placed and Routed--/

Node 3

Node 4

Placed but not Routed-- P2C / P2C

Node 5

Node 6

Not Optimized-- P2C Auto
a. b. P2C
c. P2C

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5.8.
Tcl Intel Quartus Prime Tcl API Help "Help"

quartus_sh --qhelp

/ Tcl set_global_assignment -name <.qsf variable name> <value>

Tcl set_instance_assignment -name <.qsf variable name> <value> -to <instance name>

<value>`Standard Fit'
· Intel Quartus Prime Pro Edition
Intel Quartus Prime
· Tcl Scripting In Intel Quartus Prime Pro Edition
· Command Line Scripting In Intel Quartus Prime Pro Edition

5.8.1.
Tcl Intel Quartus Prime Settings File (.qsf) Type
.qsf

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17.

Optimize IOC Register Placement For Timing IOC

.qsf File Variable Name

OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ON, OFF

OPTIMIZE_HOLD_TIMING

OFF, IO PATHS AND MINIMUM TPD PATHS, ALL PATHS

Global
Global

18.

Router Timing Optimization level

.qsf

ROUTER_TIMING_OPTIMIZATION_LEVEL NORMAL, MINIMUM, MAXIMUM

Global

( 6 )

5.8.2. I/O

.qsf I/O

19.

I/O

Optimize IOC Register Placement For Timing IOC
Fast Input Register

Fast Output Register

Fast Output Enable Register

Fast OCT Register

.qsf

OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ON, OFF Global

FAST_INPUT_REGISTER FAST_OUTPUT_REGISTER FAST_OUTPUT_ENABLE_REGISTER FAST_OCT_REGISTER

ON, OFF Instance ON, OFF Instance ON, OFF Instance ON, OFF Instance

5.8.3. Register-to-Register

.qsf Register-to-Register

20.

Perform WYSIWYG Primitive Resynthesis Fitter Seed
Maximum Fan-Out

.qsf

ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON, OFF

SEED MAX_FANOUT

Global, Instance
Global
Instance ...

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Manual Logic Duplication

.qsf DUPLICATE_ATOM

Optimize Power during

OPTIMIZE_POWER_DURING_SYNTHESIS

Synthesis

Optimize Power during Fitting Fitting

OPTIMIZE_POWER_DURING_FITTING

<node name>
NORMAL, OFF EXTRA_EFFORT NORMAL, OFF EXTRA_EFFORT

Instance Global Global

5.9.

Intel Quartus Prime

2019.07.01

19.1

2019.04.01

19.1

2018.11.12 2018.09.24 2017.11.06

18.1.0 18.1.0 17.1.0

2017.05.08

17.0.0

· · Duplicate Logic for Fan-out Control
·

· """" · " Fitter ""Fitter " · """"
· · " IOC " CARRY
CASCADE
· Intel Stratix 10 Hyper-RetimingFast Forward Fast Forward Viewer -- """""Intel Stratix 10 """" Retiming Limit Details Report ""Fast Forward "" Fast Forward "" Fast Forward "
· · """ Fitter
" · · ·
· · Register-to-Register Register-to-Register
· Timing Analyzer Timing
Analyzer · LUT-Based Devices · (LUT-Based Devices) · Timing Analyzer
...

Intel Quartus Prime Pro Edition : 93

2016.10.31 2016.05.02 2015.11.02 2014.12.15 2014 6 2013 11
2013 5
2012 11 2012 6
2011 11

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Intel Quartus Prime
16.1.0 16.0.0 15.1.0 14.1.0 14.0.0 13.1.0
13.0.0
12.1.0 12.0.0
11.1.0

· Register-to-Register Register-toRegister
· Tips for Locating Multiple Paths to the Chip Planner LogicLock Assignments and Hierarchy Assignments
· Fitter Effort Logic Option · Pin Advisor Resource Optimization Advisor · Clock Regions
· Intel
· ·
· · Quartus II Quartus Prime
· Fitter SettingAnalysis & Synthesis Physical Synthesis Optimizations Setting Compiler Setting
· DSE II
· DITA · QII v14.0 Arria GX, Arria II,
Cyclone III, Stratix II, Stratix III. · IP Megafunction
· · Optimizing Timing (Macrocell-Based CPLDs) · Multi-Corner Fitter · Timing Analyzer Report All
Summaries · Fitter Summary Reports
Ignored Assignment Report
· """" · / ·
Fitter Chip Planner .tcl
· " Fitter " 132 "I/O " 13 2" Fitter " 132 "" 13 9 "" 1321 "" 1343
· " Multi-Corner " 136 "" 1310 " Timing Analyzer " 1312 " Resource Optimization Advisor" 1315 " Placement Effort Multiplier" 1322 " Router Effort Multiplier" 1322 "Timing Analyzer " 1324
·
· """ Fit"" Fit"" Multi-Corner "" Timing Analyzer ""Timing Analyzer ""LogicLock """" """""
· 13-6 · "Spine Clock "
...

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2011 5 2010 12 2010 8 2010 7

Intel Quartus Prime
11.0.0
10.1.0
10.0.1 10.0.0

· 19 "Change State Machine Encoding" · 13-5 ·
· " Fitter " · "" · "" · Help ·
· Help · · " Timing Analyzer " · Classic Timing Analyzer ·

· """" · "" · """" · · · DSE Help · Help · "

Intel Quartus Prime

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FPGA Chip Planner Logic Lock
Intel Quartus Prime Chip Planner Chip Planner Logic Lock
Chip Planner I/O Pin Planner
"Early Place Flow"
Early Place Flow Intel Quartus Prime Pro Edition
Partial Reconfiguration Intel Quartus Prime Pro Edition
·
Intel Quartus Prime Pro Edition ·
In Intel Quartus Prime Pro Edition · I/O

6.1. Chip Planner
Chip Planner Chip Planner
Chip Planner

· Logic Lock

ISO 9001:2015 Registered

6. UG-20133 | 2019.09.30
6.1.1. Chip Planner
Chip Planner Tools > Chip Planner Chip Planner
· Intel Quartus Prime Chip Planner · Locate > Locate in Chip Planner
-- Compilation Report -- Logic Lock Regions Window -- Technology Map Viewer -- Project Navigator window -- Node Finder -- Simulation Report -- Report Timing panel of the Timing Analyzer
6.1.2. Chip Planner GUI
6.1.2.1. Chip Planner Toolbar Chip Planner View Chip Planner
6.1.2.2. Chip Planner
Layers Setting
Layers Settings Chip Planner
View > Layers Settings Layers Settings Layers Settings BasicDetailed Floorplan Editing
· ( 98 ) · Layers Settings Dialog Box
Intel Quartus Prime Help
6.1.2.3. Chip Planner Locate History Locate in Chip Planner

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Timing Analyzer Report Timing Locate History Timing Analyzer Report Timing Locate History Locate History Chip Planner
6.1.2.4. Chip Planner
Chip Planner Intel

Bird's Eye View Chip Planner

Properties Chip Planner Logic Lock Properties View > Properties
Bird's Eye View Window
Intel Quartus Prime Help
6.1.3. Chip Planner
Chip Planner I/O bank
Chip Planner
6.1.3.1.
Chip Planner Layers Settings
· Device routing resources used by your design--
· LE configuration--LE) LE LE look-up tableLUT LE
· ALM configuration-- ALM ALM ALM LUT LUT ALM
· I/O configuration-- I/O I/O I/O I/O
· PLL configuration--phase-locked loopPLL PLL PLL
· Timing-- FPGA DATAB COMBOUT

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· ( 97 )
· Layers Settings Dialog Box Intel Quartus Prime Help

6.1.3.2.

Layers Settings

38.

· Layers Settings Chip Planner PLL
·
· Spine/sector · Chip Planner Tools > Options > Colors > Clock
Regions
· ( 77 ) · ( 97 ) · Report Spine Clock Utilization dialog box (Chip Planner)
Intel Quartus Prime Help
6.1.3.3.
Chip Planner
Chip Planner

Intel Quartus Prime Pro Edition : 99

39.

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1. Tasks Report Clock Sector Utilization Report Clock Sector Utilization
2. Report source nodes TCL
3. OK
Report Report

Report Clock Sector Utilization dialog box (Chip Planner) Intel Quartus Prime Help

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6.1.3.4.
Report Routing Utilization
Chip Planner 1. Tasks Report Routing Utilization Report Routing
Utilization 2. Report Routing Utilization Preview 3. Routing Utilization Type
0% 0 100% Threshold percentage
RTL ·
Report Routing Utilization · Routing Utilization Settings
· Compiler 75%
60% 90% 75%
( 107 )
6.1.3.5. I/O Bank
Chip Planner I/O bank Tasks Report All I/O Banks
6.1.3.6. HSSI
Chip Planner HSSI Tasks Report HSSI Block Connectivity

Intel Quartus Prime Pro Edition : 101

40.

Intel Arria 10 HSSI Channel Blocks

6. UG-20133 | 2019.09.30

6.1.3.7.
Chip Planner Report Registered Connections Generate Fanin/Fanout connections 1. Chip Planner 1 2. Task Report Registered Connections 3. OK
Reports

Intel Quartus Prime Pro Edition : 102

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41.

· ( 103 ) · Expand Connections Command (View Menu)
Intel Quartus Prime Help
6.1.3.8.

1. Chip Planner Generate Fan-In Connections Generate
Fan-Out Connections 2. "Chip Planner" Clear Unselected Connections

Chip Planner View
· ( 102 ) · Expand Connections Command (View Menu)
Intel Quartus Prime Help

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6.1.3.9.

· View > Generate Immediate Fan-In Connections
View > Generate Immediate Fan-Out Connections · Chip Planner Clear Unselected Connections

6.1.3.10.

Chip Planner Chip Planner Compiler

Chip Planner
1. Tasks Report Selection ContentsReport Selection Contents
2. Report design instances in selection Show registers names Show combinational names

42.

Report Selection Contents

3. OK Reports

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43.

44.

4. Properties Report NameReport Color Highlighted Area Minimum Size

6.1.4. Chip Planner
Chip Planner Chip Planner Timing Analysis
6.1.4.1. Chip Planner Chip Planner Expand Connections

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Expand Connections Command (View Menu) Intel Quartus Prime Help

6.1.4.2. Timing Analysis Report Chip Planner Timing Analysis Chip Planner

45.

1. "Timing Analysis " 2. Locate Path > Locate in Chip Planner
Chip Planer Locate History
Locate History Window

Timing Analyzer Path Report ( 67 )
6.1.4.3.
Show Delays Timing Analyzer View > Show Delays Chip Planner "Show Delays " Locate History "+"

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46.

Timing Analyzer Path

6.1.4.4.

Chip Planner Locate History "Arrival Data""Arrival Clock"

47.

Locate History Show Physical Routing Zoom to Selection

Intel Quartus Prime Pro Edition : 107

48.

6. UG-20133 | 2019.09.30
Fitter Highlight Routing

( 101 )

6.1.5. Chip Planner

Chip Planner

49.

Chip Planner

Layer Settings

Logic Lock Fitter

6.1.6. Chip Planner Tile
Intel ALM Intel Quartus Prime ALM "tiles"

Intel Quartus Prime Pro Edition : 108

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50.

Fitter Tasks > Core Reports > Report High-Speed/ Low-Power TilesChip Planner tiles tiles tiles
Intel Arria 10 Tile

tiles High Speed Mode

6.2. Design Partition Planner Chip Planner Logic Lock
Fitter Logic Lock Design Partition Planner Chip Planner Logic Lock
Intel Quartus Prime Pro Edition 1. 2. Chip Planner Design Partition Planner
-- Tools > Chip Planner -- Tools > Design Partition Planner 3. Chip Planner Tasks Report Design Partitions Report Design Partitions Chip Planner Design Partition Planner 4. Chip Planner View > Bird's Eye View Bird's Eye View 5. Design Partition Planner Extract from Parent

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Chip Planner Design Partition Planner Chip Planner Design Partition Planner 6. Logic Lock -- Chip Planner -- Design Partition Planner 7. Logic Lock Collapse to Parent 8. Create Design Partition 9. Create Logic Lock Region Logic Lock

In Intel Quartus Prime Pro Edition

6.2.1.

Design Partition Planner

51.

Design Partition Planner

Intel Quartus Prime Pro Edition : 110

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52.

· Extract from Parent Design Partition Planner

· View > Bundle Configuration Bundle Configuration
· Timing Analyzer Design Partition Planner View > Show Timing Data
· Bundle Properties Bundle Properties
· View > Hierarchy Display
6.3. Chip Planner Logic Lock
Chip Planner Logic Lock
6.3.1. Chip Planner Logic Lock
Chip Planner Logic Lock Logic Lock Layers Settings Floorplan Editing User-assigned Logic Lock regions
Chip Planner Logic Lock Logic Lock Chip Planner View Inter-region Bundles
Inter-region Bundles
Inter-region Bundles Intel Quartus Prime Help

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6.3.3. Logic Lock

Logic Lock When you assign instances or nodes to a Logic Lock Fitter Logic Lock

"Early Place Flow"

Logic Lock Intel Quartus Prime Pro Edition Logic Lock

Logic Lock
· Placement RegionFitter "Reserved" Fitter
· Routing Region Defining Routing Regions

·
Intel Quartus Prime Pro Edition · Logic Lock ( 113 )

6.3.4. Logic Lock

Logic Lock Intel Quartus Prime Logic Lock Regions Logic Lock

21.

Logic Lock

Width

Height

Origin
Reserved Core-Only

Off | On Off | On

Size/State

Fixed/Locked | Auto/Floating

Logic Lock
Size/State Auto/Floating Undetermined

Logic Lock Logic Lock

Fitter Reserved

Intel Quartus Prime Standard Edition Intel Quartus Prime Pro Edition Reserved Core Only

Fitter Logic Lock

...

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Routing Region Unconstrained | Whole Chip | Fixed with Expansion | Custom

· "Fixed/Locked" Logic Lock
· Auto/Floating Fitter Logic Lock
Defining Routing Regions

Logic Lock ( 121 )

6.3.5. Intel Quartus Prime Standard Edition Intel Quartus Prime Pro Edition
Intel Quartus Prime Pro Edition Intel Quartus Prime Standard Edition Logic Lock Intel Quartus Prime Standard Edition Intel Quartus Prime Pro Edition Logic Lock (Standard) Logic Lock

Replace Logic Lock Regions In Intel Quartus Prime Pro Edition User Guide: Getting Started

6.3.6. Logic Lock

6.3.6.1. Chip Planner Logic Lock 1. View > Logic Lock Regions > Create Logic Lock Region 2. Chip Planner

6.3.6.2. Project Navigator Logic Lock 1. 2. Project Navigator View > Utility Windows > Project NavigatorProject Navigator 3. Create New Logic Lock 4.
6.3.6.3. Logic Lock Regions Window Logic Lock 1. Assignments > Logic Lock Regions Window 2. Logic Lock Regions <<new>>

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Logic Lock ( 121 )

6.3.6.4.

Logic Lock Logic Lock "reserved" Logic Lock Regions Routing Region

22.

Unconstrained Whole Chip Fixed with Expansion Custom

Unconstrained Intel Quartus Prime .qsf
/ Logic Lock Custom Chip Planner Shift

53.

Routing Regions

Fixed with Expansion +2

Custom Routing

6.3.6.5. Logic Lock
Logic Lock Logic Lock Logic Lock

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54.

Logic Lock

Merging Logic Lock Regions ( 116 )
6.3.6.6. Auto Sized Region Auto/Floating Size/State Logic Lock

· Auto/Floating
· Logic Lock Fitter 0 x 0
· Auto/Floating Size/State Logic Lock Fitter
-- Logic Lock Fitter Logic Lock
-- Logic Lock
-- Logic Lock Fitter
· Logic Lock
-- Logic Lock Fixed/Locked Size/State
-- Logic Lock Auto/Floating Size/State "keep together"
-- Logic Lock Logic Lock

6.3.7. Logic Lock

Logic Lock Logic Lock

17.1 Logic Lock

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6.3.7.1. Logic Lock

Logic Lock Chip Planner 1. Logic Lock 2. Navigation Add Logic Lock Region icon 3. Logic Lock
:

55.

Add Logic Lock Region

6.3.7.2. Logic Lock

Logic Lock Chip Planner 1. Logic Lock 2. Navigation Subtract Logic Lock Region icon 3.

56.

Subtract Logic Lock Region

6.3.7.3. Merging Logic Lock Regions
2 Logic Lock 1. 2. 3. Shift 4. Logic Lock Logic Lock Regions > Merge Logic
Lock Region Merge Logic Lock Region

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57.

Logic Lock

Logic Lock ( 113 )

6.3.7.4. Logic Lock

Logic Lock Logic Lock Logic Lock

58.

Logic Lock

Merging Logic Lock Regions ( 116 )
6.3.8. Logic Lock
Logic Lock
Logic Lock Intel Quartus Prime Logic Lock
Logic Lock Region Logic LockProperties > Add Intel Quartus Prime Hierarchy Logic Lock Regions Window Logic Lock

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6.3.8.1. Logic Lock

Intel Quartus Prime Logic Lock "Empty regions" FPGA Reserved

Logic Lock · · · ·

Logic Lock Fitter

Logic Lock Core Only Logic Lock

59.

empty Logic Lock IOHSSIO PLL empty IO IO root_partitiontoplevel partition
6.3.8.2.
Logic Lock Intel Quartus Prime Pro Edition Core Only "off"
Logic Lock I/O
6.3.8.3. Logic Lock
Reserved Fitter Logic Lock Logic Lockregion
Intel Quartus Prime Logic Lock

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Intel Quartus Prime Logic Lock Regions Reserved

6.3.8.4.
Compiler I/O LUT Virtual Pin Assignment Editor Virtual Pin I/O
Virtual Pin FPGA Compiler GND
I/O

Virtual Pin I/O Synthesis Fitter I/O I/O

Logic Lock Virtual Pin Virtual Pin
Node Finder Filter Type Pins: Virtual Assignment Editor Node Finder To Node Finder

· Tcl ( 127 )
· Node Finder Command Menu Intel Quartus Prime Help

6.3.8.5. Intel Arria 10 FPGA Logic Lock

"Early Place Flow"

I/O Column Intel Arria 10 FPGA Logic Lock

Intel Quartus Prime Pro Edition : 119

60.

6. UG-20133 | 2019.09.30

Intel Arria 10 FPGA I/O Column

Core I/O

Column

61.

I/O column

Intel Arria 10 FPGA I/O Column

I/O
Core I/O Column

Core I/O Column

62.

Intel Arria 10 FPGA Logic Lock Region

· Logic Lock I/O Logic Lock I/O I/O

· Logic Lock I/O

Logic Lock Region ()
I/O

Core I/O Column

High Speed Signal ()

·
Intel Quartus Prime Pro Edition ·
In Intel Quartus Prime Pro Edition

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6.3.9.
Logic Lock Parent child Reserved Core-Only
Logic Lock
Logic Lock

6.3.10. Intel Quartus Prime Logic Lock
Logic Lock Regions Window Intel Quartus Prime Logic Lock

6.3.10.1. Intel Quartus Prime
Logic Lock Intel Quartus Prime Revisions
Revisions Project > Revisions Logic Lock

6.3.11. Logic Lock

Logic Lock Regions Window Logic Lock Logic Lock Regions Window Logic Lock

Chip Planner View > Logic Lock Window Logic Lock Regions Window Intel Quartus Prime Assignments > Logic LockWindow

63.

Logic Lock

"" Logic Lock Regions Window"" ""
Logic Lock Regions
Logic Lock Regions Properties Logic Lock
Logic Lock Regions Properties Logic Lock Regions Properties...

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· Logic Lock ( 112 )
· Logic Lock Regions Window Logic Lock ( 113 )
· Logic Lock Intel Quartus Prime Help

6.3.12. Snapping to a Region

Chip Planner Logic Lock snap-to-lab Logic Lock Intel Arria 10 Intel Agilex® FPGA Intel Stratix 10 FPGA
Logic Lock lab View > Logic Lock Regions > Snap Logic Lock Region to

Logic Lock snap-to-clock-region

64.

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Logic Lock · Creating Region Logic Lock Logic
Lock · Resize region (and resize diagonal) Logic Lock
Logic Lock · Move region Logic Lock
Logic Lock -- Same place and route regions are moved
Logic Lock -- Only place | route region is moved |
"place bboxes contained within route bboxes" bbox bbox · Subtract or make a hole snap-to-clock-region
6.4. Chip Planner
Chip Planner

user-defined clock region Fitter
User-Defined Clock Region

Intel Stratix 10 Intel Agilex Devices Clock Region Assignments
Chip Planner "Clock Sector Region"SX0, SY0, SX1, SY1 0,0 1,1 2 × 2
X37 Y181 X273 Y324 Fitter

6.4.1. Chip Planner Clock Assignment

Intel Quartus Prime Pro Edition : 123

65.

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1. Create Clock Assignment Create Clock Assignment

View > Clock Assignments >

2. Chip Planner

unassigned

6.4.2. Clock Assignment
1. 2. 3.

6.4.3. Clock Assignment
1. 2. 3.

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6.4.4. Clock Region Assignment

1. 2. View 3. Clock Assignments > Delete Clock Assignment 4. Yes
6.4.5.

1. View 2. Clock Assignments > Set Clock Signal Name 3. Set Clock Signal Name
4. Ok

6.4.6. Clock Assignment

Clock Assignment Properties

Clock Assignment Properties Chip Planner

66.

Clock Assignment Properties

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6.5.
Tcl
· Tcl Scripting
In Intel Quartus Prime Pro Edition · Command Line Scripting
In Intel Quartus Prime Pro Edition

6.5.1. Tcl Logic Lock

Intel Quartus Prime Tcl Logic Lock

GUI Logic Lock QSFQSF X/Y Placement Region
X46 Y36 X65 Y49

set_instance_assignment -name PLACE_REGION "X46 Y36 X65 Y49" -to <node names>
· · ; 2 · PLACE_REGION

X5 Y5 X30 Y30

set_instance_assignment -name ROUTE_REGION -to <node names> "X5 Y5 X30 Y30"
· ·

"" set_instance_assignment -name <instance name> RESERVE_PLACE_REGION -to <node names> ON
·

"Core Only"
Intel Quartus Prime Pro Edition Logic Lock "core only"

set_instance_assignment -name <instance name> CORE_ONLY_PLACE_REGION -to <node names> ON

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Logic Lock ( 113 )

6.5.2. Tcl Tcl my_pin
set_instance_assignment -name VIRTUAL_PIN ON -to my_pin

· ( 119 )
· Node Finder Command Menu Intel Quartus Prime Help

6.5.3. Logic Lock

.qsf Logic Lock Assignment Editor Logic Lock Regions Window Chip Planner

-1:

Logic Lock

Logic Lock 10,1020,20 set_instance_assignment name PLACE_REGION to a|b|c "X10 Y10 X20 Y20"

-2:

Logic Lock
"x|y|z" L Logic Lock 4
set_instance_assignment name PLACE_REGION to x|y|z "X10 Y10 X20 Y50; X20 Y10 X50 Y20"

-3:

Logic Lock
Intel Quartus Prime Logic Lock "a|b|c|d" (10,10), (15,15)(0,0), (15,15)
set_instance_assignment name PLACE_REGION to a|b|c "X10 Y10 X20 Y20" set_instance_assignment name PLACE_REGION to a|b|c|d "X0 Y0 X15 Y15"

-4:

Logic Lock
Logic Lock c g c g
set_instance_assignment name PLACE_REGION to a|b|c "X10 Y10 X20 Y20" set_instance_assignment name PLACE_REGION to e|f|g "X10 Y10 X20 Y20"

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-5:

Logic Lock
Logic Lock
set_instance_assignment name PLACE_REGION to a|b|c "X10 Y10 X20 Y20" set_instance_assignment name RESERVE_PLACE_REGION to a|b|c ON
# The following assignment causes an error. The logic in e|f|g is not # legally placeable anywhere: # set_instance_assignment name PLACE_REGION to e|f|g "X10 Y10 X20 Y20"
# The following assignment does *not* cause an error, but is effectively # constrained to the box (20,10), (30,20), since the (10,10),(20,20) box is reserved # for a|b|c set_instance_assignment name PLACE_REGION to e|f|g "X10 Y10 X30 Y20"

6.6.

23.

Intel Quartus Prime

2019.07.30

19.3.0

2019.07.01

19.1.0

2019.04.01

19.1.0

2018.09.24

18.1.0

2018.05.07 2017.11.06

18.0.0 17.1.0

2017.05.08

17.0.0

Chip Planner
"" Snap Logic Lock Region to
· "Viewing Selected Contents"
· · ·
·
· LogicLock Plus Logic Lock · Logic Lock · Logic Lock · Design Partition Planner Chip Planner Auto
Sized RegionsCreating Partitions Logic Lock Region
· · Locate History Window Path List
LogicLock LogicLock · HSSI Channel Arria 10 Tile Chip Planner LogicLock Plus Merge LogicLock Plus · LogicLock Plus LogicLock Plus · · LogicLock Plus LogicLock Plus · Chip Planner Chip Planner · Chip Planner
...

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2016.10.31
2016.05.02 2015.11.02
2015.05.04 2014.12.15 2014 6 2013 11 2013 5 2012 6 2011 11 2011 5
2010 12 2010 7

Intel Quartus Prime 16.1.0
16.0.0 15.1.0
15.0.0 14.1.0 14.0.0 13.1.0 13.0.0
12.0.0 11.0.1 11.0.0
10.1.0 10.0.0

· Intel · LogicLock Plus
LogicLock Plus
· Quartus II Quartus Prime · LogicLock
LogicLock
Virtual Pins

HardCopy
"" Chip Planner Quartus UI

· 11.0 "LogicLock " "" "" 15-415-915-10 15-13 15-6
· 10.1
· · "
" · Help · " Design Partition Planner LogicLock "
...

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2009 11 2008 5

Intel Quartus Prime 9.1.0
8.0.0

· "" · ·
· · Timing Closure Floorplan
Timing Closure Floorplan Quartus Prime · " LogicLock " · "Selected Elements Window" · 12-1
· "Chip Planner " "LogicLock " " LogicLock " " LogicLock "
· " LogicLock " " LogicLock " ""
· 10-1 ·
LogicLock

Intel Quartus Prime

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FPGA Intel Quartus Prime ECO
ECO LUT PLL ECO
::quartus::eco Tcl ECO
Intel Quartus Prime Pro Edition Intel Stratix 10 Intel Agilex ECO

7.1.

1. ECO 2. ECO ECO ( 132 ) ECO ( 136
) 3. Tcl ECO Tcl ( 132 ) 4. ECO Project > Archive Project 5. Processing > Start > Start ECO Compilation

67.

ECO

my_script.tcl

6. ECO Tcl Script OKFitter ECO Fitter Fitter
ECO Assembler Assembler Compilation Dashboard Assembler
7. post-fit ECO Timing AnalyzerNetlist Viewer Chip Planner
GUI

ISO 9001:2015 Registered

7. UG-20133 | 2019.09.30

· Tcl Console ECO
execute_flow -eco <script>.tcl
Tcl Console ECO Assembler Assembler .qsf
set_global_assignment -name FLOW_DISABLE_ASSEMBLER ON
· " quartus_fit <project> -c <revision> --eco <script>.tcl
Intel Quartus Prime GUI GUI
ECO Fitter ECO ECO RTL IP

7.2. ECO Tcl

ECO Tcl lutmask

68.

ECO Tcl

-to inst -eqn "A|B"

7.3. ECO
Intel Quartus Prime Pro Edition ECO
make_connection ( 133 ) remove_connection ( 133 ) modify_lutmask ( 134 ) adjust_pll_refclk ( 134 ) modify_io_slew_rate ( 135 ) modify_io_current_strength ( 135 ) modify_io_delay_chain ( 135 )
ECO ( 136 )

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7.3.1. make_connection
Netlist Viewer Properties top|a_out top|x D make_connection -from top|a_out -to top|x -port D
Argument
from
to
port
tieoff VCC GND VCC GND
make_connection tieoff VCC to {node1} port DATAA
to
port
7.3.2. remove_connection
src Netlist Viewer Properties top|x D top|a_out top|x:D remove_connection -from top|a_out -to top|x -port D
Argument
from

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port
7.3.3. modify_lutmask
lutmask lutmask -mask lutmask -eqn
top|x D top|a_out top|x:D
modify_lutmask -to top|lut_c -eqn {a&b&c} modify_lutmask -to top|lut_a -mask 0xFF00FF00 modify_lutmask -to top|lut_b -mask 0b111111111001010
Argument
eqn A, B, C, D, E, F AND('&') OR('|')XOR('^')NOT('!')OPEN_BRACE('(')CLOSE_BRACE(')') -mask -eqn

mask lutmask -mask -eqn

Resource Property Viewer lutmask F0/F1/F2/F3 LUT ABC D E F LUT ALM E F

7.3.4. adjust_pll_refclk
IOPLL · refclk outclk · IOPLL IP · IOPLL · IOPLL "" · IOPLLoutclks 50 0 · Intel Agilex

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100 MHz *pll_main* IOPLL adjust_pll_refclk -to {*pll_main*} -refclk 100 Argument
to IOPLL[ or ]
refclk refclk MHz
7.3.5. modify_io_slew_rate
I/O I/O modify_io_slew_rate 1 -to top|ipin Argument
to
7.3.6. modify_io_current_strength
I/O I/O modify_io_current_strength 3mA -to top|ipin Argument
to
7.3.7. modify_io_delay_chain
I/O modify_io_delay_chain 3 -to top|ipin -type input

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Argument
type I/O input, output, oe, io_12_lane_input, io_12_lane_input_strobe

to I/O

7.4. ECO

Compiler ECO Compilation Report Fitter ECO Changes fit.eco

Compiler ECO "" ECO

69.

ECO

7.5. ECO
Intel FPGA ECO ECO ECO remove_connection make_connection
· -from · ALM LUT ·

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· RAM ECO RAM RAM Resource Property Editor Node Selection RAM RAM(s) RAM RAM Copy All ECO
· LUTRAM LAB LUTRAM
· Hyper-Register Hyper-Register
{}""

7.6.

24.

Intel Quartus Prime

2019.09.30

19.3.0

2019.07.01

19.2.0

· make_connection tieoff · modify_io_slew_rate · modify_io_current_strength · modify_io_delay_chain · " ECO " · modify_lutmask num · RTL Viewer ·
· First release of chapter.

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8. Intel Quartus Prime Pro Edition

Intel Quartus Prime

19.1

Intel Quartus Prime Pro Edition

18.1

Intel Quartus Prime Pro Edition

18.0

Intel Quartus Prime Pro Edition

ISO 9001:2015 Registered

UG-20133 | 2019.09.30

A. Intel Quartus Prime Pro Edition
Intel Quartus Prime Pro Edition FPGA

· Intel Quartus Prime Pro Edition Intel Quartus Prime Pro Edition Intel Quartus Prime Pro Edition IP
· Intel Quartus Prime Pro Edition Platform Designer IP Platform Designer IP
· Intel Quartus Prime Pro Edition Intel Quartus Prime Pro Edition FPGA HDL HDL Intel Quartus Prime Pro Edition
· Intel Quartus Prime Pro Edition Intel Quartus Prime Pro Edition Compiler Compiler
· Intel Quartus Prime Pro Edition Intel FPGA Intel Quartus Prime Pro Edition ECO
· Intel Quartus Prime Pro Edition Programmer Intel Quartus Prime Pro Edition Programmer Intel FPGA Intel FPGA CPLD
· Intel Quartus Prime Pro Edition
· Intel Quartus Prime Pro Edition Partial Reconfiguration FPGA FPGA
· Intel Quartus Prime Pro Edition Aldec*Cadence* Mentor Graphics* Synopsys RTL- Intel FPGA IP
· Intel Quartus Prime Pro Edition Mentor Graphics* Synopsys

ISO 9001:2015 Registered

A. Intel Quartus Prime Pro Edition
UG-20133 | 2019.09.30
· Intel Quartus Prime Pro Edition OneSpin* LEC LEC
· Intel Quartus Prime Pro Edition Intel Quartus Prime Pro Edition "" System ConsoleSignal Tap logic analyzerTransceiver ToolkitInSystem Memory Content Editor In-System Sources and Probes Editor
· Intel Quartus Prime Pro Edition Timing Analyzer Intel Quartus Prime Pro Edition Timing Analyzer ASIC
· Intel Quartus Prime Pro Edition Intel Quartus Prime Pro Edition Power Analysis
· Intel Quartus Prime Pro Edition Compiler I nterface Planner Pin Planner I/O
· Intel Quartus Prime Pro Edition PCB Mentor Graphics* Cadence* PCB HSPICE IBIS
· Intel Quartus Prime Pro Edition Tcl Intel Quartus Prime Pro Edition

Intel Quartus Prime Pro Edition : 140

Antenna House PDF Output Library 6.6.1359 (Linux64)

	Accelerating Timing Closure with Intel Quartus Prime Pro Edition Learn how to accelerate timing closure in FPGA designs using Intel Quartus Prime Pro Edition software. This guide details a three-step methodology for optimizing RTL, applying compiler techniques, and preserving design results for improved performance.
	Intel Quartus Prime Pro Edition User Guide: Power Analysis and Optimization A comprehensive guide to Intel Quartus Prime Pro Edition software, detailing methods for accurate FPGA power analysis and optimization. Covers tools like the Power Analyzer, input configurations, and power-driven compilation techniques for efficient power management.
	Intel® MAX® 10 FPGA Design Guidelines This document offers comprehensive design guidelines and recommendations for Intel® MAX® 10 FPGAs. It covers the entire design flow, from initial device selection and board layout to detailed implementation, timing, power optimization, and debugging, aiming to improve design productivity and achieve optimal results.
	Intel Quartus Prime Pro Edition User Guide: Power Analysis and Optimization Learn how to estimate and optimize power consumption for FPGA designs using the Intel Quartus Prime Pro Edition software. This guide covers power analysis tools, design guidelines, and compilation techniques for efficient power management.
	Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations Updated for Intel Quartus Prime Design Suite: 21.1. This guide describes best design practices for designing FPGAs with the Intel Quartus Prime Pro Edition software. HDL coding styles and synchronous design practices significantly impact design performance. Following recommended HDL coding styles ensures that Intel Quartus Prime Pro Edition synthesis optimally implements your design in hardware. Design Assistant checks your design against a set of standard design rules.
	Intel Quartus Prime Pro Edition User Guide: Scripting This user guide provides comprehensive instructions on using Tcl and command-line scripting with Intel Quartus Prime Pro Edition software. Learn to manage projects, apply constraints, automate compilation, perform timing analysis, and generate reports for efficient FPGA design.
	Intel Quartus Prime Pro Edition Software Quick-Start Guide A quick-start guide for Intel Quartus Prime Pro Edition Software, detailing the steps for creating, constraining, compiling, performing timing analysis, and configuring a design on an Intel FPGA device.
	Intel Quartus Prime Standard Edition User Guide: Third-party Simulation A comprehensive guide for simulating Intel FPGA designs using third-party EDA tools. This document covers setup, simulation flows, and specific guidelines for popular simulators like ModelSim, QuestaSim, Synopsys VCS, Cadence Incisive Enterprise, and Aldec Active-HDL.