STM32H5 Power Controller
Hello, and welcome to this presentation of the STM32H5 power controller. The STM32H5's power management functions and all power modes will also be covered in this presentation.
Power Supplies and Domains
The STM32H5 devices feature multiple independent power supplies, allowing for flexible voltage configuration. These include:
- VDDA: The analog power supply, typically for ADC, DAC, COMP, and OPAMP.
- VDDUSB: An independent supply for USB transceivers.
- VDDIO2: An independent I/O supply for specific I/O pins.
- VDD: The main power supply for most I/Os, flash memory, reset block, temperature sensor, internal clock sources, and standby circuitry.
- VBAT: Powers the backup domain, including RTC, backup registers, and backup SRAM, typically when VDD is absent.
- VCORE: Supplies the core, SRAMs, and digital peripherals.
The STM32H503 primarily uses integrated regulators, while STM32H56X and STM32H57X offer either an embedded LDO or an SMPS step-down converter for VCORE supply.
| Power supplies | STM32H503 | STM32H562/573/563 |
|---|---|---|
| VDD = 1.71 V to 3.6 V | VDD is provided externally through the VDD pins | VDD is provided externally through the VDD pins |
| VDDA = 1.62 V (ADCs, COMP) to 3.6 V 1.8 V (DAC) to 3.6 V 2.0V (OPAMP) to 3.6 V 2.1V (VREFBUF) to 3.6 V | VDDA is independent from the VDD voltage and must be connected to VDD when these peripherals are not used | VDDA is independent from the VDD voltage and must be connected to VDD when these peripherals are not used |
| VDDIO2 = 1.08 V to 3.6 V | VDDIO2 is the external power supply for: 9 I/Os (PA8, PA9, PA15, PB3:8) | VDDIO2 is the external power supply for: 10 I/Os (PD6, PD7, PG9:14, PB8, PB9) The VDDIO2 voltage level is independent from the VDD voltage and must preferably be connected to VDD when those pins are not used |
| VDDUSB = 3.0 V to 3.6 V | NA | VDDUSB is the external independent power supply for USB transceivers. |
| VBAT = 1.2 V to 3.6 V | VBAT is the power supply when VDD is not present through power switch for RTC (real-time clock), external clock 32 kHz oscillator, backup registers and optionally backup SRAM | |
Embedded Voltage Regulator
The Low Dropout (LDO) linear voltage regulator is enabled on power-on reset. To supply the VCORE from an external source, the regulator can be disabled by setting the BYPASS bit in the PWR_SCCR register. In bypass mode, internal voltage scaling is not managed, and the external voltage must be consistent with the target frequency. Some STM32H5 MCUs embed two internal regulators (LDO and SMPS) for VCORE supply, exclusively enabled by hardware based on package configuration.
Power Supply Supervision
The following units monitor the power supplies:
- Power-On-Reset (POR) and Power-Down-Reset (PDR): Ensure proper startup operation without external circuits.
- Brownout Reset (BOR): Triggers a reset if VDD power drops below a specified threshold.
- Programmable Voltage Detector (PVD): Monitors VDD power supply against a software-programmable threshold. Can also monitor PVD_IN pin.
- Analog Voltage Detector (AVD): Monitors VDDA supply against a software-programmable threshold.
- VDDIO2 Voltage Monitor (IO2VM): Ensures VDDIO2 is within its functional supply range.
- Temperature Monitor: Monitors junction temperature against fixed thresholds (TEMPhigh, TEMPlow).
- VBAT Domain Voltage Monitor: Monitors battery voltage in VBAT mode against fixed thresholds (VBAThigh, VBATlow).
Dynamic Voltage Scaling (DVFS)
The STM32H5 MCUs support Dynamic Voltage and Frequency Scaling (DVFS) to optimize power consumption in Run mode. This technique exploits the relationship between power consumption, operational frequency, and operational voltage.
The voltage from the main regulator supplying VCORE can be adjusted according to the system's maximum operating frequency. Both regulators (LDO or SMPS) can provide different voltage levels for scaling.
| Voltage scaling Range | Vcore | Max frequency |
|---|---|---|
| VOS0 | 1.35 V | 250 MHz |
| VOS1 | 1.2 V | 200 MHz |
| VOS2 | 1.1 V | 150 MHz |
| VOS3 | 1.0V | 100 MHz |
The main regulator operates in these ranges, allowing optimization of power consumption when the system operates below its maximum frequency.
Low-Power Modes
Several low-power modes are available to save power when the CPU is not actively needed, such as when waiting for an external event.
| Power mode | Description |
|---|---|
| RUN | Provides full power to VCORE domain. Regulator output voltage can be software-scaled. VOS scaling optimizes power consumption when clocked below maximum frequency. |
| SLEEP | CPU clock off, peripherals (including Cortex-M33 core, NVIC, SysTick) can run and wake up CPU on interrupt/event. I/O pins retain state. Software controls peripheral clock gating. |
| STOP | Retains SRAM and registers. Core domain clocks stopped. LSE/LSI and RTC can remain active. Unused RAMs can be shut off. Wakeup via EXTI or peripheral events. |
| STANDBY | Regulator OFF, VCORE domains powered down. Lowest power consumption. SRAM/register contents lost (except Backup domain/Standby circuitry). RTC can remain active. BOR always active. |
| VBAT | Only VBAT domain powered. RTC, backup registers, anti-tamper circuits active. |
I/O State Retention During Standby Mode
In Standby mode, I/Os are by default in a floating state. The IORETEN bit in the PWR_IORETR register controls I/O retention. When enabled, the I/O output state is sampled and retained using pull-up or pull-down resistors.
| PWR_IORETR[IORETEN] | Description |
|---|---|
| 0 | IO Retention mode is disabled. |
| 1 | IO Retention mode is enabled for all I/Os except those supporting standby functionality and debug probe related I/Os (PA13, PA14, PA15, PB4). When entering standby mode, the output is sampled and applied to the output I/O during standby power mode. |
The state of I/Os is applied to the pin via pull-up and pull-down resistors, which remain applied after Standby wakeup until the IORETEN bit is cleared by software.
Timing Diagrams:
- IO Retention Disabled: On entering STANDBY, GPIOs transition to a floating state until a wakeup event occurs.
- IO Retention Enabled: On entering STANDBY, GPIO state is retained until a wakeup event occurs, after which software clears the IORETEN control bit.
Low-Power Mode Monitoring Pins
CSLEEP and CSTOP signals are available as device pin alternate functions to help debug and track transitions between RUN, SLEEP, and STOP modes.
| CSLEEP | CSTOP | MCU power modes |
|---|---|---|
| 0 | 0 | Run mode |
| 1 | 0 | Sleep mode |
| 1 | 1 | Stop mode |
Note: CSLEEP and CSTOP are generated in the VCORE domain and are not driven in Standby mode.
VBAT Mode
The backup power domain includes the RTC (clocked by 32.768 kHz LSE oscillator), tamper pins, backup registers, the RCC_BDCR register, and backup SRAM. An automatic internal switch manages the power source between VBAT and VDD. The switch is controlled by the power-down reset embedded in the Reset block. The RTC is functional in VBAT mode when clocked by the LSE. VBAT charging is possible through an internal resistance when VDD is present, but this is automatically disabled in VBAT mode.
PWR Interrupts
The PWR module generates interrupt requests for events detected by the Programmable Voltage Detector (PVD) or the Analog Voltage Detector (AVD). These interrupts are connected to the EXTI module and can report power drops in VDD or VDDA, also causing automatic exit from SLEEP and STOP modes.
| Interrupt vector | Interrupt event | Event flag | Enable control bit | Interrupt clear method | Exit Sleep, Stop modes | Exit and Standby modes |
|---|---|---|---|---|---|---|
| PVD/AVD output | Programmable voltage detector through EXTI line 16 | PVDO/AVDO | EXTI line 16 enabled | Write EXTI PIF16 = 1 | Yes | No |
Option Bytes
Two bits in the flash option bytes can be configured to prohibit specific low-power modes. When cleared, these bits trigger a reset upon entering Standby (nRST_STDBY) or Stop (nRST_STOP) modes. This serves as a security feature to prevent unintentional entry into these modes.
PWR TrustZone Security
TrustZone security, activated by the TZEN option byte, allows securing various PWR features through the PWR_SECCFGR register. These include low-power modes, wake-up pins, voltage detection and monitoring, VBAT mode, and I/O retention configuration. Other PWR configurations, such as system clock selection and voltage scaling (VOS), can also be secured. When TrustZone security is disabled, registers are generally non-secure.
