AN13202: EMC Design Recommendation on i.MXRT Series
Rev. 0 -- 03/2021
1 Introduction
Electromagnetic Compatibility (EMC) plays an important role in the contemporary product performance, serving as the prime reliability factor for electronic equipment. Poor design can lead to significant issues, making EMC a critical consideration from the initial design stages. This document provides recommendations for effective EMC design using the i.MXRT series, helping users ensure robust EMC performance in their products.
2 Overview
2.1 Basic knowledge of EMC theory
Electromagnetic interference (EMI) is a major challenge in modern electronic systems. Designers must address it early in the design process to prevent schedule delays caused by EMC problems. Achieving electromagnetic compatibility requires sufficient EMC knowledge and good implementation practices throughout all design phases. A basic EMI model comprises an EMI source, a coupling path, and a receptor, as illustrated in Figure 1.
Figure 1. EMI elements depicts a system with an EMI source, a coupling path, and a victim. It shows that reducing noise from the EMI source, altering the coupling path, and improving the receptor's immunity can eliminate EMI issues.
Reducing noise from the EMI source may involve:
- Reducing loop areas from the noise source.
- Using slower rising and falling edge repetition signals.
- Reducing driving signal strength.
- Adding filtering.
- Shielding noise source circuitry.
- Controlling driving signal strength.
- Implementing filtering circuits.
Eliminating coupling paths may involve:
- Moving the victim component further from the noise source.
- Avoiding PCB trace coupling and power domain coupling between the receptor and noise source.
Increasing the victim's immunity may involve:
- Reducing loop areas of PCB traces related to the victim.
- Providing low impedance return paths and reference power planes for signal traces related to the victim.
2.2 Basic rules for EMC design
To effectively meet immunity (susceptibility) and emission requirements, the following guidelines can help designers mitigate potential redesign risks.
- While susceptibility requirements vary across electronic systems, Radiated Immunity (RI) and Electrostatic Discharge (ESD) tests are generally consistent in modern electronic systems.
- During RI testing, the Equipment Under Test (EUT) is exposed to high energy and very high frequencies, potentially affecting its circuit components. The fundamental design approach is to shield sensitive components, such as microcontrollers, from signal and power lines within a specified spectrum range (e.g., 10 - 900 MHz).
- ESD generates short-duration, high-energy pulses (e.g., DC - 300 MHz) that can be introduced into the EUT, potentially damaging sensitive components. The basic design strategy is to prevent sensitive circuits from being affected by ESD high-frequency components. Therefore, systems should provide high impedance relative to chassis ground on signal and power lines to prevent ESD current and energy from reaching sensitive components.
- For emissions, the EUT must ensure it does not produce electromagnetic emissions that affect other equipment. Generally, many basic design techniques used for RI and ESD can also address emission issues. The primary approach is to eliminate high-frequency interference voltage and current generation within the EUT.
Basic techniques, such as component selection and PCB layout, as detailed in the document 'Designing for Board Level Electromagnetic Compatibility' (AN2321), can be applied to both immunity and emission aspects.
3 Schematic design
The following circuits are critical for EMC/EMI/ESD performance:
- Crystal circuit
- Reset circuit
- Unused pins disposition
- Board-to-board interfaces
- Communication interfaces
- Power topology
This chapter details these design aspects, using a concentrator board based on the i.MX RT1060 processor as an example to illustrate design rules.
3.1 Crystal circuit
For the i.MXRT series, an external 24 MHz crystal is required for the primary clock reference. External clock sources, such as active oscillators, are also acceptable. External oscillators generally offer better ESD performance than crystals. Experimental results indicate that systems using an oscillator as a reference show an improvement of approximately 2 KV ESD performance compared to using a crystal.
While using an internal clock as a reference can improve EMC performance, for the RT10XX series, the internal clock does not support PLL reference clock functionality. Any component supporting this feature would be considered an EMC improvement.
3.2 Reset circuit
The chip features a System Reset Controller (SRC) that manages various reset signals. The external reset signal is routed to the SRC via the POR_B pin. A voltage supervisor IC is recommended to control POR_B, providing a reliable reset signal and monitoring the power supply for low-voltage detection, which helps prevent potential EMC issues. To mitigate noise interference in poor EMC conditions, a RC circuit should be placed close to the POR_B pins to decouple noise and enhance EMC performance. Figure 2 illustrates a reference POR circuit.
Figure 2. Chip POR circuit shows a schematic for a chip's Power-On Reset (POR) circuit. It indicates that if the POR_B signal is driven by multiple sources, either the supervisor IC's output must be open-drain, or an inverse diode must be connected to the supervisor IC's output if it has a push-pull output. The POR_B signal resides in the processor's SNVS power domain and requires a pull-up to the SNVS power supply.
3.3 Unused pins
Unused pins can negatively impact EMC performance by increasing power consumption. The status of related GPIOs may change under poor EMC conditions. For instance, a pin with High-Z impedance input might frequently switch states in a poor EMC environment, leading to increased power consumption and other EMC issues.
Avoid connecting unused pins directly to GND, as this can alter GPIO configuration registers under poor EMC conditions. If the output is high in such a scenario, significant current can flow, potentially damaging the pin.
Generally, datasheets provide recommendations for unused pin connections. Adhere to the following guidelines:
- Consult the datasheet to determine if unused pins are permitted to be floating.
- If a pin can be left floating, configure it as a GPIO and set its output to 0 or 1.
- If a pin cannot be left floating, it is advisable to pull it down to GND using a resistor, typically 10 kΩ.
3.4 Board-to-board interfaces
When designing board-to-board connections, examine signal loops. Large signal/power loops can lead to poor EMC performance and introduce EMC issues. Figure 3 illustrates a problematic example.
Figure 3. Example of board to board connection shows a system with two boards: a power board and a processor control board. The AC signal originates from the power board and travels to the processor control board. The signal loop, involving a high impedance path from VDDA through an operational amplifier (U28) to AGND, is long, leading to increased noise coupling into the processor.
Two solutions are proposed to shorten signal loops, as depicted in Figure 3:
- Relocate PT1 to the processor control board. This significantly shortens the input signal loop for amplification, improving EMC performance, with Direct Contact Discharge immunity increasing from 4 KV to 8 KV.
- Move the operational amplifier circuit to the power board and connect VDDA and AGND to the power board. This creates a small loop involving the ADC signal, VDDA, and AGND, thereby enhancing EMC performance.
For processor I/Os directly connected to a connector, incorporating a TVS component for ESD protection is recommended. An alternative, low-cost solution involves adding RC components, as shown in Figure 4. For R/C values, consider the I/O operating frequency and set the RC time constant to be significantly shorter than the signal period.
Figure 4. Example of IO interface shows a basic schematic for an I/O interface. If high-speed signals or clock signals are present in a board-to-board interface, long signal loops and significant harmonic energy can cause EMI issues. To mitigate signal loop and harmonic energy, place GND signals close to high-speed signals and reserve serial resistors on the board. If signals support software-controlled drive strength, reduce the drive strength to minimize harmonic energy.
3.5 Communication interfaces
To improve EMI and ESD performance for communication interfaces, implement the following actions:
- Connect TVS diodes to all signals going to or from connectors for transient voltage suppression.
- Install a ferrite bead between the connector's power supplies and the board's power supplies to isolate high-frequency noise.
- Connect a common-mode choke between pairs of differential signals to suppress high-frequency common-mode noise.
- Install parallel RC or ferrite bead components between the connector's metal shield and the board's GND.
3.5.1 USB
Implement the following solutions to enhance USB EMC performance:
- TVS arrays are recommended for ESD protection on VBUS, D+, D-, and ID pins.
- To improve EMI performance, connect a common-mode choke to the USB signal.
- Ferrite beads on power pins (VBUS, GND) help isolate high-frequency noise.
- For improved ESD performance, use RC or ferrite beads to isolate the USB shield and board GND.
Figure 5 presents an example circuit used in the i.MXRT1060 concentrator board.
Figure 5. USB circuit displays a schematic diagram for USB connectivity, illustrating the implementation of ESD protection and noise filtering components for USB interfaces.
3.5.2 Ethernet
For Ethernet design, the following recommendations are provided from an EMC perspective:
- Utilize TVS arrays for ESD protection on TXP, TXN, RXP, and RXN signals.
- Employ ferrite beads to isolate high-frequency noise originating from the transformer.
- To enhance ESD performance, use RC or ferrite beads to isolate the Ethernet shield and board GND.
Figure 6 shows an example circuit used in the i.MXRT1060 concentrator board.
Figure 6. Ethernet circuit illustrates a typical Ethernet interface schematic, highlighting components for ESD protection and noise isolation.
3.5.3 JTAG
JTAG is a common interface for debugging during the development phase. It is sensitive to poor electromagnetic environments and can easily encounter issues. It is recommended to reserve a 0-ohm serial resistor on JTAG signals during development and remove these resistors to disconnect JTAG signals in production.
3.6 Sensitive signals impacted by ground bounce
The i.MXRT series features multiple power domains, including SEMC, SD0, SD1, NVCC_GPIO, and others. It supports various parallel protocol interfaces like SDRAM, LCD, and CSI. These parallel interfaces operate by changing multiple I/Os' logic states simultaneously (from 1 to 0 or 0 to 1). This rapid switching causes frequent charging and discharging of parasitic capacitors and inductors, leading to ringing on the ground plane and DC supply rail. This phenomenon can affect sensitive signals, particularly those sharing power domains with these parallel interfaces.
For instance, the General Purpose Timer (GPT) module offers a capture feature. Two GPT capture pins, GPIO_EMC_40 and GPIO_EMC_41, are sensitive to edge transitions. If a ground issue occurs due to SDRAM operation, these pins might experience false triggers, especially since pins GPIO_EMC_00 to GPIO_EMC_39 are in the same power domain and are significantly impacted.
To prevent this issue, follow these suggestions:
- To avoid or reduce ground bounce, adhere to the layout recommendations for high-speed signals provided in the 'Layout design' section.
- Avoid assigning sensitive signals to the same power domain as parallel interfaces.
- To avoid or reduce ground bounce, incorporate external RC circuits for sensitive signals.
3.7 Power supply topology
The power supply topology should be planned at the outset of the design process. This includes selecting power components, determining voltages for each power rail, and defining the power sequence. A power diagram for schematic design provides a clear overview of the entire power supply architecture.
4 Layout design
4.1 Power supply routing and grounding
4.1.1 PCB stack-up
Given the high-speed signal interfaces present in i.MXRT series designs, such as SEMC, Octal SPI, and LCD, a PCB layout utilizing at least a 4-layer stack-up is strongly recommended. The advantages of a 4-layer stack-up design include:
- Effective use of ground and power planes as references for controlled impedance lines supporting high-speed and differential signals.
- Shorter signal current return loops and reduced ground-power impedance provided by ground and power planes.
- A larger current return loop acts as a larger loop antenna, directly influencing noise generation. Shortening this antenna can mitigate EMI interference and improve EMC performance.
Figure 7 illustrates an example of a 4-layer stack-up design.
Figure 7. PCB stack-up shows a diagram detailing the layers of a 4-layer PCB, including component side, ground plane, power plane, and solder side, along with material properties like thickness and dielectric constant.
Figure 8. Impedance control in signal layer presents a table detailing impedance requirements for single-ended and differential traces across different layers, specifying trace width, spacing, and impedance values.
4.1.2 Power and ground plane
In multi-layer board layout design, assign independent power and ground planes to reduce their impedance. The '20-H rule' serves as a guideline for multi-layer board design with power and ground planes. This rule suggests expanding the ground plane beyond the power plane by 20 times the distance between the planes to minimize fringing field radiation at the board edges.
- Incorporate numerous ground vias within a complete, continuous, and solid plane for power and ground.
- Enlarge the plane areas and strategically place connecting vias. This helps achieve lower impedance for power and ground planes, facilitating low-impedance return loops for signal return currents.
- Avoid routing traces across reference planes.
4.2 Placement
When placing components on a PCB layout, consider the following points. Before component placement, group circuits by function, such as power supply, analog circuits, digital circuits, and high-speed interface connectors. These functional groups should be placed in separate areas of the PCB.
- Position the power supply circuit near the board's power supply input. Arrange components from high voltage to low voltage circuits.
- Place decoupling capacitors for DC/DC or LDO voltage regulators as close as possible to their input and output ports.
- Analog circuits are more sensitive than digital circuits. Place analog circuits away from high-voltage and high-speed digital circuits to reduce noise coupling paths.
- Ensure adequate clearance between high-speed interface connectors and sensitive components.
- Pay close attention to RF, AD/DA, and analog sensor circuits, as they are particularly sensitive to noise.
- Place the crystal oscillator as close as possible to the MCU pins and surround it with a ground plane. Maintain a safe distance from other sensitive components.
4.3 Bypass and decoupling
Position small decoupling capacitors and larger bulk capacitors close to the MCU power pins. Current should first pass through the capacitor before reaching the power pin. For BGA packages, place decoupling and bulk capacitors as close as possible to the power balls. This is crucial for minimizing parasitic inductance and supporting the high-speed transient current demands of the processor.
NOTE: For the current return path of decoupling and bypass capacitors, ensure it is as short as possible.
Refer to Figure 9 for guidance on decoupling capacitor routing.
Figure 9. Decoupling and bypass capacitors placement and return current loop shows a PCB layout example illustrating the placement of decoupling capacitors and the associated return current loop.
4.4 DCDC circuit
The internal DC/DC converters in the i.MXRT family typically provide one or two outputs for the core platform supply, operating at a switching frequency of approximately 1.5 MHz. The DC/DC converters require external inductors and capacitors. Consult the hardware design guide for component selection.
To achieve good EMC performance, the following layout considerations are critical for DC/DC circuits:
- Keep the DC/DC current loop as small as possible to minimize EMI issues.
- Ensure current first passes through filter capacitors before reaching the pins.
- Avoid unnecessary vias between the inductor and bulk capacitors.
Figure 10 provides a reference for routing traces from the RT1062 DCDC_LP. It shows direct routing to the L7 (4.7 µH) inductor without vias, followed by current passage through C41 and C42. The grounds of C41 and C42 are directly connected to the RT1062 DCDC GND, establishing a short return path with minimal impedance.
Figure 10. DCDC layout on i.MXRT1062 displays a PCB layout example for a DC/DC converter on an i.MXRT1062, highlighting optimal routing and component placement.
4.5 Crystal oscillator circuit
There are two types of crystal oscillator circuits on a PCB: crystal oscillators and external oscillators. The crystal is connected between the XTALIN and XTALOUT pins of the MCU. The crystal/oscillator serves as both a noise source and a sensitive victim, requiring careful protection and routing. Experienced routing methods are highly recommended:
- The trace routing between the crystal and the XTALIN/XTALOUT pins should be as short as possible, with both traces having equivalent lengths.
- Place load capacitors and feedback resistors near the crystal to minimize the impact of parasitic parameters.
- Ensure isolation with the GROUND plane between the crystal and other circuit components.
- Maintain a solid GND plane directly beneath the crystal-associated components and traces.
- Avoid routing signal traces across the area under the crystal and under the plane.
- Improving the oscillator's drive strength can enhance EMS performance but may increase power consumption and EMI influence.
- External oscillators may offer better EMS performance than crystals.
4.6 High speed signal
The following recommendations apply to routing high-speed signals:
NOTE: To ensure effective communication with devices, consider propagation delay and impedance control.
- High-speed signals (e.g., SDRAM, RMII, RGMII, USB, Display, Hyper flash, SD card) must not cross gaps in the reference plane.
- Avoid creating slots, voids, or splits in reference planes.
- Provide ground return vias within 100 mils of signal layer-transition vias when transitioning between different reference ground planes.
- Clocks or strobes on the same layer require at least 2.5 times spacing from adjacent traces (measured as 2.5 times the height from the reference plane) to reduce crosstalk.
- Match the lengths of data, address, clock, and CMD traces (length delta depends on bus rates), ensuring the same number of vias are used.
Figure 11 shows an example of SDRAM routing.
Figure 11. High speed signal trace between RT1060 MCU and SDRAM displays a PCB layout example illustrating the routing of high-speed signals between an RT1060 MCU and SDRAM.
4.7 Shield connection
Jacks that are metal or have conductive housings, exposed externally or touchable, require careful ESD immunity design considerations. For example, USB and Ethernet jacks have specific basic design rules:
- Provide a separate shield (Ethernet/USB) chassis ground beneath the jack.
- Connect the chassis ground to the rest of the PCB GND using RC or ferrite beads. The location and value selection are critical for EMC and EMI performance.
- Keep the chassis ground return loop as small as possible and avoid routing it across key signals or components, such as the microcontroller.
Figure 12 provides an example of shield connection.
Figure 12. Shield connection example illustrates a typical shield connection setup. It shows routing the shield GND through an RC circuit or ferrite bead to the power supply GND, rather than directly connecting it to the board's digital GND. This approach helps prevent noise interference from the digital GND and protects sensitive signals.
4.8 Isolation
Isolation is frequently employed in designs to separate strong and weak power sources or different power domains. This document uses an RS485 circuit from an i.MXRT1060 concentrator board as an example to demonstrate layout considerations. An optical isolator IC is used to isolate the RS485 receiver from the system MCU I/O. To enhance isolation performance, an isolation gap is implemented under the RS485 receiver across all planes (Top, Power, GND, Bottom).
Figure 13 shows an example of an RS485 circuit with an isolation gap.
Figure 13. RS485 IO isolation gap displays a PCB layout example demonstrating an isolation gap for RS485 I/O.
4.9 Signal return path
An electrical circuit forms a closed loop between the source and the terminal device. While signal return loops are frequently discussed, power loops are equally important. Both signal and power circuits have their own current return loops. The ground plane typically serves as the reference plane for signals and power, and the power plane can also act as a reference for signals. Smaller loop areas and impedances result in less crosstalk and Electromagnetic Interference (EMI).
Figure 14 illustrates a DC-DC regulator circuit. Decoupling capacitors are placed close to the input/output ports, and the return current loops back from the top layer to minimize loop impedance.
Figure 14. DC-DC current return loop path shows a diagram illustrating the current and return current paths in a DC-DC converter circuit, emphasizing the importance of minimizing loop area.
When considering the signal return path, avoid creating slots within the current return loop path. Remember that a smaller area for the current return loop leads to better performance in EMC design.
5 Software design
Software offers a viable method to enhance EMC performance and system robustness without incurring additional costs. Key considerations for the i.MXRT series are detailed below:
5.1 Location of code running
The i.MXRT series supports code execution from:
- XIP (Execute-In-Place) flash, such as QSPI flash interfaces with FlexSPI modules.
- Internal SRAM.
- External RAM, such as SDRAM.
Internal SRAM generally provides better performance compared to external SRAM and XIP flash. Code running from external memory is more susceptible to noise. To improve performance, place code in internal SRAM.
5.2 Filter setting for some peripherals
Several peripherals support digital filters to mitigate noise interference. These include LPI2C, FlexCAN, ENC, and tamper pins in the i.MXRT series. This feature filters input noise based on specified periods. Figure 15 illustrates the digital filter functionality.
Figure 15. Digital filter working shows a diagram illustrating how a digital filter operates. Noise can be filtered by configuring the glitch filter width according to the application. Enabling the filter configuration improves EMC performance. For example, the i.MXRT1060 concentrator board failed an EFT test at 4 KV with LPI2C, but passed at 4.5 KV after enabling the LPI2C glitch filter.
5.3 IO drive strength
Electromagnetic Interference (EMI) issues are often caused by high-speed clocks or fast I/O switching. Fast I/O switching, particularly on high-speed interfaces, generates significant high-frequency harmonic energy, which can easily lead to EMI problems. To reduce harmonic impact, a series resistor can be used to slow down I/O edges and minimize overshoot and undershoot.
Fortunately, the i.MXRT series allows for software configuration of I/O drive strength, offering a cost-effective and user-friendly software solution that yields similar results. When EMI issues arise during production, analyzing harmonics and reducing the related I/O drive strength can help resolve them.
For instance, on the RT1060 EMC concentrator board, harmonics were detected at multiples of 50 MHz. By changing the ENET REF_CLK pad setting from 0x31 to 0x21 to lower the drive strength, noise at these frequencies was reduced.
5.4 Clock spread spectrum
The system PLL serves as the clock source for internal system buses, processing logic, SDRAM interfaces, and NAND/NOR interface modules. The high operating frequencies of the system PLL and peripherals are primary sources of electromagnetic emission. Figure 16 shows narrow-band signals with concentrated signal strength.
Figure 16. Narrow-band signals displays a graph of power versus frequency for a narrow-band signal, showing concentrated energy.
To reduce signal concentration, a spread-spectrum technique is employed. This method disperses the clock's energy across a wider bandwidth, thereby reducing the peak amplitude of electromagnetic energy, as illustrated in Figure 17.
Figure 17. Spread spectrum signals displays a graph of power versus frequency for a spread-spectrum signal, showing dispersed energy over a wider frequency range.
The i.MXRT series offers spread spectrum support for its system PLL. If peripherals utilize this PLL as their clock source, enabling this feature can reduce EMI impact. For detailed instructions, refer to the document 'How to Enable Spread Spectrum for RT Family' (AN12879).
On the RT1060 concentrator board, enabling the spread spectrum feature on the system PLL resulted in an improvement of approximately 5 dBm, as shown in Figure 18.
Figure 18. Comparison of spread spectrum function presents two graphs comparing the spread spectrum function. The top graph shows test results with the spread spectrum disabled, indicating higher noise levels. The bottom graph shows results with the spread spectrum enabled, demonstrating a reduction in noise levels and compliance with CISPR 22 Class B limits.
6 EMC test
This section evaluates the board-level and system-level EMC performance of the RT1062 board, using the MIMXRT1062 concentrator board as an example, based on IEC61000-4-2 and IEC61000-4-4 standards.
6.1 Introduction
Figure 19 shows the block diagram of the concentrator board based on the RT1060.
Figure 19. Block diagram of concentrate board illustrates the functional blocks of the i.MX RT1062, showing its various peripherals and interfaces, including power supply, JTAG/SWD, LEDs, LCD, GPRS, Infrared, AC Sample, RTC, GPIO, Ethernet, USB, SDRAM, and QSPI Flash.
The following functions were supported during the test:
- 4-layer board
- AC220 input, with an AC-DC power board serving as the DC supply for the concentrator board.
- i.MXRT1062 operating at 600 MHz.
- QSPI flash operating at 133 MHz, SDRAM operating at 166 MHz.
- Periodic data transmission/reception and communication checks via RS485-1/2/3 interfaces.
- Ethernet PHY loop-back for communication checks.
- RTC sampling time information via I2C interface.
- ADC sampling of AC signals periodically.
- LCD support with a resolution of 320 × 480.
- Seven LEDs for status indication.
6.2 EMC test results
Table 2. EMC test results summarizes the outcomes of EMC testing.
| EMC test standard | Descriptions | Test results | Test conditions | Comments |
|---|---|---|---|---|
| IEC61000-4-4 (EFT) | EFT test | 4.5 KV | Board level | — |
| IEC61000-4-2 (ESD) | Indirect Contact Discharge (X & Y) | 12 KV | Board level, 30-35% RH | Using external oscillator |
| IEC61000-4-2 (ESD) | Direct contact discharge | 8 KV | Board level, 30-35% RH | — |
| IEC61000-4-4 (EFT) | EFT test | 4.5 KV | System level | — |
| IEC61000-4-2 (ESD) | Indirect Contact Discharge (X & Y) | 12 KV | System level, 30-35% RH | — |
| IEC61000-4-2 (ESD) | Air discharge | 15 KV | System level, 30-35% RH | — |
7 Conclusion
This document has presented common methods for achieving good EMC performance with the i.MXRT series, using the i.MXRT1060 concentrator board as a practical example. By following the guidelines and references provided in this document, customers can save time and resources in designing robust products.
8 Reference
- i.MX RT1060 Crossover Processors for Industrial Products (document IMXRT1060IEC)
- i.MX RT1060 Processor Reference Manual (document IMXRT1060RM)
- Designing for Board Level Electromagnetic Compatibility (document AN2321)
- Transmission Line Effects in PCB Applications (document AN1051)
- Improving Transient Immunity for uC (document AN2764)
- Pad Layout Application Note (document AN3747)
9 Revision history
| Revision number | Date | Substantive changes |
|---|---|---|
| 0 | 03/2021 | Initial release |
