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vishay.com/doc?73257Si7615ADN MOSFETs | Vishay
Instructions for VISHAY models including: Si7615ADN-T1-GE3, Si7615ADN, Si7615ADN P-Channel 20 V D-S Mosfet, P-Channel 20 V D-S Mosfet, 20 V D-S Mosfet, Mosfet
SI7615ADN-T1-GE3 - РАДИОМАГ РКС КОМПОНЕНТЫ Manufacturer: Vishay Trans MOSFET P-CH 20V 35A 8-Pin PowerPAK 1212 T/R
SI7615ADN-T1-GE3 - Ð ÐÐÐÐÐÐÐ Ð ÐС ÐÐÐÐÐÐÐÐТЫ
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Si7615ADN
Vishay Siliconix
P-Channel 20 V (D-S) MOSFET
PowerPAK® 1212-8 Single
D D8 D7 D6 5
3.3 mm
1 Top View
3.3 mm
PRODUCT SUMMARY
VDS (V) RDS(on) max. () at VGS = -10 V RDS(on) max. () at VGS = -4.5 V RDS(on) max. () at VGS = -2.5 V Qg typ. (nC) ID (A) a Configuration
1 2S 3S 4S G Bottom View
-20 0.0044 0.0060 0.0098
59 -35 Single
FEATURES
· TrenchFET® Gen III p-channel power MOSFET
· 100 % Rg and UIS tested · Material categorization:
For definitions of compliance please see www.vishay.com/doc?99912
APPLICATIONS · Adaptor switch · Battery switch · Load switch
S G
D P-Channel MOSFET
ORDERING INFORMATION
Package Lead (Pb)-free and halogen-free
PowerPAK 1212-8 Si7615ADN-T1-GE3
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
Drain-source voltage Gate-source voltage
Continuous drain current (TJ = 150 °C)
Pulsed drain current (t = 300 s) Continuous source-drain diode current Avalanche current Single pulse avalanche energy
Maximum power dissipation
Operating junction and storage temperature range Soldering recommendations (peak temperature) d, e
TC = 25 °C TC = 70 °C TA = 25 °C TA = 70 °C
TC = 25 °C TA = 25 °C
L = 0.1 mH
TC = 25 °C TC = 70 °C TA = 25 °C TA = 70 °C
VDS VGS
ID
IDM IS IAS EAS
PD
TJ, Tstg
LIMIT
-20 ± 12 -35 a -35 a -22.1 b, c -17.6 b, c -80 -35 a -3.3 b, c -20 20 52 33 3.7 b, c 2.4 b, c -55 to +150 260
UNIT V
A
mJ W °C
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYPICAL
MAXIMUM
UNIT
Maximum junction-to-ambient b, f Maximum junction-to-case (drain)
t 10 s
RthJA
26
Steady state
RthJC
1.9
33 °C/W
2.4
Notes
a. Package limited b. Surface mounted on 1" x 1" FR4 board c. t = 10 s d. See solder profile (www.vishay.com/doc?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components f. Maximum under steady state conditions is 81 °C/W
S12-2733-Rev. B, 12-Nov-12
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Si7615ADN
Vishay Siliconix
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
Static
Drain-source breakdown voltage VDS temperature coefficient VGS(th) temperature coefficient Gate-source threshold voltage Gate-source leakage
Zero gate voltage drain current On-state drain current a
Drain-source on-state resistance a
Forward transconductance a Dynamic b
VDS VDS/TJ VGS(th)/TJ VGS(th)
IGSS IDSS ID(on)
RDS(on)
gfs
VGS = 0 V, ID = -250 A
ID = -250 A
VDS = VGS, ID = -250 A VDS = 0 V, VGS = ± 12 V VDS = -20 V, VGS = 0 V VDS = -20 V, VGS = 0 V, TJ = 55 °C VDS -5 V, VGS = -10 V VGS = -10 V, ID = -20 A VGS = -4.5 V, ID = -15 A VGS = -2.5 V, ID = -10 A VDS = -10 V, ID = -20 A
-20
-
-
V
-
-14
-
mV/°C
-
3
-
-0.4
-
-1.5
V
-
-
± 100
nA
-
-
-1
A
-
-
-10
-30
-
-
A
-
0.0035 0.0044
-
0.0047 0.0060
-
0.0077 0.0098
-
82
-
S
Input capacitance
Ciss
-
5590
-
Output capacitance
Coss
VDS = -10 V, VGS = 0 V, f = 1 MHz
-
640
-
pF
Reverse transfer capacitance
Crss
-
655
-
Total gate charge Gate-source charge
Qg
VDS = -10 V, VGS = -10 V, ID = -10 A
-
Qgs
VDS = -10 V, VGS = -4.5 V, ID = -10 A
-
122
183
59
93
nC
9.1
-
Gate-drain charge
Qgd
-
14.2
-
Gate resistance
Rg
f = 1 MHz
0.4
2.2
4
Turn-on delay time
td(on)
-
41
70
Rise time Turn-off delay time
tr
VDD = -10 V, RL = 1
-
td(off)
ID -10 A, VGEN = -4.5 V, Rg = 1
-
40
70
75
130
Fall time Turn-on delay time
tf td(on)
-
26
50
ns
-
13
25
Rise time Turn-off delay time
tr
VDD = -10 V, RL = 1
-
td(off)
ID -10 A, VGEN = -10 V, Rg = 1
-
12
24
85
150
Fall time
tf
-
13
26
Drain-Source Body Diode Characteristics
Continuous source-drain diode current
IS
Pulse diode forward current
ISM
Body diode voltage
VSD
Body diode reverse recovery time
trr
Body diode reverse recovery charge
Qrr
Reverse recovery fall time
ta
Reverse recovery rise time
tb
TC = 25 °C
IS = -4 A, VGS = 0 V
IF = -10 A, di/dt = 100 A/s, TJ = 25 °C
-
-
-35
A
-
-
-80
-
-0.72
-1.1
V
-
27
50
ns
-
11
20
nC
-
10
-
ns
-
17
-
Notes a. Pulse test; pulse width300 s, duty cycle 2 % b. Guaranteed by design, not subject to production testing
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
S12-2733-Rev. B, 12-Nov-12
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Document Number: 62667
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
80
80
VGS = 10 V thru 3 V
64
64
Si7615ADN
Vishay Siliconix
ID - Drain Current (A)
ID - Drain Current (A)
48 VGS = 2 V
32
16
0 0.0
VGS = 1 V
0.5
1.0
1.5
2.0
2.5
VDS - Drain-to-Source Voltage (V)
Output Characteristics
48
32 TC = 25 °C
16 TC = 125 °C
TC = - 55 °C 0
0.0
0.8
1.6
2.4
3.2
4.0
VGS - Gate-to-Source Voltage (V)
Transfer Characteristics
RDS(on) - On-Resistance ()
0.020
0.016
0.012
0.008
VGS = 2.5 V
0.004
VGS = 4.5 V VGS = 10 V
0.000 0
16
32
48
64
80
ID - Drain Current (A)
On-Resistance vs. Drain Current and Gate Voltage
C - Capacitance (pF)
8000
Ciss 6400
4800
3200
1600
Coss
Crss
0
0
4
8
12
16
20
VDS - Drain-to-Source Voltage (V)
Capacitance
VGS - Gate-to-Source Voltage (V)
10 ID = 10 A
8 VDS = 10 V
6 VDS = 5 V
4
2
VDS = 15 V
0
0
25
50
75
100
125
Qg - Total Gate Charge (nC)
Gate Charge
RDS(on) - On-Resistance (Normalized)
1.6
ID = 20 A 1.4
VGS = 10 V
1.2 VGS = 2.5 V
1.0
0.8
0.6 - 50 - 25
0 25 50 75 100 125 150 TJ - Junction Temperature (°C)
On-Resistance vs. Junction Temperature
S12-2733-Rev. B, 12-Nov-12
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Document Number: 62667
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www.vishay.com TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Si7615ADN
Vishay Siliconix
100
10 TJ = 150 °C
1
TJ = 25 °C
0.020 0.016 0.012
ID = 20 A
RDS(on) - On-Resistance ()
IS - Source Current (A)
0.1
0.01
0.001
0.0
0.2
0.4
0.6
0.8
1.0
1.2
VSD - Source-to-Drain Voltage (V)
Source-Drain Diode Forward Voltage
0.008 0.004
TJ = 125 °C TJ = 25 °C
0.000 0
2
4
6
8
10
VGS - Gate-to-Source Voltage (V)
On-Resistance vs. Gate-to-Source Voltage
VGS(th) (V)
0.20
0.40 0.60
ID = 250 A
0.80 1.00
ID = 1 mA
1.20 - 50 - 25
0 25 50 75 100 125 150 TJ - Junction Temperature (°C)
Threshold Voltage
Power (W)
100
80
60
40
20
0
0.001
0.01
0.1
1
10
Time (s)
Single Pulse Power, Junction-to-Ambient
ID - Drain Current (A)
100 IDM Limited
10 ID Limited
100 s 1 ms
1 Limited by RDS(on)*
10 ms 100 ms
1 s
0.1
10 s
TA = 25 °C Single Pulse
DC BVDSS Limited
0.01
0.01
0.1
1
10
100
VDS - Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area, Junction-to-Ambient
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
100
80
ID - Drain Current (A)
60
40
Limited by Package
20
0
0
25
50
75
100 125 150
TC - Case Temperature (°C)
Current Derating a
Si7615ADN
Vishay Siliconix
65
2.0
52
1.6
Power (W) Power (W)
39
1.2
26
0.8
13
0.4
0
0
25
50
75
100 125 150
TC - Case Temperature (°C)
Power Derating, Junction-to-Case
0.0 0
25
50
75
100 125 150
TA - Ambient Temperature (°C)
Power Derating, Junction-to-Ambient
Note
a. The power dissipation PD is based on TJ max. = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit
S12-2733-Rev. B, 12-Nov-12
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Document Number: 62667
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www.vishay.com TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
1 Duty Cycle = 0.5
Si7615ADN
Vishay Siliconix
Normalized Effective Transient Thermal Impedance
0.1
0.01 0.0001
0.2
0.1 0.05 0.02
Single Pulse
Notes:
PDM
t1
t2 1. Duty Cycle, D =
t1 t2
2. Per Unit Base = RthJA = 81 °C/W
3. TJM - TA = PDMZthJA(t)
4. Surface Mounted
0.001
0.01
0.1
1
10
100
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
1000
1 Duty Cycle = 0.5
0.2
0.1
0.05
0.1
0.02
Single Pulse
Normalized Effective Transient Thermal Impedance
0.01
0.0001
0.001
0.01
0.1
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Case
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?62667.
S12-2733-Rev. B, 12-Nov-12
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Document Number: 62667
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Package Information
Vishay Siliconix
PowerPAK® 1212-8, (Single / Dual)
D5 b
W
1
8
4
5
L1
eM
Z 2
A1
A
2 E1 E
Notes 1. Inch will govern 2 Dimensions exclusive of mold gate burrs 3. Dimensions exclusive of mold flash and cutting burrs
Detail Z
D1 D
H
E2
KL
E4
D4
D2
1 2 3 4
E3 Backside view of single pad
H H
E2
K
E4
D1
L
1 2
D2 D3(2x) D4
3 D2
4
E3 Backside view of dual pad
c
K1 D5
b
DIM.
MIN.
A
0.97
A1
0.00
b
0.23
c
0.23
D
3.20
D1
2.95
D2
1.98
D3
0.48
D4
D5
E
3.20
E1
2.95
E2
1.47
E3
1.75
E4
e
K
K1
0.35
H
0.30
L
0.30
L1
0.06
0°
W
0.15
M
ECN: S16-2667-Rev. M, 09-Jan-17 DWG: 5882
MILLIMETERS NOM. 1.04 0.30 0.28 3.30 3.05 2.11 -
0.47 typ. 2.3 typ.
3.30 3.05 1.60 1.85 0.034 typ. 0.65 BSC 0.86 typ.
0.41 0.43 0.13
0.25 0.125 typ.
MAX. 1.12 0.05 0.41 0.33 3.40 3.15 2.24 0.89
3.40 3.15 1.73 1.98
0.51 0.56 0.20 12° 0.36
MIN. 0.038 0.000 0.009 0.009 0.126 0.116 0.078 0.019
0.126 0.116 0.058 0.069
0.014 0.012 0.012 0.002
0° 0.006
INCHES NOM. 0.041 0.012 0.011 0.130 0.120 0.083 -
0.0185 typ 0.090 typ
0.130 0.120 0.063 0.073 0.013 typ. 0.026 BSC 0.034 typ.
0.016 0.017 0.005
0.010 0.005 typ.
MAX. 0.044 0.002 0.016 0.013 0.134 0.124 0.088 0.035
0.134 0.124 0.068 0.078
0.020 0.022 0.008 12° 0.014
Revison: 09-Jan-17
1
Document Number: 71656
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AN822
Vishay Siliconix
PowerPAK® 1212 Mounting and Thermal Considerations
Johnson Zhao
MOSFETs for switching applications are now available with die on resistances around 1 m and with the capability to handle 85 A. While these die capabilities represent a major advance over what was available just a few years ago, it is important for power MOSFET packaging technology to keep pace. It should be obvious that degradation of a high performance die by the package is undesirable. PowerPAK is a new package technology that addresses these issues. The PowerPAK 1212-8 provides ultra-low thermal impedance in a small package that is ideal for space-constrained applications. In this application note, the PowerPAK 1212-8's construction is described. Following this, mounting information is presented. Finally, thermal and electrical performance is discussed.
THE PowerPAK PACKAGE
The PowerPAK 1212-8 package (Figure 1) is a derivative of PowerPAK SO-8. It utilizes the same packaging technology, maximizing the die area. The bottom of the die attach pad is exposed to provide a direct, low resistance thermal path to the substrate the device is mounted on. The PowerPAK 1212-8 thus translates the benefits of the PowerPAK SO-8 into a smaller package, with the same level of thermal performance. (Please refer to application note "PowerPAK SO-8 Mounting and Thermal Considerations.")
The PowerPAK 1212-8 has a footprint area comparable to TSOP-6. It is over 40 % smaller than standard TSSOP-8. Its die capacity is more than twice the size of the standard TSOP-6's. It has thermal performance an order of magnitude better than the SO-8, and 20 times better than TSSOP-8. Its thermal performance is better than all current SMT packages in the market. It will take the advantage of any PC board heat sink capability. Bringing the junction temperature down also
increases the die efficiency by around 20 % compared with TSSOP-8. For applications where bigger packages are typically required solely for thermal consideration, the PowerPAK 1212-8 is a good option.
Both the single and dual PowerPAK 1212-8 utilize the same pin-outs as the single and dual PowerPAK SO-8. The low 1.05 mm PowerPAK height profile makes both versions an excellent choice for applications with space constraints.
PowerPAK 1212 SINGLE MOUNTING
To take the advantage of the single PowerPAK 1212-8's thermal performance see Application Note 826,
Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs. Click on the PowerPAK 1212-8 single in the index of this document.
In this figure, the drain land pattern is given to make full contact to the drain pad on the PowerPAK package.
This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-toambient thermal resistance. Under specific conditions of board configuration, copper weight, and layer stack, experiments have found that adding copper beyond an area of about 0.3 to 0.5 in2 of will yield little improvement in thermal performance.
Figure 1. PowerPAK 1212 Devices
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PowerPAK 1212 DUAL
To take the advantage of the dual PowerPAK 1212-8's thermal performance, the minimum recommended land pattern can be found in Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs. Click on the PowerPAK 1212-8 dual in the index of this document. The gap between the two drain pads is 10 mils. This matches the spacing of the two drain pads on the PowerPAK 1212-8 dual package. This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-toambient thermal resistance. Under specific conditions of board configuration, copper weight, and layer stack, experiments have found that adding copper beyond an area of about 0.3 to 0.5 in2 of will yield little improvement in thermal performance.
REFLOW SOLDERING
Vishay Siliconix surface-mount packages meet solder reflow reliability requirements. Devices are subjected to solder reflow as a preconditioning test and are then reliability-tested using temperature cycle, bias humidity, HAST, or pressure pot. The solder reflow tempera-
ture profile used, and the temperatures and time duration, are shown in Figures 2 and 3. For the lead (Pb)-free solder profile, see http://www.vishay.com/ doc?73257.
Ramp-Up Rate Temperature at 155 ± 15 °C Temperature Above 180 °C Maximum Temperature Time at Maximum Temperature Ramp-Down Rate
+ 6 °C /Second Maximum 120 Seconds Maximum 70 - 180 Seconds 240 + 5/- 0 °C 20 - 40 Seconds + 6 °C/Second Maximum
Figure 2. Solder Reflow Temperature Profile
140 - 170 °C 3° C/s (max)
210 - 220 °C 3 ° C/s (max)
10 s (max) 183 °C
60 s (min) Pre-Heating Zone
50 s (max) Reflow Zone
Maximum peak temperature at 240 °C is allowed.
4 ° C/s (max)
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Figure 3. Solder Reflow Temperatures and Time Durations
Document Number 71681 03-Mar-06
AN822
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TABLE 1: EQIVALENT STEADY STATE PERFORMANCE
Package Configuration
SO-8 Single Dual
TSSOP-8 Single Dual
TSOP-8 Single Dual
Thermal Resiatance RthJC(C/W)
20
40
52
83
40
90
PPAK 1212 Single Dual
2.4
5.5
PPAK SO-8 Single Dual
1.8
5.5
PowerPAK 1212 49.8 °C
Standard SO-8 85 °C
Standard TSSOP-8 149 °C
TSOP-6
125 °C
2.4 °C/W PC Board at 45 °C
20 °C/W
52 °C/W
Figure 4. Temperature of Devices on a PC Board
40 °C/W
THERMAL PERFORMANCE
Introduction
Spreading Copper
A basic measure of a device's thermal performance is the junction-to-case thermal resistance, Rjc, or the junction to- foot thermal resistance, Rjf. This parameter is measured for the device mounted to an infinite heat sink and is therefore a characterization of the device only, in other words, independent of the properties of the object to which the device is mounted. Table 1 shows a comparison of the PowerPAK 1212-8, PowerPAK SO-8, standard TSSOP-8 and SO-8 equivalent steady state performance.
By minimizing the junction-to-foot thermal resistance, the MOSFET die temperature is very close to the temperature of the PC board. Consider four devices mounted on a PC board with a board temperature of 45 °C (Figure 4).
Suppose each device is dissipating 2 W. Using the junction-to-foot thermal resistance characteristics of the PowerPAK 1212-8 and the other SMT packages, die temperatures are determined to be 49.8 °C for the PowerPAK 1212-8, 85 °C for the standard SO-8, 149 °C for standard TSSOP-8, and 125 °C for TSOP-6. This is a 4.8 °C rise above the board temperature for the PowerPAK 1212-8, and over 40 °C for other SMT packages. A 4.8 °C rise has minimal effect on rDS(ON) whereas a rise of over 40 °C will cause an increase in rDS(ON) as high as 20 %.
Designers add additional copper, spreading copper, to the drain pad to aid in conducting heat from a device. It is helpful to have some information about the thermal performance for a given area of spreading copper.
Figure 5 and Figure 6 show the thermal resistance of a PowerPAK 1212-8 single and dual devices mounted on a 2-in. x 2-in., four-layer FR-4 PC boards. The two internal layers and the backside layer are solid copper. The internal layers were chosen as solid copper to model the large power and ground planes common in many applications. The top layer was cut back to a smaller area and at each step junction-to-ambient thermal resistance measurements were taken. The results indicate that an area above 0.2 to 0.3 square inches of spreading copper gives no additional thermal performance improvement. A subsequent experiment was run where the copper on the back-side was reduced, first to 50 % in stripes to mimic circuit traces, and then totally removed. No significant effect was observed.
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RthJA (°C/W) RthJ A (°C/W)
AN822
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105
Spreading Copper (sq. in.) 95
85
75
65
55
0 % 45
100 %
50 %
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 Figure 5. Spreading Copper - Si7401DN
130
120
Spreading Copper (sq. in.)
110
100
90
80
50 %
100 %
70
60
0 %
50 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Figure 6. Spreading Copper - Junction-to-Ambient Performance
CONCLUSIONS
As a derivative of the PowerPAK SO-8, the PowerPAK 1212-8 uses the same packaging technology and has been shown to have the same level of thermal performance while having a footprint that is more than 40 % smaller than the standard TSSOP-8.
Recommended PowerPAK 1212-8 land patterns are provided to aid in PC board layout for designs using this new package.
The PowerPAK 1212-8 combines small size with attractive thermal characteristics. By minimizing the thermal rise above the board temperature, PowerPAK simplifies thermal design considerations, allows the device to run cooler, keeps rDS(ON) low, and permits the device to handle more current than a same- or larger-size MOSFET die in the standard TSSOP-8 or SO-8 packages.
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Document Number 71681 03-Mar-06
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR PowerPAK® 1212-8 Single
0.016 (0.405)
0.039 (0.990)
0.152 (3.860)
0.068 (1.725)
0.010 (0.255)
0.088 (2.235) 0.094 (2.390)
0.026 (0.660)
Return to Index Return to Index
0.025 (0.635)
0.030 (0.760)
Recommended Minimum Pads Dimensions in Inches/(mm)
APPLICATION NOTE
Document Number: 72597 Revision: 21-Jan-08
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Revision: 01-Jan-2023
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Document Number: 91000