SHARC® Processor System Design and Debugging

SPI Interface

SPI Boot Interface for ADSP-2126x and ADSP-21362/3/4/5/6 Processors

SPI Boot Interface for ADSP-21367/8/9 and ADSP-2137x SHARC Processors

The SHARC processors mentioned above support boot loading from SPI memory devices. When configured for SPI flash boot, these processors can boot-load an application image from SPI memory on the board.

Most commonly used SPI flash devices require a falling edge on the Chip Select (/CS) before executing the first instruction after power-up. For ADSP-2126x and ADSP-21362/3/4/5/6 processors, use a 4.7kΩ resistor to pull up the SPI flash Chip Select. These SHARC processors do not have internal pull-ups on this signal, so they do not transition from logic high to logic low by themselves. Therefore, the SPI flash select should remain low (or undefined) until the processor outputs its first instruction. For designs using ADSP-21367/8/9 and ADSP-2137x processors, this pull-up resistor is not required. This is because these processors have internal pull-up resistors that satisfy the falling edge requirement during SPI flash boot-loading operations. An example of an SPI flash memory device that meets this requirement is STMicroelectronics' MP25P80 serial flash device.

JTAG Design and Boot Issues

Most systems are designed with JTAG connections from the start to allow testing and debugging using a JTAG ICE (In-Circuit Emulator) when the prototype and production units are available. In this case, the JTAG/TRST signal (TAP reset) is driven from the ICE, but when the system operates in standalone mode due to boot operations, or when the ICE is not used, the /TRST signal should be connected to the board ground. If the /TRST signal is not connected to ground, it can cause boot errors or memory access errors during runtime. Furthermore, connecting a pull-down resistor to /TRST is not recommended. This is because the SHARC processor has an internal pull-up resistor on this signal.

For JTAG system design guidelines, refer to "Analog Devices JTAG Emulation Technical Reference (EE-68) [1]".

2-Wire Interface (TWI)

The internal 2-wire interface is an IC-compatible peripheral. Since both SCL and SDA are open-drain outputs, both TWI signals require pull-up resistors as specified by the IC standard (refer to the I²C standard and the data sheets of I²C-compatible devices when selecting pull-up resistor values).

Driving the /RESET Input

When driving the /RESET input signal of the SHARC processor, avoid using RC (Resistor/Capacitor) circuits. Analog Devices recommends using a power-monitor IC that outputs power-on and manual /RESET. A combination of RC circuits and Schmitt trigger level gates can also be used to drive the /RESET input.

Bypass Capacitors

Appropriate bypass capacitors on the internal power supply (VDDINT) are essential for high-speed operation. Unwanted parasitic inductance in the capacitors and traces can degrade high-frequency performance. If the processor operates above 100 MHz, the following two points are necessary: First, the capacitors should be small with short leads to minimize inductance. Surface-mount capacitors in size 0402 are superior to larger sizes. Second, smaller capacitance values raise the resonant frequency of the LC circuit. While several 0.1 uF capacitors are excellent below 50 MHz, a combination of 0.1 uF, 0.01 uF, 0.001 uF, and 100 pF is recommended for VDD_INT in the 500 MHz range.

AVDD Power Filtering

This section applies to ADSP-2116x, ADSP-2126x, and ADSP-21362/3/4/5/6 SHARC processors. The data sheet recommends filtering for the internal PLL. Older revisions of the data sheet recommended using a 10Ω series resistor for noise immunity and PLL stability. This rating has been updated to use a ferrite bead with high impedance (600-1000Ω at 100 MHz). The DC resistance of these types of ferrite beads is less than 1Ω.

Unused Input Signals

Do not leave unused processor inputs floating. Use pull-up or pull-down resistors, depending on the active polarity of the input signal. The recommended resistor values for pull-up and pull-down are 10kΩ and 100Ω, respectively. Inputs that have internal pull-up or pull-down resistors can be left floating. Refer to the device data sheet for inputs that have default pull-up/pull-down resistors. Leaving signals such as bus requests (/BRx) or host bus requests (/HBR) floating can cause boot errors or other problems during application runtime.

SHARC Processor Power-Up

Power up both supplies (VDDINT [core power] and VDDEXT [IO power]) simultaneously. If simultaneous power-up is not possible, ensure that the time difference between stable power supplies does not exceed the data sheet specifications (tIVDDEVDD [from VDDINT to VDDEXT]).

Shared Signals

Be aware that shared signals also have I/O functions. These signals have default functions after power-on with /RESET. Software programming is required to change from the default function to the desired function. From a system design perspective, this can cause signal contention. Some examples are:

• For ADSP-21367/8/9 SHARC processors, the /MS2 and /MS3 strobes are shared with flag pins and interrupt pins. After power-on, these signals are configured as inputs. Therefore, if you use these signals as memory select signals, pull-up resistors are required to avoid contention with external ports. For example, when boot-loading from external flash memory, use /MS1 (Bank 1). If the memory device interfaced to /MS2 or /MS3 misinterprets the logic level of the chip select pin and begins driving the bus, bus contention will occur.
• Another example is the RSTOUT/CLKOUT signal, which is shared with the running reset function on ADSP-2137x SHARC processors (see Figure 1). Upon power-on with /RESET, this signal functions as the RSTOUT signal. You must configure it as an input via software to enable the running reset function. The RSTOUT/CLKOUT signal on ADSP-2137x processors is used for running reset functions and must be driven by the host's open-drain output. At power-up, this signal is configured as an output. This state continues until you configure this signal as an input via software to enable the running reset function. Connecting this signal to the host's active-drain output will cause contention and damage the driver.
• Boot Memory Chip Select: ADSP-2106x and ADSP-2116x SHARC processors have dedicated signals (/BMS [Byte Memory Select]) to drive parallel boot memory devices. For ADSP-2126x and ADSP-21362/3/4/5/6 processors, there are no dedicated boot memory select signals. Therefore, memory select must be driven by the parallel port address driven by the processor. For ADSP-21367/8/9 and ADSP-2137x processors, /MS1 (Memory Bank 1 Select) must be used as the boot memory select signal. Booting is performed from Bank 1. ADSP-21367/8/9 and ADSP-2137x SHARC processors do not have dedicated signals like /BMS.

SDRAM Address Pin Mapping and DQM Signals

The address pin mapping for ADSP-21367/8/9 and ADSP-2137x SHARC processors differs from that of the ADSP-21161 processor. When using 32-bit mode, connect ADDR1 of the ADSP-21367/8/9 and ADSP-2137x processors to ADDR0 of the SDRAM. When using 16-bit mode, connect ADDR0 to ADDR0 of the SDRAM. Unlike the ADSP-21161 processor, ADSP-21367/8/9 and ADSP-2137x processors do not have DQM support. Some SDRAM devices have specific DQM conditions in their power-up sequence. For such SDRAM memory, the DQM signal must be driven via the processor's flag pins during the SDRAM power-up sequence. For details on the SDRAM interface with ADSP-21367/8/9 processors, refer to "Interfacing 133 MHz SDRAM Memory to ADSP-21367 SHARC Processors (EE-286) [2]".

PCG (Peripheral Clock Generator) Settings

This section discusses considerations when generating SHARC SPORT signals using the PCG (Programmable Clock Generator).

When generating signals such as FS (frame synchronization for LRCLK) or SCLK (serial clock) for the SPORT set to I2S mode, you must configure the PCG delay registers to comply with the I2S protocol timing. The LRCLK signal must be driven on the falling edge of the serial clock.

When generating signals for the SPORT set to TDM mode using the PCG, the frame synchronization must remain active for only one bit clock cycle. Note that frame synchronization in TDM mode is level-sensitive, not edge-sensitive. Loading a value of "1" into the PCG pulse width register (PCG_PW) will ensure that the frame synchronization is active for one cycle of the serial clock. With this setting, it does not matter when the SPORT is enabled or re-enabled, as the frame synchronization is active for one cycle of the serial clock. If the SPORT is enabled when the frame synchronization is inactive, it will wait for the next active frame synchronization. For systems requiring a 50% duty cycle in the PCG setting, enable the SPORT using the internal DAI interrupt.

Enabling I2S for IDP (Input Data Port)

When receiving data from external devices using the IDP, there is a sequence that must be followed when enabling the IDP port configured for I2S mode. Failure to follow this sequence can result in channel shifts or swaps.

1. Use the SRU (Signal Routing Unit) to internally connect the frame synchronization to a DAI interrupt.
2. Configure the DAI interrupt for the inactive edge of the frame synchronization.
3. Wait for the DAI interrupt, and then enable the IDP port inside the DAI interrupt service routine.
4. Read the DAI interrupt latch register to clear the DAI interrupt.

This procedure ensures that the IDP port is enabled with the correct timing, avoiding problems such as channel shifts or swaps in the received data.

DAI Interrupts

Unlike other interrupts, DAI interrupts are not automatically cleared within the DAI interrupt service routine. After latching an interrupt, the latch status persists until the DAI interrupt latch register is read. To clear a DAI interrupt, you must read the DAI interrupt latch register. If you do not do this, the interrupt will continue to trigger every time the DAI interrupt service routine is exited.

Disabling Peripherals in DMA Interrupt Service Routines

SHARC processor peripherals support DMA mode for data transfer. A DMA interrupt occurs when the DMA transfer counter counts out. If the peripheral is configured for data reception, the data is received and transferred to internal memory when the DMA counter counts out. If the peripheral is configured for data transmission, the data remains in the peripheral's DMA FIFO even when the DMA counter counts out and generates an interrupt. When attempting to disable the DMA and peripheral within the ISR, you must first poll the DMA FIFO status. Once the FIFO displays an empty status, the peripheral can be safely disabled; otherwise, data may be lost.

Boot Errors

This is reported as a case where the application can be executed when loaded via JTAG ICE, but not when loaded via boot-load. Consider the following points during debugging:

• Check the processor's BOOTCFG pins and ensure they are correctly connected to a valid high or low logic level for digital voltages. If using resistors to provide flexibility for boot mode selection, ensure the correct resistors are implemented. The best approach is to use an oscilloscope to check the voltage levels at the processor pins.
• Ensure the JTAG ICE /TRST signal is connected to the board ground. Do not leave this signal floating. Leaving this signal floating can cause boot errors or memory access errors.
• Ensure you are using the correct boot kernel and generating the loader (.LDR) file. If you are using a modified boot kernel, verify basic boot-load using the default boot kernel provided with VisualDSP++® and the application examples (e.g., flag toggling).
• Ensure you are selecting the correct parameters when generating the .LDR file. Incorrect parameter selection can cause boot errors.
• Check whether the boot-load was performed using an ICE (In-Circuit Emulator). Connect the ICE to the target and start a simulator session in VisualDSP++. Turn on the target and initiate the boot-load. Change the session from "Simulator" to "Emulator" and examine the Disassembly window. This window will indicate whether the application was boot-loaded from an external source. If the expected code does not appear, it indicates a boot error. You can also use this method to check if the processor has downloaded the first 256 instructions.
• Verify that the power-on reset timing is correct as specified in the data sheet.
• Check the CLKCFG signal to ensure the PLL is not over-driven. Verify that the selected ratio, in relation to the CLKIN frequency, does not exceed the core clock for the specified ratio.
• Check boot-related signals such as /BMS (for ADSP-21367/8/9 and ADSP-2137x processors, /MS1), /RD, ADDR, and the data bus. Check that the traces are intact, as board traces can be open or shorted. You can also monitor RSTOUT to check PLL lock.
• Check for bus contention on the external bus during boot-load operations. For example, for ADSP-21367/8/9 and ADSP-2137x processors, external pull-up resistors are required on /MS2 and /MS3 (if used). Otherwise, bus contention may occur during boot-up when memory devices interfaced to /MS2 and /MS3 drive the bus.

Application Crashes

In most cases, this problem is reported as a software crash during application execution. This can manifest as the processor hanging up at an unknown location or the entire application restarting. Causes include:

• The processor may be performing indirect accesses, which could corrupt memory locations defined for heap or stack in the .LDF file. This can corrupt critical data required at runtime, ultimately leading to a software crash. Verify that your application does not perform such memory accesses that cause corruption. You can debug this using the hardware breakpoint feature of VisualDSP++ during runtime. If the processor performs illegal accesses in these areas, you can detect these accesses.
• Check whether the application is performing any harmful/accidental accesses to system registers or IOP registers that cause application hangs or restarts. For example, check if the application is inadvertently setting up a soft reset/reboot anywhere in the code. Check for indirect jumps or calls.
• Board designs with insufficient decoupling/bypass capacitors can exhibit unexpected behavior correlated with the execution of certain code. Verify that the correct decoupling capacitors and bulk capacitors (capacitor type/value and placement are critical) are used for the processor and other devices on the board, and that they supply sufficient switching current/power for system runtime. Heavy core or I/O switching requires significant switching current. If insufficient current is supplied, symptoms such as system shutdown, application crashes, or incorrect execution of specific code may occur.
• It is useful to verify the checksum of the boot-loaded application to ensure that the entire data and code have been downloaded correctly without bit errors. Bit errors can occur in noisy environments. Due to bit errors, the processor may execute illegal instructions or process incorrect data, leading to unexpected behavior.
• Ensure that the length registers (Lx) of the DAG (Data Address Generator) are initialized to zero if they are not used as circular buffers. This issue is not apparent when performing code downloads and execution using ICE. This is because ICE initializes the length registers to zero, so the problem only manifests when the code is boot-loaded and executed in a standalone system.
• Investigate known VisualDSP++ compiler bugs related to specific tool versions (or updates). Compiler bugs can generate incorrect code, leading to unexpected behavior. It is recommended to always use the latest version of VisualDSP++.

The latest VisualDSP++ release notes are available on the Analog Devices website.

https://www.analog.com/processors/sharc/evaluationDevelopment/crosscore/toolsUpgrades/index.html

Release notes for older VisualDSP++ versions are available at:

https://www.analog.com/processors/sharc/evaluationDevelopment/crosscore/toolsUpgrades/archives.html

Data Loss

This is reported as loss of the first few words of data during data reception using SPORT, SPI, or other serial interfaces. In such cases, always ensure that the slave is enabled before enabling the master. The master generates signals like serial clock and frame synchronization, and the slave acquires these signals from the master device.

Data Corruption

This is reported as data corruption when receiving data using SPORT, SPI, link ports, or other serial links. In such cases, verify the integrity of the signals and pay attention to overshoot/undershoot-induced problems and noise spikes caused by crosstalk or other sources. If possible, perform internal loop-back tests to rule out processor functional issues. In infinite loop mode, use an oscilloscope to investigate signal integrity issues. For such cases, it is recommended to use termination (series termination) for serial clocks and frame synchronization. These problems, even when adopting other functional recommendations in the design, may appear as shifts/swaps in the received channels.

VisualDSP++ Portability Issues

These are reported as problems observed when a VisualDSP++ version (or update) is changed. In such cases, check for differences in compilers, known tool issues, or other factors. Turn off code optimization to further narrow down problems related to compiler optimization. It is recommended to use the latest version/update of VisualDSP++ from the start of the project.

Board Design Checklist

• Check the size and placement of decoupling capacitors.
• Check the boot mode selection pins (BOOTCFG).
• Check the core clock rate selection pins (CLKCFG).
• Check JTAG pins configurations. See JTAG Emulation Technical Reference (EE-68) [1].
• Check test points and probe point accessibility. Unused PF pins are very useful for hardware and software debug purposes (for example driving LEDs or probe points). If possible, pin out all DSP signals through vias.
• Check the reset circuitry. Reset should be generated by a reset supervisory IC, not by RC circuitry. RC network use is possible in combination with a Schmitt trigger gate to drive RESET/ of the processor.
• Check power supply ratings and thermal requirements. It is preferable to be able to adjust the core voltage by simply changing a resistor value.
• Check component placement, and avoid long traces.
• Check the processor's data sheet and errata for up-to-date information.

References

1. Analog Devices JTAG Emulation Technical Reference (EE-68), Rev 9, October 2004, Analog Devices, Inc.
2. Interfacing 133 MHz SDRAM Memory to ADSP-21367 SHARC Processors (EE-286), Rev 2, March 2006, Analog Devices, Inc.
3. Managing the Core PLL on ADSP-2136x SHARC Processors (EE-290), Rev 1, June 2006, Analog Devices, Inc.
4. Interfacing Gated Clocks to ADSP-21065L SHARC Processors (EE-244), Rev 1, September 2004, Analog Devices, Inc.
5. Interfacing AD7676 ADCs to ADSP-21065L SHARC Processors (EE-247), Rev 1, October 2004, Analog Devices, Inc.
6. Interfacing AD7676 ADCs to ADSP-21365 SHARC Processors (EE-248), Rev 1, October 2004, Analog Devices, Inc.
7. Hardware Design Checklist for the Blackfin Processors (EE-281), Rev 1, October 2005, Analog Devices, Inc.

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