TSW3003 Demonstration Kit User's Guide

1.1 DAC Component

The TSW3003 Demo Kit is designed for the DAC5687, and is also compatible with the pin-compatible DAC5686. Procedures in this guide are primarily for the DAC5687 but can be adapted for the DAC5686.

1.2 VComm Configuration

The analog quadrature modulator requires a common-mode DC voltage of approximately 3.3V. A DC path from the DAC output to the modulator input is crucial for carrier suppression using the DAC5687's DC-offset adjustment. A passive resistor network maintains the common-mode voltage. The DAC coarse gain should ideally be at its maximum (15) for proper DC levels.

1.3 VCXO

The CDCM7005 requires a VCXO source for its output clock signals. The VCXO frequency can be changed to support different modulation standards. Common VCXO frequency conventions include:

• WCDMA: Derivatives of 61.44 MHz (e.g., 122.88 MHz, 245.76 MHz, 491.52 MHz)
• GSM: Derivatives of 52 MHz (e.g., 104 MHz, 208 MHz)
• CDMA2K: Derivatives of 78.6432 MHz (e.g., 157.2864 MHz, 314.5728 MHz)

1.4 LO Generation

The TRF3761's integrated VCO outputs the RF signal for the analog quadrature modulator's LO drive. The default TRF3761-H has a tuning range from 2028 to 2175 MHz. Other frequency bands may require different TRF3761 variants. The RF frequency band of the VCO must be noted for programming the TRF3761 and measuring the output RF signal. Table 1 shows typical frequency bands of operation.

2.1 System Block Diagram

Figure 1 illustrates the TSW3003 Demo Kit's place within a basic radio transceiver system. The diagram shows the DAC, I/Q Modulator, LPA, TX, ANT, Diplexer, LNA, and RX components, with the TSW3003 Demo Kit components highlighted within a dashed box.

2.2 Demo Kit Block Diagram

Figure 2 presents the Demo Kit's block diagram, highlighting key Texas Instruments components: DAC5687, TRF3703 I/Q Modulator, CDCM7005 Clock Gen, VCXO, and TRF3761 PLL LO Generator.

3.1 CDCM7005

The CDCM7005 is a clock distribution chip used for synchronizing clock outputs. It offers five outputs (LVPECL or LVCMOS) with programmable division ratios (1, 2, 3, 4, 6, 8, 16). The divide-by-16 can be substituted with divide-by-4 or 8 with a 90-degree phase shift.

3.2 DAC5687

The DAC5687 is a 16-bit interpolating dual digital-to-analog converter (DAC). It includes a digital modulator, differential offset control, and I/Q amplitude control, typically used in baseband or low IF modes with an analog quadrature modulator.

3.3 TRF3703

The TRF3703 is a direct upconversion IQ modulator that accepts differential input voltage quadrature signals at baseband or low IF frequencies and outputs a modulated RF signal based on the LO drive frequency.

3.4 TRF3761

The TRF3761 is a family of high-performance, integrated frequency synthesizers optimized for wireless infrastructure. It features an integrated VCO and integer-N PLL, with different family members available for specific VCO frequency ranges.

5.1 CDCM7005 Software

The CDCM7005 serial peripheral interface (SPI) software allows users to load settings into the CDCM7005 registers. These settings must be loaded each time the kit is powered up, as the device defaults to its factory settings. The software interface (shown in Figure 4) allows saving and loading register configurations. It is recommended to tri-state unused output clocks, with OUT_MUX_1 typically used for the DAC5687.

The divider parameters M and N are calculated using the formula: FREF = (FVCXO × M)/(N × P), where P is the VCXO input divider (FB_MUX). Table 2 provides CDCM7005 register values for various VCXO frequencies.

5.2 TRF3761 Software

The TRF3761 software programs the internal PLL to lock the integrated VCO to a desired output frequency. The main menu (Figure 5) allows setting the desired VCO frequency, PFD frequency, reference frequency, and prescaler. The software displays the actual VCO frequency and counter values (R, N, A, B). The 'Send' button applies these settings. For default operation, only the VCO frequency (2028-2175 MHz) may need adjustment. The 'Advanced Operation' button (Figure 6) accesses more detailed register settings.

5.3 DAC5687 Software

This software allows reading and writing control register information to the DAC5687. Upon proper connection and power-up, the GUI (Figure 7) displays default settings. Error messages guide the user if communication fails. The 'Read All' button retrieves current device settings. For normal operation, users select desired values and switches, which are automatically sent to the device and verified.

Register controls include Load/Save/Read/Send Registers and Load Factory Optimization.

5.4 DAC5687 GUI Register Descriptions

This subsection details various configuration controls, DAC gain settings, NCO parameters, and additional control/monitor registers available through the DAC5687 GUI.

• Configuration Controls: Includes options like Full Bypass, FIR Bypass, FIFO Bypass, FIR A/B filters, Dual Clk, Interleave, Inverse Sinc, Half Rate Input, Sif, Inv. PLL Lock, PLL Freq, PLL Kv, Qflag, 2's Comp, Bus Reversal (Rev A/B Bus), USB inversion, Clock Inversion (Inv. Clk I/Q), Synchronization (Sync_Phstr, Sync_cm, Sync_NCO), Phase Clock Divider Select, DAC Serial Data, Counter Mode, DAC Static Data, Alt. PLLLOCK Output, NCO enable, and NCO Gain.
• QMC Settings: Enable QMC, QMCA/B Gain, and QMC Phase adjustments for I/Q phase imbalance.
• Mode Settings: Selects coarse mixer mode and PLL Divider.
• Interpolation: Sets FIR Interpolation factor (X2, X4, X4L, X8).
• Phstr Init. Phase: Adjusts initial phase for FS/2 and FS/4 CMIP blocks.
• Sync FIFO: Selects sync source for FIFO initialization.
• DAC A(B) Gain: Controls DAC Coarse Gain (0-15), DAC Fine Gain (-128 to 127) for I/Q amplitude imbalance, and DAC DCOffset (-4096 to 4095) for carrier suppression.
• Sleep Mode: Puts DAC A(B) to sleep when set.
• NCO: Controls NCO DDS registers, NCO Phase, and calculates required NCO DDS values using F_DAC and NCO IF.
• Additional Control/Monitor Registers: Includes a 'Version' register to check device communication status.

6.1 Jumper Settings

The TSW3003 Demo Kit features onboard jumpers to enable or disable specific devices. The kit is shipped with all devices enabled. Table 3 lists the jumpers, their labels, functions, conditions, and default settings.

(1) VCXO does not have Output Enable control.

6.2 Input/Output Connectors

Table 4 lists the input and output connectors and their descriptions.

7.1 Test Setup Block Diagram

Figure 8 shows the typical test setup for the TSW3003 Demo Kit, illustrating connections between a Power Supply, Pattern Generator, TSW3003 EVM DUT, Spectrum Analyzer, and PC Controller via USB.

7.2 Test Equipment

The following test equipment is recommended for testing the TSW3003 Demo Kit:

• Dual Power Supply (or supplied 6VDC 4A wall supply)
• Spectrum Analyzer (e.g., Rhode & Schwartz FSU, Agilent PSA)
• Pattern Generator (e.g., Agilent 16720A)
• Oscilloscope (e.g., Tektronix 650)
• Digital Voltmeter (e.g., Agilent 34401A)

7.3 Calibration

To accurately record output power, calibrate the insertion loss of the output cable by measuring it from J32 to the spectrum analyzer and setting the analyzer's reference level offset accordingly.

7.4 Test Specifications

Table 5 outlines the typical specifications for the Demo Kit, including CW Tests (Carrier suppression, Sideband rejection), Spurious Output (2nd harmonic, Aliased LSB, Output clock, Aliased USB), and WCDMA ACPR (Channel power, ACPR -Low, ACPR -High).

Figures 9 through 19 provide spectrum analysis plots and ACPR performance data for various WCDMA test modes and carrier configurations.

8.1 Initial Inspection

Inspect the board to identify the devices used, noting the VCXO frequency (U1).

8.2 Engage Power Supplies

Engage the 6-V power supply. Verify current draw is between 0.8 A and 1.3 A for the DAC5687 configuration. Note the status of LEDs D12 and D13.

8.3 Program the CDCM7005

Use the default settings in the CDCM7005 GUI (Section 5.1) to generate a 491.52-MHz clock. Hit the 'Send' button and verify LEDs D12, D13, and D14 are illuminated.

8.4 Program the TRF3761

Use the default settings in the TRF3761 GUI (Section 5.2) to place a carrier at 2.14 GHz. Hit the 'Send' button, verify LED D15 (indicating a locked LO), and monitor the RF output for a single frequency tone. Side tones may be present due to the DAC5687's complex output.

Table 6 lists frequency designations for different VCO bands and modulation standards.

8.5 DAC5687 Program

With the DAC PLL mode disabled (default jumper settings on J31), verify DACA and DACB Coarse Gain is set to 15, and DAC Offsets and fine gains are set to 0. Configure the spectrum analyzer with the specified center frequency, RBW, VBW, Span, Attenuation, and Reference Level.

8.6 Carrier Suppression

Carrier suppression can be tuned by adjusting the DAC5687's DC-offset controls. Figures 20 and 21 show the DAC GUI and the output spectrum before and after adjustments.

8.7 Sideband Rejection

Sideband rejection is achieved by ensuring quadrature signals are 180 degrees out of phase and have equal amplitude. Amplitude and phase imbalances can be compensated using DAC fine gain or QMC gain/phase adjustments. The process involves iterative tuning using markers and step adjustments to minimize sidebands and achieve performance greater than 70 dBc.

9.1 External LO

To configure the board for an external LO, specific modifications are required, including removing certain capacitors, installing others, and disabling the TRF3761 output via jumper settings (Figure 24 and 25).

9.2 External Reference

For external reference configuration, change jumpers JP1-2,3 and JP2-2,3, and connect an external VCXO to J4 (Figure 26).

10.1 Baseband Filter

The TSW3003 Demo Kit layout allows for a 5th order LC filter. By default, it includes a resistive network for attenuation and a two-inductor network to compensate for parasitic board capacitance, providing about 0.5 dB ripple up to ±200 MHz bandwidth.

10.1.1 RF Filter/Output Match

A small 3rd order LC filter can be implemented on the modulator output for filtering or impedance matching, but this filter is disabled by default through shunt element removal.

11.1 Bill of Materials

Table 7 lists the components used in the TSW3003 Demo Kit, including quantities, reference designators, values, PCB footprints, manufacturer names, and part numbers.

Table 7 (continued) lists connectors, jumpers, resistors, and integrated circuits used in the kit.

11.2 Schematics

The schematics for the TSW3003 Demo Kit are provided in the original document, detailing the circuit design for various sections like DAC, Interface Control, CDC, Modulator, VCO, and Power Distribution.