F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Release Notes

Intel FPGA IP Versioning

The Intel® FPGA IP version (X.Y.Z) number can change with each Intel Quartus® Prime software version. A change in:

  • X indicates a major revision of the IP. If you update the Intel Quartus Prime software, you must regenerate the IP.
  • Y indicates the IP includes new features. Regenerate your IP to include these new features.
  • Z indicates the IP includes minor changes. Regenerate your IP to include these changes.

Related Information

  • Introduction to Intel FPGA IP Cores
  • F-Tile PMA and FEC Direct PHY Multirate Intel FPGA IP User Guide
  • F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP v2.0.1

Intel Quartus Prime Pro Edition VersionDescriptionImpact
22.3IP enhancements and bug fixes:
  • Improved System Messages for the number of profiles.
  • Improved Reconfiguration clock source parameter selection.
  • Corrected Number of secondary profiles parameter numbering to start from 1.
  • Added the QSF settings required for the IP.
Regenerate your IP to include these changes.

F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP v2.0.0

Intel Quartus Prime Pro Edition VersionDescriptionImpact
22.2Added support for Reconfiguration group with total bandwidth >100G.
IP enhancements and bug fixes.
Added support for 400G-8, 300G-12, 150G-6, 200G-8 and 200G-4 Reconfigurable groups.
You must regenerate the IP.
Note: Auto upgrade does not work in this release and you must manually upgrade the IP.

F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP v1.0.0

Intel Quartus Prime Pro Edition VersionDescriptionImpact
22.1Initial release.

F-Tile PMA and FEC Direct PHY Multirate Intel FPGA IP User Guide Archives

For the latest and previous versions of this user guide, refer to the F-Tile PMA and FEC Direct PHY Multirate Intel FPGA IP User Guide. If an IP or software version is not listed, the user guide for the previous IP or software version applies.

Models: F-Tile PMA-FEC Direct PHY Multirate Intel FPGA IP, Direct PHY Multirate Intel FPGA IP, PHY Multirate Intel FPGA IP, Multirate Intel FPGA IP, Intel FPGA IP, FPGA IP, IP

File Info : application/pdf, 4 Pages, 84.03KB

727829?fileName=rn-726811-727829

References

Antenna House PDF Output Library 6.6.1359 (Linux64)

Related Documents

Preview Intel FPGA IP User Guide: F-Tile PMA and FEC Direct PHY Multirate
This user guide provides comprehensive details on the F-Tile PMA and FEC Direct PHY Multirate Intel FPGA IP, covering its features, architecture, instantiation steps, and design guidelines for Intel Agilex devices. It details various reconfiguration modes, interface signals, and resource utilization.
Preview Intel FPGA IP User Guide: F-Tile PMA and FEC Direct PHY Multirate
This user guide provides comprehensive details on the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP, covering its features, architecture, instantiation, and design guidelines. It details reconfiguration modes, interface signals, parameters, and resource utilization for Intel Agilex devices.
Preview Multi Channel DMA Intel FPGA IP for PCI Express: Design Example User Guide
Comprehensive user guide for the Multi Channel DMA Intel FPGA IP for PCI Express, detailing design example generation, simulation, compilation, hardware testing, and driver configurations for Intel FPGA platforms.
Preview Ethernet Subsystem Intel® FPGA IP User Guide
This user guide provides comprehensive details on the Intel® Ethernet Subsystem FPGA IP, covering its features, configuration parameters, subsystem blocks, interfaces, and register descriptions for Intel Agilex 7 devices (E-Tile and F-Tile).
Preview F-Tile CPRI PHY Intel FPGA IP Design Example User Guide
User guide detailing the F-Tile CPRI PHY Intel FPGA IP design example, covering generation, simulation, compilation, and hardware testing for Intel Agilex devices. Includes hardware and software requirements, directory structure, simulation procedures, and register details.
Preview Intel F-Tile JESD204C FPGA IP User Guide: Features, Design, and Implementation
This comprehensive user guide from Intel details the F-Tile JESD204C FPGA IP, a high-speed serial interface for DAC and ADC integration with Intel Agilex 7 FPGAs. It covers essential information for designers, including features, architecture, design steps, parameterization, performance metrics, and resource utilization, supporting the JESD204C standard.
Preview Intel Agilex CvP Implementation User Guide: PCIe Configuration for FPGAs
Learn how to configure Intel Agilex FPGAs using the Configuration via Protocol (CvP) scheme over PCIe. This user guide provides detailed implementation steps, design considerations, and driver information for efficient FPGA configuration.
Preview F-Tile Interlaken Intel FPGA IP User Guide
This user guide provides comprehensive information on the F-Tile Interlaken Intel FPGA IP core, detailing its features, installation, parameterization, simulation, and compilation processes. It covers functional descriptions, interface signals, IP registers, and performance metrics for various configurations, including Interleaved Mode, Packet Mode, and Interlaken Look-aside Mode. The guide is updated for Intel Quartus Prime Design Suite 22.1 and IP Version 4.0.0.