HYPERRAM™ Timing Compatibility with JEDEC xSPI (JESD251)
Application Note AN234072
About this document
Scope and purpose
AN234072 discusses the input and output timing compatibility between Infineon's latest high-density, high-performance, 64-Mb/128-Mb HYPERRAM™ and JEDEC xSPI (JESD251). This application note also analyzes the input and output timing parameter mismatch between HYPERRAM™ and JESD251 and provides a workaround to mitigate any incompatibility due to timing mismatch in a system.
1 Introduction
HYPERBUS™ & OCTAL xSPI HYPERRAM™ is a high-performance, 8-bit wide, serial, Self-Refresh DRAM or also called Pseudo-Static Random-Access Memory (PSRAM) introduced by Infineon. HYPERRAM™ follows JEDEC standard Expanded Serial Peripheral Interface (xSPI) (JESD251) protocol and timings. JESD251 specifies two interface profiles: profile-1 is OCTAL xSPI and profile-2 is HYPERBUS™. Both profiles support the 8D-8D-8D signaling standard in which the command, address, and data bytes are transmitted over the 8-bit DQ (IO) bus, in DDR mode. Even though HYPERRAM™ follows the JESD251 standard, there are some parameters/timings differences between the two that may make HYPERRAM™ incompatible with hosts (MCUs/ASICs) which are designed following JESD251 standard.
This application note compares all input and output timing of the 64/128-Mb HYPERRAM™ with JESD251 and analyzes any timing mismatch between them. In addition, this application note also suggests a workaround that can help in resolving any timing mismatch and make the access timing compatible in a system. Since HYPERRAM™ came into existence earlier than JESD251, some spec mismatch in HYPERRAM™ from JESD251 are inevitable. Therefore, analyzing and fixing any timing incompatibility with appropriate timing adjustment is necessary for a reliable system design. This application note doesn't capture all timing parameters and details; therefore, you must refer to the 64-Mb/128-Mb HYPERRAM™ datasheets for additional information.
Even though this application note has exclusively used the timing parameters of the 64-Mb/128-Mb density HYPERRAM™ for comparison, this timing compatibility analysis also applies to higher density HYPERBUS™ and OCTAL xSPI HYPERRAM™ (256Mb and above).
2 HYPERRAM™ vs JESD251 timing
This section provides a comparison between the input and output timings of the 64-Mb/128-Mb HYPERRAM™ and JESD251. Any timing gap either due to a difference in the measurement level and/or the parameter value is highlighted with supporting note and possible system workaround. Read-Write Data Strobe (RWDS) and Dataline (DQ) of HYPERRAM™ are the same as Data Strobe (DS) and Data-line (IO) of JESD251.
2.1 Input timing
Table 1 summarizes HYPERRAM™ and JESD251 input timing comparison at 200MHz clock ([tCK]). Figure 1 and Figure 2 show the input measurement reference for JESD251 and HYPERRAM™. Key voltage reference levels for the input timing measurement are specified as [VT] = [VCC]/2, [VIH]/[VIL] = 70%/30% of [VCC]. JESD251 specifies [VDD] as the IO voltage which is the same as [VCC]/[VCCQ] for HYPERRAM™.
| Parameter | JESD251 Spec | 64Mb/128Mb HYPERRAM™ Datasheet | Unit | |||||
|---|---|---|---|---|---|---|---|---|
| Symbol | Min | Max | Parameter | Symbol | Min | Max | ||
| Clock Input Threshold (AC) | [VT(AC)] | 0.50*[VDD] | 0.50*[VDD] | Not specified [1] | V | |||
| Input Differential Crossing (AC) | [VIX(AC)] | 0.4*[VDD] | 0.6*[VDD] | Input Differential Crossing (AC) | [VIX(AC)] | 0.4*[VCCQ] | 0.6*[VCCQ] | V |
| Cycle Time Data Transfer Mode | [tPERIOD] | 5 | CK Period | [tCK] | 5 | ns | ||
| Slew Rate (CK and Signals) - (1.8V) | [SR] | 1.125 | Minimum Input Rise and Fall Slew Rates (1.8V) | 1.13 | V/ns | |||
| Slew Rate (CK and Signals) - (3V) | [SR] | 2.06 | Minimum Input Rise and Fall Slew Rates (3.0V) | 2.06 | V/ns | |||
| Duty Cycle Distortion | [tCKDCD] | 0 | 0.25 | Not specified [2] | ns | |||
| Minimum Pulse Width | [tCKMPW] | 2.25 | CK Half Period - Duty Cycle | [tCKHP] | 0.45*[tCK] | 0.55 *[tCK] | ns | |
| Input Setup Time, with respect to VIH/VIL | [tISUddr] | 0.5 | Input Setup, with respect to [VT] | [tIS] | 0.5 | ns | ||
| Input Hold Time, with respect to VIH/VIL | [tIHddr] | 0.5 | Input Hold, with respect to [VT] | [tIH] | 0.5 | ns | ||
[1] The input clock (CK) AC input threshold is not specified in the HYPERRAM™ datasheet. However, all input measurement reference for HYPERRAM™ is [VT] of CK, which is identical to the JESD251 measurement reference.
[2] The clock (CK) duty cycle distortion is not specified in the HYPERRAM™ datasheet. However, HYPERRAM™ allows input clock duty cycle variation between 45% to 55% of [tCK] or 0.5[tCK] +/- 5%[tCK] which covers the [tCKDCD] specification of JESD251.
2.1.1 JESD251 input measurement
As per JESD251 spec, the input measurement reference is [VT] of CK to [VIH]/[VIL] of IOs, as highlighted in Figure 1.
Figure 1: JESD251 input timing diagram. This diagram illustrates the input timing for JESD251, showing the clock (CK) signal and the IO signal. Key voltage levels are indicated: [VT] for the clock threshold, and [VIH]/[VIL] for the IO signal. Timing parameters like [tISU] (input setup time) and [tIH] (input hold time) are shown relative to the clock edges and valid data windows.
2.1.2 HYPERRAM™ input measurement
As per the HYPERRAM™ datasheet, the input measurement reference is [VT] of CK to [VT] of DQs, as highlighted in Figure 2.
Figure 2: HYPERRAM™ input timing diagram. This diagram shows the input timing for HYPERRAM™, with the clock (CK) signal and the DQ signal. Key voltage levels are [VT] for both clock and DQ signals. Timing parameters like [tIS] (input setup time) and [tIH] (input hold time) are depicted.
2.1.3 Input timing compatibility analysis
The input measurement reference level for HYPERRAM™ is CK ([VT]) to DQ ([VT]) while it is CK ([VT]) to IO ([VIH]/[VIL]) for JESD251, as highlighted in Figure 1 and Figure 2. This section analyzes the input timing compatibility with respect to both measurement references by translating one reference timing to other and compares both the timings at the same reference.
2.1.3.1 Analyzing with JESD251 input reference ([VT] to [VIH]/[VIL])
If the host drives inputs as per JESD251 reference (HYPERRAM™ write operations), it will end up driving with an extra timing margin for HYPERRAM™. As highlighted in Figure 3, when extrapolating the HYPERRAM™ input timings from its standard [VT] to [VIH]/[VIL], the input timing requirement for the HYPERRAM™ @ [VIH]/[VIL] reduces by [Delta t].
For example: [VCCQ] = 1.8V with [SR]=1.125V/ns for both rising and falling signal calculates [Delta t1]/[Delta t2] = 0.32ns (0.2*1.8/1.125). Hence, HYPERRAM™ input setup ([tIS]) and the input hold ([tIH]) timing requirements at [VIH]/[VIL] reference will become [tIS]/[tIHS] @ [VT] – 0.32 ns or 0.18 ns which is then compared with the host input timing @[VIH]/[VIL] per JESD251 spec, as shown in Table 1.
2.1.3.2 Analyzing with HYPERRAM™ input reference ([VT] to [VT])
If the host drives inputs per HYPERRAM™ reference during the write operation, the host will end up driving with an extra timing margin for HYPERRAM™. As highlighted in Figure 3, when extrapolating the host input timings from its standard [VIH]/[VIL] to [VT], the equivalent input timing driven by the host @ [VT] will increase by [Delta t].
For example: [VCCQ] = 1.8V with [SR]=1.125V/ns for both rising and falling signal calculates [Delta t1]/[Delta t2] = 0.32ns (0.2*1.8/1.125). Hence, the equivalent setup ([tIS]) and hold ([tIH]) timing driven by the host at [VT] will become [tIS]/[tIHS] @ [VOH]/ [VOL] + 0.32 ns or 0.832 ns, which is then compared with HYPERRAM™ input timings at [VT], as shown in Table 1.
2.2 Output timing
Table 2 summarizes HYPERRAM™ and JESD251 output timing comparison at 200MHz [tCK]. Figure 6 and Figure 8 show the output measurement reference for JESD251 and HYPERRAM™. Output high voltage ([VOH]) and output low voltage ([VOL]) levels for the high-speed, 1.8V LVCMOS (JESD8-31) outputs are [VOH] = 75% of [VDD] or 0.75*[VDD]; [VOL] = 25% of [VDD] or 0.25*[VDD].
| Save Data Output | JESD251 spec | 64-Mb/128-Mb HYPERRAM™ datasheet | Unit | |||||
|---|---|---|---|---|---|---|---|---|
| Symbol | Min | Max | Data Output | Symbol | Min | Max | ||
| Cycle Time Data Transfer Mode | [tPERIOD] | 5 | CK Period | [tCK] | 5 | ns | ||
| Duty Cycle Distortion | [tDSDCD] | 0 | 0.2 | Not specified [0] | ns | |||
| Minimum Pulse Width | [tDSMPW] | 2.05 | Not specified [4] | ns | ||||
| Output skew | [tRQ] | 0.4 | RWDS transition to DQ Valid [5] | [tDSS] | -0.4 | 0.4 | ns | |
| Output hold skew | [tRQH] | 0.4 | RWDS transition to DQ Invalid [5] | [tDSH] | -0.4 | 0.4 | ns | |
[0] [tDSDCD] or Duty Cycle Distortion parameter is not measured on HYPERRAM™. This parameter in conjunction with [tCKMPW] can determine the minimum pulse width ([tDSMPW]) of the data strobe (DS/RWDS) output. Therefore, if the [tCKMPW] ([tCKHP]) and [tDSMPW] are specified, [tDSDCD] definition becomes redundant (optional).
[4] [tDSMPW] is not provided in the HYPERRAM™ datasheet. However, characterization of [tDSMPW] on limited HYPERRAM™ samples demonstrate that HYPERRAM™ can support [tDSMPW] = 2.05 ns (typ) and 2.0 ns (min). See Table 3 and Figure 4 for more details.
[5] HYPERRAM™ RWDS and DQs are the same as DS and IO signals of JESD251.
HYPERRAM™ datasheet values for [tDSS] and [tDSH], as shown in Table 2, are specified as per their production testing limits, while their actual measurement on the silicon is much improved. Table 3 summarizes the improved [tDSS]/[tDSH] and new [tDSMPW] of HYPERRAM™. Though these measurements are performed on limited samples they are measured across voltage, temperature, and process corners to guarantee the spec limits. Therefore, users of this application note can take the improved timings, as per new spec limits in Table 3, instead of datasheet timings if they are too tight or create challenge while evaluating the 1.8V, 64Mb/128Mb HYPERRAM™.
| Parameter | Symbol | Min. [6, 8] | Typ [7,8] | Max [6, 8] | Unit |
|---|---|---|---|---|---|
| Read-Write Data Strobe (RWDS) Transition to Data Valid | [tDSS] | -0.3 | - | 0.3 | ns |
| RWDS Transition to Data Invalid | [tDSH] | -0.3 | - | 0.3 | ns |
| RWDS Minimum Pulse Width | [tDSMPW] | 2.0 | 2.05 | - | ns |
[6] Test Conditions: fCK = 200 MHz, VCC/VCCQ = 1.8 V, TA = -40°C to +105°C, all corners.
[7] Test conditions: fCK = 200 MHz, VCC/VCCQ = 1.8 V, TA = -40°C to +105°C, typical corner.
[8] Values are guaranteed by characterization and not 100% tested in production.
Figure 4: HYPERRAM™ output data window & [tDSMPW]. This diagram illustrates the output timing for HYPERRAM™, showing the RWDS signal and the DQ signal. It depicts the data window and the minimum pulse width ([tDSMPW]) for the RWDS signal.
2.2.1 JESD251 output measurement
JESD251 output parameters are measured with capacitive load CL = 6pF as, shown in Figure 5.
Figure 5: JESD251 output load reference. This diagram shows the test setup for measuring JESD251 output parameters, including a device I/O driver, a transmission line (Zo = 50 Ohm, Td = 350 ps), and a measurement point with a reference load (CL = 6pF).
JESD251 output measurement reference is [VT] of DS to [VOH]/[VOL] of IOs, as highlighted in Figure 6.
Figure 6: JESD251 data output timing. This diagram illustrates the data output timing for JESD251, showing the Data Strobe (DS) signal and the IO output. Key voltage levels are [VDD], [VT], [VOH], and [VOL]. Timing parameters like [tRQ] (output skew) and [tRQH] (output hold skew) are shown relative to the DS signal and valid data windows.
2.2.2 HYPERRAM™ Output Measurement
HYPERRAM™ output parameters are measured with capacitive load CL = 15pF, as shown in Figure 7.
Figure 7: HYPERRAM™ output load reference. This diagram shows the test setup for measuring HYPERRAM™ output parameters with a capacitive load (CL = 15pF).
HYPERRAM™ output measurement reference is [VT] of RWDS to [VT] of DQs, as shown in Figure 8.
Figure 8: HYPERRAM™ data output timing. This diagram illustrates the data output timing for HYPERRAM™, showing the RWDS signal and the DQ signal. Key voltage levels are [VCCQ], [VT], [VOH(min)], and [VOL(max)]. Timing parameters like [tDSS] (output skew) and [tDSH] (output hold skew) are shown relative to the RWDS signal.
2.2.3 Output timing compatibility analysis
The output measurement reference for HYPERRAM™ is RWDS ([VT]) to DQ ([VT]) while it is DS ([VT]) to IO ([VOH]/[VOL]) for JESD251, as highlighted in Figure 6 and Figure 8. This section analyzes the output timing compatibility for both references by translating one reference timing to other and compares both the timings at the same reference.
2.2.3.1 Analyzing with JESD251 output reference ([VT] to [VOH]/[VOL])
When shifting the HYPERRAM™ output reference from [VT] to ([VOH]/[VOL]), its new [tDSS]/[tDSH] value at ([VOH]/[VOL]) reference will observe a [Delta t1]/[Delta t2] increase from its standard [VT] reference. The adjusted [tDSS]/[tDSH] for HYPERRAM™ is calculated as: [tDSS]/[tDSH] @ [VT] (0.3ns/0.3ns) + ([Delta t1]/ [Delta t2]) which is then compared against host's [tRQ]/[tRQH] @ ([VOH]/[VOL]), as shown in Table 3.
Figure 9 highlights the [Delta t1]/[Delta t2] change when shifting the HYPERRAM™ output reference from [VT] to ([VOH]/[VOL]).
Figure 9: Output timing comparison JESD251 vs HYPERRAM™. This diagram visually compares the output timing requirements of JESD251 and HYPERRAM™. It highlights the voltage reference differences ([VT] to [VOH]/[VOL] for JESD251, [VT] to [VT] for HYPERRAM™) and the resulting timing shifts ([Delta t1], [Delta t2]) when extrapolating between references.
The value of [Delta t] shift is determined by the HYPERRAM™ output drive strength and the system bus load capacitance. Figure 10 shows the [RC] charging and discharging behavior of an output buffer when it transitions from '0' to '1' ([RC] charging) or from '1' to '0' ([RC] discharging). For a given [RC] network, it takes ~0.7T(1.4T-0.7T) to raise the output from [VT] to [VOH]. While it takes ~0.4*T(0.69T-0.29T) to fall the output from [VOH] to [VT]. T=RC is the time constant of the HYPERRAM™ output circuit.
Figure 10: Output load ([CL]) charging and discharging characteristics. These graphs illustrate the charging and discharging behavior of an output buffer under load. The left graph shows output voltage rising from 0% to 100% of [VCCQ] over time, indicating charging time. The right graph shows output voltage falling from [VOH] to [VT], indicating discharging time. Key points like 0.7T, 1.4T, 0.4T, 0.69T, and 0.29T are marked, representing time constants related to [RC] charging/discharging.
Infineon HYPERRAM™ supports configurable output drive strength whose value can vary from 19 Ω (strongest) up to 115 Ω (weakest) with 34 Ω being the default output impedance. The configurable drive strength in HYPERRAM™ applies to both DQ and RWDS outputs. Table 4 shows the [Delta t] for various HYPERRAM™ output drive strengths with JESD251 reference load, CL = 6pF. HYPERRAM™ adjusted [tDSS]/[tDSH] is calculated as: [tDSS]/[tDSH] @ [VT] (0.3ns/0.3ns) + [Delta t1]/ [Delta t2]; while the host's [tRQ]/[tRQH] will be as per Table 2.
| R (Ω) | CL (pF) | 0.7*T(RC) ([Delta t1]) (ps) | 0.4*T(RC) ([Delta t2]) (ps) | HYPERRAM™ adjusted [tDSS]/[tDSH] with reference (RWDS ([VT]) to DQ ([VOH]/[VOL])) | |||||
|---|---|---|---|---|---|---|---|---|---|
| tDSS (ns) | tDSH (ns) | Min | Max | Min | Max | ||||
| 19 | 6 | 79.8 | 45.6 | -0.380 | +0.380 | -0.346 | +0.346 | ||
| 34 | 6 | 142.8 | 81.6 | -0.443 | +0.443 | -0.382 | +0.382 | ||
Table 5 shows the [Delta t] for various HYPERRAM™ output drive strength with CL = 15pF.
| R (Ω) | CL (pF) | 0.7*T(RC) ([Delta t1]) (ps) | 0.4*T(RC) ([Delta t2]) (ps) | HYPERRAM™ adjusted [tDSS]/[tDSH] with reference (RWDS ([VT]) to DQ ([VOH]/[VOL])) | |||||
|---|---|---|---|---|---|---|---|---|---|
| tDSS (ns) | tDSH (ns) | Min | Max | Min | Max | ||||
| 19 | 15 | 199.5 | 114 | -0.50 | +0.50 | -0.414 | +0.414 | ||
| 34 | 15 | 357 | 204 | -0.657 | +0.657 | -0.504 | -0.504 | ||
-Green text color indicates adjusted new HYPERRAM™ limits are within the host's spec min
-Orange text color indicates adjusted new HYPERRAM™ limits are off by <15% of the host's spec min
-Red text color indicates adjusted new HYPERRAM™ limits are >15% off the host's spec min
2.2.3.2 Analyzing with HYPERRAM™ output reference ([VT] to [VT])
When shifting the host's output reference from ([VOH]/[VOL]) to [VT], its new [tRQ]/[tRQH] spec value at ([VT]) reference will observe [Delta t1]/ [Delta t2] decrease from its standard ([VOH]/[VOL]) reference. The adjusted [tRQ]/[tRQH] for the host will be calculated as: [tRQ]/[tRQH] @ [VOH]/ [VOH] (0.4ns/0.4ns) – ([Delta t1]/ [Delta t2]) which is then compared against HYPERRAM™ [tDSS]/[tDSH] @ [VT], as shown in Table 3.
Figure 9 highlights the [Delta t1]/ [Delta t2] change when shifting the host output timing measurement reference from ([VOH]/[VOL]) to [VT].
Table 6 shows the [Delta t] for various HYPERRAM™ output drive strengths with JESD251 reference load, CL = 6pF.
| R (Ω) | CL (pF) | 0.7*T(RC) ([Delta t1]) (ps) | 0.4*T(RC) ([Delta t2]) (ps) | Host's adjusted [tRQ]/[tRQH] with reference (DS ([VT]) to IO ([VT]) | |||||
|---|---|---|---|---|---|---|---|---|---|
| tRQ (ns) | tRQH (ns) | Min | Max | Min | Max | ||||
| 19 | 6 | 79.8 | 45.6 | -0.320 | +0.320 | -0.354 | +0.354 | ||
| 34 | 6 | 142.8 | 81.6 | -0.257 | +0.257 | -0.318 | +0.318 | ||
Table 7 shows the [Delta t] for various HYPERRAM™ output drive strength with CL = 15pF.
| R (Ω) | CL (pF) | 0.7*T(RC) ([Delta t1]) (ps) | 0.4*T(RC) ([Delta t2]) (ps) | Host's adjusted [tRQ]/[tRQH] with reference (DS ([VT]) to IO ([VT]) | |||||
|---|---|---|---|---|---|---|---|---|---|
| tRQ (ns) | tRQH (ns) | Min | Min | Min | Min | ||||
| 19 | 15 | 199.5 | 114 | -0.20 | +0.20 | -0.286 | +0.286 | ||
| 34 | 15 | 357 | 204 | -0.043 | +0.043 | -0.196 | +0.196 | ||
-Green text color indicates adjusted new limits for the host are within the HYPERRAM™ spec min
-Orange text color indicates adjusted new limits for the host are off by <15% of the HYPERRAM™ spec min
-Red text color indicates adjusted new limits for the host are >15% off the HYPERRAM™ spec min
3 Document References
Datasheets
- [1] 64-Mb HYPERRAM™ self-refresh DRAM with HYPERBUS™ interface
- [2] 128-Mb HYPERRAM™ self-refresh DRAM with HYPERBUS™ interface
- [3] 64-Mb HYPERRAM™ self-refresh DRAM with octal SPI interface
- [4] 128-Mb HYPERRAM™ self-refresh DRAM with octal SPI interface
- [5] 256-Mb HYPERRAM™ self-refresh DRAM with HYPERBUS™ interface
- [6] 512-Mb HYPERRAM™ self-refresh DRAM with HYPERBUS™ interface
- [7] 256-Mb HYPERRAM™ self-refresh DRAM with octal SPI interface
- [8] 512-Mb HYPERRAM™ self-refresh DRAM with octal SPI interface
Application notes
- [9] AN226576 – Getting Started with HYPERRAM™
- [10] AN211622 - HYPERFLASH™ and HYPERRAM™ Layout Guide
- [11] AN218684 - HYPERBUS™ Memory: Guide to Efficient Data Access
Ecosystem
- [12] Chipset Partners
Specifications
- [13] JESD251 - Optional x4 quard I/O with data strobe
- [14] HYPERBUS™ specification
- [15] Expended Serial Peripheral Interface (xSPI) for non-volatile memory devices, version 1.0 JESD251B
- [16] 1.8 V HIGH-SPEED LVCMOS (HS_LVCMOS) interface JESD8-31
Revision history
| Document version | Date of release | Description of changes |
|---|---|---|
| ** | 2022-01-12 | Initial release |
Important Notice
The information contained in this application note is given as a hint for the implementation of the product only and shall in no event be regarded as a description or warranty of a certain functionality, condition or quality of the product. Before implementation of the product, the recipient of this application note must verify any function and other technical information given herein in the real application. Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind (including without limitation warranties of non-infringement of intellectual property rights of any third party) with respect to any and all information given in this application note.
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Edition 2022-01-12
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Document reference: 002-34072 Rev. **
