ADC Driver Reference Design Improving Full-Scale THD Using Negative Supply
This reference design, TIDA-01052, optimizes the ADC front-end signal path for full-scale signal swing without Total Harmonic Distortion (THD) degradation. It explores the benefits of a negative supply rail to provide necessary headroom for ADC driver amplifiers, maintaining signal linearity. The document details design theories, component selection, performance trade-offs between single-ended and differential architectures, and presents schematic, layout, and testing results.
System Overview
System Description
Multi-input systems for data acquisition (DAQ) and automatic testing often require hundreds or thousands of channels, demanding high Signal-to-Noise Ratio (SNR) performance while minimizing power, component count, and cost. The Analog Front-End (AFE) typically includes multiplexers, amplifiers, anti-aliasing filters, and ADC drivers. This reference design focuses on the ADC driver stage, addressing the challenge of achieving true rail-to-rail input and output signal swing amplitudes, which many amplifiers struggle with due to headroom requirements from the negative supply. By generating an additional negative supply rail (e.g., -0.2V), this design ensures signal linearity down to system ground. It evaluates performance trade-offs between single-ended and differential ADC driver architectures.
Key System Level Specifications
| PARAMETER | SPECIFICATIONS | MEASURED |
| Number of channels | Dual Differential | Dual Differential |
| Input type | ±5-V fully differential | ±5-V fully differential |
| Input range | 18 bits | 18 bits |
| Resolution | > 100 dB | 100.89 dB |
| SNR | < -120 dB | -124.40 dB |
| THD | < 1 dB | 0 dB |
| THD degradation at 0-dBFS input signal power | > 15.0 | 16.47 |
| ENOB | < 2.5 W | 2.3 W |
| System power | 120 x 100 mm | 116.59 x 99.82 mm |
| Form factor (L × W) |
Block Diagram
The system block diagram illustrates the integration of various components, including OPA827 buffers, THS4551 or OPA625 drivers, ADS8910B ADCs, and clocking circuitry (LMK61E2, LMK00804B). The power supply chain includes a 24V DC input, with regulators like TPS7A4700 and TPS7A3001 providing necessary positive and negative rails, including the critical -0.2V rail generated by the LM7705.
System Design Theory
Power
The power subsystem requires multiple voltage rails. The input is 24-V DC. The TIDA-01052 specifically highlights the use of the LM7705 negative regulator to supply VEE for amplifiers like OPA625 and THS4551. The system power tree shows distribution to various components including ADC power (AVDD, DVDD), amplifier supplies (±18V, -0.2V), and reference voltages.
-0.2-V Rail Design Theory
To ensure the AFE supports a full voltage swing from 0 to VREF, a small -0.2V rail (VEE) is generated using the LM7705. This is necessary because most amplifiers saturate when their input or output signals approach supply rails, leading to degraded linearity and supply rejection. While rail-to-rail amplifiers improve dynamic range, they may still have output limitations (e.g., 50mV from VEE). For applications requiring linearity down to 0V, this can impact performance. The LM7705 provides a stable -0.23V negative supply, enabling amplifiers to swing closer to zero without saturation. This is achieved via a switched capacitor technique. The ripple from the LM7705 is analyzed and found to be negligible for ADC performance due to amplifier PSRR.
Traditional dual-supply disadvantages include the cost of a second regulator and potential voltage limitation issues with the op amp. The LM7705 offers a single-supply solution, reducing cost and complexity, and its small negative voltage is typically within op amp operating ranges.
Reference Voltage Design Theory
External voltage references are used when internal ADC references are insufficient. These references must be low-drift, low-noise, and accurate. However, broadband noise from references can degrade ADC performance. Buffering the voltage reference with a low-output impedance buffer is crucial to preserve linearity, distortion, and noise performance, especially when driving ADCs with switched capacitors (like SAR ADCs) that create dynamic loads on the reference pin. The REF60xx family provides an integrated buffer suitable for this purpose. The REF6050 is used here, providing a 5V reference voltage suitable for LSB specifications and capable of driving multiple ADCs.
Common-Mode Voltage Design Theory
The common-mode voltage sets the center point for the output signal of driver amplifiers like the THS4551 and OPA625. For full signal swing, this voltage should ideally be half the reference voltage. The OPA376 is used with a resistor divider to achieve this, buffering the resulting voltage. For single-ended OPA625 drivers, the common-mode voltage is applied to the non-inverting terminal, with gain adjustments made via resistor dividers. Decoupling capacitors are used to reduce noise on these rails, and additional components ensure circuit stability.
OPA376 Stability Simulation: TINA-TI simulations show the OPA376 is stable with a phase margin of over 70°, indicating good performance.
OPA827 Buffer
The input stage utilizes two OPA827s as buffers to provide high input impedance and buffer the ±18V input signal. The OPA827 was chosen for its JFET input stage, 36V capability, and good noise performance. Its slew rate (28 V/µs) limits the maximum operating frequency for full-power bandwidth without distortion. Calculations show it can support signals up to 2.52 MHz, though THD degradation may occur above 10 kHz. The OPA827 is a high-bandwidth, 36V op amp suitable for high-performance applications.
OPA827 Stability Simulation: TINA-TI simulations confirm stability with a phase margin exceeding 73°, and a rate of closure below 40 dB/decade.
OPA827 Transient Simulation: Transient simulations show the OPA827 buffer stage responds without ringing and with minimal slew limitation, confirming its stability and expected performance.
THS4551 Driver
The THS4551 is a fully differential amplifier used as an input driver for high-precision ADCs. It conditions the input signal and provides a low-output impedance buffer. A flywheel RC filter is included to attenuate sampling charge injection from the ADC and act as an anti-aliasing filter. Key specifications for the input op amp include rail-to-rail input/output, low noise, high bandwidth, and low power. For DC signals with fast transients, accurate settling within the ADC's acquisition window is critical. The THS4551 is well-suited for these requirements.
An anti-aliasing filter, typically a low-pass RC filter, is essential to remove noise and harmonic content. For DC signals with fast transients, a high-bandwidth filter is used for accurate settling. For AC signals, a lower bandwidth filter limits noise and improves SNR. The filter capacitor (CFLT) helps reduce sampling charge injection and must be at least 15 times the ADC sampling capacitance (e.g., >900 pF for ADS8910B). COG/NPO type capacitors are recommended for their stability.
Series isolation resistors (RFLT) are used to prevent amplifier instability when driving capacitive loads. However, higher RFLT values can increase distortion due to interaction with the ADC's nonlinear input impedance. For the ADS8910B, RFLT is limited to 10 Ω to maintain linearity. The THS4551 is chosen for its ability to interface single-ended sources to differential outputs and its suitability for high-precision DAQ systems.
Dual OPA625 Driver
The OPA625 family is designed for high-precision SAR ADCs (up to 18 bits, 2 MSPS). Its low output impedance, low THD, low noise (2.5 nV/√Hz), and fast settling time make it ideal for driving both ADC inputs and reference inputs. The OPA625 is considered a top 5V ADC driver amplifier.
The dual OPA625 configuration uses a different front-end attenuator driver stage for comparison. The gain is set to 1, with similar stability considerations as the THS4551. The output common-mode voltage for the OPA625 is slightly lower (1.25V) than the THS4551 to compensate for its gain.
Driver Amplifier Comparison
Minimizing noise in the buffer stage is critical for ADC accuracy. Both the dual OPA625 and single THS4551 FDA drivers have advantages and disadvantages regarding system bandwidth, THD, and power consumption. FDA architectures can improve THD by reducing second harmonic distortion (HD2), potentially offering up to 4 dB improvement.
ADS8910B ADC and Conversion Start Sync
Two ADS8910B ADCs are used for analog-to-digital conversion. They follow either the THS4551 or dual OPA625 driver stages. The ADCs are powered by 5V and 3.3V (RVDD and DVDD). Ferrite beads and decoupling capacitors are used for power supply filtering. DECAP pins are handled as per the datasheet. Reference voltage pins are connected to ground, and an analog input for the reference voltage is provided, with options for external references.
SDO pins connect to the PHI connector for analysis. The RVS pin also connects to the PHI connector. The SDI pin connects to the PHI connector's SDI, allowing the FPGA to control the ADC. Both ADCs share the same SDI and reset signals. SCLK is the clock input for the serial interface. The chip-select pin is active low.
Conversion Start Synchronization: A unique approach synchronizes the CONVST signal with the SYSCLK using an inverter and a D flip-flop to ensure data integrity. Onboard clocking is used to minimize jitter introduced by external interfaces like the PHI.
Clocking
The LMK61E2 is used as the internal master clock to minimize jitter. It's an ultra-low jitter PLL oscillator generating reference clocks, configurable for LVPECL, LVDS, or HCSL outputs. It is factory programmed for 156.25 MHz LVPECL output and is programmable via I2C. Its internal power conditioning provides excellent PSRR. The device operates from a 3.3V supply.
The LMK00804B clock distributor takes the LVDS signal from the LMK61E2 and splits it into four synchronized LVCMOS outputs, providing a common buffered clock signal to all clocked devices. It was chosen for its low skew, high performance, and ability to distribute multiple LVCMOS clocks.
Host Interface
The TIDA-01052 supports the PHI platform for system evaluation, communicating with a host PC via USB. The PHI supports ADS8910 multiSPI and I2C EEPROM interfaces. GUI software allows evaluation of AC and DC parameters. The PHI module software was modified to accept an external clock input.
Highlighted Products
OPA827
The OPA827 series offers outstanding DC precision and AC performance with low offset voltage, low drift, low bias current, and low 0.1- to 10-Hz noise. It operates over a wide supply range (±4V to ±18V) and has a 22-MHz gain bandwidth product and 28 V/µs slew rate, making it suitable for 16- to 18-bit mixed-signal systems, filters, and ±10V front-ends. It is used as a signal buffer in this system and is TI's highest bandwidth 36V op amp.
OPA625
The OPAx625 family provides excellent 16-bit and 18-bit SAR ADC driving capabilities with high precision, low THD, and low noise. It features a 16-bit settling time of 280 ns, enabling true 16-bit ENOB. With a 100-µV offset voltage and 120-MHz gain-bandwidth product, it is optimized for high-throughput, high-resolution SAR ADCs. The OPA625 is used in many SAR ADC reference designs and is considered a top 5V ADC driver amplifier.
THS4551
The THS4551 is a fully differential amplifier ideal for high-precision ADCs, offering exceptional DC accuracy, low noise, and robust capacitive load driving. It features a negative rail input for DC-coupled, ground-centered signals and supports emerging 16- to 20-bit SAR input requirements. Its wide-range output common-mode control supports various supply voltages and ADC common-mode input requirements. The THS4551 is commonly used in SAR ADC driver circuits, and this design aims to clarify its benefits compared to using two precision op amps.
ADS8910B
The ADS8910B, ADS8912B, and ADS8914B family are pin-compatible, high-speed, high-precision SAR ADCs with integrated reference buffers and LDOs. They support ±0.5-LSB INL and 102.5-dB SNR. The integrated LDO enables single-supply operation, and the reference buffer supports burst-mode data acquisition. The multiSPI digital interface is compatible with SPI protocols, simplifying layout and firmware. The ADS8910B's 1 MSPS sample rate and integrated reference buffer make it ideal for multichannel simultaneous sampling systems.
LM7705
The LM7705 is a low-noise, -0.23V fixed negative voltage regulator using a switched capacitor technique. It enables low-voltage amplifiers to swing to zero volts, preventing saturation and maintaining signal accuracy. It is selected for its high efficiency, ease of implementation, and low quiescent current, making it suitable for designs requiring true rail-to-rail performance.
REF6050
The REF6000 family of voltage references includes an integrated low-output impedance buffer to drive precision data converters while preserving linearity, distortion, and noise performance. They are suitable for SAR and delta-sigma ADCs. The REF6000 family maintains output voltage within 1 LSB with minimal droop, even during the first conversion. The REF6050 provides a 5V reference voltage and can drive multiple ADCs in parallel.
OPA376
The OPA376 family offers low-noise operational amplifiers with outstanding DC precision and AC performance. Features include rail-to-rail input/output, low offset voltage (25 µV max), low noise (7.5 nV/√Hz), and a 5.5-MHz bandwidth. It is suitable for portable applications and can drive high capacitive loads, making it ideal for buffering common-mode voltages for the THS4551 and OPA625.
LMK61E2
The LMK61E2 is an ultra-low jitter PLLatinum programmable oscillator used as the main system clock generator. It provides fractional-N frequency synthesis and can output LVPECL, LVDS, or HCSL signals. It is factory programmed for 156.25 MHz LVPECL output and is programmable via I2C. Its adjustability, low jitter, low power, and robust supply noise immunity make it suitable for high-performance clock generation.
LMK00804B
The LMK00804B is a low-skew, high-performance clock fan-out buffer that distributes up to four LVCMOS clocks. It takes the LVDS signal from the LMK61E2 and splits it into synchronized LVCMOS outputs, ensuring a common buffered clock signal for all devices. It is chosen for its low additive jitter and ability to provide multiple synchronized outputs.
Getting Started Hardware and Software
Hardware Overview
The TIDA-01052 hardware board is shown, illustrating the placement of key components like OPA827 buffers, THS4551, OPA625s, ADS8910B ADCs, and clocking circuitry. Connectors for PHI and input signals are also visible.
Jumper Configuration
The system offers configurable options via three pin jumpers (J32, J33, J34). Table 3 details their functions and default configurations, such as synchronizing CONVST with SYSCLK or setting the negative rail to GND or -0.2V.
| JUMPER NAME | SHORT PINS 1 AND 2 | SHORT PINS 2 AND 3 | DEFAULT CONFIGURATION |
| J32 | CONVST synched with SYSCLK to ADC (jitter cleaner) | CONVST from PHI connector | Short pins 2 and 3 |
| J33 | CONVST synched with SYSCLK to ADC (jitter cleaner) | CONVST from PHI connector | Short pins 2 and 3 |
| J34 | Negative rail of amps to GND | Negative rail of amps to -0.2 V | Short pins 2 and 3 |
| J5 | Short to load EEPROM | Only a two-pin header | Short |
| J6 | Short to load EEPROM | Only a two-pin header | Short |
| J13 | Short when no input signal present | Only a two-pin header | Short |
| J16 | Short when no input signal present | Only a two-pin header | Short |
| J17 | Short when no input signal present | Only a two-pin header | Short |
| J20 | Short when no input signal present | Only a two-pin header | Short |
PHI Hardware
Before using the PHI connector, short jumpers J5 and J6 and attach the PHI board. The PHI EEPROM must be initialized using the PHI Software Launcher, selecting the ADS8910B, loading, writing, and verifying the EEPROM.
Measuring SNR, THD, SFDR, SINAD, and ENOB
Testing requires a high-quality signal generator with differential output. The Audio Precision AP-2700 series was used, with specifications including 10 to 30 Ω source impedance, < 10 µVRMS maximum noise, 110 dB maximum SNR, and -130 dB maximum THD.
Connect the signal generator to the front-end via SMA cables. Attach the PHI module. Set the generator to a 2-kHz differential output at the desired amplitude. Remove corresponding shorting links from the input. Run the ADS8910B EVM software, configure Spectral Analysis with the desired SCLK frequency and sampling rate, and then capture data to calculate SNR, THD, SFDR, SINAD, and ENOB.
Using Onboard Clocking and Jitter Cleaner
To program the LMK61E2, use the USB2ANY controller. Connect SCL to J3 pin 3, SDA to J3 pin 2, and J3 pin 1 to ground. Use Codeloader software to select the LMK61E2, find its I2C address, set the clocking frequency and LVDS output format, and program the EEPROM.
After programming the LMK61E2, adjust jumpers J32 and J33 to activate the jitter cleaner and synchronization circuitry. In the ADS8910B EVM software, select multiSPI for SDO Mode and INTCLK for Clock Source, ensuring the SCLK frequency matches the LMK61E2's output for accurate measurements.
Testing and Results
Testing and Results
An Audio Precision 2700 series signal generator was used as the signal source. A generic DC power supply provided input voltages (24V, 18.5V, 3.8V, 5.8V). After powering up and connecting the signal, input jumpers are removed, and the PHI module is attached. The ADS8910B EVM GUI is used for spectral analysis to measure SNR, THD, and ENOB.
A 2-kHz sinusoid was used at various amplitudes to demonstrate the benefits of the -0.2V rail when the ADC approaches its 0 to VREF swing. Figures 38-41 show performance improvements with the -0.2V rail compared to using system ground, especially for larger inputs where THD degradation occurs. Table 5 summarizes these results.
Figures 42 and 43 compare THD performance against signal power for OPA625 and THS4551, respectively, with and without the -0.2V rail. The THD performance degrades sooner for the THS4551 due to its voltage headroom requirements compared to the OPA625. The conclusion is that the -0.2V rail mitigates output voltage headroom limitations, enabling true rail-to-rail operation and maintaining signal integrity for large inputs without SNR penalty at low power inputs.
Design Files
Schematics
Schematics are available for download at TIDA-01052.
Bill of Materials
The Bill of Materials (BOM) can be downloaded at TIDA-01052.
PCB Layout Recommendations
The PCB layout requires careful consideration due to its complexity, featuring a split ground plane (analog and digital). Differential input signal traces must be of equal length to prevent propagation loss. Figure 44 shows a layout preview highlighting the split ground plane and signal path.
Layout Prints
Layer plots are available for download at TIDA-01052.
Altium Project
The Altium project files can be downloaded at TIDA-01052.
Gerber Files
Gerber files are available for download at TIDA-01052.
Assembly Drawings
Assembly drawings can be downloaded at TIDA-01052.
Related Documentation
- Texas Instruments, Noise Analysis in Operational Amplifier Circuits, Application Report (SLVA043)
- Texas Instruments, Op Amp Noise Theory and Applications, Excerpted from Op Amps for Everyone (SLOA082)
Trademarks
All trademarks are the property of their respective owners.
About the Authors
ERIC BELJAARS is a systems architect at Texas Instruments, responsible for developing reference design solutions for the industrial segment. He holds a BSEE from The University of Oklahoma.
TARAS DUDAR is a systems design engineer and architect at Texas Instruments, focusing on reference design solutions for the test and measurement industry. He previously designed high-speed analog SOC integrated circuits for data communications and holds an MSEE from Oregon State University.
