SCR 8-Bit Standby Controller

Highlights

• The SCR is an 8-bit microcontroller that can continue to run during the standby mode.
• It is based on the XC800 core, which is compatible with the industry standard 8051 processor.
• The microcontroller has an embedded 8 KB XRAM for program code and data.

SCR Architecture Overview

A block diagram illustrates the SCR's internal structure. It features an XC800 Core, SCU (System Control Unit), SCU8, Boot ROM, RAM, Arbiter, RTC (Real-Time Clock), WDT (Watchdog Timer), T2CCU (Timer/Counter/Capture/Compare Unit), SSC (Serial Synchronous Communication), LIN (Local Interconnect Network), CAN wake-up filter, OCDS (On-Chip Debug Support), ADCOMP (Analog-to-Digital Converter Comparator), and Port Control. These components are interconnected via data and control pathways, including connections to the Interrupt, Reset System, and Clock System modules.

Key Features & Customer Benefits

16-bit General Purpose Timer

The SCR incorporates the 16-bit T2CCU, which provides three timers: Timer 0 and Timer 1.

• Timers support operation as either timers or counters.
• They feature a 16-bit auto-reload mode.
• Counting direction can be selected as up or down.

Additionally, a 6-channel Capture/Compare Unit is integrated:

• It offers 16-bit resolution.
• Includes six compare channels.
• Features four capture channels.

These timers enhance module flexibility by enabling digital signal generation or periodic interrupt generation.

Real Time Clock (RTC)

The SCR includes a Real Time Clock (RTC) peripheral that operates independently of the microcontroller's main state once initiated.

The RTC, supported by an on-chip oscillator, facilitates periodic wake-up functionality during standby mode.

The periodic Wake-up Mode can utilize either a 70 kHz clock or a 100 MHz /DIV clock source.

RTC Block Diagram

The RTC block diagram shows a 9-bit prescaler feeding a 32-bit Real-Time Clock Counter (CNT0-CNT3). This counter is driven by a clock source selected between 100 MHz/DIV (RTCCLKSEL = 1) or 70 kHz (RTCCLKSEL = 0). A 32-bits Comparator compares the counter value against Real-Time Clock Compare/Capture Registers (RTCCR0-RTCCR3). A match condition generates a CFRTC signal, which triggers an Interrupt Request (ECTRC).

Power Saving Modes

The SCR supports flexible Power Saving Modes, configurable through idle mode or clock gating for individual peripherals.

The silicon architecture includes two distinct core domains:

• A "high performance" domain (TriCore™): typically active when the engine is running.
• A "low power" domain (SCR): remains permanently active, providing essential supervising task features.

The high-performance domain can be woken up as needed, for instance, when the vehicle engine starts.

System Integration

The SCR is integrated with several modules within the AURIX™ microcontroller ecosystem:

• Power Management System: Manages transitions between different power domains.
• Interrupt Router: Directs and triggers various interrupt signals.
• Clock Control Unit: Selects and manages the appropriate clock source.
• Reset Control Unit: Ensures the SCR receives and processes reset requests.
• Debug: Features a dedicated debug interface, separate from the main AURIX™ debug interface, enabling parallel debugging of both TriCore™ and SCR.
• Port Pins: Timers within the SCR can generate digital signals outputted through these pins.

System Integration Diagram

A system integration diagram depicts the SCR as a central component. It is interconnected with the Power Management System, Interrupt Router, Clock Control Unit, Debug module, Port Pins, and Reset Control Unit, illustrating the flow of control and data between these functional blocks.

Application Example: RTC with GPIO Read and TriCore™ Wake-up

This application involves the microcontroller performing periodic communication with external components via LIN channels (supporting up to 30 channels).

Communication requests are initiated by detecting a change in the logical state on one of the TX lines.

The system is designed for a response time not exceeding 200 ms, with a system current consumption in this mode limited to 7 mA, adhering to a total microcontroller average current budget of 5 mA.

The standby mode, combined with the available pins (16 pins for high-end devices), effectively meets the specified requirements:

• The periodic wake-up of the TriCore™ cluster in a minimal configuration allows for the acquisition of necessary signals.
• Even though the TriCore™ domain requires higher current, the overall average current consumption remains low because the SCR, with its minimal functionality, is the primary active component most of the time.

Trademarks, Notices, and Warnings

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Publication Details:

Edition 2020-12
Published by Infineon Technologies AG
81726 Munich, Germany
© 2020 Infineon Technologies AG. All Rights Reserved.

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Document Reference: AURIX_Training_2_ 8-Bit_Standby_Controller

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