149-Ball NAND Flash with LPDDR4/LPDDR4X MCP

$Id:, micron-ds-fo.xsl, $

Datasheet

Multichip Packages – Mouser Estonia

• Google Docs
• Google Drive
• Download [pdf]



File Info : application/pdf, 399 Pages, 10.08MB

Document Document

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Features
NAND Flash with Mobile LPDDR4/ LPDDR4X 149-Ball MCP
MT29GZ5A5BPGGA-53AIT.87J, MT29GZ5A5BPGGA-53AAT.87J, MT29GZ5A5BPGGA-046AIT.87J, MT29GZ5A5BPGGA-046AAT.87J

Features
· Micron® NAND Flash and LPDDR4/LPDDR4X components
· RoHS-compliant, "green" package · Separate NAND Flash and LPDDR4/LPDDR4X interfa-
ces · Space-saving multichip package (MCP) · Low-voltage operation · Industrial temperature range: ­40°C to +85°C · Automotive temperature range: ­40°C to +105°C · AEC-Q100
NAND Flash-Specific Features
· Organization ­ Page size x8: 4352 bytes (4096 + 256 bytes) ­ Block size: 64 pages ­ Number of planes: 1
· VCC = 1.70­1.95V; 1.80V nominal
Mobile LPDDR4/LPDDR4X-Specific Features
· Ultra-low-voltage core and I/O power supply ­ VDD1 = 1.70­1.95V; 1.80V nominal ­ VDD2 = 1.06­1.17V; 1.1V nominal ­ VDDQ = 1.06­1.17V; 1.10V nominal or Low VDDQ = 0.57­0.65V; 0.60V nominal
· Frequency range ­ 2133­10 MHz (data rate range: 4266­20 Mb/s/ pin)
· 16n prefetch DDR architecture · 8 internal banks per channel for concurrent opera-
tion · Single-data-rate CMD/ADR entry · Bidirectional/differential data strobe per byte lane

Figure 1: MCP Block Diagram

NAND Flash Power

NAND Flash Device

NAND Flash Interface

LPDRAM Power

LPDRAM Device

LPDRAM Interface

Mobile LPDDR4/LPDDR4X-Specific Features (Continued)
· Programmable READ and WRITE latencies (RL/WL) · Programmable and on-the-fly burst lengths (BL =
16, 32) · Directed per-bank refresh for concurrent bank op-
eration and ease of command scheduling · On-chip temperature sensor to control self refresh
rate · Partial-array self refresh (PASR) · Selectable output drive strength (DS) · Programmable VSS (ODT) termination
Note: 1. For physical part markings, see Part Numbering Information.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

1

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Features

Table 1: Key Timing Parameters

Speed Grade
-53
-046

Clock Rate (MHz)
1866
2133

Data Rate (Mb/s/pin)
3733
4266

WRITE Latency

Set A

Set B

16

30

18

34

READ Latency

DBI Disabled DBI Enabled

32

36

36

40

Table 2: Configuration Addressing
Architecture Die configuration Row addressing Column addressing Number of die Die per rank Ranks per channel1

256 Meg x 16 32 Meg x 16 x 8 banks
32K (A[14:0]) 1K (A[9:0]) 1 1 1

Note: 1. A channel is a complete LPDRAM interface, including command/address and data pins.

Table 3: Part Number References
MCP MT29GZ5A5BPGGA-53AIT.87J, MT29GZ5A5BPGGA-53AAT.87J, MT29GZ5A5BPGGA-046AIT.87J, MT29GZ5A5BPGGA-046AAT.87J

NAND Discrete MT29F4G08

NAND READ ID Parameter MT29F4G08ABBFA 4Gb, x8, 1.8V

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

2

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Features

Part Numbering Information
Micron NAND Flash and LPDRAM devices are available in different configurations and densities. The MCP/PoP part numbering guide is available at www.micron.com/numbering.

Figure 2: Part Number Chart

MT 29GZ 5A 5B P G GA -53 A IT

.87J

Micron Technology
Product Family 29G = LPDDR4 + SLC NAND
NAND Code 5A = 4Gb, x8
LPDDR Code 5B = 4Gb, x16
Operating Voltage Range P = NAND V CC 1.8V; LPDDR4 VDD2 1.1V, VDDQ 0.6V or 1.1V
Chip Count Code G = 1 NAND Flash; 1 LPDRAM

Die Revision Code Production Status
Blank = Production Operating Temperature Range
IT = Industrial (­40°C to +85°C) AT = Automotive (­40°C to +105°C)
Automotive Certification (option) A = Package-level burn-in Blank = Standard
LDRAM Speed Grade -53 = 1866 MHz -046 = 2133 MHz
Package Codes GA = 149-ball BGA, 8.0mm x 9.5mm x 0.8mm
*Z = a null character used as a placeholder.

Device Marking
Due to the size of the package, the Micron-standard part number is not printed on the top of the device. Instead, an abbreviated device mark consisting of a 5-digit alphanumeric code is used. The abbreviated device marks are cross-referenced to the Micron part numbers at the FBGA Part Marking Decoder site: www.micron.com/decoder. To view the location of the abbreviated mark on the device, refer to customer service note CSN-11, "Product Mark/ Label," at www.micron.com/csn.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

3

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Features
Contents
Important Notes and Warnings ....................................................................................................................... 21 MCP General Description ............................................................................................................................... 22 Ball Assignments and Descriptions ................................................................................................................. 23 Device Diagrams ............................................................................................................................................ 26 Package Dimensions ....................................................................................................................................... 27 4Gb: x8, x16 NAND Flash Memory ................................................................................................................... 28
Features ..................................................................................................................................................... 28 General Description ....................................................................................................................................... 29 Architecture ................................................................................................................................................... 30 Device and Array Organization ........................................................................................................................ 31 Asynchronous Interface Bus Operation ........................................................................................................... 34
Asynchronous Enable/Standby ................................................................................................................... 34 Asynchronous Commands .......................................................................................................................... 34 Asynchronous Addresses ............................................................................................................................ 35 Asynchronous Data Input ........................................................................................................................... 36 Asynchronous Data Output ......................................................................................................................... 38 Write Protect# ............................................................................................................................................ 39 Ready/Busy# .............................................................................................................................................. 40 Device Initialization ....................................................................................................................................... 43 Power Cycle Requirements .............................................................................................................................. 44 Command Definitions .................................................................................................................................... 45 Reset Operations ............................................................................................................................................ 47 RESET (FFh) ............................................................................................................................................... 47 Identification Operations ................................................................................................................................ 48 READ ID (90h) ............................................................................................................................................ 48 READ ID Parameter Tables .............................................................................................................................. 49 READ PARAMETER PAGE (ECh) ...................................................................................................................... 51 Parameter Page Data Structure Table ............................................................................................................... 52 READ UNIQUE ID (EDh) ................................................................................................................................ 55 Feature Operations ......................................................................................................................................... 56 SET FEATURES (EFh) .................................................................................................................................. 57 GET FEATURES (EEh) ................................................................................................................................. 57 Status Operations ........................................................................................................................................... 60 READ STATUS (70h) ................................................................................................................................... 61 READ STATUS ENHANCED (78h) ................................................................................................................ 61 Column Address Operations ........................................................................................................................... 63 RANDOM DATA READ (05h-E0h) ................................................................................................................ 63 RANDOM DATA INPUT (85h) ...................................................................................................................... 65 PROGRAM FOR INTERNAL DATA INPUT (85h) ........................................................................................... 66 Read Operations ............................................................................................................................................. 67 READ MODE (00h) ..................................................................................................................................... 68 READ PAGE (00h-30h) ................................................................................................................................ 68 READ PAGE CACHE SEQUENTIAL (31h) ...................................................................................................... 69 READ PAGE CACHE RANDOM (00h-31h) .................................................................................................... 70 READ PAGE CACHE LAST (3Fh) .................................................................................................................. 71 Program Operations ....................................................................................................................................... 72 PROGRAM PAGE (80h-10h) ......................................................................................................................... 72 PROGRAM PAGE CACHE (80h-15h) ............................................................................................................. 73 Erase Operations ............................................................................................................................................ 75 ERASE BLOCK (60h-D0h) ............................................................................................................................ 75

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

4

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Features
Internal Data Move Operations ....................................................................................................................... 76 READ FOR INTERNAL DATA MOVE (00h-35h) ............................................................................................. 76 PROGRAM FOR INTERNAL DATA MOVE (85h­10h) ..................................................................................... 77
Block Lock Feature ......................................................................................................................................... 79 WP# and Block Lock ................................................................................................................................... 79 UNLOCK (23h-24h) .................................................................................................................................... 79 LOCK (2Ah) ................................................................................................................................................ 81 LOCK TIGHT (2Ch) ..................................................................................................................................... 82 BLOCK LOCK READ STATUS (7Ah) .............................................................................................................. 83 PROTECT Command .................................................................................................................................. 85 Protection Command Details ...................................................................................................................... 86 Permanent Block Lock Disable Mode .......................................................................................................... 87
One-Time Programmable (OTP) Operations .................................................................................................... 88 Legacy OTP Commands .............................................................................................................................. 88 OTP DATA PROGRAM (80h-10h) ................................................................................................................. 88 RANDOM DATA INPUT (85h) ...................................................................................................................... 89 OTP DATA PROTECT (80h-10) ..................................................................................................................... 90 OTP DATA READ (00h-30h) ......................................................................................................................... 91
ECC Protection ............................................................................................................................................... 92 Error Management ......................................................................................................................................... 96 Electrical Specifications .................................................................................................................................. 97 Electrical Specifications ­ DC Characteristics and Operating Conditions ........................................................... 99 Electrical Specifications ­ AC Characteristics and Operating Conditions .......................................................... 101 Electrical Specifications ­ Program/Erase Characteristics ................................................................................ 104 Asynchronous Interface Timing Diagrams ...................................................................................................... 105 4Gb: x16 Mobile LPDDR4/LPDDR4X SDRAM .................................................................................................. 115
Features .................................................................................................................................................... 115 General Description ...................................................................................................................................... 116
General Notes ........................................................................................................................................... 116 MR0, MR[6:5], MR8, MR13, MR24 Definition .................................................................................................. 117 LPDDR4 IDD Parameters ................................................................................................................................ 118 LPDDR4X IDD Parameters .............................................................................................................................. 122 Functional Description .................................................................................................................................. 126 Monolithic Device Addressing ........................................................................................................................ 127 Simplified Bus Interface State Diagram ........................................................................................................... 130 Power-Up and Initialization ........................................................................................................................... 131
Voltage Ramp ............................................................................................................................................ 132 Reset Initialization with Stable Power ......................................................................................................... 134 Power-Off Sequence ...................................................................................................................................... 135 Controlled Power-Off ................................................................................................................................. 135 Uncontrolled Power-Off ............................................................................................................................. 135 Mode Registers .............................................................................................................................................. 136 Mode Register Assignments and Definitions ............................................................................................... 136 Commands and Timing ................................................................................................................................. 162 Truth Tables .................................................................................................................................................. 162 ACTIVATE Command .................................................................................................................................... 164 Read and Write Access Modes ........................................................................................................................ 166 Preamble and Postamble ............................................................................................................................... 166 Burst READ Operation ................................................................................................................................... 170 Read Timing .............................................................................................................................................. 172 tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation .................................................................................... 172 tLZ(DQS) and tHZ(DQS) Calculation for ATE (Automatic Test Equipment) ................................................... 173

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

5

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Features
tLZ(DQ) and tHZ(DQ) Calculation for ATE (Automatic Test Equipment) ....................................................... 174 Burst WRITE Operation ................................................................................................................................. 176
Write Timing ............................................................................................................................................. 179 tWPRE Calculation for ATE (Automatic Test Equipment) ............................................................................. 180 tWPST Calculation for ATE (Automatic Test Equipment) .............................................................................. 180 MASK WRITE Operation ................................................................................................................................ 181 Mask Write Timing Constraints for BL16 ..................................................................................................... 183 Data Mask and Data Bus Inversion (DBI [DC]) Function .................................................................................. 185 WRITE and MASKED WRITE Operation DQS Control (WDQS Control) ............................................................ 189 WDQS Control Mode 1 ­ Read-Based Control ............................................................................................. 189 WDQS Control Mode 2 ­ WDQS_On/Off ..................................................................................................... 189 Preamble and Postamble Behavior ................................................................................................................. 193 Preamble, Postamble Behavior in READ-to-READ Operations ..................................................................... 193 READ-to-READ Operations ­ Seamless ....................................................................................................... 194 READ-to-READ Operations ­ Consecutive .................................................................................................. 195 WRITE-to-WRITE Operations ­ Seamless ................................................................................................... 202 WRITE-to-WRITE Operations ­ Consecutive ............................................................................................... 205 PRECHARGE Operation ................................................................................................................................. 209 Burst READ Operation Followed by Precharge ............................................................................................ 209 Burst WRITE Followed by Precharge ........................................................................................................... 210 Auto Precharge .............................................................................................................................................. 211 Burst READ With Auto Precharge ............................................................................................................... 211 Burst WRITE With Auto Precharge .............................................................................................................. 212 RAS Lock Function .................................................................................................................................... 216 Delay Time From WRITE-to-READ with Auto Precharge .............................................................................. 217 REFRESH Command ..................................................................................................................................... 218 Burst READ Operation Followed by Per Bank Refresh .................................................................................. 224 Refresh Requirement ..................................................................................................................................... 225 SELF REFRESH Operation .............................................................................................................................. 226 Self Refresh Entry and Exit ......................................................................................................................... 226 Power-Down Entry and Exit During Self Refresh ......................................................................................... 227 Command Input Timing After Power-Down Exit ......................................................................................... 228 Self Refresh Abort ...................................................................................................................................... 229 MRR, MRW, MPC Commands During tXSR, tRFC ........................................................................................ 229 Power-Down Mode ........................................................................................................................................ 232 Power-Down Entry and Exit ....................................................................................................................... 232 Input Clock Stop and Frequency Change ........................................................................................................ 242 Clock Frequency Change ­ CKE LOW ......................................................................................................... 242 Clock Stop ­ CKE LOW ............................................................................................................................... 242 Clock Frequency Change ­ CKE HIGH ........................................................................................................ 242 Clock Stop ­ CKE HIGH ............................................................................................................................. 243 MODE REGISTER READ Operation ................................................................................................................ 244 MRR After a READ and WRITE Command .................................................................................................. 245 MRR After Power-Down Exit ...................................................................................................................... 247 MODE REGISTER WRITE ............................................................................................................................... 248 Mode Register Write States ......................................................................................................................... 249 VREF Current Generator (VRCG) ..................................................................................................................... 250 VREF Training ................................................................................................................................................. 252 VREF(CA) Training ........................................................................................................................................ 252 VREF(DQ) Training ....................................................................................................................................... 257 Command Bus Training ................................................................................................................................. 262 Command Bus Training Mode .................................................................................................................... 262

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

6

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Features
Training Sequence for Single-Rank Systems ................................................................................................ 263 Training Sequence for Multiple-Rank Systems ............................................................................................ 264 Relation Between CA Input Pin and DQ Output Pin ..................................................................................... 265 Write Leveling ............................................................................................................................................... 269 Mode Register Write-WR Leveling Mode ..................................................................................................... 269 Write Leveling Procedure ........................................................................................................................... 269 Input Clock Frequency Stop and Change .................................................................................................... 270 MULTIPURPOSE Operation ........................................................................................................................... 273 Read DQ Calibration Training ........................................................................................................................ 278 Read DQ Calibration Training Procedure .................................................................................................... 278 Read DQ Calibration Training Example ...................................................................................................... 280 MPC[READ DQ CALIBRATION] After Power-Down Exit ............................................................................... 281 Write Training ............................................................................................................................................... 281 Internal Interval Timer .............................................................................................................................. 287 DQS Interval Oscillator Matching Error ...................................................................................................... 289 OSC Count Readout Time .......................................................................................................................... 290 Thermal Offset .............................................................................................................................................. 292 Temperature Sensor ...................................................................................................................................... 292 ZQ Calibration ............................................................................................................................................... 293 ZQCAL Reset ............................................................................................................................................. 294 Multichannel Considerations ..................................................................................................................... 295 ZQ External Resistor, Tolerance, and Capacitive Loading ............................................................................. 295 Frequency Set Points ..................................................................................................................................... 296 Frequency Set Point Update Timing ........................................................................................................... 297 Pull-Up and Pull-Down Characteristics and Calibration .................................................................................. 301 On-Die Termination for the Command/Address Bus ....................................................................................... 302 ODT Mode Register and ODT State Table .................................................................................................... 302 ODT Mode Register and ODT Characteristics ............................................................................................. 303 ODT for CA Update Time ........................................................................................................................... 304 DQ On-Die Termination ................................................................................................................................ 304 Output Driver and Termination Register Temperature and Voltage Sensitivity .............................................. 306 ODT Mode Register ................................................................................................................................... 307 Asynchronous ODT ................................................................................................................................... 307 DQ ODT During Power-Down and Self Refresh Modes ................................................................................ 309 ODT During Write Leveling Mode .............................................................................................................. 309 Target Row Refresh Mode ............................................................................................................................... 310 TRR Mode Operation ................................................................................................................................. 310 Post-Package Repair ...................................................................................................................................... 312 Failed Row Address Repair ......................................................................................................................... 312 Read Preamble Training ................................................................................................................................. 314 Electrical Specifications ................................................................................................................................. 315 Absolute Maximum Ratings ....................................................................................................................... 315 AC and DC Operating Conditions ................................................................................................................... 315 AC and DC Input Measurement Levels ........................................................................................................... 317 Input Levels for CKE .................................................................................................................................. 317 Input Levels for RESET_n ........................................................................................................................... 317 Differential Input Voltage for CK ................................................................................................................ 317 Peak Voltage Calculation Method ............................................................................................................... 318 Single-Ended Input Voltage for Clock ......................................................................................................... 319 Differential Input Slew Rate Definition for Clock ......................................................................................... 320 Differential Input Cross-Point Voltage ........................................................................................................ 321 Differential Input Voltage for DQS .............................................................................................................. 322

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

7

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Features
Peak Voltage Calculation Method ............................................................................................................... 322 Single-Ended Input Voltage for DQS ........................................................................................................... 323 Differential Input Slew Rate Definition for DQS .......................................................................................... 324 Differential Input Cross-Point Voltage ........................................................................................................ 325 Input Levels for ODT_CA ........................................................................................................................... 326 Output Slew Rate and Overshoot/Undershoot specifications ........................................................................... 326 Single-Ended Output Slew Rate .................................................................................................................. 326 Differential Output Slew Rate ..................................................................................................................... 327 Overshoot and Undershoot Specifications .................................................................................................. 328 Driver Output Timing Reference Load ............................................................................................................ 328 LVSTL I/O System .......................................................................................................................................... 329 Input/Output Capacitance ............................................................................................................................. 330 IDD Specification Parameters and Test Conditions ........................................................................................... 331 IDD Specifications ...................................................................................................................................... 347 AC Timing ..................................................................................................................................................... 349 CA Rx Voltage and Timing .............................................................................................................................. 359 DQ Tx Voltage and Timing ............................................................................................................................. 362 DRAM Data Timing ................................................................................................................................... 362 DQ Rx Voltage and Timing ............................................................................................................................. 363 Clock Specification ........................................................................................................................................ 366 tCK(abs), tCH(abs), and tCL(abs) ................................................................................................................ 367 Clock Period Jitter .......................................................................................................................................... 367 Clock Period Jitter Effects on Core Timing Parameters ................................................................................. 367 Cycle Time Derating for Core Timing Parameters ........................................................................................ 368 Clock Cycle Derating for Core Timing Parameters ....................................................................................... 368 Clock Jitter Effects on Command/Address Timing Parameters ..................................................................... 368 Clock Jitter Effects on READ Timing Parameters .......................................................................................... 368 Clock Jitter Effects on WRITE Timing Parameters ........................................................................................ 369 LPDDR4 1.10V VDDQ ...................................................................................................................................... 370 Power-Up and Initialization - LPDDR4 ....................................................................................................... 370 Mode Register Definition - LPDDR4 ........................................................................................................... 371 Burst READ Operation - LPDDR4 ATE Condition ........................................................................................ 380
tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation ................................................................................ 380 tLZ(DQS) and tHZ(DQS) Calculation for ATE (Automatic Test Equipment) ............................................... 380 tLZ(DQ) and tHZ(DQ) Calculation for ATE (Automatic Test Equipment) ................................................... 382 VREF Specifications - LPDDR4 .................................................................................................................... 384 Internal VREF(CA) Specifications .............................................................................................................. 384 Internal VREF(DQ) Specifications .............................................................................................................. 385 Command Definitions and Timing Diagrams - LPDDR4 .............................................................................. 387 Pull Up/Pull Down Driver Characteristics and Calibration ....................................................................... 387 On-Die Termination for the Command/Address Bus ............................................................................... 387 ODT Mode Register and ODT State Table ................................................................................................ 388 ODT Mode Register and ODT Characteristics ......................................................................................... 389 DQ On-Die Termination ........................................................................................................................ 390 Output Driver and Termination Register Temperature and Voltage Sensitivity .......................................... 393 AC and DC Operating Conditions - LPDDR4 ............................................................................................... 394 Recommended DC Operating Conditions ............................................................................................... 394 Output Slew Rate and Overshoot/Undershoot specifications - LPDDR4 ....................................................... 394 Single-Ended Output Slew Rate .............................................................................................................. 394 Differential Output Slew Rate ................................................................................................................. 395 LVSTL I/O System - LPDDR4 ...................................................................................................................... 396 Revision History ............................................................................................................................................ 398

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

8

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Features
Rev. A ­ 3/2020 .......................................................................................................................................... 398

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

9

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Features
List of Figures
Figure 1: MCP Block Diagram .......................................................................................................................... 1 Figure 2: Part Number Chart ............................................................................................................................ 3 Figure 3: 149-Ball WFBGA (x16 LPDDR) Ball Assignments ............................................................................... 23 Figure 4: 149-Ball Functional Block Diagram (LPDDR) .................................................................................. 0 Figure 5: 149-Ball WFBGA .............................................................................................................................. 27 Figure 6: NAND Flash Die (LUN) Functional Block Diagram ............................................................................ 30 Figure 7: Array Organization - MT29F4G08 ..................................................................................................... 31 Figure 8: Array Organization - MT29F8G08 ..................................................................................................... 32 Figure 9: Array Organization - MT29F4G16 ..................................................................................................... 33 Figure 10: Asynchronous Command Latch Cycle ............................................................................................ 35 Figure 11: Asynchronous Address Latch Cycle ................................................................................................ 36 Figure 12: Asynchronous Data Input Cycles .................................................................................................... 37 Figure 13: Asynchronous Data Output Cycles ................................................................................................. 39 Figure 14: Asynchronous Data Output Cycles (EDO Mode) ............................................................................. 39 Figure 15: READ/BUSY# Open Drain .............................................................................................................. 41 Figure 16: tFall and tRise (3.3V VCC) ................................................................................................................ 41 Figure 17: IOL vs. Rp (VCC = 3.3V VCC) .............................................................................................................. 42 Figure 18: TC vs. Rp ....................................................................................................................................... 42 Figure 19: R/B# Power-On Behavior ............................................................................................................... 43 Figure 20: RESET (FFh) Operation .................................................................................................................. 47 Figure 21: READ ID (90h) with 00h Address Operation .................................................................................... 48 Figure 22: READ ID (90h) with 20h Address Operation .................................................................................... 48 Figure 23: READ PARAMETER (ECh) Operation .............................................................................................. 51 Figure 24: READ UNIQUE ID (EDh) Operation ............................................................................................... 55 Figure 25: SET FEATURES (EFh) Operation .................................................................................................... 57 Figure 26: GET FEATURES (EEh) Operation .................................................................................................... 58 Figure 27: READ STATUS (70h) Operation ...................................................................................................... 61 Figure 28: READ STATUS ENHANCED (78h) Operation ................................................................................... 62 Figure 29: RANDOM DATA READ (05h-E0h) Operation ................................................................................... 64 Figure 30: RANDOM DATA INPUT (85h) Operation ........................................................................................ 65 Figure 31: PROGRAM FOR INTERNAL DATA INPUT (85h) Operation .............................................................. 66 Figure 32: READ PAGE (00h-30h) Operation ................................................................................................... 68 Figure 33: READ PAGE (00h-30h) Operation with Internal ECC Enabled .......................................................... 69 Figure 34: READ PAGE CACHE SEQUENTIAL (31h) Operation ......................................................................... 69 Figure 35: READ PAGE CACHE RANDOM (00h-31h) Operation ....................................................................... 70 Figure 36: READ PAGE CACHE LAST (3Fh) Operation ..................................................................................... 71 Figure 37: PROGRAM PAGE (80h-10h) Operation ............................................................................................ 73 Figure 38: PROGRAM PAGE CACHE (80h­15h) Operation (Start) ..................................................................... 74 Figure 39: PROGRAM PAGE CACHE (80h­15h) Operation (End) ...................................................................... 74 Figure 40: ERASE BLOCK (60h-D0h) Operation .............................................................................................. 75 Figure 41: READ FOR INTERNAL DATA MOVE (00h-35h) Operation ................................................................ 76 Figure 42: READ FOR INTERNAL DATA MOVE (00h­35h) with RANDOM DATA READ (05h­E0h) ..................... 77 Figure 43: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled ........................................................ 77 Figure 44: INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT with Internal ECC Enabled ............ 77 Figure 45: PROGRAM FOR INTERNAL DATA MOVE (85h­10h) Operation ........................................................ 78 Figure 46: PROGRAM FOR INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT (85h) .................... 78 Figure 47: Flash Array Protected: Invert Area Bit = 0 ........................................................................................ 80 Figure 48: Flash Array Protected: Invert Area Bit = 1 ........................................................................................ 80 Figure 49: UNLOCK Operation ....................................................................................................................... 81 Figure 50: LOCK Operation ............................................................................................................................ 82

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

10

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Features
Figure 51: LOCK TIGHT Operation ................................................................................................................. 83 Figure 52: PROGRAM/ERASE Issued to Locked Block ...................................................................................... 83 Figure 53: BLOCK LOCK READ STATUS .......................................................................................................... 84 Figure 54: BLOCK LOCK Flowchart ................................................................................................................ 85 Figure 55: Address and Command Cycles ....................................................................................................... 86 Figure 56: OTP DATA PROGRAM (After Entering OTP Operation Mode) ........................................................... 89 Figure 57: OTP DATA PROGRAM Operation with RANDOM DATA INPUT (After Entering OTP Operation Mode) .9..0 Figure 58: OTP DATA PROTECT Operation (After Entering OTP Protect Mode) ................................................. 91 Figure 59: OTP DATA READ ........................................................................................................................... 92 Figure 60: OTP DATA READ with RANDOM DATA READ Operation ................................................................. 92 Figure 61: RESET Operation .......................................................................................................................... 105 Figure 62: READ STATUS Cycle ..................................................................................................................... 105 Figure 63: READ STATUS ENHANCED Cycle .................................................................................................. 106 Figure 64: READ PARAMETER PAGE ............................................................................................................. 106 Figure 65: READ PAGE .................................................................................................................................. 107 Figure 66: READ PAGE Operation with CE# "Don't Care" ............................................................................... 108 Figure 67: RANDOM DATA READ .................................................................................................................. 108 Figure 68: READ PAGE CACHE SEQUENTIAL ................................................................................................ 109 Figure 69: READ PAGE CACHE RANDOM ...................................................................................................... 110 Figure 70: READ ID Operation ...................................................................................................................... 111 Figure 71: PROGRAM PAGE Operation .......................................................................................................... 111 Figure 72: PROGRAM PAGE Operation with CE# "Don't Care" ........................................................................ 112 Figure 73: PROGRAM PAGE Operation with RANDOM DATA INPUT .............................................................. 112 Figure 74: PROGRAM PAGE CACHE .............................................................................................................. 113 Figure 75: PROGRAM PAGE CACHE Ending on 15h ........................................................................................ 113 Figure 76: INTERNAL DATA MOVE ............................................................................................................... 114 Figure 77: ERASE BLOCK Operation .............................................................................................................. 114 Figure 78: Functional Block Diagram ............................................................................................................ 127 Figure 79: Simplified State Diagram .............................................................................................................. 130 Figure 80: Simplified State Diagram .............................................................................................................. 131 Figure 81: Voltage Ramp and Initialization Sequence ..................................................................................... 133 Figure 82: ACTIVATE Command ................................................................................................................... 165 Figure 83: tFAW Timing ................................................................................................................................. 166 Figure 84: DQS Read Preamble and Postamble ­ Toggling Preamble and 0.5nCK Postamble ............................ 167 Figure 85: DQS Read Preamble and Postamble ­ Static Preamble and 1.5nCK Postamble ................................. 167 Figure 86: DQS Write Preamble and Postamble ­ 0.5nCK Postamble ............................................................... 168 Figure 87: DQS Write Preamble and Postamble ­ 1.5nCK Postamble ............................................................... 169 Figure 88: Burst Read Timing ........................................................................................................................ 170 Figure 89: Burst Read Followed by Burst Write or Burst Mask Write ................................................................. 171 Figure 90: Seamless Burst Read ..................................................................................................................... 171 Figure 91: Read Timing ................................................................................................................................. 172 Figure 92: tLZ(DQS) Method for Calculating Transitions and Endpoint ........................................................... 173 Figure 93: tHZ(DQS) Method for Calculating Transitions and Endpoint .......................................................... 173 Figure 94: tLZ(DQ) Method for Calculating Transitions and Endpoint ............................................................. 174 Figure 95: tHZ(DQ) Method for Calculating Transitions and Endpoint ............................................................ 175 Figure 96: Burst WRITE Operation ................................................................................................................ 177 Figure 97: Burst Write Followed by Burst Read ............................................................................................... 178 Figure 98: Write Timing ................................................................................................................................ 179 Figure 99: Method for Calculating tWPRE Transitions and Endpoints .............................................................. 180 Figure 100: Method for Calculating tWPST Transitions and Endpoints ............................................................ 180 Figure 101: MASK WRITE Command ­ Same Bank ......................................................................................... 181 Figure 102: MASK WRITE Command ­ Different Bank ................................................................................... 182

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

11

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Features
Figure 103: MASKED WRITE Command with Write DBI Enabled; DM Enabled ............................................... 187 Figure 104: WRITE Command with Write DBI Enabled; DM Disabled ............................................................. 188 Figure 105: WDQS Control Mode 1 ................................................................................................................ 189 Figure 106: Burst WRITE Operation ............................................................................................................... 191 Figure 107: Burst READ Followed by Burst WRITE or Burst MASKED WRITE (ODT Disable) ............................ 192 Figure 108: Burst READ Followed by Burst WRITE or Burst MASKED WRITE (ODT Enable) ............................. 193 Figure 109: READ Operations: tCCD = MIN, Preamble = Toggle, 1.5nCK Postamble ......................................... 194 Figure 110: Seamless READ: tCCD = MIN + 1, Preamble = Toggle, 1.5nCK Postamble ....................................... 195 Figure 111: Consecutive READ: tCCD = MIN + 1, Preamble = Toggle, 0.5nCK Postamble .................................. 195 Figure 112: Consecutive READ: tCCD = MIN + 1, Preamble = Static, 1.5nCK Postamble .................................... 196 Figure 113: Consecutive READ: tCCD = MIN + 1, Preamble = Static, 0.5nCK Postamble .................................... 196 Figure 114: Consecutive READ: tCCD = MIN + 2, Preamble = Toggle, 1.5nCK Postamble .................................. 197 Figure 115: Consecutive READ: tCCD = MIN + 2, Preamble = Toggle, 0.5nCK Postamble .................................. 198 Figure 116: Consecutive READ: tCCD = MIN + 2, Preamble = Static, 1.5nCK Postamble .................................... 198 Figure 117: Consecutive READ: tCCD = MIN + 2, Preamble = Static, 0.5nCK Postamble .................................... 199 Figure 118: Consecutive READ: tCCD = MIN + 3, Preamble = Toggle, 1.5nCK Postamble .................................. 200 Figure 119: Consecutive READ: tCCD = MIN + 3, Preamble = Toggle, 0.5nCK Postamble .................................. 200 Figure 120: Consecutive READ: tCCD = MIN + 3, Preamble = Static, 1.5nCK Postamble .................................... 201 Figure 121: Consecutive READ: tCCD = MIN + 3, Preamble = Static, 0.5nCK Postamble .................................... 201 Figure 122: Seamless WRITE: tCCD = MIN, 0.5nCK Postamble ........................................................................ 202 Figure 123: Seamless WRITE: tCCD = MIN, 1.5nCK Postamble, 533 MHz < Clock Frequency  800 MHz, ODT
Worst Timing Case ..................................................................................................................................... 203 Figure 124: Seamless WRITE: tCCD = MIN, 1.5nCK Postamble ........................................................................ 204 Figure 125: Consecutive WRITE: tCCD = MIN + 1, 0.5nCK Postamble .............................................................. 205 Figure 126: Consecutive WRITE: tCCD = MIN + 1, 1.5nCK Postamble .............................................................. 205 Figure 127: Consecutive WRITE: tCCD = MIN + 2, 0.5nCK Postamble .............................................................. 206 Figure 128: Consecutive WRITE: tCCD = MIN + 2, 1.5nCK Postamble .............................................................. 206 Figure 129: Consecutive WRITE: tCCD = MIN + 3, 0.5nCK Postamble .............................................................. 207 Figure 130: Consecutive WRITE: tCCD = MIN + 3, 1.5nCK Postamble .............................................................. 208 Figure 131: Consecutive WRITE: tCCD = MIN + 4, 1.5nCK Postamble .............................................................. 208 Figure 132: Burst READ Followed by Precharge ­ BL16, Toggling Preamble, 0.5nCK Postamble ........................ 210 Figure 133: Burst READ Followed by Precharge ­ BL32, 2tCK, 0.5nCK Postamble ............................................. 210 Figure 134: Burst WRITE Followed by PRECHARGE ­ BL16, 2nCK Preamble, 0.5nCK Postamble ...................... 211 Figure 135: Burst READ With Auto Precharge ­ BL16, Non-Toggling Preamble, 0.5nCK Postamble ................... 212 Figure 136: Burst READ With Auto Precharge ­ BL32, Toggling Preamble, 1.5nCK Postamble ........................... 212 Figure 137: Burst WRITE With Auto Precharge ­ BL16, 2 nCK Preamble, 0.5nCK Postamble .............................. 213 Figure 138: Command Input Timing with RAS Lock ....................................................................................... 217 Figure 139: Delay Time From WRITE-to-READ with Auto Precharge ............................................................... 217 Figure 140: All-Bank REFRESH Operation ..................................................................................................... 220 Figure 141: Per Bank REFRESH Operation ..................................................................................................... 221 Figure 142: Postponing REFRESH Commands (Example) ............................................................................... 223 Figure 143: Pulling in REFRESH Commands (Example) .................................................................................. 223 Figure 144: Burst READ Operation Followed by Per Bank Refresh ................................................................... 224 Figure 145: Burst READ With AUTO PRECHARGE Operation Followed by Per Bank Refresh ............................. 225 Figure 146: Self Refresh Entry/Exit Timing ..................................................................................................... 227 Figure 147: Self Refresh Entry/Exit Timing with Power-Down Entry/Exit ......................................................... 228 Figure 148: Command Input Timings after Power-Down Exit During Self Refresh ............................................ 229 Figure 149: MRR, MRW, and MPC Commands Issuing Timing During tXSR ..................................................... 230 Figure 150: MRR, MRW, and MPC Commands Issuing Timing During tRFC ..................................................... 231 Figure 151: Basic Power-Down Entry and Exit Timing .................................................................................... 233 Figure 152: Read and Read with Auto Precharge to Power-Down Entry ........................................................... 234 Figure 153: Write and Mask Write to Power-Down Entry ................................................................................ 235

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

12

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Features
Figure 154: Write With Auto Precharge and Mask Write With Auto Precharge to Power-Down Entry ................. 236 Figure 155: Refresh Entry to Power-Down Entry ............................................................................................. 237 Figure 156: ACTIVATE Command to Power-Down Entry ................................................................................. 237 Figure 157: PRECHARGE Command to Power-Down Entry ............................................................................ 238 Figure 158: Mode Register Read to Power-Down Entry ................................................................................... 239 Figure 159: Mode Register Write to Power-Down Entry .................................................................................. 240 Figure 160: MULTI PURPOSE Command for ZQCAL Start to Power-Down Entry ............................................. 241 Figure 161: MODE REGISTER READ Operation ............................................................................................. 245 Figure 162: READ-to-MRR Timing ................................................................................................................ 246 Figure 163: WRITE-to-MRR Timing ............................................................................................................... 247 Figure 164: MRR Following Power-Down ....................................................................................................... 248 Figure 165: MODE REGISTER WRITE Timing ................................................................................................ 248 Figure 166: VRCG Enable Timing .................................................................................................................. 251 Figure 167: VRCG Disable Timing ................................................................................................................. 251 Figure 168: VREF Operating Range (VREF,max, VREF,min) ..................................................................................... 252 Figure 169: VREF Set-Point Tolerance and Step Size ........................................................................................ 253 Figure 170: tVref for Short, Middle, and Long Timing Diagram ......................................................................... 254 Figure 171: VREF(CA) Single-Step Increment .................................................................................................... 254 Figure 172: VREF(CA) Single-Step Decrement ................................................................................................... 255 Figure 173: VREF(CA) Full Step from VREF,min to VREF,max .................................................................................... 255 Figure 174: VREF(CA) Full Step from VREF,max to VREF,min .................................................................................... 255 Figure 175: VREF Operating Range (VREF,max, VREF,min) ..................................................................................... 257 Figure 176: VREF Set Tolerance and Step Size .................................................................................................. 258 Figure 177: VREF(DQ) Transition Time for Short, Middle, or Long Changes ........................................................ 259 Figure 178: VREF(DQ) Single-Step Size Increment ............................................................................................. 259 Figure 179: VREF(DQ) Single-Step Size Decrement ............................................................................................ 260 Figure 180: VREF(DQ) Full Step from VREF,min to VREF,max ................................................................................... 260 Figure 181: VREF(DQ) Full Step from VREF,max to VREF,min ................................................................................... 260 Figure 182: Command Bus Training Mode Entry ­ CA Training Pattern I/O with V REF(CA) Value Update ............ 265 Figure 183: Consecutive VREF(CA) Value Update .............................................................................................. 266 Figure 184: Command Bus Training Mode Exit with Valid Command .............................................................. 267 Figure 185: Command Bus Training Mode Exit with Power-Down Entry .......................................................... 268 Figure 186: Write Leveling Timing ­ tDQSL(MAX) .......................................................................................... 270 Figure 187: Write Leveling Timing ­ tDQSL(MIN) ........................................................................................... 270 Figure 188: Clock Stop and Timing During Write Leveling .............................................................................. 271 Figure 189: DQS_t/DQS_c to CK_t/CK_c Timings at the Pins Referenced from the Internal Latch .................... 272 Figure 190: WRITE-FIFO ­ tWPRE = 2nCK, tWPST = 0.5nCK ............................................................................ 274 Figure 191: READ-FIFO ­ tWPRE = 2nCK, tWPST = 0.5nCK, tRPRE = Toggling, tRPST = 1.5nCK ......................... 275 Figure 192: READ-FIFO ­ tRPRE = Toggling, tRPST = 1.5nCK ........................................................................... 276 Figure 193: Read DQ Calibration Training Timing: Read-to-Read DQ Calibration ............................................ 279 Figure 194: Read DQ Calibration Training Timing: Read DQ Calibration to Read DQ Calibration/Read ............ 279 Figure 195: MPC[READ DQ CALIBRATION] Following Power-Down State ....................................................... 281 Figure 196: WRITE-to-MPC[WRITE-FIFO] Operation Timing ......................................................................... 283 Figure 197: MPC[WRITE-FIFO]-to-MPC[READ-FIFO] Timing ........................................................................ 284 Figure 198: MPC[READ-FIFO] to Read Timing ............................................................................................... 285 Figure 199: MPC[WRITE-FIFO] with DQ ODT Timing .................................................................................... 286 Figure 200: Power-Down Exit to MPC[WRITE-FIFO] Timing ........................................................................... 287 Figure 201: Interval Oscillator Offset ­ OSCoffset ............................................................................................. 289 Figure 202: In Case of DQS Interval Oscillator is Stopped by MPC Command .................................................. 290 Figure 203: In Case of DQS Interval Oscillator is Stopped by DQS Interval Timer ............................................. 291 Figure 204: Temperature Sensor Timing ........................................................................................................ 293 Figure 205: ZQCAL Timing ............................................................................................................................ 294

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

13

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Features
Figure 206: Frequency Set Point Switching Timing ......................................................................................... 298 Figure 207: Training for Two Frequency Set Points ......................................................................................... 300 Figure 208: Example of Switching Between Two Trained Frequency Set Points ................................................ 300 Figure 209: Example of Switching to a Third Trained Frequency Set Point ....................................................... 301 Figure 210: ODT for CA ................................................................................................................................. 302 Figure 211: ODT for CA Setting Update Timing in 4-Clock Cycle Command .................................................... 304 Figure 212: Functional Representation of DQ ODT ........................................................................................ 305 Figure 213: Asynchronous ODTon/ODToff Timing ......................................................................................... 308 Figure 214: Target Row Refresh Mode ............................................................................................................ 311 Figure 215: Post-Package Repair Timing ........................................................................................................ 313 Figure 216: Read Preamble Training .............................................................................................................. 314 Figure 217: Input Timing Definition for CKE .................................................................................................. 317 Figure 218: Input Timing Definition for RESET_n .......................................................................................... 317 Figure 219: CK Differential Input Voltage ....................................................................................................... 318 Figure 220: Definition of Differential Clock Peak Voltage ................................................................................ 319 Figure 221: Clock Single-Ended Input Voltage ................................................................................................ 319 Figure 222: Differential Input Slew Rate Definition for CK_t, CK_c .................................................................. 320 Figure 223: Vix Definition (Clock) .................................................................................................................. 321 Figure 224: DQS Differential Input Voltage .................................................................................................... 322 Figure 225: Definition of Differential DQS Peak Voltage .................................................................................. 323 Figure 226: DQS Single-Ended Input Voltage ................................................................................................. 323 Figure 227: Differential Input Slew Rate Definition for DQS_t, DQS_c ............................................................. 324 Figure 228: Vix Definition (DQS) .................................................................................................................... 325 Figure 229: Single-Ended Output Slew Rate Definition ................................................................................... 327 Figure 230: Differential Output Slew Rate Definition ...................................................................................... 327 Figure 231: Overshoot and Undershoot Definition ......................................................................................... 328 Figure 232: Driver Output Timing Reference Load ......................................................................................... 329 Figure 233: LVSTL I/O Cell ............................................................................................................................ 329 Figure 234: Pull-Up Calibration ..................................................................................................................... 330 Figure 235: tCMDCKE Timing ....................................................................................................................... 353 Figure 236: tESCKE Timing ........................................................................................................................... 356 Figure 237: CA Receiver (Rx) Mask ................................................................................................................ 359 Figure 238: Across Pin VREF (CA) Voltage Variation ........................................................................................... 359 Figure 239: CA Timings at the DRAM Pins ..................................................................................................... 360 Figure 240: CA tcIPW and SRIN_cIVW Definition (for Each Input Pulse) .......................................................... 360 Figure 241: CA VIHL_AC Definition (for Each Input Pulse) ................................................................................ 360 Figure 242: Read Data Timing Definitions ­ tQH and tDQSQ Across DQ Signals per DQS Group ....................... 362 Figure 243: DQ Receiver (Rx) Mask ................................................................................................................ 363 Figure 244: Across Pin VREF DQ Voltage Variation ........................................................................................... 363 Figure 245: DQ-to-DQS tDQS2DQ and tDQDQ .............................................................................................. 364 Figure 246: DQ tDIPW and SRIN_dIVW Definition for Each Input Pulse .......................................................... 365 Figure 247: DQ VIHL(AC) Definition (for Each Input Pulse) ............................................................................... 365 Figure 248: tLZ(DQS) Method for Calculating Transitions and Endpoint ......................................................... 380 Figure 249: tHZ(DQS) Method for Calculating Transitions and Endpoint ......................................................... 381 Figure 250: tLZ(DQ) Method for Calculating Transitions and Endpoint ........................................................... 382 Figure 251: tHZ(DQ) Method for Calculating Transitions and Endpoint .......................................................... 382 Figure 252: ODT for CA ................................................................................................................................. 388 Figure 253: Functional Representation of DQ ODT ........................................................................................ 391 Figure 254: Single-Ended Output Slew Rate Definition ................................................................................... 395 Figure 255: Differential Output Slew Rate Definition ...................................................................................... 396 Figure 256: LVSTL I/O Cell ............................................................................................................................ 396 Figure 257: Pull-Up Calibration ..................................................................................................................... 397

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

14

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Features
List of Tables
Table 1: Key Timing Parameters ....................................................................................................................... 2 Table 2: Configuration Addressing ................................................................................................................... 2 Table 3: Part Number References ..................................................................................................................... 2 Table 4: x8 NAND Ball Descriptions ............................................................................................................... 24 Table 5: x16 LPDDR Ball Descriptions ............................................................................................................ 24 Table 6: Non-Device-Specific Descriptions ..................................................................................................... 25 Table 7: Array Addressing (×8) ........................................................................................................................ 31 Table 8: Array Addressing (×8) ........................................................................................................................ 32 Table 9: Array Addressing (×16) ...................................................................................................................... 33 Table 10: Asynchronous Interface Mode Selection .......................................................................................... 34 Table 11: Power Cycle Requirements .............................................................................................................. 44 Table 12: Command Set ................................................................................................................................. 45 Table 13: READ ID Parameters for Address 00h ............................................................................................... 49 Table 14: READ ID Parameters for Address 20h ............................................................................................... 50 Table 15: Parameter Page Data Structure ........................................................................................................ 52 Table 16: Feature Address Definitions ............................................................................................................. 56 Table 17: Feature Addresses 90h: Timing Mode ............................................................................................... 56 Table 18: Feature Addresses 01h: Timing Mode ............................................................................................... 58 Table 19: Feature Addresses 80h: Programmable I/O Drive Strength ................................................................ 58 Table 20: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ...................................................... 59 Table 21: Status Register Definition ................................................................................................................ 60 Table 22: Block Lock Address Cycle Assignments ............................................................................................ 80 Table 23: Block Lock Status Register Bit Definitions ........................................................................................ 83 Table 24: Spare Area Mapping (×8) ................................................................................................................. 93 Table 25: Spare Area Mapping (×16) ............................................................................................................... 94 Table 26: ECC Status ...................................................................................................................................... 95 Table 27: Error Management Details .............................................................................................................. 96 Table 28: Absolute Maximum Ratings ............................................................................................................. 97 Table 29: Recommended Operating Conditions .............................................................................................. 97 Table 30: Capacitance .................................................................................................................................... 97 Table 31: Test Conditions ............................................................................................................................... 97 Table 32: DC Characteristics and Operating Conditions (3.3V) ........................................................................ 99 Table 33: DC Characteristics and Operating Conditions (1.8V) ....................................................................... 100 Table 34: AC Characteristics: Command, Data, and Address Input (3.3V) ........................................................ 101 Table 35: AC Characteristics: Command, Data, and Address Input (1.8V) ........................................................ 101 Table 36: AC Characteristics: Normal Operation (3.3V) .................................................................................. 102 Table 37: AC Characteristics: Normal Operation (1.8V) .................................................................................. 103 Table 38: Program/Erase Characteristics ....................................................................................................... 104 Table 39: Key Timing Parameters .................................................................................................................. 115 Table 40: Mode Register Contents ................................................................................................................. 117 Table 41: LPDDR4 IDD Specifications under 3733 Mb/s ­ Single Die ................................................................ 118 Table 42: LPDDR4 IDD Specifications under 4266 Mb/s ­ Single Die ................................................................ 119 Table 43: LPDDR4 IDD6 Full-Array Self Refresh Current .................................................................................. 121 Table 44: LPDDR4X IDD Specifications under 3733 Mb/s ­ Single Die .............................................................. 122 Table 45: LPDDR4X IDD Specifications under 4266 Mb/s ­ Single Die .............................................................. 123 Table 46: LPDDR4X IDD6 Full-Array Self Refresh Current ................................................................................ 125 Table 47: Monolithic Device Addressing ­ Dual-Channel Die .......................................................................... 128 Table 48: Monolithic Device Addressing ­ Single-Channel Die ........................................................................ 129 Table 49: Mode Register Default Settings ....................................................................................................... 132 Table 50: Voltage Ramp Conditions ............................................................................................................... 132

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

15

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Features
Table 51: Initialization Timing Parameters ..................................................................................................... 134 Table 52: Reset Timing Parameter ................................................................................................................. 135 Table 53: Power Supply Conditions ............................................................................................................... 135 Table 54: Power-Off Timing ........................................................................................................................... 136 Table 55: Mode Register Assignments ............................................................................................................ 136 Table 56: MR0 Device Feature 0 (MA[5:0] = 00h) ............................................................................................. 137 Table 57: MR0 Op-Code Bit Definitions ......................................................................................................... 137 Table 58: MR1 Device Feature 1 (MA[5:0] = 01h) ............................................................................................. 138 Table 59: MR1 Op-Code Bit Definitions ......................................................................................................... 138 Table 60: Burst Sequence for Read ................................................................................................................. 140 Table 61: Burst Sequence for Write ................................................................................................................ 140 Table 62: MR2 Device Feature 2 (MA[5:0] = 02h) ............................................................................................. 141 Table 63: MR2 Op-Code Bit Definitions ......................................................................................................... 141 Table 64: Frequency Ranges for RL, WL, nWR, and nRTP Settings ................................................................... 143 Table 65: MR3 I/O Configuration 1 (MA[5:0] = 03h) ........................................................................................ 143 Table 66: MR3 Op-Code Bit Definitions ......................................................................................................... 144 Table 67: MR4 Device Temperature (MA[5:0] = 04h) ....................................................................................... 145 Table 68: MR4 Op-Code Bit Definitions ......................................................................................................... 145 Table 69: MR5 Basic Configuration 1 (MA[5:0] = 05h) ..................................................................................... 146 Table 70: MR5 Op-Code Bit Definitions ......................................................................................................... 146 Table 71: MR6 Basic Configuration 2 (MA[5:0] = 06h) ..................................................................................... 146 Table 72: MR6 Op-Code Bit Definitions ......................................................................................................... 146 Table 73: MR7 Basic Configuration 3 (MA[5:0] = 07h) ..................................................................................... 146 Table 74: MR7 Op-Code Bit Definitions ......................................................................................................... 146 Table 75: MR8 Basic Configuration 4 (MA[5:0] = 08h) ..................................................................................... 147 Table 76: MR8 Op-Code Bit Definitions ......................................................................................................... 147 Table 77: MR9 Test Mode (MA[5:0] = 09h) ...................................................................................................... 147 Table 78: MR9 Op-Code Definitions .............................................................................................................. 147 Table 79: MR10 Calibration (MA[5:0] = 0Ah) .................................................................................................. 147 Table 80: MR10 Op-Code Bit Definitions ....................................................................................................... 148 Table 81: MR11 ODT Control (MA[5:0] = 0Bh) ................................................................................................ 148 Table 82: MR11 Op-Code Bit Definitions ....................................................................................................... 148 Table 83: MR12 Register Information (MA[5:0] = 0Ch) .................................................................................... 149 Table 84: MR12 Op-Code Bit Definitions ....................................................................................................... 149 Table 85: MR13 Register Control (MA[5:0] = 0Dh) ........................................................................................... 149 Table 86: MR13 Op-Code Bit Definition ......................................................................................................... 150 Table 87: Mode Register 14 (MA[5:0] = 0Eh) ................................................................................................... 151 Table 88: MR14 Op-Code Bit Definition ......................................................................................................... 151 Table 89: VREF Setting for Range[0] and Range[1] ............................................................................................ 152 Table 90: MR15 Register Information (MA[5:0] = 0Fh) .................................................................................... 153 Table 91: MR15 Op-code Bit Definition ......................................................................................................... 153 Table 92: MR15 Invert Register Pin Mapping .................................................................................................. 153 Table 93: MR16 PASR Bank Mask (MA[5:0] = 010h) ......................................................................................... 153 Table 94: MR16 Op-Code Bit Definitions ....................................................................................................... 153 Table 95: MR17 PASR Segment Mask (MA[5:0] = 11h) ..................................................................................... 154 Table 96: MR17 PASR Segment Mask Definitions ........................................................................................... 154 Table 97: MR17 PASR Segment Mask ............................................................................................................. 154 Table 98: MR18 Register Information (MA[5:0] = 12h) .................................................................................... 155 Table 99: MR18 LSB DQS Oscillator Count ..................................................................................................... 155 Table 100: MR19 Register Information (MA[5:0] = 13h) ................................................................................... 155 Table 101: MR19 DQS Oscillator Count ......................................................................................................... 155 Table 102: MR20 Register Information (MA[5:0] = 14h) ................................................................................... 155

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

16

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Features

Table 103: MR20 Register Information ........................................................................................................... 156 Table 104: MR20 Invert Register Pin Mapping ................................................................................................ 156 Table 105: MR21 Register Information (MA[5:0] = 15h) ................................................................................... 156 Table 106: MR22 Register Information (MA[5:0] = 16h) ................................................................................... 156 Table 107: MR22 Register Information ........................................................................................................... 157 Table 108: MR23 Register Information (MA[5:0] = 17h) ................................................................................... 157 Table 109: MR23 Register Information ........................................................................................................... 158 Table 110: MR24 Register Information (MA[5:0] = 18h) ................................................................................... 158 Table 111: MR24 Register Information ........................................................................................................... 158 Table 112: MR25 Register Information (MA[5:0] = 19h) ................................................................................... 159 Table 113: MR25 Register Information ........................................................................................................... 159 Table 114: MR26:29 Register Information (MA[5:0] = 1Ah­1Dh) ...................................................................... 159 Table 115: MR30 Register Information (MA[5:0] = 1Eh) .................................................................................. 160 Table 116: MR30 Register Information ........................................................................................................... 160 Table 117: MR31 Register Information (MA[5:0] = 1Fh) ................................................................................... 160 Table 118: MR32 Register Information (MA[5:0] = 20h) ................................................................................... 160 Table 119: MR32 Register Information ........................................................................................................... 160 Table 120: MR33:38 Register Information (MA[5:0] = 21h­26h) ....................................................................... 161 Table 121: MR39 Register Information (MA[5:0] = 27h) ................................................................................... 161 Table 122: MR39 Register Information ........................................................................................................... 161 Table 123: MR40 Register Information (MA[5:0] = 28h) ................................................................................... 161 Table 124: MR40 Register Information ........................................................................................................... 161 Table 125: MR41:47 Register Information (MA[5:0] = 29h­2Fh) ....................................................................... 162 Table 126: MR48:63 Register Information (MA[5:0] = 30h­3Fh) ....................................................................... 162 Table 127: Command Truth Table ................................................................................................................. 162 Table 128: Reference Voltage for tLZ(DQS), tHZ(DQS) Timing Measurements .................................................. 174 Table 129: Reference Voltage for tLZ(DQ), tHZ(DQ) Timing Measurements ..................................................... 175 Table 130: Method for Calculating tWPRE Transitions and Endpoints ............................................................. 180 Table 131: Reference Voltage for tWPST Timing Measurements ...................................................................... 181 Table 132: Same Bank (ODT Disabled) .......................................................................................................... 183 Table 133: Different Bank (ODT Disabled) ..................................................................................................... 183 Table 134: Same Bank (ODT Enabled) ........................................................................................................... 184 Table 135: Different Bank (ODT Enabled) ...................................................................................................... 184 Table 136: Function Behavior of DMI Signal During WRITE, MASKED WRITE, and READ Operations .............. 185 Table 137: WDQS_On/WDQS_Off Definition ................................................................................................. 190 Table 138: WDQS_On/WDQS_Off Allowable Variation Range ......................................................................... 190 Table 139: DQS Turn-Around Parameter ........................................................................................................ 191 Table 140: Precharge Bank Selection ............................................................................................................. 209 Table 141: Timing Between Commands (PRECHARGE and AUTO PRECHARGE): DQ ODT is Disable ............... 213 Table 142: Timing Between Commands (PRECHARGE and AUTO PRECHARGE): DQ ODT is Enable ................ 216 Table 143: Bank and Refresh Counter Increment Behavior ............................................................................. 218 Table 144: REFRESH Command Timing Constraints ...................................................................................... 220 Table 145: Legacy REFRESH Command Timing Constraints ........................................................................... 222 Table 146: Modified REFRESH Command Timing Constraints ........................................................................ 222 Table 147: Refresh Requirement Parameters .................................................................................................. 225 Table 148: MRR ............................................................................................................................................ 244 Table 149: Truth Table for MRR and MRW ..................................................................................................... 249 Table 150: MRR/MRW Timing Constraints: DQ ODT is Disable ...................................................................... 249 Table 151: MRR/MRW Timing Constraints: DQ ODT is Enable ....................................................................... 250 Table 152: VRCG Enable/Disable Timing ....................................................................................................... 251 Table 153: Internal VREF(CA) Specifications ..................................................................................................... 256 Table 154: Internal VREF(DQ) Specifications .................................................................................................... 261

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

17

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Features
Table 155: Mapping MR12 Op Code and DQ Numbers ................................................................................... 263 Table 156: Mapping CA Input Pin and DQ Output Pin .................................................................................... 265 Table 157: Write Leveling Timing Parameters ................................................................................................. 271 Table 158: Write Leveling Setup and Hold Timing .......................................................................................... 271 Table 159: MPC Command Definition ........................................................................................................... 273 Table 160: MPC Commands .......................................................................................................................... 274 Table 161: Timing Constraints for Training Commands .................................................................................. 276 Table 162: Invert Mask Assignments .............................................................................................................. 278 Table 163: Read DQ Calibration Bit Ordering and Inversion Example .............................................................. 280 Table 164: MR Setting vs. DMI Status ............................................................................................................. 281 Table 165: MPC[WRITE-FIFO] AC Timing ...................................................................................................... 287 Table 166: DQS Oscillator Matching Error Specification ................................................................................. 289 Table 167: DQS Interval Oscillator AC Timing ................................................................................................ 291 Table 168: Temperature Sensor ..................................................................................................................... 293 Table 169: ZQ Calibration Parameters ........................................................................................................... 294 Table 170: Mode Register Function With Two Physical Registers ..................................................................... 296 Table 171: Relation Between MR Setting and DRAM Operation ...................................................................... 297 Table 172: Frequency Set Point AC Timing ..................................................................................................... 298 Table 173: tFC Value Mapping ....................................................................................................................... 298 Table 174: tFC Value Mapping: Example ........................................................................................................ 299 Table 175: Pull-Down Driver Characteristics ­ ZQ Calibration ........................................................................ 301 Table 176: Pull-Up Characteristics ­ ZQ Calibration ....................................................................................... 301 Table 177: Valid Calibration Points ................................................................................................................ 301 Table 178: Command Bus ODT State ............................................................................................................. 303 Table 179: ODT DC Electrical Characteristics for Command/Address Bus ....................................................... 303 Table 180: ODT DC Electrical Characteristics for DQ Bus ............................................................................... 305 Table 181: Output Driver and Termination Register Sensitivity Definition ....................................................... 306 Table 182: Output Driver and Termination Register Temperature and Voltage Sensitivity ................................. 306 Table 183: ODTLON and ODTLOFF Latency Values .......................................................................................... 308 Table 184: Termination State in Write Leveling Mode ..................................................................................... 309 Table 185: Post-Package Repair Timing Parameters ........................................................................................ 313 Table 186: Absolute Maximum DC Ratings .................................................................................................... 315 Table 187: Recommended DC Operating Conditions ..................................................................................... 315 Table 188: Input Leakage Current .................................................................................................................. 315 Table 189: Input/Output Leakage Current ..................................................................................................... 316 Table 190: Operating Temperature Range ...................................................................................................... 316 Table 191: Input Levels ................................................................................................................................. 317 Table 192: Input Levels ................................................................................................................................. 317 Table 193: CK Differential Input Voltage ........................................................................................................ 318 Table 194: Clock Single-Ended Input Voltage ................................................................................................. 320 Table 195: Differential Input Slew Rate Definition for CK_t, CK_c ................................................................... 320 Table 196: Differential Input Level for CK_t, CK_c .......................................................................................... 321 Table 197: Differential Input Slew Rate for CK_t, CK_c .................................................................................... 321 Table 198: Cross-Point Voltage for Differential Input Signals (Clock) ............................................................... 322 Table 199: DQS Differential Input Voltage ...................................................................................................... 322 Table 200: DQS Single-Ended Input Voltage ................................................................................................... 324 Table 201: Differential Input Slew Rate Definition for DQS_t, DQS_c .............................................................. 324 Table 202: Differential Input Level for DQS_t, DQS_c ..................................................................................... 325 Table 203: Differential Input Slew Rate for DQS_t, DQS_c ............................................................................... 325 Table 204: Cross-Point Voltage for Differential Input Signals (DQS) ................................................................ 326 Table 205: Input Levels for ODT_CA .............................................................................................................. 326 Table 206: Single-Ended Output Slew Rate .................................................................................................... 326

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

18

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Features
Table 207: Differential Output Slew Rate ....................................................................................................... 327 Table 208: AC Overshoot/Undershoot Specifications ..................................................................................... 328 Table 209: Overshoot/Undershoot Specification for CKE and RESET .............................................................. 328 Table 210: Input/Output Capacitance ........................................................................................................... 330 Table 211: IDD Measurement Conditions ....................................................................................................... 331 Table 212: CA Pattern for IDD4R for BL = 16 ..................................................................................................... 331 Table 213: CA Pattern for IDD4W for BL = 16 .................................................................................................... 332 Table 214: Data Pattern for IDD4W (DBI Off ) for BL = 16 .................................................................................. 332 Table 215: Data Pattern for IDD4R (DBI Off ) for BL = 16 ................................................................................... 333 Table 216: Data Pattern for IDD4W (DBI On) for BL = 16 ................................................................................... 335 Table 217: Data Pattern for IDD4R (DBI On) for BL = 16 .................................................................................... 336 Table 218: CA Pattern for IDD4R for BL = 32 ..................................................................................................... 337 Table 219: CA Pattern for IDD4W for BL = 32 .................................................................................................... 338 Table 220: Data Pattern for IDD4W (DBI Off ) for BL = 32 .................................................................................. 339 Table 221: Data Pattern for IDD4R (DBI Off ) for BL = 32 ................................................................................... 340 Table 222: Data Pattern for IDD4W (DBI On) for BL = 32 ................................................................................... 342 Table 223: Data Pattern for IDD4R (DBI On) for BL = 32 .................................................................................... 344 Table 224: IDD Specification Parameters and Operating Conditions ................................................................ 347 Table 225: Clock Timing ............................................................................................................................... 349 Table 226: Read Output Timing ..................................................................................................................... 349 Table 227: Write Timing ................................................................................................................................ 351 Table 228: CKE Input Timing ........................................................................................................................ 352 Table 229: Command Address Input Timing .................................................................................................. 353 Table 230: Boot Timing Parameters (10­55 MHz) ........................................................................................... 354 Table 231: Mode Register Timing Parameters ................................................................................................. 354 Table 232: Core Timing Parameters ............................................................................................................... 354 Table 233: CA Bus ODT Timing ..................................................................................................................... 356 Table 234: CA Bus Training Parameters .......................................................................................................... 356 Table 235: Asynchronous ODT Turn On and Turn Off Timing ......................................................................... 357 Table 236: Temperature Derating Parameters ................................................................................................ 357 Table 237: DRAM CMD/ADR, CS ................................................................................................................... 361 Table 238: DQs In Receive Mode ................................................................................................................... 365 Table 239: Definitions and Calculations ........................................................................................................ 366 Table 240: tCK(abs), tCH(abs), and tCL(abs) Definitions ................................................................................. 367 Table 241: Mode Register Default Settings ..................................................................................................... 370 Table 242: Mode Register Assignments .......................................................................................................... 371 Table 243: MR0 Device Feature 0 (MA[5:0] = 00h) ........................................................................................... 372 Table 244: MR0 Op-Code Bit Definitions ....................................................................................................... 372 Table 245: MR3 I/O Configuration 1 (MA[5:0] = 03h) ...................................................................................... 373 Table 246: MR3 Op-Code Bit Definitions ....................................................................................................... 374 Table 247: MR12 Register Information (MA[5:0] = 0Ch) .................................................................................. 375 Table 248: MR12 Op-Code Bit Definitions ...................................................................................................... 375 Table 249: Mode Register 14 (MA[5:0] = 0Eh) ................................................................................................. 375 Table 250: MR14 Op-Code Bit Definition ....................................................................................................... 376 Table 251: VREF Setting for Range[0] and Range[1] .......................................................................................... 377 Table 252: MR22 Register Information (MA[5:0] = 16h) ................................................................................... 378 Table 253: MR22 Register Information ........................................................................................................... 378 Table 254: Reference Voltage for tLZ(DQS), tHZ(DQS) Timing Measurements .................................................. 381 Table 255: Reference Voltage for tLZ(DQ), tHZ(DQ) Timing Measurements ..................................................... 383 Table 256: Internal VREF(CA) Specifications ..................................................................................................... 384 Table 257: Internal VREF(DQ) Specifications .................................................................................................... 385 Table 258: Pull-Down Driver Characteristics ­ ZQ Calibration ........................................................................ 387

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

19

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Features
Table 259: Pull-Up Characteristics ­ ZQ Calibration ....................................................................................... 387 Table 260: Terminated Valid Calibration Points .............................................................................................. 387 Table 261: Command Bus ODT State ............................................................................................................. 388 Table 262: ODT DC Electrical Characteristics for Command/Address Bus ­ up to 3200 Mb/s ........................... 389 Table 263: ODT DC Electrical Characteristics for Command/Address Bus ­ Beyond 3200 Mb/s ....................... 390 Table 264: ODT DC Electrical Characteristics for DQ Bus­ up to 3200 Mb/s .................................................... 391 Table 265: ODT DC Electrical Characteristics for DQ Bus ­ Beyond 3200 Mb/s ................................................ 392 Table 266: Output Driver and Termination Register Sensitivity Definition ....................................................... 393 Table 267: Output Driver and Termination Register Temperature and Voltage Sensitivity ................................. 393 Table 268: Recommended DC Operating Conditions ..................................................................................... 394 Table 269: Single-Ended Output Slew Rate .................................................................................................... 394 Table 270: Differential Output Slew Rate ....................................................................................................... 395

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

20

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Important Notes and Warnings
Important Notes and Warnings
Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions. This document supersedes and replaces all information supplied prior to the publication hereof. You may not rely on any information set forth in this document if you obtain the product described herein from any unauthorized distributor or other source not authorized by Micron.
Automotive Applications. Products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distributor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting directly or indirectly from any use of nonautomotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and conditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting from any use of non-automotive-grade products in automotive applications.
Critical Applications. Products are not authorized for use in applications in which failure of the Micron component could result, directly or indirectly in death, personal injury, or severe property or environmental damage ("Critical Applications"). Customer must protect against death, personal injury, and severe property and environmental damage by incorporating safety design measures into customer's applications to ensure that failure of the Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron component for any critical application, customer and distributor shall indemnify and hold harmless Micron and its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, or death arising in any way out of such critical application, whether or not Micron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the Micron product.
Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems, applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAILURE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included in customer's applications and products to eliminate the risk that personal injury, death, or severe property or environmental damages will result from failure of any semiconductor component.
Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort, warranty, breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly authorized representative.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

21

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP MCP General Description
MCP General Description
Micron MCP products combine NAND Flash and Mobile LPDRAM devices in a single MCP. These products target mobile applications with low-power, high-performance, and minimal package-footprint design requirements. The NAND Flash and Mobile LPDRAM devices are also members of the Micron discrete memory products portfolio.
The NAND Flash and Mobile LPDRAM devices are packaged with separate interfaces (no shared address, control, data, or power balls). This bus architecture supports an optimized interface to processors with separate NAND Flash and Mobile LPDRAM buses. The NAND Flash and Mobile LPDRAM devices have separate core power connections and share a common ground (that is, VSS is tied together on the two devices).
The bus architecture of this device also supports separate NAND Flash and Mobile LPDRAM functionality without concern for device interaction.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

22

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Ball Assignments and Descriptions
Ball Assignments and Descriptions

Figure 3: 149-Ball WFBGA (x16 LPDDR) Ball Assignments

1

2

3

4

5

6

7

8

9

A

DNU

DNU

B

DNU

NC

NC

NC

NC

NC

NC

C

NC

NC

D

NC

NC

E

F

DQ10

VDD2

G

DQ11

VDDQ

H

DMI1

VSS

J

DQ13

VSS

K

NC

WP#

NC

NC

DQ8 VDDQ VDDQ VSS

DQ9 VSS DQ14 VSS

R/B# CE# VDD2 VSS DQ12 VSS VDD2

VSSm VSSm VDD2 VSS VDDQ DQ15 VDD2

WE# RE# VDD2 DQS1_t DQS1_c VDDQ VDD2

L

M DQ3

N

DQ2

P

DQ1

R

DNU

T

DNU

VSS VSS DQ0 VDD1 DNU

DMI0 VSS VDDQ VDD2

VSS DQ5 VSS VDDQ

DQ6 VSS DQ4 VDDQ

VSS DQ7 VSS VDD2

DQS0_c DQS0_t
VDD2 VDD1

1

2

3

4

5

6

7

8

9

Top View (ball down)

NAND

DDR4_A (Channel A)

ZQ, ODT_CA, RESET

10

11

12

NC VSSm ALE VSSm CLE

NC IO7 VSSm IO2 VSSm ODT_ca VSS VSS CA1 CA4 CA3 CA2 VDD2 VDDQ

VCC IO6 VSSm IO5 VSSm NC NC CA0 VSS VSS VSS VSS VDD2 VDDQ

10

11

12

13 DNU NC VCC IO1 VCC IO3 NC VSS VSS RFU CS0 VSS CA5 VDD1 VDD1 DNU

14 DNU DNU NC IO4 VCC IO0 NC CLK_t CLK_c RFU CKE0 RESET_n RFU ZQ0 DNU DNU

13

14

Supply

Ground

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

23

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Ball Assignments and Descriptions

Table 4: x8 NAND Ball Descriptions

Symbol ALE
CE# CLE
RE# WE# WP# I/O[7:0] (x8)
R/B#
VCC

Type Input
Input Input
Input Input Input Input/ output
Output
Supply

Description
Address latch enable: When ALE is HIGH, addresses can be transferred to the on-chip address register.
Chip enable: Gates transfers between the host system and the NAND device.
Command latch enable: When CLE is HIGH, commands can be transferred to the on-chip command register.
Read enable: Gates information from the NAND device to the host system.
Write enable: Gates information from the host system to the NAND device.
Write protect: Driving WP# LOW blocks ERASE and PROGRAM operations.
Data inputs/outputs: The bidirectional I/Os transfer address, data, and instruction information. Data is output only during READ operations; at other times the I/Os are inputs. for NAND x8 devices.
Ready/busy: Open-drain, active-LOW output that indicates when an internal operation is in progress.
VCC: NAND power supply.

Note: 1. Balls marked RFU may or may not be connected internally. These balls should not be used. Contact factory for details.

Table 5: x16 LPDDR Ball Descriptions

Symbol CK_t, CK_c
CKE0, CKE1
CS0, CS1 CA[5:0]
ODT_ca
DQ0[15:0] DQS0_t, DQS0_c, DQS1_t, DQS1_c

Type Input
Input
Input Input
Input
I/O I/O

Description
Clock: CK_t and CK_c are differential clock inputs. All address, command and control input signals are sampled on positive edge of CK_t and the negative edge of CK_c. AC timings for CA parameters are referenced to clock. Each channel (A, B, C, and D) has its own clock pair.
Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock signals, input buffers, and output drivers. Power-saving modes are entered and exited via CKE transitions. CKE is sampled at the rising edge of CK.
Chip select: Each channel (A, B, C, and D) has its own CS signals.
Command/address inputs: Provide the command and address inputs according to the command truth table. Each channel (A, B, C, and D) has its own CA signals.
CA ODT control: The ODT_CA pin is ignored by LPDDR4X devices. CA ODT is fully controlled through MR11 and MR22. The ODT_CA pin shall be connected to a valid logic level.
Data input/output: Bidirectional data bus.
Data strobe: DQS_t and DQS_c are bi-directional differential output clock signals used to strobe data during a READ or WRITE. The data strobe is generated by the DRAM for a READ and is edge-aligned with data. The data strobe is generated by the SoC memory controller for a WRITE and is trained to precede data. Each byte of data has a data strobe signal pair. Each channel (A, B, C, and D) has its own DQS_t and DQS_c strobes.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

24

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Ball Assignments and Descriptions

Table 5: x16 LPDDR Ball Descriptions (Continued)

Symbol DMI[1:0]
ZQ0, ZQ1 VDD1, VDD2 , VDDQ
VSS RESET_n
NC

Type I/O
Reference Supply Supply Input ­

Description
Data mask/Data bus inversion: DMI is a dual use bi-directional signal used to indicate data to be masked, and data which is inverted on the bus. For data bus inversion (DBI), the DMI signal is driven HIGH when the data on the data bus is inverted, or driven LOW when the data is in its normal state. DBI can be disabled via a mode register setting. For data mask, the DMI signal is used in combination with the data lines to indicate data to be masked in a MASK WRITE command (see the Data Mask (DM) and Data Bus Inversion (DBI) sections for details). The data mask function can be disabled via a mode register setting. Each byte of data has a DMI signal. Each channel has its own DMI signals.
ZQ calibration reference: Used to calibrate the output drive strength and the termination resistance. The ZQ pin shall be connected to VDDQ through a 240 ±1% resistor.
Power supplies: Isolated on the die for improved noise immunity.
Ground reference: Power supply ground reference.
RESET: When asserted LOW, the RESET pin resets all channels of the die.
No connect: Not internally connected.

Note: 1. Balls marked RFU may or may not be connected internally. These balls should not be used. Contact factory for details.

Table 6: Non-Device-Specific Descriptions

Symbol VSS
Symbol DNU NC RFU1

Type Supply Type
­ ­ ­

Description

VSS: Shared ground.

Description

Do not use: Must be grounded or left floating.

No connect: Not internally connected.

Reserved for future use.

Note: 1. Balls marked RFU may or may not be connected internally. These balls should not be used. Contact factory for details.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

25

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Device Diagrams
Device Diagrams
Figure 4: 149-Ball Functional Block Diagram (LPDDR)

CE# CLE ALE RE# WE# WP#

NAND Flash

RESET_n CS0
CKE0 CK_t CK_c CA[5:0]
ODT_ca

LPDDR4
ODTca

VCC
I/O
R/B# VSS
VDDQ ZQ0 RZQ0 VDD1 VDD2 VDDQ VSS
DMI[1:0] DQ DQS[1:0]_t DQS[1:0]_c

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

26

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Package Dimensions

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Package Dimensions

Figure 5: 149-Ball WFBGA

Seating plane

A

0.08 A

149X Ø0.319 Dimensions apply to solder balls postreflow on Ø0.30 SMD ball pads.

Ball A1 ID (covered by SR)
1413121110 9 8 7 6 5 4 3 2 1

A

B

C

D

E

9.5 ±0.1

F G

7.5 CTR

H J

K

L

M

N

P

0.5 TYP

R T

0.5 TYP

0.7 ±0.1

6.5 CTR

0.214 ±0.05

8 ±0.1
Notes: 1. All dimensions are in millimeters. 2. Package height does not include room temperature warpage.

Ball A1 ID

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

27

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP 4Gb: x8, x16 NAND Flash Memory

4Gb: x8, x16 NAND Flash Memory

Features

· Open NAND Flash Interface (ONFI) 1.0-compliant1 · Single-level cell (SLC) technology · Organization
­ Page size x8: 4352 bytes (4096 + 256 bytes) ­ Page size x16: 2176 words (2048 + 128 words) ­ Block size: 64 pages ­ Plane size: 1 ­ Device size: 4Gb: 2048 blocks · Asynchronous I/O performance ­ tRC/tWC: 20ns (3.3V), 30ns (1.8V) · Array performance ­ Read page: 25µs ­ Program page: 200µs (TYP) ­ Erase block: 2ms (TYP) · Command set: ONFI NAND Flash Protocol · Advanced command set ­ Program page cache mode ­ Read page cache mode ­ Permanent block locking (blocks 47:0) ­ One-time programmable (OTP) mode ­ Block lock ­ Programmable drive strength ­ Read unique ID ­ Internal data move · Operation status byte provides software method for detecting ­ Operation completion ­ Pass/fail condition ­ Write-protect status · Ready/Busy# (R/B#) provides a hardware method of detecting operation completion · WP#: Write protect entire device · Blocks 7­0 are valid when shipped from factory with ECC. For minimum required ECC, see Error Management. · RESET (FFh) required as first command after power-on · Alternate method of device initialization after power-up (contact factory) · Internal data move operations supported within the plane from which data is read · Quality and reliability ­ Endurance: 100,000 PROGRAM/ERASE cycles IT temperature range ­ Endurance: 60,000 PROGRAM/ERASE cycles AT temperature range ­ Data retention: JESD47G-compliant; see qualification report · Additional: Uncycled data retention: 10 years 24/7 @ 85°C

Note: 1. The ONFI 1.0 specification is available at www.onfi.org.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

28

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP General Description
General Description
Micron NAND Flash devices include an asynchronous data interface for high-performance I/O operations. These devices use a highly multiplexed 8-bit bus (I/Ox) to transfer commands, address, and data. There are five control signals used to implement the asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control hardware write protection and monitor device status (R/B#).
This hardware interface creates a low pin-count device with a standard pinout that remains the same from one density to another, enabling future upgrades to higher densities with no board redesign.
A target is the unit of memory accessed by a chip enable signal. A target contains one or more NAND Flash die. A NAND Flash die is the minimum unit that can independently execute commands and report status. A NAND Flash die, in the ONFI specification, is referred to as a logical unit (LUN). There is at least one NAND Flash die per chip enable signal. For further details, see Device and Array Organization.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

29

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Architecture

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Architecture
These devices use NAND Flash electrical and command interfaces. Data, commands, and addresses are multiplexed onto the same pins and received by I/O control circuits. The commands received at the I/O control circuits are latched by a command register and are transferred to control logic circuits for generating internal signals to control device operations. The addresses are latched by an address register and sent to a row decoder to select a row address, or to a column decoder to select a column address.
Data is transferred to or from the NAND Flash memory array, byte by byte (x8) or word by word (x16), through a data register and a cache register.
The NAND Flash memory array is programmed and read using page-based operations and is erased using block-based operations. During normal page operations, the data and cache registers act as a single register. During cache operations, the data and cache registers operate independently to increase data throughput. The status register reports the status of die operations.

Figure 6: NAND Flash Die (LUN) Functional Block Diagram

VCC VSS

I/Ox

I/O control

Address register

Status register

CE# CLE ALE WE# RE# WP# LOCK
R/B#

Command register
Control logic

Row decode

Column decode
NAND Flash array
Data register Cache register
ECC

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

30

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Device and Array Organization
Device and Array Organization

Figure 7: Array Organization - MT29F4G08 4352 bytes

Cache Register

4096

256

Data Register

4096

256

IO0 IO7

2048 blocks per plane
1 plane per device

1 block

1 page = (4K + 256) bytes 1 block = (4K + 256) bytes x 64 pages 1 plane = 2048 blocks

Table 7: Array Addressing (×8)

Cycle First Second Third Fourth Fifth

I/07 CA7 LOW BA7 BA15 LOW

I/06 CA6 LOW BA6 BA14 LOW

I/05 CA5 LOW PA5 BA13 LOW

I/04 CA4 CA122 PA4 BA12 LOW

I/03 CA3 CA11 PA3 BA11 LOW

I/02 CA2 CA10 PA2 BA10 LOW

I/01 CA1 CA9 PA1 BA9 LOW

I/00 CA0 CA8 PA0 BA8 BA16

Notes: 1. Block address concatenated with page address = actual page address. CAx = column address; PAx = page address; BAx = block address.
2. If CA12 is 1, then CA[11:8] must be 0.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

31

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Device and Array Organization
Figure 8: Array Organization - MT29F8G08

Cache Register Data Register
2048 blocks per device

4352 bytes

4352 bytes

4096

256

4096

256

4096

256 4096

256

1 block

1 block

Serial data
1 page = (4K + 256 bytes) 1 block = (4K + 256) bytes x 64 pages 1 plane = 2048 blocks 1 device = 2 die, each single plane

Table 8: Array Addressing (×8)

Cycle First Second Third Fourth Fifth

I/07 CA7 LOW BA7 BA15 LOW

I/06 CA6 LOW BA6 BA14 LOW

I/05 CA5 LOW PA5 BA13 LOW

I/04 CA4 CA122 PA4 BA12 LOW

I/03 CA3 CA11 PA3 BA11 LOW

I/02 CA2 CA10 PA2 BA10 LOW

I/01 CA1 CA9 PA1 BA9 LUA03

I/00 CA0 CA8 PA0 BA8 BA16

Notes:

1. Block address concatenated with page address = actual page address. CAx = column address; PAx = page address; BAx = block address.
2. If CA12 is 1, then CA[11:8] must be 0.
3. LUA0 is used to select die in multi-LUN configuration.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

32

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Device and Array Organization

Figure 9: Array Organization - MT29F4G16 Logical Unit (LUN) 2176 words

Cache Register

2048

128

Data Register

2048

128

IO15 IO0

2048 blocks per plane
1 plane per LUN

1 Block

1 page = (2K + 128) words 1 block = (2K + 128) words x 64 pages 1 plane = 2048 blocks

Table 9: Array Addressing (×16)

Cycle First Second Third Fourth Fifth

I/O[15:8] LOW LOW LOW LOW LOW

I/07 CA7 LOW BA7 BA15 LOW

I/06 CA6 LOW BA6 BA14 LOW

I/05 CA5 LOW PA5 BA13 LOW

I/04 CA4 LOW PA4 BA12 LOW

I/03 CA3 CA112 PA3 BA11 LOW

I/02 CA2 CA10 PA2 BA10 LOW

I/01 CA1 CA9 PA1 BA9 LOW

I/00 CA0 CA8 PA0 BA8 BA16

Notes: 1. Block address concatenated with page address = actual page address. CAx = column address; PAx = page address; BAx = block address.
2. If CA11 is 1, then CA[10:7] must be 0.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

33

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Asynchronous Interface Bus Operation
Asynchronous Interface Bus Operation
The bus on the device is multiplexed. Data I/O, addresses, and commands all share the same pins. I/O[15:8] are used only for data in the ×16 configuration. Addresses and commands are always supplied on I/O[7:0].
The command sequence typically consists of a COMMAND LATCH cycle, ADDRESS INPUT cycles, and one or more DATA cycles, either READ or WRITE.

Table 10: Asynchronous Interface Mode Selection

Mode1 Standby2 Command input

CE#

CLE

ALE

WE#

RE#

I/Ox

WP#

H

X

X

X

X

X

0V/VCC

L

H

L

H

X

H

Address input

L

L

H

H

X

H

Data input

L

L

L

H

X

H

Data output

L

L

L

H

X

X

Write protect

X

X

X

X

X

X

L

Notes:

1. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = VIH or VIL.
2. WP# should be biased to CMOS LOW or HIGH for standby.

Asynchronous Enable/Standby
When the device is not performing an operation, the CE# pin is typically driven HIGH and the device enters standby mode. The memory will enter standby if CE# goes HIGH while data is being transferred and the device is not busy. This helps to reduce power consumption.
The CE# "Don't Care" operation enables the NAND Flash to reside on the same asynchronous memory bus as other Flash or SRAM devices. Other devices on the memory bus can then be accessed while the NAND Flash is busy with internal operations. This capability is important for designs that require multiple NAND Flash devices on the same bus.
A HIGH CLE signal indicates that a command cycle is taking place. A HIGH ALE signal signifies that an ADDRESS INPUT cycle is occurring.

Asynchronous Commands
An asynchronous command is written from I/O[7:0] to the command register on the rising edge of WE# when CE# is LOW, ALE is LOW, CLE is HIGH, and RE# is HIGH.
Commands are typically ignored by die (LUNs) that are busy (RDY = 0); however, some commands, including READ STATUS (70h) and READ STATUS ENHANCED (78h), are accepted by die (LUNs) even when they are busy.
For devices with a ×16 interface, I/O[15:8] must be written with zeros when a command is issued.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

34

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Asynchronous Interface Bus Operation

Figure 10: Asynchronous Command Latch Cycle

CLE tCLS tCLH

tCS

tCH

CE#

WE# ALE

tWP tALS tALH

tDS tDH

I/Ox

COMMAND

Don't Care
Asynchronous Addresses
An asynchronous address is written from I/O[7:0] to the address register on the rising edge of WE# when CE# is LOW, ALE is HIGH, CLE is LOW, and RE# is HIGH.
Bits that are not part of the address space must be LOW (see Device and Array Organization). The number of cycles required for each command varies. Refer to the command descriptions to determine addressing requirements.
Addresses are typically ignored by die (LUNs) that are busy (RDY = 0); however, some addresses are accepted by die (LUNs) even when they are busy; for example, like address cycles that follow the READ STATUS ENHANCED (78h) command.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

35

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Asynchronous Interface Bus Operation

Figure 11: Asynchronous Address Latch Cycle

CLE
tCLS tCS

CE#

tWC

tWP

tWH

WE#
tALS tALH

ALE
tDS tDH

I/Ox

Col add 1

Col add 2

Row add 1

Row add 2

Row add 3

Don't Care

Undefined

Asynchronous Data Input
Data is written from I/O[7:0] to the cache register of the selected die (LUN) on the rising edge of WE# when CE# is LOW, ALE is LOW, CLE is LOW, and RE# is HIGH.
Data input is ignored by die (LUNs) that are not selected or are busy (RDY = 0). Data is written to the data register on the rising edge of WE# when CE#, CLE, and ALE are LOW, and the device is not busy.
Data input utilizes I/O[7:0] on ×8 devices and I/O[15:0] on ×16 devices.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

36

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Asynchronous Interface Bus Operation

Figure 12: Asynchronous Data Input Cycles
CLE

CE# ALE WE# I/Ox

tALS

tWC tWP

tWP

tWH tDS tDH
DIN M

tDS tDH DIN M+1

tCLH
tCH tWP
tDS tDH DIN N

Don't Care

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

37

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Asynchronous Interface Bus Operation
Asynchronous Data Output
Data can be output from a die (LUN) if it is in a ready state. Data output is supported following a READ operation from the NAND Flash array. Data is output from the cache register of the selected die (LUN) to IO bus on the falling edge of RE# when CE# is LOW, ALE is LOW, CLE is LOW, and WE# is HIGH.
If the host controller is using a tRC of 30ns or greater, the host can latch the data on the rising edge of RE# (see the figure below for proper timing). If the host controller is using a tRC of less than 30ns, the host can latch the data on the next falling edge of RE#.
Using the READ STATUS ENHANCED (78h) command prevents data contention following an interleaved die (multi-LUN) operation. After issuing the READ STATUS ENHANCED (78h) command, to enable data output, issue the READ MODE (00h) command.
Data output requests are typically ignored by a die (LUN) that is busy (RDY = 0); however, it is possible to output data from the status register even when a die (LUN) is busy by first issuing the READ STATUS or READ STATUS ENHANCED (78h) command.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

38

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Asynchronous Interface Bus Operation

Figure 13: Asynchronous Data Output Cycles
tCEA
CE#

tREA tRP

tREH

tREA

RE#
tRHZ

I/Ox RDY

DOUT

tRR

tRC

DOUT

tREA

tCHZ tCOH

tRHZ tRHOH
DOUT

Don't Care

Figure 14: Asynchronous Data Output Cycles (EDO Mode)

CE# tRC
tRP tREH

RE#

tREA tCEA

tREA tRLOH

I/Ox

DOUT

DOUT

tCHZ tCOH
tRHZ tRHOH
DOUT

RDY
Write Protect#

tRR
Don't Care
The write protect# (WP#) signal enables or disables PROGRAM and ERASE operations to a target. When WP# is LOW, PROGRAM and ERASE operations are disabled. When WP# is HIGH, PROGRAM and ERASE operations are enabled.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

39

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Ready/Busy#

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Asynchronous Interface Bus Operation
It is recommended that the host drive WP# LOW during power-on until V CC is stable to prevent inadvertent PROGRAM and ERASE operations (see Device Initialization for additional details). WP# must be transitioned only when the target is not busy and prior to beginning a command sequence. After a command sequence is complete and the target is ready, WP# can be transitioned. After WP# is transitioned, the host must wait tWW before issuing a new command. The WP# signal is always an active input, even when CE# is HIGH. This signal should not be multiplexed with other signals.

The ready/busy# (R/B#) signal provides a hardware method of indicating whether a target is ready or busy. A target is busy when one or more of its die (LUNs) are busy (RDY = 0). A target is ready when all of its die (LUNs) are ready (RDY = 1). Because each die (LUN) contains a status register, it is possible to determine the independent status of each die (LUN) by polling its status register instead of using the R/B# signal (see Status Operations for details regarding die (LUN) status).
This signal requires a pull-up resistor, Rp, for proper operation. R/B# is HIGH when the target is ready, and transitions LOW when the target is busy. The signal's open-drain driver enables multiple R/B# outputs to be OR-tied. Typically, R/B# is connected to an interrupt pin on the system controller.
The combination of Rp and capacitive loading of the R/B# circuit determines the rise time of the R/B# signal. The actual value used for Rp depends on the system timing requirements. Large values of Rp cause R/B# to be delayed significantly. Between the 10% and 90% points on the R/B# waveform, the rise time is approximately two time constants (TC).

TC = R × C Where R = Rp (resistance of pull-up resistor), and C = total capacitive load.

The fall time of the R/B# signal is determined mainly by the output impedance of the R/B# signal and the total load capacitance. Approximate Rp values using a circuit load of 100pF are provided in Figure 18 (page 42).
The minimum value for Rp is determined by the output drive capability of the R/B# signal, the output voltage swing, and VCC.

Rp

=

VCC

(MAX) IOL

- VOL + IL

(MAX)

Where IL is the sum of the input currents of all devices tied to the R/B# pin.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

40

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Asynchronous Interface Bus Operation
Figure 15: READ/BUSY# Open Drain

VCC

Rp

R/B# Open drain output

IOL
VSS Device

Figure 16: tFall and tRise (3.3V VCC) 3.50

3.00

2.50 2.00 V 1.50

tFall tRise

1.00

0.50

0.00 ­1

0

2

4

0

2

4

6

TC

VCC 3.3V

Notes:

1. tFall and tRise calculated at 10% and 90% points. 2. tRise dependent on external capacitance and resistive loading and output transistor im-
pedance. 3. tRise primarily dependent on external pull-up resistor and external capacitive loading. 4. tFall = 10ns at 3.3V.
5. See TC values in Figure 18 (page 42) for approximate Rp value and TC.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

41

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Asynchronous Interface Bus Operation

Figure 17: IOL vs. Rp (VCC = 3.3V VCC) 3.50 3.00 2.50 2.00
I (mA) 1.50 1.00 0.50 0.00 0
Figure 18: TC vs. Rp

2000

400 0

6000 8000 Rp ()

10,000 12,000 IOL at VCC (MAX)

1200
1000
800
TC (ns) 600
400
200
0 0

2000

4000

6000 8000
Rp (W)

10,000 12,000 IOL at VCC (MAX) RC = TC C = 100pF

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

42

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Device Initialization
Device Initialization
Micron NAND Flash devices are designed to prevent data corruption during power transitions. VCC is internally monitored. (The WP# signal supports additional hardware protection during power transitions.) When ramping V CC, use the following procedure to initialize the device:
1. Ramp VCC. 2. The host must wait for R/B# to be valid and HIGH before issuing RESET (FFh) to
any target. The R/B# signal becomes valid when 50µs has elapsed since the beginning the VCC ramp, and 10µs has elapsed since VCC reaches VCC,min. 3. If not monitoring R/B#, the host must wait at least 100µs after VCC reaches VCC,min. If monitoring R/B#, the host must wait until R/B# is HIGH. 4. The asynchronous interface is active by default for each target. Each LUN draws less than an average of 10mA (IST) measured over intervals of 1ms until the RESET (FFh) command is issued. 5. The RESET (FFh) command must be the first command issued to all targets (CE#s) after the NAND Flash device is powered on. Each target will be busy for 1ms after a RESET command is issued. The RESET busy time can be monitored by polling R/B# or issuing the READ STATUS (70h) command to poll the status register. 6. The device is now initialized and ready for normal operation.

Figure 19: R/B# Power-On Behavior

50µs (MIN)

VCC = VCC (MIN)

VCC

10µs

(MAX)

R/B#

VCsCtarratms p

100µs (MAX)

Reset (FFh) is issued
Invalid

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

43

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Power Cycle Requirements

Power Cycle Requirements
Upon power-down the NAND device requires a maximum voltage and minimum time that the host must hold VCC and VCCQ below the voltage prior to power-on.

Table 11: Power Cycle Requirements

Device can not operate correctly when VCC is lower than 2.5V@3.3V or 1.5V@1.8V.

Parameter

Value

Unit

Maximum VCC/VCCQ Minimum time below maximum voltage

100

mV

100

nS

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

44

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

Command Definitions

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Command Definitions

Table 12: Command Set

Command

Command Cycle #1

Reset Operations

RESET

FFh

Identification Operation

READ ID

90h

READ PARAMETER PAGE

ECh

READ UNIQUE ID

EDh

Feature Operations

GET FEATURES

EEh

SET FEATURES

EFh

Status Operations

READ STATUS

70h

READ STATUS EN-

78h

HANCED

Column Address Operations

RANDOM DATA READ

05h

RANDOM DATA INPUT

85h

PROGRAM FOR

85h

INTERNAL DATA MOVE

READ Operations

READ MODE

00h

READ PAGE

00h

READ PAGE CACHE SE-

31h

QUENTIAL

READ PAGE CACHE

00h

RANDOM

READ PAGE CACHE LAST

3Fh

Program Operations

PROGRAM PAGE

80h

PROGRAM PAGE CACHE

80h

Erase Operations

ERASE BLOCK

60h

Internal Data Move Operations

READ FOR INTERNAL

00h

DATA MOVE

Number of Valid
Address Cycles
0
1 1 1
1 1
0 3
2 2 5
0 5 0
5
0
5 5
3
5

Data Input Cycles

Valid While

Command Selected LUN

Cycle #2

is Busy1

Valid While
Other LUNs are Busy1

Notes

­

­

Yes

Yes

­

­

­

No

­

­

No

­

­

No

No

­

No

­

No

­

­

­

No

4

­

No

No

­

No

­

­

­

Yes

N/A

­

­

­

Yes

Yes

2

­

E0h

No

Optional

­

No

Optional

­

No

Yes

­

Yes

­

Yes

3

­

­

No

­

30h

No

­

­

No

­

31h

No

­

­

No

Yes

10h

No

Yes

15h

No

­

D0h

No

­

35h

No

Yes

­

Yes

­

Yes

4

Yes

4

Yes

4

Yes

2

Yes

2, 5

Yes

­

Yes

3

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

45

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Command Definitions

Table 12: Command Set (Continued)

Command

Command Cycle #1

Number of Valid
Address Cycles

PROGRAM FOR INTER-

85h

5

NAL DATA MOVE

Block Lock Operations

BLOCK UNLOCK LOW

23h

3

BLOCK UNLOCK HIGH

24h

3

BLOCK LOCK

2Ah

­

BLOCK LOCK-TIGHT

2Ch

­

BLOCK LOCK READ

7Ah

3

STATUS

PERMANENT BOOT

­

­

BLOCK PROTECT

PERMANENT BOOT

83h

5

BLOCK PROTECT

PERMANENT BOOT

80h

5

BLOCK PROTECT Disable

One-Time Programmable (OTP) Operations

OTP DATA LOCK BY

80h

5

BLOCK (ONFI)

OTP DATA PROGRAM

80h

5

(ONFI)

OTP DATA READ (ONFI)

00h

5

Data Input Cycles
Optional

Valid While

Command Selected LUN

Cycle #2

is Busy1

10h

No

Valid While Other LUNs are Busy1
Yes

Notes ­

­

­

No

­

­

No

­

­

No

­

­

No

­

­

No

­

­

No

­

10h

No

Yes

10h

No

Yes

­

Yes

­

Yes

­

Yes

­

Yes

­

Yes

­

Yes

­

No

­

No

10h

No

Yes

10h

No

No

30h

No

No

6

No

6

No

6

Notes:

1. Busy means RDY = 0.
2. These commands can be used for interleaved die (multi-LUN) operations (applicable to Multi-LUN Operations).
3. Do not cross plane address boundaries when using READ for INTERNAL DATA MOVE and PROGRAM for INTERNAL DATA MOVE.
4. Issuing a READ PAGE CACHE series (31h, 00h-31h, 00h-32h, 3Fh) command when the array is busy (RDY = 1, ARDY = 0) is supported if the previous command was a READ PAGE (00h-30h) or READ PAGE CACHE series command; otherwise, it is prohibited.
5. Issuing a PROGRAM PAGE CACHE (80h-15h) command when the array is busy (RDY = 1, ARDY = 0) is supported if the previous command was a PROGRAM PAGE CACHE (80h-15h) command; otherwise, it is prohibited.
6. OTP commands can be entered only after issuing the SET FEATURES command with the feature address.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

46

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Reset Operations

Reset Operations

RESET (FFh)

The RESET command is used to put the memory device into a known condition and to abort the command sequence in progress.
READ, PROGRAM, and ERASE commands can be aborted while the device is in the busy state. The contents of the memory location being programmed or the block being erased are no longer valid. The data may be partially erased or programmed, and is invalid. The command register is cleared and is ready for the next command. The data register and cache register contents are marked invalid.
The status register contains the value E0h when WP# is HIGH; otherwise it is written with a 60h value. R/B# goes LOW for tRST after the RESET command is written to the command register.
The RESET command must be issued to all CE#s as the first command after power-on. The device will be busy for a maximum of 1ms.

Figure 20: RESET (FFh) Operation

CLE

CE# WE# R/B#

tWB

tRST

I/O[7:0]

FFh RESET command

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

47

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Identification Operations

Identification Operations

READ ID (90h)

The READ ID (90h) command is used to read identifier codes programmed into the target. This command is accepted by the target only when all die (LUNs) on the target are idle.
Writing 90h to the command register puts the target in read ID mode. The target stays in this mode until another valid command is issued.
When the 90h command is followed by an 00h address cycle, the target returns a 5-byte identifier code that includes the manufacturer ID, device configuration, and part-specific information.
When the 90h command is followed by a 20h address cycle, the target returns the 4-byte ONFI identifier code.

Figure 21: READ ID (90h) with 00h Address Operation

Cycle type I/O[7:0]

Command Address tWHR

90h

00h

DOUT

DOUT

DOUT

DOUT

DOUT

Byte 0 Byte 1 Byte 2 Byte 3 Byte 4

Note: 1. See READ ID Parameter tables for byte definitions. Figure 22: READ ID (90h) with 20h Address Operation

Cycle type I/O[7:0]

Command Address tWHR

90h

20h

DOUT

DOUT

DOUT

DOUT

4Fh

4Eh

46h

49h

Note: 1. See READ ID Parameter tables for byte definitions.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

48

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

READ ID Parameter Tables

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP READ ID Parameter Tables

Table 13: READ ID Parameters for Address 00h

Byte

Options

I/07 I/06 I/05 I/04 I/03 I/02 I/01 I/00 Value

Byte 0 ­ Manufacturer ID

Manufacturer

Micron

0

0

1

0

1

1

0

0

2Ch

Byte 1 ­ Device ID

MT29F4G08ABBFA

4Gb, ×8, 1.8V

1

0

1

0

1

1

0

0

ACh

MT29F4G16ABBFA

4Gb, ×16, 1.8V

1

0

1

1

1

1

0

0

BCh

MT29F4G08ABAFA

4Gb, ×8, 3.3V

1

1

0

1

1

1

0

0

DCh

MT29F4G16ABAFA

4Gb, ×16, 3.3V

1

1

0

0

1

1

0

0

CCh

MT29F8G08ADAFA

8Gb, ×8, 3.3V

1

1

0

1

0

0

1

1

D3h

MT29F8G08ADBFA

8Gb, ×8, 1.8V

1

0

1

0

0

0

1

1

A3h

Byte 2

Number of die per CE

1

0

0

00b

Cell type

SLC

0

0

00b

Number of simultaneously 1 (4Gb)

0

0

00b

programmed pages

2 (8Gb)

0

1

01b

Interleaved operations

Not supported (4Gb)

0

0b

between multiple die

Supported (8Gb)

1

1b

Cache programming

Supported

1

1b

Byte value

4Gb

1

0

0

0

0

0

0

0

80h

8Gb

1

1

0

1

0

0

0

0

D0h

Byte 3

Page size

4KB

1

0

10b

Spare area size (bytes)

256B

1

1b

Block size (without spare) 256KB

1

0

10b

Organization

×8

0

0b

Organization

×16

1

1b

Serial access

1.8V

30ns

0

0

0b

(MIN)

3.3V

20ns

1

0

10b

Byte value

×8, 1.8V

0

0

1

0

0

1

1

0

26h

×8, 3.3V

1

0

1

0

0

1

1

0

A6h

×16, 1.8V

0

1

1

0

0

1

1

0

66h

×16, 3.3V

1

1

1

0

0

1

1

0

E6h

Byte 4

Internal ECC level

8-bit ECC/512B (main) + 16B (Spare)+16B (parity) bytes

1

0

10b

Planes per CE#

1

0

0

00b

2

0

1

01b

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

49

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP READ ID Parameter Tables

Table 13: READ ID Parameters for Address 00h (Continued)

Byte Plane size Internal ECC
Byte value

Options 4Gb ECC Disabled ECC Enabled 4Gb 8Gb

I/07 I/06 I/05 I/04 I/03 I/02 I/01 I/00 Value

1

1

0

110b

0

0b

1

1b

x

1

1

0

0

0

1

0

62h

x

1

1

0

0

1

1

0

66h

Note: 1. b = binary; h = hexadecimal.

Table 14: READ ID Parameters for Address 20h

Byte

Options

I/07

I/06

I/05

I/04

I/03

I/02

I/01

I/00

Value

0

"O"

0

1

0

0

1

1

1

1

4Fh

1

"N"

0

1

0

0

1

1

1

0

4Eh

2

"F"

0

1

0

0

0

1

1

0

46h

3

"I"

0

1

0

0

1

0

0

1

49h

4

Undefined

X

X

X

X

X

X

X

X

XXh

Note: 1. h = hexadecimal; X = VIH or VIL.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

50

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP READ PARAMETER PAGE (ECh)
READ PARAMETER PAGE (ECh)
The READ PARAMETER PAGE (ECh) command is used to read the ONFI parameter page programmed into the target. This command is accepted by the target only when all die (LUNs) on the target are idle.
Writing ECh to the command register puts the target in read parameter page mode. The target stays in this mode until another valid command is issued.
When the ECh command is followed by an 00h address cycle, the target goes busy for tR. If the READ STATUS (70h) command is used to monitor for command completion, the READ MODE (00h) command must be used to re-enable data output mode. Use of the READ STATUS ENHANCED (78h) command is prohibited while the target is busy and during data output.
A minimum of three copies of the parameter page are stored in the device. Each parameter page is 256 bytes. If desired, the RANDOM DATA READ (05h-E0h) command can be used to change the location of data output.

Figure 23: READ PARAMETER (ECh) Operation
Cycle type Command Address

DOUT

DOUT

DOUT

DOUT

DOUT

DOUT

I/O[7:0]

ECh

00h

tWB

R/B#

P00

P10

...

P01

P11

...

tR

tRR

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

51

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Parameter Page Data Structure Table
Parameter Page Data Structure Table

Table 15: Parameter Page Data Structure

Byte 0­3 4­5 6­7
8­9 10­31 32­43 44­63
64 65­66 67­79 80­83 84­85 86­89
90­91
92­95

Features Supported

Description Parameter page signature Revision number 4Gb (x8 I/O) 4Gb (x16 I/O) 8Gb (x8 I/O) Optional commands support Reserved Device manufacturer

Device model

MT29F4G08ABAFAH4

MT29F4G16ABAFAH4

MT29F4G08ABAFAWP

MT29F8G08ADAFAH4

MT29F8G08ADAFAWP

MT29F8G08ADBFAH4

MT29F4G08ABBFAH4

MT29F4G16ABBFAH4

Manufacturer ID
Date code
Reserved
Number of data bytes per page
Number of spare bytes per page
Number of data bytes per partial page (AIT)
Number of data bytes per partial page (AAT)
Number of spare bytes per partial page (AIT)
Number of spare bytes per partial page (AAT)
Number of pages per block

Value (hex) 4Fh, 4Eh, 46h, 49h 02h, 00h 10h, 00h 11h, 00h 12h, 00h 3Fh, 00h 00h 4Dh, 49h, 43h, 52h, 4Fh, 4Eh, 20h, 20h, 20h, 20h, 20h, 20h 4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 30h, 38h, 41h, 42h, 41h, 46h, 41h, 48h, 34h, 20h, 20h, 20h, 20h 4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 31h, 36h, 41h, 42h, 41h, 46h, 41h, 48h, 34h, 20h, 20h, 20h, 20h 4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 30h, 38h, 41h, 42h, 41h, 46h, 41h, 57h, 50h, 20h, 20h, 20h, 20h 4Dh, 54h, 32h, 39h, 46h, 38h, 47h, 30h, 38h, 41h, 44h, 41h, 46h, 41h, 48h, 34h, 20h, 20h, 20h, 20h 4Dh, 54h, 32h, 39h, 46h, 38h, 47h, 30h, 38h, 41h, 44h, 41h, 46h, 41h, 57h, 50h, 20h, 20h, 20h, 20h 4Dh, 54h, 32h, 39h, 46h, 38h, 47h, 30h, 38h, 41h, 44h, 42h, 46h, 41h, 48h, 34h, 20h, 20h, 20h, 20h 4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 30h, 38h, 41h, 42h, 42h, 46h, 41h, 48h, 34h, 20h, 20h, 20h, 20h 4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 31h, 36h, 41h, 42h, 42h, 46h, 41h, 48h, 34h, 20h, 20h, 20h, 20h 2Ch 00h 00h 00h, 10h, 00h, 00h 00h, 01h 00h, 04h, 00h, 00h
00h, 10h, 00h, 00h
40h, 00h
00h, 01h
40h, 00h, 00h, 00h

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

52

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Parameter Page Data Structure Table

Table 15: Parameter Page Data Structure (Continued)

Byte 96­99 100
101 102 103­104 105­106
107
108­109
110
111 112 113 114 115­127 128 129­130
131­132
133­134 135­136 137­138 139­140 141­163 164­165 166­179
180­247 248 249 250­253 254­255

Timing mode support
Program cache timing mode support

Description

Value (hex)

Number of blocks per unit

00h, 08h, 00h, 00h

Number of logical units (4Gb)

01h

Number of logical units (8Gb)

02h

Number of address cycles

23h

Number of bits per cell

01h

Bad blocks maximum per unit

28h, 00h

Block endurance (AIT)

01h, 05h

Block endurance (AAT)

06h, 04h

Guaranteed valid blocks at begin- 08h ning of target

Block endurance for guaranteed 00h valid blocks

Number of programs per page

04h

(AIT)

Number of programs per page

01h

(AAT)

Partial programming attributes 00h

Number of ECC bits

08h

Number of interleaved address bits 01h

Interleaved operation attributes 0Eh

Reserved

00h

I/O pin capacitance

08h

VCC = 3.3V VCC = 1.8V VCC = 3.3V VCC = 1.8V tPROG (MAX) page program time

3Fh, 00h 0Fh, 00h 3Fh, 00h 0Fh, 00h 58h, 02h

tERS (MAX) block erase time

10h, 27h

tR (MAX) page read time

19h, 00h

tCCS (MIN)

64h, 00h

Reserved

00h

Vendor-specific revision number 01h, 00h

Vendor-specific

00h, 00h, 00h, 02h, 04h, 80h, 01h, 81h, 04h, 03h, 02h, 01h, 30h, 90h

Reserved

00h

ECC maximum correct ability

00h

Die select feature

00h

Reserved

00h

Integrity CRC

Calculated

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

53

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Parameter Page Data Structure Table

Table 15: Parameter Page Data Structure (Continued)

Byte 256­512 513­768 769­2048

Description 2nd copy of the parameter table 3rd copy of the parameter table Additional redundant parameter pages

Value (hex)

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

54

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP READ UNIQUE ID (EDh)
READ UNIQUE ID (EDh)
The READ UNIQUE ID (EDh) command is used to read a unique identifier programmed into the target. This command is accepted by the target only when all die (LUNs) on the target are idle.
Writing EDh to the command register puts the target in read unique ID mode. The target stays in this mode until another valid command is issued.
When the EDh command is followed by an 00h address cycle, the target goes busy for tR. If the READ STATUS (70h) command is used to monitor for command completion, the READ MODE (00h) command must be used to re-enable data output mode.
After tR completes, the host enables data output mode to read the unique ID. When the asynchronous interface is active, one data byte is output per RE# toggle.
Sixteen copies of the unique ID data are stored in the device. Each copy is 32 bytes. The first 16 bytes of a 32-byte copy are unique data, and the second 16 bytes are the complement of the first 16 bytes. The host should XOR the first 16 bytes with the second 16 bytes. If the result is 16 bytes of FFh, then that copy of the unique ID data is correct. In the event that a non-FFh result is returned, the host can repeat the XOR operation on a subsequent copy of the unique ID data. If desired, the RANDOM DATA READ (05h-E0h) command can be used to change the data output location.
The upper eight I/Os on a x16 device are not used and are a "Don't Care" for x16 devices.

Figure 24: READ UNIQUE ID (EDh) Operation
Cycle type Command Address

DOUT

DOUT

DOUT

DOUT

DOUT

DOUT

I/O[7:0]

EDh

R/B#

00h tWB

U00

U10

...

U01

U11

...

tR

tRR

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

55

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Feature Operations
Feature Operations
The SET FEATURES (EFh) and GET FEATURES (EEh) commands are used to modify the target's default power-on behavior. These commands use a one-byte feature address to determine which sub-feature parameters will be read or modified. Each feature address (in the 00h to FFh range) is defined in below. The SET FEATURES (EFh) command writes sub-feature parameters (P1­P4) to the specified feature address. The GET FEATURES command reads the sub-feature parameters (P1­P4) at the specified feature address.

Table 16: Feature Address Definitions

Feature Address 00h 01h
02h­7Fh 80h 81h
82h­FFh 90h

Definition Reserved Timing mode Reserved Programmable output drive strength Programmable RB# pull-down strength Reserved Array operation mode

Table 17: Feature Addresses 90h: Timing Mode

Sub-feature Parameter P1 Timing mode
P2 P3 P4

Options

I/O7 I/O6 I/O5 I/O4 I/O3

Normal OTP operation OTP protection Disable ECC Enable ECC Permanent block lock disable

Reserved (0)

Reserved (0)

Reserved (0)

Reserved (0)

0

Reserved (0)

1

Reserved (0)

1

0

Reserved (0)

Reserved (0)

Reserved (0)

I/O2
0 0 0

I/O1
1 0 0 0

I/O0 Value Notes

0

00h

1

1

01h

1

03h

0

00h

3

0

08h 1, 2

0

10h

4

00h 00h 00h

Notes:

1. These bits are reset to 00h after power cycle.
2. Bit3 is used to enable/disable ECC. For ECC always on or ECC always off configuration, bit3 is reserved (0) and should be set to 0.
3. For MPNs with "-ITE" ECC enabled by default, this bit is Reserved.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

56

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Feature Operations

4. If Permanent block lock disable sequence is issued again to a part that has already been disabled, the part will be busy for tOBSY and exit with SR=60h. The part will be busy for tOBSY_ECC when ECC is enabled.
SET FEATURES (EFh)
The SET FEATURES (EFh) command writes the subfeature parameters (P1­P4) to the specified feature address to enable or disable target-specific features.
Writing EFh to the command register puts the target in the set features mode. The target stays in this mode until another command is issued. The EFh command is followed by a valid feature address. The host waits for tADL before the subfeature parameters are input. When the asynchronous interface is active, one subfeature parameter is latched per rising edge of WE#. After all four subfeature parameters are input, the target goes busy for tFEAT. The READ STATUS (70h) command can be used to monitor for command completion.
Feature address 01h (timing mode) operation is unique. If SET FEATURES is used to modify the interface type, the target will be busy for tITC.
Figure 25: SET FEATURES (EFh) Operation

Cycle type Command Address

DIN

tADL

I/O[7:0]

EFh

FA

P1

R/B#

DIN

DIN

DIN

P2

P3

P4

tWB

tFEAT

GET FEATURES (EEh)
The GET FEATURES (EEh) command reads the subfeature parameters (P1­P4) from the specified feature address. This command is accepted by the target only when all die (LUNs) on the target are idle.
Writing EEh to the command register puts the target in get features mode. The target stays in this mode until another valid command is issued.
When the EEh command is followed by a feature address, the target goes busy for tFEAT. If the READ STATUS (70h) command is used to monitor for command completion, the READ MODE (00h) command must be used to re-enable data output mode. During and prior to data output, use of the READ STATUS ENHANCED (78h) command is prohibited.
After tFEAT completes, the host enables data output mode to read the subfeature parameters.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

57

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Feature Operations

Figure 26: GET FEATURES (EEh) Operation
Cycle type Command Address

DOUT

DOUT

DOUT

DOUT

I/Ox

EEh

FA

P1

P2

P3

P4

tWB

tFEAT tRR

R/B#

Table 18: Feature Addresses 01h: Timing Mode

Subfeature Parameter P1 Timing mode
P2 P3 P4

Options
Mode 0 (default) Mode 1 Mode 2 Mode 3 Mode 4 Mode 5

I/O7 I/O6 I/O5 I/O4
Reserved (0)
Reserved (0) Reserved (0) Reserved (0) Reserved (0) Reserved (0)
Reserved (0)
Reserved (0)
Reserved (0)

I/O3

I/O2
0
0 0 0 1 1

I/O1
0
0 1 1 0 0

I/O0 Value Notes

0

00h

1

1

01h

0

02h

1

03h

0

04h

1

05h

00h

00h

00h

Note:

1. The timing mode feature address is used to change the default timing mode. The timing mode should be selected to indicate the maximum speed at which the device will receive commands, addresses, and data cycles. The five supported settings for the timing mode are shown. The default timing mode is mode 0. The device returns to mode 0 when the device is power cycled. Supported timing modes are reported in the parameter page.

Table 19: Feature Addresses 80h: Programmable I/O Drive Strength

Subfeature Parameter P1 I/O drive strength
P2

Options
Full (default) Three-quarters One-half One-quarter

I/O7

I/O6

I/O5 I/O4
Reserved (0) Reserved (0) Reserved (0) Reserved (0)

I/O3

I/O2

I/O1
0 0 1 1

I/O0 Value Notes

0

00h

1

1

01h

0

02h

1

03h

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

58

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Feature Operations

Table 19: Feature Addresses 80h: Programmable I/O Drive Strength (Continued)

Subfeature Parameter
P3
P4

Options

I/O7

I/O6 I/O5 I/O4 Reserved (0)

I/O3

I/O2

I/O1

I/O0 Value Notes 00h

Reserved (0)

00h

Reserved (0)

00h

Note:

1. The programmable drive strength feature address is used to change the default I/O drive strength. Drive strength should be selected based on expected loading of the memory bus. This table shows the four supported output drive strength settings. The default drive strength is full strength. The device returns to the default drive strength mode when the device is power cycled. AC timing parameters may need to be relaxed if I/O drive strength is not set to full.

Table 20: Feature Addresses 81h: Programmable R/B# Pull-Down Strength

Subfeature Parameter P1 R/B# pull-down strength
P2
P3
P4

Options

I/O7 I/O6 I/O5

Full (default) Three-quarters One-half One-quarter

I/O4 I/O3 I/O2
Reserved (0) Reserved (0) Reserved (0)

I/O1
0 0 1 1

I/O0 Value Notes

0

00h

1

1

01h

0

02h

1

03h

00h

00h

00h

Note: 1. This feature address is used to change the default R/B# pull-down strength. Its strength should be selected based on the expected loading of R/B#. Full strength is the default, power-on value.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

59

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Status Operations
Status Operations
Each die (LUN) provides its status independently of other die (LUNs) on the same target through its 8-bit status register.
When a READ STATUS (70h) or READ STATUS ENHANCED (78h) command is issued, status register output is enabled. Status register contents are returned on I/O[7:0] for each data output request.
When the asynchronous interface is active and status register output is enabled, changes in the status register are seen on I/O[7:0] when CE# and RE# are LOW; it is not necessary to toggle RE# to see the status register update.
While monitoring the status register for completion of a data transfer from the Flash array to the data register (tR), the host must issue the READ MODE (00h) command to disable the status register and enable data output (see Read Operations).
The READ STATUS (70h) command returns the status of the most recently selected die (LUN). To prevent data contention during or following an interleaved die (multi-LUN) operation, the host must enable only one die (LUN) for status output by using the READ STATUS ENHANCED (78h) command (see Interleaved Die (Multi-LUN) Operations).

Table 21: Status Register Definition

Program

Page

SR Program Cache

Bit

Page

Mode

Page Read

7

Write

Write

Write

protect protect protect

6

RDY

RDY

RDY

cache

5

ARDY

ARDY

ARDY

Page Read Cache Mode
Write protect
RDY cache
ARDY

4

0

3

0

0

ECC

ECC

0

status1

status

(N­1)1

2

­

­

­

­

1

FAILC

FAILC Reserved

­

(N­1)

(N­1)

Block Erase Write protect RDY
ARDY
0 0
­ ­

Description
0 = Protected 1 = Not protected
0 = Busy (PROGRAM operation in progress) 1 = Ready (Cache can accept data; R/B# follows)
0 = Busy (PROGRAM operation in progress) 1 = Ready (Internal operations completed, if cache mode is used)
00 = Normal or uncorrectable 01 = 4~6 10 = 1~3 11 = 7~8 (Rewrite recommended)
Don't Care
0 = Pass 1 = Fail

This bit is valid only when RDY (SR bit 6) is 1. This bit retains the status of the previous valid program operation when the most recent program operation is complete.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

60

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Status Operations

Table 21: Status Register Definition (Continued)

Program

Page

SR Program Cache

Bit

Page

Mode

0

FAIL

FAIL (N)

Page Read
FAIL2

Page Read Cache Mode
FAIL (N-1)

Block Erase
FAIL

Description
0 = Pass 1 = Fail
This bit is set if the most recent finished operation on the selected die (LUN) failed. This bit is valid only when ARDY (SR bit 5) is 1.

Notes:

1. Bit = 11 when a rewrite is recommended because the page includes READ errors per sector (512-Byte [main] + 16-Byte [spare] + 16-Byte [parity]). When ECC is enabled, up to 7~8-bit error is corrected automatically.
2. A status register bit defined as FAIL signifies that an uncorrectable READ error has occurred.

READ STATUS (70h)
The READ STATUS (70h) command returns the status of the last-selected die (LUN) on a target. This command is accepted by the last-selected die (LUN) even when it is busy (RDY = 0).
If there is only one die (LUN) per target, the READ STATUS (70h) command can be used to return status following any NAND command.
In devices that have more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be used to select the die (LUN) that should report status. In this situation, using the READ STATUS (70h) command will result in bus contention, as two or more die (LUNs) could respond until the next operation is issued. The READ STATUS (70h) command can be used following all single die (LUN) operations.

Figure 27: READ STATUS (70h) Operation

Cycle type I/O[7:0]

Command tWHR
70h

DOUT SR

READ STATUS ENHANCED (78h)
The READ STATUS ENHANCED (78h) command returns the status of the addressed die (LUN) on a target even when it is busy (RDY = 0). This command is accepted by all die (LUNs), even when they are BUSY (RDY = 0).
Writing 78h to the command register, followed by row address cycles containing the page, block, and LUN addresses, puts the selected die (LUN) into read status mode. The selected die (LUN) stays in this mode until another valid command is issued. Die (LUNs) that are not addressed are deselected to avoid bus contention.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

61

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Status Operations
The selected LUN's status is returned when the host requests data output. The RDY and ARDY bits of the status register are shared for all planes on the selected die (LUN). The FAILC and FAIL bits are specific to the plane specified in the row address.
The READ STATUS ENHANCED (78h) command also enables the selected die (LUN) for data output. To begin data output following a READ-series operation after the selected die (LUN) is ready (RDY = 1), issue the READ MODE (00h) command, then begin data output.
Use of the READ STATUS ENHANCED (78h) command is prohibited during the poweron RESET (FFh) command and when OTP mode is enabled. It is also prohibited following some of the other reset, identification, and configuration operations. See individual operations for specific details.
Figure 28: READ STATUS ENHANCED (78h) Operation

Cycle type I/Ox

Command Address

Address tWHR

78h

R1

R2

DOUT SR

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

62

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Column Address Operations
Column Address Operations
The column address operations affect how data is input to and output from the cache registers within the selected die (LUNs). These features provide host flexibility for managing data, especially when the host internal buffer is smaller than the number of data bytes or words in the cache register.
When the asynchronous interface is active, column address operations can address any byte in the selected cache register.
RANDOM DATA READ (05h-E0h)
The RANDOM DATA READ (05h-E0h) command changes the column address of the selected cache register and enables data output from the last selected die (LUN). This command is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It is also accepted by the selected die (LUN) during CACHE READ operations (RDY = 1; ARDY = 0).
Writing 05h to the command register, followed by two column address cycles containing the column address, followed by the E0h command, puts the selected die (LUN) into data output mode. After the E0h command cycle is issued, the host must wait at least tWHR before requesting data output. The selected die (LUN) stays in data output mode until another valid command is issued.
In devices with more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be issued prior to issuing the RANDOM DATA READ (05h-E0h). In this situation, using the RANDOM DATA READ (05h-E0h) command without the READ STATUS ENHANCED (78h) command will result in bus contention because two or more die (LUNs) could output data.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

63

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Column Address Operations

Figure 29: RANDOM DATA READ (05h-E0h) Operation
CLE

CE# WE#

tRHW

tCLR tWHR

ALE
tRC
RE#

tREA

I/Ox

DOUT
N - 1

DOUT
N

RDY

05h

Col add 1

Col add 2

E0h

Column address M

DOUT
M

DOUT
M + 1

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

64

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Column Address Operations
RANDOM DATA INPUT (85h)
The RANDOM DATA INPUT (85h) command changes the column address of the selected cache register and enables data input on the last-selected die (LUN). This command is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It is also accepted by the selected die (LUN) during cache program operations (RDY = 1; ARDY = 0).
Writing 85h to the command register, followed by two column address cycles containing the column address, puts the selected die (LUN) into data input mode. After the second address cycle is issued, the host must wait at least tADL before inputting data. The selected die (LUN) stays in data input mode until another valid command is issued. Though data input mode is enabled, data input from the host is optional. Data input begins at the column address specified.
The RANDOM DATA INPUT (85h) command is allowed after the required address cycles are specified, but prior to the final command cycle (10h, 11h, 15h) of the following commands while data input is permitted: PROGRAM PAGE (80h-10h), PROGRAM PAGE CACHE (80h-15h) and PROGRAM FOR INTERNAL DATA MOVE (85h-10h).
In devices that have more than one die (LUN) per target, the RANDOM DATA INPUT (85h) command can be used with other commands that support interleaved die (multiLUN) operations.

Figure 30: RANDOM DATA INPUT (85h) Operation
As defined for PAGE (CACHE) PROGRAM

Cycle type I/O[7:0]

DIN

DIN

Command Address Address

tADL

Dn Dn + 1

85h

C1

C2

As defined for PAGE (CACHE) PROGRAM

DIN

DIN

DIN

Dk Dk + 1 Dk + 2

RDY

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

65

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Column Address Operations
PROGRAM FOR INTERNAL DATA INPUT (85h)
The PROGRAM FOR INTERNAL DATA INPUT (85h) command changes the row address (block and page) where the cache register contents will be programmed in the NAND Flash array. It also changes the column address of the selected cache register and enables data input on the specified die (LUN). This command is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It is also accepted by the selected die (LUN) during cache programming operations (RDY = 1; ARDY = 0).
Write 85h to the command register. Then write two column address cycles and row address cycles. This updates the page and block destination of the selected device for the addressed LUN and puts the cache register into data input mode. After the fifth address cycle is issued the host must wait at least tADL before inputting data. The selected LUN stays in data input mode until another valid command is issued. Though data input mode is enabled, data input from the host is optional. Data input begins at the column address specified.
The PROGRAM FOR INTERNAL DATA INPUT (85h) command is allowed after the required address cycles are specified, but prior to the final command cycle (10h, 11h, 15h) of the following commands while data input is permitted: PROGRAM PAGE (80h-10h), PROGRAM PAGE CACHE (80h-15h) and PROGRAM FOR INTERNAL DATA MOVE (85h-10h). When used with these commands, the LUN address and plane select bits are required to be identical to the LUN address and plane select bits originally specified.
The PROGRAM FOR INTERNAL DATA INPUT (85h) command enables the host to modify the original page and block address for the data in the cache register to a new page and block address.
In devices that have more than one die (LUN) per target, the PROGRAM FOR INTERNAL DATA INPUT (85h) command can be used with other commands that support interleaved die (multi-LUN) operations.
The PROGRAM FOR INTERNAL DATA INPUT (85h) command can be used with the RANDOM DATA READ (05h-E0h) commands to read and modify cache register contents in small sections prior to programming cache register contents to the NAND Flash array. This capability can reduce the amount of buffer memory used in the host controller.
The RANDOM DATA INPUT (85h) command can be used during the PROGRAM FOR INTERNAL DATA MOVE command sequence to modify one or more bytes of the original data. First, data is copied into the cache register using the 00h-35h command sequence, then the RANDOM DATA INPUT (85h) command is written along with the address of the data to be modified next. New data is input on the external data pins. This copies the new data into the cache register.

Figure 31: PROGRAM FOR INTERNAL DATA INPUT (85h) Operation

Cycle type I/O[7:0]

DIN

DIN

Command Address Address Address Address Command

t ADL

Dn Dn + 1

85h

C1

C2

R1

R2

10h

DIN

DIN

DIN

Dk Dk + 1 Dk + 2

RDY

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

66

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Read Operations
Read Operations
The READ PAGE (00h-30h) command, when issued by itself, reads one page from the NAND Flash array to its cache register and enables data output for that cache register.
During data output the following commands can be used to read and modify the data in the cache registers: RANDOM DATA READ (05h-E0h) and RANDOM DATA INPUT (85h).
Read Cache Operations
To increase data throughput, the READ PAGE CACHE series (31h, 00h-31h) commands can be used to output data from the cache register while concurrently copying a page from the NAND Flash array to the data register.
To begin a read page cache sequence, begin by reading a page from the NAND Flash array to its corresponding cache register using the READ PAGE (00h-30h) command. R/B# goes LOW during tR and the selected die (LUN) is busy (RDY = 0, ARDY = 0). After tR (R/B# is HIGH and RDY = 1, ARDY = 1), issue either of these commands:
· READ PAGE CACHE SEQUENTIAL (31h) ­ copies the next sequential page from the NAND Flash array to the data register
· READ PAGE CACHE RANDOM (00h-31h) ­ copies the page specified in this command from the NAND Flash array to its corresponding data register
After the READ PAGE CACHE series (31h, 00h-31h) command has been issued, R/B# goes LOW on the target, and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while the next page begins copying data from the array to the data register. After tRCBSY, R/B# goes HIGH and the die's (LUN's) status register bits indicate the device is busy with a cache operation (RDY = 1, ARDY = 0). The cache register becomes available and the page requested in the READ PAGE CACHE operation is transferred to the data register. At this point, data can be output from the cache register, beginning at column address 0. The RANDOM DATA READ (05h-E0h) command can be used to change the column address of the data output by the die (LUN).
After outputting the desired number of bytes from the cache register, either an additional READ PAGE CACHE series (31h, 00h-31h) operation can be started or the READ PAGE CACHE LAST (3Fh) command can be issued.
If the READ PAGE CACHE LAST (3Fh) command is issued, R/B# goes LOW on the target, and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while the data register is copied into the cache register. After tRCBSY, R/B# goes HIGH and RDY = 1 and ARDY = 1, indicating that the cache register is available and that the die (LUN) is ready. Data can then be output from the cache register, beginning at column address 0. The RANDOM DATA READ (05h-E0h) command can be used to change the column address of the data being output.
For READ PAGE CACHE series (31h, 00h-31h, 3Fh), during the die (LUN) busy time, tRCBSY, when RDY = 0 and ARDY = 0, the only valid commands are status operations (70h, 78h) and RESET (FFh). When RDY = 1 and ARDY = 0, the only valid commands during READ PAGE CACHE series (31h, 00h-31h) operations are status operations (70h, 78h), READ MODE (00h), READ PAGE CACHE series (31h, 00h-31h), RANDOM DATA READ (05h-E0h), and RESET (FFh).

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

67

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Read Operations
READ MODE (00h)
The READ MODE (00h) command disables status output and enables data output for the last-selected die (LUN) and cache register after a READ operation (00h-30h, 00h-3Ah, 00h-35h) has been monitored with a status operation (70h, 78h). This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN) during READ PAGE CACHE (31h, 00h-31h) operations (RDY = 1 and ARDY = 0).
In devices that have more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be used to select only one die (LUN) prior to issuing the READ MODE (00h) command. This prevents bus contention.
READ PAGE (00h-30h)
The READ PAGE (00h­30h) command copies a page from the NAND Flash array to its respective cache register and enables data output. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1).
To read a page from the NAND Flash array, write the 00h command to the command register, then write n address cycles to the address registers, and conclude with the 30h command. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for tR as data is transferred.
To determine the progress of the data transfer, the host can monitor the target's R/B# signal or, alternatively, the status operations (70h, 78h) can be used. If the status operations are used to monitor the LUN's status, when the die (LUN) is ready (RDY = 1, ARDY = 1), the host disables status output and enables data output by issuing the READ MODE (00h) command. When the host requests data output, output begins at the column address specified.
During data output the RANDOM DATA READ (05h-E0h) command can be issued.
When internal ECC is enabled, the READ STATUS (70h) command is required after the completion of the data transfer (tR_ECC) to determine whether an uncorrectable read error occured. (tR_ECC is the data transferred with internal ECC enabled.)
In devices that have more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations the READ STATUS ENHANCED (78h) command must be used to select only one die (LUN) prior to the issue of the READ MODE (00h) command. This prevents bus contention.

Figure 32: READ PAGE (00h-30h) Operation
Cycle type Command Address Address Address Address Address Command

DOUT DOUT DOUT

I/O[7:0]

00h

C1

C2

R1

R2

R3

30h

Dn Dn+1 Dn+2

tWB

tR tRR

RDY

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

68

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Read Operations

Figure 33: READ PAGE (00h-30h) Operation with Internal ECC Enabled

RDY

tR_ECC

I/O[7:0] 00h Address Address Address Address Address 30h

70h Status 00h

DOUT (serial access)

SR bit 0 = 0 READ successful SR bit 1 = 0 READ error

READ PAGE CACHE SEQUENTIAL (31h)
The READ PAGE CACHE SEQUENTIAL (31h) command reads the next sequential page within a block into the data register while the previous page is output from the cache register. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN) during READ PAGE CACHE (31h, 00h-31h) operations (RDY = 1 and ARDY = 0).
To issue this command, write 31h to the command register. After this command is issued, R/B# goes LOW and the die (LUN) is busy (RDY = 0, ARDY = 0) for tRCBSY. After tRCBSY, R/B# goes HIGH and the die (LUN) is busy with a cache operation (RDY = 1, ARDY = 0), indicating that the cache register is available and that the specified page is copying from the NAND Flash array to the data register. At this point, data can be output from the cache register beginning at column address 0. The RANDOM DATA READ (05h-E0h) command can be used to change the column address of the data being output from the cache register.
The READ PAGE CACHE SEQUENTIAL (31h) command can be used to cross block boundaries. If the READ PAGE CACHE SEQUENTIAL (31h) command is issued after the last page of a block is read into the data register, the next page read will be the next logical block in which the 31h command was issued. Do not issue the READ PAGE CACHE SEQUENTIAL (31h) to cross die (LUN) boundaries. Instead, issue the READ PAGE CACHE LAST (3Fh) command.

Figure 34: READ PAGE CACHE SEQUENTIAL (31h) Operation

Cycle type Command Address x5 Command

Command

DOUT

DOUT

DOUT Command

DOUT

I/O[7:0] RDY

00h Page Address M 30h

31h

D0

tWB tR RR

tWB tRCBSY tRR

...

Dn

Page M

31h

D0

tWB tRCBSY tRR

Page M+1

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

69

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Read Operations
READ PAGE CACHE RANDOM (00h-31h)
The READ PAGE CACHE RANDOM (00h-31h) command reads the specified block and page into the data register while the previous page is output from the cache register. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN) during READ PAGE CACHE (31h, 00h-31h) operations (RDY = 1 and ARDY = 0).
To issue this command, write 00h to the command register, then write n address cycles to the address register, and conclude by writing 31h to the command register. The column address in the address specified is ignored. The die (LUN) address must match the same die (LUN) address as the previous READ PAGE (00h-30h) command or, if applicable, the previous READ PAGE CACHE RANDOM (00h-31h) command.
After this command is issued, R/B# goes LOW and the die (LUN) is busy (RDY = 0, ARDY = 0) for tRCBSY. After tRCBSY, R/B# goes HIGH and the die (LUN) is busy with a cache operation (RDY = 1, ARDY = 0), indicating that the cache register is available and that the specified page is copying from the NAND Flash array to the data register. At this point, data can be output from the cache register beginning at column address 0. The RANDOM DATA READ (05h-E0h) command can be used to change the column address of the data being output from the cache register.
In devices that have more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations the READ STATUS ENHANCED (78h) command followed by the READ MODE (00h) command must be used to select only one die (LUN) and prevent bus contention.

Figure 35: READ PAGE CACHE RANDOM (00h-31h) Operation

Cycle type Command Address x5 Command

Command Address x5 Command

DOUT

DOUT

DOUT

Command

I/O[7:0] RDY

00h Page Address M 30h

00h

Page Address N 31h

D0

tWB tR RR

tWB tRCBSY tRR

Cycle type

DOUT

Command Address x5 Command

DOUT

...

Dn

00h

Page M 1

I/O[7:0] RDY

Dn

00h

1

Page Address P 31h

D0

tWB tRCBSY tRR

Page N

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

70

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Read Operations
READ PAGE CACHE LAST (3Fh)
The READ PAGE CACHE LAST (3Fh) command ends the read page cache sequence and copies a page from the data register to the cache register. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN) during READ PAGE CACHE (31h, 00h-31h) operations (RDY = 1 and ARDY = 0).
To issue the READ PAGE CACHE LAST (3Fh) command, write 3Fh to the command register. After this command is issued, R/B# goes LOW and the die (LUN) is busy (RDY = 0, ARDY = 0) for tRCBSY. After tRCBSY, R/B# goes HIGH and the die (LUN) is ready (RDY = 1, ARDY = 1). At this point, data can be output from the cache register, beginning at column address 0. The RANDOM DATA READ (05h-E0h) command can be used to change the column address of the data being output from the cache register.
In devices that have more than one LUN per target, during and following interleaved die (multi-LUN) operations the READ STATUS ENHANCED (78h) command followed by the READ MODE (00h) command must be used to select only one die (LUN) and prevent bus contention.

Figure 36: READ PAGE CACHE LAST (3Fh) Operation

As defined for READ PAGE CACHE (SEQUENTIAL OR RANDOM)

Cycle type Command

DOUT

DOUT

DOUT

Command

DOUT

DOUT

DOUT

I/O[7:0]

31h

D0

...

Dn

tWB

tRCBSY tRR

RDY

Page Address N

3Fh

D0

...

Dn

tWB

tRCBSY tRR

Page N

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

71

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Program Operations
Program Operations
Program operations are used to move data from the cache or data registers to the NAND array. During a program operation the contents of the cache and/or data registers are modified by the internal control logic.
Within a block, pages must be programmed sequentially from the least significant page address to the most significant page address (0, 1, 2, ....., 63). During a program operation, the contents of the cache and/or data registers are modified by the internal control logic.
Program Operations
The PROGRAM PAGE (80h-10h) command programs one page from the cache register to the NAND Flash array. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host should check the FAIL bit to verify that the operation has completed successfully.
Program Cache Operations
The PROGRAM PAGE CACHE (80h-15h) command can be used to improve program operation system performance. When this command is issued, the die (LUN) goes busy (RDY = 0, ARDY = 0) while the cache register contents are copied to the data register, and the die (LUN) is busy with a PROGRAM CACHE operation (RDY = 1, ARDY = 0. While the contents of the data register are moved to the NAND Flash array, the cache register is available for an additional PROGRAM PAGE CACHE (80h-15h) or PROGRAM PAGE (80h-10h) command.
For PROGRAM PAGE CACHE series (80h-15h) operations, during the die (LUN) busy times, tCBSY and tLPROG, when RDY = 0 and ARDY = 0, the only valid commands are status operations (70h, 78h) and reset (FFh). When RDY = 1 and ARDY = 0, the only valid commands during PROGRAM PAGE CACHE series (80h-15h) operations are status operations (70h, 78h), PROGRAM PAGE CACHE (80h-15h), PROGRAM PAGE (80h-10h), RANDOM DATA INPUT (85h), PROGRAM FOR INTERNAL DATA INPUT (85h), and RESET (FFh).
PROGRAM PAGE (80h-10h)
The PROGRAM PAGE (80h-10h) command enables the host to input data to a cache register, and moves the data from the cache register to the specified block and page address in the array of the selected die (LUN). This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN) when it is busy with a PROGRAM PAGE CACHE (80h-15h) operation (RDY = 1, ARDY = 0).
To input a page to the cache register and move it to the NAND array at the block and page address specified, write 80h to the command register. Issuing the 80h to the command register clears all of the cache registers' contents on the selected target. Then write n address cycles containing the column address and row address. Data input cycles follow. Serial data is input beginning at the column address specified. At any time during the data input cycle the RANDOM DATA INPUT (85h) and PROGRAM FOR INTERNAL DATA INPUT (85h) commands may be issued. When data input is complete, write 10h to the command register. The selected LUN will go busy (RDY = 0, ARDY = 0) for tPROG as data is transferred.
To determine the progress of the data transfer, the host can monitor the target's R/B# signal or, alternatively, the status operations (70h, 78h) may be used. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host should check the status of the FAIL bit.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

72

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Program Operations
In devices that have more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be used to select only one die (LUN) for status output. Use of the READ STATUS (70h) command could cause more than one die (LUN) to respond, resulting in bus contention. When internal ECC is enabled, the duration of array programming time is tPROG_ECC. During tPROG_ECC, the internal ECC generates parity bits when error detection is complete.

Figure 37: PROGRAM PAGE (80h-10h) Operation

Cycle type Command Address Address Address Address Address

DIN

tADL

I/O[7:0]

80h

C1

C2

R1

R2

R3

D0

RDY

DIN

DIN

DIN

Command

Command

DOUT

D1

...

Dn

10h

tPROG or

70h

tWB tPROG_ECC

Status

PROGRAM PAGE CACHE (80h-15h)
The PROGRAM PAGE CACHE (80h-15h) command enables the host to input data to a cache register; copies the data from the cache register to the data register; then moves the data register contents to the specified block and page address in the array of the selected die (LUN). After the data is copied to the data register, the cache register is available for additional PROGRAM PAGE CACHE (80h-15h) or PROGRAM PAGE (80h-10h) commands. The PROGRAM PAGE CACHE (80h-15h) command is accepted by the die (LUN) when it is ready (RDY =1, ARDY = 1). It is also accepted by the die (LUN) when busy with a PROGRAM PAGE CACHE (80h-15h) operation (RDY = 1, ARDY = 0).
To input a page to the cache register to move it to the NAND array at the block and page address specified, write 80h to the command register. Issuing the 80h to the command register clears all of the cache registers' contents on the selected target. Then write n address cycles containing the column address and row address. Data input cycles follow. Serial data is input beginning at the column address specified. At any time during the data input cycle the RANDOM DATA INPUT (85h) and PROGRAM FOR INTERNAL DATA INPUT (85h) commands may be issued. When data input is complete, write 15h to the command register. The selected LUN will go busy (RDY = 0, ARDY = 0) for tCBSY to allow the data register to become available from a previous program cache operation, to copy data from the cache register to the data register, and then to begin moving the data register contents to the specified page and block address.
To determine the progress of tCBSY, the host can monitor the target's R/B# signal or, alternatively, the status operations (70h, 78h) can be used. When the LUN's status shows that it is busy with a PROGRAM CACHE operation (RDY = 1, ARDY = 0), the host should check the status of the FAILC bit to see if a previous cache operation was successful.
If, after tCBSY, the host wants to wait for the PROGRAM CACHE operation to complete, without issuing the PROGRAM PAGE (80h-10h) command, the host should monitor ARDY until it is 1. The host should then check the status of the FAIL and FAILC bits.
In devices with more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

73

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Program Operations
used to select only one die (LUN) for status output. Use of the READ STATUS (70h) command could cause more than one die (LUN) to respond, resulting in bus contention.

Figure 38: PROGRAM PAGE CACHE (80h­15h) Operation (Start)

Cycle type Command Address Address Address Address Address

DIN

tADL

I/O[7:0]

80h

C1

C2

R1

R2

R3

D0

RDY

DIN

DIN

DIN

Command

D1

...

Dn

15h

tWB

tCBSY

1

Cycle type Command Address Address Address Address Address

DIN

tADL

I/O[7:0]

80h

C1

C2

R1

R2

R3

D0

RDY

DIN

DIN

DIN

Command

D1

...

Dn

15h

tWB

tCBSY

1

Figure 39: PROGRAM PAGE CACHE (80h­15h) Operation (End)
As defined for PAGE CACHE PROGRAM

Cycle type Command Address Address Address Address Address

DIN

tADL

I/O[7:0]

80h

C1

C2

R1

R2

R3

D0

RDY

DIN

DIN

DIN

Command

D1

...

Dn

15h

tWB

tCBSY

Cycle type Command Address Address Address Address Address

DIN

tADL

I/O[7:0]

80h

C1

C2

R1

R2

R3

D0

RDY

1

DIN

DIN

DIN

Command

D1

...

Dn

10h

tWB

tLPROG

1

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

74

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Erase Operations
Erase Operations
Erase operations are used to clear the contents of a block in the NAND Flash array to prepare its pages for program operations.
Erase Operations
The ERASE BLOCK (60h-D0h) command, erases one block in the NAND Flash array. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host should check the FAIL bit to verify that this operation completed successfully.
ERASE BLOCK (60h-D0h)
The ERASE BLOCK (60h-D0h) command erases the specified block in the NAND Flash array. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1).
To erase a block, write 60h to the command register. Then write three address cycles containing the row address; the page address is ignored. Conclude by writing D0h to the command register. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for tBERS while the block is erased.
To determine the progress of an ERASE operation, the host can monitor the target's R/B# signal, or alternatively, the status operations (70h, 78h) can be used. When the die (LUN) is ready (RDY = 1, ARDY = 1) the host should check the status of the FAIL bit.
In devices that have more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be used to select only one die (LUN) for status output. Use of the READ STATUS (70h) command could cause more than one die (LUN) to respond, resulting in bus contention.
Figure 40: ERASE BLOCK (60h-D0h) Operation
Cycle type Command Address Address Address Command

I/O[7:0]

60h

R1

R2

R3

D0h

RDY

tWB

tBERS

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

75

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Internal Data Move Operations
Internal Data Move Operations
Internal data move operations make it possible to transfer data within a device from one page to another, on the same plane, using the cache register. This is particularly useful for block management and wear leveling.
It is not possible to use the READ FOR INTERNAL DATA MOVE operation to move data from one die (LUN) to another. Instead, use a READ PAGE (00h-30h) or READ FOR INTERNAL DATA MOVE (00h-35h) command to read the data out of the NAND, and then use a PROGRAM PAGE (80h-10h) command with data input to program the data to a new die (LUN).
Between the READ FOR INTERNAL DATA MOVE (00h-35h) and PROGRAM FOR INTERNAL DATA MOVE (85h-10h) commands, the following commands are supported: status operations (70h, 78h) and column address operations (05h-E0h, 06h-E0h, 85h). The RESET operation (FFh) can be issued after READ FOR INTERNAL DATA MOVE (00h-35h), but the contents of the cache registers on the target are not valid.
In devices that have more than one die (LUN) per target, once the READ FOR INTERNAL DATA MOVE (00h-35h) is issued, interleaved die (multi-LUN) operations are prohibited until after the PROGRAM FOR INTERNAL DATA MOVE (85h-10h) command is issued.
READ FOR INTERNAL DATA MOVE (00h-35h)
The READ FOR INTERNAL DATA MOVE (00h-35h) command is functionally identical to the READ PAGE (00h-30h) command, except that 35h is written to the command register instead of 30h.
Though it is not required, it is recommended that the host read the data out of the device to verify the data prior to issuing the PROGRAM FOR INTERNAL DATA MOVE (85h-10h) command to prevent the propagation of data errors.
If internal ECC is enabled, the data does not need to be toggled out by the host to be corrected and moving data can then be written to a new page without data reloading, which improves system performance.

Figure 41: READ FOR INTERNAL DATA MOVE (00h-35h) Operation
Cycle type Command Address Address Address Address Address Command

DOUT DOUT DOUT

I/O[7:0]

00h

C1

C2

R1

R2

R3

35h

Dn Dn+1 Dn+2

RDY

tWB

tR tRR

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

76

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Internal Data Move Operations

Figure 42: READ FOR INTERNAL DATA MOVE (00h­35h) with RANDOM DATA READ (05h­E0h)

Cycle type Command Address Address Address Address Address Command

DOUT DOUT DOUT

I/O[7:0]

00h

C1

C2

R1

R2

R3

35h

D0

... Dj + n

RDY

tWB

tR tRR

1

Cycle type I/O[7:0]

Command Address

Address

Command tWHR

05h

C1

C2

E0h

RDY

DOUT

DOUT

DOUT

Dk Dk + 1 Dk + 2

1

Figure 43: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled

R/B#

tR_ECC

tPROG_ECC

I/O[7:0]

00h

Address (5 cycles)

35h

Source address

70h Status 00h
SR bit 0 = 0 READ successful SR bit 1 = 0 READ error

DOUT

85h

Address (5 cycles)

10h

DOUT is optional Destination address

70h Status 00h
SR bit 0 = 0 READ successful SR bit 1 = 0 READ error

Figure 44: INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT with Internal ECC Enabled

R/B#

tR_ECC

tPROG_ECC

I/O[7:0] 00h (A5dcdycrelesss) 35h

70h Status 00h

DOUT

85h (A5dcdycrelesss) Data 85h (A2dcdycrelesss) Data 10h

70h

Source address

SR bit 0 = 0 READ successful SR bit 1 = 0 READ error

DOUT is optional

Destination address
Column address 1, 2 (Unlimitted repetitions are possible)

PROGRAM FOR INTERNAL DATA MOVE (85h­10h)
The PROGRAM FOR INTERNAL DATA MOVE (85h-10h) command is functionally identical to the PROGRAM PAGE (80h-10h) command, except that when 85h is written to the command register, cache register contents are not cleared.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

77

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Internal Data Move Operations

Figure 45: PROGRAM FOR INTERNAL DATA MOVE (85h­10h) Operation
Cycle type Command Address Address Address Address Address Command

I/O[7:0]

85h

C1

C2

R1

R2

R3

10h

RDY

tWB

tPROG

Figure 46: PROGRAM FOR INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT (85h)

Cycle type I/O[7:0]

Command Address

85h

C1

Address C2

Address R1

Address R2

Address tWHR
R3

RDY

DIN

DIN

Di

Di + 1

Cycle type I/O[7:0]

Command Address

Address tWHR

85h

C1

C2

RDY

1

DIN

DIN

DIN Command

Dj

Dj + 1 Dj + 2

10h tWB

tPROG

1

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

78

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Block Lock Feature
Block Lock Feature
The block lock feature protects either the entire device or ranges of blocks from being programmed and erased. Using the block lock feature is preferable to using WP# to prevent PROGRAM and ERASE operations.
Block lock is enabled and disabled at power-on through the LOCK pin. At power-on, if LOCK is LOW, all BLOCK LOCK commands are disabled. However if LOCK is HIGH at power-on, the BLOCK LOCK commands are enabled and, by default, all the blocks on the device are protected, or locked, from PROGRAM and ERASE operations, even if WP# is HIGH.
Before the contents of the device can be modified, the device must first be unlocked. Either a range of blocks or the entire device may be unlocked. PROGRAM and ERASE operations complete successfully only in the block ranges that have been unlocked. Blocks, once unlocked, can be locked again to protect them from further PROGRAM and ERASE operations.
Blocks that are locked can be protected further, or locked tight. When locked tight, the device's blocks can no longer be locked or unlocked.
WP# and Block Lock
The following is true when the block lock feature is enabled:
· Holding WP# LOW locks all blocks, provided the blocks are not locked tight. · If WP# is held LOW to lock blocks, then returned to HIGH, a new UNLOCK command
must be issued to unlock blocks.
UNLOCK (23h-24h)
By default at power-on, if LOCK is HIGH, all the blocks are locked and protected from PROGRAM and ERASE operations. The UNLOCK (23h) command is used to unlock a range of blocks. Unlocked blocks have no protection and can be programmed or erased.
The UNLOCK command uses two registers, a lower boundary block address register and an upper boundary block address register, and the invert area bit to determine what range of blocks are unlocked. When the invert area bit = 0, the range of blocks within the lower and upper boundary address registers are unlocked. When the invert area bit = 1, the range of blocks outside the boundaries of the lower and upper boundary address registers are unlocked. The lower boundary block address must be less than the upper boundary block address. The figures below show examples of how the lower and upper boundary address registers work with the invert area bit.
To unlock a range of blocks, issue the UNLOCK (23h) command followed by the appropriate address cycles that indicate the lower boundary block address. Then issue the 24h command followed by the appropriate address cycles that indicate the upper boundary block address. The least significant page address bit, PA0, should be set to 1 if setting the invert area bit; otherwise, it should be 0. The other page address bits should be 0.
Only one range of blocks can be specified in the lower and upper boundary block address registers. If after unlocking a range of blocks the UNLOCK command is again issued, the new block address range determines which blocks are unlocked. The previous unlocked block address range is not retained.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

79

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Block Lock Feature

Figure 47: Flash Array Protected: Invert Area Bit = 0

Block 2047 Block 2046 Block 2045 Block 2044 Block 2043 Block 2042 Block 2041 Block 2040 Block.............. 2039 Block 0002 Block 0001 Block 0000

7FCh Upper block boundary 7F8h Lower block boundary

Figure 48: Flash Array Protected: Invert Area Bit = 1

Protected area
Unprotected area
Protected area

Block 2047 Block 2046 Block 2045 Block 2044 Block 2043 Block 2042 Block 2041 Block 2040 Block.............. 2039 Block 0002 Block 0001 Block 0000

7FCh Upper block boundary 7F8h Lower block boundary

Unprotected Area
Protected area
Unprotected area

Table 22: Block Lock Address Cycle Assignments

ALE Cycle First Second Third

I/O[15:8]1 LOW LOW LOW

I/O7 BA7 BA15 LOW

I/O6 BA6 BA14 LOW

I/O5 LOW BA13 LOW

I/O4 LOW BA12 LOW

I/O3 LOW BA11 LOW

I/O2 LOW BA10 LOW

I/O1 LOW BA9 BA17

I/O0 Invert area bit2
BA8 BA16

Notes: 1. I/O[15:8] is applicable only for x16 devices.
2. Invert area bit is applicable for 24h command; it may be LOW or HIGH for 23h command.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

80

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Block Lock Feature

Figure 49: UNLOCK Operation
WP# CLE

CE#

WE#

ALE

RE# I/Ox
R/B#
LOCK (2Ah)

23h

Block Block Block add 1 add 2 add 3

24h

Block Block Block add 1 add 2 add 3

Unlock

Lower boundary

Upper boundary

By default at power-on, if LOCK is HIGH, all the blocks are locked and protected from PROGRAM and ERASE operations. If portions of the device are unlocked using the UNLOCK (23h) command, they can be locked again using the LOCK (2Ah) command. The LOCK command locks all of the blocks in the device. Locked blocks are write-protected from PROGRAM and ERASE operations.
To lock all of the blocks in the device, issue the LOCK (2Ah) command.
When a PROGRAM or ERASE operation is issued to a locked block, R/B# goes LOW for tLBSY. The PROGRAM or ERASE operation does not complete. Any READ STATUS command reports bit 7 as 0, indicating that the block is protected.
The LOCK (2Ah) command is disabled if LOCK is LOW at power-on or if the device is locked tight.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

81

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Block Lock Feature

Figure 50: LOCK Operation
CLE

CE#

WE#

I/Ox

2Ah

LOCK command

LOCK TIGHT (2Ch)
The LOCK TIGHT (2Ch) command prevents locked blocks from being unlocked and also prevents unlocked blocks from being locked. When this command is issued, the UNLOCK (23h) and LOCK (2Ah) commands are disabled. This provides an additional level of protection against inadvertent PROGRAM and ERASE operations to locked blocks.
To implement LOCK TIGHT in all of the locked blocks in the device, verify that WP# is HIGH and then issue the LOCK TIGHT (2Ch) command.
When a PROGRAM or ERASE operation is issued to a locked block that has also been locked tight, R/B# goes LOW for tLBSY. The PROGRAM or ERASE operation does not complete. The READ STATUS (70h) command reports bit 7 as 0, indicating that the block is protected. PROGRAM and ERASE operations complete successfully to blocks that were not locked at the time the LOCK TIGHT command was issued.
After the LOCK TIGHT command is issued, the command cannot be disabled via a software command. Lock tight status can be disabled only by power cycling the device or toggling WP#. When the lock tight status is disabled, all of the blocks become locked, the same as if the LOCK (2Ah) command had been issued.
The LOCK TIGHT (2Ch) command is disabled if LOCK is LOW at power-on.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

82

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Block Lock Feature
Figure 51: LOCK TIGHT Operation
LOCK

WP#

CLE

CE#

WE#

I/Ox R/B#

2Ch LOCK TIGHT
command

Figure 52: PROGRAM/ERASE Issued to Locked Block

R/B#

tLBSY

I/Ox

PROGRAM or ERASE

Add ress/data input Locked block

CONFIRM

70h

60h

READ STATUS

BLOCK LOCK READ STATUS (7Ah)
The BLOCK LOCK READ STATUS (7Ah) command is used to determine the protection status of individual blocks. The address cycles have the same format, as shown below, and the invert area bit should be set LOW. On the falling edge of RE# the I/O pins output the block lock status register, which contains the information on the protection status of the block.

Table 23: Block Lock Status Register Bit Definitions

Block Lock Status Register Definitions Block is locked tight Block is locked Block is unlocked, and device is locked tight Block is unlocked, and device is not locked tight Block is permanently protected

I/O[7:4] X X X X X

I/O3 (Protect#)
1 1 1 1 0

I/O2 (Lock#)
0 0 1 1 x

I/O1 (LT#)
0 1 0 1 x

I/O0 (LT)
1 0 1 0 x

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

83

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Block Lock Feature
Figure 53: BLOCK LOCK READ STATUS
CLE

CE#

WE# ALE

tWHR

RE#

I/Ox

7Ah

Add 1 Add 2 Add 3

BLOCK LOCK READ STATUS

Block address

Status

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

84

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Block Lock Feature

Figure 54: BLOCK LOCK Flowchart
Power-up with LOCK HIGH
Entire NAND Flash array locked
LOCK TIGHT Cmd with WP# and LOCK HIGH Entire NAND Flash array locked tight

Power-up

Power-up with LOCK LOW (default)
BLOCK LOCK function disabled

UNLOCK Cmd with invert area bit = 1

UNLOCK Cmd with invert area bit = 0

WP# LOW >100ns or LOCK Cmd

Unlocked range Locked range

Unlocked range

WP# LOW >100ns or LOCK Cmd
UNLOCK Cmd with invert area bit = 1
UNLOCK Cmd with invert area bit = 0

UNLOCK Cmd with invert area
bit = 1

LOCK TIGHT Cmd with WP# and LOCK HIGH

Locked range Unlocked range

UNLOCK Cmd with invert area bit = 0

Locked range

LOCK TIGHT Cmd with WP# and LOCK HIGH

Unlocked range

Locked tight range

Locked tight range

Unlocked range

Unlocked range

Locked-tight range

PROTECT Command
Blocks 00h­07h are guaranteed valid with ECC when shipped from the factory. The PROTECT command provides nonvolatile, irreversible protection of up to twelve groups (48 blocks total). Implementation of the protection is group-based, which means that a minimum of one group (4 blocks) is protected when the PROTECT command is issued.
Because block protection is nonvolatile, a power-on or power-off sequence does not affect the block status after the PROTECT command is issued. The device ships from the factory with no blocks protected so that users can program or erase the blocks before issuing the PROTECT command. Block protection is also irreversible in that when pro-

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

85

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Block Lock Feature
tection is enabled by the issuing PROTECT command, the protected blocks can no longer be programmed or erased. The PROTECT command includes the steps detailed below.

Figure 55: Address and Command Cycles

Cycle type
I/O[7:0]
Cycle type
I/O[7:0]

Command 4Ch
Address 00h

Command 03h
Address 0Yh

Command 1Dh
Address 00h

Command 41h
Command 10h

Command 80h
tPROG

Address 00h
Command FFh

Address 00h

Note:

1. In the 4th address cycle, 0YH is the last 4 bits and represents the group of blocks to be protected. There are always 12 Groups, so Y = 0000b-1011b: Y = 0000 protects Group0 = blks 0, 1, 2, 3; Y = 0001 protects Group1 = blks 4, 5, 6, 7; Y = 1011 protects Group11 = blks 44, 45, 46, 47.

Protection Command Details
To enable protection, four bus WRITE cycles set up the 4Ch, 03h, 1Dh, and 41h commands. Next, one bus WRITE cycle sets up the PAGE PROGRAM command (80h).
Then, five bus WRITE cycles are required to input the targeted block group information: 00h, 00h, 00h, 0Yh, 00h. In this 4th address cycle, 0YH is the last 4 bits and represents the group of blocks to be protected. There are always 12 Groups, so Y = 0000b-1011b:
· Y = 0000 protects Group0 = blks 0, 1, 2, 3. · Y = 0001 protects Group1 = blks 4, 5, 6, 7. · Y = 1011 protects Group11 = blks 44, 45, 46, 47.
One bus cycle is required to issue the PAGE PROGRAM CONFIRM command. After tPROG, the targeted block groups are protected. The EXIT protection command (FFh) is issued to ensure the device exits protection mode.
(4Ch-03h-1Dh-41h)-80h-addr(00h-00h-00h-0Yh-00h)-10h-tPROG-FFh
The enable protection step is four bytes wide to prevent implementing involuntary protection. In addition, any spurious command/address/data cycles between each byte invalidates the entire process and the next PROGRAM command does not affect the block protection status. Likewise, any spurious command/address/data cycle between enable protection and setting up the PAGE PROGRAM command invalidates the entire protection command process.
If enable protection is followed by an operation other than the PROGRAM operation, such as a PAGE READ or BLOCK ERASE operation, this other operation is executed without affecting block protection status. Therefore, the PROTECT operation must still be executed to protect the block. The PROTECT operation is inhibited if WP# is LOW. Upon PROTECT operation failure, the status register reports a value of E1h. Upon PROTECT operation success, the status register reports value of E0h.
The following is an example of boot block protection:
Protect group 5 (blks20-23): (4Ch-03h-1Dh-41h)-80h-addr(00h-00h-00h-05h-00h)-10htPROG-FFh

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

86

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Block Lock Feature
Permanent Block Lock Disable Mode
The PROTECT command provides nonvolatile, irreversible protection of up to twelve groups (48 blocks total), these blocks are permanent locked once the PROTECT command is issued to them. The permanent block lock disable mode provides the command sequence to freeze the block lock status, it is highly recommended for customers to follow this operation to prevent unintentional or malicious changes but not limited to these scenarios:
· Only certain number of groups of blocks need to be permanently locked, the rest of the block groups do not need to be permanently locked
· Customer do not need permanent block lock feature, and all 48 blocks are normal blocks
In permanent block lock disable mode, the following program sequence is used to disable protection command to add more permanent locked block groups:
· SET FEATURE command (EFh) with feature address 90h and data value 10h-00h-00h-00h to enter permanent block lock disable mode
· PROGRAM command (80h-10h) with block/page address all "0", and data input 0x00 · READ STATUS command 70h to check the operation status and success
READ command also could be used in permanent block lock disable mode to check whether PROTECT command is disabled by reading out all "0"; all "1" indicates Protection command is not disabled.
If permanent block lock disable sequence is issued again to the part that has already been disabled, the part will be busy for tOBSY and exit with SR = 60h. The part will be busy for tOBSY_ECC when ECC is enabled.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

87

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP One-Time Programmable (OTP) Operations
One-Time Programmable (OTP) Operations
This Micron NAND Flash device offers a protected, one-time programmable NAND Flash memory area. 48 full pages of OTP data are available on the device, and the entire range is guaranteed to be good. The OTP area is accessible only through the OTP commands. Customers can use the OTP area any way they choose; typical uses include programming serial numbers or other data for permanent storage.
The OTP area leaves the factory in an unwritten state (all bits are 1s). Programming or partial-page programming enables the user to program only 0 bits in the OTP area. The OTP area cannot be erased, whether it is protected or not. Protecting the OTP area prevents further programming of that area.
Micron provides a unique way to program and verify data before permanently protecting it and preventing future changes. The OTP area is only accessible while in OTP operation mode. To set the device to OTP operation mode, issue the SET FEATURE (EFh) command to feature address 90h and write 01h to P1, followed by three cycles of 00h to P2-P4. For parameters to enter OTP mode, see Features Operations.
When the device is in OTP operation mode, all subsequent PAGE READ (00h-30h) and PROGRAM PAGE (80h-10h) commands are applied to the OTP area. The OTP area is assigned to page addresses 02h-31h. To program an OTP page, issue the PROGRAM PAGE (80h-10h) command. The pages must be programmed in the ascending order. Similarly, to read an OTP page, issue the PAGE READ (00h-30h) command.
Protecting the OTP is done by entering OTP protect mode. To set the device to OTP protect mode, issue the SET FEATURE (EFh) command to feature address 90h and write 03h to P1, followed by three cycles of 00h to P2-P4.
To determine whether the device is busy during an OTP operation, either monitor R/B# or use the READ STATUS (70h) command.
To exit OTP operation or protect mode, write 00h to P1 at feature address 90h.
Legacy OTP Commands
For legacy OTP commands, OTP DATA PROGRAM (A0h-10h), OTP DATA PROTECT (A5h-10h), and OTP DATA READ (AFh-30h).
OTP DATA PROGRAM (80h-10h)
The OTP DATA PROGRAM (80h-10h) command is used to write data to the pages within the OTP area. An OTP page allows only four partial-page programs. There is no ERASE operation for OTP pages.
PROGRAM PAGE enables programming into an offset of an OTP page using two bytes of the column address (CA[12:0]). The command is compatible with the RANDOM DATA INPUT (85h) command. The PROGRAM PAGE command will not execute if the OTP area has been protected.
To use the PROGRAM PAGE command, issue the 80h command. Issue n address cycles. The first two address cycles are the column address. For the remaining cycles, select a page in the range of 02h-00h through 31h-00h. Next, write n bytes of data. After data input is complete, issue the 10h command. The internal control logic automatically executes the proper programming algorithm and controls the necessary timing for programming and verification.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

88

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP One-Time Programmable (OTP) Operations
R/B# goes LOW for the duration of the array programming time (tPROG). The READ STATUS (70h) command is the only valid command for reading status in OTP operation mode. Bit 5 of the status register reflects the state of R/B#. When the device is ready, read bit 0 of the status register to determine whether the operation passed or failed (see Status Operations). Each OTP page can be programmed to 4 partial-page programming.
RANDOM DATA INPUT (85h)
After the initial OTP data set is input, additional data can be written to a new column address with the RANDOM DATA INPUT (85h) command. The RANDOM DATA INPUT command can be used any number of times in the same page prior to the OTP PAGE WRITE (10h) command being issued.

Figure 56: OTP DATA PROGRAM (After Entering OTP Operation Mode)
CLE

CE# tWC
WE#
ALE

tWB tPROG

RE#

I/Ox

80h OTP DATA INPUT
command

Col add 1

Col

OTP

add 2 page1

00h

OTP address1

R/B#

00h

DnIN

DmIN

10h

1 up to m bytes PROGRAM serial input command

x8 device: m = 4320 bytes x16 device: m = 2160 words

Note: 1. The OTP page must be within the 02h­31h range.

70h READ STATUS
command

Status

OTP data written (following good status confirmation)
Don't Care

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

89

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP One-Time Programmable (OTP) Operations

Figure 57: OTP DATA PROGRAM Operation with RANDOM DATA INPUT (After Entering OTP Operation Mode)
CLE

CE# tWC
WE#
ALE

tADL

tADL

tWB tPROG

RE#

I/Ox

80h

Col add1

Col add2

pOagTPe1

00h

00h

SERIAL DATA INPUT command

R/B#

DnIN

nD+IN1

85h

Col Col add1 add2

Serial input RANDOM DATA Column address INPUT command

DnIN

nD+IN1

Serial input

10h PROGRAM command

70h READ STATUS
command

Status

Don`t Care

OTP DATA PROTECT (80h-10)
The OTP area is protected on a block basis. To protect a block, set the device to OTP protect mode, then issue the PROGRAM PAGE (80h-10h) command and write OTP address 00h, 00h, 00h, 00h. To set the device to OTP protect mode, issue the SET FEATURE (EFh) command to 90h (feature address) and write 03h to P1, followed by three cycles of 00h to P2-P4.
After the data is protected, it cannot be programmed further. When the OTP area is protected, the pages within the area are no longer programmable and cannot be unprotected.
To use the PROGRAM PAGE command to protect the OTP area, issue the 80h command, followed by n address cycles, write 00h data, data cycle of 00h, followed by the 10h command. (An example of the address sequence is shown in the following figure.) If an OTP DATA PROGRAM command is issued after the OTP area has been protected, R/B# will go LOW for tOBSY.
The READ STATUS (70h) command is the only valid command for reading status in OTP operation mode. Bit 5 of the status register reflects the state of R/B#.
When the device is ready, read bit 0 of the status register to determine whether the operation passed or failed (see Status Operations).

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

90

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP One-Time Programmable (OTP) Operations

Figure 58: OTP DATA PROTECT Operation (After Entering OTP Protect Mode)
CLE

CE# tWC
WE#
ALE

tWB

tPROG

RE#

I/Ox

80h

Col 00h

Col 00h

pOaTgPe

00h

00h

OTP DATA PROTECT command

OTP address

R/B#

DIN 10h PROGRAM command

70h READ STATUS
command

Status

OTP data protected1 Don't Care

Note: 1. OTP data is protected following a good status confirmation.

OTP DATA READ (00h-30h)
To read data from the OTP area, set the device to OTP operation mode, then issue the PAGE READ (00h-30h) command. Data can be read from OTP pages within the OTP area whether the area is protected or not.
To use the PAGE READ command for reading data from the OTP area, issue the 00h command, and then issue five address cycles: for the first two cycles, the column address; and for the remaining address cycles, select a page in the range of 02h-00h-00h through 31h-00h-00h. Lastly, issue the 30h command. The PAGE READ CACHE MODE command is not supported on OTP pages.
R/B# goes LOW (tR) while the data is moved from the OTP page to the data register. The READ STATUS (70h) command is the only valid command for reading status in OTP operation mode. Bit 5 of the status register reflects the state of R/B# (see Status Operations).
Normal READ operation timings apply to OTP read accesses. Additional pages within the OTP area can be selected by repeating the OTP DATA READ command.
The PAGE READ command is compatible with the RANDOM DATA OUTPUT (05h-E0h) command.
Only data on the current page can be read. Pulsing RE# outputs data sequentially.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

91

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP ECC Protection

Figure 59: OTP DATA READ
CLE CE# WE# ALE

RE# I/Ox
R/B#

00h

Col add 1

Col add 2

pOagTeP1

00h

00h

OTP address

30h tR Busy

DOnUT

DnO+U1T

Note: 1. The OTP page must be within the 02h­31h range.

DOmUT Don't Care

Figure 60: OTP DATA READ with RANDOM DATA READ Operation

CLE CE#

t CLR

WE# ALE RE# I/Ox R/B#

t WB t AR

t WHR

t RC

t REA

t RR

00h

Col add 1

Col add 2

pOagTeP1

00h

00h

30h

DOnUT Dn O+U1T

Column addressn

tR Busy

05h

Col

Col

add 1 add 2

E0h

Column addressm

Note: 1. The OTP page must be within the range 02h­31h.

DOmUT mDO+U1T Don't Care

ECC Protection

Internal ECC enables 9-bit detection and 8-bit correction in 512 bytes (x8) of main area and 16 bytes (x8) of spare area or 256 words (x16) of the main area and 8 words (x16) of

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

92

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP ECC Protection

spare area. During the busy time for PROGRAM operations, internal ECC generates parity bits when error detection is complete. During READ operations the device executes the internal ECC engine (9-bit detection and 8-bit error correction). When the READ operation is complete, read status bit 0 must be checked to determine whether errors larger than eight bits have occurred.
Following the READ STATUS command, the device must be returned to read mode by issuing the 00h command.
Limitations of internal ECC include the spare area, defined in the Spare Area Mapping (x8) and (x16) tables, and ECC parity areas that cannot be written to. Each ECC user area (referred to main and spare) must be written within one partial-page program so that the NAND device can calculate the proper ECC parity. The number of partial-page programs within a page cannot exceed four.
During a PROGRAM operation, the device calculates an ECC code on the 4K page in the cache register, before the page is written to the NAND Flash array. The ECC code is stored in the spare area of the page.
During a READ operation, the page data is read from the array to the cache register, where the ECC code is calculated and compared with the ECC code value read from the array. If a 1- to 8-bit error is detected, the error is corrected in the cache register. Only corrected data is output on the I/O bus. The ECC status bit indicates whether the error correction was successful. The Spare Area Mapping (x8) and (x16) tables that follow show the ECC protection scheme used throughout a page.
With internal ECC, the user must accommodate the following:
· Spare area definitions provided in the Spare Area Mapping table below.
· WRITEs to ECC are supported for main and spare areas 0 and 1. WRITEs to the ECC area are prohibited (see the Spare Area Mapping table below).
· When using partial-page programming, the following conditions must both be met: First, in the main user area and in user meta data area, single partial-page programming operations must be used (see the Spare Area Mapping table below). Second, within a page, the user can perform a maximum of four partial-page programming operations.

Table 24: Spare Area Mapping (×8)

Max Byte Address User Data
1FFh 3FFh 5FFh 7FFh 9FFh BFFh DFFh FFFh User Meta Data

Min Byte Address
000h 200h 400h 600h 800h A00h C00h E00h

ECC Protected
Yes Yes Yes Yes Yes Yes Yes Yes

Area
Main 0 Main 1 Main 2 Main 3 Main 4 Main 5 Main 6 Main 7

Description
User data 0 User data 1 User data 2 User data 3 User data 4 User data 5 User data 6 User data 7

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

93

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP ECC Protection

Table 24: Spare Area Mapping (×8) (Continued)

Max Byte Address
100Fh 101Fh 102Fh 103Fh 104Fh 105Fh 106Fh 107Fh ECC 108Fh 109Fh 10AFh 10BFh 10CFh 10DFh 10EFh 10FFh

Min Byte Address
1000h 1010h 1020h 1030h 1040h 1050h 1060h 1070h
1080h 1090h 10A0h 10B0h 10C0h 10D0h 10E0h 10F0h

ECC Protected
Yes Yes Yes Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes Yes Yes Yes

Area Spare 0 Spare 1 Spare 2 Spare 3 Spare 4 Spare 5 Spare 6 Spare 7
Spare 0 Spare 1 Spare 2 Spare 3 Spare 4 Spare 5 Spare 6 Spare 7

Description User meta data User meta data User meta data User meta data User meta data User meta data User meta data User meta data
ECC for main/spare 0 ECC for main/spare 1 ECC for main/spare 2 ECC for main/spare 3 ECC for main/spare 4 ECC for main/spare 5 ECC for main/spare 6 ECC for main/spare 7

Table 25: Spare Area Mapping (×16)

Max Byte Address User Data
0FFh 1FFh 2FFh 3FFh 4FFh 5FFh 6FFh 7FFh User Meta Data 807h 80Fh 817h 81Fh 827h

Min Byte Address
000h 100h 200h 300h 400h 500h 600h 700h
800h 808h 810h 818h 820h

ECC Protected
Yes Yes Yes Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes

Area
Main 0 Main 1 Main 2 Main 3 Main 4 Main 5 Main 6 Main 7
Spare 0 Spare 1 Spare 2 Spare 3 Spare 4

Description
User data 0 User data 1 User data 2 User data 3 User data 4 User data 5 User data 6 User data 7
User meta data User meta data User meta data User meta data User meta data

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

94

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP ECC Protection

Table 25: Spare Area Mapping (×16) (Continued)

Max Byte Address
82Fh 837h 83Fh ECC 847h 84Fh 857h 85Fh 867h 86Fh 877h 87Fh

Min Byte Address
828h 830h 838h
840h 848h 850h 858h 860h 868h 870h 878h

ECC Protected
Yes Yes Yes
Yes Yes Yes Yes Yes Yes Yes Yes

Area Spare 5 Spare 6 Spare 7
Spare 0 Spare 1 Spare 2 Spare 3 Spare 4 Spare 5 Spare 6 Spare 7

Description User meta data User meta data User meta data
ECC for main/spare 0 ECC for main/spare 1 ECC for main/spare 2 ECC for main/spare 3 ECC for main/spare 4 ECC for main/spare 5 ECC for main/spare 6 ECC for main/spare 7

Table 26: ECC Status

Bit 4 0 0 0 0 1 1 1

Bit 3 0 0 1 1 0 0 1

1

1

Bit 0 0 1 0 1 0 1 0
1

Description No bit errors were detected. More than 8 bits error were detected and not corrected. 4 to 6 bit errors were detected and corrected. Refresh is recommended. Reserved 1 to 3 bit errors/page were detected and corrected. Reserved 7 to 8 bit errors were detected and corrected. Refresh is required to guarantee data retention. Reserved

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

95

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Error Management
Error Management
Each NAND Flash die (LUN) is specified to have a minimum number of valid blocks (NVB) of the total available blocks. This means the die (LUNs) could have blocks that are invalid when shipped from the factory. An invalid block is one that contains at least one page that has more bad bits than can be corrected by the minimum required ECC. Additional blocks can develop with use. However, the total number of available blocks per die (LUN) will not fall below NVB during the endurance life of the product.
Although NAND Flash memory devices could contain bad blocks, they can be used quite reliably in systems that provide bad block management and error-correction algorithms. This type of software environment ensures data integrity.
Internal circuitry isolates each block from other blocks, so the presence of a bad block does not affect the operation of the rest of the NAND Flash array.
NAND Flash devices are shipped from the factory erased. The factory identifies invalid blocks before shipping by attempting to program the bad block mark into every location in the first page of each invalid block. It may not be possible to program every location with the bad block mark. However, the first spare area location in each bad block is guaranteed to contain the bad block mark. This method is compliant with ONFI Factory Defect Mapping requirements.
System software should check the first spare area location on the first page of each block prior to performing any PROGRAM or ERASE operations on the NAND Flash device. A bad block table can then be created, enabling system software to map around these areas. Factory testing is performed under worst-case conditions. Because invalid blocks could be marginal, it may not be possible to recover this information if the block is erased.
Over time, some memory locations may fail to program or erase properly. In order to ensure that data is stored properly over the life of the NAND Flash device, the following precautions are required:
· Always check status after a PROGRAM or ERASE operation · Under typical conditions, use the minimum required ECC (see table below) · Use bad block management and wear-leveling algorithms

Table 27: Error Management Details

Description Minimum number of valid blocks (NVB) per LUN Total available blocks per LUN First spare area location
Bad block mark
Minimum required ECC Minimum ECC with internal ECC enabled

Requirement
2008
2048
×8: byte 4096 ×16: word 2048
×8: 00h ×16: 0000h
8-bit ECC per 544 bytes of data
8-bit ECC per 528 bytes (user data) + 16 bytes (parity data)

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

96

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Electrical Specifications
Electrical Specifications
Stresses greater than those listed can cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. Exposure to absolute maximum rating conditions for extended periods can affect reliability.

Table 28: Absolute Maximum Ratings

Parameter/Condition Voltage input VCC supply voltage Storage temperature Electrostatic discharge voltage

3.3V 3.3V

Symbol
VIN VCC TSTG VESD

Min ­0.6 ­0.6 ­65 ­2000

Note: 1. All specified voltages are with respect to VSS.

Max +4.6 +4.6 +150 2000

Table 29: Recommended Operating Conditions

Parameter/Condition

Symbol

Min

Typ

Max

VCC supply voltage
Ground supply voltage Operating temperature

1.8V 3.3V
Industrial Automotive

VCC

1.7

VCC

2.7

VSS

0

TA

­40

­40

1.8

1.95

3.3

3.6

0

0

­

+85

­

+105

Notes: 1. 2. All specified voltages are with respect to VSS.

Table 30: Capacitance

Description Input/output capacitance (I/O) Input capacitance Input capacitance

Symbol CIO
CIN (4Gb) CIN (8Gb)

Max 8 6 9

Unit pF pF pF

Notes: 1. These parameters will be verified in device characterization. 2. Test conditions: TC = 25°C; f = 1 MHz; Vin = 0V.

Table 31: Test Conditions
Parameter Input pulse levels Input rise and fall times Input and output timing levels

Value 0.0V to VCC
5ns VCC/2

Unit V V °C V
Unit V V V °C °C
Notes 1, 2 1, 2 1, 2
Notes

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

97

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Electrical Specifications

Table 31: Test Conditions (Continued)
Parameter Output load

Value 1 TTL GATE and CL = 50pF (3.3V, 1.8V)

Note: 1. These parameters will be verify in device characterization.

Notes 1

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

98

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Electrical Specifications ­ DC Characteristics and Operating
Conditions
Electrical Specifications ­ DC Characteristics and Operating Conditions

Table 32: DC Characteristics and Operating Conditions (3.3V)

Parameter

Conditions

Symbol Min

Typ

Max

Unit

Sequential read current tRC = tRC (MIN); CE# = VIL;

ICC1

­

ECC off

IOUT = 0mA

Sequential read current tRC = tRC (MIN); CE# = VIL;

ICC1

­

ECC on

IOUT = 0mA

Program current ECC off

­

ICC2

­

Program current ECC on

­

ICC2

Erase current

­

ICC3

­

Standby current (TTL)

CE# = VIH; WP# = 0V/VCC

ISB1

­

Standby current (CMOS)

CE# = VCC - 0.2V;

ISB2

­

WP# = 0V/VCC

Staggered power-up cur-

Rise time = 1ms

IST

­

rent

Line capacitance = 0.1µF

15

20

mA

25

35

mA

15

20

mA

20

25

mA

15

20

mA

­

1

mA

20

100

µA

­

10 per die mA

Input leakage current

VIN = 0V to VCC

ILI

­

­

±10

µA

Output leakage current

VOUT = 0V to VCC

ILO

­

­

±10

µA

Input high voltage

I/O[7:0], I/O[15:0],

VIH

0.8 × VCC

­

VCC + 0.3

V

CE#, CLE, ALE, WE#, RE#,

WP#, R/B#

Input low voltage, all in-

­

puts

VIL

­0.3

­

0.2 × VCC

V

Output high voltage Output low voltage Output low current

IOH = ­400µA IOL = 2.1mA VOL = 0.4V

VOH 0.67 × VCC

­

VOL

­

­

IOL (R/B#)

8

10

­

V

0.4

V

­

mA

Notes 1 1 1 1 1
2
3 3 4

Notes:

1. Typical and maximum values are for single-plane operation only.
2. Measurement is taken with 1ms averaging intervals and begins after VCC reaches VCC,min. 3. IOL (R/B#) may need to be relaxed if R/B pull-down strength is not set to full. 4. VOH and VOL may need to be relaxed if I/O drive strength is not set to full.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

99

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Electrical Specifications ­ DC Characteristics and Operating
Conditions

Table 33: DC Characteristics and Operating Conditions (1.8V)

Parameter Sequential read current ECC off Sequential read current ECC on Program current ECC on Program current ECC off Erase current Standby current (TTL)
Standby current (CMOS)
Staggered power-up current Input leakage current Output leakage current Input high voltage
Input low voltage, all inputs Output high voltage Output low voltage Output low current

Conditions
tRC = tRC (MIN); CE# = VIL; IOUT = 0mA
tRC = tRC (MIN); CE# = VIL; IOUT = 0mA ­
­
­
CE# = VIH; LOCK = WP# = 0V/VCC
CE# = VCC - 0.2V; LOCK = WP# = 0V/VCC
Rise time = 1ms Line capacitance = 0.1µF
VIN = 0V to VCC VOUT = 0V to VCC I/O[7:0], I/O[15:0], CE#, CLE, ALE, WE#, RE#, WP#, R/B#, LOCK
­

Symbol ICC1
­
ICC2 ICC2 ICC3 ISB1
ISB2
IST
ILI ILO VIH
VIL

IOH = ­100µA IOL = 100µA VOL = 0.2V

VOH VOL IOL (R/B#)

Min ­
­
­ ­ ­ ­
­
­
­ ­ 0.8 × VCC
­0.3
VCC - 0.2 ­ 3

Typ

Max

Unit

13

20

mA

25

35

mA

13

20

mA

20

25

mA

15

20

mA

­

1

mA

15

50

µA

­

10 per die mA

­

±10

µA

­

±10

µA

­

VCC + 0.3

V

­

0.2 × VCC

V

­

­

V

­

0.2

V

4

­

mA

Notes 1, 2 1, 2 1, 2 1, 2 1, 2
3
4 4 5

Notes:

1. Typical and maximum values are for single-plane operation only.
2. Values are for single die operations. Values could be higher for interleaved die operations.
3. Measurement is taken with 1ms averaging intervals and begins after VCC reaches VCC,min. 4. Test conditions for VOH and VOL. 5. DC characteristics may need to be relaxed if R/B# pull-down strength is not set to full.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

100

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Electrical Specifications ­ AC Characteristics and Operating
Conditions
Electrical Specifications ­ AC Characteristics and Operating Conditions

Table 34: AC Characteristics: Command, Data, and Address Input (3.3V)

Parameter ALE to data start ALE hold time ALE setup time CE# hold time CLE hold time CLE setup time CE# setup time Data hold time Data setup time WRITE cycle time WE# pulse width HIGH WE# pulse width WP# transition to WE# LOW

Symbol tADL tALH tALS tCH tCLH tCLS tCS tDH tDS tWC tWH tWP tWW

Min 70 5 10 5 5 10 15 5 7 20 7 10 100

Max ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns

Notes 1
1 1 1

Note: 1. Timing for tADL begins in the address cycle, on the final rising edge of WE#, and ends with the first rising edge of WE# for data input.

Table 35: AC Characteristics: Command, Data, and Address Input (1.8V)

Parameter ALE to data start ALE hold time ALE setup time CE# hold time CLE hold time CLE setup time CE# setup time Data hold time Data setup time WRITE cycle time WE# pulse width HIGH WE# pulse width WP# transition to WE# LOW

Symbol tADL tALH tALS tCH tCLH tCLS tCS tDH tDS tWC tWH tWP tWW

Min 100
5 10 5 5 10 25 5 10 30 10 15 100

Max ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns

Notes 1
1 1 1

Note: 1. Timing for tADL begins in the address cycle, on the final rising edge of WE#, and ends with the first rising edge of WE# for data input.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

101

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Electrical Specifications ­ AC Characteristics and Operating
Conditions

Table 36: AC Characteristics: Normal Operation (3.3V)

Note 1 applies to all Parameter ALE to RE# delay CE# access time CE# HIGH to output High-Z CLE to RE# delay CE# HIGH to output hold Output High-Z to RE# LOW READ cycle time RE# access time RE# HIGH hold time RE# HIGH to output hold RE# HIGH to WE# LOW RE# HIGH to output High-Z RE# LOW to output hold RE# pulse width Ready to RE# LOW Reset time (READ/PROGRAM/ERASE) WE# HIGH to busy WE# HIGH to RE# LOW ALE to RE# delay

Symbol tAR tCEA tCHZ tCLR tCOH tIR tRC tREA tREH
tRHOH tRHW tRHZ tRLOH
tRP tRR tRST tWB tWHR tAR

Min 10 ­ ­ 10 15 0 20 ­ 7 15 100 ­ 5 10 20 ­ ­ 60 10

Max ­ 25 30 ­ ­ ­ ­ 16 ­ ­ ­
100 ­ ­ ­
5/10/500 100 ­ ­

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ns ns ns

Notes 2
2 3 4

Notes:

1. AC characteristics may need to be relaxed if I/O drive strength is not set to "full."
2. Transition is measured ±200mV from steady-state voltage with load. This parameter is sampled and not 100% tested.
3. The first time the RESET (FFh) command is issued while the device is idle, the device will go busy for a maximum of 1ms. Thereafter, the device goes busy for a maximum of 5µs.
4. Do not issue a new command during tWB, even if R/B# is ready.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

102

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Electrical Specifications ­ AC Characteristics and Operating
Conditions

Table 37: AC Characteristics: Normal Operation (1.8V)

Note 1 applies to all Parameter ALE to RE# delay CE# access time CE# HIGH to output High-Z CLE to RE# delay CE# HIGH to output hold Output High-Z to RE# LOW READ cycle time RE# access time RE# HIGH hold time RE# HIGH to output hold RE# HIGH to WE# LOW RE# HIGH to output High-Z RE# pulse width Ready to RE# LOW Reset time (READ/PROGRAM/ERASE) WE# HIGH to busy WE# HIGH to RE# LOW

Symbol tAR tCEA tCHZ tCLR tCOH tIR tRC tREA tREH
tRHOH tRHW tRHZ
tRP tRR tRST tWB tWHR

Min 10 ­ ­ 10 15 0 30 ­ 10 15 100 ­ 15 20 ­ ­ 80

Max ­ 30 50 ­ ­ ­ ­ 25 ­ ­ ­ 65 ­ ­
7/13/600 100 ­

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ns ns

Notes 2
2 3 4

Notes:

1. AC characteristics may need to be relaxed if I/O drive strength is not set to "full."
2. Transition is measured ±200mV from steady-state voltage with load. This parameter is sampled and not 100% tested.
3. The first time the RESET (FFh) command is issued while the device is idle, the device will go busy for a maximum of 1ms. Thereafter, the device goes busy for a maximum of 5µs.
4. Do not issue a new command during tWB, even if R/B# is ready.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

103

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Electrical Specifications ­ Program/Erase Characteristics
Electrical Specifications ­ Program/Erase Characteristics

Table 38: Program/Erase Characteristics

Parameter Number of partial-page programs (AIT) Number of partial-page programs (AAT) BLOCK ERASE operation time Busy time for PROGRAM CACHE operation 3.3V VCC Cache read busy time Cache read busy time ECC enabled 3.3V VCC Cache read busy time ECC enabled 1.8V VCC Busy time for SET FEATURES and GET FEATURES operations LAST PAGE PROGRAM operation time Busy time for OTP DATA PROGRAM operation if OTP is protected (ECC disabled) Busy time for OTP DATA PROGRAM operation if OTP is protected (ECC enabled), 3.3V Busy time for OTP DATA PROGRAM operation if OTP is protected (ECC enabled), 1.8V Busy time for PROGRAM/ERASE on locked blocks PROGRAM PAGE operation time PROGRAM PAGE ECC ON operation time Power-on reset time READ PAGE operation time READ PAGE operation time ECC enabled 3.3V VCC READ PAGE operation time ECC enabled 1.8V VCC

Symbol NOP
tBERS tCBSY tRCBSY tRCBSY_ECC
tFEAT
tLPROG tOBSY
tOBSY_ECC
tLBSY tPROG tPROG_ECC tPOR
tR tR_ECC

Typ

Max

Unit

Notes

­

4

cycles

1

­

4

cycles

1

2

10

ms

3

600

µs

2

5

25

µs

80

115

µs

90

170

µs

­

1

µs

­

­

­

3

­

30

µs

­

75

µs

­

90

µs

­

3

µs

200

600

µs

240

600

µs

­

1

ms

­

25

µs

80

115

µs

90

170

µs

Notes:

1. Four total partial-page programs to the same page.
2. tCBSY (MAX) time depends on timing between internal program completion and datain.
3. tLPROG = tPROG (last page) + tPROG (last - 1 page) - command load time (last page) address load time (last page) - data load time (last page).

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

104

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Asynchronous Interface Timing Diagrams
Asynchronous Interface Timing Diagrams
Figure 61: RESET Operation
CLE

CE# WE# R/B#

tWB

tRST

I/O[7:0]

FFh RESET command

Figure 62: READ STATUS Cycle

CLE CE# WE#

RE#

I/O[7:0]

tCLS tCS tWP

tCLR tCLH

tCH tWHR

tCEA tRP

tDS

tDH

70h

tIR

tREA

tCOH

tCHZ

tRHZ tRHOH
Status output

Don't Care

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

105

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Asynchronous Interface Timing Diagrams
Figure 63: READ STATUS ENHANCED Cycle

CE# CLE WE#
ALE RE#
I/O[7:0]

tCS

tCLS

tCLH

tWP

tWC tWP tWH

tALH

tALS

tCH

tALH

tCEA tAR

tCHZ tCOH

tDS

tDH

78h

Row add 1 Row add 2 Row add 3

tWHR

tREA

tRHZ tRHOH

Status output

Don't Care

Figure 64: READ PARAMETER PAGE

CLE WE#
ALE RE#

tWB

I/O[7:0]

ECh

00h

tR R/B#

tRC

tRR

tRP

P00

P10

P2550

P01

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

106

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Asynchronous Interface Timing Diagrams

Figure 65: READ PAGE
CLE CE#
tWC WE#

ALE RE#

I/Ox

00h

Col

Col Row Row Row

add 1 add 2 add 1 add 2 add 3

RDY

tCLR

tWB tAR

tR

tRC

tRR

tRP

30h

DONUT

NDO+U1T

Busy

tRHZ DMOUT Don't Care

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

107

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Asynchronous Interface Timing Diagrams

Figure 66: READ PAGE Operation with CE# "Don't Care"
CLE CE# RE#

ALE tR
RDY
WE#

I/Ox

00h

Address (5 cycles)

30h
CE# RE# I/Ox

tCEA

tREA

tCHZ tCOH

Out

Data output

Don't Care

Figure 67: RANDOM DATA READ
CLE
CE# WE#
ALE
tRC
RE#

tRHW

tCLR
tWHR tREA

I/Ox

DOUT
N - 1

DOUT
N

RDY

05h

Col Col add 1 add 2

E0h

Column address M

DOUT
M

DOUT
M + 1

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

108

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Asynchronous Interface Timing Diagrams

Figure 68: READ PAGE CACHE SEQUENTIAL

CLE
tCLS tCS
CE#
WE#

tCLH tCH
tWC

ALE

RE#
tDH
tDS

I/Ox

00h

RDY

Col add 1

Col add 2

Row add 1

Row add 2

tWB

Row add 3

30h

Column address 00h

Page address M

CLE CE#

tCLS tCLH
tCS tCH

tCLS tCLH
tCS tCH

tCEA

tRHW

tRC

tR 31h

tREA tRR

DO0UT

DO1UT

tDS
DOUT

tWB
tDH 31h

tRCBSY

Page address M

Column address 0
1

WE#
ALE
tRC

tRHW

tCEA tRC

tRHW

RE# I/Ox

tREA

DO0UT

DO1UT

tDS
DOUT

tWB tRR
tDH 31h

tREA

DO0UT

DO1UT

DOUT

3Fh

Page address M
RDY
Column address 0

tRCBSY

Page address M + 1

Column address 0

1

tRCBSY

DO0UT

DO1UT

DOUT

Page address M + 2

Column address 0

Don't Care

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

109

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Asynchronous Interface Timing Diagrams

Figure 69: READ PAGE CACHE RANDOM

CLE
tCLS tCS
CE#
WE#

tCLH tCH
tWC

ALE

RE#

tDH

tDS

I/Ox

00h

Col

Col

Row Row Row

add 1 add 2 add 1 add 2 add 3

RDY

Column address 00h

Page address M

tWB

tR

30h

00h

Col

Col

Row Row

add 1 add 2 add 1 add 2

Column address 00h

Page address N

1

CLE

tCLS

tCLH

tCS

tCH

CE#

WE#

tCEA

tRHW

ALE

RE#

tDS

I/Ox

Col

Col

add 1 add 2

Row Row Row add 1 add 2 add 3

Column address 00h

Page address N

tWB tRR
tDH 31h
tRCBSY

tRC

tREA

DO0UT

DO1UT

DOUT

Page address M

RDY
1

Column address 0

3Fh tRCBSY

DO0UT

DO1UT

DOUT

Page address N

Column address 0

Don't Care

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

110

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Asynchronous Interface Timing Diagrams

Figure 70: READ ID Operation

CLE CE#

WE#
ALE RE#
I/Ox

tAR

tWHR

tREA

90h

00h or 20h

Address, 1 cycle

Byte 0

Byte 1

Figure 71: PROGRAM PAGE Operation
CLE CE#

tWC WE#

tADL

Byte 2

Byte 3

tWB tPROG

Byte 4
tWHR

ALE RE#

I/Ox

80h

RDY

Col

Col

Row

Row Row

add 1 add 2 add 1 add 2 add 3

DNIN

DMIN

10h

1 up to m byte serial Input

70h

Status

Don't Care

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

111

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Asynchronous Interface Timing Diagrams
Figure 72: PROGRAM PAGE Operation with CE# "Don't Care"
CLE CE# WE#

ALE I/Ox 80h

Address (5 cycles)

CE# WE#

Data input tCS tCH tWP

Data input

10h

Don't Care

Figure 73: PROGRAM PAGE Operation with RANDOM DATA INPUT

CLE CE#
tWC WE#

tADL

tADL

ALE RE#

tWB tPROG

tWHR

I/Ox RDY

80h

Col Col Row Row Row add 1 add 2 add 1 add 2 add 3

DMIN

DNIN

85h

Col Col add 1 add 2

DPIN

DQIN

10h

CHANGE WRITE Column address Serial input COLUMN command

Serial input

70h
READ STATUS command

Status

Don't Care

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

112

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Asynchronous Interface Timing Diagrams

Figure 74: PROGRAM PAGE CACHE

CLE CE#
tWC WE#
ALE RE#

tWB tCBSY

I/Ox 80h RDY

aCdodl1

aCdodl2

Row add 1

Row add 2

Row add 3

DNIN

DMIN

15h

Serial input

Last page - 1

tADL

tWB tLPROG

tWHR

80h

aCdodl1

aCdodl2

Row add 1

Row add 2

Row add 3

DNIN

DMIN 10h

Last page

70h

Status

Don't Care

Figure 75: PROGRAM PAGE CACHE Ending on 15h

CLE CE#

WE#

tWC

tADL

ALE RE# I/Ox 80h

Col Col Row Row Row add 1 add 2 add 1 add 2 add 3

DNIN

DMIN 15h 70h Status

80h

Serial input

Last page ­ 1

tADL

Col Col Row Row Row add 1 add 2 add 1 add 2 add 3

DNIN

Last page

tWHR

tWHR

DMIN 15h

70h Status

70h Status

Poll status until: I/O6 = 1, Ready

To verify successful completion of the last 2 pages: I/O5 = 1, Ready I/O0 = 0, Last page PROGRAM successful I/O1 = 0, Last page ­ 1 PROGRAM successful

Don't Care

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

113

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Asynchronous Interface Timing Diagrams

Figure 76: INTERNAL DATA MOVE
CLE

CE# WE#

tWC

ALE

tWB

tADL

tWB tPROG

tWHR

RE#

tR

I/Ox

00h

aCdodl1 aCdodl2 aRdodw1 aRdodw2 aRdodw3 (or353h0h)

85h

RDY

Busy

aCdodl1 aCdodl2 aRdodw1 aRdodw2 aRdodw3 Da1ta

DNata 10h

70h

Status

READ STATUS Busy command

Data Input Optional

Don't Care

Figure 77: ERASE BLOCK Operation
CLE CE#

WE#
ALE RE# I/O[7:0] RDY

tWC

tWB

60h

Row Row Row add 1 add 2 add 3

D0h

Row address

tBERS Busy

tWHR

70h
READ STATUS command

Status

I/O0 = 0, Pass I/O0 = 1, Fail

Don't Care

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

114

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP 4Gb: x16 Mobile LPDDR4/LPDDR4X SDRAM

4Gb: x16 Mobile LPDDR4/LPDDR4X SDRAM
Hereafter, for general 4Gb Mobile LPDDR4/LPDDR4X SDRAM, only one die specification is described. Electrical specification, including die internal organization and operating temperature range, are defined in Features in cover page. IDD values can be calculated according to the die configuration in the package.

Features

· Ultra-low-voltage core and I/O power supplies ­ VDD1 = 1.70­1.95V; 1.8V nominal ­ VDD2 = 1.06­1.17V; 1.10V nominal ­ VDDQ = 1.06­1.17V; 1.10V nominal or Low VDDQ = 0.57­0.65V; 0.60V nominal
· JEDEC LPDDR4/LPDDR4X-compliant · Frequency range
­ 2133­10 MHz (data rate range: 4266­20 Mb/s/pin) · 16n prefetch DDR architecture · 8 internal banks per channel for concurrent operation · Single-data-rate CMD/ADR entry · Bidirectional/differential data strobe per byte lane · Programmable READ and WRITE latencies (RL/WL) · Programmable and on-the-fly burst lengths (BL = 16, 32) · Directed per-bank refresh for concurrent bank operation and ease of command
scheduling · Up to 8.5 GB/s per die · On-chip temperature sensor to control self refresh rate · Partial-array self refresh (PASR) · Selectable output drive strength (DS) · Clock-stop capability · RoHS-compliant, "green" packaging · Programmable VSS (ODT) termination

Table 39: Key Timing Parameters

Speed Grade
-053
-046

Clock Rate (MHz)
1866
2133

Data Rate (Mb/s/pin)
3733
4266

WRITE Latency

Set A

Set B

16

30

18

34

READ Latency

DBI Disabled

DBI Enabled

32

36

36

40

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

115

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP General Description

General Description
The 4Gb Mobile Low-Power DDR4 SDRAM with low VDDQ (LPDDR4X) is a high-speed CMOS, dynamic random-access memory. The device is internally configured with x16 I/O, 8-banks.
Each of the x16's 536,870,912-bit banks is organized as 32,768 rows by 1024 columns by 16 bits.

General Notes

Throughout the data sheet, figures and text refer to DQs as "DQ." DQ should be interpreted as any or all DQ collectively, unless specifically stated otherwise.
"DQS" and "CK" should be interpreted as DQS_t, DQS_c and CK_t, CK_c respectively, unless specifically stated otherwise. "CA" includes all CA pins used for a given density.
In timing diagrams, "CMD" is used as an indicator only. Actual signals occur on CA[5:0]. VREF indicates VREF(CA) and VREF(DQ).
Complete functionality may be described throughout the entire document. Any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements.
Any specific requirement takes precedence over a general statement.
Any functionality not specifically stated herein is considered undefined, illegal, is not supported, and will result in unknown operation.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

116

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP MR0, MR[6:5], MR8, MR13, MR24 Definition
MR0, MR[6:5], MR8, MR13, MR24 Definition

Table 40: Mode Register Contents

Mode Register MR0
MR5 MR6 MR8
MR13
MR24

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

Latency

REF

Mode

OP[0] = 0b: Both legacy and modified refresh mode supported OP[1] = 0b: Device supports normal latency

Manufacturer ID

1111 1111b : Micron

Revision ID1

0000 0011b

I/O Width

Density

OP[7:6] = 00b: x16/channel

OP[5:2] = 0010b: 4Gb single-channel die

VRO

TRR Mode

OP[2] = 0b: Normal operation (default)

1b: Output the VREF(CA) value on DQ7 and VREF(DQ) value on DQ6

Unlimited

MAC Value

MAC

OP[3:0] = 1000b: Unlimited MAC

OP[7] = 0b: Disable (default) 1b: Reserved

Notes:

1. The contents of MR0, MR[6:5], MR8, MR13, and MR24 will reflect information specific to each die in these packages.
2. Other bits not defined above and other mode registers are referred to Mode Register Assignments and Definitions section.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

117

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 IDD Parameters
LPDDR4 IDD Parameters
Refer to LPDDR4 IDD Specification Parameters and Test Conditions section for detailed conditions.

Table 41: LPDDR4 IDD Specifications under 3733 Mb/s ­ Single Die

VDD2, VDDQ = 1.06­1.17V; VDD1 = 1.70­1.95V

Parameter
IDD01 IDD02 IDD0Q IDD2P1 IDD2P2 IDD2PQ IDD2PS1 IDD2PS2 IDD2PSQ IDD2N1 IDD2N2 IDD2NQ IDD2NS1 IDD2NS2 IDD2NSQ IDD3P1 IDD3P2 IDD3PQ IDD3PS1 IDD3PS2 IDD3PSQ IDD3N1 IDD3N2 IDD3NQ IDD3NS1 IDD3NS2 IDD3NSQ IDD4R1 IDD4R2 IDD4RQ IDD4W1 IDD4W2 IDD4WQ

Supply
VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ

95°C 3.2 40.0 0.80 1.4 2.6 0.80 1.4 2.6 0.80 1.4 22.8 0.80 1.4 18.0 0.80 1.4 13.0 0.80 1.4 13.0 0.80 1.7 27.3 0.80 1.7 21.4 0.80 2.1 322 137 2.1 272 0.80

TC/3733 Mb/s 105°C 3.2 40.0 0.80 1.4 2.6 0.80 1.4 2.6 0.80 1.4 25.0 0.80 1.4 18.0 0.80 1.4 13.0 0.80 1.4 13.0 0.80 1.7 28.0 0.80 1.7 22.0 0.80 2.1 330 137 2.1 280 0.80

125°C 3.8 45.2 1.0 1.9 3.4 1.2 1.9 3.4 1.2 2.0 30.4 1.0 2.0 23.2 1.0 2.0 18.5 1.2 2.0 18.5 1.2 2.2 34.9 1.0 2.2 27.5 1.0 2.5 342 139 2.5 292 0.90

Unit mA

Note

mA

mA

mA

mA

mA

mA

mA

mA

mA

2, 3

mA

3

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

118

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 IDD Parameters

Table 41: LPDDR4 IDD Specifications under 3733 Mb/s ­ Single Die (Continued)

VDD2, VDDQ = 1.06­1.17V; VDD1 = 1.70­1.95V

Parameter
IDD51 IDD52 IDD5Q IDD5AB1 IDD5AB2 IDD5ABQ IDD5PB1 IDD5PB2 IDD5PBQ

Supply
VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ5 VDD1 VDD2 VDDQ

95°C 10.0 76.0 0.80 4.2 40.0 0.80 4.2 40.0 0.80

TC/3733 Mb/s 105°C 10.0 76.0 0.80 4.2 40.0 0.80 4.2 40.0 0.80

125°C 11.2 83.0 1.0 5.8 47.1 1.0 5.8 47.4 1.0

Unit mA
mA
mA

Note

Notes:

1. Published IDD values, except IDD4RQ, are the maximum IDD values considering the worstcase conditions of process, temperature, and voltage. Refer to the note below for IDD4RQ; refer to IDD6 Full-Array Self Refresh Current table for IDD6.
2. IDD4RQ value is reference only. DBI disabled, VOH = VDDQ/3, TC = 25°C. 3. Measurement conditions of IDD4R and IDD4W values: DBI disabled, BL = 16.

Table 42: LPDDR4 IDD Specifications under 4266 Mb/s ­ Single Die

VDD2, VDDQ = 1.06­1.17V; VDD1 = 1.70­1.95V

Parameter
IDD01 IDD02 IDD0Q IDD2P1 IDD2P2 IDD2PQ IDD2PS1 IDD2PS2 IDD2PSQ IDD2N1 IDD2N2 IDD2NQ IDD2NS1 IDD2NS2 IDD2NSQ IDD3P1 IDD3P2 IDD3PQ

Supply
VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ

95°C 3.2 42.0 0.80 1.4 2.6 0.80 1.4 2.6 0.80 1.4 23.8 0.80 1.4 18.0 0.80 1.4 13.0 0.80

TC/4266 Mb/s 105°C 3.2 42.0 0.80 1.4 2.6 0.80 1.4 2.6 0.80 1.4 26.0 0.80 1.4 18.0 0.80 1.4 13.0 0.80

125°C 3.8 47.5 1.0 1.9 3.4 1.2 1.9 3.4 1.2 2.0 31.7 1.0 2.0 23.2 1.0 2.0 18.5 1.2

Unit mA

Note

mA

mA

mA

mA

mA

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

119

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 IDD Parameters

Table 42: LPDDR4 IDD Specifications under 4266 Mb/s ­ Single Die (Continued)

VDD2, VDDQ = 1.06­1.17V; VDD1 = 1.70­1.95V

Parameter
IDD3PS1 IDD3PS2 IDD3PSQ IDD3N1 IDD3N2 IDD3NQ IDD3NS1 IDD3NS2 IDD3NSQ IDD4R1 IDD4R2 IDD4RQ IDD4W1 IDD4W2 IDD4WQ IDD51 IDD52 IDD5Q IDD5AB1 IDD5AB2 IDD5ABQ IDD5PB1 IDD5PB2 IDD5PBQ

Supply
VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ5 VDD1 VDD2 VDDQ

95°C 1.4 13.0 0.80 1.7 28.3 0.80 1.7 21.4 0.80 2.2 366 152 2.2 296 0.80 10.5 80.0 0.80 4.2 45.0 0.80 4.2 45.0 0.80

TC/4266 Mb/s 105°C 1.4 13.0 0.80 1.7 29.0 0.80 1.7 22.0 0.80 2.2 375 152 2.2 305 0.80 10.5 80.0 0.80 4.2 45.0 0.80 4.2 45.0 0.80

125°C 2.0 18.5 1.2 2.2 36.2 1.0 2.2 27.5 1.0 2.7 389 155 2.7 319 0.90 11.8 87.4 1.0 5.8 53.0 1.0 5.8 53.4 1.0

Unit mA mA mA mA mA mA mA mA

Note
2, 3 3

Notes:

1. Published IDD values, except IDD4RQ, are the maximum IDD values considering the worstcase conditions of process, temperature, and voltage. Refer to the note below for IDD4RQ; refer to IDD6 Full-Array Self Refresh Current table for IDD6.
2. IDD4RQ value is typical reference only. DBI disabled, VOH = VDDQ/3, TC = 25°C. 3. Measurement conditions of IDD4R and IDD4W values: DBI disabled, BL = 16.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

120

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 IDD Parameters

Table 43: LPDDR4 IDD6 Full-Array Self Refresh Current

VDD2, VDDQ = 1.06­1.17V; VDD1 = 1.70­1.95V

Self Refresh Current/3733 Mb/s and 4266 Mb/s

Temperature

Supply

Full-Array

1/2-Array

1/4-Array

1/8-Array

25°C 95°C 105°C

VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ

0.10 0.30 0.01 2.5 8.4 0.80 2.5 12.0 0.80

0.10 0.30 0.01 2.0 6.3 0.80 2.0 9.0 0.80

0.10 0.30 0.01 2.0 5.0 0.80 2.0 7.2 0.80

0.10 0.30 0.01 2.0 4.2 0.80 2.0 6.0 0.80

Unit mA

Notes:

1. IDD6 25°C is the typical, IDD6 95°C and IDD6 105°C are the maximum IDD value considering the worst-case conditions of process, temperature, and voltage.
2. When TC > 105°C, self refresh mode is not available.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

121

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4X IDD Parameters
LPDDR4X IDD Parameters
Refer to LPDDR4X IDD Specification Parameters and Test Conditions section for detailed conditions.

Table 44: LPDDR4X IDD Specifications under 3733 Mb/s ­ Single Die

VDD2 = 1.06­1.17V; VDDQ = 0.57­0.65V; VDD1 = 1.70­1.95V

Parameter
IDD01 IDD02 IDD0Q IDD2P1 IDD2P2 IDD2PQ IDD2PS1 IDD2PS2 IDD2PSQ IDD2N1 IDD2N2 IDD2NQ IDD2NS1 IDD2NS2 IDD2NSQ IDD3P1 IDD3P2 IDD3PQ IDD3PS1 IDD3PS2 IDD3PSQ IDD3N1 IDD3N2 IDD3NQ IDD3NS1 IDD3NS2 IDD3NSQ IDD4R1 IDD4R2 IDD4RQ IDD4W1 IDD4W2 IDD4WQ

Supply
VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ

95°C 3.2 40.0 0.80 1.4 2.6 0.80 1.4 2.6 0.80 1.4 22.8 0.80 1.4 18.0 0.80 1.4 13.0 0.80 1.4 13.0 0.80 1.7 27.3 0.80 1.7 21.4 0.80 2.1 322 91.0 2.1 272 0.80

TC/3733 Mb/s 105°C 3.2 40.0 0.80 1.4 2.6 0.80 1.4 2.6 0.80 1.4 25.0 0.80 1.4 18.0 0.80 1.4 13.0 0.80 1.4 13.0 0.80 1.7 28.0 0.80 1.7 22.0 0.80 2.1 330 91.0 2.1 280 0.80

125°C 3.8 45.2 1.0 1.9 3.4 1.2 1.9 3.4 1.2 2.0 30.4 1.0 2.0 23.2 1.0 2.0 18.5 1.2 2.0 18.5 1.2 2.2 34.9 1.0 2.2 27.5 1.0 2.5 342 92.6 2.5 292 0.90

Unit mA

Note

mA

mA

mA

mA

mA

mA

mA

mA

mA

2, 3

mA

3

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

122

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4X IDD Parameters

Table 44: LPDDR4X IDD Specifications under 3733 Mb/s ­ Single Die (Continued)

VDD2 = 1.06­1.17V; VDDQ = 0.57­0.65V; VDD1 = 1.70­1.95V

Parameter
IDD51 IDD52 IDD5Q IDD5AB1 IDD5AB2 IDD5ABQ IDD5PB1 IDD5PB2 IDD5PBQ

Supply
VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ5 VDD1 VDD2 VDDQ

95°C 10.0 76.0 0.80 4.2 40.0 0.80 4.2 40.0 0.80

TC/3733 Mb/s 105°C 10.0 76.0 0.80 4.2 40.0 0.80 4.2 40.0 0.80

125°C 11.2 83.0 1.0 5.8 47.1 1.0 5.8 47.4 1.0

Unit mA
mA
mA

Note

Notes:

1. Published IDD values, except IDD4RQ, are the maximum IDD values considering the worstcase conditions of process, temperature, and voltage. Refer to the note below for IDD4RQ; refer to IDD6 Full-Array Self Refresh Current table for IDD6.
2. IDD4RQ value is typical, for reference only. DBI disabled, VOH = 0.5 × VDDQ, TC = 25°C. 3. Measurement conditions of IDD4R and IDD4W values: DBI disabled, BL = 16.

Table 45: LPDDR4X IDD Specifications under 4266 Mb/s ­ Single Die

VDD2 = 1.06­1.17V; VDDQ = 0.57­0.65V; VDD1 = 1.70­1.95V

Parameter
IDD01 IDD02 IDD0Q IDD2P1 IDD2P2 IDD2PQ IDD2PS1 IDD2PS2 IDD2PSQ IDD2N1 IDD2N2 IDD2NQ IDD2NS1 IDD2NS2 IDD2NSQ IDD3P1 IDD3P2 IDD3PQ

Supply
VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ

95°C 3.2 42.0 0.80 1.4 2.6 0.80 1.4 2.6 0.80 1.4 23.8 0.80 1.4 18.0 0.80 1.4 13.0 0.80

TC/4266 Mb/s 105°C 3.2 42.0 0.80 1.4 2.6 0.80 1.4 2.6 0.80 1.4 26.0 0.80 1.4 18.0 0.80 1.4 13.0 0.80

125°C 3.8 47.5 1.0 1.9 3.4 1.2 1.9 3.4 1.2 2.0 31.7 1.0 2.0 23.2 1.0 2.0 18.5 1.2

Unit mA

Note

mA

mA

mA

mA

mA

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

123

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4X IDD Parameters

Table 45: LPDDR4X IDD Specifications under 4266 Mb/s ­ Single Die (Continued)

VDD2 = 1.06­1.17V; VDDQ = 0.57­0.65V; VDD1 = 1.70­1.95V

Parameter
IDD3PS1 IDD3PS2 IDD3PSQ IDD3N1 IDD3N2 IDD3NQ IDD3NS1 IDD3NS2 IDD3NSQ IDD4R1 IDD4R2 IDD4RQ IDD4W1 IDD4W2 IDD4WQ IDD51 IDD52 IDD5Q IDD5AB1 IDD5AB2 IDD5ABQ IDD5PB1 IDD5PB2 IDD5PBQ

Supply
VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ5 VDD1 VDD2 VDDQ

95°C 1.4 13.0 0.80 1.7 28.3 0.80 1.7 21.4 0.80 2.2 366 101 2.2 296 0.80 10.5 80.0 0.80 4.2 45.0 0.80 4.2 45.0 0.80

TC/4266 Mb/s 105°C 1.4 13.0 0.80 1.7 29.0 0.80 1.7 22.0 0.80 2.2 375 101 2.2 305 0.80 10.5 80.0 0.80 4.2 45.0 0.80 4.2 45.0 0.80

125°C 2.0 18.5 1.2 2.2 36.2 1.0 2.2 27.5 1.0 2.7 389 103 2.7 319 0.90 11.8 87.4 1.0 5.8 53.0 1.0 5.8 53.4 1.0

Unit mA mA mA mA mA mA mA mA

Note
2, 3 3

Notes:

1. Published IDD values, except IDD4RQ, are the maximum IDD values considering the worstcase conditions of process, temperature, and voltage. Refer to the note below for IDD4RQ; refer to IDD6 Full-Array Self Refresh Current table for IDD6.
2. IDD4RQ value is typical, for reference only. DBI disabled, VOH = 0.5 × VDDQ, TC = 25°C. 3. Measurement conditions of IDD4R and IDD4W values: DBI disabled, BL = 16.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

124

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4X IDD Parameters

Table 46: LPDDR4X IDD6 Full-Array Self Refresh Current

VDD2 = 1.06­1.17V; VDDQ = 0.57­0.65V; VDD1 = 1.70­1.95V Self Refresh Current/3733 Mb/s and 4266 Mb/s

Temperature

Supply

Full-Array

1/2-Array

1/4-Array

1/8-Array

25°C 95°C 105°C

VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ

0.10 0.30 0.01 2.5 8.4 0.80 2.5 12.0 0.80

0.10 0.30 0.01 2.0 6.3 0.80 2.0 9.0 0.80

0.10 0.30 0.01 2.0 5.0 0.80 2.0 7.2 0.80

0.10 0.30 0.01 2.0 4.2 0.80 2.0 6.0 0.80

Unit mA

Notes:

1. IDD6 25°C is the typical, IDD6 95°C and IDD6 105°C are the maximum IDD value considering the worst-case conditions of process, temperature, and voltage.
2. When TC > 105°C, self refresh mode is not available.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

125

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Functional Description
Functional Description
The Mobile Low-Power DDR4 SDRAM (LPDDR4) is a high-speed CMOS, dynamic random-access memory internally configured with either 1 or 2 channels. Each channel is comprised of 16 DQs and 8 banks.
LPDDR4 uses a 2-tick, single-data-rate (SDR) protocol on the CA bus to reduce the number of input signals in the system. The term "2-tick" means that the command/ address is decoded across two transactions, such that half of the command/address is captured with each of two consecutive rising edges of CK. The 6-bit CA bus contains command, address, and bank information. Some commands such as READ, WRITE, MASKED WRITE, and ACTIVATE require two consecutive 2-tick SDR commands to complete the instruction.
LPDDR4 uses a double-data-rate (DDR) protocol on the DQ bus to achieve high-speed operation. The DDR interface transfers two data bits to each DQ lane in one clock cycle and is matched to a 16n-prefetch DRAM architecture. A write/read access consists of a single 16n-bit-wide data transfer to/from the DRAM core and 16 corresponding n-bitwide data transfers at the I/O pins.
Read and write accesses to the device are burst-oriented. Accesses start at a selected column address and continue for a programmed number of columns in a programmed sequence.
Accesses begin with the registration of an ACTIVATE command to open a row in the memory core, followed by a WRITE or READ command to access column data within the open row. The address and bank address (BA) bits registered by the ACTIVATE command are used to select the bank and row to be opened. The address and BA bits registered with the WRITE or READ command are used to select the bank and the starting column address for the burst access.
Prior to normal operation, the LPDDR4 SDRAM must be initialized. Following sections provide detailed information about device initialization, register definition, command descriptions and device operations.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

126

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Monolithic Device Addressing

Figure 78: Functional Block Diagram

VDDQ RZQ
ZQ
RESET CKE
CK_t, CK_c CS_n
CA[5:0] ODT_CA

RCVRS

Control logic

Command/Address Multiplex and Decode

CA ODT control

Mode registers

(1...n)
VSS RTT,nom SW

ZQ Cal

To CLK, CS, CA ODT calibration To DQS, DQ, DMI ODT calibration

DQ ODT control

Refresh counter
0­7

x
Rowaddress
MUX

Bank 7

Bank 7

Bank 6

Bank 6

Bank 5

Bank 5

Bank 4

Bank 4

Bank 3

Bank 3

Bank 2

Bank 2

Bank 1

Bank 1 Bank 0

Bank 0

rowaddress

Memory array

latch

and

decoder

Sense amplifier

COL[3:0]

16n

Read latch

16n MUX n DATA

DRVRS

DQS generator DQS_t,
DQS_c

0­7 Bank control logic

I/O gating DM mask logic

Column- y-4

address counter/

4

latch

Column decoder

16n

WRITE

FIFO

16n

and drivers

CK_t, CK_c

CK out CK in

n Mask
16n Data

COL[3:0]

n/16
Input registers
n

Read data path

(1...n)
VSS RTT,nom SW

RCVRS

Write data path

DQ[n-1:0] DQS_t, DQS_c

DMI

Monolithic Device Addressing
The table below includes all monolithic device addressing options defined by JEDEC. Under the SDRAM Addressing heading near the beginning of this data sheet are addressing details for this product data sheet.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

127

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

128

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

Table 47: Monolithic Device Addressing ­ Dual-Channel Die

Memory Density (Per Die) Memory density (per channel) Configuration
Number of channels (per die) Number of banks (per channel) Array prefetch (bits, per channel) Number of rows (per channel) Number of columns (fetch boundaries) Page size (bytes) Channel density (bits per channel) Total density (bits per die) Bank address ×16 Row add

4Gb 2Gb
16Mb × 16DQ × 8 banks
× 2 channels 2
8
256
16,384
64
2048 2,147,483,648
4,294,967,296
BA[2:0] R[13:0]

Col. add
Burst starting address boundary

C[9:0] 64 bit

6Gb 3Gb
24Mb × 16DQ × 8 banks
× 2 channels 2
8
256
24,576
64
2048 3,221,225,472
6,442,450,944
BA[2:0] R[14:0] (R13 = 0 when R14 = 1) C[9:0] 64 bit

8Gb 4Gb
32Mb × 16DQ × 8 banks
× 2 channels 2
8
256
32,768
64
2048 4,294,967,296
8,589,934,592
BA[2:0] R[14:0]
C[9:0] 64 bit

12Gb 6Gb

16Gb 8Gb

24Gb 12Gb

32Gb 16Gb

48Mb × 16DQ × 8 banks
× 2 channels
2

64Mb × 16DQ × 8 banks
× 2 channels
2

96Mb × 16DQ × 8 banks
× 2 channels
2

128Mb × 16DQ × 8 banks
× 2 channels
2

8

8

8

8

256

256

256

256

49,152

65,536

98,304

131,072

64

64

64

64

2048 6,442,450,944

2048 8,589,934,592

2048

2048

12,884,901,888 17,179,869,184

12,884,901,888 17,179,869,184 25,769,803,776 34,359,738,368

BA[2:0]
R[15:0] (R14 = 0 when
R15 = 1)
C[9:0]
64 bit

BA[2:0] R[15:0]
C[9:0] 64 bit

BA[2:0]
R[16:0] (R15 = 0 when
R16 = 1)
C[9:0]
64 bit

BA[2:0] R[16:0]
C[9:0] 64 bit

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Monolithic Device Addressing

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Monolithic Device Addressing

Table 48: Monolithic Device Addressing ­ Single-Channel Die

Memory Density (Per Die) Memory density (per channel) Configuration
Number of channels (per die) Number of banks (per channel) Array prefetch (bits, per channel) Number of rows (per channel) Number of columns (fetch boundaries) Page size (bytes) Channel density (bits per channel) Total density (bits per die) Bank address ×16 Row add

2Gb 2Gb
16Mb × 16 DQ × 8 banks 1
8
256
16,384
64
2048 2,147,483,648
2,147,483,648
BA[2:0] R[13:0]

Col. add
Burst starting address boundary

C[9:0] 64 bit

3Gb 3Gb
24Mb × 16 DQ × 8 banks 1
8
256
24,576
64
2048 3,221,225,472
3,221,225,472
BA[2:0] R[14:0] (R13 = 0 when R14 = 1) C[9:0] 64 bit

4Gb 4Gb
32Mb × 16 DQ × 8 banks 1
8
256
32,768
64
2048 4,294,967,296
4,294,967,296
BA[2:0] R[14:0]
C[9:0] 64 bit

6Gb 6Gb
48Mb × 16 DQ × 8 banks 1
8
256
49,152
64
2048 6,442,450,944
6,442,450,944
BA[2:0] R[15:0] (R14 = 0 when R15 = 1) C[9:0] 64 bit

8Gb 8Gb
64Mb × 16 DQ × 8 banks 1
8
256
65,536
64
2048 8,589,934,592
8,589,934,592
BA[2:0] R[15:0]
C[9:0] 64 bit

12Gb 12Gb

16Gb 16Gb

96Mb × 16 DQ × 8 banks
1

128Mb × 16 DQ × 8 banks
1

8

8

256

256

98,304

131,072

64

64

2048 12,884,901,888

2048 17,179,869,184

12,884,901,888 17,179,869,184

BA[2:0]
R[16:0] (R15 = 0 when
R16 = 1)
C[9:0]
64 bit

BA[2:0] R[16:0]
C[9:0] 64 bit

129

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Notes:

1. The lower two column addresses (C[1:0]) are assumed to be zero and are not transmitted on the CA bus.
2. Row and column address values on the CA bus that are not used for a particular density should be at valid logic levels.
3. For non-binary memory densities, only a quarter of the row address space is invalid. When the MSB address bit is HIGH, then the MSB - 1 address bit must be LOW.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Simplified Bus Interface State Diagram
Simplified Bus Interface State Diagram
The state diagram provides a simplified illustration of the bus interface, supported state transitions, and the commands that control them. For a complete description of device behavior, use the information provided in the state diagram with the truth tables and timing specifications. The truth tables describe device behavior and applicable restrictions when considering the actual state of all banks. For command descriptions, see the Commands and Timing section.

MRW MRR
CKEC=KEL = H

Figure 79: Simplified State Diagram

SR powerdown

Power-on =RLESET_n

MPCbased training

Command bus
training
MPC

MRW MRW

MR read

MRR

Self refresh

Automatic sequence Command sequence

MPCbased training

Reset

=RHESET_n MPC

MRW

SRE

SRX

Idle

MR write

MR write

REF

MPCbased training
MPC MRR

MR read

Per bank refresh

MRW

MR write

REF

MRW MRW

Command bus
training

All bank refresh

MPC MRR

MPCbased training

MR read

MRW CKE = L CKE = H

MR write

ACT

Idle powerdown

MR read

Activating

RDA CKEC=KEL = H

Active powerdown

MPCbased training
WR or MWR

WR or MWR

Write or mask write

MR write
MRW MRR

Bank

REF

active

RD

MR read

MRW

MR write

Per bank refresh
RD
Read

MPC MRR

MPCbased training

MR read

WRA or MWRA

WRA or MWRA
Write or mask write with auto precharge

PRE or PREA

PRE or PREA

PRE or PREA

Precharging

RDA
Read with auto precharge

PRE(A) = PRECHARGE (ALL) ACT = ACTIVATE WR(A) = WRITE (with auto precharge) MWR(A) = Mask WRITE
(with auto precharge) RD(A) = READ (with auto precharge) MRW = MODE REGISTER WRITE MRR = MODE REGISTER READ "CKE = L" = Enter power-down "CKE = H" = Exit power-down SRE = Enter self refresh SRX = Exit self refresh REF = REFRESH MPC = Mult-purpose command (with NOP)

Notes: 1. From the self refresh state, the device can enter power-down, MRR, MRW, or any of the training modes initiated with the MPC command. See the Self Refresh section.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

130

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Power-Up and Initialization

2. All banks are precharged in the idle state.
3. In the case of using an MRW command to enter a training mode, the state machine will not automatically return to the idle state at the conclusion of training. See the applicable training section for more information.
4. In the case of an MPC command to enter a training mode, the state machine may not automatically return to the idle state at the conclusion of training. See the applicable training section for more information.
5. This diagram is intended to provide an overview of the possible state transitions and commands to control them; however, it does not contain the details necessary to operate the device. In particular, situations involving more than one bank are not captured in complete detail.
6. States that have an "automatic return" and can be accessed from more than one prior state (that is, MRW from either idle or active states) will return to the state where they were initiated (that is, MRW from idle will return to idle).
7. The RESET pin can be asserted from any state and will cause the device to enter the reset state. The diagram shows RESET applied from the power-on and idle states as an example, but this should not be construed as a restriction on RESET.
8. MRW commands from the active state cannot change operating parameters of the device that affect timing. Mode register fields which may be changed via MRW from the active state include: MR1-OP[3:0], MR1-OP[7], MR3-OP[7:6], MR10-OP[7:0], MR11OP[7:0], MR13-OP[5], MR15-OP[7:0], MR16-OP[7:0], MR17-OP[7:0], MR20-OP[7:0], and MR22-OP[4:0].

Figure 80: Simplified State Diagram

a) FIFO-Based Write/Read Timing

Automatic sequence Command sequence

MPC

MPC

MPC

Write -FIFO

MPC

Read -FIFO

MPC

MPCbased

=

training

WRW

MPC

MRW

WRW

c) ZQCAL Start

b) Read DQ Calibration
MPC

MPC

DQ Calibration

d) ZQCAL Latch

MPC

ZQ Calibration
Start

MPC

ZQ Calibration
Latch

Power-Up and Initialization
To ensure proper functionality for power-up and reset initialization, default values for the MR settings are provided in the table below.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

131

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Power-Up and Initialization

Table 49: Mode Register Default Settings

Item FSP-OP/WR
WLS WL RL nWR DBI-WR/RD

Mode Register Setting MR13 OP[7:6] MR2 OP[6] MR2 OP[5:3] MR2 OP[2:0] MR1 OP[6:4] MR3 OP[7:6]

CA ODT DQ ODT VREF(CA) setting VREF(CA) value VREF(DQ) setting VREF(DQ) value

MR11 OP[6:4] MR11 OP[2:0] MR12 OP[6] MR12 OP[5:0] MR14 OP[6] MR14 OP[5:0]

Default Setting 00b 0b 000b 000b 000b 00b
000b 000b
1b 011101b
1b 011101b

Description FSP-OP/WR[0] are enabled WRITE latency set A is selected WL = 4 RL = 6, nRTP = 8 nWR = 6 Write and read DBI are disabled CA ODT is disabled DQ ODT is disabled VREF(CA) range[1] is enabled Range1: 50.3% of VDDQ VREF(DQ) range[1] enabled Range1: 50.3% of VDDQ

Voltage Ramp

The following sequence must be used to power up the device. Unless specified otherwise, this procedure is mandatory. The power-up sequence of all channels must proceed simultaneously.
1. While applying power (after Ta), RESET_n should be held LOW (0.2 × VDD2), and all other inputs must be between VIL,min and VIH,max. The device outputs remain at High-Z while RESET_n is held LOW. Power supply voltage ramp requirements are provided in the table below. VDD1 must ramp at the same time or earlier than VDD2. VDD2 must ramp at the same time or earlier than VDDQ.

Table 50: Voltage Ramp Conditions

After... Ta is reached

Applicable Conditions VDD1 must be greater than VDD2 VDD2 must be greater than VDDQ - 200mV

Notes:

1. Ta is the point when any power supply first reaches 300mV.
2. Voltage ramp conditions in above table apply between Ta and power-off (controlled or uncontrolled).
3. Tb is the point at which all supply and reference voltages are within their defined operating ranges.
4. Power ramp duration tINIT0 (Tb­Ta) must not exceed 20ms.
5. The voltage difference between any VSS and VSSQ must not exceed 100mV.

2. Following completion of the of the voltage ramp (Tb), RESET_n must be held LOW for tINIT1. DQ, DMI, DQS_t, and DQS_c voltage levels must be between VSSQ and VDDQ during voltage ramp to avoid latch-up. CK_t and CK_c, CS, and CA input levels must be between VSS and VDD2 during voltage ramp to avoid latch-up. Voltage ramp power supply requirements are provided in the table below.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

132

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Power-Up and Initialization
3. Beginning at Tb, RESET_n must remain LOW for at least tINIT1(Tc), after which RESET_n can be de-asserted to HIGH(Tc). At least 10ns before CKE de-assertion, CKE is required to be set LOW. All other input signals are "Don't Care."

Figure 81: Voltage Ramp and Initialization Sequence

Ta

Tb

Tc

Td

Te

Tf

Tg

Th

Ti

Power Ramp

Reset

Initialization

Training

CK_c CK_t

tINIT0=20ms(MAX)

tINIT1=200µs(MIN)

tINIT4=5tCK(MIN)

Supplies

Tj

Tk

RESET_n
CKE
CA[5:0] CS

tINIT2=10ns(MIN) tINIT3=2ms(MIN)

tINIT5=2µs(MIN)

tZQCAL=1µs(MIN) tZQLAT=MAX(30ns, 8tCK)(MIN)

Exit PD DES

MMRRWR

DES

ZSQtaCrat l

DES

ZLQatCchal

DES

TCrAainBiUnSg

DES

LeWveriltineg

DES

TraDinQing

DES

Valid

DQs

Valid

Valid

Valid

Don't Care
Note: 1. Training is optional and may be done at the system designer's discretion. The order of training may be different than what is shown here.
4. After RESET_n is de-asserted(Tc), wait at least tINIT3 before activating CKE. CK_t, CK_c must be started and stabilized for tINIT4 before CKE goes active(Td). CS must remain LOW when the controller activates CKE.
5. After CKE is set to HIGH, wait a minimum of tINIT5 to issue any MRR or MRW commands(Te). For MRR and MRW commands, the clock frequency must be within the range defined for tCKb. Some AC parameters (for example, tDQSCK) could have relaxed timings (such as tDQSCKb) before the system is appropriately configured.
6. After completing all MRW commands to set the pull-up, pull-down, and Rx termination values, the controller can issue the ZQCAL START command to the memory(Tf). This command is used to calibrate the VOH level and the output impedance over process, voltage, and temperature. In systems where more than one device share one external ZQ resistor, the controller must not overlap the ZQ calibration sequence of each device. The ZQ calibration sequence is completed after tZQCAL (Tg). The ZQCAL LATCH command must be issued to update the DQ drivers and DQ + CA ODT to the calibrated values.
7. After tZQLAT is satisfied (Th), the command bus (internal VREF(CA), CS, and CA) should be trained for high-speed operation by issuing an MRW command (command bus training mode). This command is used to calibrate the device's internal VREF and align CS/CA with CK for high-speed operation. The device will power-up with receivers configured for low-speed operations and with VREF(CA) set to a default factory setting. Normal device operation at clock speeds higher than tCKb may not be possible until command bus training is complete. The command bus training MRW command uses the CA bus as inputs for the calibration data stream, and it outputs the results asynchro-

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

133

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Power-Up and Initialization

nously on the DQ bus. See command bus training in the MRW section for information on how to enter/exit the training mode.
8. After command bus training, the controller must perform write leveling. Write leveling mode is enabled when MR2 OP[7] is HIGH(Ti). See the Write Leveling section for a detailed description of the write leveling entry and exit sequence. In write leveling mode, the controller adjusts write DQS timing to the point where the device recognizes the start of write DQ data burst with desired WRITE latency.
9. After write leveling, the DQ bus (internal VREF(DQ), DQS, and DQ) should be trained for high-speed operation using the MPC TRAINING commands and by issuing MRW commands to adjust VREF(DQ). The device will power-up with receivers configured for low-speed operations and with VREF(DQ) set to a default factory setting. Normal device operation at clock speeds higher than tCKb should not be attempted until DQ bus training is complete. The MPC[READ DQ CALIBRATION] command is used together with MPC[READ-FIFO] or MPC[WRITE-FIFO] commands to train the DQ bus without disturbing the memory array contents. See the DQ Bus Training section for more information on the DQ bus training sequence.
10. At Tk, the device is ready for normal operation and is ready to accept any valid command. Any mode registers that have not previously been configured for normal operation should be written at this time.

Table 51: Initialization Timing Parameters

Parameter tINIT0 tINIT1

Min ­
200

Max 20 ­

tINIT2 tINIT3 tINIT4 tINIT5 tCKb

10 2 5 2 Note 1, 2

­ ­ ­ ­ Note 1, 2

Unit ms µs
ns ms tCK s ns

Comment Maximum voltage ramp time Minimum RESET_n LOW time after completion of voltage ramp Minimum CKE LOW time before RESET_n goes HIGH Minimum CKE LOW time after RESET_n goes HIGH Minimum stable clock before first CKE HIGH Minimum idle time before first MRW/MRR command Clock cycle time during boot

Notes:

1. Minimum tCKb guaranteed by DRAM test is 18ns.
2. The system may boot at a higher frequency than dictated by minimum tCKb. The higher boot frequency is system dependent.

Reset Initialization with Stable Power
The following sequence is required for RESET at no power interruption initialization.
1. Assert RESET_n below 0.2 × VDD2 anytime when reset is needed. RESET_n needs to be maintained for minimum tPW_RESET. CKE must be pulled LOW at least 10ns before de-asserting RESET_n.
2. Repeat steps 4­10 in Voltage Ramp section.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

134

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Power-Off Sequence

Table 52: Reset Timing Parameter

Parameter tPW_RESET

Value

Min

Max

100

­

Unit ns

Comment
Minimum RESET_n LOW time for reset initialization with stable power

Power-Off Sequence
Controlled Power-Off
While powering off, CKE must be held LOW (0.2 × VDD2); all other inputs must be between VIL,min and VIH,max. The device outputs remain at High-Z while CKE is held LOW. DQ, DMI, DQS_t, and DQS_c voltage levels must be between VSSQ and VDDQ during the power-off sequence to avoid latch-up. CK_t, CK_c, CS, and CA input levels must be between VSS and VDD2 during the power-off sequence to avoid latch-up. Tx is the point where any power supply drops below the minimum value specified in the minimum DC Operating Condition.
Tz is the point where all power supplies are below 300mV. After Tz, the device is powered off.

Table 53: Power Supply Conditions

The voltage difference between VSS and VSSQ must not exceed 100mV

Between...

Applicable Conditions

Tx and Tz

VDD1 must be greater than VDD2 VDD2 must be greater than VDDQ - 200mV

Uncontrolled Power-Off
When an uncontrolled power-off occurs, the following conditions must be met.
· At Tx, when the power supply drops below the minimum values specified in the Recommended DC Operating Conditions table, all power supplies must be turned off and all power supply current capacity must be at zero, except for any static charge remaining in the system.
· After Tz (the point at which all power supplies first reach 300mV), the device must power off. During this period, the relative voltage between power supplies is uncontrolled. VDD1 and VDD2 must decrease with a slope lower than 0.5 V/µs between Tx and Tz.
An uncontrolled power-off sequence can occur a maximum of 400 times over the life of the device.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

135

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Mode Registers

Table 54: Power-Off Timing
Parameter Power-off ramp time

Symbol tPOFF

Min ­

Max 2

Unit sec

Mode Registers
Mode Register Assignments and Definitions
Mode register definitions are provided in the Mode Register Assignments table. In the access column of the table, R indicates read-only; W indicates write-only; R/W indicates read- or write-capable or enabled. The MRR command is used to read from a register. The MRW command is used to write to a register.

Table 55: Mode Register Assignments

Notes 1­5 apply to entire table MR# MA[5:0] Function

0

00h Device info

1

01h Device feature 1

2

02h Device feature 2

3

03h I/O config-1

4

04h Refresh and

training

5

05h Basic config-1

6

06h Basic config-2

7

07h Basic config-3

8

08h Basic config-4

9

09h Test mode

10

0Ah I/O calibration

11

0Bh ODT

12

0Ch VREF(CA)

13

0Dh Register control

14

0Eh VREF(DQ)

15

0Fh DQI-LB

16

10h PASR_Bank

17

11h PASR_Seg

18

12h IT-LSB

19

13h IT-MSB

20

14h DQI-UB

21

15h Vendor use

22

16h ODT feature 2

Access R
W W W R /W
R R R R W W W R/W W R/W W W W R R W W W

OP7
RD-PST WR Lev DBI-WR
TUF

OP6

OP5

OP4

OP3

OP2

OP1

OP0

RFU

RZQI

RFU Latency REF

mode

nWR (for AP)

RD-PRE WR-PRE

BL

WLS

WL

RL

DBI-RD

PDDS

PPRP WR-PST PU-CAL

Thermal offset PPRE SR abort

Refresh rate

Manufacturer ID

Revision ID1

Revision ID2

I/O width

Density

Type

Vendor-specific test mode

RFU

ZQ RST

RFU

CA ODT

RFU

DQ ODT

RFU

VRCA

VREF(CA)

FSP-OP FSP-WR DMD RRO VRCG VRO

RPT

CBT

RFU

VRDQ

VREF(DQ)

Lower-byte invert register for DQ calibration

PASR bank mask

PASR segment mask

DQS oscillator count ­ LSB

DQS oscillator count ­ MSB

Upper-byte invert register for DQ calibration

RFU

ODTD for x8_2ch ODTD -CA

ODTE -CS

ODTE -CK

SoC ODT

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

136

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Mode Registers

Table 55: Mode Register Assignments (Continued)

Notes 1­5 apply to entire table MR# MA[5:0] Function

23

17h DQS oscillator

stop

24

18h TRR control

25

19h PPR resources

26­29 1Ah~1D

­

h

30

1Eh

Reserved for

test

31

1Fh

­

32

20h DQ calibration

pattern A

33­38 21h26h Do not use

39

27h

Reserved for

test

40

28h DQ calibration

pattern B

41­47 29h2Fh Do not use

48­63 30h3Fh Reserved

Access W

OP7

R/W

TRR

mode

R

B7

­

W

­ W

­ W

W

­ ­

OP6

OP5

OP4

OP3

OP2

DQS oscillator run-time setting

OP1

OP0

TRR mode BAn

Unltd MAC

MAC value

B6

B5

B4

B3

B2

B1

B0

Reserved for future use

SDRAM will ignore

Reserved for future use See DQ calibration section

Do not use SDRAM will ignore

See DQ calibration section

Do not use Reserved for future use

Notes:

1. RFU bits must be set to 0 during MRW commands. 2. RFU bits are read as 0 during MRR commands. 3. All mode registers that are specified as RFU or write-only shall return undefined data
when read via an MRR command. 4. RFU mode registers must not be written. 5. Writes to read-only registers will not affect the functionality of the device.

Table 56: MR0 Device Feature 0 (MA[5:0] = 00h)

OP7

OP6 RFU

OP5

OP4

OP3

RZQI

OP2 RFU

OP1 Latency mode

OP0 REF

Table 57: MR0 Op-Code Bit Definitions

Register Information Refresh mode

Type Read-only

OP OP[0]

Latency mode

Read-only OP[1]

Definition
0b: Both legacy and modified refresh mode supported 1b: Only modified refresh mode supported
0b: Device supports normal latency 1b: Device supports byte mode latency

Notes 5, 6

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

137

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Mode Registers

Table 57: MR0 Op-Code Bit Definitions (Continued)

Register Information
Built-in self-test for RZQ information

Type Read-only

OP OP[4:3]

Definition
00b: RZQ self-test not supported
01b: ZQ may connect to VSSQ or float 10b: ZQ may short to VDDQ 11b: ZQ pin self-test completed, no error condition detected (ZQ may not connect to VSSQ, float, or short to VDDQ)

Notes 1­4

Notes:

1. RZQI MR value, if supported, will be valid after the following sequence:
· Completion of MPC[ZQCAL START] command to either channel · Completion of MPC[ZQCAL LATCH] command to either channel then tZQLAT is satis-
fied RZQI value will be lost after reset.
2. If ZQ is connected to VSSQ to set default calibration, OP[4:3] must be set to 01b. If ZQ is not connected to VSSQ, either OP[4:3] = 01b or OP[4:3] = 10b might indicate a ZQ pin assembly error. It is recommended that the assembly error be corrected.
3. In the case of possible assembly error, the device will default to factory trim settings for RON, and will ignore ZQ CALIBRATION commands. In either case, the device may not function as intended.
4. If the ZQ pin self-test returns OP[4:3] = 11b, the device has detected a resistor connected to the ZQ pin. However, this result cannot be used to validate the ZQ resistor value or that the ZQ resistor meets the specified limits (that is, 240 ±1%).
5. See byte mode addendum spec for byte mode latency details.
6. Byte mode latency for 2Ch. x16 device is only allowed when it is stacked in a same package with byte mode device.

Table 58: MR1 Device Feature 1 (MA[5:0] = 01h)

OP7 RD-PST

OP6

OP5 nWR (for AP)

OP4

OP3 RD-PRE

OP2 WR-PRE

OP1

OP0

BL

Table 59: MR1 Op-Code Bit Definitions

Feature BL Burst length
WR-PRE Write preamble length RD-PRE Read preamble type

Type Write-only
Write-only Write-only

OP OP[1:0]
OP[2] OP[3]

Definition 00b: BL = 16 sequential (default) 01b: BL = 32 sequential 10b: BL = 16 or 32 sequential (on-the-fly) 11b: Reserved 0b: Reserved 1b: WR preamble = 2 × tCK 0b: RD preamble = Static (default) 1b: RD preamble = Toggle

Notes 1
5, 6 3, 5, 6

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

138

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Mode Registers

Table 59: MR1 Op-Code Bit Definitions (Continued)

Feature nWR Write-recovery for AUTO PRECHARGE command
RD-PST Read postamble length

Type Write-only
Write-only

OP OP[6:4]
OP[7]

Definition 000b: nWR = 6 (default) 001b: nWR = 10 010b: nWR = 16 011b: nWR = 20 100b: nWR = 24 101b: nWR = 30 110b: nWR = 34 111b: nWR = 40 0b: RD postamble = 0.5 × tCK (default) 1b: RD postamble = 1.5 × tCK

Notes 2, 5, 6
4, 5, 6

Notes:

1. Burst length on-the-fly can be set to either BL = 16 or BL = 32 by setting the BL bit in the command operands. See the Command Truth Table.
2. The programmed value of nWR is the number of clock cycles the device uses to determine the starting point of an internal precharge after a write burst with auto precharge (AP) enabled. See Frequency Ranges for RL, WL, and nWR Settings table.
3. For READ operations, this bit must be set to select between a toggling preamble and a non-toggling preamble (see the Preamble section).
4. OP[7] provides an optional read postamble with an additional rising and falling edge of DQS_t. The optional postamble cycle is provided for the benefit of certain memory controllers.
5. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address.
6. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. The device will operate only according to the values stored in the registers for the active set point, that is, the set point determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device and may be changed without affecting device operation.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

139

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

Table 60: Burst Sequence for Read
C4 C3 C2 C1 C0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 16-Bit READ Operation V 0 0 0 0 0 1 2 34 5 6 7 8 9ABCDE F V 0 1 0 0 4 5 6 78 9ABCDE F 0 1 2 3 V 1 0 0 0 8 9ABCDE F 0 1 2 34 5 6 7 V 1 1 0 0 CDE F01 234 5 6789AB 32-Bit READ Operation 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 0 0 1 0 0 4 5 6 7 8 9 A B C D E F 0 1 2 3 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 10 11 12 13 0 1 0 0 0 8 9 A B C D E F 0 1 2 3 4 5 6 7 18 19 1A 1B 1C 1D 1E 1F 10 11 12 13 14 15 16 17 0 1 1 0 0 C D E F 0 1 2 3 4 5 6 7 8 9 A B 1C 1D 1E 1F 10 11 12 13 14 15 16 17 18 19 1A 1B 1 0 0 0 0 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 0 1 2 3 4 5 6 7 8 9 A B C D E F 1 0 1 0 0 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 10 11 12 13 4 5 6 7 8 9 A B C D E F 0 1 2 3 1 1 0 0 0 18 19 1A 1B 1C 1D 1E 1F 10 11 12 13 14 15 16 17 8 9 A B C D E F 0 1 2 3 4 5 6 7 1 1 1 0 0 1C 1D 1E 1F 10 11 12 13 14 15 16 17 18 19 1A 1B C D E F 0 1 2 3 4 5 6 7 8 9 A B

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Mode Registers

140

Notes: 1. C[1:0] are not present on the CA bus; they are implied to be zero. 2. The starting burst address is on 64-bit (4n) boundaries.

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Table 61: Burst Sequence for Write
C4 C3 C2 C1 C0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 16-Bit WRITE Operation V 0 0 0 0 0 1 2 34 5 6 7 8 9ABCDE F 32-Bit WRITE Operation 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F

Notes:

1. C[1:0] are not present on the CA bus; they are implied to be zero. 2. The starting burst address is on 256-bit (16n) boundaries for burst length 16. 3. The starting burst address is on 512-bit (32n) boundaries for burst length 32. 4. C[3:2] must be set to 0 for all WRITE operations.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Mode Registers

Table 62: MR2 Device Feature 2 (MA[5:0] = 02h)

OP7 WR Lev

OP6 WLS

OP5

OP4 WL

OP3

OP2

OP1 RL

OP0

Table 63: MR2 Op-Code Bit Definitions

Feature
RL READ latency

Type Write-only

OP OP[2:0]

Definition RL and nRTP for DBI-RD disabled (MR3 OP[6] = 0b) 000b: RL = 6, nRTP = 8 (default) 001b: RL = 10, nRTP = 8 010b: RL = 14, nRTP = 8 011b: RL = 20, nRTP = 8 100b: RL = 24, nRTP = 10 101b: RL = 28, nRTP = 12 110b: RL = 32, nRTP = 14 111b: RL = 36, nRTP = 16
RL and nRTP for DBI-RD enabled (MR3 OP[6] = 1b) 000b: RL = 6, nRTP = 8 001b: RL = 12,nRTP = 8 010b: RL = 16, nRTP = 8 011b: RL = 22, nRTP = 8 100b: RL = 28, nRTP = 10 101b: RL = 32, nRTP = 12 110b: RL = 36, nRTP = 14 111b: RL = 40, nRTP = 16

Notes 1, 3, 4

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

141

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Mode Registers

Table 63: MR2 Op-Code Bit Definitions (Continued)

Feature WL WRITE latency
WLS WRITE latency set WR Lev Write leveling

Type Writeonly
Writeonly Writeonly

OP OP[5:3]
OP[6] OP[7]

Definition WL set A (MR2 OP[6] = 0b) 000b: WL = 4 (default) 001b: WL = 6 010b: WL = 8 011b: WL = 10 100b: WL = 12 101b: WL = 14 110b: WL = 16 111b: WL = 18
WL set B (MR2 OP[6] = 1b) 000b: WL = 4 001b: WL = 8 010b: WL = 12 011b: WL = 18 100b: WL = 22 101b: WL = 26 110b: WL = 30 111b: WL = 34 0b: Use WL set A (default) 1b: Use WL set B 0b: Disable write leveling (default) 1b: Enable write leveling

Notes 1, 3, 4
1, 3, 4 2

Notes:

1. See Latency Code Frequency Table for allowable frequency ranges for RL/WL/nWR.
2. After an MRW command to set the write leveling enable bit (OP[7] = 1b), the device remains in the MRW state until another MRW command clears the bit (OP[7] = 0b). No other commands are allowed until the write leveling enable bit is cleared.
3. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command this MR address, or read from with an MRR command to this address.
4. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. The device will operate only according to the values stored in the registers for the active set point, that is, the set point determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device and may be changed without affecting device operation.
5. nRTP is valid for BL16 only. For BL32, the SDRAM will add 8 clocks to the nRTP value before starting a precharge.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

142

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Mode Registers

Table 64: Frequency Ranges for RL, WL, nWR, and nRTP Settings

READ Latency

No DBI 6 10 14 20 24 28 32 36

w/DBI 6 12 16 22 28 32 36 40

WRITE Latency

Set A 4 6 8 10 12 14 16 18

Set B 4 8 12 18 22 26 30 34

nWR 6 10 16 20 24 30 34 40

nRTP 8 8 8 8 10 12 14 16

Lower Frequency Limit (>)
10 266 533 800 1066 1333 1600 1866

Upper Frequency
Limit() 266 533 800 1066 1333 1600 1866 2133

Units MHz

Notes 1­6

Notes:

1. The device should not be operated at a frequency above the upper frequency limit or below the lower frequency limit shown for each RL, WL, or nWR value.
2. DBI for READ operations is enabled in MR3 OP[6]. When MR3 OP[6] = 0, then the "No DBI" column should be used for READ latency. When MR3 OP[6] = 1, then the "w/DBI" column should be used for READ latency.
3. WRITE latency set A and set B are determined by MR2 OP[6]. When MR2 OP[6] = 0, then WRITE latency set A should be used. When MR2 OP[6] = 1, then WRITE latency set B should be used.
4. The programmed value for nRTP is the number of clock cycles the device uses to determine the starting point of an internal PRECHARGE operation after a READ burst with AP (auto precharge) enabled . It is determined by RU(tRTP/tCK).
5. The programmed value of nWR is the number of clock cycles the device uses to determine the starting point of an internal PRECHARGE operation after a WRITE burst with AP (auto precharge) enabled. It is determined by RU(tWR/tCK).
6. nRTP shown in this table is valid for BL16 only. For BL32, the device will add 8 clocks to the nRTP value before starting a precharge.

Table 65: MR3 I/O Configuration 1 (MA[5:0] = 03h)

OP7 DBI-WR

OP6 DBI-RD

OP5

OP4 PDDS

OP3

OP2 PPRP

OP1 WR-PST

OP0 PU-CAL

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

143

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Mode Registers

Table 66: MR3 Op-Code Bit Definitions

Feature PU-CAL (Pull-up calibration point) WR-PST (WR postamble length) PPRP (Post-package repair protection) PDDS (Pull-down drive strength)
DBI-RD (DBI-read enable) DBI-WR (DBI-write enable)

Type Write-only

OP OP[0] OP[1] OP[2] OP[5:3]
OP[6] OP[7]

Definition 0b: VDDQ × 0.6 1b: VDDQ × 0.5 (default) 0b: WR postamble = 0.5 × tCK (default) 1b: WR postamble = 1.5 × tCK 0b: PPR protection disabled (default) 1b: PPR protection enabled
000b: RFU 001b: RZQ/1 010b: RZQ/2 011b: RZQ/3 100b: RZQ/4 101b: RZQ/5 110b: RZQ/6 (default) 111b: Reserved 0b: Disabled (default) 1b: Enabled 0b: Disabled (default) 1b: Enabled

Notes 1­4
2, 3, 5 6
1, 2, 3
2, 3 2, 3

Notes:

1. All values are typical. The actual value after calibration will be within the specified tolerance for a given voltage and temperature. Recalibration may be required as voltage and temperature vary.
2. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address.
3. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1.The device will operate only according to the values stored in the registers for the active set point, for example, the set point determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation.
4. For dual-channel device, PU-CAL (MR3-OP[0]) must be set the same for both channels on a die. The SDRAM will read the value of only one register (Ch.A or Ch.B); the choice is vendor-specific, so both channels must be set the same.
5. 1.5 × tCK apply > 1.6 GHz clock.
6. If MR3 OP[2] is set to 1b, PPR protection mode is enabled. The PPR protection bit is a sticky bit and can only be set to 0b by a power on reset. MR4 OP[4] controls entry to PPR mode. If PPR protection is enabled then the DRAM will not allow writing of 1b to MR4 OP[4].

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

144

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Mode Registers

Table 67: MR4 Device Temperature (MA[5:0] = 04h)

OP7 TUF

OP6

OP5

Thermal offset

OP4 PPRE

OP3 SR abort

OP2

OP1 Refresh rate

OP0

Table 68: MR4 Op-Code Bit Definitions

Feature Refresh rate
SR abort (Self refresh abort) PPRE (Post-package repair entry/ exit) Thermal offset-controller offset to TCSR
TUF (Temperature update flag)

Type Read-only
Write Write Write Read-only

OP OP[2:0]
OP[3] OP[4] OP[6:5] OP7

Definition 000b: SDRAM low temperature operating limit exceeded 001b: 4x refresh 010b: 2x refresh 011b: 1x refresh (default) 100b: 0.5x refresh 101b: 0.25x refresh, no derating 110b: 0.25x refresh, with derating 111b: SDRAM high temperature operating limit exceeded 0b: Disable (default) 1b: Device dependent 0b: Exit PPR mode (default) 1b: Enter PPR mode (Reference MR25 OP[7:0] for available PPR resources) 00b: No offset, 0~5°C gradient (default) 01b: 5°C offset, 5~10°C gradient 10b: 10°C offset, 10~15°C gradient 11b: Reserved 0b: OP[2:0] No change in OP[2:0] since last MR4 read (default) 1b: Change in OP[2:0] since last MR4 read

Notes 1­4, 7­9
9 5, 9
9
6­8

Notes:

1. The refresh rate for each MR4 OP[2:0] setting applies to tREFI, tREFIpb, and tREFW. MR4 OP[2:0] = 011b corresponds to a device temperature of 85°C. Other values require either a longer (2x, 4x) refresh interval at lower temperatures or a shorter (0.5x, 0.25x) refresh interval at higher temperatures. If MR4 OP[2] = 1b, the device temperature is greater than 85°C.
2. At higher temperatures (>85°C), AC timing derating may be required. If derating is required the device will set MR4 OP[2:0] = 110b. See derating timing requirements in the AC Timing section.
3. DRAM vendors may or may not report all of the possible settings over the operating temperature range of the device. Each vendor guarantees that their device will work at any temperature within the range using the refresh interval requested by their device.
4. The device may not operate properly when MR4 OP[2:0 ] = 000b or 111b.
5. Post-package repair can be entered or exited by writing to MR4 OP[4].
6. When MR4 OP[7] = 1b, the refresh rate reported in MR4 OP[2:0] has changed since the last MR4 read. A mode register read from MR4 will reset MR4 OP[7] to 0b.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

145

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Mode Registers

7. MR4 OP[7] = 0b at power-up. MR4 OP[2:0] bits are valid after initialization sequence (Te).
8. See the Temperature Sensor section for information on the recommended frequency of reading MR4.
9. MR4 OP[6:3] can be written in this register. All other bits will be ignored by the device during an MRW command to this register.

Table 69: MR5 Basic Configuration 1 (MA[5:0] = 05h)

OP7

OP6

OP5

OP4

OP3

Manufacturer ID

OP2

OP1

OP0

Table 70: MR5 Op-Code Bit Definitions

Feature Manufacturer ID

Type Read-only

OP OP[7:0]

Definition 1111 1111b : Micron All others: Reserved

Table 71: MR6 Basic Configuration 2 (MA[5:0] = 06h)

OP7

OP6

OP5

OP4

OP3

Revision ID1

OP2

OP1

OP0

Note: 1. MR6 is vendor-specific.

Table 72: MR6 Op-Code Bit Definitions

Feature Revision ID1

Type

OP Definition

Read-only OP[7:0] xxxx xxxxb: Revision ID1

Note: 1. MR6 is vendor-specific.

Table 73: MR7 Basic Configuration 3 (MA[5:0] = 07h)

OP7

OP6

OP5

OP4

OP3

Revision ID2

OP2

OP1

OP0

Table 74: MR7 Op-Code Bit Definitions

Feature Revision ID2

Type

OP Definition

Read-only OP[7:0] xxxx xxxxb: Revision ID2

Note: 1. MR7 is vendor-specific.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

146

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Mode Registers

Table 75: MR8 Basic Configuration 4 (MA[5:0] = 08h)

OP7

OP6

I/O width

OP5

OP4

OP3

Density

OP2

OP1

OP0

Type

Table 76: MR8 Op-Code Bit Definitions

Feature Type Density
I/O width

Type Read-only Read-only
Read-only

OP OP[1:0] OP[5:2]
OP[7:6]

Definition 00b: S16 SDRAM (16n prefetch) All others: Reserved 0000b: 4Gb dual-channel die/2Gb single-channel die 0001b: 6Gb dual-channel die/3Gb single-channel die 0010b: 8Gb dual-channel die/4Gb single-channel die 0011b: 12Gb dual-channel die/6Gb single-channel die 0100b: 16Gb dual-channel die/8Gb single-channel die 0101b: 24Gb dual-channel die/12Gb single-channel die 0110b: 32Gb dual-channel die/16Gb single-channel die 1100b: 2Gb dual-channel die/1Gb single-channel die All others: Reserved 00b: x16/channel 01b: x8/channel All others: Reserved

Table 77: MR9 Test Mode (MA[5:0] = 09h)

OP7

OP6

OP5

OP4

OP3

Vendor-specific test mode

OP2

OP1

OP0

Table 78: MR9 Op-Code Definitions

Feature Test mode

Type

OP Definition

Write-only OP[7:0] 0000000b; Vendor-specific test mode disabled (default)

Table 79: MR10 Calibration (MA[5:0] = 0Ah)

OP7

OP6

OP5

OP4 RFU

OP3

OP2

OP1

OP0 ZQ RESET

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

147

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Mode Registers

Table 80: MR10 Op-Code Bit Definitions

Feature ZQ reset

Type Write-only

OP OP[0]

Definition 0b: Normal operation (default) 1b: ZQ reset

Notes:

1. See AC Timing table for calibration latency and timing.
2. If ZQ is connected to VDDQ through RZQ, either the ZQ CALIBRATION function or default calibration (via ZQ reset) is supported. If ZQ is connected to VSS, the device operates with default calibration and ZQ CALIBRATION commands are ignored. In both cases, the ZQ connection must not change after power is supplied to the device.

Table 81: MR11 ODT Control (MA[5:0] = 0Bh)

OP7 RFU

OP6

OP5 CA ODT

OP4

OP3 RFU

OP2

OP1 DQ ODT

OP0

Table 82: MR11 Op-Code Bit Definitions

Feature DQ ODT DQ bus receiver on-die termination
CA ODT CA bus receiver on-die termination

Type Write-only
Write-only

OP OP[2:0]
OP[6:4]

Definition 000b: Disable (default) 001b: RZQ/1 010b: RZQ/2 011b: RZQ/3 100b: RZQ/4 101b: RZQ/5 110b: RZQ/6 111b: RFU 000b: Disable (default) 001b: RZQ/1 010b: RZQ/2 011b: RZQ/3 100b: RZQ/4 101b: RZQ/5 110b: RZQ/6 111b: RFU

Notes 1, 2, 3
1, 2, 3

Notes:

1. All values are typical. The actual value after calibration will be within the specified tolerance for a given voltage and temperature. Re-calibration may be required as voltage and temperature vary.
2. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address.
3. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. The device will operate only according to the values stored

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

148

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Mode Registers

in the registers for the active set point, for example, the set point determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device and may be changed without affecting device operation.

Table 83: MR12 Register Information (MA[5:0] = 0Ch)

OP7 RFU

OP6 VRCA

OP5

OP4

OP3

OP2

VREF(CA)

OP1

OP0

Table 84: MR12 Op-Code Bit Definitions

Feature
VREF(CA) VREF(CA) settings
VRCA VREF(CA) range

Type
Read/ Write
Read/ Write

OP OP[5:0]
OP[6]

Data
000000b­110010b: See VREF Settings table All others: Reserved
0b: VREF(CA) range[0] enabled 1b: VREF(CA) range[1] enabled (default)

Notes 1­3, 5, 6
1, 2, 4, 5, 6

Notes:

1. This register controls the VREF(CA) levels for frequency set point[1:0]. Values from either VR(ca)[0] or VR(ca)[1] may be selected by setting MR12 OP[6] appropriately.
2. A read to MR12 places the contents of OP[7:0] on DQ[7:0]. Any RFU bits and unused DQ will be set to 0. See the MRR Operation section.
3. A write to MR12 OP[5:0] sets the internal VREF(CA) level for FSP[0] when MR13 OP[6] = 0b or sets the internal VREF(CA) level for FSP[1] when MR13 OP[6] = 1b. The time required for VREF(CA) to reach the set level depends on the step size from the current level to the new level. See the VREF(CA) training section.
4. A write to MR12 OP[6] switches the device between two internal VREF(CA) ranges. The range (range[0] or range[1]) must be selected when setting the VREF(CA) register. The value, once set, will be retained until overwritten or until the next power-on or reset event.
5. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address.
6. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. The device will operate only according to the values stored in the registers for the active set point, for example, the set point determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation.

Table 85: MR13 Register Control (MA[5:0] = 0Dh)

OP[7] FSP-OP

OP[6] FSP-WR

OP[5] DMD

OP[4] RRO

OP[3] VRCG

OP[2] VRO

OP[1] RPT

OP[0] CBT

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

149

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Mode Registers

Table 86: MR13 Op-Code Bit Definition

Feature
CBT Command bus training

Type Write-only

RPT Read preamble training

VRO VREF output
VRCG VREF current generator
RRO Refresh rate option

DMD Data mask disable

FSP-WR Frequency set point write/ read
FSP-OP FREQUENCY SET POINT operation mode

OP OP[0] OP[1] OP[2] OP[3] OP[4] OP[5] OP[6]
OP[7]

Definition 0b: Normal operation (default) 1b: Command bus training mode enabled 0b: Disabled (default) 1b: Read preamble training mode enabled 0b: Normal operation (default) 1b: Output the VREF(CA) and VREF(DQ) values on DQ bits 0b: Normal operation (default) 1b: Fast response (high current) mode 0b: Disable codes 001 and 010 in MR4 OP[2:0] 1b: Enable all codes in MR4 OP[2:0] 0b: DATA MASK operation enabled (default) 1b: DATA MASK operation disabled 0b: Frequency set point[0] (default) 1b: Frequency set point[1]
0b: Frequency set point[0] (default) 1b: Frequency set point[1]

Notes 1
2 3 4, 5 6 7
8

Notes:

1. A write to set OP[0] = 1 causes the LPDDR4 SDRAM to enter the command bus training mode. When OP[0] = 1 and CKE goes LOW, commands are ignored and the contents of CA[5:0] are mapped to the DQ bus. CKE must be brought HIGH before doing a MRW to clear this bit (OP[0] = 0) and return to normal operation. See the Command Bus Training section for more information.
2. When set, the device will output the VREF(CA) and VREF(DQ) voltage on DQ pins. Only the "active" frequency set point, as defined by MR13 OP[7], will be output on the DQ pins. This function allows an external test system to measure the internal VREF levels. The DQ pins used for VREF output are vendor-specific.
3. When OP[3] = 1, the VREF circuit uses a high current mode to improve VREF settling time. 4. MR13 OP[4] RRO bit is valid only when MR0 OP[0] = 1. For LPDDR4 SDRAM with MR0
OP[0] = 0, MR4 OP[2:0] bits are not dependent on MR13 OP[4].
5. When OP[4] = 0, only 001b and 010b in MR4 OP[2:0] are disabled. LPDDR4 SDRAM must report 011b instead of 001b or 010b in this case. Controller should follow the refresh mode reported by MR4 OP[2:0], regardless of RRO setting. TCSR function does not depend on RRO setting.
6. When enabled (OP[5] = 0b) data masking is enabled for the device. When disabled (OP[5] = 1b), the device will ignore any mask patterns issued during a MASKED WRITE command. See the Data Mask section for more information.
7. FSP-WR determines which frequency set point registers are accessed with MRW and MRR commands for the following functions such as VREF(CA) setting, VREF(CA) range, VREF(DQ) setting, VREF(DQ) range. For more information, refer to Frequency Set Point section.
8. FSP-OP determines which frequency set point register values are currently used to specify device operation for the following functions such as VREF(CA) setting, VREF(CA) range, VREF(DQ) setting, VREF(DQ) range. For more information, refer to Frequency Set Point section.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

150

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Mode Registers

Table 87: Mode Register 14 (MA[5:0] = 0Eh)

OP[7] RFU

OP[6] VRDQ

OP[5]

OP[4]

OP[3]

OP[2]

VREF(DQ)

OP[1]

OP[0]

Table 88: MR14 Op-Code Bit Definition

Feature
VREF(DQ) VREF(DQ) setting
VRDQ VREF(DQ) range

Type
Read/ Write

OP OP[5:0]
OP[6]

Definition
000000b­110010b: See VREF Settings table All others: Reserved
0b: VREF(DQ) range[0] enabled 1b: VREF(DQ) range[1] enabled (default)

Notes 1­3, 5, 6
1, 2, 4­6

Notes:

1. This register controls the VREF(DQ) levels for frequency set point[1:0]. Values from either VRDQ[0] (vendor defined) or VRDQ[1] (vendor defined) may be selected by setting OP[6] appropriately.
2. A read (MRR) to this register places the contents of OP[7:0] on DQ[7:0]. Any RFU bits and unused DQ shall be set to 0. See the MRR Operation section.
3. A write to OP[5:0] sets the internal VREF(DQ) level for FSP[0] when MR13 OP[6] = 0b, or sets FSP[1] when MR13 OP[6] = 1b. The time required for VREF(DQ) to reach the set level depends on the step size from the current level to the new level. See the VREF(DQ) training section.
4. A write to OP[6] switches the device between two internal VREF(DQ) ranges. The range (range[0] or range[1]) must be selected when setting the VREF(DQ) register. The value, once set, will be retained until overwritten, or until the next power-on or reset event.
5. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address.
6. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. The device will operate only according to the values stored in the registers for the active set point, for example, the set point determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

151

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Mode Registers

Table 89: VREF Setting for Range[0] and Range[1]

Notes 1-3 apply to entire table

Range[0] Values

Function
VREF setting for MR12 and MR14

OP OP[5:0]

VREF(CA) (% of VDDQ) VREF(DQ) (% of VDDQ) 000000b: 15.0% 000001b: 15.6% 000010b: 16.2%

011010b: 30.5% 011011b: 31.1% 011100b: 31.7%

000011b: 16.8%

011101b: 32.3%

000100b: 17.4%

011110b: 32.9%

000101b: 18.0%

011111b: 33.5%

000110b: 18.6%

100000b: 34.1%

000111b: 19.2%

100001b: 34.7%

001000b: 19.8%

100010b: 35.3%

001001b: 20.4%

100011b: 35.9%

001010b: 21.0%

100100b: 36.5%

001011b: 21.6%

100101b: 37.1%

001100b: 22.2%

100110b: 37.7%

001101b: 22.8%

100111b: 38.3%

001110b: 23.4%

101000b: 38.9%

001111b: 24.0%

101001b: 39.5%

010000b: 24.6%

101010b: 40.1%

010001b: 25.1%

101011b: 40.7%

010010b: 25.7%

101100b: 41.3%

010011b: 26.3%

101101b: 41.9%

010100b: 26.9%

101110b: 42.5%

010101b: 27.5%

101111b: 43.1%

010110b: 28.1%

110000b: 43.7%

010111b: 28.7%

110001b: 44.3%

011000b: 29.3%

110010b: 44.9%

011001b: 29.9%

All others: Reserved

Range[1] Values

VREF(CA) (% of VDDQ) VREF(DQ) (% of VDDQ) 000000b: 32.9%

011010b: 48.5%

000001b: 33.5%

011011b: 49.1%

000010b: 34.1%

011100b: 49.7%

000011b: 34.7%

011101b: 50.3% (default)

000100b: 35.3%

011110b: 50.9%

000101b: 35.9%

011111b: 51.5%

000110b: 36.5%

100000b: 52.1%

000111b: 37.1%

100001b: 52.7%

001000b: 37.7%

100010b: 53.3%

001001b: 38.3%

100011b: 53.9%

001010b: 38.9%

100100b: 54.5%

001011b: 39.5%

100101b: 55.1%

001100b: 40.1%

100110b: 55.7%

001101b: 40.7%

100111b: 56.3%

001110b: 41.3%

101000b: 56.9%

001111b: 41.9%

101001b: 57.5%

010000b: 42.5%

101010b: 58.1%

010001b: 43.1%

101011b: 58.7%

010010b: 43.7%

101100b: 59.3%

010011b: 44.3%

101101b: 59.9%

010100b: 44.9%

101110b: 60.5%

010101b: 45.5%

101111b: 61.1%

010110b: 46.1%

110000b: 61.7%

010111b: 46.7%

110001b: 62.3%

011000b: 47.3%

110010b: 62.9%

011001b: 47.9%

All others: Reserved

Notes:

1. These values may be used for MR14 OP[5:0] and MR12 OP[5:0] to set the VREF(CA) or VREF(DQ) levels in the device.
2. The range may be selected in each of the MR14 or MR12 registers by setting OP[6] appropriately.
3. Each of the MR14 or MR12 registers represents either FSP[0] or FSP[1]. Two frequency set points each for CA and DQ are provided to allow for faster switching between terminated and unterminated operation or between different high-frequency settings, which may use different terminations values.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

152

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Mode Registers

Table 90: MR15 Register Information (MA[5:0] = 0Fh)

OP[7]

OP[6]

OP[5]

OP[4]

OP[3]

OP[2]

Lower-byte invert register for DQ calibration

OP[1]

OP[0]

Table 91: MR15 Op-code Bit Definition

Feature
Lower-byte invert for DQ calibration

Type Write-only

OP OP[7:0]

Definition
The following values may be written for any operand OP[7:0] and will be applied to the corresponding DQ locations DQ[7:0] within a byte lane 0b: Do not invert 1b: Invert the DQ calibration patterns in MR32 and MR40 Default value for OP[7:0] = 55h

Notes 1­3

Notes:

1. This register will invert the DQ calibration pattern found in MR32 and MR40 for any single DQ or any combination of DQ. Example: If MR15 OP[7:0] = 00010101b, then the DQ calibration patterns transmitted on DQ[7, 6, 5, 3, 1] will not be inverted, but the DQ calibration patterns transmitted on DQ[4, 2, 0] will be inverted.
2. DM[0] is not inverted and always transmits the "true" data contained in MR32 and MR40.
3. No DATA BUS INVERSION (DBI) function is enacted during read DQ calibration, even if DBI is enabled in MR3-OP[6].

Table 92: MR15 Invert Register Pin Mapping

PIN MR15

DQ0 OP0

DQ1 OP1

DQ2 OP2

DQ3 OP3

DMIO No invert

DQ4 OP4

DQ5 OP5

DQ6 OP6

DQ7 OP7

Table 93: MR16 PASR Bank Mask (MA[5:0] = 010h)

OP7

OP6

OP5

OP4

OP3

PASR bank mask

OP2

OP1

OP0

Table 94: MR16 Op-Code Bit Definitions

Feature Bank[7:0] mask

Type Write-only

OP OP[7:0]

Definition 0b: Bank refresh enabled (default) 1b: Bank refresh disabled

OP[n] 0 1 2

Bank Mask xxxxxxx1 xxxxxx1x xxxxx1xx

8-Bank SDRAM Bank 0 Bank 1 Bank 2

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

153

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Mode Registers

OP[n] 3 4 5 6 7

Bank Mask xxxx1xxx xxx1xxxx xx1xxxxx x1xxxxxx 1xxxxxxx

8-Bank SDRAM Bank 3 Bank 4 Bank 5 Bank 6 Bank 7

Notes: 1. When a mask bit is asserted (OP[n] = 1), refresh to that bank is disabled.
2. PASR bank masking is on a per-channel basis; the two channels on the die may have different bank masking in dual-channel devices.

Table 95: MR17 PASR Segment Mask (MA[5:0] = 11h)

OP7

OP6

OP5

OP4

OP3

PASR segment mask

OP2

OP1

OP0

Table 96: MR17 PASR Segment Mask Definitions

Feature Segment[7:0] mask

Type Write-only

OP OP[7:0]

Definition 0b: Segment refresh enabled (default) 1b: Segment refresh disabled

Table 97: MR17 PASR Segment Mask

Segment OP

0

0

1

1

2

2

3

3

4

4

5

5

6

6

7

7

Segment Mask
XXXXXXX1 XXXXXX1X XXXXX1XX XXXX1XXX XXX1XXXX XX1XXXXX X1XXXXXX 1XXXXXXX

Density (per channel)

1Gb

2Gb

3Gb

4Gb

6Gb

8Gb

12Gb 16Gb

R[12:10] R[13:11] R[14:12] R[14:12] R[15:13] R[15:13] R[16:14] R[16:14]

000b

001b

010b

011b

100b

101b

110b 111b

110b 111b

Not allowed

110b 111b

Not allowed

110b 111b

Not allowed

110b 111b

Notes:

1. This table indicates the range of row addresses in each masked segment. "X" is "Don't Care" for a particular segment.
2. PASR segment-masking is on a per-channel basis. The two channels on the die may have different segment masking in dual-channel devices.
3. For 3Gb, 6Gb, and 12Gb density per channel, OP[7:6] must always be LOW (= 00b).

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

154

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Mode Registers

Table 98: MR18 Register Information (MA[5:0] = 12h)

OP7

OP6

OP5

OP4

OP3

DQS oscillator count - LSB

OP2

OP1

OP0

Table 99: MR18 LSB DQS Oscillator Count

Notes 1­3 apply to entire table

Function

Type

DQS oscillator count

Read-only

(WR training DQS oscillator)

OP OP[7:0]

Definition 0h­FFh LSB DRAM DQS oscillator count

Notes:

1. MR18 reports the LSB bits of the DRAM DQS oscillator count. The DRAM DQS oscillator count value is used to train DQS to the DQ data valid window. The value reported by the DRAM in this mode register can be used by the memory controller to periodically adjust the phase of DQS relative to DQ.
2. Both MR18 and MR19 must be read (MRR) and combined to get the value of the DQS oscillator count.
3. The value in this register is reset each time an MPC command is issued to start in the DQS oscillator counter.

Table 100: MR19 Register Information (MA[5:0] = 13h)

OP7

OP6

OP5

OP4

OP3

DQS oscillator count ­ MSB

OP2

OP1

OP0

Table 101: MR19 DQS Oscillator Count

Notes 1­3 apply to the entire table

Function

Type

DQS oscillator count ­ MSB Read-only (WR training DQS oscillator)

OP OP[7:0]

Definition 0h­FFh MSB DRAM DQS oscillator count

Notes:

1. MR19 reports the MSB bits of the DRAM DQS oscillator count. The DRAM DQS oscillator count value is used to train DQS to the DQ data valid window. The value reported by the DRAM in this mode register can be used by the memory controller to periodically adjust the phase of DQS relative to DQ.
2. Both MR18 and MR19 must be read (MRR) and combined to get the value of the DQS oscillator count.
3. A new MPC[START DQS OSCILLATOR] should be issued to reset the contents of MR18/ MR19.

Table 102: MR20 Register Information (MA[5:0] = 14h)

OP7

OP6

OP5

OP4

OP3

OP2

Upper-byte invert register for DQ calibration

OP1

OP0

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

155

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Mode Registers

Table 103: MR20 Register Information

Notes 1­3 apply to entire table

Function

Type

Upper-byte invert for DQ calibration

Write-only

OP OP[7:0]

Definition
The following values may be written for any operand OP[7:0] and will be applied to the corresponding DQ locations DQ[15:8] within a byte lane 0b: Do not invert 1b: Invert the DQ calibration patterns in MR32 and MR40 Default value for OP[7:0] = 55h

Notes:

1. This register will invert the DQ calibration pattern found in MR32 and MR40 for any single DQ or any combination of DQ. For example, if MR20 OP[7:0] = 00010101b, the DQ calibration patterns transmitted on DQ[15, 14, 13, 11, 9] will not be inverted, but the DQ calibration patterns transmitted on DQ[12, 10, 8] will be inverted.
2. DM[1] is not inverted and always transmits the true data contained in MR32 and MR40.
3. No DATA BUS INVERSION (DBI) function is enacted during read DQ calibration, even if DBI is enabled in MR3 OP[6].

Table 104: MR20 Invert Register Pin Mapping

Pin MR20

DQ8 OP0

DQ9 OP1

DQ10 OP2

DQ11 OP3

DMI1 No invert

DQ12 OP4

DQ13 OP5

DQ14 OP6

DQ15 OP7

Table 105: MR21 Register Information (MA[5:0] = 15h)

OP7

OP6

OP5

OP4

OP3

RFU

OP2

OP1

OP0

Table 106: MR22 Register Information (MA[5:0] = 16h)

OP7

OP6

ODTD for x8_2ch

OP5 ODTD-CA

OP4 ODTE-CS

OP3 ODTE-CK

OP2

OP1 SOC ODT

OP0

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

156

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Mode Registers

Table 107: MR22 Register Information

Function
SOC ODT (controller ODT value for VOH calibration)

Type Write-only

ODTE-CK (CK ODT enabled Write-only for non-terminating rank)

ODTE-CS (CS ODT enabled Write-only for non-terminating rank)

ODTD-CA (CA ODT termina- Write-only tion disable)

ODTD for x8_2ch (Byte) mode

Write-only

OP OP[2:0]
OP[3] OP[4] OP[5] OP[7:6]

Data 000b: Disable (default) 001b: RZQ/1 (Illegal if MR3 OP[0] = 0b) 010b: RZQ/2 011b: RZQ/3 (Illegal if MR3 OP[0] = 0b) 100b: RZQ/4 101b: RZQ/5 (Illegal if MR3 OP[0] = 0b) 110b: RZQ/6 (Illegal if MR3 OP[0] = 0b) 111b: RFU ODT bond PAD is ignored 0b: ODT-CK enable (default) 1b: ODT-CK disable ODT bond PAD is ignored 0b: ODT-CS enable (default) 1b: ODT-CS disable ODT bond PAD is ignored 0b: CA ODT enable (default) 1b: CA ODT disable See Byte Mode section

Notes 1, 2, 3
2, 3 2, 3 2, 3

Notes:

1. All values are typical.
2. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address.
3. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. The device will operate only according to the values stored in the registers for the active set point, for example, the set point determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation.

Table 108: MR23 Register Information (MA[5:0] = 17h)

OP7

OP6

OP5

OP4

OP3

OP2

DQS interval timer run-time setting

OP1

OP0

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

157

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Mode Registers

Table 109: MR23 Register Information

Notes 1­2 apply to entire table

Function

Type

DQS interval timer run-time Write-only

OP OP[7:0]

Data
00000000b: Disabled (default) 00000001b: DQS timer stops automatically at the 16th clock after timer start 00000010b: DQS timer stops automatically at the 32nd clock after timer start 00000011b: DQS timer stops automatically at the 48th clock after timer start 00000100b: DQS timer stops automatically at the 64th clock after timer start
--------- Through --------00111111b: DQS timer stops automatically at the (63 × 16)th clock after timer start 01XXXXXXb: DQS timer stops automatically at the 2048th clock after timer start 10XXXXXXb: DQS timer stops automatically at the 4096th clock after timer start 11XXXXXXb: DQS timer stops automatically at the 8192nd clock after timer start

Notes:

1. MPC command with OP[6:0] = 1001101b (STOP DQS INTERVAL OSCILLATOR) stops the DQS interval timer in the case of MR23 OP[7:0] = 00000000b.
2. MPC command with OP[6:0] = 1001101b (STOP DQS INTERVAL OSCILLATOR) is illegal with valid nonzero values in MR23 OP[7:0].

Table 110: MR24 Register Information (MA[5:0] = 18h)

OP7 TRR mode

OP6

OP5 TRR mode BAn

OP4

OP3
Unlimited MAC

OP2

OP1 MAC value

OP0

Table 111: MR24 Register Information

Function MAC value

Type Read

OP Data OP[2:0] 000b: Unknown (OP[3] = 0) or unlimited (OP[3] = 1)
001b: 700K 010b: 600K 011b: 500K 100b: 400K 101b: 300K 110b: 200K 111b: Reserved

Notes 1, 2

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

158

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Mode Registers

Table 111: MR24 Register Information (Continued)

Function Unlimited MAC TRR mode BAn
TRR mode

Type Read Write
Write

OP Data OP[3] 0b: OP[2:0] defines the MAC value
1b: Unlimited MAC value OP[6:4] 000b: Bank 0
001b: Bank 1 010b: Bank 2 011b: Bank 3 100b: Bank 4 101b: Bank 5 110b: Bank 6 111b: Bank 7 OP[7] 0b: Disabled (default) 1b: Enabled

Notes 2, 3

Notes:

1. Unknown means that the device is not tested for tMAC and pass/fail values are unknown. Unlimited means that there is no restriction on the number of activates between refresh windows. However, specific attempts to by-pass TRR may result in data disturb.
2. There is no restriction to the number of activates.
3. MR24 OP[2:0] set to 000b.

Table 112: MR25 Register Information (MA[5:0] = 19h)

OP7 Bank 7

OP6 Bank 6

OP5 Bank 5

OP4 Bank 4

OP3 Bank 3

OP2 Bank 2

OP1 Bank 1

OP0 Bank 0

Table 113: MR25 Register Information

Function PPR resources

Type Read-only

OP OP[7:0]

Data 0b: PPR resource is not available 1b: PPR resource is available

Note: 1. When OP[n] = 0, there is no PPR resource available for that bank. When OP[n] = 1, there is a PPR resource available for that bank, and PPR can be initiated by the controller.

Table 114: MR26:29 Register Information (MA[5:0] = 1Ah­1Dh)

OP7

OP6

OP5

OP4

OP3

Reserved for future use

OP2

OP1

OP0

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

159

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Mode Registers

Table 115: MR30 Register Information (MA[5:0] = 1Eh)

OP7

OP6

OP5

OP4

OP3

Valid 0 or 1

OP2

OP1

OP0

Table 116: MR30 Register Information

Function SDRAM will ignore

Type

OP Data

Write-only OP[7:0] Don't care

Note: 1. This register is reserved for testing purposes. The logical data values written to OP[7:0] will have no effect on SDRAM operation; however, timings need to be observed as for any other MR access command.

Table 117: MR31 Register Information (MA[5:0] = 1Fh)

OP7

OP6

OP5

OP4

OP3

Reserved for future use

OP2

OP1

OP0

Table 118: MR32 Register Information (MA[5:0] = 20h)

OP7

OP6

OP5

OP4

OP3

OP2

DQ calibration pattern A (default = 5Ah)

OP1

OP0

Table 119: MR32 Register Information

Feature
Return DQ calibration pattern MR32 + MR40

Type Write-only

OP OP[7:0]

Data
Xb: An MPC command issued with OP[6:0] = 1000011b causes the device to return the DQ calibration pattern contained in this register and (followed by) the contents of MR40. A default pattern 5Ah is loaded at power-up or reset, or the pattern may be overwritten with a MRW to this register. The contents of MR15 and MR20 will invert the MR32/MR40 data pattern for a given DQ (see MR15/ MR20 for more information).

Notes 1, 2, 3

Notes:

1. The patterns contained in MR32 and MR40 are transmitted on DQ[15:0] and DMI[1:0] when read DQ calibration is initiated via an MPC command. The pattern is transmitted serially on each data lane and organized little endian such that the low-order bit in a byte is transmitted first. If the data pattern is 27H, the first bit transmitted is a 1 followed by 1, 1, 0, 0, 1, 0, and 0. The bit stream will be 00100111.
2. MR15 and MR20 may be used to invert the MR32/MR40 data pattern on the DQ pins. See MR15 and MR20 for more information. Data is never inverted on the DMI[1:0] pins.
3. The data pattern is not transmitted on the DMI[1:0] pins if DBI-RD is disabled via MR3 OP[6].

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

160

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Mode Registers

4. No DATA BUS INVERSION (DBI) function is enacted during read DQ calibration, even if DBI is enabled in MR3 OP[6].

Table 120: MR33:38 Register Information (MA[5:0] = 21h­26h)

OP7

OP6

OP5

OP4

OP3

Do not use

OP2

OP1

OP0

Table 121: MR39 Register Information (MA[5:0] = 27h)

OP7

OP6

OP5

OP4

OP3

Valid 0 or 1

OP2

OP1

OP0

Table 122: MR39 Register Information

Function SDRAM will ignore

Type

OP Data

Write-only OP[7:0] Don't care

Note: 1. This register is reserved for testing purposes. The logical data values written to OP[7:0] will have no effect on SDRAM operation; however, timings need to be observed as for any other MR access command.

Table 123: MR40 Register Information (MA[5:0] = 28h)

OP7

OP6

OP5

OP4

OP3

OP2

DQ calibration pattern B (default = 3Ch)

OP1

OP0

Table 124: MR40 Register Information

Function
Return DQ calibration pattern MR32 + MR40

Type Write-only

OP OP[7:0]

Data
Xb: A default pattern 3Ch is loaded at power-up or reset, or the pattern may be overwritten with a MRW to this register. See MR32 for more information.

Notes 1, 2, 3

Notes:

1. The pattern contained in MR40 is concatenated to the end of MR32 and transmitted on DQ[15:0] and DMI[1:0] when read DQ calibration is initiated via an MPC command. The pattern is transmitted serially on each data lane and organized little endian such that the low-order bit in a byte is transmitted first. If the data pattern in MR40 is 27H, the first bit transmitted will be a 1, followed by 1, 1, 0, 0, 1, 0, and 0. The bit stream will be 00100111.
2. MR15 and MR20 may be used to invert the MR32/MR40 data patterns on the DQ pins. See MR15 and MR20 for more information. Data is never inverted on the DMI[1:0] pins.
3. The data pattern is not transmitted on the DMI[1:0] pins if DBI-RD is disabled via MR3 OP[6].
4. No DATA BUS INVERSION (DBI) function is enacted during read DQ calibration, even if DBI is enabled in MR3 OP[6].

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

161

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Commands and Timing

Table 125: MR41:47 Register Information (MA[5:0] = 29h­2Fh)

OP7

OP6

OP5

OP4

OP3

Do not use

OP2

OP1

OP0

Table 126: MR48:63 Register Information (MA[5:0] = 30h­3Fh)

OP7

OP6

OP5

OP4

OP3

Reserved for future use

OP2

OP1

OP0

Commands and Timing
Commands transmitted on the CA bus are encoded into two parts and are latched on two consecutive rising edges of the clock. This is called 2-tick CA capture because each command requires two clock edges to latch and decode the entire command.

Truth Tables

Truth tables provide complementary information to the state diagram. They also clarify device behavior and applicable restrictions when considering the actual state of the banks.
Unspecified operations and timings are illegal. To ensure proper operation after an illegal event, the device must be either reset by asserting the RESET_n command or powered down and then restarted using the specified initialization sequence before normal operation can continue.
CKE signal has to be held HIGH when the commands listed in the command truth table input.

Table 127: Command Truth Table

Commands are transmitted to the device across a six-lane interface and use CK, CKE, and CS to control the capture of transmitted data
SDR CA Pins

Command

CS

CA0

CA1

CA2

CA3

CA4

CA5

CK Edge Notes

MRW-1

H

L

H

H

L

L

OP7

1

1, 11

L

MA0

MA1

MA2

MA3

MA4

MA5

2

MRW-2

H

L

H

H

L

H

OP6

1

1, 11

L

OP0

OP1

OP2

OP3

OP4

OP5

2

MRR-1

H

L

H

H

H

L

V

1

1, 2, 12

L

MA0

MA1

MA2

MA3

MA4

MA5

2

REFRESH

H

L

L

L

H

(all/per bank)

L

BA0

BA1

BA2

V

L

AB

V

V

1

1, 2, 3, 4

2

ENTER SELF RE-

H

L

L

L

H

H

V

FRESH

L

V

1

1, 2

2

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

162

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Truth Tables

Table 127: Command Truth Table (Continued)

Commands are transmitted to the device across a six-lane interface and use CK, CKE, and CS to control the capture of transmitted data
SDR CA Pins

Command

CS

CA0

CA1

CA2

CA3

CA4

CA5

CK Edge Notes

ACTIVATE-1

H

H

L

R12

R13

R14

R15

1

1, 2, 3, 11

L

BA0

BA1

BA2

R16

R10

R11

2

ACTIVATE-2

H

H

H

R6

R7

R8

R9

1

1, 11

L

R0

R1

R2

R3

R4

R5

2

WRITE-1

H

L

L

H

L

L

BA0

BA1

BA2

V

L

BL

C9

AP

1

1, 2, 3, 6,

7, 9
2

EXIT SELF RE-

H

L

L

H

L

H

V

FRESH

L

V

1

1, 2

2

MASK WRITE-1

H

L

L

H

H

L

BA0

BA1

BA2

V

L

BL

C9

AP

1

1, 2, 3, 5,

6, 7, 9
2

RFU

H

L

L

H

H

H

V

1

1, 2

L

V

2

RFU

H

L

H

L

H

L

V

2

1, 2

L

V

2

RFU

H

L

H

L

H

H

V

2

1, 2

L

V

2

READ-1

H

L

H

L

L

L

BA0

BA1

BA2

V

L

BL

C9

AP

1

1, 2, 3, 6,

7, 9
2

CAS-2

H

(WRITE-2,

L

MASKED

WRITE-2,

READ-2, MRR-2,

MPC (except

NOP)

L

H

L

L

H

C8

C2

C3

C4

C5

C6

C7

1

1, 8, 9

2

PRECHARGE

H

L

L

L

L

(all/per bank)

L

BA0

BA1

BA2

V

H

AB

V

V

1

1, 2, 3, 4

2

MPC

H

L

L

L

L

L

OP6

(TRAIN, NOP)

L

OP0

OP1

OP2

OP3

OP4

OP5

1

1, 2, 13

2

DESELECT

L

X

1

1, 2

Notes:

1. All commands except for DESELECT are two clock cycles and are defined by the current state of CS and CA[5:0] at the rising edge of the clock. DESELECT command is one clock cycle and is not latched by the device.
2. V = H or L (a defined logic level); X = "Don't Care," in which case CS, CK_t, CK_c, and CA[5:0] can be floated.
3. Bank addresses BA[2:0] determine which bank is to be operated upon.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

163

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP ACTIVATE Command
4. AB HIGH during PRECHARGE or REFRESH commands indicate the command must be applied to all banks, and the bank addresses are "Don't Care."
5. MASK WRITE-1 command only supports BL16. For MASK WRITE-1 commands, CA5 must be driven LOW on the first rising clock cycle (R1).
6. AP HIGH during a WRITE-1, MASK WRITE-1, or READ-1 command indicates that an auto precharge will occur to the bank the command is operating on. AP LOW indicates that no auto precharge will occur and the bank will remain open upon completion of the command.
7. When enabled in the mode register, BL HIGH during a WRITE-1, MASK-WRITE-1, or READ-1 command indicates the burst length should be set on-the-fly to BL = 32; BL LOW during one of these commands indicates the burst length should be set on-the-fly to BL = 16. If on-the-fly burst length is not enabled in the mode register, this bit should be driven to a valid level and is ignored by the device.
8. For CAS-2 commands (WRITE-2, MASK WRITE-2, READ-2, MRR-2, or MPC (only WRITEFIFO, READ-FIFO, and READ DQ CALIBRATION)), C[1:0] are not transmitted on the CA [5:0] bus and are assumed to be zero. Note that for CAS-2 WRITE-2 or CAS-2 MASK WRITE-2 command, C[3:2] must be driven LOW.
9. WRITE-1, MASK-WRITE-1, READ-1, MODE REGISTER READ-1, or MPC (only WRITE-FIFO, READ-FIFO, and READ DQ CALIBRATION) command must be immediately followed by CAS-2 command consecutively without any other command in between. WRITE-1, MASK WRITE-1, READ-1, MRR-1, or MPC (only WRITE-FIFO, READ-FIFO, and READ DQ CALIBRATION) command must be issued first before issuing CAS-2 command. MPC (only START and STOP DQS OSCILLATOR, ZQCAL START and LATCH) commands do not require CAS-2 command; they require two additional DES or NOP commands consecutively before issuing any other commands.
10. The ACTIVATE-1 command must be followed by the ACTIVATE-2 command consecutively without any other command between them. The ACTIVATE-1 command must be issued prior to the ACTIVATE-2 command. When the ACTIVATE-1 command is issued, the ACTIVATE-2 command must be issued before issuing another ACTIVATE-1 command.
11. The MRW-1 command must be followed by the MRW-2 command consecutively without any other command between them. The MRW-1 command must be issued prior to the MRW-2 command.
12. The MRR-1 command must be followed by the CAS-2 command consecutively without any other commands between them. The MRR-1 command must be issued prior to the CAS-2 command.
13. The MPC command for READ or WRITE TRAINING operations must be followed by the CAS-2 command consecutively without any other commands between them. The MPC command must be issued prior to the CAS-2 command.
ACTIVATE Command
The ACTIVATE command must be executed before a READ or WRITE command can be issued. The ACTIVATE command is issued in two parts: The bank and upper-row addresses are entered with activate-1 and the lower-row addresses are entered with ACTIVATE-2. ACTIVATE-1 and ACTIVATE-2 are executed by strobing CS HIGH while setting CA[5:0] at valid levels (see Command table) at the rising edge of CK.
The bank addresses (BA[2:0]) are used to select the desired bank. The row addresses (R[15:0]) are used to determine which row to activate in the selected bank. The ACTIVATE-2 command must be applied before any READ or WRITE operation can be executed. The device can accept a READ or WRITE command at time tRCD after the ACTIVATE-2 command is sent. After a bank has been activated, it must be precharged to close the active row before another ACTIVATE-2 command can be applied to the same

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

164

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP ACTIVATE Command
bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum time interval between successive ACTIVATE-2 commands to the same bank is determined by the row cycle time of the device (tRC). The minimum time interval between ACTIVATE-2 commands to different banks is tRRD. Certain restrictions must be observed for bank ACTIVATE and REFpb operations. · Four-activate window (tFAW): No more than 4 banks may be activated (or refreshed,
in the case of REFpb) per channel in a rolling tFAW window. Convert to clocks by dividing tFAW[ns] by tCK[ns] and rounding up to the next integer value. As an example of the rolling window, if RU[(tFAW/tCK)] is 64 clocks, and an ACTIVATE command is issued on clock N, no more than three additional ACTIVATE commands may be issued between clock N + 1 and N + 63. REFpb also counts as bank activation for the purposes of tFAW. · 8-bank per channel, precharge all banks (AB) allowance: tRP for a PRECHARGE ALL BANKS command for an 8-bank device must equal tRPab, which is greater than tRPpb.

Figure 82: ACTIVATE Command

T0 T1 T2 T3 CK_c
CK_t

Ta0 Ta1 Ta2 Ta3

CKE

Tb0 Tb1 Tb2 Tb3

Tc0 Tc1

Td0 Td1 Td2 Td3 Td4 Td5

CS

CA RA

RA BA0

RA

RA

Command ACTIVATE-1 ACTIVATE-2 DES

RA

RA BA1

RA

RA

tRRD

tRCD

Valid BA0

CA

CA

Valid BA0

RA

RA BA0

RA

RA

tRP

ACTIVATE-1

ACTIVATE-2

DES

READ1

tRAS tRC

CAS2

DES

PRECHARGE per bank

DES

ACTIVATE-1

ACTIVATE-2

DES DES

Don't Care

Note:

1. A PRECHARGE command uses tRPab timing for all-bank precharge and tRPpb timing for single-bank precharge. In this figure, tRP is used to denote either all-bank precharge or a single-bank precharge. tCCD = MIN, 1.5nCK postamble, 533 MHz < clock frequency  800 MHz, ODT worst timing case.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

165

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Read and Write Access Modes

Figure 83: tFAW Timing
T0 T1 T2 T3 CK_c CK_t
CKE

Ta0 Ta1 Ta2 Ta3

Tb0 Tb1 Tb2 Tb3

Tc0 Tc1 Tc2 Tc3 Tc4 Td0 Td1 Td2 Td3 Td4

CS

CA RA

RA BA0

RA

RA

RA

RA BA1

RA

RA

RA

RA BA2

RA

RA

RA

RA BA3

RA

RA

RA

RA BA4

RA

RA

Command ACTIVATE-1

ACTIVATE-2 DES

ACTIVATE-1 tRRD

ACTIVATE-2 DES

ACTIVATE-1
tRRD t FAW

ACTIVATE-2 DES

ACTIVATE-1 tRRD

ACTIVATE-2

DES

DES

ACTIVATE-1

ACTIVATE-2

Don't Care
Note: 1. REFpb may be substituted for one of the ACTIVATE commands for the purposes of tFAW.

Read and Write Access Modes
After a bank has been activated, a READ or WRITE command can be executed. This is accomplished by asserting CKE asynchronously, with CS and CA[5:0] set to the proper state (see Command Truth Table) on the rising edge of CK.
The device provides a fast column access operation. A single READ or WRITE command will initiate a burst READ or WRITE operation, where data is transferred to/from the device on successive clock cycles. Burst interrupts are not allowed; however, the optimal burst length may be set on-the-fly (see Command Truth Table).

Preamble and Postamble
The DQS strobe for the device requires a preamble prior to the first latching edge (the rising edge of DQS_t with data valid), and it requires a postamble after the last latching edge. The preamble and postamble options are set via MODE REGISTER WRITE commands.
The read preamble is two tCK in length and is either static or has one clock toggle before the first latching edge. The read preamble option is enabled via MRW to MR1 OP[3] (0 = Static; 1 = Toggle).
The read postamble has a programmable option to extend the postamble by 1nCK (tRPSTE). The extended postamble option is enabled via MRW to MR1 OP[7] (0 = 0.5nCK; 1 = 1.5nCK).

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

166

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Preamble and Postamble

Figure 84: DQS Read Preamble and Postamble ­ Toggling Preamble and 0.5nCK Postamble
T0 T1 T2 T3 T4 Ta0 Ta1 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tc0 Tc1 Tc2 Tc3 Tc4 CK_c CK_t

Command
DQS_c DQS_t
DQ DMI

RD-1

CAS-2

DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES

RL

tDQSCK

tRPRE

tDQSQ

tRPST

DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n10 n11 n12 n13 n14 n15

Notes:

1. BL = 16, Preamble = Toggling, Postamble = 0.5nCK. 2. DQS and DQ terminated VSSQ. 3. DQS_t/DQS_c is "Don't Care" prior to the start of tRPRE. No transition of DQS is implied,
as DQS_t/DQS_c can be HIGH, LOW, or High-Z prior to tRPRE.

Figure 85: DQS Read Preamble and Postamble ­ Static Preamble and 1.5nCK Postamble
T0 T1 T2 T3 T4 Ta0 Ta1 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tc0 Tc1 Tc2 Tc3 Tc4 CK_c CK_t

Command
DQS_c DQS_t
DQ DMI

RD-1

CAS-2

DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES

RL

tDQSCK

tRPRE

tDQSQ

tRPSTE

DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n10 n11 n12 n13 n14 n15

Notes:

1. BL = 16, Preamble = Static, Postamble = 1.5nCK (extended). 2. DQS and DQ terminated VSSQ. 3. DQS_t/DQS_c is "Don't Care" prior to the start of tRPRE. No transition of DQS is implied,
as DQS_t/DQS_c can be HIGH, LOW, or High-Z prior to tRPRE.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

167

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Preamble and Postamble
Figure 86: DQS Write Preamble and Postamble ­ 0.5nCK Postamble
T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7
CK_c CK_t CKE
CS
CA Valid Valid Valid Valid

Command
DQS_c DQS_t
DQ DMI

WRITE-1

CAS-2

DES DES DES DES DES DES DES DES

DES DES DES DES DES

DES DES

WL

tDQSS

t WPRE

t WPST

tDQS2DQ

BL/2
DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN n0 n1 n2 n3 n8 n9 n10 n11 n12 n13 n14 n15

Don't Care

Notes:

1. BL = 16, Postamble = 0.5nCK. 2. DQS and DQ terminated VSSQ. 3. DQS_t/DQS_c is "Don't Care" prior to the start of tWPRE. No transition of DQS is implied,
as DQS_t/DQS_c can be HIGH, LOW, or High-Z prior to tWPRE.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

168

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Preamble and Postamble
Figure 87: DQS Write Preamble and Postamble ­ 1.5nCK Postamble
T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7
CK_c CK_t CKE
CS
CA Valid Valid Valid Valid

Command
DQS_c DQS_t
DQ DMI

WRITE-1

CAS-2

DES DES DES DES DES DES DES DES

DES DES DES DES DES

DES DES

WL

tDQSS

t WPRE

t WPST

tDQS2DQ

BL/2
DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN n0 n1 n2 n3 n8 n9 n10 n11 n12 n13 n14 n15

Don't Care

Notes:

1. BL = 16, Postamble = 1.5nCK. 2. DQS and DQ terminated VSSQ. 3. DQS_t/DQS_c is "Don't Care" prior to the start of tWPRE. No transition of DQS is implied,
as DQS_t/DQS_c can be HIGH, LOW, or High-Z prior to tWPRE.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

169

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Burst READ Operation
Burst READ Operation
A burst READ command is initiated with CKE, CS, and CA[5:0] asserted to the proper state on the rising edge of CK, as defined by the Command Truth Table. The command address bus inputs determine the starting column address for the burst. The two loworder address bits are not transmitted on the CA bus and are implied to be 0; therefore, the starting burst address is always a multiple of four (that is, 0x0, 0x4, 0x8, 0xC).
The READ latency (RL) is defined from the last rising edge of the clock that completes a READ command (for example, the second rising edge of the CAS-2 command) to the rising edge of the clock from which the tDQSCK delay is measured. The first valid data is available RL × tCK + tDQSCK + tDQSQ after the rising edge of clock that completes a READ command.
The data strobe output is driven tRPRE before the first valid rising strobe edge. The first data bit of the burst is synchronized with the first valid (post-preamble) rising edge of the data strobe. Each subsequent data-out appears on each DQ pin, edge-aligned with the data strobe. At the end of a burst, the DQS signals are driven for another half cycle postamble, or for a 1.5-cycle postamble if the programmable postamble bit is set in the mode register. The RL is programmed in the mode registers. Pin timings for the data strobe are measured relative to the cross-point of DQS_t and DQS_c.

Figure 88: Burst Read Timing

T0 T1 T2

T3 T4 T5

T6 T7 T15 T16 T17 T18 T19 T20 T21 T22 T23 T33 T34 T35 T36 T41 T42 T43 T44

CK_c

CK_t

CS

CA

BL

BA0, CA, AP

CAn

CAn

BL

BA0, CA, AP

CAm

CAm

Command

READ-1

DQS_c DQS_t
DQ DMI

CAS-2

DES DES DES DES DES
t CCD = 16 RL = 14

READ-1

CAS-2

tDQSCK

DES DES DES DES

t RPRE

RL = 14 BL/2 = 16

DES DES DES tDQSCK

DES DES DES BL/2 = 8

DES DES

t RPST

tDQSQ

tDQSQ

DOUT n0

DOUT n1

DOUT n2

DOUT n3

DOUT DOUT n4 n5

DOUT n6

DOUT DOUT DOUT n7 n26 n27

DOUT DOUT n28 n29

DOUT DOUT n30 n31

DOUT DOUT m0 m1

DOUT DOUT m10 m11

DOUT m12

DOUT DOUT DOUT m13 m14 m15

Don't Care

Notes:

1. BL = 32 for column n, BL = 16 for column m, RL = 14, Preamble = Toggle, Postamble = 0.5nCK, DQ/DQS: VSSQ termination.
2. DOUT n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

170

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Burst READ Operation

Figure 89: Burst Read Followed by Burst Write or Burst Mask Write

T0

T1 T2

T3

T4 T5

Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7

CK_c

CK_t

CS

CA

BL

BA0, CA, AP

CA

CA

BL

BA0, CA, AP

CA

CA

Command

READ-1

DQS_c DQS_t
DQ DMI

CAS-2

DES DES DES WR-1/MWR-1

CAS-2

RL + RU( tDQSCK(MAX)/ tCK) + BL/2 + RD( tRPST) - WL + tWPRE

RL

tDQSCK

t RPRE

DES DES

DES DES DES DES

DES DES DES DES DES DES

DES DES DES DES

WL BL/2 = 8

tDQSS t WPRE

tDQSQ

tRPST

DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n9 n10 n11 n12 n13 n14 n15

tDQS2DQ

DOUT n0

DOUT DOUT n9 n10

DOUT DOUT n11 n12

DOUT DOUT DOUT n13 n14 n15

Don't Care

Notes:

1. BL = 16, Read preamble = Toggle, Read postamble = 0.5nCK, Write preamble = 2nCK, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination.
2. DOUT n = data-out from column n and DIN n = data-in to column n.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.

Figure 90: Seamless Burst Read

T0 T1 T2 T3 CK_c CK_t
CS

Ta0 Ta1 Ta2 Ta3

Tb0 Tb1 Tb2 Tb3 Tb4 Tc0 Tc1 Tc2 Tc3 Td0 Td1 Td2 Td3 Te0 Te1 Te2 Te3

CA

BL

BA0, CA, AP

CAn

CAn

Command READ-1

CAS-2

DES

DQS_c DQS_t
DQ DMI

BL

BA0, CA, AP

CAm

CAm

BL

BA1, CA, AP

CAn

CAn

READ-1

CAS-2

DES

RL

READ-1

CAS-2

RL tDQSCK t RPRE

DES DES DES

DES

RL t DQSCK

DES DES DES DES DES t DQSCK

DES DES DES DES

tDQSQ

tDQSQ

tDQSQ

tRPST

DOUT DOUT n0 n1

DOUT DOUT n10 n11

DOUT n12

DOUT n13

DOUT DOUT DOUT DOUT n14 n15 m0 m1

DOUT m10

DOUT m11

DOUT m12

DOUT m13

DOUT DOUT DOUT DOUT m14 m15 n0 n1

DOUT n10

DOUT n11

DOUT n12

DOUT n13

DOUT DOUT n14 n15

Bank 0

Bank 1

Don't Care

Notes:

1. BL = 16, tCCD = 8, Preamble = Toggle, Postamble = 0.5nCK, DQ/DQS: VSSQ termination. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

171

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Read Timing

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Burst READ Operation

Figure 91: Read Timing
T0 T1 T2 T3 CK_c CK_t

T4 Ta0 Ta1 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 Tc0 Tc1 Tc2 Tc3

Command

RD-1

DQS_c DQS_t
DQ DMI

CAS-2

DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES

tHZ(DQS)

RL

tDQSCK

tLZ(DQS)

tRPRE

tHZ(DQ) tLZ(DQ)

tDQSQ

tRPST

DnO0UT DnO1UT DnO2UT DnO3UT DnO4UT DnO5UT DnO1U0T DnO1U1T DnO1U2T DnO1U3T DnO1U4T DnO1U5T

Notes:

1. BL = 16, Preamble = Toggling, Postamble = 0.5nCK.
2. DQS, DQ, and DMI terminated VSSQ. 3. Output driver does not turn on before an endpoint of tLZ(DQS) and tLZ(DQ). 4. Output driver does not turn off before an endpoint of tHZ(DQS) and tHZ(DQ).

tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation
tHZ and tLZ transitions occur in the same time window as valid data transitions. These parameters are referenced to a specific voltage level that specifies when the device output is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS) and tLZ(DQ). This section shows a method to calculate the point when the device is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS) and tLZ(DQ), by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. The parameters tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as single ended.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

172

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Burst READ Operation
tLZ(DQS) and tHZ(DQS) Calculation for ATE (Automatic Test Equipment)
Figure 92: tLZ(DQS) Method for Calculating Transitions and Endpoint
CK_t ­ CK_c crossing at the second CAS-2 of READ command
CK_t CK_c
tLZ(DQS)

VOH

DQS_c

0.5 x VOH

VSW2 VSW1

End point: Extrapolated point
0V

Notes:

1. Conditions for calibration: Pull down driver RON = 40 ohms, VOH = VDDQ × 0.5. 2. Termination condition for DQS_t and DQS_C = 50 ohms to VSSQ. 3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device toler-
ances. Use the actual VOH value for tHZ and tLZ measurements.

Figure 93: tHZ(DQS) Method for Calculating Transitions and Endpoint

CK_t ­ CK_c crossing at the second CAS-2 of READ command
CK_t

CK_c

tHZ(DQS)
VOH

End point: Extrapolated point

0.5 x VOH

VSW2 VSW1

0V

DQS_c

Notes: 1. Conditions for calibration: Pull down driver RON = 40 ohms, VOH = VDDQ × 0.5. 2. Termination condition for DQS_t and DQS_C = 50 ohms to VSSQ.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

173

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Burst READ Operation

3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device tolerances. Use the actual VOH value for tHZ and tLZ measurements.

Table 128: Reference Voltage for tLZ(DQS), tHZ(DQS) Timing Measurements

Measured Parameter
DQS_c Low-Z time from CK_t, CK_c
DQS_c High-Z time from CK_t, CK_c

Measured Parameter Symbol tLZ(DQS)
tHZ(DQS)

Vsw1 0.4 × VOH
0.4 × VOH

Vsw2 0.6 × VOH
0.6 × VOH

Unit V

tLZ(DQ) and tHZ(DQ) Calculation for ATE (Automatic Test Equipment)
Figure 94: tLZ(DQ) Method for Calculating Transitions and Endpoint CK_t ­ CK_c crossing at the second CAS-2 of READ command
CK_t

CK_c

t LZ(DQ)

VOH

DQs

0.5 x VOH

VSW2 VSW1

End point: Extrapolated point
0V

Notes:

1. Conditions for calibration: Pull down driver RON = 40 ohms, VOH = VDDQ × 0.5. 2. Termination condition for DQ and DMI = 50 ohms to VSSQ. 3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device toler-
ances. Use the actual VOH value for tHZ and tLZ measurements.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

174

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Burst READ Operation
Figure 95: tHZ(DQ) Method for Calculating Transitions and Endpoint CK_t ­ CK_c crossing at the second CAS-2 of READ command
CK_t
CK_c

tHZ(DQ)
VOH

End point: Extrapolated point

0.5 x VOH

VSW2 VSW1

0V

DQs

Notes:

1. Conditions for calibration: Pull down driver RON = 40 ohms, VOH = VDDQ × 0.5. 2. Termination condition for DQ and DMI = 50 ohms to VSSQ. 3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device toler-
ances. Use the actual VOH value for tHZ and tLZ measurements.

Table 129: Reference Voltage for tLZ(DQ), tHZ(DQ) Timing Measurements

Measured Parameter
DQ Low-Z time from CK_t, CK_c
DQ High-Z time from CK_t, CK_c

Measured Parameter Symbol tLZ(DQ)
tHZ(DQ)

Vsw1 0.4 × VOH
0.4 × VOH

Vsw2 0.6 × VOH
0.6 × VOH

Unit V

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

175

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Burst WRITE Operation
Burst WRITE Operation
A burst WRITE command is initiated with CKE, CS, and CA[5:0] asserted to the proper state at the rising edge of CK, as defined by the Command Truth Table. Column addresses C[3:2] should be driven LOW for burst WRITE commands, and column addresses C[1:0] are not transmitted on the CA bus and are assumed to be zero so that the starting column burst address is always aligned with a 32-byte boundary. The WRITE latency (WL) is defined from the last rising edge of the clock that completes a WRITE command (for example, the second rising edge of the CAS-2 command) to the rising edge of the clock from which tDQSS is measured. The first valid latching edge of DQS must be driven WL × t CK + tDQSS after the rising edge of clock that completes a WRITE command.
The device uses an unmatched DQS DQ path for lower power, so the DQS strobe must arrive at the SDRAM ball prior to the DQ signal by tDQS2DQ. The DQS strobe output must be driven tWPRE before the first valid rising strobe edge. The tWPRE preamble is required to be 2 × tCK at any speed ranges. The DQS strobe must be trained to arrive at the DQ pad latch center-aligned with the DQ data. The DQ data must be held for TdiVW, and the DQS must be periodically trained to stay roughly centered in the TdiVW. Burst data is captured by the SDRAM on successive edges of DQS until the 16- or 32-bit data burst is complete. The DQS strobe must remain active (toggling) for tWPST (write postamble) after the completion of the burst WRITE. After a burst WRITE operation, tWR must be satisfied before a PRECHARGE command to the same bank can be issued. Signal input timings are measured relative to the cross point of DQS_t and DQS_c.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

176

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Burst WRITE Operation

Figure 96: Burst WRITE Operation
T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 CK_c CK_t
CS

Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Tc3 Tc4 Td0 Td1 Td2 Td3 Tb4 Td5

CA

BL

BA0, CA, AP

CA

CA

Valid BA0

RA

BA0, RA

RA

RA

Command WRITE-1
DQS_c DQS_t
DQ
DQS_c DQS_t
DQ
DQS_c DQS_t
DQ

CAS-2

DES DES DES DES DES DES DES DES DES DES DES DES DES PRECHARGE DES DES DES DES

WL

BL/2 + 1 Clock

tWR

tRP

tDQSS (MIN)

tWPRE

tDSH

tDSS

tWPST

ACT-1

tDQS2DQ DnI0N DnI1N DnI2N DnI3N DnI4N DnI5N nD1IN2 nD1IN3 nD1IN4 nD1IN5 tDQSS (Nominal)
tWPRE

ACT-2

tDQS2DQ DnI0N DnI1N DnI2N DnI3N DnI4N nD1IN1 nD1IN2 nD1IN3 nD1IN4 nD1IN5 tDQSS (MAX)
tWPRE

tDQS2DQ DnI0N DnI1N DnI2N DnI3N DnI4N nD1IN1 nD1IN2 nD1IN3 nD1IN4 nD1IN5

Don't Care

Notes:

1. BL = 16, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination. 2. DIN n = data-in to column n. 3. tWR starts at the rising edge of CK after the last latching edge of DQS.
4. DES commands are shown for ease of illustration; other commands may be valid at these times.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

177

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Burst WRITE Operation

Figure 97: Burst Write Followed by Burst Read
T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 CK_c CK_t
CS

Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Tc9 Tc10

CA BL CBAA, A0P, CA CA

BL CBAA, A0P, CA CA

Command WRITE-1
DQS_c DQS_t
DQ

CAS-2

DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES

WL

BL/2 + 1 Clock

tWTR

tDQSS (MIN)

tWPRE

tDSH

tDSS

tWPST

READ-1

tDQS2DQ Dn0IN Dn1IN Dn2IN Dn3IN Dn4IN Dn5IN nD1IN2 nD1IN3 nD1IN4 Dn1IN5

CAS-2

DES DES DES DES RL

Don't Care

Notes:

1. BL = 16, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination. 2. DIN n = data-in to column n. 3. The minimum number of clock cycles from the burst WRITE command to the burst READ
command for any bank is [WL + 1 + BL/2 + RU(tWTR/tCK)]. 4. tWTR starts at the rising edge of CK after the last latching edge of DQS.
5. DES commands are shown for ease of illustration; other commands may be valid at these times.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

178

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Write Timing

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Burst WRITE Operation

Figure 98: Write Timing
T0 T1 T2 T3 CK_c CK_t

T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6

CS

Tb0 Tb1 Tb2 Tb3 Tb4 Tb5

CA

BL

BA0, CA, AP

CA

CA

Command WRITE-1

CAS-2

DQS_c DQS_t

tDQSS (MIN)

DQ

tDQSS (Nominal)
DQS_c DQS_t
DQ

DQS_c DQS_t

tDQSS (MAX)

DQ

DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES

WL

tDQSS (MIN)

tWPRE

tDSH

tDSS

tWPST

tDQS2DQ

DnI0N DnI1N DnI2N DnI3N DnI4N DnI5N nD1I2N nD1IN3 nD1IN4 nD1IN5

tDQSS (Nominal)

tWPRE

tDSH

tDSS

tDQS2DQ

DnI0N DnI1N DnI2N DnI3N DnI4N nD1IN1 nD1I2N nD1IN3 nD1IN4 nD1IN5

tDQSS (MAX)

tWPRE

tDSH

tDSS

tDQS2DQ

tDQSH tDQSL DnI0N DnI1N DnI2N DnI3N DnI4N nD1IN1 nD1I2N nD1IN3 nD1IN4 nD1IN5

Don't Care

Notes:

1. BL = 16, Write postamble = 0.5nCK.
2. DIN n = data-in to column n. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

179

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Burst WRITE Operation

tWPRE Calculation for ATE (Automatic Test Equipment)
Figure 99: Method for Calculating tWPRE Transitions and Endpoints
CK_t
CK_c
Resulting differential signal relevant for tWPRE specification

Vref(CA)

Vsw2

Vsw1

DQS_t - DQS_c

0V

Begin point: Extrapolated point

tWPRE

Note: 1. Termination condition for DQS_t, DQS_c, DQ, and DMI = 50 ohms to VSSQ.

Table 130: Method for Calculating tWPRE Transitions and Endpoints

Measured Parameter
DQS_t, DQS_c differential write preamble

Measured Parameter Symbol
tWPRE

Vsw1 VIHL_AC × 0.3

Vsw2 VIHL_AC × 0.7

tWPST Calculation for ATE (Automatic Test Equipment)
Figure 100: Method for Calculating tWPST Transitions and Endpoints
CK_t
CK_c

Vref(CA)

Unit V

Resulting differential signal relevant for tWPST specification

DQS_t - DQS_c

tWPST

0V
Vsw2 Vsw1
End point: Extrapolated point

Notes:

1. Termination condition for DQS_t, DQS_c, DQ, and DMI = 50 ohms to VSSQ. 2. Write postamble: 0.5tCK 3. The method for calculating differential pulse widths for 1.5tCK postamble is same as
0.5tCK postamble.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

180

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP MASK WRITE Operation

Table 131: Reference Voltage for tWPST Timing Measurements

Measured Parameter
DQS_t, DQS_c differential write postamble

Measured Parameter Symbol
tWPST

Vsw1 ­(VIHL_AC × 0.7)

Vsw2 ­(VIHL_AC × 0.3)

Unit V

MASK WRITE Operation
The device requires that WRITE operations that include a byte mask anywhere in the burst sequence must use the MASK WRITE command. This allows the device to implement efficient data protection schemes based on larger data blocks. The MASK WRITE-1 command is used to begin the operation, followed by a CAS-2 command. A MASKED WRITE command to the same bank cannot be issued until tCCDMW later, to allow the device to finish the internal READ-MODIFY-WRITE operation. One datamask-invert (DMI) pin is provided per byte lane, and the data-mask-invert timings match data bit (DQ) timing. See Data Mask Invert for more information on the use of the DMI signal.

Figure 101: MASK WRITE Command ­ Same Bank
T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 CK_c CK_t
CS

Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Tc9 Tc10

CA BL

BA0, CA, AP

CA

CA

BL

BA0, CA, AP

CA

CA

Command MASK WRITE-1
DQS_c DQS_t
DQ DMI

CAS-2

DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES MASK WRITE-1

WL

tDQSS(MIN)

tWPRE

tCCDMW t WPST

CAS-2

DES DES DES DES WL

tDQS2DQ
DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN n0 n1 n2 n3 n4 n5 n12 n13 n14 n15

Don't Care

Notes:

1. BL = 16, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination. 2. DIN n = data-in to column n. 3. Mask-write supports only BL16 operations. For BL32 configuration, the system needs to
insert only 16-bit wide data for MASKED WRITE operation.
4. DES commands are shown for ease of illustration; other commands may be valid at these time.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

181

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP MASK WRITE Operation

Figure 102: MASK WRITE Command ­ Different Bank

T0 T1 T2 T3 CK_c CK_t
CS

T8 T9 T10 T11

T16 T17 T18 T19

T24 T25 T26 T27

T32 T33 T34 T35 T36 T37 T38

CA BL

BA0, CA, AP

CA

CA

BL

BA1, CA, AP

CA

CA

BL

BA2, CA, AP

CA

CA

BL

BA3, CA, AP

CA

CA

BL

BA0, CA, AP

CA

CA

Command MASK WRITE-1
DQS_c DQS_t
DQ DMI

CAS-2

DES MASK WRITE-1

CAS-2

DES MASK WRITE-1

CAS-2

DES MASK WRITE-1

tCCD

WL

tDQSS

tWPRE

tCCD

tCCDMW

tCCD

CAS-2

DES MASK WRITE-1 tCCD

CAS-2

DES DES DES

tDQS2DQ
DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN n0 n1 n2 n3 n10 n11 n12 n13 n14 n15 n0 n1 n2 n3 n10 n11 n12 n13 n14 n15 n0 n1 n2 n10 n11 n12 n13 n14 n15 n0 n1 n2 n3 n4 n5 n6 n7 n8

Don't Care

Notes:

1. BL = 16, DQ/DQS/DMI: VSSQ termination. 2. DIN n = data-in to column n. 3. Mask-write supports only BL16 operations. For BL32 configuration, the system needs to
insert only 16-bit wide data for MASKED WRITE operation.
4. DES commands are shown for ease of illustration; other commands may be valid at these time.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

182

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP MASK WRITE Operation
Mask Write Timing Constraints for BL16

Table 132: Same Bank (ODT Disabled)

Next CMD Current CMD ACTIVE READ (with BL = 16)
READ (with BL = 32)
WRITE (with BL = 16) WRITE (with BL = 32) MASK WRITE
PRECHARGE

ACTIVE Illegal Illegal
Illegal
Illegal Illegal Illegal RU(tRP/tCK), RU(tRPab/tCK)

READ (BL = 16 or 32)
RU(tRCD/tCK) 81
162
WL + 1+ BL/2 + RU(tWTR/tCK) WL + 1 + BL/2 + RU(tWTR/tCK) WL + 1 + BL/2 + RU(tWTR/tCK)
Illegal

WRITE (BL = 16 or 32)

MASK WRITE

RU(tRCD/tCK)

RU(tRCD/tCK)

RL +

RL +

RU(tDQSCK(MAX)/ RU(tDQSCK(MAX)/

tCK) + BL/2 - WL + tCK) + BL/2 - WL +

tWPRE + RD( tRPST) tWPRE + RD( tRPST)

RL +

RL +

RU(tDQSCK(MAX)/ RU(tDQSCK(MAX)/

tCK) + BL/2 - WL + tCK) + BL/2 - WL +

tWPRE + RD( tRPST) tWPRE + RD( tRPST)

81

tCCDMW3

162

tCCDMW + 84

tCCD

tCCDMW3

Illegal

Illegal

PRECHARGE RU(tRAS/tCK)
BL/2 + MAX{(8,RU(tRTP/
tCK)} - 8
BL/2 + MAX{(8,RU(tRTP/
tCK)} - 8
WL + 1 + BL/2 + RU(tWR/tCK)
WL + 1 + BL/2 + RU(tWR/tCK)
WL + 1 + BL/2 + RU(tWR/tCK) 4

Notes:

1. In the case of BL = 16, tCCD is 8 × tCK. 2. In the case of BL = 32, tCCD is 16 × tCK. 3. tCCDMW = 32 × tCK (4 × tCCD at BL = 16). 4. WRITE with BL = 32 operation is 8 × tCK longer than BL = 16.

Table 133: Different Bank (ODT Disabled)

Next CMD Current CMD ACTIVE READ (with BL = 16)
READ (with BL = 32)
WRITE (with BL = 16) WRITE (with BL = 32) MASK WRITE

ACTIVE RU(tRRD/tCK)
4
4
4 4 4

READ (BL = 16 or 32)
4 81
162
WL + 1+ BL/2 + RU(tWTR/tCK) WL + 1 + BL/2 + RU(tWTR/tCK) WL + 1 + BL/2 + RU(tWTR/tCK)

WRITE (BL = 16 or 32)

MASK WRITE

4

4

RL +

RL +

RU(tDQSCK(MAX)/ RU(tDQSCK(MAX)/

tCK) + BL/2 - WL + tCK) + BL/2 - WL +

tWPRE + RD( tRPST) tWPRE + RD( tRPST)

RL +

RL +

RU(tDQSCK(MAX)/ RU(tDQSCK(MAX)/

tCK) + BL/2 - WL + tCK) + BL/2 - WL +

tWPRE + RD( tRPST) tWPRE + RD( tRPST)

81

81

162

162

81

81

PRECHARGE 22 22
22
22 22 22

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

183

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP MASK WRITE Operation

Table 133: Different Bank (ODT Disabled) (Continued)

Next CMD Current CMD
PRECHARGE

ACTIVE 4

READ (BL = 16 or 32)
4

WRITE (BL = 16 or 32)
4

Notes: 1. In the case of BL = 16, tCCD is 8 × tCK 2. In the case of BL = 32, tCCD is 16 × tCK

MASK WRITE 4

PRECHARGE 4

Table 134: Same Bank (ODT Enabled)

Next CMD Current CMD ACTIVE READ (with BL = 16)
READ (with BL = 32)
WRITE (with BL = 16) WRITE (with BL = 32) MASK WRITE
PRECHARGE

ACTIVE Illegal Illegal
Illegal
Illegal Illegal Illegal RU(tRP/tCK), RU(tRPab/tCK)

READ (BL = 16 or 32)
RU(tRCD/tCK) 81
162
WL + 1+ BL/2 + RU(tWTR/tCK) WL + 1 + BL/2 + RU(tWTR/tCK) WL + 1 + BL/2 + RU(tWTR/tCK)
Illegal

WRITE (BL = 16 or 32)

MASK WRITE

RU(tRCD/tCK)

RU(tRCD/tCK)

RL + RU(

RL + RU(

tDQSCK(MAX)/ tCK) tDQSCK(MAX)/ tCK)

+ BL/2 + RD( tRPST) + BL/2 + RD( tRPST)

- ODTLon - RD(

- ODTLon - RD(

tODTon(MIN)/ tCK) tODTon(MIN)/ tCK)

RL + RU(

RL + RU(

tDQSCK(MAX)/ tCK) tDQSCK(MAX)/ tCK)

+ BL/2 + RD( tRPST) + BL/2 + RD( tRPST)

- ODTLon - RD(

- ODTLon - RD(

tODTon(MIN)/ tCK) tODTon(MIN)/ tCK)

81

tCCDMW3

162

tCCDMW + 84

tCCD

tCCDMW3

Illegal

Illegal

PRECHARGE RU(tRAS/tCK)
BL/2 + MAX{(8,RU(tRTP/
tCK)} - 8
BL/2 + MAX{(8,RU(tRTP/
tCK)} - 8
WL + 1 + BL/2 + RU(tWR/tCK)
WL + 1 + BL/2 + RU(tWR/tCK)
WL + 1 + BL/2 + RU(tWR/tCK) 4

Notes:

1. In the case of BL = 16, tCCD is 8 × tCK. 2. In the case of BL = 32, tCCD is 16 × tCK. 3. tCCDMW = 32 × tCK (4 × tCCD at BL = 16). 4. WRITE with BL = 32 operation is 8 × tCK longer than BL = 16.

Table 135: Different Bank (ODT Enabled)

Next CMD Current CMD
ACTIVE
READ (with BL = 16)

ACTIVE RU(tRRD/tCK)
4

READ (BL = 16 or 32)
4 81

WRITE (BL = 16 or 32)

MASK WRITE

4

4

RL + RU(

RL + RU(

tDQSCK(MAX)/ tCK) tDQSCK(MAX)/ tCK)

+ BL/2 + RD( tRPST) + BL/2 + RD( tRPST)

- ODTLon - RD(

- ODTLon - RD(

tODTon(MIN)/ tCK) tODTon(MIN)/ tCK)

PRECHARGE 22 22

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

184

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Data Mask and Data Bus Inversion (DBI [DC]) Function

Table 135: Different Bank (ODT Enabled) (Continued)

Next CMD Current CMD READ (with BL = 32)
WRITE (with BL = 16) WRITE (with BL = 32) MASK WRITE
PRECHARGE

ACTIVE 4
4 4 4 4

READ (BL = 16 or 32)
162
WL + 1+ BL/2 + RU(tWTR/tCK) WL + 1 + BL/2 + RU(tWTR/tCK) WL + 1 + BL/2 + RU(tWTR/tCK)
4

WRITE (BL = 16 or 32)

MASK WRITE

RL + RU(

RL + RU(

tDQSCK(MAX)/ tCK) tDQSCK(MAX)/ tCK)

+ BL/2 + RD( tRPST) + BL/2 + RD( tRPST)

- ODTLon - RD(

- ODTLon - RD(

tODTon(MIN)/ tCK) tODTon(MIN)/ tCK)

81

81

162

162

81

81

4

4

Notes: 1. In the case of BL = 16, tCCD is 8 × tCK. 2. In the case of BL = 32, tCCD is 16 × tCK.

PRECHARGE 22
22 22 22 4

Data Mask and Data Bus Inversion (DBI [DC]) Function
Data mask (DM) is supported for WRITE operations and the data bus inversion DBI (DC) is supported for READ, WRITE, MASK WRITE, MRR, and MRW operations. DM and DBI (DC) functions are supported with byte granularity. DBI (DC) for READ operations (READ, MRR) can be enabled or disabled via MR3 OP[6]. DBI (DC) for WRITE operations (WRITE, MASK WRITE, MRW ) can be enabled or disabled via MR3 OP[7]. DM for MASK WRITE operations can be enabled or disabled via MR13 OP[5]. The device has one data mask inversion (DMI) pin per byte and a total of two DMI pins per channel. The DMI signal is a bidirectional DDR signal, is sampled with the DQ signals, and is electrically identical to a DQ signal.
There are eight possible states for the device with the DM and DBI (DC) functions.

Table 136: Function Behavior of DMI Signal During WRITE, MASKED WRITE, and READ Operations

DM Function Disabled Disabled Disabled Disabled Enabled Enabled Enabled

Write DBI (DC)
Disabled Enabled Disabled Enabled Disabled Enabled Disabled

Read DBI (DC)
Disabled Disabled Enabled Enabled Disabled Disabled Enabled

During WRITE Don't Care1 DBI (DC)4 Don't Care1 DBI (DC)4 Don't Care6 DBI (DC)4 Don't Care6

During MASKED
WRITE Illegal1, 3 Illegal3 Illegal3 Illegal3
DM7 DBI (DC)8
DM7

DMI Signal

During READ

During

During

During

MPC[WRIT MPC[READ- MPC[READ

E-FIFO]

FIFO]

DQ CAL]

High-Z2 Don't Care1 High-Z2

High-Z2

High-Z2

Train9

Train10

Train11

DBI (DC)5

Train9

Train10

Train11

DBI (DC)5

Train9

Train10

Train11

High-Z2

Train9

Train10

Train11

High-Z2

Train9

Train10

Train11

DBI (DC)5

Train9

Train10

Train11

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

185

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Data Mask and Data Bus Inversion (DBI [DC]) Function

Table 136: Function Behavior of DMI Signal During WRITE, MASKED WRITE, and READ Operations (Continued)

DM Function
Enabled

Write DBI (DC)
Enabled

Read DBI (DC)
Enabled

During WRITE
DBI (DC)4

During MASKED
WRITE
DBI (DC)8

DMI Signal

During READ

During

During

During

MPC[WRIT MPC[READ- MPC[READ

E-FIFO]

FIFO]

DQ CAL]

DBI (DC)5

Train9

Train10

Train11

Notes: 1. The DMI input signal is "Don't Care." DMI input receivers are turned off.
2. DMI output drivers are turned off.
3. The MASK WRITE command is not allowed and is considered an illegal command when the DM function is disabled.
4. The DMI signal is treated as DBI and indicates whether the device needs to invert the write data received on DQ within a byte. The device inverts write data received on the DQ inputs if DMI is sampled HIGH and leaves the write data non-inverted if DMI is sampled LOW.
5. The device inverts read data on its DQ outputs associated within a byte and drives the DMI signal HIGH when more than four data bits = 1 within a given byte lane; otherwise, the device does not invert the read data and drives DMI signal LOW.
6. The device does not perform a MASK operation when it receives a WRITE (or MRW) command. During the WRITE burst, the DMI signal must be driven LOW.
7. The device requires an explicit MASKED WRITE command for all MASKED WRITE operations. The DMI signal is treated as a data mask (DM) and indicates which bytes within a burst will be masked. When the DMI signal is sampled HIGH, the device masks that beat of the burst for the given byte lane. All DQ input signals within a byte are "Don't Care" (either HIGH or LOW) when DMI is HIGH. When the DMI signal is sampled LOW, the device does not perform a MASK operation and data received on the DQ inputs is written to the array.
8. The device requires an explicit MASKED WRITE command for all MASKED WRITE operations. The device masks the write data received on the DQ inputs if five or more data bits = 1 on DQ[2:7] or DQ[10:15] (for lower byte or upper byte respectively) and the DMI signal is LOW. Otherwise, the device does not perform the MASK operation and treats it as a legal DBI pattern. The DMI signal is treated as a DBI signal, and data received on the DQ input is written to the array.
9. The DMI signal is treated as a training pattern. The device does not perform any MASK operation and does not invert write data received on the DQ inputs.
10. The DMI signal is treated as a training pattern. The device returns the data pattern written to the WRITE-FIFO.
11. The DMI signal is treated as a training pattern. For more information, see the Read DQ Calibration Training section.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

186

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Data Mask and Data Bus Inversion (DBI [DC]) Function
Figure 103: MASKED WRITE Command with Write DBI Enabled; DM Enabled T0 T1 T2 T3 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0
CK_c CK_t CKE
CS

CA Valid Valid Valid Valid

Command MASK WRITE-1 DQS_c DQS_t
DQ[7:0] DMI[0]

CAS-2 WL

DES DES DES DES DES DES DES DES DES tDQSS

t WPRE

tDQS2DQ
Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid
N1 I2 I M3 N I N M N N

Don't Care

Notes:

1. N: Input data is written to DRAM cell.
2. I: Input data is inverted, then written to DRAM cell.
3. M: Input data is masked. The total count of 1 data bits on DQ[7:2] is equal to or greater than five.
4. Data mask (DM) is enable: MR13 OP [5] = 0, Data bus inversion (DBI) write is enable: MR3 OP[7] = 1.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

187

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Data Mask and Data Bus Inversion (DBI [DC]) Function
Figure 104: WRITE Command with Write DBI Enabled; DM Disabled T0 T1 T2 T3 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0
CK_c CK_t CKE
CS

CA Valid Valid Valid Valid

Command WRITE-1 DQS_c DQS_t
DQ[7:0] DMI[0]

CAS-2 WL

DES DES DES DES DES DES DES DES DES tDQSS

t WPRE

tDQS2DQ
Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid
N1 N I2 I N N I N N N

Don't Care

Notes:

1. N: Input data is written to DRAM cell.
2. I: Input data is inverted, then written to DRAM cell.
3. Data mask (DM) is disable: MR13 OP [5] = 1, Data bus inversion (DBI) write is enable: MR3 OP[7] = 1.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

188

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP WRITE and MASKED WRITE Operation DQS Control (WDQS
Control)
WRITE and MASKED WRITE Operation DQS Control (WDQS Control)
The device supports WRITE, MASKED WRITE, and WR-FIFO operations with the following DQS controls. Before and after WRITE, MASKED WRITE, and WR-FIFO operations, DQS_t, and DQS_c are required to have sufficient voltage gap to make sure the write buffers operating normally without any risk of meta-stability.
The device is supported by either of the two WDQS control modes below.
· Mode 1: Read based control · Mode 2: WDQS_on / WDQS_off definition based control
Regardless of ODT enable/disable, WDQS related timing described here does not allow any change of existing command timing constraints for all READ/WRITE operations. In case of any conflict or ambiguity on the command timing constraints caused by the specification here, the specification defined in the Timing Constraints for Training Commands table should have higher priority than WDQS control requirements.
In order to prevent write preamble related failure, either of the two WDQS controls to the device should be supported.
WDQS Control Mode 1 ­ Read-Based Control
The device needs to be guaranteed the differential WDQS, but the differential WDQS can be controlled as described below. WDQS control requirements here can be ignored while differential read DQS is operated or while DQS hands over from read to write or vice versa.
1. When WRITE/MASKED WRITE command is issued, SoC makes the transition from driving DQS_c HIGH to driving differential DQS_t/DQS_c, followed by normal differential burst on DQS pins.
2. At the end of post amble of WRITE/MASKED WRITE burst, SoC resumes driving DQS_c HIGH through the subsequent states except for DQS toggling and DQS turn around time of WT-RD and RD-WT as long as CKE is HIGH.
3. When CKE is LOW, the state of DQS_t/DQS_c is allowed to be "Don't Care."

Figure 105: WDQS Control Mode 1
WT CMD

WT BURST

Following states from WT burst

CKE DQS_c DQS_t

Don't Care

WDQS Control Mode 2 ­ WDQS_On/Off
After WRITE/MASKED WRITE command is issued, DQS_t and DQS_c required to be differential from WDQS_on, and DQS_t and DQS_c can be "Don't Care" status from WDQS_off of WRITE/MASKED WRITE command. When ODT is enabled, WDQS_on and WDQS_off timing is located in the middle of the operations. When host disables

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

189

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP WRITE and MASKED WRITE Operation DQS Control (WDQS
Control)
ODT, WDQS_on and WDQS_off constraints conflict with tRTW. The timing does not conflict when ODT is enabled because WDQS_on and WDQS_off timing is covered in ODTLon and ODTLoff. However, regardless of ODT on/off, WDQS_on/off timing below does not change any command timing constraints for all read and write operations. In order to prevent the conflict, WDQS_on/off requirement can be ignored where WDQS_on/off timing is overlapped with read operation period including READ burst period and tRPST or overlapped with turn-around time (RD-WT or WT-RD). In addition, the period during DQS toggling caused by read and write can be counted as WDQS_on/ off.
Parameters
· WDQS_on: The maximum delay from WRITE/MASKED WRITE command to differential DQS_t and DQS_c
· WDQS_off: The minimum delay for DQS_t and DQS_c differential input after the last WRITE/MASKED WRITE command
· WDQS_Exception: The period where WDQS_on and WDQS_off timing is overlapped with READ operation or with DQS turn around (RD-WT, WT-RD)
­ WDQS_Exception @ ODT disable = MAX(WL-WDQS_on + tDQSTA - tWPRE - n tCK, 0 tCK) where RD to WT command gap = tRTW(MIN)@ODT disable + n tCK
­ WDQS_Exception @ ODT enable = tDQSTA

Table 137: WDQS_On/WDQS_Off Definition

WRITE Latency

Set A

Set B

4

4

6

8

8

12

10

18

12

22

14

26

16

30

18

34

nWR 6 10 16 20 24 30 34 40

nRTP 8 8 8 8 10 12 14 16

WDQS_On (Max)

Set A

Set B

0

0

0

0

0

6

4

12

4

14

6

18

6

20

8

24

WDQS_Off (Min)

Set A

Set B

15

15

18

20

21

25

24

32

27

37

30

42

33

47

36

52

Lower Frequency Limit (>)
10 266 533 800 1066 1333 1600 1866

Upper Frequency Limit ()
266 533 800 1066 1333 1600 1866 2133

Notes:

1. WDQS_on/off requirement can be ignored when WDQS_on/off timing is overlapped with READ operation period including READ burst period and tRPST or overlapped with turn-around time (RD-WT or WT-RD).
2. DQS toggling period caused by read and write can be counted as WDQS_on/off.

Table 138: WDQS_On/WDQS_Off Allowable Variation Range

WDQS_on WDQS_off

Min ­0.25 ­0.25

Max 0.25 0.25

Unit tCK(avg) tCK(avg)

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

190

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP WRITE and MASKED WRITE Operation DQS Control (WDQS
Control)

Table 139: DQS Turn-Around Parameter

Parameter tDQSTA

Description Turn-around time RDQS to WDQS for WDQS control case

Value TBD

Unit ­

Note 1

Note: 1. tDQSTA is only applied to WDQS_exception case when WDQS Control. Except for WDQS Control, tDQSTA can be ignored.

Figure 106: Burst WRITE Operation
T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Ta9 Ta10 Ta11 Ta12 Ta13 Ta14 Ta15 Ta16 Ta17 Ta18 Ta19 Ta20 Ta21 CK_c CK_t
CS

CA BL

BA0, CA,AP

CA

CA

Command WRITE-1
DQS_c DQS_t
DQ
DQS_c DQS_t
DQ
DRAM RTT

CAS-2

DES

DES DES DES DES DES DES

WL

WDQS_on

DES DES DES DES DES DES DES

DES DES DES

DES DES DES DES DES DES

tWPRE

t DQSS(MIN)

WDQS_off

t WPST

t DQS2DQ

Dnn0I0 nD1I nD2I nD3I nD4I nD5I nD6I DnI7 nD8I nD9I nD1I0 nD1I1 nD1I2 nD1I3 nD14I nD1I5 tDQSS(MAX)

t WPRE

t WPST

ODTLon

tODTon(MAX) tODTon(MIN)

tDQS2DQ nDn00I nD1I nD2I nD3I nD4I nD5I Dn6I Dn7I nD8I nD9I nD1I0 nD1I1 nD1I2 nD1I3 nD1I4 nD15I

ODT High-Z

Transion

ODT on ODTL off

Transition
tODToff(MIN) tODToff(MAX)

ODT High-Z

Don't Care

Notes:

1. BL=16, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination. 2. DI n = data-in to column n.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. DRAM RTT is only applied when ODT is enabled (MR11 OP[2:0] is not 000b).

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

191

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP WRITE and MASKED WRITE Operation DQS Control (WDQS
Control)

Figure 107: Burst READ Followed by Burst WRITE or Burst MASKED WRITE (ODT Disable)
T0 T1 T2 T3 T4 T8 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7
CK_c CK_t
CS

CA

BL CBAA, 0A,P CA

CA

BL

BA0, CA, AP

CA

CA

Command READ-1
DQS_c DQS_t
DQ

CAS-2

DES DES DES WR-1/MWR-1

CAS-2

RL + RU(tDQSCK(MAX)/tCK) + BL/2 + RD(tRPST) - WL + tWPRE

RL

tDQSCK

tRPRE

DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES

WDQS_on

WL WDQS_exception

WDQS_off

tDQSS

BL/2 = 8

tWPRE

tDQSQ

tRPST

D0 D0 D0 D0 D0 D0 D0 D0 n0 n9 n10 n11 n12 n13 n14 n15

tDQSTA

tDQS2DQ
DI DI DI DI DI DI DI DI n0 n9 n10 n11 n12 n13 n14 n15

Don't Care

Notes:

1. BL = 16, Read preamble = Toggle, Read postamble = 0.5nCK, Write preamble = 2nCK, Write postamble = 0.5nCK.
2. DO n = data-out from column n, DI n = data-in to column n.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. WDQS_on and WDQS_off requirement can be ignored where WDQS_on/off timing is overlapped with READ operation period including READ burst period and tRPST or overlapped with turn-around time (RD-WT or WT-RD).

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

192

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Preamble and Postamble Behavior

Figure 108: Burst READ Followed by Burst WRITE or Burst MASKED WRITE (ODT Enable)

T0 T1 T2 T3 T4 T8 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1 Tb2 Tb3 Tb4 Tc0 Tc1 Tc2 Td0 Td1 Td2 Td3 Td4 Te0 Te1 Te2 Te3 Te4 Te5 Te6 Tf0 Tf1 CK_c CK_t
CS

CA

BL

BA0, CA,AP

CA

CA

BL

BA0, CA,AP

CA

CA

Command

READ-1

DQS_c DQS_t
DQ
DRAM RTT

CAS-2

DES

DES DES WR-1/MWR-1

CAS-2

RL + RU(tDQSCK(MAX)/ tCK) + BL/2 + RD(tRPST) - ODTLon - RD(tODTon(MIN)/tCK) + 1

RL

tDQSCK

t RPRE

DES DES DES DES DES DES DES WL

DES DES DES

DES DES

DES DES tDQSS

DES DES WDQS_off

DES DES

DES DES

DES DES

BL/2 = 8

WDQS_on ODTLon

t WPRE

ODTL_off

tDQSQ

tRPST

DO DO DO DO DO DO DO DO n0 n9 n10 n11 n12 n13 n14 n15

t DQSTA

ODT High-Z

ODTon,max ODTon,min
Transion

tDQS2DQ DI DI DI DI DI DI DI DI n0 n9 n10 n11 n12 n13 n14 n15
ODToff,min

ODToff,max

Transition ODT On

Transion ODT High-Z

Don't Care

Notes:

1. BL = 16, Read preamble = Toggle, Read postamble = 0.5nCK, Write preamble = 2nCK, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination.
2. DO n = data-out from column n, DI n = data-in to column n.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.
4. WDQS_on and WDQS_off requirement can be ignored where WDQS_on/off timing is overlapped with READ operation period including READ burst period and tRPST or overlapped with turn-around time (RD-WT or WT-RD).

Preamble and Postamble Behavior
Preamble, Postamble Behavior in READ-to-READ Operations
The following illustrations show the behavior of the device's read DQS_t and DQS_c pins during cases where the preamble, postamble, and/or data clocking overlap.
DQS will be driven with the following priority
1. Data clocking edges will always be driven 2. Postamble 3. Preamble
Essentially the data clocking, preamble, and postamble will be ordered such that all edges will be driven.
Additional examples of seamless and borderline non-overlapping cases have been included for clarity.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

193

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Preamble and Postamble Behavior
READ-to-READ Operations ­ Seamless

Figure 109: READ Operations: tCCD = MIN, Preamble = Toggle, 1.5nCK Postamble
T0 T1 T2 T3 T4 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T26 T27 T28 T29 T30 T31 CK_c CK_t
CS

CA

BL

BA0, CA, AP

CAn

CAn

BL

BA0, CA, AP

CAm

CAm

Command READ-1
DQS_c DQS_t
DQ DMI

CAS-2

DES DES READ-1

CAS-2

DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES

tCCD = 8 RL = 6
High-Z
High-Z

tDQSCK tRPRE

RL = 6

tDQSCK

tRPST

tDQSQ

tDQSQ

DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 m0 m1 m12 m13 m14 m15

BL/2 = 8

BL/2 = 8

High-Z High-Z

Don't Care

Notes:

1. BL = 16 for column n and column m; RL = 6; Preamble = Toggle; Postamble = 1.5nCK.
2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

194

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Preamble and Postamble Behavior
READ-to-READ Operations ­ Consecutive

Figure 110: Seamless READ: tCCD = MIN + 1, Preamble = Toggle, 1.5nCK Postamble
T0 T1 T2 T3 T4 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T26 T27 T28 T29 T30 CK_c CK_t
CS

CA

BL

BA0, CA, AP

CAn

CAn

BL

BA0, CA, AP

CAm

CAm

Command READ-1
DQS_c DQS_t
DQ DMI

CAS-2

DES DES DES READ-1

CAS-2

DES DES DES DES DES DES DES DES DES DES DES DES DES DES

tCCD = 9 RL = 6
High-Z
High-Z

tDQSCK tRPRE

RL = 6

tDQSCK tRPST

tRPST

tDQSQ

tDQSQ

High-Z DnO0UT

DnO1UT

DOUT n2

DnO3UT

DnO4UT

DnO5UT DnO6UT

DnO7UT

DnO8UT

DnO9UT

DnO1U0T

DnO1U1T DnO1U2T

DnO1U3T

DnO1U4T

DnO1U5T

DmO0UT DmO1UT DmO1U2T DmO1U3T DmO1U4T DmO1U5T

BL/2 = 8

BL/2 = 8

High-Z High-Z Don't Care

Notes:

1. BL = 16 for column n and column m; RL = 6; Preamble = Toggle; Postamble = 1.5nCK.
2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times.

Figure 111: Consecutive READ: tCCD = MIN + 1, Preamble = Toggle, 0.5nCK Postamble
T0 T1 T2 T3 T4 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T26 T27 T28 T29 T30 CK_c CK_t
CS

CA

BL

BA0, CA, AP

CAn

CAn

BL

BA0, CA, AP

CAm

CAm

Command READ-1
DQS_c DQS_t
DQ DMI

CAS-2

DES DES DES READ-1

CAS-2

DES DES DES DES DES DES DES DES DES DES DES DES DES DES

tCCD = 9 RL = 6
High-Z
High-Z

tDQSCK tRPRE

RL = 6

tDQSCK

tRPST

tRPRE

tRPST High-Z

tDQSQ

tDQSQ

High-Z DnO0UT

DnO1UT

DnO2UT

DnO3UT

DnO4UT

DOUT n5

DnO6UT

DOUT n7

DOUT n8

DnO9UT

DOUT n10

DOUT DOUT n11 n12

DOUT n13

DOUT n14

DOUT n15

DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15

BL/2 = 8

BL/2 = 8

High-Z Don't Care

Notes: 1. BL = 16 for column n and column m; RL = 6; Preamble = Toggle; Postamble = 0.5nCK. 2. DOUT n/m = data-out from column n and column m.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

195

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Preamble and Postamble Behavior

3. DES commands are shown for ease of illustration; other commands may be valid at these times.

Figure 112: Consecutive READ: tCCD = MIN + 1, Preamble = Static, 1.5nCK Postamble
T0 T1 T2 T3 T4 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T26 T27 T28 T29 T30 CK_c CK_t
CS

CA

BL

BA0, CA, AP

CAn

CAn

BL

BA0, CA, AP

CAm

CAm

Command READ-1
DQS_c DQS_t
DQ DMI

CAS-2

DES DES DES READ-1

CAS-2

tCCD = 9 RL = 6

tDQSCK tRPRE

DES DES DES DES DES DES DES DES DES DES DES DES DES DES

RL = 6

tDQSCK

tRPST

tRPST

High-Z High-Z

tDQSQ

tDQSQ

High-Z DOUT
n0

DOUT n1

DOUT n2

DOUT n3

DOUT n4

DOUT DOUT n5 n6

DOUT n7

DOUT n8

DOUT n9

DOUT n10

DOUT DOUT n11 n12

DOUT n13

DOUT n14

DOUT n15

DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15

BL/2 = 8

BL/2 = 8

High-Z High-Z Don't Care

Notes:

1. BL = 16 for column n and column m; RL = 6; Preamble = Static; Postamble = 1.5nCK.
2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times.

Figure 113: Consecutive READ: tCCD = MIN + 1, Preamble = Static, 0.5nCK Postamble
T0 T1 T2 T3 T4 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T26 T27 T28 T29 T30 CK_c CK_t
CS

CA

BL

BA0, CA, AP

CAn

CAn

BL

BA0, CA, AP

CAm

CAm

Command READ-1
DQS_c DQS_t
DQ DMI

CAS-2

DES DES DES tCCD = 9 RL = 6

High-Z

High-Z

READ-1

CAS-2

DES DES DES DES DES DES DES DES DES DES DES DES DES DES

tDQSCK tRPRE

RL = 6

tDQSCK tRPRE

tRPST

tDQSQ

tDQSQ

High-Z DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15

DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15

BL/2 = 8

BL/2 = 8

High-Z High-Z
Don't Care

Notes: 1. BL = 16 for column n and column m; RL = 6; Preamble = Static; Postamble = 0.5nCK.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

196

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Preamble and Postamble Behavior

2. DOUT n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.

Figure 114: Consecutive READ: tCCD = MIN + 2, Preamble = Toggle, 1.5nCK Postamble
T0 T1 T2 T3 T4 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T28 T29 T30 T31 CK_c CK_t
CS

CA

BL

BA0, CA, AP

CAn

CAn

BL

BA0, CA, AP

CAm

CAm

Command READ-1
DQS_c DQS_t
DQ DMI

CAS-2

DES DES DES DES READ-1

CAS-2

DES DES DES DES DES DES DES DES DES DES DES DES DES

tCCD = 10 RL = 6

tDQSCK tRPRE

RL = 6

tDQSCK tRPST tRPRE

tRPST

High-Z High-Z

tDQSQ
DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
BL/2 = 8

High-Z

tDQSQ
DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15
BL/2 = 8

High-Z High-Z

Don't Care

Notes:

1. BL = 16 for column n and column m; RL = 6; Preamble = Toggle; Postamble = 1.5nCK.
2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

197

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Preamble and Postamble Behavior

Figure 115: Consecutive READ: tCCD = MIN + 2, Preamble = Toggle, 0.5nCK Postamble
T0 T1 T2 T3 T4 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T28 T29 T30 T31 CK_c CK_t
CS

CA

BL

BA0, CA, AP

CAn

CAn

BL

BA0, CA, AP

CAm

CAm

Command READ-1
DQS_c DQS_t
DQ DMI

CAS-2

DES DES DES DES READ-1

CAS-2

DES DES DES DES DES DES DES DES DES DES DES DES DES

tCCD = 10 RL = 6
High-Z
High-Z

tDQSCK tRPRE

RL = 6 tRPST

tDQSCK tRPRE

tRPST

tDQSQ
DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
BL/2 = 8

High-Z

tDQSQ

DOUT m0

DOUT m1

DOUT m12

DOUT m13

DOUT m14

DOUT m15

BL/2 = 8

High-Z High-Z

Don't Care

Notes:

1. BL = 16 for column n and column m; RL = 6; Preamble = Toggle; Postamble = 0.5nCK.
2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times.

Figure 116: Consecutive READ: tCCD = MIN + 2, Preamble = Static, 1.5nCK Postamble
T0 T1 T2 T3 T4 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T28 T29 T30 T31 CK_c CK_t
CS

CA

BL

BA0, CA, AP

CAn

CAn

BL

BA0, CA, AP

CAm

CAm

Command READ-1
DQS_c DQS_t
DQ DMI

CAS-2

DES DES DES DES READ-1

CAS-2

DES DES DES DES DES DES DES DES DES DES DES DES DES

tCCD = 10 RL = 6

tDQSCK tRPRE

RL = 6

tDQSCK tRPST tRPRE

tRPST

High-Z High-Z

tDQSQ
DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
BL/2 = 8

High-Z

tDQSQ
DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15
BL/2 = 8

High-Z High-Z

Don't Care

Notes: 1. BL = 16 for column n and column m; RL = 6; Preamble = Static; Postamble = 1.5nCK. 2. DOUT n/m = data-out from column n and column m.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

198

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Preamble and Postamble Behavior

3. DES commands are shown for ease of illustration; other commands may be valid at these times.

Figure 117: Consecutive READ: tCCD = MIN + 2, Preamble = Static, 0.5nCK Postamble

T0 T1 T2 T3 T4 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T28 T29 T30 T31 CK_c CK_t
CS

CA

BL

BA0, CA, AP

CAn

CAn

BL

BA0, CA, AP

CAm

CAm

Command READ-1
DQS_c DQS_t
DQ DMI

CAS-2

DES DES DES DES READ-1

CAS-2

DES DES DES DES DES DES DES DES DES DES DES DES DES

tCCD = 10 RL = 6
High-Z
High-Z

tDQSCK tRPRE

RL = 6

tDQSCK

tRPST

tRPRE

tRPST

tDQSQ
DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
BL/2 = 8

High-Z

tDQSQ
DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15
BL/2 = 8

High-Z High-Z

Don't Care

Notes:

1. BL = 16 for column n and column m; RL = 6; Preamble = Static; Postamble = 0.5nCK.
2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

199

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Preamble and Postamble Behavior

Figure 118: Consecutive READ: tCCD = MIN + 3, Preamble = Toggle, 1.5nCK Postamble
T0 T1 T2 T3 T4 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T29 T30 T31 CK_c CK_t
CS

CA

BL

BA0, CA, AP

CAn

CAn

BL

BA0, CA, AP

CAm

CAm

Command READ-1
DQS_c DQS_t
DQ DMI

CAS-2

DES DES DES DES DES READ-1

CAS-2

DES DES DES DES DES DES DES DES DES DES DES DES DES

tCCD = 11 RL = 6

tDQSCK tRPRE

RL = 6

tDQSCK

tRPST

tRPRE

tRPST

High-Z High-Z

tDQSQ
DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
BL/2 = 8

High-Z

High-Z

tDQSQ

DOUT m0

DOUT m1

DOUT m12

DOUT m13

DOUT m14

DOUT m15

BL/2 = 8

High-Z

Don't Care

Notes:

1. BL = 16 for column n and column m; RL = 6; Preamble = Toggle; Postamble = 1.5nCK.
2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times.

Figure 119: Consecutive READ: tCCD = MIN + 3, Preamble = Toggle, 0.5nCK Postamble
T0 T1 T2 T3 T4 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T29 T30 T31 CK_c CK_t
CS

CA

BL

BA0, CA, AP

CAn

CAn

BL

BA0, CA, AP

CAm

CAm

Command READ-1
DQS_c DQS_t
DQ DMI

CAS-2

DES DES DES DES DES READ-1

CAS-2

DES DES DES DES DES DES DES DES DES DES DES DES DES

tCCD = 11 RL = 6
High-Z
High-Z

tDQSCK tRPRE

RL = 6

tDQSCK

tRPST

tRPRE High-Z

tDQSQ
DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
BL/2 = 8

High-Z

tRPST

High-Z

tDQSQ

DOUT m0

DOUT m1

DOUT m12

DOUT m13

DOUT m14

DOUT m15

BL/2 = 8

High-Z

Don't Care

Notes:

1. BL = 16 for column n and column m; RL = 6; Preamble = Toggle; Postamble = 0.5nCK.
2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

200

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Preamble and Postamble Behavior

Figure 120: Consecutive READ: tCCD = MIN + 3, Preamble = Static, 1.5nCK Postamble
T0 T1 T2 T3 T4 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T29 T30 T31 CK_c CK_t
CS

CA

BL

BA0, CA, AP

CAn

CAn

BL

BA0, CA, AP

CAm

CAm

Command READ-1
DQS_c DQS_t
DQ DMI

CAS-2

DES DES DES DES DES READ-1

CAS-2

DES DES DES DES DES DES DES DES DES DES DES DES DES

tCCD = 11 RL = 6

tDQSCK tRPRE

RL = 6

tDQSCK

tRPST

tRPRE

tRPST

High-Z High-Z

tDQSQ
DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
BL/2 = 8

High-Z

tDQSQ
DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15
BL/2 = 8

High-Z High-Z

Don't Care

Notes:

1. BL = 16 for column n and column m; RL = 6; Preamble = Static; Postamble = 1.5nCK.
2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times.

Figure 121: Consecutive READ: tCCD = MIN + 3, Preamble = Static, 0.5nCK Postamble
T0 T1 T2 T3 T4 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T29 T30 T31 CK_c CK_t
CS

CA

BL

BA0, CA, AP

CAn

CAn

BL

BA0, CA, AP

CAm

CAm

Command READ-1
DQS_c DQS_t
DQ DMI

CAS-2

DES DES DES DES DES READ-1

CAS-2

DES DES DES DES DES DES DES DES DES DES DES DES DES

tCCD = 11 RL = 6
High-Z
High-Z

tDQSCK tRPRE

RL = 6

tDQSCK

tRPST

tRPRE High-Z

tDQSQ
DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
BL/2 = 8

High-Z

tRPST

High-Z

tDQSQ

DOUT m0

DOUT m1

DOUT m12

DOUT m13

DOUT m14

DOUT m15

BL/2 = 8

High-Z

Don't Care

Notes:

1. BL = 16 for column n and column m; RL = 6, Preamble = Static; Postamble = 0.5nCK
2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

201

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Preamble and Postamble Behavior
WRITE-to-WRITE Operations ­ Seamless

Figure 122: Seamless WRITE: tCCD = MIN, 0.5nCK Postamble
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T23 T24 T25 T26 T27 T28 CK_c CK_t
CS

CA BL

BA0, CA

CAn

CAn

BL

BA0, CA

CAm CAm

Command WRITE-1
DQS_c DQS_t
DQ DMI

CAS-2

DES DES DES DES WRITE-1

tCCD = 8 WL = 4

tWPRE

tDQSS

CAS-2

DES DES DES DES DES DES DES DES DES DES DES DES DES

WL = 4

tDQSS

tWPST

tDQS2DQ

tDQS2DQ

DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 m0 m1 m2 m3 m12 m13 m14 m15

BL/2 = 8

BL/2 = 8

Don't Care

Notes:

1. BL = 16, Write postamble = 0.5nCK.
2. DIN n/m = data-in from column n and column m. 3. The minimum number of clock cycles from the burst WRITE command to the burst
WRITE command for any bank is BL/2.
4. DES commands are shown for ease of illustration; other commands may be valid at these times.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

202

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Preamble and Postamble Behavior

Figure 123: Seamless WRITE: tCCD = MIN, 1.5nCK Postamble, 533 MHz < Clock Frequency  800 MHz, ODT Worst Timing Case
T0 T1 T2 T3 T4 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T23 T24 T25 T31 T32 T33 T34 T35 T36 CK_c CK_t
CS

CA

BL

BA0, CA

CAn

CAn

BL

BA0, CA

CAm CAm

Command WRITE-1
DQS_c DQS_t
DQ DMI DRAM RTT

CAS-2

DES DES WRITE-1
tCCD = 8 WL = 12

CAS-2

DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES

WL = 12 tWPRE

tDQSS

tDQSS

tWPST

ODTLon = 6

t ODTon(MAX)

tDQS2DQ

tDQS2DQ

DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN n0 n1 n2 n13 n14 n15 m0 m1 m2 m13 m14 m15

BL/2 = 8

BL/2 = 8

ODT High-Z

ODT on ODTLoff = 22

ODT High-Z t ODToff(MIN)

Don't Care

Notes:

1. Clock frequency = 800 MHz, tCK(AVG) = 1.25ns.
2. BL = 16, Write postamble = 1.5nCK.
3. DIN n/m = data-in from column n and column m. 4. The minimum number of clock cycles from the burst WRITE command to the burst
WRITE command for any bank is BL/2.
5. DES commands are shown for ease of illustration; other commands may be valid at these times.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

203

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Preamble and Postamble Behavior

Figure 124: Seamless WRITE: tCCD = MIN, 1.5nCK Postamble
T0 T1 T2 T3 T4 T7 T8 T9 T10 T11 T12 T15 T16 T17 T18 T19 T25 T26 T27 T33 T34 T35 T36 T37 T38 CK_c CK_t
CS

CA

BL

BA0, CA

CAn

CAn

BL

BA0, CA

CAm CAm

Command WRITE-1
DQS_c DQS_t
DQ DMI

CAS-2

DES DES WRITE-1
tCCD = 8 WL = 14

CAS-2

DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES

WL = 14 tWPRE

tDQSS

tDQSS

tWPST

tDQS2DQ

tDQS2DQ

DIN n0

DIN n1

DnIN2

DIN n13

DIN n14

DIN n15

DIN m0

DIN m1

DmI2N

DIN m13

DIN DIN m14 m15

BL/2 = 8

BL/2 = 8

Don't Care

Notes:

1. BL = 16, Write postamble = 1.5nCK.
2. DIN n/m = data-in from column n and column m. 3. The minimum number of clock cycles from the burst WRITE command to the burst
WRITE command for any bank is BL/2.
4. DES commands are shown for ease of illustration; other commands may be valid at these times.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

204

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Preamble and Postamble Behavior
WRITE-to-WRITE Operations ­ Consecutive

Figure 125: Consecutive WRITE: tCCD = MIN + 1, 0.5nCK Postamble
T0 T1 T2 T3 T4 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T23 T24 T25 T26 T32 T33 T34 T35 T36 T37 CK_c CK_t
CS

CA

BL

BA0, CA

CAn

CAn

BL

BA0, CA

CAm CAm

Command WRITE-1
DQS_c DQS_t
DQ DMI

CAS-2

DES DES WRITE-1

CAS-2

tCCD = 9

WL = 12

DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES

t WPRE

WL = 12 tDQSS

tDQSS

t WPST

tDQS2DQ
DIN DIN DIN DIN DIN DIN n0 n1 n2 n13 n14 n15
BL/2 = 8

tDQS2DQ

DIN m0

DIN m1

DmI2N

DIN DIN DIN m13 m14 m15

BL/2 = 8

Don't Care

Notes:

1. BL = 16, Write postamble = 0.5nCK.
2. DIN n/m = data-in from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times.

Figure 126: Consecutive WRITE: tCCD = MIN + 1, 1.5nCK Postamble

T0 T1 T2 T3 T4 CK_c CK_t
CS

T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T23 T24 T25 T26 T32 T33 T34 T35 T36 T37

CA

BL

BA0, CA

CAn

CAn

BL

BA0, CA

CAm CAm

Command WRITE-1
DQS_c DQS_t
DQ DMI

CAS-2

DES DES WRITE-1

CAS-2

tCCD = 9

WL = 12

DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES

t WPRE

WL = 12 tDQSS

tDQSS

t WPST

tDQS2DQ
DIN DIN DIN DIN DIN DIN n0 n1 n2 n13 n14 n15
BL/2 = 8

tDQS2DQ

DmI0N

mDI1N

DIN m2

mD1IN3 mD1IN4 mD1IN5

BL/2 = 8

Notes: 1. BL = 16, Write postamble = 1.5nCK. 2. DIN n/m = data-in from column n and column m.

Don't Care

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

205

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Preamble and Postamble Behavior

3. DES commands are shown for ease of illustration; other commands may be valid at these times.

Figure 127: Consecutive WRITE: tCCD = MIN + 2, 0.5nCK Postamble
T0 T1 T2 T3 T4 T9 T10 T11 T12 T13 T14 T15 T16 T17 T23 T24 T25 T26 T27 T33 T34 T35 T36 T37 T38 CK_c CK_t
CS

CA

BL

BA0, CA

CAn

CAn

BL

BA0, CA

CAm CAm

Command WRITE-1
DQS_c DQS_t
DQ DMI

CAS-2

DES DES WRITE-1

CAS-2

tCCD = 10

WL = 12

DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES

t WPRE

WL = 12 tDQSS

tDQSS t WPRE

t WPST

tDQS2DQ
DIN DIN DIN DIN DIN DIN n0 n1 n2 n13 n14 n15
BL/2 = 8

tDQS2DQ

DIN m0

DIN m1

DIN m2

DIN DIN DIN m13 m14 m15

BL/2 = 8

Don't Care

Notes:

1. BL = 16, Write postamble = 0.5nCK.
2. DIN n/m = data-in from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times.

Figure 128: Consecutive WRITE: tCCD = MIN + 2, 1.5nCK Postamble
T0 T1 T2 T3 T4 T9 T10 T11 T12 T13 T14 T15 T16 T17 T23 T24 T25 T26 T27 T33 T34 T35 T36 T37 T38 CK_c CK_t
CS

CA

BL

BA0, CA

CAn

CAn

BL

BA0, CA

CAm CAm

Command WRITE-1
DQS_c DQS_t
DQ DMI

CAS-2

DES DES WRITE-1

CAS-2

tCCD = 10

WL = 12

DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES

t WPRE

WL = 12 tDQSS

tDQSS t WPRE

t WPST

tDQS2DQ
DIN DIN DIN DIN DIN DIN n0 n1 n2 n13 n14 n15
BL/2 = 8
Notes: 1. BL = 16, Write postamble = 1.5nCK.

tDQS2DQ

DmI0N

mDI1N

DIN m2

mD1IN3 mD1IN4 mD1IN5

BL/2 = 8

Don't Care

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

206

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Preamble and Postamble Behavior

2. DIN n/m = data-in from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at these times.

Figure 129: Consecutive WRITE: tCCD = MIN + 3, 0.5nCK Postamble
T0 T1 T2 T3 T4 T9 T10 T11 T12 T13 T14 T15 T16 T17 T23 T24 T25 T26 T27 T28 T34 T35 T36 T37 T38 CK_c CK_t
CS

CA BL

BA0, CA

CAn

CAn

BL

BA0, CA

CAm CAm

Command WRITE-1
DQS_c DQS_t
DQ DMI

CAS-2

DES DES DES WRITE-1

CAS-2

DES DES DES DES DES DES DES DES DES DES DES DES DES DES

tCCD = 11

WL = 12

t WPRE

WL = 12 tDQSS
t WPST

tDQSS t WPRE

t WPST

tDQS2DQ

DnI0N

DnIN1

DnIN2

DIN n13

DIN n14

DIN n15

BL/2 = 8

tDQS2DQ

DIN m0

DIN m1

DIN m2

Din DIN DIN m13 m14 m15

BL/2 = 8

Don't Care

Notes:

1. BL = 16, Write postamble = 0.5nCK.
2. DIN n/m = data-in from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

207

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Preamble and Postamble Behavior

Figure 130: Consecutive WRITE: tCCD = MIN + 3, 1.5nCK Postamble
T0 T1 T2 T3 T4 T9 T10 T11 T12 T13 T14 T15 T16 T17 T23 T24 T25 T26 T27 T28 T34 T35 T36 T37 T38 CK_c CK_t
CS

CA

BL

BA0, CA

CAn

CAn

BL

BA0, CA

CAm CAm

Command WRITE-1
DQS_c DQS_t
DQ DMI

CAS-2

DES DES DES WRITE-1

CAS-2

DES DES DES DES DES DES DES DES DES DES DES DES DES DES

tCCD = 11

WL = 12

t WPRE

WL = 12 tDQSS

t WPST

tDQSS t WPRE

t WPST

tDQS2DQ

DIN n0

DIN n1

DIN n2

DnI1N3

DnI1N4

Dn1IN5

BL/2 = 8

tDQS2DQ

DIN m0

DIN m1

DIN m2

DIN DIN DIN m13 m14 m15

BL/2 = 8

Don't Care

Notes:

1. BL = 16, Write postamble = 1.5nCK.
2. DIN n/m = data-in from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times.

Figure 131: Consecutive WRITE: tCCD = MIN + 4, 1.5nCK Postamble
T0 T1 T2 T3 T4 T9 T10 T11 T12 T13 T14 T15 T16 T17 T23 T24 T25 T26 T27 T28 T29 T35 T36 T37 T38 CK_c CK_t
CS

CA

BL

BA0, CA

CAn

CAn

BL

BA0, CA

CAm CAm

Command WRITE-1
DQS_c DQS_t
DQ DMI

CAS-2

DES DES DES WRITE-1
tCCD = 12 WL = 12

CAS-2

DES DES DES DES DES DES DES DES DES DES DES DES DES DES

t WPRE

WL = 12 tDQSS

t WPST

tDQSS t WPRE

t WPST

tDQS2DQ

DnI0N

DnIN1

DnIN2

DIN n13

DIN n14

DIN n15

BL/2 = 8

t DQS2DQ

DIN m0

DIN m1

DIN m2

DIN DIN DIN m13 m14 m15

BL/2 = 8

Don't Care

Notes:

1. BL = 16, Write postamble = 1.5nCK.
2. DIN n/m = data-in from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

208

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP PRECHARGE Operation
PRECHARGE Operation
The PRECHARGE command is used to precharge or close a bank that has been activated. The PRECHARGE command is initiated with CKE, CS, and CA[5:0] in the proper state (see Command Truth Table). The PRECHARGE command can be used to precharge each bank independently or all banks simultaneously. The all banks (AB) flag and the bank address bit are used to determine which bank(s) to precharge. The precharged bank(s) will be available for subsequent row access tRPab after an all-bank PRECHARGE command is issued, or tRPpb after a single-bank PRECHARGE command is issued.
To ensure that the device can meet the instantaneous current demands, the row precharge time for an all-bank PRECHARGE ( tRPab) is longer than the per-bank precharge time (tRPpb).

Table 140: Precharge Bank Selection

AB (CA[5], R1) 0 0 0 0 0 0 0 0 1

BA2 (CA[2], R2) 0 0 0 0 1 1 1 1
Don't Care

BA1 (CA[1], R2) 0 0 1 1 0 0 1 1
Don't Care

BA0 (CA[0], R2) 0 1 0 1 0 1 0 1
Don't Care

Precharged Bank Bank 0 only Bank 1 only Bank 2 only Bank 3 only Bank 4 only Bank 5 only Bank 6 only Bank 7 only All banks

Burst READ Operation Followed by Precharge
The PRECHARGE command can be issued as early as BL/2 clock cycles after a READ command, but the PRECHARGE command cannot be issued until after tRAS is satisfied. A new bank ACTIVATE command can be issued to the same bank after the row precharge time (tRP) has elapsed. The minimum read-to-precharge time must also satisfy a minimum analog time from the second rising clock edge of the CAS-2 command. tRTP begins BL/2 - 8 clock cycles after the READ command.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

209

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP PRECHARGE Operation

Figure 132: Burst READ Followed by Precharge ­ BL16, Toggling Preamble, 0.5nCK Postamble
T0 T1 T2 T3 T4 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Ty Ty+1 Ty+2 Ty+3 Ty+4 CK_c CK_t

CA[5:0] Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid

tRTP

tRP

Command

READ-1

CAS-2

Valid

PRECHARGE

Valid

Valid

Valid

ACT-1

ACT-2

DQS_t DQS_c
DQ[15:0] DMI[1:0]

Valid
Transitioning Data

Don't Care

Figure 133: Burst READ Followed by Precharge ­ BL32, 2tCK, 0.5nCK Postamble
T0 T1 T2 T3 T4 T5 T10 T11 T12 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Ty Ty+1 Ty+2 Ty+3 Ty+4 CK_c CK_t

CA[5:0] Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid

tRTP

tRP

Command

READ-1

CAS-2

Valid

Valid

Valid

PRECHARGE

Valid

Valid

Valid

ACT-1

ACT-2

DQS_t DQS_c
DQ[15:0] DMI[1:0]

Valid

Transitioning Data

Don't Care

Burst WRITE Followed by Precharge
A write recovery time (tWR) must be provided before a PRECHARGE command may be issued. This delay is referenced from the next rising edge of CK after the last valid DQS clock of the burst.
Devices write data to the memory array in prefetch multiples (prefetch = 16). An internal WRITE operation can only begin after a prefetch group has been clocked; therefore, tWR starts at the prefetch boundaries. The minimum write-to-precharge time for commands to the same bank is WL + BL/2 + 1 + RU(tWR /tCK) clock cycles.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

210

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Auto Precharge

Figure 134: Burst WRITE Followed by PRECHARGE ­ BL16, 2nCK Preamble, 0.5nCK Postamble
T0 T1 T2 T3 T4 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Ta Ta+1 Ta+2 Tn Tn+1 Tn+2 Tn+3 Ty Ty+1 Ty+2 Ty+3 Ty+4 CK_c CK_t

CA Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid
WL

Command

WRITE-1

CAS-2

Valid

DQS_c DQS_t
DQ DMI

Valid

Valid

tDQSS(MAX)

Valid

Valid

Valid tWR

PRECHARGE Valid

tDQS2DQ

ACT-1 tRP

ACT-2

Valid

Transitioning Data

Don't Care

Auto Precharge
Before a new row can be opened in an active bank, the active bank must be precharged using either the PRECHARGE command or the auto precharge (AP) function. When a READ or a WRITE command is issued to the device, the AP bit (CA5) can be set to enable the active bank to automatically begin precharge at the earliest possible moment during the burst READ or WRITE cycle.
If AP is LOW when the READ or WRITE command is issued, the normal READ or WRITE burst operation is executed, and the bank remains active at the completion of the burst.
If AP is HIGH when the READ or WRITE command is issued, the auto PRECHARGE function is engaged. This feature enables the PRECHARGE operation to be partially or completely hidden during burst READ cycles (dependent upon READ or WRITE latency), thus improving system performance for random data access.
Burst READ With Auto Precharge
If AP is HIGH when a READ command is issued, the READ with AUTO PRECHARGE function is engaged. The devices start an AUTO PRECHARGE operation on the rising edge of the clock at BL/2 after the second beat of the READ w/AP command, or BL/4 - 4 + RU(tRTP/tCK) clock cycles after the second beat of the READ w/AP command, whichever is greater. Following an AUTO PRECHARGE operation, an ACTIVATE command can be issued to the same bank if the following two conditions are both satisfied:
1. The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge began, and
2. The RAS cycle time (tRC) from the previous bank activation has been satisfied.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

211

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Auto Precharge

Figure 135: Burst READ With Auto Precharge ­ BL16, Non-Toggling Preamble, 0.5nCK Postamble
T0 T1 T2 T3 T4 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Ty Ty+1 Ty+2 Ty+3 Ty+4 CK_c CK_t

CA[5:0] Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid

tRTP

tRPpb

Command

READ-1 w/AP

CAS-2

Valid

Valid

Valid

Valid

Valid

ACT-1

ACT-2

DQS_t DQS_c

DQ[15:0] DMI[1:0]

Valid
Transitioning Data

Don't Care

Figure 136: Burst READ With Auto Precharge ­ BL32, Toggling Preamble, 1.5nCK Postamble
T0 T1 T2 T3 T4 T5 T10 T11 T12 T13 T14 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Ty Ty+1 Ty+2 Ty+3 Ty+4 CK_c CK_t

CA[5:0] Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid

tRTP

tRP

Command

READ-1

CAS-2

Valid

Valid

Valid

Valid

Valid

Valid

Valid

ACT-1

ACT-2

DQS_t DQS_c
DQ[15:0] DMI[1:0]

Valid

Transitioning Data

Don't Care

Burst WRITE With Auto Precharge
If AP is HIGH when a WRITE command is issued, the WRITE with AUTO PRECHARGE function is engaged. The device starts an auto precharge on the rising edge tWR cycles after the completion of the burst WRITE.
Following a WRITE with AUTO PRECHARGE, an ACTIVATE command can be issued to the same bank if the following conditions are met:
1. The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge began, and

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

212

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Auto Precharge
2. The RAS cycle time (tRC) from the previous bank activation has been satisfied.

Figure 137: Burst WRITE With Auto Precharge ­ BL16, 2nCK Preamble, 0.5nCK Postamble
T0 T1 T2 T3 T4 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Ta Ta+1 Ta+2 Tn Tn+1 Tn+2 Tn+3 Ty Ty+1 Ty+2 Ty+3 Ty+4 CK_c CK_t

CA Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid
WL

Command

WRITE-1

CAS-2

Valid

DQS_c DQS_t
DQ[15:0] DMI[1:0]

Valid

Valid

tDQSS (MAX)

Valid

tDQS2DQ

Valid

Valid tWR

Valid

Valid

ACT-1 tRP

ACT-2

Valid

Transitioning Data

Don't Care

Table 141: Timing Between Commands (PRECHARGE and AUTO PRECHARGE): DQ ODT is Disable

From Command To Command

READ BL = 16

PRECHARGE (to same bank as READ)

PRECHARGE ALL

READ BL = 32

PRECHARGE (to same bank as READ)

PRECHARGE ALL

READ w/AP BL = 16

PRECHARGE (to same bank as READ w/AP)

PRECHARGE ALL

ACTIVATE (to same bank as READ w/AP)

WRITE or WRITE w/AP (same bank)

MASK-WR or MASK-WR w/AP (same bank)

WRITE or WRITE w/AP (different bank)

MASK-WR or MASK-WR w/AP (different bank)

READ or READ w/AP (same bank)

READ or READ w/AP (different bank)

Minimum Delay Between "From Command" and "To Command"
tRTP
tRTP 8tCK + tRTP
8tCK + tRTP nRTP
nRTP nRTP + tRPpb
Illegal
Illegal
RL + RU(tDQSCK(MAX)/tCK) + BL/2 + RD(tRPST) - WL + tWPRE
RL + RU(tDQSCK(MAX)/tCK) + BL/2 + RD(tRPST) - WL + tWPRE Illegal
BL/2

Unit tCK

Notes 1, 6

tCK

1, 6

tCK

1, 6

tCK

1, 6

tCK

1, 10

tCK

1, 10

tCK 1, 8, 10

­

­

tCK 3, 4, 5

tCK 3, 4, 5

­

tCK

3

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

213

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Auto Precharge

Table 141: Timing Between Commands (PRECHARGE and AUTO PRECHARGE): DQ ODT is Disable (Continued)

From Command To Command

READ w/AP BL = 32

PRECHARGE (to same bank as READ w/AP)

PRECHARGE ALL

ACTIVATE (to same bank as READ w/AP)

WRITE or WRITE w/AP (same bank)

MASK-WR or MASK-WR w/AP (same bank)

WRITE or WRITE w/AP (different bank)

MASK-WR or MASK-WR w/AP (different bank)

READ or READ w/AP (same bank)

READ or READ w/AP (different bank)

WRITE BL = 16 and 32

PRECHARGE (to same bank as WRITE)

PRECHARGE ALL

MASK-WR BL = 16

PRECHARGE (to same bank as MASK-WR)

PRECHARGE ALL

WRITE w/AP BL = 16 and 32

PRECHARGE (to same bank as WRITE w/AP)

PRECHARGE ALL

ACTIVATE (to same bank as WRITE w/AP)

WRITE or WRITE w/AP (same bank)

READ or READ w/AP (same bank)

WRITE or WRITE w/AP (different bank)

MASK-WR or MASK-WR w/AP (different bank)

READ or READ w/AP (different bank)

Minimum Delay Between "From Command" and "To Command"
8tCK + nRTP
8tCK + nRTP 8tCK + nRTP + tRPpb
Illegal
Illegal
RL + RU(tDQSCK(MAX)/tCK) + BL/2 + RD(tRPST) - WL + tWPRE
RL + RU(tDQSCK(MAX)/tCK) + BL/2 + RD(tRPST) - WL + tWPRE Illegal
BL/2
WL + BL/2 + tWR + 1
WL + BL/2 + tWR + 1 WL + BL/2 + tWR + 1
WL + BL/2 + tWR + 1 WL + BL/2 + nWR + 1
WL + BL/2 + nWR + 1 WL + BL/2 + nWR + 1 + tRPpb
Illegal
Illegal
BL/2
BL/2
WL + BL/2 + tWTR + 1

Unit tCK

Notes 1, 10

tCK

1, 10

tCK 1, 8, 10

­

­

tCK 3, 4, 5

tCK 3, 4, 5

­

tCK

3

tCK

1, 7

tCK

1, 7

tCK

1, 7

tCK

1, 7

tCK

1, 11

tCK

1, 11

tCK 1, 8, 11

­

­

tCK

3

tCK

3

tCK

3, 9

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

214

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Auto Precharge

Table 141: Timing Between Commands (PRECHARGE and AUTO PRECHARGE): DQ ODT is Disable (Continued)

From Command To Command

MASK-WR w/AP BL = 16

PRECHARGE (to same bank as MASK-WR w/AP)

PRECHARGE ALL

ACTIVATE (to same bank as MASK-WR w/AP)

WRITE or WRITE w/AP (same bank)

MASK-WR or MASK-WR w/AP (same bank)

WRITE or WRITE w/AP (different bank)

MASK-WR or MASK-WR w/AP (different bank)

READ or READ w/AP (same bank)

READ or READ w/AP (different bank)

PRECHARGE

PRECHARGE (to same bank as PRECHARGE)

PRECHARGE ALL

PRECHARGE ALL PRECHARGE

PRECHARGE ALL

Minimum Delay Between "From Command" and "To Command"
WL + BL/2 + nWR +1
WL + BL/2 + nWR + 1 WL + BL/2 + nWR + 1 + tRPpb
Illegal Illegal BL/2 BL/2 Illegal WL + BL/2 + tWTR + 1
4 4 4 4

Unit tCK

Notes 1, 11

tCK

1, 11

tCK 1, 8, 11

­

3

­

3

tCK

3

tCK

3

­

3

tCK

3, 9

tCK

1

tCK

1

tCK

1

tCK

1

Notes:

1. For a given bank, the precharge period should be counted from the latest PRECHARGE command, whether per-bank or all-bank, issued to that bank. The precharge period is satisfied tRP after that latest PRECHARGE command.
2. Any command issued during the minimum delay time as specified in the table above is illegal.
3. After READ w/AP, seamless READ operations to different banks are supported. After WRITE w/AP or MASK-WR w/AP, seamless WRITE operations to different banks are supported. READ, WRITE, and MASK-WR operations may not be truncated or interrupted.
4. tRPST values depend on MR1 OP[7] respectively. 5. tWPRE values depend on MR1 OP[2] respectively.
6. Minimum delay between "from command" and "to command" in clock cycle is calculated by dividing tRTP (in ns) by tCK (in ns) and rounding up to the next integer: Minimum delay [cycles] = roundup(tRTP [ns]/tCK [ns]).
7. Minimum delay between "from command" and "to command" in clock cycle is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer: Minimum delay [cycles] = roundup(tWR [ns]/tCK [ns]).

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

215

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Auto Precharge

8. Minimum delay between "from command" and "to command" in clock cycle is calculated by dividing tRPpb (in ns) by tCK (in ns) and rounding up to the next integer: Minimum delay [cycles] = roundup(tRPpb [ns]/tCK [ns]).
9. Minimum delay between "from command" and "to command" in clock cycle is calculated by dividing tWTR (in ns) by tCK (in ns) and rounding up to the next integer: Minimum delay [cycles] = roundup(tWTR [ns]/tCK [ns]).
10. For READ w/AP the value is nRTP, which is defined in mode register 2. 11. For WRITE w/AP the value is nWR, which is defined in mode register 1.

Table 142: Timing Between Commands (PRECHARGE and AUTO PRECHARGE): DQ ODT is Enable

From Command To Command

READ w/AP BL = 16

WRITE or WRITE w/AP (different bank)

MASK-WR or MASK-WR w/AP (different bank)

READ w/AP BL = 32

WRITE or WRITE w/AP (different bank)

MASK-WR or MASK-WR w/AP (different bank)

Minimum Delay Between "From Command" and "To Command"
RL + RU(tDQSCK(MAX)/tCK) + BL/2 + RD(tRPST) - ODTLon - RD(tODTon(MIN)/tCK) + 1
RL + RU(tDQSCK(MAX)/tCK) + BL/2 + RD(tRPST) - ODTLon - RD(tODTon(MIN)/tCK) + 1
RL + RU(tDQSCK(MAX)/tCK) + BL/2 + RD(tRPST) - ODTLon - RD(tODTon(MIN)/tCK) + 1
RL + RU(tDQSCK(MAX)/tCK) + BL/2 + RD(tRPST) - ODTLon - RD(tODTon(MIN)/tCK) + 1

Unit tCK tCK tCK tCK

Notes 2, 3 2, 3 2, 3 2, 3

Notes:

1. The rest of the timing about PRECHARGE and AUTO PRECHARGE is same as DQ ODT is disable case.
2. After READ w/AP, seamless read operations to different banks are supported. READ, WRITE, and MASK-WR operations may not be truncated or interrupted.
3. tRPST values depend on MR1 OP[7] respectively.

RAS Lock Function
READ with AUTO PRECHARGE or WRITE/MASK WRITE with AUTO PRECHARGE commands may be issued after tRCD has been satisfied. The LPDDR4 SDRAM RAS lockout feature will schedule the internal precharge to assure that tRAS is satisfied. tRC needs to be satisfied prior to issuing subsequent ACTIVATE commands to the same bank.
The figure below shows example of RAS lock function.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

216

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Auto Precharge

Figure 138: Command Input Timing with RAS Lock
T0 T1 T2 T3 T4 T19 T20 T21 T22 T23 T24 T25 T31 T32 CK_c CK_t
CKE

T38 T39 T47

T48 Ta0 Ta1 Ta2 Ta3

Ta4 Ta5

CS

CA RA

RA BA0

RA

RA

Valid BA0

CA

CA

RA

RA BA0

RA

RA

Command ACTIVATE-1 ACTIVATE-2 DES DES

RDA-1

CAS-2

tRCD = 20nCK

tRAS

DES

DES DES DES DES

DES DES DES DES DES

ACTIVATE-1

ACTIVATE-2

8nCK

nRTP = 8nCK

tRC

Don't Care

Notes:

1. tCK (AVG) = 0.938ns, Data rate = 2133 Mb/s, tRCD(MIN) = MAX(18ns, 4nCK), tRAS(MIN) = MAX(42ns, 3nCK), nRTP = 8nCK, BL = 32.
2. tRCD = 20nCK comes from roundup(18ns/0.938ns).
3. DES commands are shown for ease of illustration; other commands may be valid at these times.

Delay Time From WRITE-to-READ with Auto Precharge
In the case of WRITE command followed by READ with AUTO PRECHARGE, controller must satisfy tWR for the WRITE command before initiating the device internal auto-precharge. It means that (tWTR + nRTP) should be equal or longer than (tWR) when BL setting is 16, as well as (tWTR + nRTP + 8nCK) should be equal or longer than (tWR) when BL setting is 32. Refer to the following figure for details.

Figure 139: Delay Time From WRITE-to-READ with Auto Precharge
T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Tb0 Tb1 Tb2 Tb3 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Td0 Td1 Td2 Td3 Td4 CK_c CK_t
CKE

CS

CA BL

BA0 CA

CA

CA

Valid BA0

CA

CA

Command

WRITE-1

CAS-2

DES DES DES DES DES DES DES DES DES DES

RDA-1

CAS-2

WL

BL/2 + 1 clock

tWTR

tWR

Notes: 1. Burst length at read = 16.

DES DES DES DES DES DES nRTP Don't Care

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

217

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP REFRESH Command

2. DES commands are shown for ease of illustration; other commands may be valid at these times.

REFRESH Command
The REFRESH command is initiated with CS HIGH, CA0 LOW, CA1 LOW, CA2 LOW, CA3 HIGH and CA4 LOW at the first rising edge of clock. Per bank REFRESH is initiated with CA5 LOW at the first rising edge of the clock. The all-bank REFRESH is initiated with CA5 HIGH at the first rising edge of clock.
A per bank REFRESH command (REFpb) is performed to the bank address as transferred on CA0, CA1, and CA2 on the second rising edge of the clock. Bank address BA0 is transferred on CA0, bank address BA1 is transferred on CA1, and bank address BA2 is transferred on CA2. A per bank REFRESH command (REFpb) to the eight banks can be issued in any order. For example, REFpb commands may be issued in the following order: 1-3-0-2-4-7-5-6. After the eight banks have been refreshed using the per bank REFRESH command, the controller can send another set of per bank REFRESH commands in the same order or a different order. One possible order can be a sequential round robin: 0-1-2-3-4-5-6-7. It is illegal to send a per bank REFRESH command to the same bank unless all eight banks have been refreshed using the per bank REFRESH command. The count of eight REFpb commands starts with the first REFpb command after a synchronization event.
The bank count is synchronized between the controller and the device by resetting the bank count to zero. Synchronization can occur upon reset procedure or at every exit from self refresh. The REFab command also synchronizes the counter between the controller and the device to zero. The device can be placed in self refresh, or a REFab command can be issued at any time without cycling through all eight banks using per bank REFRESH command. After the bank count is synchronized to zero, the controller can issue per bank REFRESH commands in any order, as described above.
A REFab command issued when the bank counter is not zero will reset the bank counter to zero and the device will perform refreshes to all banks as indicated by the row counter. If another REFRESH command (REFab or REFpb) is issued after the REFab command then it uses an incremented value of the row counter.
The table below shows examples of both bank and refresh counter increment behavior.

Table 143: Bank and Refresh Counter Increment Behavior

#

Command

0

1

REFpb

2

REFpb

3

REFpb

4

REFpb

5

REFpb

6

REFpb

7

REFpb

8

REFpb

BA2
0 0 0 0 1 1 1 1

BA1 Reset, SRX, or REFab
0 0 1 1 0 0 1 1

BA0
0 1 0 1 0 1 0 1

Refresh Bank #
0 1 2 3 4 5 6 7

Bank Counter #
To 0 0 to 1 1 to 2 2 to 3 3 to 4 4 to 5 5 to 6 6 to 7 7 to 0

Ref. Conter # (Row Address #)
­
n

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

218

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP REFRESH Command

Table 143: Bank and Refresh Counter Increment Behavior (Continued)

#

Command

9

REFpb

10

REFpb

11

REFpb

12

REFpb

13

REFpb

14

REFpb

15

REFpb

16

REFpb

17

REFpb

18

REFpb

19

REFpb

20

REFab

21

REFpb

22

REFpb

BA2 1 1 0 0 1 0 0 1 0 0 0 V 1 1

BA1 1 1 0 1 0 1 0 0 0 0 1 V 1 1

BA0 0 1 1 1 1 0 0 0 0 1 0 V 0 1
Snip

Refresh Bank #
6 7 1 3 5 2 0 4 0 1 2 0 to 7 6 7

Bank Counter #
0 to 1 1 to 2 2 to 3 3 to 4 4 to 5 5 to 6 6 to 7 7 to 0 0 to 1 1 to 2 2 to 3 To 0 0 to 1 1 to 2

Ref. Conter # (Row Address #)
n + 1
n + 2 n + 2 n + 3

A bank must be idle before it can be refreshed. The controller must track the bank being refreshed by the per bank REFRESH command.
The REFpb command must not be issued to the device until the following conditions have been met:
· tRFCab has been satisfied after the prior REFab command · tRFCpb has been satisfied after the prior REFpb command · tRP has been satisfied after the prior PRECHARGE command to that bank · tRRD has been satisfied after the prior ACTIVATE command (for example, after acti-
vating a row in a different bank than the one affected by the REFpb command)
The target bank is inaccessible during per bank REFRESH cycle time (tRFCpb). However, other banks within the device are accessible and can be addressed during the cycle. During the REFpb operation, any of the banks other than the one being refreshed can be maintained in an active state or accessed by a READ or a WRITE command. When the per bank REFRESH cycle has completed, the affected bank will be in the idle state.
After issuing REFpb, the following conditions must be met:
· tRFCpb must be satisfied before issuing a REFab command · tRFCpb must be satisfied before issuing an ACTIVATE command to the same bank · tRRD must be satisfied before issuing an ACTIVATE command to a different bank · tRFCpb must be satisfied before issuing another REFpb command
An all-bank REFRESH command (REFab) issues a REFRESH command to every bank in a channel. All banks must be idle when REFab is issued (for example, by issuing a PRECHARGE ALL command prior to issuing an all-bank REFRESH command). The REFab

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

219

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP REFRESH Command

command must not be issued to the device until the following conditions have been met:
· tRFCab has been satisfied following the prior REFab command · tRFCpb has been satisfied following the prior REFpb command · tRP has been satisfied following the prior PRECHARGE command
When an all-bank REFRESH cycle has completed, all banks will be idle. After issuing REFab:
· RFCab latency must be satisfied before issuing an ACTIVATE command, · RFCab latency must be satisfied before issuing a REFab or REFpb command

Table 144: REFRESH Command Timing Constraints

Symbol tRFCab
tRFCpb
tRRD

Minimum Delay From...
REFab
REFpb
REFpb ACTIVATE

To REFab ACTIVATE command to any bank REFpb REFab ACTIVATE command to same bank as REFpb REFpb ACTIVATE command to a different bank than REFpb REFpb ACTIVATE command to a different bank than the prior ACTIVATE command

Notes 1

Note: 1. A bank must be in the idle state before it is refreshed; therefore, REFab is prohibited following an ACTIVATE command. REFpb is supported only if it affects a bank that is in the idle state.

Figure 140: All-Bank REFRESH Operation
T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tc0 Tc1 Tc2 Tc3 CK_c CK_t

CKE

CS

CA Valid Valid

tRPab

Valid Valid

tRFCab

Valid Valid

tRFCab

Valid Valid

Command

PRECHARGE ALL bank

DES

DES

DES

DES

AREllFbRaEnSkH

DES DES DES DES

AREllFbRaEnSkH

DES DES DES DES

Any command

DES

Don't Care

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

220

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP REFRESH Command

Figure 141: Per Bank REFRESH Operation
T0 T1 T2 T3 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1 Tb2 Tb3 Tb4 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 CK_c CK_t
CKE

CS

CA Valid Valid

tRPab

Valid BA0

Valid BA1 tRFCpb

tRFCpb

Valid BA1 Valid Valid

Command

PRECHARGE ALL bank

DES

DES

DES

Per bank REFRESH

DES DES DES

Per bank REFRESH

DES DES DES ACTIVATE-1 ACTIVATE-2 DES DES

Don't Care

Notes:

1. In the beginning of this example, the REFpb bank is pointing to bank 0. 2. Operations to banks other than the bank being refreshed are supported during the
tRFCpb period.

In general, a REFRESH command needs to be issued to the device regularly every tREFI interval. To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight REFRESH commands can be postponed during operation of the device, but at no point in time are more than a total of eight REFRESH commands allowed to be postponed. And a maximum number of pulled-in or postponed REF command is dependent on refresh rate. It is described in the table below. In the case where eight REFRESH commands are postponed in a row, the resulting maximum interval between the surrounding REFRESH commands is limited to 9 × tREFI. A maximum of eight additional REFRESH commands can be issued in advance (pulled in), with each one reducing the number of regular REFRESH commands required later by one. Note that pulling in more than eight REFRESH commands in advance does not reduce the number of regular REFRESH commands required later; therefore, the resulting maximum interval between two surrounding REFRESH commands is limited to 9 × tREFI. At any given time, a maximum of 16 REFRESH commands can be issued within 2 × tREFI.

Self refresh mode may be entered with a maximum of eight REFRESH commands being postponed. After exiting self refresh mode with one or more REFRESH commands postponed, additional REFRESH commands may be postponed to the extent that the total number of postponed REFRESH commands (before and after self refresh) will never exceed eight. During self refresh mode, the number of postponed or pulled-in REFRESH commands does not change.

And for per bank refresh, a maximum of 8 x 8 per bank REFRESH commands can be postponed or pulled in for scheduling efficiency. At any given time, a maximum of 2 x 8 x 8 per bank REFRESH commands can be issued within 2 × tREFI.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

221

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP REFRESH Command

Table 145: Legacy REFRESH Command Timing Constraints

MR4 OP[2:0]
000b 001b 010b 011b 100b 101b 110b 111b

Refresh rate Low temp. limit
4 × tREFI 2 × tREFI 1 × tREFI 0.5 × tREFI 0.25 × tREFI 0.25 × tREFI High temp. limit

Max. No. of pulled-in or postponed REFab
N/A 8 8 8 8 8 8
N/A

Max. Interval between two REFab
N/A 9 × 4 × tREFI 9 × 2 × tREFI
9 × tREFI 9 × 0.5 × tREFI 9 × 0.25 × tREFI 9 × 0.25 × tREFI
N/A

Max. No. of REFab1 N/A 16 16 16 16 16 16 N/A

Per-bank REFRESH N/A
1/8 of REFab 1/8 of REFab 1/8 of REFab 1/8 of REFab 1/8 of REFab 1/8 of REFab
N/A

Note: 1. Maximum number of REFab within MAX(2 × tREFI × refresh rate multiplier, 16 × tRFC).

Table 146: Modified REFRESH Command Timing Constraints

MR4 OP[2:0]
000B 001B 010B 011B 100B 101B 110B 111B

Refresh Rate Low temp. limit
4 × tREFI 2 × tREFI 1 × tREFI 0.5 × tREFI 0.25 × tREFI 0.25 × tREFI High temp. limit

Max. No. of Pulled-in or Postponed REFab
N/A 2 4 8 8 8 8
N/A

Max. Interval between Two REFab
N/A 3 × 4 × tREFI 5 × 2 × tREFI
9 × tREFI 9 × 0.5 × tREFI 9 × 0.25 × tREFI 9 × 0.25 × tREFI
N/A

Max. No. of REFab1 N/A 4 8 16 16 16 16 N/A

Per-bank REFRESH N/A
1/8 of REFab 1/8 of REFab 1/8 of REFab 1/8 of REFab 1/8 of REFab 1/8 of REFab
N/A

Notes:

1. For any thermal transition phase where refresh mode is transitioned to either 2 × tREFI or 4 × tREFI, LPDDR4 devices will support the previous postponed refresh requirement provided the number of postponed refreshes is monotonically reduced to meet the new requirement. However, the pulled-in REFRESH commands in the previous thermal phase are not applied in the new thermal phase. Entering a new thermal phase, the controller must count the number of pulled-in REFRESH commands as zero, regardless of the number of remaining pulled-in REFRESH commands in the previous thermal phase.
2. LPDDR4 devices are refreshed properly if the memory controller issues REFRESH commands with same or shorter refresh period than reported by MR4 OP[2:0]. If a shorter refresh period is applied, the corresponding requirements from this table apply. For example, when MR4 OP[2:0] = 001b, the controller can be in any refresh rate from 4 × tREFI to 0.25 × tREFI. When MR4 OP[2:0] = 010b, the only prohibited refresh rate is 4 × tREFI.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

222

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP REFRESH Command

Figure 142: Postponing REFRESH Commands (Example)

tREFI

9 tREFI

t tRFC

8 REFRESH commands postponed
Figure 143: Pulling in REFRESH Commands (Example) tREFI

tRFC

9 tREFI t

8 REFRESH commands pulled in

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

223

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP REFRESH Command
Burst READ Operation Followed by Per Bank Refresh

Figure 144: Burst READ Operation Followed by Per Bank Refresh
T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tc0 Tc1 Tc2 CK_c CK_t
CS

CA

BL

BA0, CA, AP

CAn

CAn

Valid BA0

Valid

Any Bank

Command

READ-1

DQS_c DQS_t
DQ

CAS-2

DES

DES

Per bank PRECHARGE

DES

DES

DES

DES

DES

t RTP Note 4

t RPpb

RL

t DQSCK

t RPRE

Per bank REFRESH

DES DES DES DES tRPST

tDQSQ
DnO0UT DnO1UT DnO2UT DnO3UT DnO4UT DnO5UT DnO6UT DnO7UT DnO1U2T DnO1U3T DnO1U4T DnO1U5T

Don't Care

Notes:

1. The per bank REFRESH command can be issued after tRTP + tRPpb from READ command.
2. BL = 16; Preamble = Toggle; Postamble = 0.5nCK; DQ/DQS: VSSQ termination. 3. DOUT n = data-out from column n. 4. In the case of BL = 32, delay time from read to per bank precharge is 8nCK + tRTP.
5. DES commands are shown for ease of illustration; other commands may be valid at these times.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

224

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Refresh Requirement

Figure 145: Burst READ With AUTO PRECHARGE Operation Followed by Per Bank Refresh
T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Ta9 Ta10 Tb0 Tb1 Tb2 CK_c CK_t
CS

CA BL CBAA, 0A,P CAn CAn

Valid BAannyk

Command READ with AP-1

CAS-2

DQS_c DQS_t
DQ

DES DES DES DES DES DES DES DES DES

t RC Note 4

RL

t DQSCK

t RPRE

PReErFbRaEnSHk

DES DES DES DES tRPST

t DQSQ
DnO0UT DnO1UT DnO2UT DnO3UT DnO4UT DnO5UT DnO6UT DnO7UT DnO1U2T DnO1U3T DnO1U4T DnO1U5T

Don't Care

Notes:

1. BL = 16; Preamble = Toggle; Postamble = 0.5nCK; DQ/DQS: VSSQ termination. 2. DOUT n = data-out from column n. 3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. tRC needs to be satisfied prior to issuing a subsequent per bank REFRESH command.

Refresh Requirement
Between the SRX command and SRE command, at least one extra REFRESH command is required. After the SELF REFRESH EXIT command, in addition to the normal REFRESH command at tREFI interval, the device requires a minimum of one extra REFRESH command prior to the SELF REFRESH ENTRY command.

Table 147: Refresh Requirement Parameters

Parameter

Number of banks per channel

Refresh window (tREFW): (1 × Refresh)3

Required number of REFRESH commands in tREFW window

Average refresh interval REFab

(1 × Refresh)3

REFpb

Symbol ­
tREFW
R
tREFI tREFIpb

2Gb

3Gb

Density (per channel)

4Gb

6Gb

8Gb

8

32

8192

3.904 488

12Gb

16Gb

Unit ­ ms

­

µs ns

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

225

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP SELF REFRESH Operation

Table 147: Refresh Requirement Parameters (Continued)

Parameter REFRESH cycle time (all banks) REFRESH cycle time (per bank) Per bank refresh to per bank refresh time (different bank)

Symbol tRFCab tRFCpb tPBR2PBR

2Gb 130 60 60

Density (per channel)

3Gb

4Gb

6Gb

8Gb

180

280

90

140

90

90

12Gb 16Gb 380 190 90

Unit ns ns ns

Notes:

1. Refresh for each channel is independent of the other channel on the die, or other channels in a package. Power delivery in the user's system should be verified to make sure the DC operating conditions are maintained when multiple channels are refreshed simultaneously.
2. Self refresh abort feature is available for higher density devices starting with 6Gb density per channel device and tXSR_abort(MIN) is defined as tRFCpb + 17.5ns.
3. Refer to MR4 OP[2:0] for detailed refresh rate and its multipliers.

SELF REFRESH Operation

Self Refresh Entry and Exit
The SELF REFRESH command can be used to retain data in the device without external REFRESH commands. The device has a built-in timer to accommodate SELF REFRESH operation. Self refresh is entered by the SELF REFRESH ENTRY command defined by having CS HIGH, CA0 LOW, CA1 LOW, CA2 LOW, CA3 HIGH, CA4 HIGH, and CA5 valid (valid meaning that it is at a logic level HIGH or LOW) for the first rising edge, and CS LOW, CA0 valid, CA1 valid, CA2 valid, CA3 valid, CA4 valid, and CA5 valid at the second rising edge of clock. The SELF REFRESH command is only allowed when READ DATA burst is completed and the device is in the idle state.
During self refresh mode, external clock input is needed and all input pins of the device are activated. The device can accept the following commands: MRR-1, CAS-2, DES, SRX, MPC, MRW-1, and MRW-2, except PASR bank/segment mask setting and SR abort setting.
The device can operate in self refresh mode within the standard and elevated temperature ranges. It also manages self refresh power consumption when the operating temperature changes: lower at low temperatures and higher at high temperatures.
For proper SELF REFRESH operation, power supply pins (VDD1, VDD2, and VDDQ) must be at valid levels. VDDQ can be turned off during self refresh with power-down after tCKELCK is satisfied. (Refer to the Self Refresh Entry/Exit Timing with Power-Down Entry/Exit figure.) Prior to exiting self refresh with power-down, VDDQ must be within specified limits. The minimum time that the device must remain in self refresh mode is tSR(MIN). After self refresh exit is registered, only MRR-1, CAS-2, DES, MPC, MRW-1, and MRW-2 except PASR bank/segment mask setting and SR abort setting are allowed until tXSR is satisfied.
The use of self refresh mode introduces the possibility that an internally timed refresh event can be missed when self refresh exit is registered. Upon exit from self refresh, it is required that at least one REFRESH command (8 per-bank or 1 all-bank) is issued before entry into a subsequent self refresh. This REFRESH command is not included in the

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

226

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP SELF REFRESH Operation
count of regular REFRESH commands required by the tREFI interval, and does not modify the postponed or pulled-in refresh counts; the REFRESH command does count toward the maximum refreshes permitted within 2 × tREFI.
Figure 146: Self Refresh Entry/Exit Timing
T0 T1 T2 T3 T4 T5 T6 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 CK_c CK_t
CKE
CS

CA

Valid Valid

t SR

Valid Valid

Valid Valid Valid Valid t XSR

Command

DES

SELF REFRESH ENTRY

DES

DES

DES

DES

DES

DES

SELF REFRESH EXIT

DES

DES

DES

DES Any command Any command DES

DES

Enter self refresh

Exit self refresh

Don't Care

Notes:

1. MRR-1, CAS-2, DES, SRX, MPC, MRW-1, and MRW-2 commands (except PASR bank/ segment mask setting and SR abort setting) are allowed during self refresh.
2. DES commands are shown for ease of illustration; other commands may be valid at these times.

Power-Down Entry and Exit During Self Refresh
Entering/exiting power-down mode is allowed during self refresh mode. The related timing parameters between self refresh entry/exit and power-down entry/exit are shown below.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

227

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP SELF REFRESH Operation

Figure 147: Self Refresh Entry/Exit Timing with Power-Down Entry/Exit

T0 T1 T2 T3 Ta0 Tb0 Tb1 Tc0 Td1

CK_c CK_t

Note 2

tCKE

tCKELCK

Te0 Tf0 Tf1 Tg0 Tg1 Th0 Tk0 Tk1 Tk2 Tk3
tCKCKEH

CKE CS

tCSCKE tCKELCS

tESCKE

tCMDCKE

tCSCKEH tCKEHCS tXP

CA Valid Valid Valid Valid

Command

Note 3

MSERLFEWNRTErRFitRYeES-2H

Any command

DES

Enter self refresh

Valid Valid tSR

DES DES

SELF ERXEIFTRESH

DES

Exit self refresh

Don't Care

Notes:

1. MRR-1, CAS-2, DES, SRX, MPC, MRW-1, and MRW-2 commands (except PASR bank/ segment mask setting and SR abort setting) are allowed during self refresh.
2. Input clock frequency can be changed, or the input clock can be stopped, or floated after tCKELCK satisfied and during power-down, provided that upon exiting power-down, the clock is stable and within specified limits for a minimum of tCKCKEH of stable clock prior to power-down exit and the clock frequency is between the minimum and maximum specified frequency for the speed grade in use.
3. Two clock command for example.

Command Input Timing After Power-Down Exit
Command input timings after power-down exit during self refresh mode are shown below.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

228

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP SELF REFRESH Operation

Figure 148: Command Input Timings after Power-Down Exit During Self Refresh

T0 T1 T2 T3 Ta0 Tb0 Tb1 Tc0 Td1

CK_c CK_t

Note 2

tCKE

tCKELCK

Te0 Tf0 Tf1 Tg0 Tg1 Th0 Tk0 Tk1 Tk2 Tk3
tCKCKEH

CKE CS

tCSCKE tCKELCS

tESCKE

tCMDCKE

tCSCKEH tCKEHCS tXP

CA Valid Valid Valid Valid

Command

Note 3

MSERLFEWNRTErRFitRYeES-2H

Any command

DES

Enter self refresh

Valid Valid
tSR Note 3
DES DES Any command DES

Don't Care

Notes:

1. MRR-1, CAS-2, DES, SRX, MPC, MRW-1, and MRW-2 commands (except PASR bank/ segment setting) are allowed during self refresh.
2. Input clock frequency can be changed or the input clock can be stopped or floated after tCKELCK satisfied and during power-down, provided that upon exiting power-down, the clock is stable and within specified limits for a minimum of tCKCKEH of stable clock prior to power-down exit and the clock frequency is between the minimum and maximum specified frequency for the speed grade in use.
3. Two clock command for example.

Self Refresh Abort
If MR4 OP[3] is enabled, the device aborts any ongoing refresh during self refresh exit and does not increment the internal refresh counter. The controller can issue a valid command after a delay of tXSR_abort instead of tXSR.
The value of tXSR_abort(MIN) is defined as tRFCpb + 17.5ns.
Upon exit from self refresh mode, the device requires a minimum of one extra refresh (eight per bank or one for the entire bank) before entering a subsequent self refresh mode. This requirement remains the same irrespective of the setting of the MR bit for self refresh abort.
Self refresh abort feature is valid for 6Gb density per channel and larger densities only.

MRR, MRW, MPC Commands During tXSR, tRFC
MODE REGISTER READ (MRR), MULTI PURPOSE (MPC), and MODE REGISTER WRITE (MRW) command except PASR bank/segment mask setting and SR abort setting can be issued during tXSR period.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

229

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP SELF REFRESH Operation
Figure 149: MRR, MRW, and MPC Commands Issuing Timing During tXSR T0 T1 T2 T3 T4 T5 T6 T7 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5
CK_c CK_t

CKE CS "H" for case 2
CS

CA

Valid Valid Valid Valid

Valid Valid Valid Valid

Valid Valid

tMRD

Note 3

Command DES (Case 1)

SRX

MPC
(2 clock command)

DES

DES

DES

DES

MRW-1

MRW-2 DES DES DES DES Any command

tMRD

Note 3

Command DES (Case 2)

SRX

MPC
(4 clock command)

CAS-2 DES DES

MRW-1

MRW-2 DES DES DES DES Any command

tXSR Note 2

Don't Care

Notes:

1. MPC and MRW commands are shown. Any combination of MRR, MRW, and MPC is allowed during tXSR period.
2. "Any command" includes MRR, MRW, and all MPC commands.

MRR, MRW, and MPC can be issued during tRFC period.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

230

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP SELF REFRESH Operation
Figure 150: MRR, MRW, and MPC Commands Issuing Timing During tRFC T0 T1 T2 T3 T4 T5 T6 T7 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5
CK_c CK_t

CKE CS "H" for case 2
CS

CA

Valid Valid Valid Valid

Valid Valid Valid Valid

Valid Valid

Command (Case 1)

DES

REF all bank

MPC
(2 clock command)

DES

DES

DES

DES

Command (Case 2)

DES

REF all bank

MPC
(4 clock command)

CAS-2 DES DES

MRW-1

MRW-2

tMRD

Note 3

DES DES DES DES Any command

MRW-1

MRW-2

tMRD

Note 3

DES DES DES DES Any command

tRFCab Note 2

Don't Care

Notes:

1. MPC and MRW commands are shown. Any combination of MRR, MRW, and MPC is allowed during tRFCab or tRFCpb period.
2. REFRESH cycle time depends on REFRESH command. In the case of per bank REFRESH command issued, REFRESH cycle time will be tRFCpb.
3. "Any command" includes MRR, MRW, and all MPC commands.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

231

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Power-Down Mode
Power-Down Mode
Power-Down Entry and Exit
Power-down is asynchronously entered when CKE is driven LOW. CKE must not go LOW while the following operations are in progress:
· Mode register read · Mode register write · Read · Write · VREF(CA) range and value setting via MRW · VREF(DQ) range and value setting via MRW · Command bus training mode entering/exiting via MRW · VRCG HIGH current mode entering/exiting via MRW
CKE can go LOW while any other operations such as row activation, precharge, auto precharge, or refresh are in progress. The power-down IDD specification will not be applied until such operations are complete. Power-down entry and exit are shown below.
Entering power-down deactivates the input and output buffers, excluding CKE and RESET_n. To ensure that there is enough time to account for internal delay on the CKE signal path, CS input is required stable LOW level and CA input level is "Don't Care" after CKE is driven LOW, this timing period is defined as tCKELCS. Clock input is required after CKE is driven LOW, this timing period is defined as tCKELCK. CKE LOW will result in deactivation of all input receivers except RESET_n after tCKELCK has expired. In powerdown mode, CKE must be held LOW; all other input signals except RESET_n are "Don't Care." CKE LOW must be maintained until tCKE(MIN) is satisfied.
VDDQ can be turned off during power-down after tCKELCK is satisfied. Prior to exiting power-down, VDDQ must be within its minimum/maximum operating range. No REFRESH operations are performed in power-down mode except self refresh power-down. The maximum duration in non-self-refresh power-down mode is only limited by the refresh requirements outlined in the REFRESH command section.
The power-down state is asynchronously exited when CKE is driven HIGH. CKE HIGH must be maintained until tCKE(MIN) is satisfied. A valid, executable command can be applied with power-down exit latency tXP after CKE goes HIGH. Power-down exit latency is defined in the AC timing parameter table.
Clock frequency change or clock stop is inhibited during tCMDCKE, tCKELCK, tCKCKEH, tXP, tMRWCKEL, and tZQCKE periods.
If power-down occurs when all banks are idle, this mode is referred to as idle powerdown. if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. And If power-down occurs when self refresh is in progress, this mode is referred to as self refresh power-down in which the internal refresh is continuing in the same way as self refresh mode.
When CA, CK, and/or CS ODT is enabled via MR11 OP[6:4] and also via MR22 or CAODT pad setting, the rank providing ODT will continue to terminate the command bus in all DRAM states including power-down when VDDQ is stable and within its minimum/maximum operating range.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

232

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Power-Down Mode
The LPDDR4 DRAM cannot be placed in power-down state during start DQS interval oscillator operation.

Figure 151: Basic Power-Down Entry and Exit Timing

T0 CK_c
CK_t

T1 Ta0 Tb0 Tb1 Tc0 Tc1

Td0 Te0 Te1 Tf0 Tf1 Tg0 Th0 Th1 Th2 Th3 Tk0 Tk1 Tk2

Note 1

t CMDCKE

t CKELCK

tCKE

t CKCKEH

t CKE t XP

CKE t CSCKE t CKELCS
CS

t CSCKEH t CKEHCS

CA Valid Valid

Valid Valid

Command Valid

DES

DES DES Valid DES DES

Don't Care

Note:

1. Input clock frequency can be changed or the input clock can be stopped or floated during power-down, provided that upon exiting power-down, the clock is stable and within specified limits for a minimum of tCKCKEH of stable clock prior to power-down exit and the clock frequency is between the minimum and maximum specified frequency for the speed grade in use.

Current Generator (VRCG)

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

233

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Power-Down Mode
Figure 152: Read and Read with Auto Precharge to Power-Down Entry
T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Tb0 Tb1 Tb2 Tb3 Tc0 Tc1 Tc2 Tc3 Tc4 Td0 Td1 CK_c CK_t

CKE See Note 2
CS

CA Valid Valid Valid Valid

Command READ-1

CAS-2

DES DES DES DES DES DES DES DES DES DES

DQS_c DQS_t
DQ DMI

RL

tDQSCK

tRPRE

DO DO DO DO DO DO n0 n1 n2 n13 n14 n15

tRPST

Don't Care

Notes:

1. CKE must be held HIGH until the end of the burst operation. 2. Minimum delay time from READ command or READ with AUTO PRECHARGE command
to falling edge of CKE signal is as follows:
When read postamble = 0.5nCK (MR1 OP[7] = [0]),
(RL × tCK) + tDQSCK(MAX) + ((BL/2) × tCK) + 1tCK
When read postamble = 1.5nCK (MR1 OP[7] = [1]),
(RL × tCK) + tDQSCK(MAX) + ((BL/2) × tCK) + 2tCK

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

234

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Power-Down Mode
Figure 153: Write and Mask Write to Power-Down Entry
T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Td0 Td1 Td2 CK_c CK_t
CKE See Note 2
CS

CA Valid Valid Valid Valid

Command

WRITE-1 MASK WRITE-1

CAS-2

DES DES DES DES DES DES DES DES DES DES

WL

tDQSS

tWPST

tWPRE

tDQS2DQ BL/2

tWR

DI DI DI DI DI DI n0 n1 n2 n13 n14 n15

Don't Care

Notes:

1. CKE must be held HIGH until the end of the burst operation. 2. Minimum delay time from WRITE command or MASK WRITE command to falling edge
of CKE signal is as follows:
(WL × tCK) + tDQSS(MAX) + tDQS2DQ(MAX) + ((BL/2) × tCK) + tWR 3. This timing is applied regardless of DQ ODT disable/enable setting: MR11 OP[2:0]. 4. This timing diagram only applies to the WRITE and MASK WRITE commands without au-
to precharge.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

235

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Power-Down Mode
Figure 154: Write With Auto Precharge and Mask Write With Auto Precharge to Power-Down Entry
T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Tc3 Tc4 Td0 CK_c CK_t
CKE See Note 2
CS

CA Valid Valid Valid Valid

Command MAWSKRWITREIT-E1-1

CAS-2

DES DES DES DES DES DES DES DES DES DES DES DES DES

WL

tDQSS

tWPST

tWPRE

tDQS2DQ

BL/2

DI DI DI DI DI DI n0 n1 n2 n13 n14 n15

Don't Care

Notes:

1. CKE must be held HIGH until the end of the burst operation.
2. Delay time from WRITE with AUTO PRECHARGE command or MASK WRITE with AUTO PRECHARGE command to falling edge of CKE signal is more than (WL × tCK) + tDQSS(MAX) + tDQS2DQ(MAX) + ((BL/2) × tCK) + (nWR × tCK) + (2 × tCK)
3. This timing is applied regardless of DQ ODT disable/enable setting: MR11 OP[2:0].

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

236

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Power-Down Mode
Figure 155: Refresh Entry to Power-Down Entry
T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 Tb8 Tb9 Tb10 CK_c CK_t

CKE tCMDCKE
CS

CA Valid Valid

Command REFRESH DES DES

Note: 1. CKE must be held HIGH until tCMDCKE is satisfied.

Don't Care

Figure 156: ACTIVATE Command to Power-Down Entry
T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tb2 Tb4 Tb5 Tb6 Tb7 Tb8 Tb9 CK_c CK_t

CKE tCMDCKE
CS

CA Valid Valid Valid Valid

Command ACTIVATE-1 ACTIVATE-2 DES DES
Note: 1. CKE must be held HIGH until tCMDCKE is satisfied.

Don't Care

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

237

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Power-Down Mode
Figure 157: PRECHARGE Command to Power-Down Entry
T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 Tb8 Tb9 Tb10 Tb11 CK_c CK_t

CKE tCMDCKE
CS

CA Valid Valid

Command PRECHARGE DES DES
Note: 1. CKE must be held HIGH until tCMDCKE is satisfied.

Don't Care

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

238

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Power-Down Mode
Figure 158: Mode Register Read to Power-Down Entry
T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Tb0 Tb1 Tb2 Tb3 Tc0 Tc1 Tc2 Tc3 Tc4 Td0 Td1 CK_c CK_t

CKE See Note 2
CS

CA Valid Valid Valid Valid

Command MR READ-1

CAS-2

DQS_c DQS_t
DQ DMI

DES DES DES DES DES DES DES DES DES DES

RL

tDQSCK

tRPRE

DO DO DO DO DO DO n0 n1 n2 n13 n14 n15

tRPST

Don't Care

Notes:

1. CKE must be held HIGH until the end of the burst operation. 2. Minimum delay time from MODE REGISTER READ command to falling edge of CKE sig-
nal is as follows:
When read postamble = 0.5nCK ( MR1 OP[7] = [0]),
(RL × tCK) + tDQSCK(MAX) + ((BL/2) × tCK) + 1tCK
When read postamble = 1.5nCK (MR1 OP[7] = [1]),
(RL × tCK) + tDQSCK(MAX) + ((BL/2) × tCK) + 2tCK

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

239

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Power-Down Mode
Figure 159: Mode Register Write to Power-Down Entry
T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 CK_c CK_t

CKE tMRWCKEL
CS

CA Valid Valid Valid Valid

Command MR WRITE-1 MR WRITE-2 DES DES DES

Don't Care

Notes:

1. CKE must be held HIGH until tMRWCKEL is satisfied.
2. This timing is the general definition for power-down entry after MODE REGISTER WRITE command. When a MODE REGISTER WRITE command changes a parameter or starts an operation that requires special timing longer than tMRWCKEL, that timing must be satisfied before CKE is driven LOW. Changing the VREF(DQ) value is one example, in this case the appropriate tVREF-SHORT/MIDDLE/LONG must be satisfied.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

240

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Power-Down Mode

Figure 160: MULTI PURPOSE Command for ZQCAL Start to Power-Down Entry
T0 T1 T2 Ta0 Ta1 Ta2 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 Tb8 Tb9 Tb10 Tb11 CK_c CK_t
CKE tZQCKE
CS

CA Valid Valid

Command

MPC [ZQCAL START]

DES

DES

ZQ Cal Status

ZQ calibration progresses tZQCAL

Note: 1. ZQ calibration continues if CKE goes LOW after tZQCKE is satisfied.

Don't Care

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

241

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Input Clock Stop and Frequency Change
Input Clock Stop and Frequency Change
Clock Frequency Change ­ CKE LOW
During CKE LOW, the device supports input clock frequency changes under the following conditions:
· tCK(abs)min is met for each clock cycle · Refresh requirements apply during clock frequency change · During clock frequency change, only REFab or REFpb commands may be executing · Any ACTIVATE or PRECHARGE commands have completed prior to changing the fre-
quency · Related timing conditions, tRCD and tRP, have been met prior to changing the fre-
quency · The initial clock frequency must be maintained for a minimum of tCKELCK after CKE
goes LOW · The clock satisfies tCH(abs) and tCL(abs) for a minimum of tCKCKEH prior to CKE go-
ing HIGH
After the input clock frequency changes and CKE is held HIGH, additional MRW commands may be required to set the WR, RL, and so forth. These settings may require adjustment to meet minimum timing requirements at the target clock frequency.
Clock Stop ­ CKE LOW
During CKE LOW, the device supports clock stop under the following conditions:
· CK_t and CK_c are don't care during clock stop · Refresh requirements apply during clock stop · During clock stop, only REFab or REFpb commands may be executing · Any ACTIVATE or PRECHARGE commands have completed prior to stopping the
clock · Related timing conditions, tRCD and tRP, have been met prior to stopping the clock · The initial clock frequency must be maintained for a minimum of tCKELCK after CKE
goes LOW · The clock satisfies tCH(abs) and tCL(abs) for a minimum of tCKCKEH prior to CKE go-
ing HIGH
Clock Frequency Change ­ CKE HIGH
During CKE HIGH, the device supports input clock frequency change under the following conditions:
· tCK(abs)min is met for each clock cycle · Refresh requirements apply during clock frequency change · During clock frequency change, only REFab or REFpb commands may be executing · Any ACTIVATE, READ, WRITE, PRECHARGE, MODE REGISTER WRITE, or MODE
REGISTER READ commands (and any associated data bursts) have completed prior to changing the frequency · Related timing conditions (tRCD, tWR, tRP, tMRW, and tMRR) have been met prior to changing the frequency

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

242

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Input Clock Stop and Frequency Change
· During clock frequency change, CS is held LOW · The device is ready for normal operation after the clock satisfies tCH(abs) and
tCL(abs) for a minimum of 2 × tCK + tXP
After the input clock frequency is changed, additional MRW commands may be required to set the WR, RL, and so forth. These settings may need to be adjusted to meet minimum timing requirements at the target clock frequency.
Clock Stop ­ CKE HIGH
During CKE HIGH, the device supports clock stop under the following conditions:
· CK_t is held LOW and CK_c is held HIGH during clock stop · During clock stop, CS is held LOW · Refresh requirements apply during clock stop · During clock stop, only REFab or REFpb commands may be executing · Any ACTIVATE, READ, WRITE, MPC (WRITE-FIFO, READ-FIFO, READ DQ CALIBRA-
TION), PRECHARGE, MODE REGISTER WRITE, or MODE REGISTER READ commands have completed, including any associated data bursts and extra 4 clock cycles must be provided prior to stopping the clock · Related timing conditions (tRCD, tWR, tRP, tMRW, tMRR, tZQLAT, and so forth) have been met prior to stopping the clock · READ with AUTO PRECHARGE and WRITE with AUTO PRECHARGE commands need extra 4 clock cycles in addition to the related timing constraints, nWR and nRTP, to complete the operations · REFab, REFpb, SRE, SRX, and MPC[ZQCAL START] commands are required to have extra 4 clock cycles prior to stopping the clock · The device is ready for normal operation after the clock is restarted and satisfies tCH(abs) and tCL(abs) for a minimum of 2 × tCK + tXP

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

243

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP MODE REGISTER READ Operation
MODE REGISTER READ Operation
The MODE REGISTER READ (MRR) command is used to read configuration and status data from the device registers. The MRR command is initiated with CS and CA[5:0] in the proper state as defined by the Command Truth Table. The mode register address operands (MA[5:0]) enable the user to select one of 64 registers. The mode register contents are available on the first four UI data bits of DQ[7:0] after RL × tCK + tDQSCK + tDQSQ following the MRR command. Subsequent data bits contain valid but undefined content. DQS is toggled for the duration of the MODE REGISTER READ burst. The MRR has a command burst length of 16. MRR operation must not be interrupted.

Table 148: MRR

UI

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

DQ0

OP0

V

DQ1

OP1

V

DQ2

OP2

V

DQ3

OP3

V

DQ4

OP4

V

DQ5

OP5

V

DQ6

OP6

V

DQ7

OP7

V

DQ8­

V

DQ15

DMI0­

V

DMI1

Notes:

1. MRR data are extended to the first 4 UIs, allowing the LPDRAM controller to sample data easily.
2. DBI during MRR depends on mode register setting MR3 OP[6].
3. The read preamble and postamble of MRR are the same as for a normal read.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

244

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP MODE REGISTER READ Operation

Figure 161: MODE REGISTER READ Operation
T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tc0 Tc1 CK_c CK_t
CS

CA Valid MA CAn CAn

Valid Valid Valid Valid

Command MR READ-1 CAS-2
DQS_c DQS_t DQ7:0

DES DES Any command Any command DES DES DES DES DES DES DES DES DES

tMRR RL

tDQSCK tRPRE

BL/2 = 8

tDQSQ

OP Code out

tRPST
Va- Va- Va- Valid lid lid lid

DQ15:8 DMI1:0

Va- Va- Va- Va- Va- Va- Va- Valid lid lid lid lid lid lid lid

Don't Care

Notes:

1. Only BL = 16 is supported. 2. Only DESELECT is allowed during tMRR period. 3. There are some exceptions about issuing commands after tMRR. Refer to MRR/MRW
Timing Constraints Table for detail.
4. DBI is disable mode. 5. DES commands except tMRR period are shown for ease of illustration; other commands
may be valid at these times.
6. DQ/DQS: VSSQ termination

MRR After a READ and WRITE Command

After a prior READ command, the MRR command must not be issued earlier than BL/2 clock cycles, in a similar way WL + BL/2 + 1 + RU(tWTR/tCK) clock cycles after a PRIOR WRITE, WRITE with AP, MASK WRITE, MASK WRITE with AP, and MPC[WRITE-FIFO] command in order to avoid the collision of READ and WRITE burst data on device internal data bus.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

245

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP MODE REGISTER READ Operation

Figure 162: READ-to-MRR Timing
T0 T1 T2 T3 T4 T15 T16 T17 T18 T19 T20 T21 T33 T34 T35 T36 T37 T43 T44 CK_c CK_t
CS

CA

BL

BA0, CA, AP

CAn

CAn

Valid MA CAn CAn

Command READ-1
DQS_c DQS_t DQ7:0

CAS-2

DES DES

MRR-1

CAS-2

BL/2 RL = 14

tDQSCK tRPRE

DES DES DES DES DES DES DES DES

RL/2 = 14 BL/2 = 16

tDQSCK

BL/2 = 8

tRPST

tDQSQ

tDQSQ
DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n26 n27 n28 n29 n30 n31

OP Code out

Va- Valid lid

DQ15:8 DMI1:0

DOUT n0

DOUT DOUT DOUT n1 n2 n3

DOUT n26

DOUT DOUT DOUT n27 n28 n29

DOUT n30

DOUT n31

Valid

Valid

Valid

Valid

Valid

Valid

Don't Care

Notes:

1. The minimum number of clock cycles from the burst READ command to the MRR command is BL/2.
2. Read BL = 32, MRR BL = 16, RL = 14, Preamble = Toggle, Postamble = 0.5nCK, DBI = Disable, DQ/DQS: VSSQ termination.
3. DOUT n = data-out to column n. 4. DES commands except tMRR period are shown for ease of illustration; other commands
may be valid at these times.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

246

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP MODE REGISTER READ Operation

Figure 163: WRITE-to-MRR Timing
T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 CK_c CK_t
CS

CA

BL

BA0, CA, AP

CAn

CAn

Valid MA CAn CAn

Command WRITE-1

CAS-2

DES DES DES DES DES DES DES DES DES DES MRR-1

WL

BL/2 + 1 clock

tWTR

CAS-2

DES

tMMR

DQS_c DQS_t
DQ DMI

tWPRE

tWPST

tDQS2DQ
DnO0UT DnO1UT DnO1U2T DnO1U3T DnO1U4T DnO1U5T

Don't Care

Notes:

1. Write BL = 16, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination. 2. Only DES is allowed during tMRR period.
3. DOUT n = data-out to column n. 4. The minimum number of clock cycles from the BURST WRITE command to MRR com-
mand is WL + BL/2 + 1 + RU(tWTR/tCK). 5. tWTR starts at the rising edge of CK after the last latching edge of DQS. 6. DES commands except tMRR period are shown for ease of illustration; other commands
may be valid at these times.

MRR After Power-Down Exit
Following the power-down state, an additional time, tMRRI, is required prior to issuing the MODE REGISTER READ (MRR) command. This additional time (equivalent to tRCD) is required in order to maximize power-down current savings by allowing more power-up time for the MRR data path after exit from power-down mode.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

247

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP MODE REGISTER WRITE

Figure 164: MRR Following Power-Down
T0 Ta0 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Td0 Td1 Td2 Td3 Td4 Td5 Td6 Td7 Td8 Td9 CK_c CK_t
tCKCKEH

CKE tXP

tMRRI

tMMR

CS

CA

Valid Valid Valid Valid

Valid MA CAn CAn

Command

DES DES Any command Any command DES DES DES DES MRR-1

CAS-2

DES DES DES

Don't Care

Notes:

1. Only DES is allowed during tMRR period.
2. DES commands except tMRR period are shown for ease of illustration; other commands may be valid at these times.

MODE REGISTER WRITE
The MODE REGISTER WRITE (MRW ) writes configuration data to the mode registers. The MRW command is initiated with CKE, CS, and CA[5:0] to valid levels at the rising edge of the clock. The mode register address and the data written to it is contained in CA[5:0] according to the Command Truth Table. The MRW command period is defined by tMRW. Mode register WRITEs to read-only registers have no impact on the functionality of the device.

Figure 165: MODE REGISTER WRITE Timing
T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Tb0 Tb1 Tb2 Tb3 Tb4
CK_c CK_t

Tb5 Tb6 Tb7

CS

CA OPn MA OPn OPn

OPn MA tMRW

OPn OPn

Valid Valid Valid Valid tMRD

Command MRW-1

MRW-2

DES

DES

MRW-1

MRW-2

DES DES Any command Any command DES DES DES
Don't Care

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

248

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP MODE REGISTER WRITE

Mode Register Write States
MRW can be issued from either a bank-idle or a bank-active state. Certain restrictions may apply for MRW from an active state.

Table 149: Truth Table for MRR and MRW

Current State All banks idle
Bank(s) active

Command MRR MRW MRR MRW

Intermediate State Reading mode register, all banks idle Writing mode register, all banks idle
Reading mode register Writing mode register

Next State All banks idle All banks idle Bank(s) active Bank(s) active

Table 150: MRR/MRW Timing Constraints: DQ ODT is Disable

From Command To Command

MRR

MRR

RD/RDA

WR/WRA/MWR/MWRA

RD/RDA WR/WRA/MWR/ MWRA MRW POWER-DOWN EXIT MRW
RD/ RD-FIFO/ READ DQ CAL RD with AUTO PRECHARGE WR/ MWR/ WR-FIFO WR/MWR with AUTO PRECHARGE

MRW MRR
RD/RDA WR/WRA/MWR/MWRA MRW MRW

Minimum Delay Between "From Command" and "To Command"
tMRR tMRR RL + RU(tDQSCK(MAX)/tCK) + BL/2 -WL + tWPRE + RD(tRPST) RL + RU(tDQSCK(MAX)/tCK) + BL/2 + 3
BL/2 WL + 1 + BL/2 + RU(tWTR/tCK)

Unit ­ ­
nCK
nCK nCK nCK

tMRD

­

tXP + tMRRI

­

tMRD

­

tMRD

­

tMRW

­

RL + BL/2 + RU(tDQSCK(MAX)/tCK) + RD(tRPST) + nCK MAX(RU(7.5ns/tCK), 8nCK)

RL + BL/2 + RU(tDQSCK(MAX)/tCK) + RD(tRPST) + nCK MAX(RU(7.5ns/tCK), 8nCK) + nRTP - 8

WL + 1 + BL/2 + MAX(RU(7.5ns/tCK), 8nCK)

nCK

WL + 1 + BL/2 + MAX(RU(7.5ns/tCK), 8nCK) + nWR nCK

Notes

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

249

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP VREF Current Generator (VRCG)

Table 151: MRR/MRW Timing Constraints: DQ ODT is Enable

From Command To Command

MRR

MRR

RD/RDA

WR/WRA/MWR/MWRA

RD/RDA WR/WRA/MWR/ MWRA MRW POWER-DOWN EXIT MRW
RD/ RD-FIFO/ READ DQ CAL RD with AUTO PRECHARGE WR/ MWR/ WR-FIFO WR/MWR with AUTO PRECHARGE

MRW MRR
RD/RDA WR/WRA/MWR/MWRA MRW MRW

Minimum Delay Between "From Command" and "To Command"
tMRR tMRR RL + RU(tDQSCK(MAX)/tCK) + BL/2 - ODTLon RD(tODTon(MIN)/tCK) + RD(tRPST) + 1 RL + RU(tDQSCK(MAX)/tCK) + BL/2 + 3
BL/2 WL + 1 + BL/2 + RU(tWTR/tCK)

Unit ­ ­
nCK
nCK nCK nCK

tMRD

­

tXP + tMRRI

­

tMRD

­

tMRD

­

tMRW

­

RL + BL/2 + RU(tDQSCK(MAX)/tCK) + RD(tRPST) + nCK MAX(RU(7.5ns/tCK), 8nCK)

RL + BL/2 + RU(tDQSCK(MAX)/tCK) + RD(tRPST) + nCK MAX(RU(7.5ns/tCK), 8nCK) + nRTP - 8

WL + 1 + BL/2 + MAX(RU(7.5ns/tCK), 8nCK)

nCK

WL + 1 + BL/2 + MAX(RU(7.5ns/tCK), 8nCK) + nWR nCK

Notes

VREF Current Generator (VRCG)
LPDDR4 SDRAM VREF current generators (VRCG) incorporate a high current mode to reduce the settling time of the internal VREF(DQ) and VREF(CA) levels during training and when changing frequency set points during operation. The high current mode is enabled by setting MR13[OP3] = 1. Only DESELECT commands may be issued until tVRCG_ENABLE is satisfied. tVRCG_ENABLE timing is shown below.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

250

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP VREF Current Generator (VRCG)
Figure 166: VRCG Enable Timing
T0 T1 T2 T3 T4 T5 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 CK_c CK_t
CKE CS

CA DES MRW1 MRW1 MRW2 MRW2 DES DES Valid Valid Valid Valid DES DES Valid Valid Valid Valid DES DES

Command DES VRCG enable: MR13 [OP3] = 1 DES DES

Valid

t VRCG_ENABLE

DES DES

Valid

DES DES

VRCG high current mode is disabled by setting MR13[OP3] = 0. Only DESELECT commands may be issued until tVRCG_DISABLE is satisfied. tVRCG_DISABLE timing is shown below.

Figure 167: VRCG Disable Timing
T0 T1 T2 T3 T4 T5 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 CK_c CK_t
CKE
CS

CA DES Valid Valid Valid Valid DES DES MRW1 MRW1 MRW2 MRW2 DES DES Valid Valid Valid Valid DES DES

Command DES

Valid

DES DES VRCG disable: MR13 [OP3] = 0 DES DES

Valid

DES DES

t VRCG_DISABLE

Note that LPDDR4 SDRAM devices support VFER(CA) and VREF(DQ) range and value changes without enabling VRCG high current mode.

Table 152: VRCG Enable/Disable Timing

Parameter VREF high current mode enable time VREF high current mode disable time

Symbol tVRCG_ENABLE tVRCG_DISABLE

Min ­ ­

Max 200 100

Unit ns ns

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

251

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP VREF Training

VREF Training

VREF(CA) Training

The device's internal VREF(CA) specification parameters are operating voltage range, step size, VREF step time, VREF full-range step time, and VREF valid level. The voltage operating range specifies the minimum required VREF setting range for LPDDR4 devices. The minimum range is defined by V REF,max and VREF,min.

Figure 168: VREF Operating Range (VREF,max, VREF,min)

VDD2 VIN(DC)max

VREF,max
VREF,min VIN(DC)min

VREF range

VSWING large VSWING small

System variance Total range

The VREF step size is defined as the step size between adjacent steps. However, for a given design, the device has one value for VREF step size that falls within the given range. The VREF set tolerance is the variation in the VREF voltage from the ideal setting. This accounts for accumulated error over multiple steps. There are two ranges for VREF set tolerance uncertainty. The range of VREF set tolerance uncertainty is a function of the number of steps n. The VREF set tolerance is measured with respect to the ideal line that is based on the two endpoints, where the endpoints are at the minimum and maximum VREF values for a specified range.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

252

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP VREF Training
Figure 169: VREF Set-Point Tolerance and Step Size
lVevREeFl

Actuoaul VtpRuEFt

VREF set-point tolerance VREF step size

Straight line endpoint fit

VREF step setting
The VREF increment/decrement step times are defined by tVREF_TIME-SHORT, tVREF_TIME-MIDDLE, and tVREF_TIME-LONG. The parameters are defined from TS to TE as shown below, where TE is referenced to when the VREF voltage is at the final DC level within the VREF valid tolerance (VREF,val_tol). The VREF valid level is defined by VREF,val_tol to qualify the step time TE (see the following figures). This parameter is used to ensure an adequate RC time constant behavior of the voltage level change after any VREF increment/decrement adjustment. This parameter is only applicable for LPDDR4 component level validation/characterization. tVREF_TIME-SHORT is for a single step size increment/decrement change in the VREF voltage. tVREF_TIME-MIDDLE is at least two stepsizes increment/decrement change within the same VREF(CA) range in VREF voltage. tVREF_TIME-LONG is the time including up to VREF,min to VREF,max or VREF,max to VREF,min change across the VREF(CA) range in VREF voltage. TS is referenced to MRW command clock.
TE is referenced to VREF_val_tol.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

253

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP VREF Training
Figure 170: tVref for Short, Middle, and Long Timing Diagram
T0 T1 T2 T3 T4 T5 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Ta9 Ta10 Ta11 Ta12 CK_c CK_t
CKE CS

CA DES MRW-1 MRW-1 MRW-2 MRW-2 DES DES DES DES DES DES DES DES DES DES DES DES DES DES

Command DES

VRFF(CA) value/range set

DES DES DES DES DES DES DES DES DES DES DES DES DES DES
VREF_time ­ short/middle/long

Old VREF setting

TS aVRdEjFussettmtienngt

Updating VRFF(CA) setting

New VREF setting TE

The MRW command to the mode register bits are as follows;

MR12 OP[5:0] : VREF(CA) Setting MR12 OP[6] : VREF(CA) Range The minimum time required between two VREF MRW commands is tVREF_TIME-SHORT for a single step and tVREF_TIME-MIDDLE for a full voltage range step.

Figure 171: VREF(CA) Single-Step Increment

voltVaRgEeF step size

VREF(DC) VREF_val_tol

t1

Time

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

254

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP VREF Training
Figure 172: VREF(CA) Single-Step Decrement

VREF voltage
stepsize

t1 VREF_val_tol
VREF(DC)

Figure 173: VREF(CA) Full Step from VREF,min to VREF,max
VREF VREF,max voltage
Full range step

Time
VREF(DC) VREF_val_tol
t1

VREF,min
Figure 174: VREF(CA) Full Step from VREF,max to VREF,min voltVaRgEeF VREF,max

Time

Full range step
VREF,min

t1
VREF_val_tol VREF(DC)

Time The following table contains the CA internal VREF specification that will be characterized at the component level for compliance.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

255

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP VREF Training

Table 153: Internal VREF(CA) Specifications

Symbol VREF(CA),max_r0
VREF(CA),min_r0
VREF(CA),max_r1
VREF(CA),min_r1
VREF(CA),step VREF(CA),set_tol

Parameter
VREF(CA) range-0 MAX operating point
VREF(CA) range-0 MIN operating point
VREF(CA) range-1 MAX operating point
VREF(CA) range-1 MIN operating point
VREF(CA) step size VREF(CA) set tolerance

tVREF_TIME-SHORT tVREF_TIME-MIDDLE
tVREF_TIME-LONG tVREF_time_weak
VREF(CA)_val_tol

VREF(CA) step time VREF(CA) valid tolerance

Min ­
15.0%
­
32.9%
0.50% ­11 ­1.1 ­ ­ ­ ­
­0.10%

Typ ­
­
­
­
0.60% 0 0 ­ ­ ­ ­
0.00%

Max 44.9%
­
62.9%
­
0.70% 11 1.1 100 200 250 1
0.10%

Unit VDDQ
VDDQ
VDDQ
VDDQ
VDDQ mV mV ns ns ns ms VDDQ

Notes 1, 11
1, 11
1, 11
1, 11
2 3, 4, 6 3, 5, 7
8 12 9 13, 14 10

Notes:

1. VREF(CA) DC voltage referenced to VDDQ(DC). 2. VREF(CA) step size increment/decrement range. VREF(CA) at DC level. 3. VREF(CA),new = VREF(CA),old + n × VREF(CA),step; n = number of steps; if increment, use "+"; if
decrement, use "­".

4. The minimum value of VREF(CA) setting tolerance = VREF(CA),new - 11mV. The maximum value of VREF(CA) setting tolerance = VREF(CA),new + 11mV. For n > 4.
5. The minimum value of VREF(CA) setting tolerance = VREF(CA),new - 1.1mV. The maximum value of VREF(CA) setting tolerance = VREF(CA),new + 1.1mV. For n  4.
6. Measured by recording the minimum and maximum values of the VREF(CA) output over the range, drawing a straight line between those points and comparing all other

VREF(CA) output settings to that line. 7. Measured by recording the minimum and maximum values of the VREF(CA) output across
four consecutive steps (n = 4), drawing a straight line between those points and compar-

ing all other VREF(CA) output settings to that line. 8. Time from MRW command to increment or decrement one step size for VREF(CA) . 9. Time from MRW command to increment or decrement VREF,min to VREF,max or VREF,max to
VREF,min change across the VREF(CA) range in VREF voltage. 10. Only applicable for DRAM component level test/characterization purposes. Not applica-

ble for normal mode of operation. VREF valid is to qualify the step times which will be characterized at the component level.

11. DRAM range-0 or range-1 set by MR12 OP[6].

12. Time from MRW command to increment or decrement more than one step size up to a

full range of VREF voltage within the same VREF(CA) range. 13. Applies when VRCG high current mode is not enabled, specified by MR13 [OP3] = 0b.

14. tVREF_time_weak covers all VREF(CA) range and value change conditions are applied to tVREF_TIME-SHORT/MIDDLE/LONG.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

256

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP VREF Training

VREF(DQ) Training

The device's internal VREF(DQ) specification parameters are operating voltage range, step size, VREF step tolerance, VREF step time and VREF valid level. The voltage operating range specifies the minimum required VREF setting range for LPDDR4 devices. The minimum range is defined by V REF,max and VREF,min.

Figure 175: VREF Operating Range (VREF,max, VREF,min)

VDDQ VIN(DC)max

VREF,max
VREF,min VIN(DC)min

VREF range

VSWING large VSWING small

System variance Total range

The VREF step size is defined as the step size between adjacent steps. However, for a given design, the device has one value for VREF step size that falls within the given range. The VREF set tolerance is the variation in the VREF voltage from the ideal setting. This accounts for accumulated error over multiple steps. There are two ranges for VREF set tolerance uncertainty. The range of VREF set tolerance uncertainty is a function of the number of steps n. The VREF set tolerance is measured with respect to the ideal line that is based on the two endpoints, where the endpoints are at the minimum and maximum VREF values for a specified range.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

257

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP VREF Training
Figure 176: VREF Set Tolerance and Step Size
lVevREeFl

Actuoaul VtpRuEFt

VREF set-point tolerance VREF step size

Straight line endpoint fit

VREF step setting
The VREF increment/decrement step times are defined by tVREF_TIME-SHORT, tVREF_TIME-MIDDLE and tVREF_TIME-LONG. The tVREF_TIME-SHORT, tVREF_TIMEMIDDLE and tVREF_TIME-LONG times are defined from TS to TE in the following figure where TE is referenced to when the V REF voltage is at the final DC level within the VREF valid tolerance (VREF,VAL_TOL). The VREF valid level is defined by VREF,VAL_TOL to qualify the step time TE (see the figure below). This parameter is used to ensure an adequate RC time constant behavior of the voltage level change after any VREF increment/decrement adjustment. This parameter is only applicable for DRAM component level validation/characterization. tVREF_TIME-SHORT is for a single step size increment/decrement change in the VREF voltage. tVREF_TIME-MIDDLE is at least two step sizes of increment/decrement change in the VREF(DQ) range in the VREFvoltage. tVREF_TIME-LONG is the time including and up to the full range of VREF (MIN to MAX or MAX to MIN) across the VREF(DQ) range in VREF voltage.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

258

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP VREF Training

Figure 177: VREF(DQ) Transition Time for Short, Middle, or Long Changes
T0 T1 T2 T3 T4 T5 Ta Ta+1 Ta+2 Ta+3 Ta+4 Ta+5 Ta+6 Ta+7 Ta+8 Ta+9 T+10 T+11 T+12 CK_c CK_t
CKE
CS

CA[5:0] DES MRW-1 MRW-1 MRW-2 MRW-2 DES DES DES DES

DES DES DES DES DES DES DES DES DES DES

Command DES VREF

VREF(DQ) value/range set Old VREF setting

DES DES DES DES

DES DES DES DES DES DES DES DES DES DES

VREF_time ­ short/middle/long

Updating VREF(DQ) setting

New VREF setting

TS

TE

VREF setting adjustment

Notes: 1. TS is referenced to MRW command clock. 2. TE is referenced to VREF,VAL_TOL.
The MRW command to the mode register bits are defined as:

MR14 OP[5:0]: VREF(DQ) setting MR14 OP[6]: VREF(DQ) range The minimum time required between two VREF MRW commands is tVREF_TIME-SHORT for a single step and tVREF_TIME-MIDDLE for a full voltage range step.

Figure 178: VREF(DQ) Single-Step Size Increment

voltVaRgEeF step size

VREF(DC) VREF_val_tol

t1

Time

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

259

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP VREF Training
Figure 179: VREF(DQ) Single-Step Size Decrement

VREF voltage
stepsize

t1 VREF_val_tol
VREF(DC)

Figure 180: VREF(DQ) Full Step from VREF,min to VREF,max
VREF VREF,max voltage
Full range step

Time
VREF(DC) VREF_val_tol
t1

VREF,min
Figure 181: VREF(DQ) Full Step from VREF,max to VREF,min voltVaRgEeF VREF,max

Time

Full range step
VREF,min

t1
VREF_val_tol VREF(DC)

Time The following table contains the DQ internal VREF specification that will be characterized at the component level for compliance.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

260

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP VREF Training

Table 154: Internal VREF(DQ) Specifications

Symbol VREF(DQ),max_r0
VREF(DQ),min_r0
VREF(DQ),max_r1
VREF(DQ),min_r1
VREF(DQ),step VREF(DQ),set_tol

Parameter
VREF MAX operating point Range-0
VREF MIN operating point Range-0
VREF MAX operating point Range-1
VREF MIN operating point Range-1
VREF(DQ) step size VREF(DQ) set tolerance

tVREF_TIME-SHORT tVREF_TIME-MIDDLE tVREF_TIME-LONG
tVREF_time_weak
VREF(DQ),val_tol

VREF(DQ) step time VREF(DQ) valid tolerance

Min ­
15.0%
­
32.9%
0.50% ­11 ­1.1 ­ ­ ­ ­
­0.10%

Typ ­
­
­
­
0.60% 0 0 ­ ­ ­ ­
0.00%

Max 44.9%
­
62.9%
­
0.70% 11 1.1 100 200 250 1
0.10%

Unit VDDQ
VDDQ
VDDQ
VDDQ
VDDQ mV mV ns ns ns ms VDDQ

Notes 1, 11
1, 11
1, 11
1, 11
2 3, 4, 6 3, 5, 7
8 12 9 13, 14 10

Notes:

1. VREF(DQ) DC voltage referenced to VDDQ(DC). 2. VREF(DQ) step size increment/decrement range. VREF(DQ) at DC level. 3. VREF(DQ),new = VREF(DQ),old + n × VREF(DQ),step; n = number of steps; if increment, use "+"; if
decrement, use "­".

4. The minimum value of VREF(DQ) setting tolerance = VREF(DQ),new - 11mV. The maximum value of VREF(DQ) setting tolerance = VREF(DQ),new + 11mV. For n > 4.
5. The minimum value of VREF(DQ)setting tolerance = VREF(DQ),new - 1.1mV. The maximum value of VREF(DQ) setting tolerance = VREF(DQ),new + 1.1mV. For n  4.
6. Measured by recording the minimum and maximum values of the VREF(DQ) output over the range, drawing a straight line between those points and comparing all other

VREF(DQ) output settings to that line. 7. Measured by recording the minimum and maximum values of the VREF(DQ) output across
four consecutive steps (n = 4), drawing a straight line between those points and compar-

ing all other VREF(DQ) output settings to that line. 8. Time from MRW command to increment or decrement one step size for VREF(DQ) . 9. Time from MRW command to increment or decrement VREF,min to VREF,max or VREF,max to
VREF,min change across the VREF(DQ) Range in VREF(DQ) Voltage. 10. Only applicable for DRAM component level test/characterization purposes. Not applica-

ble for normal mode of operation. VREF valid is to qualify the step times which will be characterized at the component level.

11. DRAM range-0 or range-1 set by MR14 OP[6].

12. Time from MRW command to increment or decrement more than one step size up to a

full range of VREF voltage within the same VREF(DQ) range. 13. Applies when VRCG high current mode is not enabled, specified by MR13 [OP3] = 0.

14. tVREF_time_weak covers all VREF(DQ) Range and Value change conditions are applied to tVREF_TIME-SHOR/MIDDLE/LONG.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

261

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Command Bus Training
Command Bus Training
Command Bus Training Mode
The command bus must be trained before enabling termination for high-frequency operation. The device provides an internal V REF(CA) that defaults to a level suitable for unterminated, low-frequency operation, but the VREF(CA) must be trained to achieve suitable receiver voltage margin for terminated, high-frequency operation.
The training mode described here centers the internal VREF(CA) in the CA data eye and at the same time allows for timing adjustments of the CS and CA signals to meet setup/ hold requirements. Because it can be difficult to capture commands prior to training the CA inputs, the training mode described here uses a minimum of external commands to enter, train, and exit the CA bus training mode.
The die has a bond-pad (ODT_CA) but ODT_CA pin is ignored by LPDDR4X devices. CA ODT is fully controlled through MR11 and MR22. See On-Die Termination for more information.
The device uses frequency set points to enable multiple operating settings for the die. The device defaults to FSP-OP[0] at power-up, which has the default settings to operate in un-terminated, low-frequency environments. Prior to training, the termination should be enabled for one die in each channel by setting MR13 OP[6] = 1b (FSP-WR[1]) and setting all other mode register bits for FSP-OP[1] to the desired settings for highfrequency operation. Upon training entry, the device will automatically switch to FSPOP[1] and use the high-frequency settings during training (See the Command Bus Training Entry Timing figure for more information on FSP-OP register sets). Upon training exit, the device will automatically switch back to FSP-OP[0], returning to a "knowngood" state for unterminated, low-frequency operation.
To enter command bus training mode, issue a MRW-1 command followed by a MRW-2 command to set MR13 OP[0] = 1b (command bus training mode enabled).
After time tMRD, CKE may be set LOW, causing the device to switch to FSP-OP[1], and completing the entry into command bus training mode.
A status DQS_t, DQS_c, DQ, and DMI are as noted below; the DQ ODT state will be followed by FREQUENCY SET POINT function except in the case of output pins.
· DQS_t[0], DQS_c[0] become input pins for capturing DQ[6:0] levels by toggling. · DQ[5:0] become input pins for setting VREF(CA) level. · DQ[6] becomes an input pin for setting VREF(CA) range. · DQ[7] and DMI[0] become input pins, and their input level is valid or floating. · DQ[13:8] become output pins to feedback, capturing value via the command bus us-
ing the CS signal. · DQS_t[1], DQS_c[1], DMI[1], and DQ[15:14] become output pins or are disabled,
meaning the device may be driven to a valid level or may be left floating.
At time tCAENT later, the device may change its VREF(CA) range and value using input signals DQS_t[0], DQS_c[0], and DQ[6:0] from existing value that is set via MR12 OP[6:0]. The mapping between MR12 OP code and DQs is shown below. At least one VREF(CA) setting is required before proceeding to the next training step.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

262

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Command Bus Training

Table 155: Mapping MR12 Op Code and DQ Numbers

MR12 OP code DQ number

OP6 DQ6

OP5 DQ5

OP4 DQ4

Mapping OP3 DQ3

OP2 DQ2

OP1 DQ1

OP0 DQ0

The new VREF(CA) value must "settle" for time tVREFCA_Long before attempting to latch CA information.
Note: If DQ ODT is enabled in MR11-OP[2:0], then the SDRAM will terminate the DQ lanes during command bus training when entering VREF(CA) range and values on DQ[6:0].
To verify that the receiver has the correct VREF(CA) setting, and to further train the CA eye relative to clock (CK), values latched at the receiver on the CA bus are asynchronously output to the DQ bus.
To exit command bus training mode, drive CKE HIGH, and after time tVREFCA_Long, issue the MRW-1 command followed by the MRW-2 command to set MR13 OP[0] = 0b. After time tMRW, the device is ready for normal operation. After training exit, the device will automatically switch back to the FSP-OP registers that were in use prior to training.
Command bus training (CBT) may be executed from the idle or self refresh state. When executing CBT within the self refresh state, the device must not be in a power-down state (for example, CKE must be HIGH prior to training entry). CBT entry and exit is the same, regardless of the state from which CBT is initiated.

Training Sequence for Single-Rank Systems
The sequence example shown here assumes an initial low-frequency, non-terminating operating point training a high-frequency, terminating operating point. The bold text shows high-frequency instructions. Any operating point may be trained from any known good operating point.
1. Set MR13 OP[6] = 1b to enable writing to frequency set point 1 (FSP-WR[1]) (or FSP-OP[0]).
2. Write FSP-WR[1] (or FSP-WR[0]) registers for all channels to set up high-frequency operating parameters.
3. Issue MRW-1 and MRW-2 commands to enter command bus training mode. 4. Drive CKE LOW, and change CK frequency to the high-frequency operating
point. 5. Perform command bus training (VREF(CA), CS, and CA). 6. Exit training by driving CKE HIGH, change CK frequency to the low-frequency
operating point, and issue MRW-1 and MRW-2 commands. When CKE is driven HIGH, the device will automatically switch back to the FSP-OP registers that were in use prior to training (trained values are not retained). 7. Write the trained values to FSP-WR[1] (or FSP-WR[0]) by issuing MRW-1 and MRW-2 commands to the SDRAM and setting all applicable mode register parameters. 8. Issue MRW-1 and MRW-2 commands to switch the terminating rank to FSP-OP[1] (or FSP-OP[0]), to turn on termination, and change CK frequency to the high-frequency operating point. At this point the command bus is trained and you may proceed to other training or normal operation.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

263

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Command Bus Training
Training Sequence for Multiple-Rank Systems
The sequence example shown here is assuming an initial low-frequency operating point, training a high-frequency operating point. The bold text shows high-frequency instructions. Any operating point may be trained from any known good operating point.
1. Set MR13 OP[6] = 1b to enable writing to frequency set point 1 (FSP-WR[1]) (or FSP-WR[0]).
2. Write FSP-WR[1] (or FSP-WR[0]) registers for all channels and ranks to set up high-frequency operating parameters.
3. Read MR0 OP[7] on all channels and ranks to determine which die are terminating, signified by MR0 OP[7] = 1b.
4. Issue MRW-1 and MRW-2 commands to enter command bus training mode on the terminating rank.
5. Drive CKE LOW on the terminating rank (or all ranks), and change CK frequency to the high-frequency operating point.
6. Perform command bus training on the terminating rank (VREF(CA), CS, and CA). 7. Exit training by driving CKE HIGH, change CK frequency to the low-frequency
operating point, and issue MRW-1 and MRW-2 commands to write the trained values to FSP-WR[1] (or FSP-WR[0]). When CKE is driven HIGH, the SDRAM will automatically switch back to the FSP-OP registers that were in use prior to training (trained values are not retained by the device). 8. Issue MRW-1 and MRW-2 commands to enter training mode on the non-terminating rank (but keep CKE HIGH). 9. Issue MRW-1 and MRW-2 commands to switch the terminating rank to FSP-OP[1] (or FSP-OP[0]), to turn on termination, and change CK frequency to the high-frequency operating point. 10. Drive CKE LOW on the non-terminating (or all) ranks. The non-terminating rank(s) will now be using FSP-OP[1] (or FSP-OP[0]). 11. Perform command bus training on the non-terminating rank (VREF(CA), CS, and CA). 12. Issue MRW-1 and MRW-2 commands to switch the terminating rank to FSPOP[0] (or FSP-OP[1]) to turn off termination. 13. Exit training by driving CKE HIGH on the non-terminating rank, change CK frequency to the low-frequency operating point, and issue MRW-1 and MRW-2 commands. When CKE is driven HIGH, the device will automatically switch back to the FSP-OP registers that were in use prior to training (that is, trained values are not retained by the device). 14. Write the trained values to FSP-WR[1] (or FSP-WR[0]) by issuing MRW-1 and MRW-2 commands and setting all applicable mode register parameters. 15. Issue MRW-1 and MRW-2 commands to switch the terminating rank to FSP-OP[1] (or FSP-OP[0]), to turn on termination, and change CK frequency to the high-frequency operating point. At this point the command bus is trained for both ranks and the user may proceed to other training or normal operation.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

264

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Command Bus Training
Relation Between CA Input Pin and DQ Output Pin

Table 156: Mapping CA Input Pin and DQ Output Pin

CA number DQ number

CA5 DQ13

CA4 DQ12

Mapping

CA3

CA2

DQ11

DQ10

CA1 DQ9

CA0 DQ8

Figure 182: Command Bus Training Mode Entry ­ CA Training Pattern I/O with VREF(CA) Value Update

T0

T1

T2

T3

T4

T5

Ta

Tb

Tb+1

Tc See Note 1

CK_c

CK_t

CKE

tMRD

See Note 7 tCKELCK See Note 3

Td Te Te+1 Te+2 Tf Tg Th Th+1 Th+2

tCKPRECS

tCKPSTCS See Note 2

tCACD

CS

CA DES

MRW1

MRW1

MRW2

MRW2

DES

DES

DES

DES

DES

Valid

Command DES
DQS0_t DQS0_c DQ[6:0]

Enter command bus training mode

DES

DES

DES

DES

DES

tDQSCKE

tCAENT

See Note 4

tVREFCA_Long (see Note 5)

CA training pattern A

tDS,train

Valid

tDH,train

tADR

Valid CA training pattern B

DQ7 DMI0
DQ[13:8]
DQ[15:14] DMI1
DQS1_t DQS1_c (refVeRreEFn(cCeA))
ODT_CA (reference)

Pattern A

Setting value of MR X (Y) Mode register X (Y)

Updating setting from FSP switching tCKELODTon (see Note 6)
Switching MR

Updating setting Mode register X (Y)

Temporary setting value

Don't Care

Notes:

1. After tCKELCK, the clock can be stopped or the frequency changed any time.
2. The input clock condition should be satisfied tCKPRECS and tCKPSTCS.
3. Continue to drive CK, and hold CA and CS LOW, until tCKELCK after CKE is LOW (which disables command decoding).
4. The device may or may not capture the first rising edge of DQS_t/DQS_c due to an unstable first rising edge. Therefore, at least two consecutive pulses of DQS signal input is required every for DQS input signal while capturing DQ[6:0] signals. The captured value of the DQ[6:0] signal level by each DQS edge may be overwritten at any time and the device will temporarily update the VREF(CA) setting of MR12 after time tVREFCA_Long.
5. tVREFCA_Long may be reduced to tVREFCA_Short if the following conditions are met: 1) The new VREF setting is a single step above or below the old VREF setting; 2) The DQS pulses a single time, or the new VREF setting value on DQ[6:0] is static and meets tDS,train/ tDH,train for every DQS pulse applied.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

265

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Command Bus Training

6. When CKE is driven LOW, the device will switch its FSP-OP registers to use the alternate (non-active) set. For example, if the device is currently using FSP-OP[0], then it will switch to FSP-OP[1] when CKE is driven LOW. All operating parameters should be written to the alternate mode registers before entering command bus training to ensure that ODT settings, RL/WL/nWR setting, and so forth, are set to the correct values.
7. When CKE is driven LOW in command bus training mode, the device will change operation to the alternate FSP, that is, the inverse of the FSP programmed in the FSP-OP mode register.

Figure 183: Consecutive VREF(CA) Value Update

T0

Ta

Tb

Tb+1

Tc See Note 1

CK_c

CK_t

CKE

See Note 7

tCKELCK (see Note 3)
CS

Td Te Te+1 Te+2 Te+3 Te+4 Te+5 Te+6 Te+7 Te+8 Te+9 Te+10 Tf Tf+1 Tf+2 Tf+3 tCKELCK (see Note 2)

CA DES

DES

DES

DES

DES

Valid

Command DES

DES

DES

DES

DES

tDQSCKE

tCAENT

See Note 4

CA training pattern A

tVREFCA_Long (see Note 5)

tCS_VREF

See Note 4

tVREFCA_Long (see Note 5)

DQS0_t DQS0_c

tDS,train

tDH,train

tDS,train

tDH,train

DQ[6:0]

Valid

Valid

DQ7 DMI0

DQ[13:8]
DQ[15:14] DMI1
DQS1_t DQS1_c (refVeRreEFn(cCeA))
ODT_CA (reference)

Setting value of MR X (Y)

Updating setting from FSP switching

tCKELODTon (see Note 6)

Mode register X (Y)

Switching MR

Updating setting Mode register X (Y)

tADR

Temporary setting value

Updating setting

Pattern A

Don't Care

Notes:

1. After tCKELCK, the clock can be stopped or the frequency changed any time.
2. The input clock condition should be satisfied tCKPRECS and tCKPSTCS.
3. Continue to drive CK, and hold CA and CS LOW, until tCKELCK after CKE is LOW (which disables command decoding).
4. The device may or may not capture the first rising edge of DQS_t/DQS_c due to an unstable first rising edge. Therefore, at least two consecutive pulses of DQS signal input is required every for DQS input signal while capturing DQ[6:0] signals. The captured value of the DQ[6:0] signal level by each DQS edge may be overwritten at any time and the device will temporarily update the VREF(CA) setting of MR12 after time tVREFCA_Long.
5. tVREFCA_Long may be reduced to tVREFCA_Short if the following conditions are met: 1) The new VREF setting is a single step above or below the old VREF setting; 2) The DQS

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

266

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Command Bus Training

pulses a single time, or the new VREF setting value on DQ[6:0] is static and meets tDS,train/ tDH,train for every DQS pulse applied.
6. When CKE is driven LOW, the device will switch its FSP-OP registers to use the alternate (non-active) set. For example, if the device is currently using FSP-OP[0], then it will switch to FSP-OP[1] when CKE is driven LOW. All operating parameters should be written to the alternate mode registers before entering command bus training to ensure that ODT settings, RL/WL/nWR setting, and so forth, are set to the correct values.
7. When CKE is driven LOW in command bus training mode, the device will change operation to the alternate FSP, that is, the inverse of the FSP programmed in the FSP-OP mode register.

Figure 184: Command Bus Training Mode Exit with Valid Command

T0 T1 T2 Ta0 Ta1 Ta2 Tb0 CK_c

CK_t

tCKPSTCS

CKE

tCACD

CS

Tc0

Td0 Td1 Te0

Te1

Tf0

Tf1

Tf2

Tf3

Tf4

Tg0 Tg1 Tg2 Tg3 Tg4 Tg5

Note 5 tCKCKEH Note 1

tXCBT

tMRW

CA
Command
DQS_t[0] DQS_c[0]
DQ[6:0]
DQ[7] DMI[0]
DQ[13:8] DQ[15:14]
DMI[1] DQS_t[1] DQS_c[1]
VREF(CA) (Reference)
ODT_CA (Reference)

Valid
patCteArn B tADR

Valid
patCteArn C tADR

MRW-1 MRW-1 MRW-2 MRW-2

Valid Valid Valid Valid

Note 2

DES

DES

DES

DES

DES

DES

Exiting command bus training mode

DES

Valid

DES

tCKEHDQS

Pattern A

Pattern B

tMRZ Pattern C

Temporary setting value Mode register Y (X)

Note 4

Switching MR

tCKELODToff Note 3

Switching MR

Setting value of MR X (Y) Mode register X (Y)

Don't Care

Notes:

1. The clock can be stopped or the frequency changed any time before tCKCKEH. CK must meet tCKCKEH before CKE is driven HIGH. When CKE is driven HIGH, the clock frequency must be returned to the original frequency (that is, the frequency corresponding to the FSP at command bus training mode entry.
2. CS and CA[5:0] must be deselected (LOW) tCKCKEH before CKE is driven HIGH.
3. When CKE is driven HIGH, ODT_CA will revert to the state/value defined by FSP-OP prior to command bus training mode entry, that is, the original frequency set point (FSP-OP, MR13-OP[7]). For example, if the device was using FSP-OP[1] for training, then it will switch to FSP-OP[0] when CKE is driven HIGH.
4. Training values are not retained by the device and must be written to the FSP-OP register set before returning to operation at the trained frequency. For example, VREF(CA) will return to the value programmed in the original set point.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

267

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Command Bus Training

5. When CKE is driven HIGH, the device will revert to the FSP in operation at command bus training mode entry.

Figure 185: Command Bus Training Mode Exit with Power-Down Entry

T0 T1 T2 Ta0 Ta1 Ta2 Tb0 CK_c

CK_t

tCKPSTCS

CKE

tCACD

Tc0

Td0 Td1 Te0

Te1

Tf0

Tf1

Tf2

Tf3

Tf4

Tg0 Tg1 Tg2 Tg3 Th0 Tk1

Note 5 tCKCKEH Note 1

tXCBT

tMRD

tCKELCK tCKELCMD

CS

CA
Command
DQS_t[0] DQS_c[0]
DQ[6:0]
DQ[7] DMI[0]
DQ[13:8] DQ[15:14]
DMI[1] DQS_t[1] DQS_c[1]
VREF(CA) (Reference)
ODT_CA (Reference)

Valid
CA pattern B
tADR

Valid
CA pattern C
tADR

MRW-1 MRW-1 MRW-2 MRW-2

Valid Valid

Note 2

DES

DES

DES

DES

DES

DES

Exiting command bus training mode

DES

POWER-DOWN ENTRY

DES

DES

tCKEHDQS

Pattern A

Pattern B

tMRZ Pattern C

Temporary setting value Mode register Y (X)

Note 4 Switching MR
tCKELODToff Note 3
Switching MR

Setting value of MR X (Y) Mode register X (Y)

Don't Care

Notes:

1. The clock can be stopped or the frequency changed any time before tCKCKEH. CK must meet tCKCKEH before CKE is driven HIGH. When CKE is driven HIGH, the clock frequency must be returned to the original frequency (that is, the frequency corresponding to the FSP at command bus training mode entry.
2. CS and CA[5:0] must be deselected (LOW) tCKCKEH before CKE is driven HIGH.
3. When CKE is driven HIGH, ODT_CA will revert to the state/value defined by FSP-OP prior to command bus training mode entry, that is, the original frequency set point (FSP-OP, MR13-OP[7]). For example, if the device was using FSP-OP[1] for training, then it will switch to FSP-OP[0] when CKE is driven HIGH.
4. Training values are not retained by the device and must be written to the FSP-OP register set before returning to operation at the trained frequency. For example, VREF(CA) will return to the value programmed in the original set point.
5. When CKE is driven HIGH, the device will revert to the FSP in operation at command bus training mode entry.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

268

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Write Leveling
Write Leveling
Mode Register Write-WR Leveling Mode
To improve signal-integrity performance, the device provides a write leveling feature to compensate for CK-to-DQS timing skew, affecting timing parameters such as tDQSS, tDSS, and tDSH. The memory controller uses the write leveling feature to receive feedback from the device, enabling it to adjust the clock-to-data strobe signal relationship for each DQS_t/DQS_c signal pair. The device samples the clock state with the rising edge of DQS signals and asynchronously feeds back to the memory controller. The memory controller references this feedback to adjust the clock-to-data strobe signal relationship for each DQS_t/DQS_c signal pair.
All data bits (DQ[7:0] for DQS[0] and DQ[15:8] for DQS[1]) carry the training feedback to the controller. Both DQS signals in each channel must be leveled independently. Write leveling entry/exit is independent between channels for dual-channel devices.
The device enters write leveling mode when mode register MR2-OP[7] is set HIGH. When entering write leveling mode, the state of the DQ pins is undefined. During write leveling mode, only DESELECT commands, or a MRW command to exit the WRITE LEVELING operation, are allowed. Depending on the absolute values of tQSL and tQSH in the application, the value of tDQSS may have to be better than the limits provided in the AC Timing Parameters section in order to satisfy the tDSS and tDSH specifications. Upon completion of the WRITE LEVELING operation, the device exits write leveling mode when MR2-OP[7] is reset LOW.
Write leveling should be performed before write training (DQS2DQ training).
Write Leveling Procedure
1. Enter write leveling mode by setting MR2-OP[7]=1. 2. Once in write leveling mode, DQS_t must be driven LOW and DQS_c HIGH after a
delay of tWLDQSEN. 3. Wait for a time tWLDQSEN before providing the first DQS signal input. The delay
time tWLMRD(MAX) is controller-dependent. 4. The device may or may not capture the first rising edge of DQS_t due to an unsta-
ble first rising edge; therefore, at least two consecutive pulses of DQS signal input is required for every DQS input signal during write training mode. The captured clock level for each DQS edge is overwritten, and the device provides asynchronous feedback on all DQ bits after time tWLO. 5. The feedback provided by the device is referenced by the controller to increment or decrement the DQS_t and/or DQS_c delay settings. 6. Repeat steps 4 and 5 until the proper DQS_t/DQS_c delay is established. 7. Exit write leveling mode by setting MR2-OP[7] = 0.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

269

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Write Leveling

Figure 186: Write Leveling Timing ­ tDQSL(MAX)

T0 T1 T2 T3 T4 Ta Ta1 Tb Tb1 Tc Tc1 CK_c CK_t

Td Td1 Td2 Td3 Te Te1 Tf Tf1 Tf2 Tf3 Tf4 Tg Tg1 Tg2 Tg3 Tg4

CA[5:0]

MRW MRW MRW MRW

MA

MA

OP

OP

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES DES

MRW MRW MRW MRW

MA MA OP

OP

DES

DES Valid Valid Valid Valid

Command

MRW-1

MRW-2

WR LEVELING WR LEVELING

DES

DES

DES

DES

DES

tWLDQSEN

tWLWPRE

tDQSH

tDQSL

DQS_c DQS_t

tWLMRD

tWLO

tWLO

DQ[15:0] DMI[1:0]

DES

DES

MRW-1 WR

MRW-2 WR

LEVELING exit LEVELING exit

DES

Valid

Valid

tWLO tWLO

tMRD

Don't Care
Note: 1. Clock can be stopped except during DQS toggle period (CK_t = LOW, CK_c = HIGH). However, a stable clock prior to sampling is required to ensure timing accuracy.

Figure 187: Write Leveling Timing ­ tDQSL(MIN)
T0 T1 T2 T3 T4 Ta Ta1 Tb Tb1 Tc Tc1 CK_c CK_t

Td Td1 Td2 Td3 Te Te1 Tf Tf1 Tf2 Tf3 Tf4 Tg Tg1 Tg2 Tg3

CA[5:0]

MRW MRW MRW MRW

MA

MA

OP

OP

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES

DES DES

MRW MRW MRW MRW

MA MA OP

OP

DES

DES Valid Valid Valid Valid

Command

MRW-1

MRW-2

WR LEVELING WR LEVELING

DES

DES

DQS_c DQS_t

tWLDQSEN tWLWPRE tWLMRD

DQ[15:0] DMI[1:0]

DES

DES

tDQSH

tWLO tWLO

DES

DES

DES

MRW1 WR

MRW-2 WR

LEVELING exit LEVELING exit

DES

tDQSL

Valid

Valid

tWLO

tMRD

Don't Care
Note: 1. Clock can be stopped except during DQS toggle period (CK_t = LOW, CK_c = HIGH). However, a stable clock prior to sampling is required to ensure timing accuracy.

Input Clock Frequency Stop and Change
The input clock frequency can be stopped or changed from one stable clock rate to another stable clock rate during write leveling mode. The frequency stop or change timing is shown below.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

270

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Write Leveling

Figure 188: Clock Stop and Timing During Write Leveling
T0 T1 T2 T3 T4 Ta0 Ta1 Tb0 Tb1 Tb2 Tc0 CK_c CK_t
t CKPSTDQS
CS

CKE

CA

MRW MRW MRW MRW

MA MA OP

OP

DES

DES

DES

DES

DES

DES

DES

Td0 Te0 Te1 Te2 Te3 Te4 Tf0 Tf1 Tf2 Tf3 t CKPRDQS

DES DES

DES DES DES DES DES

DES DES DES

Command
DQS_t DQS_c

MRW-1 WR LEVELING

MRW-2 WR LEVELING

DESELECT

DESELECT

t WLDQSEN

t WLWPRE

t WLMRD

DQ DMI

DESELECT t DQSH
t WLO t WLO

t DQSL

DESELECT

DESELECT

Notes: 1. CK_t is held LOW and CK_c is held HIGH during clock stop. 2. CS will be held LOW during clock stop.

DESELECT

DESELECT

t WLO

t WLO

DESELECT Don't Care

Table 157: Write Leveling Timing Parameters

Parameter DQS_t/DQS_c delay after write leveling mode is programmed
Write preamble for write leveling

Symbol tWLDQSEN
tWLWPRE

First DQS_t/DQS_c edge after write leveling mode is programmed
Write leveling output delay

tWLMRD tWLO

MODE REGISTER SET command delay Valid clock requirement before DQS toggle

tMRD tCKPRDQS

Valid clock requirement after DQS toggle

tCKPSTDQS

Min/Max

Value

Units

MIN

20

tCK

MAX

­

MIN

20

tCK

MAX

­

MIN

40

tCK

MAX

­

MIN

0

ns

MAX

20

Refer to Mode Register Timing Parameter Table

MIN

MAX(7.5ns, 4nCK)

­

MAX

­

MIN

MAX(7.5ns, 4nCK)

­

MAX

­

Table 158: Write Leveling Setup and Hold Timing

Parameter Write leveling hold time Write leveling setup time

Symbol tWLH tWLS

Min/Max MIN MIN

1600 150 150

2400 100 100

Data Rate 3200 75 75

3733 62.5 62.5

4267 50 50

Unit ps ps

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

271

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Write Leveling

Table 158: Write Leveling Setup and Hold Timing (Continued)

Parameter
Write leveling input valid window

Symbol tWLIVW

Min/Max MIN

1600 240

2400 160

Data Rate 3200 120

3733 105

4267 90

Unit ps

Notes:

1. In addition to the traditional setup and hold time specifications, there is value in a invalid window-based specification for write leveling training. As the training is based on each device, worst-case process skews for setup and hold do not make sense to close timing between CK and DQS.
2. tWLIVW is defined in a similar manner to TdIVW_total, except that here it is a DQS invalid window with respect to CK. This would need to account for all voltage and temperature (VT) drift terms between CK and DQS within the device that affect the write leveling invalid window.

The figure below shows the DQS input mask for timing with respect to CK. The "total" mask (tWLIVW) defines the time the input signal must not encroach in order for the DQS input to be successfully captured by CK. The mask is a receiver property and it is not the valid data-eye.

Figure 189: DQS_t/DQS_c to CK_t/CK_c Timings at the Pins Referenced from the Internal Latch

Internal composite DQS eye center aligned to CK
CK_c

CK_t

DQ_diff = DQS_t­DQS_c

tWLIVW

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

272

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP MULTIPURPOSE Operation
MULTIPURPOSE Operation
The device uses the MULTIPURPOSE command to issue a NO OPERATION (NOP) command and to access various training modes. The MPC command is initiated with CS, and CA[5:0] asserted to the proper state at the rising edge of CK, as defined by the Command Truth Table. The MPC command has seven operands (OP[6:0]) that are decoded to execute specific commands in the SDRAM. OP[6] is a special bit that is decoded on the first rising CK edge of the MPC command. When OP[6] = 0, the device executes a NOP command, and when OP[6] = 1, the device further decodes one of several training commands.
When OP[6] = 1 and the training command includes a READ or WRITE operation, the MPC command must be followed immediately by a CAS-2 command. For training commands that read or write, READ latency (RL) and WRITE latency (WL) are counted from the second rising CK edge of the CAS-2 command with the same timing relationship as a typical READ or WRITE command. The operands of the CAS-2 command following a MPC READ/WRITE command must be driven LOW. The following MPC commands must be followed by a CAS-2 command:
· WRITE-FIFO · READ-FIFO · READ DQ CALIBRATION
All other MPC commands do not require a CAS-2 command, including the following:
· NOP · START DQS INTERVAL OSCILLATOR · STOP DQS INTERVAL OSCILLATOR · ZQCAL START (ZQ CALIBRATION START) · ZQCAL LATCH (ZQ CALIBRATION LATCH)

Table 159: MPC Command Definition

SDR Command
MPC (Train, NOP)

SDR Command Pins

CKE

CK_t (n-1) CK_t(n) CS

H

H

H

L

CA0 L
OP0

CA1 L
OP1

SDR CA Pins

CA2 L
OP2

CA3 L
OP3

CA4 L
OP4

CA5 OP6 OP5

CK_t Edge
1
2

Notes 1, 2

Notes:

1. See the Command Truth Table for more information.
2. MPC commands for READ or WRITE TRAINING operations must be immediately followed by the CAS-2 command, consecutively, without any other commands in between. The MPC command must be issued before issuing the CAS-2 command.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

273

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP MULTIPURPOSE Operation

Table 160: MPC Commands

Function Training Modes

Operand OP[6:0]

Data 0XXXXXXb: NOP 1000001b: READ-FIFO: READ-FIFO supports only BL16 operation 1000011b: READ DQ CALIBRATION (MR32/MR40) 1000101b: RFU 1000111b: WRITE-FIFO: WRITE-FIFO supports only BL16 operation 1001001b: RFU 1001011b: START DQS OSCILLATOR 1001101b: STOP DQS OSCILLATOR 1001111b: ZQCAL START 1010001b: ZQCAL LATCH All Others: Reserved

Notes:

1. See command truth table for more information.
2. MPC commands for READ or WRITE TRAINING operations must be immediately followed by CAS-2 command consecutively without any other commands in-between. MPC command must be issued first before issuing the CAS-2 command.
3. WRITE-FIFO and READ-FIFO commands will only operate as BL16, ignoring the burst length selected by MR1 OP[1:0].

Figure 190: WRITE-FIFO ­ tWPRE = 2nCK, tWPST = 0.5nCK

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Tb0 Tb1 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Td0 Td1 Td2 Td3 Td4 Td5 Te0 Te1 Te2 Tf0 Tf1 Tg0 Tg1 Tg2 Tg3 CK_c
CK_t

CS

CA BL

BA0, CA

CAn

CAn

Valid Valid Valid Valid

Valid Valid Valid Valid

Command WRITE-1
DQS_c DQS_t DQ[15:0] DMI[1:0]

CAS-2

DES DES DES DES DES

WL t WPRE

t WRWTR tDQSS

DES

DES

MPC [WRITE-FIFO]

t WPST

CAS-2

DES

DES

MPC [WRITE-FIFO]

tCCD = 8 WL

CAS-2

DES DES DES DES DES DES DES DES DES DES

WL WPRE

tDQSS

tDQSS

t WPST

tDQS2DQ n0 n13 n14 n15

tDQS2DQ

tDQS2DQ

n0 n13 n14 n15 n0 n13 n14 n15

Don't Care

Notes:

1. MPC[WRITE-FIFO] can be executed with a single bank or multiple banks active, during refresh or during self refresh, with CKE HIGH.
2. Write-1 to MPC is shown as an example of command-to-command timing for MPC. Timing from Write-1 to MPC[WRITE-FIFO] is tWRWTR.
3. Seamless MPC[WRITE-FIFO] commands may be executed by repeating the command every tCCD time.
4. MPC[WRITE-FIFO] uses the same command-to-data timing relationship (WL, tDQSS, tDQS2DQ) as a WRITE-1 command.
5. A maximum of five MPC[WRITE-FIFO] commands may be executed consecutively without corrupting FIFO data. The sixth MPC[WRITE-FIFO] command will overwrite the FIFO data

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

274

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP MULTIPURPOSE Operation

from the first command. If fewer than five MPC[WRITE-FIFO] commands are executed, then the remaining FIFO locations will contain undefined data.
6. For the CAS-2 command following an MPC command, the CAS-2 operands must be driven LOW.
7. To avoid corrupting the FIFO contents, MPC[READ-FIFO] must immediately follow MPC[WRITE-FIFO]/CAS-2 without any other commands in-between. See Write Training section for more information on FIFO pointer behavior.

Figure 191: READ-FIFO ­ tWPRE = 2nCK, tWPST = 0.5nCK, tRPRE = Toggling, tRPST = 1.5nCK

T0 T1 T2 T3 T4 Ta Ta+1 Ta+2 Ta+3 Tb Tb+1 Tb+2 Tb+3 Tb+4 Tb+5 Tc+2 Tc+3 Tc+4 Tc+5 Tc+6 Tc+7 Td Td+1 Td+2 Td+3 Td+4 Td+5 Te Te+1 Tf Tf+1 Tf+2 Tf+3 Tf+4 CK_c
CK_t
tCCD

CA[5:0]

Valid

Valid

Valid

Valid

Valid WL

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid RL

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Command

MPC [WRITE-FIFO]

DQS_t DQS_c

CAS-2

Valid

Valid tDQSS

Valid

tDQS2DQ

MPC [READ-FIFO]
tWTR

CAS-2

Valid

MPC [READ-FIFO]

CAS-2

Valid

Valid

Valid tDQSCK

Valid

Valid

tRPRE

Valid

Valid

tRPST

DQ[15:0] DMI[1:0]

D0 D1 D12 D13 D14 D15

D0 D1 D2 D13 D14 D15 D0 D11 D12 D13 D14 D15
Don't Care

Notes:

1. MPC[WRITE-FIFO] can be executed with a single bank or multiple banks active, during refresh or during self refresh with CKE HIGH.
2. Seamless MPC[READ-FIFO] commands may be executed by repeating the command every tCCD time.
3. MPC[READ-FIFO] uses the same command-to-data timing relationship (RL, tDQSCK) as a READ-1 command.
4. Data may be continuously read from the FIFO without any data corruption. After five MPC[READ-FIFO] commands, the FIFO pointer will wrap back to the first FIFO and continue advancing. If fewer than five MPC[WRITE-FIFO] commands were executed, then the MPC[READ-FIFO] commands to those FIFO locations will return undefined data. See Write Training for more information on the FIFO pointer behavior.
5. For the CAS-2 command immediately following an MPC command, the CAS-2 operands must be driven LOW.
6. DMI[1:0] signals will be driven if WR-DBI, RD-DBI, or DM is enabled in the mode registers. See Write Training for more information on DMI behavior.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

275

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP MULTIPURPOSE Operation

Figure 192: READ-FIFO ­ tRPRE = Toggling, tRPST = 1.5nCK

T0 T1 T2 T3 T4 Ta Ta+1 Ta+2 Ta+3 Ta+4 CK_c

CK_t

tRTRRD

Tb Tb+1

Tc Tc+1 Tc+2 Tc+3 Tc+4 Tc+5 Td Td+1 Td+2 Td+3 Te Te+1 Te+2 Te+3 Te+4 Te+5

CA[5:0] Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid

RL

RL

Command

MPC [READ-FIFO]

DQS_t DQS_c

DQ[15:0] DMI[1:0]

CAS-2

Valid

Valid

Valid

tDQSCK

Valid

Valid

READ-1

CAS-2

Valid

Valid

Valid

tDQSCK

Valid

Valid

Valid

tRPRE

tRPST

D0 D1 D2 D13 D14 D15

tRPRE D0 D1 D12 D13 D14 D15

tRPST

Don't Care

Notes:

1. MPC[WRITE-FIFO] can be executed with a single bank or multiple banks active, during refresh or during self refresh with CKE HIGH.
2. MPC[READ-FIFO] to READ-1 operation is shown as an example of command-to-command timing for MPC. Timing from MPC[READ-FIFO] command to read is tRTRRD.
3. Seamless MPC[READ-FIFO] commands may be executed by repeating the command every tCCD time.
4. MPC[READ-FIFO] uses the same command-to-data timing relationship (RL, tDQSCK) as a READ-1 command.
5. Data may be continuously read from the FIFO without any data corruption. After five MPC[READ-FIFO] commands, the FIFO pointer will wrap back to the first FIFO and continue advancing. If fewer than five MPC[WRITE-FIFO] commands are executed, then the MPC[READ-FIFO] commands to those FIFO locations will return undefined data. See Write Training for more information on the FIFO pointer behavior.
6. For the CAS-2 command immediately following an MPC command, the CAS-2 operands must be driven LOW.
7. DMI[1:0] signals will be driven if WR-DBI, RD-DBI, or DM is enabled in the mode registers. See Write Training for more information on DMI behavior.

Table 161: Timing Constraints for Training Commands

Previous Command
WR/MWR

Next Command MPC[WRITE-FIFO] MPC[READ-FIFO] MPC[READ DQ CALIBRATION]

RD/MRR

MPC[WRITE-FIFO] MPC[READ-FIFO] MPC[READ DQ CALIBRATION]

Minimum Delay tWRWTR
Not allowed WL + RU(tDQSS(MAX)/tCK) +
BL/2 + RU(tWTR/tCK) tRTRRD
Not allowed tRTRRD

Unit nCK
­ nCK
nCK ­
nCK

Notes 1 2
3 2 3

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

276

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP MULTIPURPOSE Operation

Table 161: Timing Constraints for Training Commands (Continued)

Previous Command
MPC[WRITE-FIFO]
MPC[READ-FIFO]
MPC[READ DQ CALIBRATION]

Next Command WR/MWR
MPC[WRITE-FIFO] RD/MRR
MPC[READ-FIFO]
MPC[READ DQ CALIBRATION] WR/MWR
MPC[WRITE-FIFO] RD/MRR
MPC[READ-FIFO] MPC[READ DQ CALIBRATION]
WR/MWR MPC[WRITE-FIFO]
RD/MRR MPC[READ-FIFO] MPC[READ DQ CALIBRATION]

Minimum Delay Not allowed tCCD Not allowed
WL + RU(tDQSS(MAX)/tCK) + BL/2 + RU(tWTR/tCK) Not allowed tRTRRD tRTW tRTRRD tCCD tRTRRD tRTRRD tRTRRD tRTRRD Not allowed tCCD

Unit ­
nCK ­
nCK
­ nCK nCK nCK nCK nCK nCK nCK nCK
­ nCK

Notes 2
2
2 3 4 3
3 3 3 3 2

Notes:

1. tWRWTR = WL + BL/2 + RU(tDQSS(MAX)/tCK) + MAX(RU(7.5ns/tCK), 8nCK). 2. No commands are allowed between MPC[WRITE-FIFO] and MPC[READ-FIFO] except the
MRW commands related to training parameters. 3. tRTRRD = RL + RU(tDQSCK(MAX)/tCK) + BL/2 + RD(tRPST) + MAX(RU(7.5ns/tCK), 8nCK). 4. In case of DQ ODT disable MR11 OP[2:0] = 000b,
tRTW = RL + RU(tDQSCK(MAX)/tCK) + BL/2 - WL + tWPRE + RD(tRPST).
In case of DQ ODT enable MR11 OP[2:0]  000b,
tRTW = RL + RU(tDQSCK(MAX)/tCK) + BL/2 + RD(tRPST) - ODTLon - RD(tODTon(MIN)/tCK) + 1.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

277

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Read DQ Calibration Training
Read DQ Calibration Training
The READ DQ CALIBRATION TRAINING function outputs a 16-bit, user-defined pattern on the DQ pins. Read DQ calibration is initiated by issuing a MPC[READ DQ CALIBRATION] command followed by a CAS-2 command, which causes the device to drive the contents of MR32, followed by the contents of MR40 on each of DQ[15:0] and DMI[1:0]. The pattern can be inverted on selected DQ pins according to user-defined invert masks written to MR15 and MR20.
Read DQ Calibration Training Procedure
1. Issue MRW commands to write MR32 (first eight bits), MR40 (second eight bits), MR15 (eight-bit invert mask for byte 0), and MR20 (eight-bit invert mask for byte 1). In the alternative, this step could be replaced with the default pattern:
· MR32 default = 5Ah · MR40 default = 3Ch · MR15 default = 55h · MR20 default = 55h 2. Issue an MPC command, followed immediately by a CAS-2 command.
· Each time an MPC command, followed by a CAS-2, is received by the device, a 16-bit data burst will drive the eight bits programmed in MR32 followed by the eight bits programmed in MR40 on all I/O pins after the currently set RL.
· The data pattern will be inverted for I/O pins with a 1 programmed in the corresponding invert mask mode register bit (see table below).
· The pattern is driven on the DMI pins, but no DATA BUS INVERSION function is enabled, even if read DBI is enabled in the mode register.
· The MPC command can be issued every tCCD seamlessly, and tRTRRD delay is required between ARRAY READ command and the MPC command as well the delay required between the MPC command and an ARRAY READ.
· The operands received with the CAS-2 command must be driven LOW. 3. DQ
Read DQ calibration training can be performed with any or no banks active during refresh or during self refresh with CKE HIGH.

Table 162: Invert Mask Assignments

DQ pin

0

1

2

3

DMI0

4

5

6

7

MR15 bit

0

1

2

3

N/A

4

5

6

7

DQ pin

8

9

10

11

DMI1

12

13

14

15

MR20 bit

0

1

2

3

N/A

4

5

6

7

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

278

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Read DQ Calibration Training

Figure 193: Read DQ Calibration Training Timing: Read-to-Read DQ Calibration

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Tb0 Tb1 Tb2 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Td1 Td2 Td3 Td4 Td5 Td6 Te0 Te1 Te2 Te3 CK_c
CK_t

CS

CA BL

BA0, CA

CAn

CAn

Valid Valid Valid Valid

Command READ-1
DQS_c DQS_t
DQ DMI

CAS-2

DES DES DES DES DES DES DES

RL
High-Z

t DQSCK t RPRE

DES DES

DES DES

DES

MPC [RD DQ CAL]

tRTRRD

t RPST

High-Z

tDQSQ

High-Z

n0 n13 n14 n15

High-Z

CAS-2

DES DES

DES DES DES DES

DES DES

DES DES DES

RL

t DQSCK

t RPRE

t RPST

tDQSQ n0 n13 n14 n15

Don't Care

Notes:

1. Read-1 to MPC operation is shown as an example of command-to-command timing. Timing from Read-1 to MPC command is tRTRRD.
2. MPC uses the same command-to-data timing relationship (RL, tDQSCK, tDQSQ) as a Read-1 command.
3. BL = 16, Read preamble: Toggle, Read postamble: 0.5nCK.
4. DES commands are shown for ease of illustration; other commands may be valid at these times.

Figure 194: Read DQ Calibration Training Timing: Read DQ Calibration to Read DQ Calibration/Read

T0 T1 T2 T3 CK_c
CK_t

T8 T9 T10 T11 T12 T13 T14 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Td0 Td1 Td2 Td3 Td4 Te0 Te1

CS

CA Valid Valid Valid Valid

Valid Valid Valid Valid

BL

BA0, CA

CAn

CAn

Command

MPC [RD DQ CAL]

DQS_c DQS_t
DQ DMI

CAS-2

DES

MPC [RD DQ CAL]
t CCD

RL

CAS-2

High-Z

High-Z

DES DES

DES DES DES DES DES DES DES

DES

RL tDQSCK
t RPRE

tDQSCK

tRTRRD

t RPST

tDQSQ

t DQSQ n0 n9 n10 n11 n12 n13 n14 n15 n0 n13 n14 n15

READ-1

CAS-2

High-Z High-Z

DES DES DES DES DES DES DES DES

RL

tDQSCK

t RPRE

t RPST

tDQSQ n0 n13 n14 n15

Don't Care

Notes:

1. MPC[READ DQ CALIBRATION] to MPC[READ DQ CALIBRATION] operation is shown as an example of command-to-command timing.
2. MPC[READ DQ CALIBRATION] to READ-1 operation is shown as an example of command-to-command timing.
3. MPC[READ DQ CALIBRATION] uses the same command-to-data timing relationship (RL, tDQSCK, tDQSQ) as a READ-1 command.
4. Seamless MPC[READ DQ CALIBRATION] commands may be executed by repeating the command every tCCD time.
5. Timing from MPC[READ DQ CALIBRATION] command to READ-1 is tRTRRD.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

279

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Read DQ Calibration Training

6. BL = 16, Read preamble: Toggle, Read postamble: 0.5nCK. 7. DES commands are shown for ease of illustration; other commands may be valid at
these times.
Read DQ Calibration Training Example
An example of read DQ calibration training output is shown in table below. This shows the 16-bit data pattern that will be driven on each DQ in byte 0 when one READ DQ CALIBRATION TRAINING command is executed. This output assumes the following mode register values are used:
· MR32 = 1CH · MR40 = 59H · MR15 = 55H · MR20 = 55H

Table 163: Read DQ Calibration Bit Ordering and Inversion Example

Bit Sequence 

Pin Invert 15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

DQ0

Yes

1

0

1

0

0

1

1

0

1

1

1

0

0

0

1

1

DQ1

No

0

1

0

1

1

0

0

1

0

0

0

1

1

1

0

0

DQ2

Yes

1

0

1

0

0

1

1

0

1

1

1

0

0

0

1

1

DQ3

No

0

1

0

1

1

0

0

1

0

0

0

1

1

1

0

0

DMI0 Never 0

1

0

1

1

0

0

1

0

0

0

1

1

1

0

0

DQ4

Yes

1

0

1

0

0

1

1

0

1

1

1

0

0

0

1

1

DQ5

No

0

1

0

1

1

0

0

1

0

0

0

1

1

1

0

0

DQ6

Yes

1

0

1

0

0

1

1

0

1

1

1

0

0

0

1

1

DQ7

No

0

1

0

1

1

0

0

1

0

0

0

1

1

1

0

0

DQ8

Yes

1

0

1

0

0

1

1

0

1

1

1

0

0

0

1

1

DQ9

No

0

1

0

1

1

0

0

1

0

0

0

1

1

1

0

0

DQ10 Yes

1

0

1

0

0

1

1

0

1

1

1

0

0

0

1

1

DQ11 No

0

1

0

1

1

0

0

1

0

0

0

1

1

1

0

0

DMI1 Never 0

1

0

1

1

0

0

1

0

0

0

1

1

1

0

0

DQ12 Yes

1

0

1

0

0

1

1

0

1

1

1

0

0

0

1

1

DQ13 No

0

1

0

1

1

0

0

1

0

0

0

1

1

1

0

0

DQ14 Yes

1

0

1

0

0

1

1

0

1

1

1

0

0

0

1

1

DQ15 No

0

1

0

1

1

0

0

1

0

0

0

1

1

1

0

0

Notes:

1. The patterns contained in MR32 and MR40 are transmitted on DQ[15:0] and DMI[1:0] when read DQ calibration is initiated via a MPC[READ DQ CALIBRATION] command. The pattern transmitted serially on each data lane, organized little endian such that the loworder bit in a byte is transmitted first. If the data pattern is 27H, then the first bit transmitted with be a 1, followed by 1, 1, 0, 0, 1, 0, and 0. The bit stream will be 00100111 .
2. MR15 and MR20 may be used to invert the MR32/MR40 data pattern on the DQ pins. See MR15 and MR20 for more information. Data is never inverted on the DMI[1:0] pins.
3. DMI [1:0] outputs status follows MR Setting vs. DMI Status table.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

280

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Write Training

4. No DATA BUS INVERSION (DBI) function is enacted during read DQ calibration, even if DBI is enabled in MR3-OP[6].

Table 164: MR Setting vs. DMI Status

DM Function MR13 OP[5]
1: Disable 1: Disable 1: Disable 1: Disable 0: Enable 0: Enable 0: Enable 0: Enable

WRITE DBIdc Function MR3 OP[7] 0: Disable 1: Enable 0: Disable 1: Enable 0: Disable 1: Enable 0: Disable 1: Enable

READ DBIdc Function MR3 OP[6] DMI 0: Disable 0: Disable 1: Enable 1: Enable 0: Disable 0: Disable 1: Enable 1: Enable

Status
High-Z The data pattern is transmitted The data pattern is transmitted The data pattern is transmitted The data pattern is transmitted The data pattern is transmitted The data pattern is transmitted The data pattern is transmitted

MPC[READ DQ CALIBRATION] After Power-Down Exit
Following the power-down state, an additional time, tMRRI, is required prior to issuing the MPC[READ DQ CALIBRATION] command. This additional time (equivalent to tRCD) is required in order to be able to maximize power-down current savings by allowing more power-up time for the read DQ data in MR32 and MR40 data path after exit from standby, power-down mode.

Figure 195: MPC[READ DQ CALIBRATION] Following Power-Down State

T0 Ta0 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Td0 Td1 Td2 Td3 Td4 Td5 Td6 Td7 Td8 Td9

CK_c

CK_t

tCKCKEH

CKE tXP
CS

tMRRI

CA

Valid Valid Valid Valid

Command

DES DES DES DES DES DES DES DES DES DES [READMDPQC CAL] CAS-2

DES DES DES Don't Care

Write Training

The device uses an unmatched DQS-DQ path to enable high-speed performance and save power. As a result, the DQS strobe must be trained to arrive at the DQ latch centeraligned with the data eye. The DQ receiver is located at the DQ pad and has a shorter internal delay than the DQS signal. The DQ receiver will latch the data present on the

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

281

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Write Training
DQ bus when DQS reaches the latch, and training is accomplished by delaying the DQ signals relative to DQS such that the data eye arrives at the receiver latch centered on the DQS transition.
Two modes of training are available:
· Command-based FIFO WR/RD with user patterns · An internal DQS clock-tree oscillator, which determines the need for, and the magni-
tude of, required training
The command-based FIFO WR/RD uses the MPC command with operands to enable this special mode of operation. When issuing the MPC command, if CA[5] is set LOW (OP[6] = 0), then the device will perform a NOP command. When CA[5] is set HIGH, the CA[4:0] pins enable training functions or are reserved for future use (RFU). MPC commands that initiate a read or write to the device must be followed immediately by a CAS-2 command. See the MPC Operation section for more information.
To perform write training, the controller can issue an MPC[WRITE-FIFO] command with OP[6:0] set, followed immediately by a CAS-2 command (CAS-2 operands should be driven LOW ) to initiate a WRITE-FIFO. Timings for MPC[WRITE-FIFO] are identical to WRITE commands, with WL timed from the second rising clock edge of the CAS-2 command. Up to five consecutive MPC[WRITE-FIFO] commands with user-defined patterns may be issued to the device, which will store up to 80 values (BL16 × 5) per pin that can be read back via the MPC[READ-FIFO] command. (The WRITE/READ-FIFO POINTER operation is described in a different section.
After writing data with the MPC[WRITE-FIFO] command, the data can be read back with the MPC[READ-FIFO] command and results can be compared with "expected" data to determine whether further training (DQ delay) is needed. MPC[READ-FIFO] is initiated by issuing an MPC command, as described in the MPC Operation section, followed immediately by a CAS-2 command (CAS-2 operands must be driven LOW). Timings for the MPC[READ-FIFO] command are identical to READ commands, with RL timed from the second rising clock edge of the CAS-2 command.
READ-FIFO is nondestructive to the data captured in the FIFO; data may be read continuously until it is disturbed by another command, such as a READ, WRITE, or another MPC[WRITE-FIFO]. If fewer than five WRITE-FIFO commands are executed, unwritten registers will have undefined (but valid) data when read back.
For example: If five WRITE-FIFO commands are executed sequentially, then a series of READ-FIFO commands will read valid data from FIFO[0], FIFO[1]....FIFO[4] and then wrap back to FIFO[0] on the next READ-FIFO. However, if fewer than five WRITE-FIFO commands are executed sequentially (example = 3), then a series of READ-FIFO commands will return valid data for FIFO[0], FIFO[1], and FIFO[2], but the next two READFIFO commands will return undefined data for FIFO[3] and FIFO[4] before wrapping back to the valid data in FIFO[0].
The READ-FIFO pointer and WRITE-FIFO pointer are reset under the following conditions:
· Power-up initialization · RESET_n asserted · Power-down entry · Self refresh power-down entry

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

282

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Write Training
The MPC[WRITE-FIFO] command advances the WRITE-FIFO pointer, and the MPC[READ-FIFO] advances the READ-FIFO pointer. Also any normal (non-FIFO) READ operation (RD, RDA) advances both WRITE-FIFO pointer and READ-FIFO pointer. Issuing (non-FIFO) READ operation command is inhibited during write training period. To keep the pointers aligned, the SoC memory controller must adhere to the following restriction at the end of Write training period:
b = a + (n × c)
Where: 'a' is the number of MPC[WRITE-FIFO] commands 'b' is the number of MPC[READ-FIFO] commands 'c' is the FIFO depth (= 5 for LPDDR4) 'n' is a positive integer, 0

Figure 196: WRITE-to-MPC[WRITE-FIFO] Operation Timing

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Tb0 Tb1 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Td0 Td1 Td2 Td3 Td4 Td5 Te0 Te1 Te2 Tf0 Tf1 Tg0 Tg1 Tg2 Tg3 CK_c
CK_t

CS

CA BL

BA0, CA

CAn

CAn

Valid Valid Valid Valid

Valid Valid Valid Valid

Command WRITE-1
DQS_c DQS_t DQ[15:0] DMI[1:0]

CAS-2

DES DES DES DES DES

WL t WPRE

t WRWTR tDQSS

DES

DES

MPC [WRITE-FIFO]

t WPST

CAS-2

DES

DES

MPC [WRITE-FIFO]

tCCD = 8 WL

CAS-2

DES DES DES DES DES DES DES DES DES DES

WL

WPRE

tDQSS

tDQSS

t WPST

tDQS2DQ n0 n13 n14 n15

tDQS2DQ

tDQS2DQ

n0 n13 n14 n15 n0 n13 n14 n15

Don't Care

Notes:

1. MPC[WRITE-FIFO] can be executed with a single bank or multiple banks active during REFRESH or during SELF REFRESH with CKE HIGH.
2. Write-1 to MPC is shown as an example of command-to-command timing for MPC. Timing from Write-1 to MPC[WRITE-FIFO] is tWRWTR.
3. Seamless MPC[WR-FIFO] commands may be executed by repeating the command every tCCD time.
4. MPC[WRITE-FIFO] uses the same command-to-data timing relationship (WL, tDQSS, tDQS2DQ) as a WRITE-1 command.
5. A maximum of five MPC[WRITE-FIFO] commands may be executed consecutively without corrupting FIFO data. The sixth MPC[WRITE-FIFO] command will overwrite the FIFO data from the first command. If fewer than five MPC[WRITE-FIFO] commands are executed, then the remaining FIFO locations will contain undefined data.
6. For the CAS-2 command following an MPC command, the CAS-2 operands must be driven LOW.
7. To avoid corrupting the FIFO contents, MPC[READ-FIFO] must immediately follow MPC[WRITE-FIFO]/CAS-2 without any other commands disturbing FIFO pointers in between. FIFO pointers are disturbed by CKE LOW, WRITE, MASKED WRITE, READ, READ DQ CALIBRATION, and MRR.
8. BL = 16, Write postamble = 0.5nCK.
9. DES commands are shown for ease of illustration; other commands may be valid at these times.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

283

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Write Training

Figure 197: MPC[WRITE-FIFO]-to-MPC[READ-FIFO] Timing

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Td0 Td1 Td2 Td3 Td4 Td5 Te0 Te1 Te2 Te3 Tf0 Tf1 Tg0 Tg1 CK_c
CK_t

CS

CA BL

BA0, CA

CAn

CAn

Valid Valid Valid Valid

Valid Valid Valid Valid

Command

MPC [WRITE-FIFO]

DQS_c DQS_t
DQ DMI

CAS-2

DES DES DES DES DES DES DES

WL t WPRE

BL/2 + 1 clock tDQSS

t WPST

DES

MPC [READ-FIFO]

tWTR

CAS-2

DES

DES

MPC [READ-FIFO]

tCCD = 8 RL

CAS-2

DES DES DES DES DES DES DES DES DES

tDQSCK t RPRE

t RPST

tDQS2DQ n0 n13 n14 n15

tDQSQ n0 n13 n14 n15 n0 n13 n14 n15

Don't Care

Notes:

1. MPC[WRITE-FIFO] can be executed with a single bank or multiple banks active during refresh or during self refresh with CKE HIGH.
2. MPC[WRITE-FIFO] to MPC[READ-FIFO] is shown as an example of command-to-command timing for MPC. Timing from MPC[WRITE-FIFO] to MPC[READ-FIFO] is specified in the command-to-command timing table.
3. Seamless MPC[READ-FIFO] commands may be executed by repeating the command every tCCD time.
4. MPC[READ-FIFO] uses the same command-to-data timing relationship (RL, tDQSCK, tDQSQ ) as a READ-1 command.
5. Data may be continuously read from the FIFO without any data corruption. After five MPC[READ-FIFO] commands, the FIFO pointer will wrap back to the first FIFO and continue advancing. If fewer than five MPC[WRITE-FIFO] commands were executed, then the MPC[READ-FIFO] commands to those FIFO locations will return undefined data. See Write Training for more information on the FIFO pointer behavior.
6. For the CAS-2 command immediately following an MPC command, the CAS-2 operands must be driven LOW.
7. DMI[1:0] signals will be driven if WR-DBI, RD-DBI, or DM is enabled in the mode registers. See Write Training section for more information on DMI behavior.
8. BL = 16, Write postamble = 0.5nCK, Read preamble: Toggle, Read postamble: 0.5nCK.
9. DES commands are shown for ease of illustration; other commands may be valid at these times.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

284

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Write Training

Figure 198: MPC[READ-FIFO] to Read Timing

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Tb0 Tb1 Tb2 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Td1 Td2 Td3 Td4 Td5 Td6 Te0 Te1 Te2 Te3 CK_c
CK_t

CS

CA Valid Valid CAn CAn

BL

BA0, CA

CAn

CAn

Command

MPC RAD FIFO

DQS_c DQS_t
DQ DMI

CAS-2

DES DES DES DES DES DES DES

RL

t DQSCK

t RPRE

DES DES

DES DES DES

tRTRRD

t RPST

READ-1

CAS-2

DES DES

DES DES DES DES

DES DES

DES DES DES

RL

t DQSCK

t RPRE

t RPST

tDQSQ n0 n13 n14 n15

tDQSQ n0 n13 n14 n15

Don't Care

Notes:

1. MPC[WRITE-FIFO] can be executed with a single bank or multiple banks active during refresh or during self refresh with CKE HIGH.
2. MPC[READ-FIFO] to READ-1 operation is shown as an example of command-to-command timing for MPC. Timing from MPC[READ-FIFO] command to READ is tRTRRD.
3. Seamless MPC[READ-FIFO] commands may be executed by repeating the command every tCCD time.
4. MPC[READ-FIFO] uses the same command-to-data timing relationship (RL, tDQSCK, tDQSQ ) as a READ-1 command.
5. Data may be continuously read from the FIFO without any data corruption. After five MPC[READ-FIFO] commands, the FIFO pointer will wrap back to the first FIFO and continue advancing. If fewer than five MPC[WRITE-FIFO] commands were executed, then the MPC[READ-FIFO] commands to those FIFO locations will return undefined data. See Write Training for more information on the FIFO pointer behavior.
6. For the CAS-2 command immediately following an MPC command, the CAS-2 operands must be driven LOW.
7. DMI[1:0] signals will be driven if WR-DBI, RD-DBI, or DM is enabled in the mode registers. See Write Training for more information on DMI behavior.
8. BL = 16, Read preamble: Toggle, Read postamble: 0.5nCK
9. DES commands are shown for ease of illustration; other commands may be valid at these times.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

285

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Write Training

Figure 199: MPC[WRITE-FIFO] with DQ ODT Timing
T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 CK_c CK_t
CS
CA Valid Valid Valid Valid

Command

MPC [WRITE-FIFO]

DQS_c DQS_t
DQ DMI
DRAM RTT

CAS-2

DES DES DES DES DES DES DES

DES DES DES

DES DES DES DES DES DES DES

WL

tDQSS

t WPRE

t WPST

ODTLon ODT High-Z

tODTon(MAX) tODTon(MIN)
Transition

ODT On ODTLoff

tDQS2DQ n0 n1 n2 n13 n14 n15

Transition ODT High-Z
tODToff(MIN) tODToff(MAX)

Don't Care

Notes:

1. MPC[WRITE-FIFO] can be executed with a single bank or multiple banks active during refresh or during self refresh with CKE HIGH.
2. MPC[WRITE-FIFO] uses the same command-to-data/ODT timing relationship (RL, tDQSCK, tDQS2DQ, ODTLon, ODTLoff, tODTon, tODToff) as a WRITE-1 command.
3. For the CAS-2 command immediately following an MPC command, the CAS-2 operands must be driven LOW.
4. BL = 16, Write postamble = 0.5nCK.
5. DES commands are shown for ease of illustration; other commands may be valid at these times.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

286

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Write Training

Figure 200: Power-Down Exit to MPC[WRITE-FIFO] Timing

T0 CK_c

Ta0 Tb0 Tb1 Tb2 Tc0 Tc1

CK_t

t CKCKEH

Tc2 Tc3 Tc4 Tc5 Td0 Td1 Td2 Td3 Td4 Td5 Td6 Td7 Td8 Td9

CKE t XP

t MPCWR (= t RCD + 3nCK)

WL

CS

CA Command

Valid Valid Valid Valid

Valid Valid Valid Valid

Note 1

DES

DES Any command Any command DES

DES

DES

DES

MPC [WRITE-FIFO]

CAS-2

DES DES DES

Don't Care

Notes:

1. Any commands except MPC[WRITE-FIFO] and other exception commands defined other section in this document (for example. MPC[READ DQ CALIBRATION]).
2. DES commands are shown for ease of illustration; other commands may be valid at these times.

Table 165: MPC[WRITE-FIFO] AC Timing
Parameter Additional time after tXP has expired until MPC[WRITE-FIFO] command may be issued

Symbol tMPCWR

MIN/MAX MIN

Value tRCD + 3nCK

Unit ­

Internal Interval Timer
As voltage and temperature change on the device, the DQS clock-tree delay will shift, requiring retraining. The device includes an internal DQS clock-tree oscillator to measure the amount of delay over a given time interval (determined by the controller), allowing the controller to compare the trained delay value to the delay value seen at a later time. The DQS oscillator will provide the controller with important information regarding the need to retrain and the magnitude of potential error.
The DQS interval oscillator is started by issuing an MPC command with OP[6:0] set as described in MPC Operation, which will start an internal ring oscillator that counts the number of time a signal propagates through a copy of the DQS clock tree.
The DQS oscillator may be stopped by issuing an MPC[STOP DQS OSCILLATOR] command with OP[6:0] set as described in MPC Operation, or the controller may instruct the SDRAM to count for a specific number of clocks and then stop automatically (See MR23 for more information). If MR23 is set to automatically stop the DQS oscillator, then the MPC[STOP DQS OSCILLATOR] command should not be used (illegal). When the DQS oscillator is stopped by either method, the result of the oscillator counter is automatically stored in MR18 and MR19.
The controller may adjust the accuracy of the result by running the DQS interval oscillator for shorter (less accurate) or longer (more accurate) duration. The accuracy of the

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

287

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Write Training

result for a given temperature and voltage is determined by the following equation, where run time = total time between START and STOP commands and DQS delay = the value of the DQS clock tree delay (tDQS2DQ(MIN)/(MAX)):

DQS oscillator granularity error =

2 x (DQS delay) run time

Additional matching error must be included, which is the difference between DQS training circuit and the actual DQS clock tree across voltage and temperature. The matching error is vendor specific. Therefore, the total accuracy of the DQS oscillator counter is given by:

DQS oscillator accuracy = 1 - granularity error - matching error

For example, if the total time between START and STOP commands is 100ns, and the maximum DQS clock tree delay is 800ps (tDQS2DQ(MAX)), then the DQS oscillator granularity error is:

DQS oscillator granularity error =

2 x (0.8ns) 100ns

= 1.6%

This equates to a granularity timing error of 12.8ps. Assuming a circuit matching error of 5.5ps across voltage and temperature, the accuracy is:

DQS oscillator accuracy = 1 -

12.8 + 5.5 800

= 97.7%

For example, running the DQS oscillator for a longer period improves the accuracy. If the total time between START and STOP commands is 500ns, and the maximum DQS clock tree delay is 800ps (tDQS2DQ(MAX)), then the DQS oscillator granularity error is:

DQS oscillator granularity error =

2 x (0.8ns) 500ns

= 0.32%

This equates to a granularity timing error or 2.56ps. Assuming a circuit matching error of 5.5ps across voltage and temperature, the accuracy is:

DQS oscillator accuracy = 1 -

2.56 + 5.5 800

= 99.0%

The result of the DQS interval oscillator is defined as the number of DQS clock tree delays that can be counted within the run time, determined by the controller. The result is stored in MR18-OP[7:0] and MR19-OP[7:0].
MR18 contains the least significant bits (LSB) of the result, and MR19 contains the most significant bits (MSB) of the result. MR18 and MR19 are overwritten by the SDRAM when a MPC[STOP DQS OSCILLATOR] command is received.
The SDRAM counter will count to its maximum value (= 2^16) and stop. If the maximum value is read from the mode registers, the memory controller must assume that the counter overflowed the register and therefore discard the result. The longest run time for the oscillator that will not overflow the counter registers can be calculated as follows:
Longest runtime interval = 216 x tDQS2DQ(MIN) = 216 × 0.2ns = 13.1µs

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

288

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Write Training
DQS Interval Oscillator Matching Error
The interval oscillator matching error is defined as the difference between the DQS training ckt (interval oscillator) and the actual DQS clock tree across voltage and temperature. Parameters: tDQS2DQ: Actual DQS clock tree delay tDQSOSC: Training ckt (interval oscillator) delay OSCOffset: Average delay difference over voltage and temperature (shown below) OSCMatch: DQS oscillator matching error Figure 201: Interval Oscillator Offset ­ OSCoffset
Offset 2

Time (ps)
Offset 1

tDQS2DQ tDQSOSC

OSC offset = AVG(offset1, offset2)

Offset 1 (at end point) = Offset 2 (at end point) =

tDQS2DQ(V,T ) tDQS2DQ(V,T )

­ ­

ttDDQQSSOOSSCC((VV,,TT))

Temperature(T)/Voltage(V)

OSCMatch : OSCMatch = [ tDQS2DQ(V,T) - tDQSOSC (V,T) - OSCoffset ]

tDQSOSC:

tDQSOSC(V,T) = [

Runtime 2 × Count

]

Table 166: DQS Oscillator Matching Error Specification

Parameter DQS oscillator matching error
DQS oscillator offset

Symbol OSCMatch
OSCoffset

MIN ­20
­100

MAX 20
100

Unit ps
ps

Notes
1, 2, 3, 4, 5, 6, 7, 8
2, 4. 7

Notes: 1. The OSCMatch is the matching error per between the actual DQS and DQS interval oscillator over voltage and temperature.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

289

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Write Training

2. This parameter will be characterized or guaranteed by design. 3. The OSCMatch is defined as the following:

OSCMatch = [ tDQS2DQ(V, T) - tDQSOSC(V, T) - OSCoffset ]

Where tDQS2DQ(V,T) and tDQSOSC(V,T) are determined over the same voltage and temperature conditions. 4. The runtime of the oscillator must be at least 200ns for determining tDQSOSC(V,T).

tDQSOSC(V,T) = [

Runtime 2 × Count

]

5. The input stimulus for tDQS2DQ will be consistent over voltage and temperature conditions.
6. The OSCoffset is the average difference of the endpoints across voltage and temperature. 7. These parameters are defined per channel. 8. tDQS2DQ(V,T) delay will be the average of DQS-to-DQ delay over the runtime period.

OSC Count Readout Time
OSC Stop to its counting value readout timing is shown in following figures.

Figure 202: In Case of DQS Interval Oscillator is Stopped by MPC Command
T0 T1 T2 T3 T4 T5 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 CK_c CK_t

CKE CS

CA

Valid Valid

Valid Valid

Valid Valid Valid Valid

Command

DES DMQSMROPWCSC:IrSLiTLtAAeRT-TO2R DES

DES

DES

DES

MPC :STOP DQS OSCILLATOR

DES

DES

DES

DES

MRR-1 MR18/MR19

tOSCO

Note: 1. DQS interval timer run time setting :MR23 OP[7:0] = 00000000b.

CAS-2 Don't Care

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

290

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Write Training
Figure 203: In Case of DQS Interval Oscillator is Stopped by DQS Interval Timer
T0 T1 T2 T3 T4 T5 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 CK_c CK_t

CKE CS

CA

Valid Valid

Valid Valid Valid Valid

Command DES DMQSMROPWCSC:IrSLiTLtAAeRT-TO2R DES DES DES DES DES DES DES DES DES DES

MRR-1 MR18/MR19

CAS-2

See Note 2

tOSCO

Notes: 1. DQS interval timer run time setting: MR23 OP[7:0]  00000000b. 2. Setting counts of MR23.

Don't Care

Table 167: DQS Interval Oscillator AC Timing

Parameter
Delay time from OSC stop to mode register readout

Symbol tOSCO

MIN/MAX MIN

Value
MAX(40ns, 8nCK)

Unit ns

Note: 1. START DQS OSCILLATOR command is prohibited until tOSCO(MIN) is satisfied.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

291

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Thermal Offset
Thermal Offset
Because of tight thermal coupling, hot spots on an SOC can induce thermal gradients across the device. Because these hot spots may not be located near the thermal sensor, the temperature compensated self refresh (TCSR) circuit may not generate enough refresh cycles to guarantee memory retention. To address this shortcoming, the controller can provide a thermal offset that the memory can use to adjust its TCSR circuit to ensure reliable operation.
This thermal offset is provided through MR4 OP[6:5] to either or both channels (dualchannel devices). This temperature offset may modify refresh behaviour for the channel to which the offset is provided. It will take a maximum of 200µs to have the change reflected in MR4 OP[2:0] for the channel to which the offset is provided. If the induced thermal gradient from the device temperature sensor location to the hot spot location of the controller is greater than 15°C, self refresh mode will not reliably maintain memory contents.
To accurately determine the temperature gradient between the memory thermal sensor and the induced hot spot, the memory thermal sensor location must be provided to the controller.
Temperature Sensor
The device has a temperature sensor that can be read from MR4. This sensor can be used to determine the appropriate refresh rate, to determine whether AC timing de-rating is required at an elevated temperature range, and to monitor the operating temperature. Either the temperature sensor or the device TOPER can be used to determine if operating temperature requirements are being met.
The device monitors device temperature and updates MR4 according to tTSI. Upon exiting self refresh or power-down, the device temperature status bits shall be no older than tTSI.
When using the temperature sensor, the actual device case temperature may be higher than the TOPER specification that applies to standard or elevated temperature ranges. For example, TCASE may be above 85°C when MR4[2:0] = b011. The device enables a 2°C temperature margin between the point when the device updates the MR4 value and the point when the controller reconfigures the system accordingly. When performing tight thermal coupling of the device to external hot spots, the maximum device temperature may be higher than indicated by MR4.
To ensure proper operation when using the temperature sensor, consider the following:
· TempGradient is the maximum temperature gradient experienced by the device at the temperature of interest over a range of 2°C.
· ReadInterval is the time period between MR4 reads from the system. · TempSensorInterval (tTSI) is the maximum delay between the internal updates of
MR4. · SysRespDelay is the maximum time between a read of MR4 and a response from the
system.
In order to determine the required frequency of polling MR4, the system uses the TempGradient and the maximum response time of the system in the following equation:
TempGradient × (ReadInterval + tTSI + SysRespDelay)  2°C

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

292

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP ZQ Calibration

Table 168: Temperature Sensor
Parameter System temperature gradient MR4 read interval Temperature sensor interval System response delay Device temperature margin

Symbol TempGradient ReadInterval
tTSI SysRespDelay TempMargin

Max/Min MAX MAX MAX MAX MAX

Value System Dependent System Dependent
32 System Dependent
2

For example, if TempGradient is 10°C/s and the SysRespDelay is 1ms: (10°C/s) x (ReadInterval + 32ms + 1ms)  2°C In this case, ReadInterval shall be no greater than 167ms.

Figure 204: Temperature Sensor Timing

Temperature
Device temperature
margin

< [tTSI + ReadInterval + SysRespDelay]

2°

TempGradient

MR4 trip level

Unit °C/s ms ms ms °C

Temperature sensor update
Host MR4 read

tTSI MR4 = 0x03

MR4 = 0x06

MR4 = 0x06 MR4 = 0x06

MR4 = 0x06 MR4 = 0x06

Time

MRR MR4 = 0x06

ReadInterval

SysRespDelay MRR MR4 = 0x06

ZQ Calibration

The MPC command is used to initiate ZQ calibration, which calibrates the output driver impedance and CA/DQ ODT impedance across process, temperature, and voltage. ZQ calibration occurs in the background of device operation and is designed to eliminate any need for coordination between channels (that is, it allows for channel independence). ZQ calibration is required each time that the PU-Cal value (MR3-OP[0]) is changed. Additional ZQ CALIBRATION commands may be required as the voltage and temperature change in the system environment. CA ODT values (MR11-OP[6:4]) and DQ ODT values (MR11-OP[2:0]) may be changed without performing ZQ calibration, as long as the PU-Cal value doesn't change.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

293

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP ZQ Calibration

ZQCAL Reset

There are two ZQ calibration modes initiated with the MPC command: ZQCAL START and ZQCAL LATCH. ZQCAL START initiates the calibration procedure, and ZQCAL LATCH captures the result and loads it into the drivers.
A ZQCAL START command may be issued anytime the device is not in a power-down state. A ZQCAL LATCH command may be issued anytime outside of power-down after tZQCAL has expired and all DQ bus operations have completed. The CA bus must maintain a deselect state during tZQLAT to allow CA ODT calibration settings to be updated. The DQ calibration value will not be updated until ZQCAL LATCH is performed and tZQLAT has been met. The following mode register fields that modify I/O parameters cannot be changed following a ZQCAL START command and before tZQCAL has expired:
· PU-Cal (pull-up calibration VOH point) · PDDS (pull-down drive strength and Rx termination) · DQ ODT (DQ ODT value) · CA ODT (CA ODT value)
The ZQCAL RESET command resets the output impedance calibration to a default accuracy of ±30% across process, voltage, and temperature. This command is used to ensure output impedance accuracy to ±30% when ZQCAL START and ZQCAL LATCH commands are not used.
The ZQCAL RESET command is executed by writing MR10-OP[0] = 1B.

Table 169: ZQ Calibration Parameters
Parameter ZQCAL START to ZQCAL LATCH command interval ZQCAL LATCH to next valid command interval ZQCAL RESET to next valid command interval

Symbol tZQCAL tZQLAT tZQRESET

Min/Max MIN MIN MIN

Value 1
MAX(30ns, 8nCK) MAX(50ns, 3nCK)

Unit µs ns ns

Figure 205: ZQCAL Timing

T0 T1 T2 T3 T4 T5 T6 T7 T8 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 CK_c

CK_t

tZQCAL

tZQLAT

CA

ZQCAL ZQCAL START START

WR WR CAS CAS WL

ZQCAL ZQCAL LATCH LATCH

Valid Valid

Command

MPC TRAIN/CAL

DES

DES

WRITE

DQS_t DQS_c

DQ[15:0]

CAS2

DES DES DES DES DES DES DES DES DES DES DES DES DES DES tDQSS

MPC TRAIN/CAL

DES

DES

DES

DES

PRECHARGE

DES

DES

tWPRE

tDQS2DQ

tWPST

Transitioning Data

Don't Care

Notes: 1. WRITE and PRECHARGE operations are shown for illustrative purposes. Any single or multiple valid commands may be executed within the tZQCAL time and prior to latching the results.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

294

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP ZQ Calibration
2. Before the ZQCAL LATCH command can be executed, any prior commands that utilize the DQ bus must have completed. WRITE commands with DQ termination must be given enough time to turn off the DQ ODT before issuing the ZQCAL LATCH command. See the ODT section for ODT timing.
Multichannel Considerations
The device includes a single ZQ pin and associated ZQ calibration circuitry. Calibration values from this circuit will be used by both channels according to the following protocol:
· The ZQCAL START command can be issued to either or both channels. · The ZQCAL START command can be issued when either or both channels are execut-
ing other commands, and other commands can be issued during tZQCAL. · The ZQCAL START command can be issued to both channels simultaneously. · The ZQCAL START command will begin the calibration unless a previously requested
ZQ calibration is in progress. · If the ZQCAL START command is received while a ZQ calibration is in progress, the
command will be ignored and the in-progress calibration will not be interrupted. · The ZQCAL LATCH command is required for each channel. · The ZQCAL LATCH command can be issued to both channels simultaneously. · The ZQCAL LATCH command will latch results of the most recent ZQCAL START
command provided tZQCAL has been met. · ZQCAL LATCH commands that do not meet tZQCAL will latch the results of the most
recently completed ZQ calibration. · The ZQRESET MRW commands will only reset the calibration values for the channel
issuing the command.
In compliance with complete channel independence, either channel may issue ZQCAL START and ZQCAL LATCH commands as needed without regard to the state of the other channel.
ZQ External Resistor, Tolerance, and Capacitive Loading
To use the ZQ CALIBRATION function, a 240 ohms, ±1% tolerance external resistor must be connected between the ZQ pin and VDDQ.
If the system configuration shares the CA bus to form a x32 (or wider) channel, the ZQ pin of each die's x16 channel must use a separate ZQCAL resistor.
If the system configuration has more than one rank, and if the ZQ pins of both ranks are attached to a single resistor, then the SDRAM controller must ensure that the ZQCAL's don't overlap.
The total capacitive loading on the ZQ pin must be limited to 25pF. For example, if a system configuration shares a CA bus between n channels to form an n x16 wide bus, and no means are available to control the ZQCAL separately for each channel (that is, separate CS, CKE, or CK), then each x16 channel must have a separate ZQCAL resistor. For a x32, two-rank system, each x16 channel must have its own ZQCAL resistor, but the ZQCAL resistor can be shared between ranks on each x16 channel. In this configuration, the CS signal can be used to ensure that the ZQCAL commands for Rank[0] and Rank[1] don't overlap.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

295

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Frequency Set Points
Frequency Set Points
Frequency set points enable the CA bus to be switched between two differing operating frequencies with changes in voltage swings and termination values, without ever being in an untrained state, which could result in a loss of communication to the device. This is accomplished by duplicating all CA bus mode register parameters, as well as other mode register parameters commonly changed with operating frequency.
These duplicated registers form two sets that use the same mode register addresses, with read/write access controlled by MR bit FSP-WR (frequency set point write/read) and the operating point controlled by MR bit FSP-OP (FREQUENCY SET POINT operation). Changing the FSP-WR bit enables MR parameters to be changed for an alternate frequency set point without affecting the current operation.
Once all necessary parameters have been written to the alternate set point, changing the FSP-OP bit will switch operation to use all of the new parameters simultaneously (within tFC), eliminating the possibility of a loss of communication that could be caused by a partial configuration change.
Parameters that have two physical registers controlled by FSP-WR and FSP-OP include those in the following table.

Table 170: Mode Register Function With Two Physical Registers

MR Number MR1
MR2 MR3
MR11 MR12 MR14

Operand OP[2] OP[3] OP[6:4] OP[7] OP[2:0] OP[5:3] OP[6] OP[0] OP[1] OP[5:3] OP[6] OP[7] OP[2:0] OP[6:4] OP[5:0] OP[6] OP[5:0] OP[6]

Function WR-PRE (Write preamble length) RD-PRE (Read preamble type) nWR (Write-recovery for AUTO PRECHARGE command) RD-PST (Read postamble length) RL (READ latency) WL (WRITE latency) WLS (WRITE latency set) PU-CAL (Pull-up calibration point) WR-PST(Write postamble length) PDDS (Pull-down drive strength) DBI-RD (DBI-read enable) DBI-WR (DBI-write enable) DQ ODT (DQ bus receiver on-die termination) CA ODT (CA bus receiver on-die termination) VREF(CA) (VREF(CA) setting) VRCA (VREF(CA) range) VREF(DQ) (VREF(DQ) setting) VRDQ (VREF(DQ) range)

Notes 1

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

296

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Frequency Set Points

Table 170: Mode Register Function With Two Physical Registers (Continued)

MR Number MR22

Operand OP[2:0] OP[3] OP[4] OP[5]

Function SOC ODT (Controller ODT value for VOH calibration) ODTE-CK (CK ODT enabled for non-terminating rank) ODTE-CS (CS ODT enable for non-terminating rank) ODTD-CA (CA ODT termination disable)

Notes

Note: 1. For dual-channel devices, PU-CAL setting is required as the same value for both Ch.A and Ch.B before issuing ZQCAL START command. See Mode Register Definition section for more details.
The table below shows how the two mode registers for each of the parameters in the previous table can be modified by setting the appropriate FSP-WR value and how device operation can be switched between operating points by setting the appropriate FSP-OP value. The FSP-WR and FSP-OP functions operate completely independently.

Table 171: Relation Between MR Setting and DRAM Operation

Function FSP-WR
FSP-OP

MR# and Operand
MR13 OP[6]
MR13 OP[7]

Data 0 (default)
1
0 (default) 1

Operation Data write to mode register N for FSP-OP[0] by MRW command. Data read from mode register N for FSP-OP[0] by MRR command. Data write to mode register N for FSP-OP[1] by MRW command. Data read from mode register N for FSP-OP[1] by MRR command. DRAM operates with mode register N for FSP-OP[0] setting. DRAM operates with mode register N for FSP-OP[1] setting.

Notes 1
2

Notes: 1. FSP-WR stands for frequency set point write/read. 2. FSP-OP stands for frequency set point operating point.
Frequency Set Point Update Timing
The frequency set point update timing is shown below. When changing the frequency set point via MR13 OP[7], the VRCG setting: MR13 OP[3] have to be changed into VREF fast response (high current) mode at the same time. After frequency change time (tFC) is satisfied. VRCG can be changed into normal operation mode via MR13 OP[3].

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

297

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Frequency Set Points

Figure 206: Frequency Set Point Switching Timing

T0

T1

T2

T3

T4

T5

Ta0

CK_c

CK_t

tCKFSPE

CKE CS

Ta1

Tb0 Tb1 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6

FrequencyNote 1 change

tCKFSPX

tVRCG_DISABLE

CA DES

MRW-1

MRW-1

MRW-2

MRW-2

DES

DES

DES DES DES MRW-1 MRW-1 MRW-2 MRW-2 DES

Command DES
Applicable mode register

FSP changes from 0 to 1 VRCG changes from normal to HIGH current Mode register for FSP-OP0

DES

DES

tFC_short/middle/long

DES DES DES

VRCG changes from HIGH current to normal

DES

Switching mode register

Mode register for FSP-OP1

Don't Care
Note: 1. For frequency change during frequency set point switching, refer to Input Clock Stop and Frequency Change section.

Table 172: Frequency Set Point AC Timing

Parameter Frequency set point switching time
Valid clock requirement after entering FSP change Valid clock requirement before first valid command after FSP change

Symbol tFC_short tFC_middle tFC_long tCKFSPE
tCKFSPX

Min/ Max MIN MIN MIN MIN
MIN

1600

Data Rate 3200 3733
200 200 250 MAX(7.5ns, 4nCK)

4267

MAX(7.5ns, 4nCK)

Unit ns ns ns ­

Notes 1

­

Note:

1. Frequency set point switching time depends on value of VREF(CA) setting: MR12 OP[5:0] and VREF(CA) range: MR12 OP[6] of FSP-OP 0 and 1. The details are shown in table below. Additionally change of frequency set point may affect VREF(DQ) setting. Settling time of VREF(DQ) level is the same as VREF(CA) level.

Table 173: tFC Value Mapping

Application
tFC_short
tFC_middle

Step Size

From FSP-OP0

To FSP-OP1

Base

A single step size increment/decrement

Base

Two or more step size increment/decrement

From FSP -OP0 Base

Range

To FSP-OP1 No change

Base

No change

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

298

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Frequency Set Points

Table 173: tFC Value Mapping (Continued)

Application
tFC_long

Step Size From FSP-OP0
­

To FSP-OP1 ­

From FSP -OP0 Base

Range

To FSP-OP1 Change

Note: 1. As well as change from FSP-OP1 to FSP-OP0.

Table 174: tFC Value Mapping: Example

Case 1
2
3

From/To From To From To From To

FSP-OP: MR13 OP[7]
0 1 0 1 0 1

VREF(CA) Setting: MR12: OP[5:0]
001100 001101 001100 001110 Don't Care Don't Care

VREF(CA) Range: MR12 OP[6] 0 0 0 0 0 1

Application tFC_short
tFC_middle
tFC_long

Notes 1
2
3

Notes:

1. A single step size increment/decrement for VREF(CA) setting value. 2. Two or more step size increment/decrement for VREF(CA) setting value. 3. VREF(CA) range is changed. In this case, changing VREF(CA) setting doesn't affect tFC value.

The LPDDR4 SDRAM defaults to FSP-OP[0] at power-up. Both set points default to settings needed to operate in un-terminated, low-frequency environments. To enable the device to operate at higher frequencies, Command bus training mode should be utilized to train the alternate frequency set point. See Command Bus Training section for more details on this training mode.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

299

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Frequency Set Points
Figure 207: Training for Two Frequency Set Points

Power-up/ Initialization
FSP-OP = 0 FSP-WR = 0 Freq. = Boot

Prepare for CA bus training of FSP1 for
high frequency
FSP-OP = 0 FSP-WR = 1 Freq. = Boot

CKE High to Low

CA bus training, FSP-OP1
FSP-WR = 1 Freq. = High

Exit CA bus training
FSP-OP = 0 FSP-WR = 1 Freq. = Boot

CKE LOW to HIGH Switch to highspeed mode
FSP-OP = 1 FSP-WR = 1 Freq. = High

Prepare for CA bus training of FSP0 for medium frequency
FSP-OP = 1 FSP-WR = 0 Freq. = High

CKE HIGH to LOW

CA bus training, FSP-OP0
FSP-WR = 0 Freq. = Medium

CKE LOW to HIGH

Exit CA bus training
FSP-OP = 1 FSP-WR = 0 Freq. = High

Operate at high speed

Once both of the frequency set points have been trained, switching between points can be performed with a single MRW followed by waiting for time tFC. Figure 208: Example of Switching Between Two Trained Frequency Set Points

Operate at high speed

State n-1:

FSP-OP = 1

MRW command

State n: FSP-OP = 0

tFC

Operate at medium speed

State n-1:

FSP-OP = 0

MRW command

State n: FSP-OP = 1

tFC

Operate at high speed

Switching to a third (or more) set point can be accomplished if the memory controller has stored the previously-trained values (in particular the VREF(CA) calibration value) and rewrites these to the alternate set point before switching FSP-OP.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

300

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Pull-Up and Pull-Down Characteristics and Calibration
Figure 209: Example of Switching to a Third Trained Frequency Set Point

Operate at high speed

State n-1:

FSP-WR = 1

MRW command State n: FSP-WR = 0

tFC

MRW command CA O{DVRTE, FD(CQA)ODT, RLO, WDTLD, V-CRAEF.(.D.}Q),

State n-1:

FSP-OP = 1

MRW command

State n: FSP-OP = 0

tFC

Operate at third speed

Pull-Up and Pull-Down Characteristics and Calibration

Table 175: Pull-Down Driver Characteristics ­ ZQ Calibration

RONPD,nom 40 ohms 48 ohms 60 ohms 80 ohms 120 ohms 240 ohms

Register
RON40PD RON48PD RON60PD RON80PD RON120PD RON240PD

Min 0.90 0.90 0.90 0.90 0.90 0.90

Nom 1.0 1.0 1.0 1.0 1.0 1.0

Max 1.10 1.10 1.10 1.10 1.10 1.10

Unit
RZQ/6 RZQ/5 RZQ/4 RZQ/3 RZQ/2 RZQ/1

Note: 1. All value are after ZQ calibration. Without ZQ calibration, RONPD values are ±30%.

Table 176: Pull-Up Characteristics ­ ZQ Calibration

VOHPU,nom VDDQ × 0.5 VDDQ × 0.6

VOH,nom 300 360

Min 0.90 0.90

Nom 1.0 1.0

Max 1.10 1.10

Unit VOH,nom VOH,nom

Notes: 1. All value are after ZQ calibration. Without ZQ calibration, RONPD values are ±30%. 2. VOH,nom (mV) values are based on a nominal VDDQ = 0.6V.

Table 177: Valid Calibration Points

VOHPU VDDQ × 0.5

240 Valid

120 Valid

ODT Value

80

60

Valid

Valid

48 Valid

40 Valid

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

301

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP On-Die Termination for the Command/Address Bus

Table 177: Valid Calibration Points (Continued)

VOHPU VDDQ × 0.6

240 DNU

120 Valid

ODT Value

80

60

DNU

Valid

48 DNU

40 DNU

Notes:

1. After the output is calibrated for a given VOH,nom calibration point, the ODT value may be changed without recalibration.
2. If the VOH,nom calibration point is changed, then recalibration is required. 3. DNU = Do not use.

On-Die Termination for the Command/Address Bus

The on-die termination (ODT) feature allows the device to turn on/off termination resistance for CK_t, CK_c, CS, and CA[5:0] signals without the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to turn on and off termination resistance for any target DRAM devices via the mode register setting.
A simple functional representation of the DRAM ODT feature is shown below.

Figure 210: ODT for CA

RTT =

VOUT |IOUT|

To other circuitry like RCV, ...

VDD2

ODT RTT

IOUT

CA VOUT

VSS

ODT Mode Register and ODT State Table
ODT termination values are set and enabled via MR11. The CA bus (CK_t, CK_c, CS, CA[5:0]) ODT resistance values are set by MR11 OP[6:4]. The default state for the CA is ODT disabled.
ODT is applied on the CA bus to the CK_t, CK_c, CS, and CA signals. Generally only one termination load will be present even if multiple devices are sharing the command signals. In contrast to LPDDR4 where the ODT_CA input is used in combination with mode registers, LPDDR4X uses mode registers exclusively to enable CA termination. Be-

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

302

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP On-Die Termination for the Command/Address Bus

fore enabling CA termination via MR11, all ranks should have appropriate MR22 termination settings programmed. In a multi rank system, the terminating rank should be trained first, followed by the non-terminating rank(s).

Table 178: Command Bus ODT State

CA ODT MR11[6:4] Disabled1
Valid 2 Valid 2 Valid 2 Valid 2 Valid 2 Valid 2 Valid 2 Valid 2

ODTD-CA MR22 OP[5]
Valid2 0 0 0 0 1 1 1 1

ODTE-CK MR22 OP[3]
Valid2 0 0 1 1 0 0 1 1

ODTE-CS MR22 OP[4]
Valid2 0 1 0 1 0 1 0 1

Notes: 1. Default value 2. Valid = 0 or 1
ODT Mode Register and ODT Characteristics

ODT State for CA Off On On On On Off Off Off Off

ODT State for CK Off On On Off Off On On Off Off

ODT State for CS Off On Off On Off On Off On Off

Table 179: ODT DC Electrical Characteristics for Command/Address Bus

RZQ = 240 ±1% over entire operating range after calibration

MR11 OP[6:4]

RTT

VOUT

001b

240

VOL(DC) = 0.2 × VDDQ

VOM(DC) = 0.50 × VDDQ

VOH(DC) = 0.75 × VDDQ

010b

120

VOL(DC) = 0.2 × VDDQ

VOM(DC) = 0.50 × VDDQ

VOH(DC) = 0.75 × VDDQ

011b

80

VOL(DC) = 0.2 × VDDQ

VOM(DC) = 0.50 × VDDQ

VOH(DC) = 0.75 × VDDQ

100b

60

VOL(DC) = 0.2 × VDDQ

VOM(DC) = 0.50 × VDDQ

VOH(DC) = 0.75 × VDDQ

101b

48

VOL(DC) = 0.2 × VDDQ

VOM(DC) = 0.50 × VDDQ

VOH(DC) = 0.75 × VDDQ

Min 0.8 0.9 0.9 0.8 0.9 0.9 0.8 0.9 0.9 0.8 0.9 0.9 0.8 0.9 0.9

Nom 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0

Max 1.1 1.1 1.3 1.1 1.1 1.3 1.1 1.1 1.3 1.1 1.1 1.3 1.1 1.1 1.3

Unit RZQ/1

Notes 1, 2

RZQ/2

1, 2

RZQ/3

1, 2

RZQ/4

1, 2

RZQ/5

1, 2

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

303

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP DQ On-Die Termination

Table 179: ODT DC Electrical Characteristics for Command/Address Bus (Continued)

RZQ = 240 ±1% over entire operating range after calibration

MR11 OP[6:4]

RTT

VOUT

110b

40

VOL(DC) = 0.2 × VDDQ

VOM(DC) = 0.50 × VDDQ

VOH(DC) = 0.75 × VDDQ

Mismatch CA-to-CA within clock group

0.50 × VDDQ

Min 0.8 0.9 0.9 ­

Nom 1.0 1.0 1.0 ­

Max 1.1 1.1 1.3 2

Unit RZQ/6
%

Notes 1, 2
1, 2, 3

Notes:

1. The tolerance limits are specified after calibration with stable temperature and voltage. To understand the behavior of the tolerance limits when voltage or temperature changes after calibration, see the section on voltage and temperature sensitivity.
2. Pull-down ODT resistors are recommended to be calibrated at 0.50 × VDDQ. Other calibration points may be used to achieve the linearity specification shown above, for example, calibration at 0.75 × VDDQ and 0.20 × VDDQ.
3. CA to CA mismatch within clock group variation for a given component including CK_t, CK_c ,and CS (characterized).

CA-to-CA mismatch = RODT (MAX) - RODT (MIN) RODT (AVG)

ODT for CA Update Time

Figure 211: ODT for CA Setting Update Timing in 4-Clock Cycle Command

T0

T1

T2

T3

T4

T5

Ta

Ta1

Ta2

Ta3

Ta4

Ta5

Ta6

Ta7

Ta8

CK_c

CK_t

CKE CS_n

Command DES

MRW1 MRW1 MRW2 MRW2

DES

DES

DES

DES

DES

Valid1 Valid1 Valid1 Valid1

Valid

CA[5:0]

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

Valid

CA ODT

Old setting value

Updating setting tODTUP

New setting value
Don't Care

DQ On-Die Termination
On-die termination (ODT) is a feature that allows the device to turn on/off termination resistance for each DQ, DQS, and DMI signal without the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

304

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP DQ On-Die Termination

DRAM controller to turn on and off termination resistance for any target DRAM devices during WRITE or MASK WRITE operation.
The ODT feature is off and cannot be supported in power-down and self refresh modes.
The switch is enabled by the internal ODT control logic, which uses the WRITE-1 or MASK WRITE-1 command and other mode register control information. The value of RTT is determined by the MR bits.

RTT =

VOUT |IOUT|

Figure 212: Functional Representation of DQ ODT

To other circuitry like RCV, ...

VDDQ

ODT RTT

IOUT

DQ VOUT

VSSQ

Table 180: ODT DC Electrical Characteristics for DQ Bus

RZQ = 240 ±1% over entire operating range after calibration

MR11 OP[2:0]

RTT

VOUT

001b

240

VOL(DC) = 0.2 × VDDQ

VOM(DC) = 0.50 × VDDQ

VOH(DC) = 0.75 × VDDQ

010b

120

VOL(DC) = 0.2 × VDDQ

VOM(DC) = 0.50 × VDDQ

VOH(DC) = 0.75 × VDDQ

011b

80

VOL(DC) = 0.2 × VDDQ

VOM(DC) = 0.50 × VDDQ

VOH(DC) = 0.75 × VDDQ

100b

60

VOL(DC) = 0.2 × VDDQ

VOM(DC) = 0.50 × VDDQ

VOH(DC) = 0.75 × VDDQ

101b

48

VOL(DC) = 0.2 × VDDQ

VOM(DC) = 0.50 × VDDQ

VOH(DC) = 0.75 × VDDQ

Min 0.8 0.9 0.9 0.8 0.9 0.9 0.8 0.9 0.9 0.8 0.9 0.9 0.8 0.9 0.9

Nom 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0

Max 1.1 1.1 1.3 1.1 1.1 1.3 1.1 1.1 1.3 1.1 1.1 1.3 1.1 1.1 1.3

Unit RZQ/1

Notes 1, 2

RZQ/2

1, 2

RZQ/3

1, 2

RZQ/4

1, 2

RZQ/5

1, 2

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

305

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP DQ On-Die Termination

Table 180: ODT DC Electrical Characteristics for DQ Bus (Continued)

RZQ = 240 ±1% over entire operating range after calibration

MR11 OP[2:0]

RTT

VOUT

110b

40

VOL(DC) = 0.2 × VDDQ

VOM(DC) = 0.50 × VDDQ

VOH(DC) = 0.75 × VDDQ

Mismatch DQ-to-DQ within clock group

0.50 × VDDQ

Min 0.8 0.9 0.9 ­

Nom 1.0 1.0 1.0 ­

Max 1.1 1.1 1.3 2

Unit RZQ/6

Notes 1, 2

%

1, 2, 3

Notes:

1. The ODT tolerance limits are specified after calibration with stable temperature and voltage. To understand the behavior of the tolerance limits when voltage or temperature changes after calibration, see the following section on voltage and temperature sensitivity.
2. Pull-down ODT resistors are recommended to be calibrated at 0.50 × VDDQ. Other calibration points may be used to achieve the linearity specification shown above, for example, calibration at 0.75 × VDDQ and 0.20 × VDDQ.
3. DQ-to-DQ mismatch within byte variation for a given component, including DQS (characterized).

DQ-to-DQ mismatch= RODT (MAX) - RODT (MIN) RODT (AVG)

Output Driver and Termination Register Temperature and Voltage Sensitivity
When temperature and/or voltage change after calibration, the tolerance limits are widen according to the tables below.

Table 181: Output Driver and Termination Register Sensitivity Definition

Resistor
RONPD VOHPU RTT(I/O) RTT(IN)

Definition Point
0.50 × VDDQ 0.50 × VDDQ 0.50 × VDDQ 0.50 × VDD2

Min
90 - (dRONdT × |T|) - (dRONdV × |V|) 90 - (dVOHdT × |T|) - (dVOHdV × |V|) 90 - (dRONdT × |T|) - (dRONdV × |V|) 90 - (dRONdT × |T|) - (dRONdV × |V|)

Max
110 + (dRONdT × |T|) + (dRONdV × |V|) 110 + (dVOHdT × |T|) + (dVOHdV × |V|) 110 + (dRONdT × |T|) + (dRONdV × |V|) 110 + (dRONdT × |T|) + (dRONdV × |V|)

Unit %

Notes 1, 2 1, 2
1, 2, 3 1, 2, 4

Notes:

1. T = T - T(@calibration), V = V - V(@calibration) 2. dRONdT, dRONdV, dVOHdT, dVOHdV, dRTTdV, and dRTTdT are not subject to production test
but are verified by design and characterization. 3. This parameter applies to input/output pin such as DQS, DQ, and DMI. 4. This parameter applies to input pin such as CK, CA, and CS. 5. Refer to Pull-Up/Pull-Down Driver Characteristics for VOHPU.

Table 182: Output Driver and Termination Register Temperature and Voltage Sensitivity

Symbol dRONdT dRONdV

Parameter RON temperature sensitivity RON voltage sensitivity

Min 0 0

Max 0.75 0.20

Unit %/°C %/mV

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

306

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP DQ On-Die Termination

Table 182: Output Driver and Termination Register Temperature and Voltage Sensitivity (Continued)

Symbol
dVOHdT dVOHdV dRTTdT dRTTdV

Parameter
VOH temperature sensitivity VOH voltage sensitivity RTT temperature sensitivity RTT voltage sensitivity

Min 0 0 0 0

Max 0.75 0.35 0.75 0.20

Unit %/°C %/mV %/°C %/mV

ODT Mode Register
The ODT mode is enabled if MR11 OP[2:0] are non-zero. In this case, the value of RTT is determined by the settings of those bits. The ODT mode is disabled if MR11 OP[2:0] = 0.

Asynchronous ODT
When ODT mode is enabled in MR11 OP[2:0], DRAM ODT is always High-Z. The DRAM ODT feature is automatically turned ON asynchronously after a WRITE-1, MASK WRITE-1, or MPC[WRITE-FIFO] command. After the burst write is complete, the DRAM ODT turns OFF asynchronously. The DQ bus ODT control is automatic and will turn the ODT resistance on/off if DQ ODT is enabled in the mode register.
The following timing parameters apply when the DQ bus ODT is enabled:
· ODTLon, tODTon(MIN), tODTon(MAX) · ODTLoff, tODToff(MIN), tODToff(MAX)
ODTLON is a synchronous parameter and is the latency from a CAS-2 command to the tODTon reference. ODTLON latency is a fixed latency value for each speed bin. Each speed bin has a different ODTLON latency. Minimum RTT turn-on time ( tODTon(MIN)) is the point in time when the device termination circuit leaves High-Z and ODT resistance begins to turn on.
Maximum RTT turn on time ( tODTon(MAX)) is the point in time when the ODT resistance is fully on.
tODTon(MIN) and tODTon(MAX) are measured after ODTLON latency is satisfied from CAS-2 command.
ODTLOFF is a synchronous parameter and it is the latency from CAS-2 command to tODToff reference. ODTLOFF latency is a fixed latency value for each speed bin. Each speed bin has a different ODTLOFF latency. Minimum RTT turn-off time ( tODToff(MIN)) is the point in time when the device termination circuit starts to turn off the ODT resistance.
Maximum ODT turn off time ( tODToff(MAX)) is the point in time when the on-die termination has reached High-Z.
tODToff(MIN) and tODToff(MAX) are measured after ODTLOFF latency is satisfied from CAS-2 command.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

307

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP DQ On-Die Termination

Table 183: ODTLON and ODTLOFF Latency Values

ODTLON Latency1 tWPRE = 2tCK

WL Set A (nCK) WL Set B (nCK)

N/A

N/A

N/A

N/A

N/A

6

4

12

4

14

6

18

6

20

8

24

ODTLOFF Latency2 WL Set A (nCK) WL Set B (nCK)

N/A

N/A

N/A

N/A

N/A

22

20

28

22

32

24

36

26

40

28

44

Lower Frequency Limit
(>) (MHz) 10 266 533 800
1066 1333 1600 1866

Upper Frequency Limit
() (MHz) 266 533 800 1066 1333 1600 1866 2133

Notes: 1. ODTLON is referenced from CAS-2 command. 2. ODTLOFF as shown in table assumes BL = 16. For BL32, 8 tCK should be added.

Figure 213: Asynchronous ODTon/ODToff Timing
T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Ta9 Ta10 Ta11 Ta12 Ta13 Ta14 Ta15 Ta16 Ta17 Ta18 Ta19 Ta20 Ta21 CK_c CK_t
CS

CA

BL

BA0, CA, AP

CAn

CAn

Command WRITE-1

CAS-2

DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES

WL

tDQSS(MIN)

DQS_c DQS_t
DQ DMI
DQS_c DQS_t
DQ DMI
DRAM RTT

ODTLon tODTon(MIN) ODT High-Z

tODTon(MAX) Transition

t WPRE

t WPST

tDQS2DQ

DIN n0

DIN DIN n1 n2

DIN n3

DIN n4

DIN n5

DIN n6

DIN n7

DIN n8

DIN n9

DIN DIN DIN DIN DIN DIN n10 n11 n12 n13 n14 n15

tDQSS(MAX)

t WPRE

t WPST

tDQS2DQ

DIN n0

DIN DIN n1 n2

DnI3N

DnIN4

DIN n5

DnI6N

DnI7N

DIN n8

DIN n9

DIN DIN DIN DIN DIN DIN n10 n11 n12 n13 n14 n15

ODTLoff

ODTL On

tODToff(MIN)

tODToff(MAX) Transition ODT High-Z Don't Care

Notes: 1. BL = 16, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination. 2. DIN n = data-in to column n.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

308

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP DQ On-Die Termination

3. DES commands are shown for ease of illustration; other commands may be valid at these times.
DQ ODT During Power-Down and Self Refresh Modes
DQ bus ODT will be disabled in power-down mode. In self refresh mode, the ODT will be turned off when CKE is LOW but will be enabled if CKE is HIGH and DQ ODT is enabled in the mode register.
ODT During Write Leveling Mode
If ODT is enabled in MR11 OP[2:0] in write leveling mode, the device always provides the termination on DQS signals. DQ termination is always off in write leveling mode.

Table 184: Termination State in Write Leveling Mode

ODT State in MR11 OP[2:0] Disabled Enabled

DQS Termination Off On

DQ[15:0]/DMI[1:0] Termination
Off
Off

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

309

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Target Row Refresh Mode
Target Row Refresh Mode
The device limits the number of times that a given row can be accessed within a refresh period (tREFW × 2) prior to requiring adjacent rows to be refreshed. The maximum activate count (MAC) is the maximum number of activates that a single row can sustain within a refresh period before the adjacent rows need to be refreshed. The row receiving the excessive actives is the target row (TRn), the adjacent rows to be refreshed are the victim rows. When the MAC limit is reached on TRn, either the device receives all (R × 2) REFRESH commands before another row activate is issued, or the device should be placed into targeted row refresh (TRR) mode. The TRR mode will refresh the rows adjacent to the TRn that encountered tMAC limit.
If the device supports unlimited MAC value: MR24 OP[2:0] = 000 and MR24 OP[3] = 1, TARGET ROW REFRESH operation is not required. Even though the device allows to set MR24 OP[7] = 1: TRR mode enable, in this case the device behavior is vendor specific. For example, a certain device may ignore MRW command for entering/exiting TRR mode or a certain device may support commands related TRR mode. See vendor device data sheets for details about TRR mode definition at supporting unlimited MAC value case.
There could be a maximum of two target rows to a victim row in a bank. The cumulative value of the activates from the two target rows on a victim row in a bank should not exceed MAC value.
MR24 fields are required to support the new TRR settings. Setting MR24 OP[7] = 1 enables TRR mode and setting MR24 OP[7] = 0 disables TRR mode. MR24 OP[6:4] defines which bank (BAn) the target row is located in (refer to MR24 table for details).
The TRR mode must be disabled during initialization as well as any other device calibration modes. The TRR mode is entered from a DRAM idle state, once TRR mode has been entered, no other mode register commands are allowed until TRR mode is completed; however, setting MR24 OP[7] = 0 to interrupt and reissue the TRR mode is allowed.
When enabled, TRR mode is self-clearing. the mode will be disabled automatically after the completion of defined TRR flow (after the third BAn precharge has completed plus tMRD). Optionally, the TRR mode can also be exited via another MRS command at the completion of TRR by setting MR24 OP[7] = 0. If the TRR is exited via another MRS command, the value written to MR24 OP[6:4] are "Don't Care."
TRR Mode Operation
1. The timing diagram depicts TRR mode. The following steps must be performed when TRR mode is enabled. This mode requires all three ACT (ACT1, ACT2, and ACT3) and three corresponding PRE commands (PRE1, PRE2, and PRE3) to complete TRR mode. PRECHARGE All (PREA) commands issued while the device is in TRR mode will also perform precharge to BAn and counts towards PREn command.
2. Prior to issuing the MRW command to enter TRR mode, the device should be in the idle state. MRW command must be issued with MR24 OP[7] = 1 and MR24 OP[6:4] defining the bank in which the targeted row is located. All other MR24 bits should remain unchanged.
3. No activity is to occur with the device until tMRD has been satisfied. When tMRD has been satisfied, the only commands allowed BAn, until TRR mode has completed, are ACT and PRE.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

310

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Target Row Refresh Mode
4. The first ACT to the BAn with the TRn address can now be applied; no other command is allowed at this point. All other banks must remain inactive from when the first BAn ACT command is issued until [(1.5 x tRAS) + tRP] is satisfied.
5. After the first ACT to the BAn with the TRn address is issued, PRE to BAn is to be issued (1.5 × tRAS) later; and then followed tRP later by the second ACT to the BAn with the TRn address.
6. After the second ACT to the BAn with the TRn address is issued, PRE to BAn is to be issued tRAS later and then followed tRP later by the third ACT to the BAn with the TRn address.
7. After the third ACT to the BAn with the TRn address is issued, PRE to BAn would be issued tRAS later. TRR mode is completed once tRP plus tMRD is satisfied.
8. TRR mode must be completed as specified to guarantee that adjacent rows are refreshed. Anytime the TRR mode is interrupted and not completed, the interrupted TRR mode must be cleared and then subsequently performed again. To clear an interrupted TRR mode, MR24 change is required with setting MR24 OP[7] = 0, MR24 OP[6:4] are "Don't Care," followed by three PRE to BAn, with tRP time in between each PRE command. The complete TRR sequence (steps 2­7) must be then reissued and completed to guarantee that the adjacent rows are refreshed.
9. A REFRESH command to the device, or entering self refresh mode, is not allowed while the device is in TRR mode.

Figure 214: Target Row Refresh Mode

T0 T1 T2 T3 CK_c
CK_t

Ta0 Ta1 Ta2 Ta3

Tb0 Tb1

Tc0 Tc1 Tc2 Tc3

Td0 Td1 Td2 Td3

Te0 Te1

Tf0 Tf1 Tf2 Tf3

Tg0 Tg1 Tg2 Tg3

Th0 Th1 Th2 Th3

Tk0 Tk1 Tk2 Tm0 Tm1 Tm2 Tm3 Tm4 Tm5

CKE

CS Command MRW-1

ACT1

PRE1

ACT2

MRW-2 DES ACT-1

ACT-2

DES

PRE

DES ACT-1

ACT-2 DES

TRR entry

Bank Address

N/A

N/A N/A

N/A

1st ACT
N/A BAn N/A N/A

1st PRE
N/A BAn

2nd ACT
N/A BAn N/A N/A

CMD-1

V

Non BAn

CMD-2 VV

PRE2

DES

PRE

DES

2nd PRE
N/A BAn

CMD-1

V

Non BAn

CMD-2 VV

ACT3

DES ACT-1

ACT-2 DES

3rd ACT
N/A BAn N/A N/A

CMD-1

V

Non BAn

CMD-2 VV

PRE3

DES

PRE

DES DES

3rd PRE
N/A BAn

CMD-1

V

Any BAn

CMD-2 DES VV

Address OP MA OP OP

TRn TRn TRn TRn

N/A N/A

TRn TRn TRn TRn

V

VV

V

N/A N/A

V

VV V

TRn TRn TRn TRn

V

VV

V

N/A N/A

V

VV

V

Non BAn

Non BAn in idle

tMRD

1.5 × tRAS

tRP

No activity allowed in other banks (Banks closed)

tRAS

t RP Activity allowed

tRAS

tRP + tMRD No activity allowed (may have bank(s) open)

Activity allowed

BAn

BAn in idle

No activity allowed (Banks closed)

BAn TRR operation9allowed

Activity allowed
Don't Care

Notes: 1. TRn is the targeted row. 2. Bank BAn represents the bank in which the targeted row is located. 3. TRR mode self-clears after tMRD + tRP measured from the third BAn precharge PRE3 at clock edge Th4. 4. TRR mode or any other activity can be re-engaged after tRP + tMRD from the third BAn precharge PRE3. PRE_ALL also counts if it is issued instead of PREn. TRR mode is cleared by the device after PRE3 to the BAn bank.
5. ACTIVATE commands to BAn during TRR mode do not provide refresh support (the refresh counter is unaffected).
6. The device must restore the degraded row(s) caused by excessive activation of the targeted row (TRn) necessary to meet refresh requirements.
7. A new TRR mode must wait tMRD + tRP time after the third precharge.
8. BAn may not be used with any other command.
9. ACT and PRE are the only allowed commands to BAn during TRR mode.
10. REFRESH commands are not allowed during TRR mode.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

311

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Post-Package Repair
11. All timings are to be met by DRAM during TRR mode, such as tFAW. Issuing ACT1, ACT2, and ACT3 counts towards tFAW budget.
Post-Package Repair
The device has fail row address repair as an optional post-package repair (PPR) feature and it is readable through MR25 OP[7:0]. PPR provides simple and easy repair method in the system and fail row address can be repaired by the electrical programming of Electrical-fuse scheme. The device can correct one row per bank with PPR. Electrical-fuse cannot be switched back to un-fused states once it is programmed. The controller should prevent unintended PPR mode entry and repair.
Failed Row Address Repair
1. Before entering PPR mode, all banks must be precharged. 2. Enable PPR using MR4 OP[4] = 1 and wait tMRD. 3. Issue ACT command with fail row address. 4. Wait tPGM to allow the device repair target row address internally then issue PRE-
CHARGE 5. Wait tPGM_EXIT after PRECHARGE, which allows the device to recognize repaired
row address RAn. 6. Exit PPR mode with setting MR4 OP[4] = 0. 7. The device is ready for any valid command after tPGMPST. 8. In more than one fail address repair case, repeat step 2 to 7. Once PPR mode is exited, to confirm whether the target row has correctly repaired, the host can verify the repair by writing data into the target row and reading it back after PPR exit with MR4 OP[4] = 0 and tPGMPST. The following timing diagram shows PPR operation.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

312

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Post-Package Repair

Figure 215: Post-Package Repair Timing

CK_c CK_t

T0 T1

T2 T3 T4

T5 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tb3 Tb4 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Td0 Td1 Td2 Td3 Td4 Td5

CKE CS

Command DES MR WRITE-1 MR WRITE-2 DES

ACT-1

ACT-2

DES

BA

N/A N/A N/A N/A

Valid BA Valid Valid

DES

PRE DES

Valid Valid

MR WRITE-1 MR WRITE-2 DES N/A N/A N/A N/A

Any command

comAmnyand

Valid Valid Valid Valid

Address

OP MA OP OP

PPR staus

Normal mode (All banks must be idle)

RAn RAn RAn RAn
Move to PPR mode tMRD

Valid Valid
PPR repair tPGM

OP MA OP OP
PPR recognition tPGM_Exit

Valid Valid Valid Valid

Move to PPR mode tPGMPST

Normal mode

Don't Care

Notes:

1. During tPGM, any other commands (including refresh) are not allowed on each die. 2. With one PPR command, only one row can be repaired at one time per die. 3. When PPR procedure completes, reset procedure is required before normal operation. 4. During PPR, memory contents are not refreshed and may be lost.

Table 185: Post-Package Repair Timing Parameters

Parameter PPR programming time PPR exit time New address setting time

Symbol tPGM
tPGM_EXIT tPGMPST

Min 1000
15 50

Max ­ ­ ­

Units ms ns µs

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

313

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Read Preamble Training
Read Preamble Training
Read preamble training is supported through the MPC function.
This mode can be used to train or read level the DQS receivers. After read preamble training is enabled by MR13 OP[1] = 1, the device will drive DQS_t LOW and DQS_c HIGH within tSDO and remain at these levels until an MPC[READ DQ CALIBRATION] command is issued.
During read preamble training, the DQS preamble provided during normal operation will not be driven by the device. After the MPC[READ DQ CALIBRATION] command is issued, the device will drive DQS_t/DQS_c and DQ like a normal READ burst after RL and tDQSCK. Prior to the MPC[READ DQ CALIBRATION] command, the device may or may not drive DQ[15:0] in this mode.
While in read preamble training mode, only READ DQ CALIBRATION commands may be issued.
· Issue an MPC[READ DQ CALIBRATION] command followed immediately by a CAS-2 command.
· Each time an MPC[READ DQ CALIBRATION] command followed by a CAS-2 is received by the device, a 16-bit data burst will, after the currently set RL, drive the eight bits programmed in MR32 followed by the eight bits programmed in MR40 on all I/O pins.
· The data pattern will be inverted for I/O pins with a 1 programmed in the corresponding invert mask mode register bit.
· Note that the pattern is driven on the DMI pins, but no DATA BUS INVERSION function is enabled, even if read DBI is enabled in the DRAM mode register.
· This command can be issued every tCCD seamlessly. · The operands received with the CAS-2 command must be driven LOW.
Read preamble training is exited within tSDO after setting MR13 OP[1] = 0.

Figure 216: Read Preamble Training
T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tc0 Tc1 Tc2 Tc3 Tc4 Td0 Td1 Td2 Td3 Td4 Td5 Te0 Te1 CK_c CK_t
CS

Command MRW-1 MRW-1 MRW-2 MRW-2 DES

DES

DES

MPC [RD DQ CAL]

[RDMDPQCCAL]

CAS-2

CAS-2

DES

DES

DES

DES

DES

DES

DES

DES

DES MRW-1 MRW-1 MRW-2 MRW-2 DES

DES

DES

DQS_c DQS_t
DQ DMI

tSDO
Read preamble training mode = Enable: MR13[OP1] = 1

RL DQ (High-Z or Driven )

tDQSCK

tDQSQ

DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n12 n13 n14 n15

tSDO Read preamble training mode =
Enable: MR13[OP1] = 0
DQ (High-Z or Driven )

Don't Care

Note: 1. Read DQ calibration supports only BL16 operation.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

314

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Electrical Specifications
Electrical Specifications
Absolute Maximum Ratings
Stresses greater than those listed in the table below may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these conditions, or any other conditions outside those indicated in the operational sections of this document, is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability.

Table 186: Absolute Maximum DC Ratings

Parameter
VDD1 supply voltage relative to VSS VDD2 supply voltage relative to VSS VDDQ supply voltage relative to VSS Voltage on any ball relative to VSS Storage temperature

Symbol
VDD1 VDD2 VDDQ VIN, VOUT TSTG

Min ­0.4 ­0.4 ­0.4 ­0.4 ­55

Max 2.1 1.5 1.5 1.5 125

Unit V V V V °C

Notes 1 1 1
2

Notes:

1. For information about relationships between power supplies, see the Voltage Ramp and Device Initialization section.
2. Storage temperature is the case surface temperature on the center/top side of the device. For measurement conditions, refer to the JESD51-2 standard.

AC and DC Operating Conditions
Operation or timing that is not specified is illegal. To ensure proper operation, the device must be initialized properly.

Table 187: Recommended DC Operating Conditions

Symbol VDD1 VDD2 VDDQ

Min 1.7 1.06 0.57

Typ 1.8 1.1 0.60

Max 1.95 1.17 0.65

DRAM Core 1 power Core 2 power/Input buffer power I/O buffer power

Unit V V V

Notes 1, 2
1, 2, 3 2, 3

Notes:

1. VDD1 uses significantly less power than VDD2. 2. The voltage range is for DC voltage only. DC voltage is the voltage supplied at the
DRAM and is inclusive of all noise up to 20 MHz at the DRAM package ball.
3. The voltage noise tolerance from DC to 20 MHz exceeding a peak-to-peak tolerance of 45mV at the DRAM ball is not included in the TdIVW.

Table 188: Input Leakage Current

Parameter/Condition Input leakage current

Symbol IL

Min ­4

Max 4

Unit A

Notes 1, 2

Notes: 1. For CK_t, CK_c, CKE, CS, CA, ODT_CA and RESET_n. Any input 0V  VIN  VDD2. All other pins not under test = 0V.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

315

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP AC and DC Operating Conditions

2. CA ODT is disabled for CK_t, CK_c, CS, and CA.

Table 189: Input/Output Leakage Current

Parameter/Condition Input/Output leakage current

Symbol IOZ

Min ­5

Max 5

Notes: 1. For DQ, DQS_t, DQS_c and DMI. Any I/O 0V  VOUT  VDDQ. 2. I/Os status are disabled: High impedance and ODT off.

Unit A

Notes 1, 2

Table 190: Operating Temperature Range

Parameter/Condition Standard Elevated Automotive Ultra

Symbol TOPER

Min Note 4
85 95 105

Max 85 95 105 125

Unit °C °C °C °C

Notes:

1. Operating temperature is the case surface temperature at the center of the top side of the device. For measurement conditions, refer to the JESD51-2 standard.
2. When using the device in the elevated temperature range, some derating may be required. See Mode Registers for vendor-specific derating.
3. Either the device case temperature rating or the temperature sensor can be used to set an appropriate refresh rate, determine the need for AC timing derating, and/or monitor the operating temperature (see Temperature Sensor). When using the temperature sensor, the actual device case temperature may be higher than the TOPER rating that applies for the standard or elevated temperature range. For example, TCASE could be above +85°C when the temperature sensor indicates a temperature of less than +85°C.
4. Refer to operating temperature range on top page.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

316

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP AC and DC Input Measurement Levels
AC and DC Input Measurement Levels
Input Levels for CKE

Table 191: Input Levels

Parameter Input HIGH level (AC) Input LOW level (AC) Input HIGH level (DC) Input LOW level (DC)

Symbol
VIH(AC) VIL(AC) VIH(DC) VIL(DC)

Min 0.75 × VDD2
­0.2 0.65 × VDD2
­0.2

Note: 1. See the AC Overshoot and Undershoot section.

Figure 217: Input Timing Definition for CKE

Input level

VIH(AC) VIL(AC)

VIH(DC) VIL(DC)

Max
VDD2 + 0.2 0.25 × VDD2 VDD2 + 0.2 0.35 × VDD2

Unit V V V V

Notes 1 1

Don't Care

Input Levels for RESET_n

Table 192: Input Levels

Parameter Input HIGH level Input LOW level

Symbol VIH VIL

Min 0.80 × VDD2
­0.2

Note: 1. See the AC Overshoot and Undershoot section.

Figure 218: Input Timing Definition for RESET_n

VIH

VIH

Input

level

VIL

VIL

Max VDD2 + 0.2 0.20 × VDD2

Unit V V

Notes 1 1

Don't Care

Differential Input Voltage for CK
The minimum input voltage needs to satisfy both Vindiff_CK and Vindiff_CK/2 specification at input receiver and their measurement period is 1tCK. Vindiff_CK is the peak-to-peak

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

317

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP AC and DC Input Measurement Levels
voltage centered on 0 volts differential and Vindiff_CK/2 is maximum and minimum peak voltage from 0 volts. Figure 219: CK Differential Input Voltage
Peak voltage

Vindiff_CK/2

Vindiff_CK

Differential Input Voltage : CK_t - CK_c

0.0

Vindiff_CK/2

Peak voltage
Time

Table 193: CK Differential Input Voltage

Parameter CK differential input voltage

Symbol Vindiff_CK

1600/1867

Min Max

420

­

2133/2400/3200

Min Max

380

­

3733/4267

Min Max

360

­

Unit mV

Note 1

Note:

1. The peak voltage of differential CK signals is calculated in a following equation.
· Vindiff_CK = (Maximum peak voltage) - (Minimum peak voltage) · Maximum peak voltage = MAX(f(t)) · Minimum peak voltage = MIN(f(t)) · f(t) = VCK_t - VCK_c

Peak Voltage Calculation Method

The peak voltage of differential clock signals are calculated in a following equation.
· VIH.DIFF.peak voltage = MAX(f(t)) · VIL.DIFF.peak voltage = MIN(f(t)) · f(t) = VCK_t - VCK_c

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

318

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP AC and DC Input Measurement Levels
Figure 220: Definition of Differential Clock Peak Voltage

CK_t VREF(CA)

Min(f(t))

Max(f(t))

Single Ended Input Voltage

CK_c

Note: 1. VREF(CA) is device internal setting value by VREF training.

Time

Single-Ended Input Voltage for Clock
The minimum input voltage need to satisfy Vinse_CK, Vinse_CK_HIGH, and Vinse_CK_LOW specification at input receiver.

Figure 221: Clock Single-Ended Input Voltage

CK_t

Vinse_CK_HIGH

Vinse_CK_HIGH

Vinse_CK

Vinse_CK

Single Ended Input Voltage

VREF(CA)

Vinse_CK_LOW

Vinse_CK_LOW

CK_c Note: 1. VREF(CA) is device internal setting value by VREF training.

Time

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

319

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP AC and DC Input Measurement Levels

Table 194: Clock Single-Ended Input Voltage

Parameter
Clock single-ended input voltage
Clock single-ended input voltage HIGH from VREF(CA) Clock single-ended input voltage LOW from VREF(CA)

Symbol Vinse_CK
Vinse_CK_HIGH
Vinse_CK_LOW

1600/1867

Min

Max

210

­

2133/2400/3200

Min

Max

190

­

3733/4267

Min

Max

180

­

105

­

95

­

90

­

105

­

95

­

90

­

Unit mV
mV
mV

Differential Input Slew Rate Definition for Clock
Input slew rate for differential signals (CK_t, CK_c) are defined and measured as shown below in figure and the tables.

Figure 222: Differential Input Slew Rate Definition for CK_t, CK_c

Peak Voltage
VIHdiff_CK

0.0

Differential Input Voltage : f(t) = CK_t - CK_c

Delta TFdiff

Delta TRdiff

VILdiff_CK Peak Voltage
Time

Notes: 1. Differential signal rising edge from VILdiff_CK to VIHdiff_CK must be monotonic slope. 2. Differential signal falling edge from VIHdiff_CK to VILdiff_CK must be monotonic slope.

Table 195: Differential Input Slew Rate Definition for CK_t, CK_c

Description
Differential input slew rate for rising edge (CK_t - CK_c)
Differential input slew rate for falling edge (CK_t - CK_c)

From VILdiff_CK
VIHdiff_CK

To VIHdiff_CK
VILdiff_CK

Defined by |VILdiff_CK - VIHdiff_CK|/TRdiff
|VILdiff_CK - VIHdiff_CK|/TFdiff

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

320

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP AC and DC Input Measurement Levels

Table 196: Differential Input Level for CK_t, CK_c

Parameter Differential Input HIGH Differential Input LOW

Symbol VIHdiff_CK VILdiff_CK

1600/1867

Min

Max

175

­

­

­175

2133/2400/3200

Min

Max

155

­

­

­155

3733/4267

Min

Max

145

­

­

­145

Unit mV mV

Table 197: Differential Input Slew Rate for CK_t, CK_c

Parameter
Differential input slew rate for clock

Symbol SRIdiff_CK

1600/1867

Min

Max

2

14

2133/2400/3200

Min

Max

2

14

3733/4267

Min

Max

2

14

Unit V/ns

Differential Input Cross-Point Voltage
The cross-point voltage of differential input signals (CK_t, CK_c) must meet the requirements in table below. The differential input cross-point voltage VIX is measured from the actual cross-point of true and complement signals to the mid level that is VREF(CA).
Figure 223: Vix Definition (Clock)
VDD

CK_t

VREF(CA)

ViX_CK_FR Min(f(t))

Max(f(t)) ViX_CK_RF

ViX_CK_FR

ViX_CK_RF

Single-Ended Input Voltage

CK_c VSS Time
Note: 1. The base levels of Vix_CK_FR and Vix_CK_RF are VREF(CA) that is device internal setting value by VREF training.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

321

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP AC and DC Input Measurement Levels

Table 198: Cross-Point Voltage for Differential Input Signals (Clock)

Notes 1 and 2 apply to entire table

Parameter
Clock differential input cross-point voltage ratio

Symbol Vix_CK_ratio

1600/1867

Min

Max

­

25

2133/2400/3200

Min

Max

­

25

3733/4267

Min

Max

­

25

Unit %

Notes: 1. Vix_CK_ratio is defined by this equation: Vix_CK_ratio = Vix_CK_FR/|MIN(f(t))| 2. Vix_CK_ratio is defined by this equation: Vix_CK_ratio = Vix_CK_RF/MAX(f(t))
Differential Input Voltage for DQS
The minimum input voltage needs to satisfy both Vindiff_DQS and Vindiff_DQS/2 specification at input receiver and their measurement period is 1UI (tCK/2). Vindiff_DQS is the peak to peak voltage centered on 0 volts differential and Vindiff_DQS/2 is maximum and minimum peak voltage from 0 volts.
Figure 224: DQS Differential Input Voltage

Peak voltage

Vindiff_DQS /2

Vindiff_DQS

Differential Input Voltage : DQS_t - DQS_c

0.0

Vindiff_DQS /2

Peak voltage
Time

Table 199: DQS Differential Input Voltage

Parameter DQS differential input voltage

Symbol Vindiff_DQS

1600/1867

Min Max

360

­

2133/2400/3200

Min Max

360

­

3733/4267

Min Max

340

­

Unit mV

Note 1

Note:

1. The peak voltage of differential DQS signals is calculated in a following equation.
· Vindiff_DQS = (Maximum peak voltage) - (Minimum peak voltage) · Maximum peak voltage = MAX(f(t)) · Minimum peak voltage = MIN(f(t)) · f(t) = VDQS_t - VDQS_c

Peak Voltage Calculation Method

The peak voltage of differential DQS signals are calculated in a following equation.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

322

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP AC and DC Input Measurement Levels
· VIH.DIFF.peak voltage = MAX(f(t)) · VIL.DIFF.peak voltage = MIN(f(t)) · f(t) = VDQS_t - VDQS_c Figure 225: Definition of Differential DQS Peak Voltage

DQS_t VREF(DQ)

Min(f(t))

Max(f(t))

Single Ended Input Voltage

DQS_c

Note: 1. VREF(DQ) is device internal setting value by VREF training.

Time

Single-Ended Input Voltage for DQS
The minimum input voltage need to satisfy Vinse_DQS, Vinse_DQS_HIGH, and Vinse_DQS_LOW specification at input receiver.

Figure 226: DQS Single-Ended Input Voltage

DQS_t

inse_DQS_HIGH V

inse_DQS_HIGH V

inse_DQS V inse_DQS_LOW V

inse_DQS V inse_DQS_LOW V

Single Ended Input Voltage

VREF(DQ)

DQS_c Note: 1. VREF(DQ) is device internal setting value by VREF training.

Time

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

323

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP AC and DC Input Measurement Levels

Table 200: DQS Single-Ended Input Voltage

Parameter
DQS single-ended input voltage
DQS single-ended input voltage HIGH from VREF(DQ) DQS single-ended input voltage LOW from VREF(DQ)

Symbol Vinse_DQS
Vinse_DQS_HIGH
Vinse_DQS_LOW

1600/1867

Min

Max

180

­

2133/2400/3200

Min

Max

180

­

3733/4267

Min

Max

170

­

90

­

90

­

85

­

90

­

90

­

85

­

Unit mV
mV
mV

Differential Input Slew Rate Definition for DQS
Input slew rate for differential signals (DQS_t, DQS_c) are defined and measured as shown below in figure and the tables.

Figure 227: Differential Input Slew Rate Definition for DQS_t, DQS_c

Peak Voltage
VIHdiff_CK

0.0

Differential Input Voltage : f(t) = CK_t - CK_c

Delta TFdiff

Delta TRdiff

VILdiff_CK Peak Voltage
Time

Notes: 1. Differential signal rising edge from VILdiff_DQS to VIHdiff_DQS must be monotonic slope. 2. Differential signal falling edge from VIHdiff_DQS to VILdiff_DQS must be monotonic slope.

Table 201: Differential Input Slew Rate Definition for DQS_t, DQS_c

Description
Differential input slew rate for rising edge (DQS_t - DQS_c)
Differential input slew rate for falling edge (DQS_t - DQS_c)

From VILdiff_DQS
VIHdiff_DQS

To VIHdiff_DQS

Defined by |VILdiff_DQS - VIHdiff_DQS|/TRdiff

VILdiff_DQS

|VILdiff_DQS - VIHdiff_DQS|/TFdiff

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

324

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP AC and DC Input Measurement Levels

Table 202: Differential Input Level for DQS_t, DQS_c

Parameter Differential Input HIGH Differential Input LOW

Symbol VIHdiff_DQS VILdiff_DQS

1600/1867

Min

Max

140

­

­

­140

2133/2400/3200

Min

Max

140

­

­

­140

3733/4267

Min

Max

120

­

­

­120

Unit mV mV

Table 203: Differential Input Slew Rate for DQS_t, DQS_c

Parameter Differential input slew rate

Symbol SRIdiff

1600/1867

Min

Max

2

14

2133/2400/3200

Min

Max

2

14

3733/4267

Min

Max

2

14

Unit V/ns

Differential Input Cross-Point Voltage
The cross-point voltage of differential input signals (DQS_t, DQS_c) must meet the requirements in table below. The differential input cross-point voltage VIX is measured from the actual cross-point of true and complement signals to the mid level that is VREF(DQ).
Figure 228: Vix Definition (DQS)
VDDQ

DQS_t

VREF(DQ)

ViX_DQS_FR Min(f(t))

Max(f(t)) ViX_DQS_RF

ViX_DQS_FR

ViX_DQS_RF

Single-Ended Input Voltage

DQS_c VSSQ Time
Note: 1. The base levels of Vix_DQS_FR and Vix_DQS_RF are VREF(DQ) that is device internal setting value by VREF training.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

325

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Output Slew Rate and Overshoot/Undershoot specifications

Table 204: Cross-Point Voltage for Differential Input Signals (DQS)

Notes 1 and 2 apply to entire table

Parameter
DQS differential input cross-point voltage ratio

Symbol Vix_DQS_ratio

1600/1867

Min

Max

­

20

2133/2400/3200

Min

Max

­

20

3733/4267

Min

Max

­

20

Notes: 1. Vix_DQS_ratio is defined by this equation: Vix_DQS_ratio = Vix_DQS_FR/|MIN(f(t))| 2. Vix_DQS_ratio is defined by this equation: Vix_DQS_ratio = Vix_DQS_RF/MAX(f(t))
Input Levels for ODT_CA

Table 205: Input Levels for ODT_CA
Parameter ODT input HIGH level ODT input LOW level

Symbol VIHODT VILODT

Min 0.75 × VDD2
­0.2

Max VDD2 + 0.2 0.25 × VDD2

Unit %
Unit V V

Output Slew Rate and Overshoot/Undershoot specifications
Single-Ended Output Slew Rate

Table 206: Single-Ended Output Slew Rate Note 1-5 applies to entire table
Parameter Single-ended output slew rate (VOH = VDDQ x 0.5) Output slew rate matching ratio (rise to fall)

Symbol SRQse ­

Min 3.0 0.8

Value

Max 9.0 1.2

Units V/ns
­

Notes:

1. SR = Slew rate; Q = Query output; se = Single-ended signal.
2. Measured with output reference load.
3. The ratio of pull-up to pull-down slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation.
4. The output slew rate for falling and rising edges is defined and measured between VOL(AC) = 0.2 × VOH(DC) and VOH(AC) = 0.8 × VOH(DC).
5. Slew rates are measured under average SSO conditions with 50% of the DQ signals per data byte switching.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

326

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Output Slew Rate and Overshoot/Undershoot specifications

Figure 229: Single-Ended Output Slew Rate Definition

TRSE

Single-Ended Output Voltage (DQ)

VOH(AC) VCENT VOL(AC)

TFSE

Time

Differential Output Slew Rate

Table 207: Differential Output Slew Rate Note 1-4 applies to entire table
Parameter Differential output slew rate (VOH = VDDQ x 0.5)

Symbol SRQdiff

Min 6

Value

Max 18

Units V/ns

Notes:

1. SR = Slew rate; Q = Query output; se = Differential signal.
2. Measured with output reference load.
3. The output slew rate for falling and rising edges is defined and measured between VOL(AC) = ­0.8 × VOH(DC) and VOH(AC) = 0.8 × VOH(DC).
4. Slew rates are measured under average SSO conditions with 50% of the DQ signals per data byte switching.

Figure 230: Differential Output Slew Rate Definition

TRdiff

Differential Output Voltage (DQ)

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

0

TFdiff

Time

327

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Driver Output Timing Reference Load
Overshoot and Undershoot Specifications

Table 208: AC Overshoot/Undershoot Specifications

Parameter
Maximum peak amplitude provided for overshoot area
Maximum peak amplitude provided for undershoot area
Maximum area above VDD/ VDDQ Maximum area below VSS/ VSSQ

MAX
MAX
MAX MAX

1600 0.3
0.3
0.1 0.1

1866 0.3
0.3
0.1 0.1

3200 0.3
0.3
0.1 0.1

3733 0.3
0.3
0.1 0.1

4267 0.3

Unit V

0.3

V

0.1

V-ns

0.1

V-ns

Notes:

1. VDD stands for VDD2 for CA[5:0], CK_t, CS_n, CKE, and ODT. VDD stands for VDDQ for DQ, DMI, DQS_t, and DQS_c.
2. VSS stands for VSS for CA[5:0], CK_t, CK_c, CS_n, CKE, and ODT. VSS stands for VSSQ for DQ, DMI, DQS_t, and DQS_c.
3. Maximum peak amplitude values are referenced from actual VDD and VSS values. 4. Maximum area values are referenced from maximum VDD and VSS values.

Table 209: Overshoot/Undershoot Specification for CKE and RESET
Parameter Maximum peak amplitude provided for overshoot area Maximum peak amplitude provided for undershoot area Maximum area above VDD Maximum area below VSS
Figure 231: Overshoot and Undershoot Definition
Maximum amplitude

Specification 0.35V 0.35V
0.8 V-ns 0.8 V-ns
Overshoot area

Volts (V)

VDD

Time (ns)

VSS

Maximum amplitude

Undershoot area

Driver Output Timing Reference Load
Timing reference loads are not intended as a precise representation of any particular system environment or depiction of an actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

328

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LVSTL I/O System
Figure 232: Driver Output Timing Reference Load
DRAM
50 ohms

Note: 1. All output timing parameter values are reported with respect to this reference load; this reference load is also used to report slew rate.
LVSTL I/O System
LVSTL I/O cells are comprised of a driver pull-up and pull-down and a terminator. Figure 233: LVSTL I/O Cell
VDDQ

Pull-Up Pull-Down

DQ
ODT Enabled when receiving

VSSQ

VSSQ

To ensure that the target impedance is achieved, calibrate the LVSTL I/O cell as following example:
1. Calibrate the pull-down device against a 240 ohm resistor to VDDQ via the ZQ pin.
· Set strength control to minimum setting · Increase drive strength until comparator detects data bit is less than VDDQ/2 · NMOS pull-down device is calibrated to 240 ohms

2. Calibrate the pull-up device against the calibrated pull-down device. · Set VOH target and NMOS controller ODT replica via MRS (VOH can be automatically
controlled by ODT MRS)

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

329

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Input/Output Capacitance
· Set strength control to minimum setting · Increase drive strength until comparator detects data bit is greater than VOH target · NMOS pull-up device is calibrated to VOH target Figure 234: Pull-Up Calibration
VDDQ

Strength contol [N-1:0] N

Comparator

VOH target

Calibrated NMOS PD control + ODT information

Controller ODT replica could be 60 ohms, 120 ohms, ... via MRS setting

VSSQ

Input/Output Capacitance

Table 210: Input/Output Capacitance
Notes 1 and 2 apply to entire table Parameter Input capacitance, CK_t and CK_c Input capacitance delta, CK_t and CK_c Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DMI, DQS_t, DQS_c Input/output capacitance delta, DQS_t, DQS_c Input/output capacitance delta, DQ, DMI Input/output capacitance, ZQ pin

Symbol
CCK CDCK
CI CDI CIO CDDQS CDIO CZQ

Min 0.5 0 0.5 ­0.1 0.7 0 ­0.1 0

Max 0.9 0.09 0.9 0.1 1.3 0.1 0.1 5.0

Unit Notes

3

4

pF

5 6

7

8

Notes:

1. This parameter applies to LPDDR4 die only (does not include package capacitance).
2. This parameter is not subject to production testing; It is verified by design and characterization. The capacitance is measured according to JEP147 (procedure for measuring input capacitance using a vector network analyzer), with VDD1, VDD2, VDDQ, and VSS applied; All other pins are left floating.
3. Absolute value of CCK_t ­ CCK_c. 4. CI applies to CS, CKE, and CA[5:0]. 5. CDI = CI ­ 0.5 × (CCK_t + CCK_c); It does not apply to CKE. 6. DMI loading matches DQ and DQS.
7. Absolute value of CDQS_t and CDQS_c.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

330

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP IDD Specification Parameters and Test Conditions

8. CDIO = CIO ­ Average(CDQn, CDMI, CDQS_t, CDQS_c) in byte-lane.
IDD Specification Parameters and Test Conditions

Table 211: IDD Measurement Conditions

CK_t edge CKE CS CA0 CA1 CA2 CA3 CA4 CA5

R1 HIGH LOW HIGH HIGH HIGH HIGH HIGH HIGH

R2 HIGH LOW LOW HIGH LOW HIGH LOW HIGH

Switching for CA

R3

R4

R5

HIGH

HIGH

HIGH

LOW

LOW

LOW

LOW

LOW

LOW

HIGH

LOW

LOW

LOW

LOW

LOW

HIGH

LOW

LOW

LOW

LOW

LOW

HIGH

LOW

LOW

R6 HIGH LOW HIGH LOW HIGH LOW HIGH LOW

R7 HIGH LOW HIGH LOW HIGH LOW HIGH LOW

R8 HIGH LOW HIGH HIGH HIGH HIGH HIGH HIGH

Notes:

1. LOW = VIN  VIL(DC) MAX. HIGH = VIN  VIH(DC) MIN. STABLE = Inputs are stable at a HIGH or LOW level.
2. CS must always be driven LOW. 3. 50% of CA bus is changing between HIGH and LOW once per clock for the CA bus. 4. The pattern is used continuously during IDD measurement for IDD values that require
switching on the CA bus.

Table 212: CA Pattern for IDD4R for BL = 16

Clock Cycle Number N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N+10 N+11 N+12 N+13 N+14

CKE HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH

CS HIGH LOW HIGH LOW LOW LOW LOW LOW HIGH LOW HIGH LOW LOW LOW LOW

Command READ-1
CAS-2
DES DES DES DES READ-1
CAS-2
DES DES DES

CA0 L L L L L L L L L L L H L L L

CA1 H H H L L L L L H H H H L L L

CA2 L L L L L L L L L L L H L L L

CA3 L L L L L L L L L L L H L L L

CA4 L L H L L L L L L H H H L L L

CA5 L L L L L L L L L L H H L L L

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

331

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP IDD Specification Parameters and Test Conditions

Table 212: CA Pattern for IDD4R for BL = 16 (Continued)

Clock Cycle Number
N+15

CKE HIGH

CS LOW

Command DES

CA0 L

CA1 L

CA2 L

CA3 L

CA4 L

CA5 L

Notes:

1. BA[2:0] = 010; C[9:4] = 000000 or 111111; Burst order C[3:2] = 00 or 11 (same as LPDDR3 IDDR4R specification).
2. CA pins are kept LOW with DES command to reduce ODT current (different from LPDDR3 IDDR4R specification).

Table 213: CA Pattern for IDD4W for BL = 16

Clock Cycle Number N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N+10 N+11 N+12 N+13 N+14 N+15

CKE HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH

CS HIGH LOW HIGH LOW LOW LOW LOW LOW HIGH LOW HIGH LOW LOW LOW LOW LOW

Command WRITE-1
CAS-2
DES DES DES DES WRITE-1
CAS-2
DES DES DES DES

CA0 L L L L L L L L L L L L L L L L

CA1 L H H L L L L L L H H L L L L L

CA2 H L L L L L L L H L L H L L L L

CA3 L L L L L L L L L L L H L L L L

CA4 L L H L L L L L L H H H L L L L

CA5 L L L L L L L L L L H H L L L L

Notes:

1. BA[2:0] = 010; C[9:4] = 000000 or 111111 (same as LPDDR3 IDDR4W specification). 2. No burst ordering (different from LPDDR3 IDDR4W specification). 3. CA pins are kept LOW with DES command to reduce ODT current (different from
LPDDR3 IDDR4W specification).

Table 214: Data Pattern for IDD4W (DBI Off) for BL = 16

DBI Off Case

DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2]

BL0

1

1

1

1

1

1

BL1

1

1

1

1

0

0

BL2

0

0

0

0

0

0

BL3

0

0

0

0

1

1

DQ[1] 1 0 0 1

DQ[0] 1 0 0 1

DBI

# of 1s

0

8

0

4

0

0

0

4

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

332

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP IDD Specification Parameters and Test Conditions

Table 214: Data Pattern for IDD4W (DBI Off) for BL = 16 (Continued)

BL4 BL5 BL6 BL7 BL8 BL9 BL10 BL11 BL12 BL13 BL14 BL15

DQ[7] 0 0 1 1 1 1 0 0 0 0 1 1

DQ[6] 0 0 1 1 1 1 0 0 0 0 1 1

DQ[5] 0 0 1 1 1 1 0 0 0 0 1 1

DBI Off Case

DQ[4] DQ[3] DQ[2]

0

0

0

0

1

1

1

1

1

1

0

0

1

1

1

1

0

0

0

0

0

0

1

1

0

0

0

0

1

1

1

1

1

1

0

0

DQ[1] 1 1 0 0 1 0 0 1 1 1 0 0

BL16

1

1

1

1

1

1

0

BL17

1

1

1

1

0

0

0

BL18

0

0

0

0

0

0

1

BL19

0

0

0

0

1

1

1

BL20

0

0

0

0

0

0

0

BL21

0

0

0

0

1

1

1

BL22

1

1

1

1

1

1

1

BL23

1

1

1

1

0

0

0

BL24

0

0

0

0

0

0

1

BL25

0

0

0

0

1

1

1

BL26

1

1

1

1

1

1

0

BL27

1

1

1

1

0

0

0

BL28

1

1

1

1

1

1

1

BL29

1

1

1

1

0

0

0

BL30

0

0

0

0

0

0

0

BL31

0

0

0

0

1

1

1

# of 1s

16

16

16

16

16

16

16

DQ[0] 1 1 0 0 1 0 0 1 1 1 0 0
0 0 1 1 0 1 1 0 1 1 0 0 1 0 0 1 16

DBI

# of 1s

0

2

0

4

0

6

0

4

0

8

0

4

0

0

0

4

0

2

0

4

0

6

0

4

0

6

0

4

0

2

0

4

0

0

0

4

0

8

0

4

0

2

0

4

0

6

0

4

0

8

0

4

0

0

0

4

Note: 1. Simplified pattern; same data pattern was applied to DQ[4], DQ[5], DQ[6], and DQ[7] to reduce complexity for IDD4W pattern programming.

Table 215: Data Pattern for IDD4R (DBI Off) for BL = 16

DBI Off Case

DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2]

BL0

1

1

1

1

1

1

DQ[1] 1

DQ[0] 1

DBI

# of 1s

0

8

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

333

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP IDD Specification Parameters and Test Conditions

Table 215: Data Pattern for IDD4R (DBI Off) for BL = 16 (Continued)

BL1 BL2 BL3 BL4 BL5 BL6 BL7 BL8 BL9 BL10 BL11 BL12 BL13 BL14 BL15

DQ[7] 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1

DQ[6] 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1

DQ[5] 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1

DBI Off Case

DQ[4] DQ[3] DQ[2]

1

0

0

0

0

0

0

1

1

0

0

0

0

1

1

1

1

1

1

0

0

1

1

1

1

0

0

0

0

0

0

1

1

0

0

0

0

1

1

1

1

1

1

0

0

DQ[1] 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0

BL16

1

1

1

1

1

1

1

BL17

1

1

1

1

0

0

0

BL18

0

0

0

0

0

0

0

BL19

0

0

0

0

1

1

1

BL20

1

1

1

1

1

1

0

BL21

1

1

1

1

0

0

0

BL22

0

0

0

0

0

0

1

BL23

0

0

0

0

1

1

1

BL24

0

0

0

0

0

0

0

BL25

0

0

0

0

1

1

1

BL26

1

1

1

1

1

1

1

BL27

1

1

1

1

0

0

0

BL28

0

0

0

0

0

0

1

BL29

0

0

0

0

1

1

1

BL30

1

1

1

1

1

1

0

BL31

1

1

1

1

0

0

0

# of 1s

16

16

16

16

16

16

16

DQ[0] 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0
1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 0 16

DBI

# of 1s

0

4

0

0

0

4

0

2

0

4

0

6

0

4

0

8

0

4

0

0

0

4

0

2

0

4

0

6

0

4

0

8

0

4

0

0

0

4

0

6

0

4

0

2

0

4

0

0

0

4

0

8

0

4

0

2

0

4

0

6

0

4

Note: 1. Simplified pattern; same data pattern was applied to DQ[4], DQ[5], DQ[6], and DQ[7] to reduce complexity for IDD4R pattern programming.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

334

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP IDD Specification Parameters and Test Conditions

Table 216: Data Pattern for IDD4W (DBI On) for BL = 16

DBI On Case

DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0]

DBI

BL0

0

0

0

0

0

0

0

0

1

BL1

1

1

1

1

0

0

0

0

0

BL2

0

0

0

0

0

0

0

0

0

BL3

0

0

0

0

1

1

1

1

0

BL4

0

0

0

0

0

0

1

1

0

BL5

0

0

0

0

1

1

1

1

0

BL6

0

0

0

0

0

0

1

1

1

BL7

1

1

1

1

0

0

0

0

0

BL8

0

0

0

0

0

0

0

0

1

BL9

1

1

1

1

0

0

0

0

0

BL10

0

0

0

0

0

0

0

0

0

BL11

0

0

0

0

1

1

1

1

0

BL12

0

0

0

0

0

0

1

1

0

BL13

0

0

0

0

1

1

1

1

0

BL14

0

0

0

0

0

0

1

1

1

BL15

1

1

1

1

0

0

0

0

0

BL16

0

0

0

0

0

0

1

1

1

BL17

1

1

1

1

0

0

0

0

0

BL18

0

0

0

0

0

0

1

1

0

BL19

0

0

0

0

1

1

1

1

0

BL20

0

0

0

0

0

0

0

0

0

BL21

0

0

0

0

1

1

1

1

0

BL22

0

0

0

0

0

0

0

0

1

BL23

1

1

1

1

0

0

0

0

0

BL24

0

0

0

0

0

0

1

1

0

BL25

0

0

0

0

1

1

1

1

0

BL26

0

0

0

0

0

0

1

1

1

BL27

1

1

1

1

0

0

0

0

0

BL28

0

0

0

0

0

0

0

0

1

BL29

1

1

1

1

0

0

0

0

0

BL30

0

0

0

0

0

0

0

0

0

BL31

0

0

0

0

1

1

1

1

0

# of 1s

8

8

8

8

8

8

16

16

8

Note: 1. DBI enabled burst: BL0, BL6, BL8, BL14, BL16, BL22, BL26, and BL28.

# of 1s 1 4 0 4 2 4 3 4 1 4 0 4 2 4 3 4
3 4 2 4 0 4 1 4 2 4 3 4 1 4 0 4

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

335

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP IDD Specification Parameters and Test Conditions

Table 217: Data Pattern for IDD4R (DBI On) for BL = 16

BL0 BL1 BL2 BL3 BL4 BL5 BL6 BL7 BL8 BL9 BL10 BL11 BL12 BL13 BL14 BL15

DQ[7] 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1

DQ[6] 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1

DQ[5] 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1

DBI On Case

DQ[4] DQ[3] DQ[2]

0

0

0

1

0

0

0

0

0

0

1

1

0

0

0

0

1

1

0

0

0

1

0

0

0

0

0

1

0

0

0

0

0

0

1

1

0

0

0

0

1

1

0

0

0

1

0

0

BL16

0

0

0

0

0

0

BL17

1

1

1

1

0

0

BL18

0

0

0

0

0

0

BL19

0

0

0

0

1

1

BL20

0

0

0

0

0

0

BL21

1

1

1

1

0

0

BL22

0

0

0

0

0

0

BL23

0

0

0

0

1

1

BL24

0

0

0

0

0

0

BL25

0

0

0

0

1

1

BL26

0

0

0

0

0

0

BL27

1

1

1

1

0

0

BL28

0

0

0

0

0

0

BL29

0

0

0

0

1

1

BL30

0

0

0

0

0

0

BL31

1

1

1

1

0

0

# of 1s

8

8

8

8

8

8

DQ[1] 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0
0 0 0 1 1 0 1 1 0 1 0 0 1 1 1 0 16

DQ[0] 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0
0 0 0 1 1 0 1 1 0 1 0 0 1 1 1 0 16

Note: 1. DBI enabled burst: BL0, BL6, BL8, BL14, BL20, BL26, and BL30.

DBI

# of 1s

1

1

0

4

0

0

0

4

0

2

0

4

1

3

0

4

1

1

0

4

0

0

0

4

0

2

0

4

1

3

0

4

1

1

0

4

0

0

0

4

1

3

0

4

0

2

0

4

0

0

0

4

1

1

0

4

0

2

0

4

1

3

0

4

8

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

336

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP IDD Specification Parameters and Test Conditions

Table 218: CA Pattern for IDD4R for BL = 32

Clock Cycle Number N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N+10 N+11 N+12 N+13 N+14 N+15 N+16 N+17 N+18 N+19 N+20 N+21 N+22 N+23 N+24 N+25 N+26 N+27 N+28 N+29 N+30 N+31

CKE HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH

CS HIGH LOW HIGH LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW HIGH LOW HIGH LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW

Command READ-1
CAS-2
DES DES DES DES DES DES DES DES DES DES DES DES READ-1
CAS-2
DES DES DES DES DES DES DES DES DES DES DES DES

CA0 L L L L L L L L L L L L L L L L L L L H L L L L L L L L L L L L

CA1 H H H L L L L L L L L L L L L L H H H H L L L L L L L L L L L L

CA2 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L

CA3 L L L L L L L L L L L L L L L L L L L H L L L L L L L L L L L L

CA4 L L H L L L L L L L L L L L L L L H H H L L L L L L L L L L L L

Note: 1. BA[2:0] = 010, C[9:5] = 00000 or 11111, Burst order C[4:2] = 000 or 111.

CA5 L L L L L L L L L L L L L L L L L L H H L L L L L L L L L L L L

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

337

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP IDD Specification Parameters and Test Conditions

Table 219: CA Pattern for IDD4W for BL = 32

Clock Cycle Number N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N+10 N+11 N+12 N+13 N+14 N+15 N+16 N+17 N+18 N+19 N+20 N+21 N+22 N+23 N+24 N+25 N+26 N+27 N+28 N+29 N+30 N+31

CKE HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH

CS HIGH LOW HIGH LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW HIGH LOW HIGH LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW

Command WRITE-1
CAS-2
DES DES DES DES DES DES DES DES DES DES DES DES WRITE-1
CAS-2
DES DES DES DES DES DES DES DES DES DES DES DES

CA0 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L

Note: 1. BA[2:0] = 010, C[9:5] = 00000 or 11111.

CA1 L H H L L L L L L L L L L L L L L H H L L L L L L L L L L L L L

CA2 H L L L L L L L L L L L L L L L H L L L L L L L L L L L L L L L

CA3 L L L L L L L L L L L L L L L L L L L H L L L L L L L L L L L L

CA4 L L H L L L L L L L L L L L L L L H H H L L L L L L L L L L L L

CA5 L L L L L L L L L L L L L L L L L L H H L L L L L L L L L L L L

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

338

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP IDD Specification Parameters and Test Conditions

Table 220: Data Pattern for IDD4W (DBI Off) for BL = 32

BL0 BL1 BL2 BL3 BL4 BL5 BL6 BL7 BL8 BL9 BL10 BL11 BL12 BL13 BL14 BL15

DQ[7] 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1

DQ[6] 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1

DQ[5] 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1

DBI Off Case

DQ[4] DQ[3] DQ[2]

1

1

1

1

0

0

0

0

0

0

1

1

0

0

0

0

1

1

1

1

1

1

0

0

1

1

1

1

0

0

0

0

0

0

1

1

0

0

0

0

1

1

1

1

1

1

0

0

BL16

1

1

1

1

1

1

BL17

1

1

1

1

0

0

BL18

0

0

0

0

0

0

BL19

0

0

0

0

1

1

BL20

0

0

0

0

0

0

BL21

0

0

0

0

1

1

BL22

1

1

1

1

1

1

BL23

1

1

1

1

0

0

BL24

0

0

0

0

0

0

BL25

0

0

0

0

1

1

BL26

1

1

1

1

1

1

BL27

1

1

1

1

0

0

BL28

1

1

1

1

1

1

BL29

1

1

1

1

0

0

BL30

0

0

0

0

0

0

BL31

0

0

0

0

1

1

BL32

1

1

1

1

1

1

BL33

1

1

1

1

0

0

BL34

0

0

0

0

0

0

BL35

0

0

0

0

1

1

BL36

0

0

0

0

0

0

DQ[1] 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0
0 0 1 1 0 1 1 0 1 1 0 0 1 0 0 1
1 0 0 1 1

DQ[0] 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0
0 0 1 1 0 1 1 0 1 1 0 0 1 0 0 1
1 0 0 1 1

DBI

# of 1s

0

8

0

4

0

0

0

4

0

2

0

4

0

6

0

4

0

8

0

4

0

0

0

4

0

2

0

4

0

6

0

4

0

6

0

4

0

2

0

4

0

0

0

4

0

8

0

4

0

2

0

4

0

6

0

4

0

8

0

4

0

0

0

4

0

8

0

4

0

0

0

4

0

2

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

339

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP IDD Specification Parameters and Test Conditions

Table 220: Data Pattern for IDD4W (DBI Off) for BL = 32 (Continued)

BL37 BL38 BL39 BL40 BL41 BL42 BL43 BL44 BL45 BL46 BL47

DQ[7] 0 1 1 1 1 0 0 0 0 1 1

DQ[6] 0 1 1 1 1 0 0 0 0 1 1

DQ[5] 0 1 1 1 1 0 0 0 0 1 1

DBI Off Case

DQ[4] DQ[3] DQ[2]

0

1

1

1

1

1

1

0

0

1

1

1

1

0

0

0

0

0

0

1

1

0

0

0

0

1

1

1

1

1

1

0

0

DQ[1] 1 0 0 1 0 0 1 1 1 0 0

BL48

1

1

1

1

1

1

0

BL49

1

1

1

1

0

0

0

BL50

0

0

0

0

0

0

1

BL51

0

0

0

0

1

1

1

BL52

0

0

0

0

0

0

0

BL53

0

0

0

0

1

1

1

BL54

1

1

1

1

1

1

1

BL55

1

1

1

1

0

0

0

BL56

0

0

0

0

0

0

1

BL57

0

0

0

0

1

1

1

BL58

1

1

1

1

1

1

0

BL59

1

1

1

1

0

0

0

BL60

1

1

1

1

1

1

1

BL61

1

1

1

1

0

0

0

BL62

0

0

0

0

0

0

0

BL63

0

0

0

0

1

1

1

# of 1s

32

32

32

32

32

32

32

DQ[0] 1 0 0 1 0 0 1 1 1 0 0
0 0 1 1 0 1 1 0 1 1 0 0 1 0 0 1 32

DBI

# of 1s

0

4

0

6

0

4

0

8

0

4

0

0

0

4

0

2

0

4

0

6

0

4

0

6

0

4

0

2

0

4

0

0

0

4

0

8

0

4

0

2

0

4

0

6

0

4

0

8

0

4

0

0

0

4

Note: 1. Simplified pattern; same data pattern was applied to DQ[4], DQ[5], DQ[6], and DQ[7] to reduce complexity for IDD4W pattern programming.

Table 221: Data Pattern for IDD4R (DBI Off) for BL = 32

DBI Off Case

DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2]

BL0

1

1

1

1

1

1

BL1

1

1

1

1

0

0

DQ[1] 1 0

DQ[0] 1 0

DBI

# of 1s

0

8

0

4

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

340

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP IDD Specification Parameters and Test Conditions

Table 221: Data Pattern for IDD4R (DBI Off) for BL = 32 (Continued)

BL2 BL3 BL4 BL5 BL6 BL7 BL8 BL9 BL10 BL11 BL12 BL13 BL14 BL15

DQ[7] 0 0 0 0 1 1 1 1 0 0 0 0 1 1

DQ[6] 0 0 0 0 1 1 1 1 0 0 0 0 1 1

DQ[5] 0 0 0 0 1 1 1 1 0 0 0 0 1 1

DBI Off Case

DQ[4] DQ[3] DQ[2]

0

0

0

0

1

1

0

0

0

0

1

1

1

1

1

1

0

0

1

1

1

1

0

0

0

0

0

0

1

1

0

0

0

0

1

1

1

1

1

1

0

0

DQ[1] 0 1 1 1 0 0 1 0 0 1 1 1 0 0

BL16

1

1

1

1

1

1

0

BL17

1

1

1

1

0

0

0

BL18

0

0

0

0

0

0

1

BL19

0

0

0

0

1

1

1

BL20

0

0

0

0

0

0

0

BL21

0

0

0

0

1

1

1

BL22

1

1

1

1

1

1

1

BL23

1

1

1

1

0

0

0

BL24

0

0

0

0

0

0

1

BL25

0

0

0

0

1

1

1

BL26

1

1

1

1

1

1

0

BL27

1

1

1

1

0

0

0

BL28

1

1

1

1

1

1

1

BL29

1

1

1

1

0

0

0

BL30

0

0

0

0

0

0

0

BL31

0

0

0

0

1

1

1

BL32

0

0

0

0

0

0

1

BL33

0

0

0

0

1

1

1

BL34

1

1

1

1

1

1

0

BL35

1

1

1

1

0

0

0

BL36

1

1

1

1

1

1

1

BL37

1

1

1

1

0

0

0

BL38

0

0

0

0

0

0

0

DQ[0] 0 1 1 1 0 0 1 0 0 1 1 1 0 0
0 0 1 1 0 1 1 0 1 1 0 0 1 0 0 1
1 1 0 0 1 0 0

DBI

# of 1s

0

0

0

4

0

2

0

4

0

6

0

4

0

8

0

4

0

0

0

4

0

2

0

4

0

6

0

4

0

6

0

4

0

2

0

4

0

0

0

4

0

8

0

4

0

2

0

4

0

6

0

4

0

8

0

4

0

0

0

4

0

2

0

4

0

6

0

4

0

8

0

4

0

0

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

341

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP IDD Specification Parameters and Test Conditions

Table 221: Data Pattern for IDD4R (DBI Off) for BL = 32 (Continued)

BL39 BL40 BL41 BL42 BL43 BL44 BL45 BL46 BL47

DQ[7] 0 0 0 1 1 1 1 0 0

DQ[6] 0 0 0 1 1 1 1 0 0

DQ[5] 0 0 0 1 1 1 1 0 0

DBI Off Case

DQ[4] DQ[3] DQ[2]

0

1

1

0

0

0

0

1

1

1

1

1

1

0

0

1

1

1

1

0

0

0

0

0

0

1

1

DQ[1] 1 1 1 0 0 1 0 0 1

BL48

1

1

1

1

1

1

1

BL49

1

1

1

1

0

0

0

BL50

0

0

0

0

0

0

0

BL51

0

0

0

0

1

1

1

BL52

1

1

1

1

1

1

0

BL53

1

1

1

1

0

0

0

BL54

0

0

0

0

0

0

1

BL55

0

0

0

0

1

1

1

BL56

0

0

0

0

0

0

0

BL57

0

0

0

0

1

1

1

BL58

1

1

1

1

1

1

1

BL59

1

1

1

1

0

0

0

BL60

0

0

0

0

0

0

1

BL61

0

0

0

0

1

1

1

BL62

1

1

1

1

1

1

0

BL63

1

1

1

1

0

0

0

# of 1s

32

32

32

32

32

32

32

DQ[0] 1 1 1 0 0 1 0 0 1
1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 0 32

DBI

# of 1s

0

4

0

2

0

4

0

6

0

4

0

8

0

4

0

0

0

4

0

8

0

4

0

0

0

4

0

6

0

4

0

2

0

4

0

0

0

4

0

8

0

4

0

2

0

4

0

6

0

4

Note: 1. Simplified pattern; same data pattern was applied to DQ[4], DQ[5], DQ[6], and DQ[7] to reduce complexity for IDD4R pattern programming.

Table 222: Data Pattern for IDD4W (DBI On) for BL = 32

DBI On Case

DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2]

BL0

0

0

0

0

0

0

BL1

1

1

1

1

0

0

BL2

0

0

0

0

0

0

BL3

0

0

0

0

1

1

DQ[1] 0 0 0 1

DQ[0] 0 0 0 1

DBI

# of 1s

1

1

0

4

0

0

0

4

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

342

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP IDD Specification Parameters and Test Conditions

Table 222: Data Pattern for IDD4W (DBI On) for BL = 32 (Continued)

BL4 BL5 BL6 BL7 BL8 BL9 BL10 BL11 BL12 BL13 BL14 BL15

DQ[7] 0 0 0 1 0 1 0 0 0 0 0 1

DQ[6] 0 0 0 1 0 1 0 0 0 0 0 1

DQ[5] 0 0 0 1 0 1 0 0 0 0 0 1

DBI On Case

DQ[4] DQ[3] DQ[2]

0

0

0

0

1

1

0

0

0

1

0

0

0

0

0

1

0

0

0

0

0

0

1

1

0

0

0

0

1

1

0

0

0

1

0

0

DQ[1] 1 1 1 0 0 0 0 1 1 1 1 0

BL16

0

0

0

0

0

0

1

BL17

1

1

1

1

0

0

0

BL18

0

0

0

0

0

0

1

BL19

0

0

0

0

1

1

1

BL20

0

0

0

0

0

0

0

BL21

0

0

0

0

1

1

1

BL22

0

0

0

0

0

0

0

BL23

1

1

1

1

0

0

0

BL24

0

0

0

0

0

0

1

BL25

0

0

0

0

1

1

1

BL26

0

0

0

0

0

0

1

BL27

1

1

1

1

0

0

0

BL28

0

0

0

0

0

0

0

BL29

1

1

1

1

0

0

0

BL30

0

0

0

0

0

0

0

BL31

0

0

0

0

1

1

1

BL32

0

0

0

0

0

0

0

BL33

1

1

1

1

0

0

0

BL34

0

0

0

0

0

0

0

BL35

0

0

0

0

1

1

1

BL36

0

0

0

0

0

0

1

BL37

0

0

0

0

1

1

1

BL38

0

0

0

0

0

0

1

BL39

1

1

1

1

0

0

0

BL40

0

0

0

0

0

0

0

DQ[0] 1 1 1 0 0 0 0 1 1 1 1 0
1 0 1 1 0 1 0 0 1 1 1 0 0 0 0 1
0 0 0 1 1 1 1 0 0

DBI

# of 1s

0

2

0

4

1

3

0

4

1

1

0

4

0

0

0

4

0

2

0

4

1

3

0

4

1

3

0

4

0

2

0

4

0

0

0

4

1

1

0

4

0

2

0

4

1

3

0

4

1

1

0

4

0

0

0

4

1

1

0

4

0

0

0

4

0

2

0

4

1

3

0

4

1

1

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

343

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP IDD Specification Parameters and Test Conditions

Table 222: Data Pattern for IDD4W (DBI On) for BL = 32 (Continued)

BL41 BL42 BL43 BL44 BL45 BL46 BL47

DQ[7] 1 0 0 0 0 0 1

DQ[6] 1 0 0 0 0 0 1

DQ[5] 1 0 0 0 0 0 1

DBI On Case

DQ[4] DQ[3] DQ[2]

1

0

0

0

0

0

0

1

1

0

0

0

0

1

1

0

0

0

1

0

0

DQ[1] 0 0 1 1 1 1 0

BL48

0

0

0

0

0

0

1

BL49

1

1

1

1

0

0

0

BL50

0

0

0

0

0

0

1

BL51

0

0

0

0

1

1

1

BL52

0

0

0

0

0

0

0

BL53

0

0

0

0

1

1

1

BL54

0

0

0

0

0

0

0

BL55

1

1

1

1

0

0

0

BL56

0

0

0

0

0

0

1

BL57

0

0

0

0

1

1

1

BL58

0

0

0

0

0

0

1

BL59

1

1

1

1

0

0

0

BL60

0

0

0

0

0

0

0

BL61

1

1

1

1

0

0

0

BL62

0

0

0

0

0

0

0

BL63

0

0

0

0

1

1

1

# of 1s

16

16

16

16

16

16

32

DQ[0] 0 0 1 1 1 1 0
1 0 1 1 0 1 0 0 1 1 1 0 0 0 0 1 32

DBI

# of 1s

0

4

0

0

0

4

0

2

0

4

1

3

0

4

1

3

0

4

0

2

0

4

0

0

0

4

1

1

0

4

0

2

0

4

1

3

0

4

1

1

0

4

0

0

0

4

16

Note: 1. DBI enabled burst: BL0, BL6, BL8, BL14, BL16, BL22, BL26, BL28, BL32, BL38, BL40, BL46, BL48, BL54, BL58, and BL60.

Table 223: Data Pattern for IDD4R (DBI On) for BL = 32

DBI On Case

DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2]

BL0

0

0

0

0

0

0

BL1

1

1

1

1

0

0

BL2

0

0

0

0

0

0

BL3

0

0

0

0

1

1

BL4

0

0

0

0

0

0

BL5

0

0

0

0

1

1

DQ[1] 0 0 0 1 1 1

DQ[0] 0 0 0 1 1 1

DBI

# of 1s

1

1

0

4

0

0

0

4

0

2

0

4

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

344

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP IDD Specification Parameters and Test Conditions

Table 223: Data Pattern for IDD4R (DBI On) for BL = 32 (Continued)

BL6 BL7 BL8 BL9 BL10 BL11 BL12 BL13 BL14 BL15

DQ[7] 0 1 0 1 0 0 0 0 0 1

DQ[6] 0 1 0 1 0 0 0 0 0 1

DQ[5] 0 1 0 1 0 0 0 0 0 1

DBI On Case

DQ[4] DQ[3] DQ[2]

0

0

0

1

0

0

0

0

0

1

0

0

0

0

0

0

1

1

0

0

0

0

1

1

0

0

0

1

0

0

DQ[1] 1 0 0 0 0 1 1 1 1 0

BL16

0

0

0

0

0

0

1

BL17

1

1

1

1

0

0

0

BL18

0

0

0

0

0

0

1

BL19

0

0

0

0

1

1

1

BL20

0

0

0

0

0

0

0

BL21

0

0

0

0

1

1

1

BL22

0

0

0

0

0

0

0

BL23

1

1

1

1

0

0

0

BL24

0

0

0

0

0

0

1

BL25

0

0

0

0

1

1

1

BL26

0

0

0

0

0

0

1

BL27

1

1

1

1

0

0

0

BL28

0

0

0

0

0

0

0

BL29

1

1

1

1

0

0

0

BL30

0

0

0

0

0

0

0

BL31

0

0

0

0

1

1

1

BL32

0

0

0

0

0

0

1

BL33

0

0

0

0

1

1

1

BL34

0

0

0

0

0

0

1

BL35

1

1

1

1

0

0

0

BL36

0

0

0

0

0

0

0

BL37

1

1

1

1

0

0

0

BL38

0

0

0

0

0

0

0

BL39

0

0

0

0

1

1

1

BL40

0

0

0

0

0

0

1

BL41

0

0

0

0

1

1

1

BL42

0

0

0

0

0

0

1

DQ[0] 1 0 0 0 0 1 1 1 1 0
1 0 1 1 0 1 0 0 1 1 1 0 0 0 0 1
1 1 1 0 0 0 0 1 1 1 1

DBI

# of 1s

1

3

0

4

1

1

0

4

0

0

0

4

0

2

0

4

1

3

0

4

1

3

0

4

0

2

0

4

0

0

0

4

1

1

0

4

0

2

0

4

1

3

0

4

1

1

0

4

0

0

0

4

0

2

0

4

1

3

0

4

1

1

0

4

0

0

0

4

0

2

0

4

1

3

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

345

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP IDD Specification Parameters and Test Conditions

Table 223: Data Pattern for IDD4R (DBI On) for BL = 32 (Continued)

BL43 BL44 BL45 BL46 BL47

DQ[7] 1 0 1 0 0

DQ[6] 1 0 1 0 0

DQ[5] 1 0 1 0 0

DBI On Case

DQ[4] DQ[3] DQ[2]

1

0

0

0

0

0

1

0

0

0

0

0

0

1

1

DQ[1] 0 0 0 0 1

BL48

0

0

0

0

0

0

0

BL49

1

1

1

1

0

0

0

BL50

0

0

0

0

0

0

0

BL51

0

0

0

0

1

1

1

BL52

0

0

0

0

0

0

1

BL53

1

1

1

1

0

0

0

BL54

0

0

0

0

0

0

1

BL55

0

0

0

0

1

1

1

BL56

0

0

0

0

0

0

0

BL57

0

0

0

0

1

1

1

BL58

0

0

0

0

0

0

0

BL59

1

1

1

1

0

0

0

BL60

0

0

0

0

0

0

1

BL61

0

0

0

0

1

1

1

BL62

0

0

0

0

0

0

1

BL63

1

1

1

1

0

0

0

# of 1s

16

16

16

16

16

16

32

DQ[0] 0 0 0 0 1
0 0 0 1 1 0 1 1 0 1 0 0 1 1 1 0 32

DBI

# of 1s

0

4

1

1

0

4

0

0

0

4

1

1

0

4

0

0

0

4

1

3

0

4

0

2

0

4

0

0

0

4

1

1

0

4

0

2

0

4

1

3

0

4

16

Note: 1. DBI enabled burst: BL0, BL6, BL8, BL14, BL16, BL22, BL26, BL28, BL34, BL36, BL42, BL44, BL48, BL52, BL58, and BL62.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

346

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP IDD Specification Parameters and Test Conditions

IDD Specifications

IDD values are for the entire operating voltage range, and all of them are for the entire standard temperature range.

Table 224: IDD Specification Parameters and Operating Conditions LPDDR4: VDD2, VDDQ = 1.06­1.17V; VDD1 = 1.70­1.95V LPDDR4X: VDD2= 1.06­1.17V; VDDQ = 0.57­0.65V; VDD1 = 1.70­1.95V

Parameter/Condition Operating one bank active-precharge current: tCK = tCK (MIN); tRC = tRC (MIN); CKE is HIGH; CS is LOW between valid commands; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled Idle power-down standby current: tCK = tCK (MIN); CKE is LOW; CS is LOW; All banks are idle; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled
Idle power-down standby current with clock stop: CK_t = LOW, CK_c = HIGH; CKE is LOW; CS is LOW; All banks are idle; CA bus inputs are stable; Data bus inputs are stable; ODT is disabled
Idle non-power-down standby current: tCK = tCK (MIN); CKE is HIGH; CS is LOW; All banks are idle; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled
Idle non-power-down standby current with clock stopped: CK_t = LOW; CK_c = HIGH; CKE is HIGH; CS is LOW; All banks are idle; CA bus inputs are stable; Data bus inputs are stable; ODT is disabled Active power-down standby current: tCK = tCK (MIN); CKE is LOW; CS is LOW; One bank is active; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled
Active power-down standby current with clock stop: CK_t = LOW, CK_c = HIGH; CKE is LOW; CS is LOW; One bank is active; CA bus inputs are stable; Data bus inputs are stable; ODT is disabled
Active non-power-down standby current: tCK = tCK (MIN); CKE is HIGH; CS is LOW; One bank is active; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled
Active non-power-down standby current with clock stopped: CK_t = LOW, CK_c = HIGH; CKE is HIGH; CS is LOW; One bank is active; CA bus inputs are stable; Data bus inputs are stable; ODT is disabled Operating burst READ current: tCK = tCK (MIN); CS is LOW between valid commands; One bank is active; BL = 16 or 32; RL = RL (MIN); CA bus inputs are switching; 50% data change each burst transfer; ODT is disabled

Symbol IDD01 IDD02 IDD0Q
IDD2P1 IDD2P2 IDD2PQ IDD2PS1 IDD2PS2 IDD2PSQ IDD2N1 IDD2N2 IDD2NQ IDD2NS1 IDD2NS2 IDD2NSQ
IDD3P1 IDD3P2 IDD3PQ IDD3PS1 IDD3PS2 IDD3PSQ IDD3N1 IDD3N2 IDD3NQ IDD3NS1 IDD3NS2 IDD3NSQ
IDD4R1 IDD4R2 IDD4RQ

Power Supply
VDD1 VDD2 VDDQ
VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ
VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ
VDD1 VDD2 VDDQ

Notes 2 2 2 2 2 2 3 3 3 4

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

347

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP IDD Specification Parameters and Test Conditions

Table 224: IDD Specification Parameters and Operating Conditions (Continued)

LPDDR4: VDD2, VDDQ = 1.06­1.17V; VDD1 = 1.70­1.95V
LPDDR4X: VDD2= 1.06­1.17V; VDDQ = 0.57­0.65V; VDD1 = 1.70­1.95V
Parameter/Condition Operating burst WRITE current: tCK = tCK (MIN); CS is LOW between valid commands; One bank is active; BL = 16 or 32; WL = WL (MIN); CA bus inputs are switching; 50% data change each burst transfer; ODT is disabled All-bank REFRESH burst current: tCK = tCK (MIN); CKE is HIGH between valid commands; tRC = tRFCab (MIN); Burst refresh; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled All-bank REFRESH average current: tCK = tCK (MIN); CKE is HIGH between valid commands; tRC = tREFI; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled
Per-bank REFRESH average current: tCK = tCK (MIN); CKE is HIGH between valid commands; tRC = tREFI/8; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled
Power-down self refresh current: CK_t = LOW, CK_c = HIGH; CKE is LOW; CA bus inputs are stable; Data bus inputs are stable; Maximum 1x self refresh rate; ODT is disabled

Symbol IDD4W1 IDD4W2 IDD4WQ
IDD51 IDD52 IDD5Q
IDD5AB1 IDD5AB2 IDD5ABQ IDD5PB1 IDD5PB2 IDD5PBQ
IDD61 IDD62 IDD6Q

Power Supply
VDD1 VDD2 VDDQ
VDD1 VDD2 VDDQ
VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ VDD1 VDD2 VDDQ

Notes
3
3
3
3 5, 6 5, 6 3, 5, 6

Notes:

1. ODT disabled: MR11[2:0] = 000b.
2. IDD current specifications are tested after the device is properly initialized. 3. Measured currents are the summation of VDDQ and VDD2. 4. Guaranteed by design with output load = 5pF and RON = 40 ohm. 5. The 1x self refresh rate is the rate at which the device is refreshed internally during self
refresh before going into the elevated temperature range.
6. This is the general definition that applies to full-array self refresh.
7. For all IDD measurements, VIHCKE = 0.8 × VDD2; VILCKE = 0.2 × VDD2.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

348

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

AC Timing

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP AC Timing

Table 225: Clock Timing
Parameter Average clock period
Average HIGH pulse width
Average LOW pulse width Absolute clock period Absolute clock HIGH pulse width
Absolute clock LOW pulse width
Clock period jitter Maximum clock jitter between two consecutive clock cycles (includes clock period jitter)

Symbol tCK(AVG)
tCH(AVG)
tCL(AVG) tCK(ABS) tCH(ABS)
tCL(ABS) tJIT(per)al-
lowed

Min/ Max Min Max Min Max Min Max Min Min Max Min Max Min Max

tJIT(cc)allowed Max

Data Rate

1600

3200

3733

4267

1250

625

535

468

100

100

100

100

0.46

0.54

0.46

0.54

tCK(AVG)min + tJIT(per)min

0.43

0.57

0.43

0.57

­70

­40

­34

­30

70

40

34

30

140

80

68

60

Unit ps ns
tCK(AVG)
tCK(AVG) ps
tCK(AVG)
tCK(AVG)
ps
ps

Table 226: Read Output Timing

Parameter

Min/

Data Rate

Symbol Max 533 1066 1600 2133 2667 3200 3733 4267

DQS output access time from CK_t/CK_c

tDQSCK

Min Max

1500 3500

DQS output access time from CK_t/CK_c - voltage variation

tDQSCK_ VOLT

Max

7

DQS output access time from CK_t/CK_c - temperature variation

tDQSCK_ TEMP

Max

4

CK to DQS rank to rank variation

tDQSCK_r ank2rank

Max

1.0

DQS_t, DQS_c to DQ skew

total, per group, per ac- tDQSQ Max

0.18

cess (DBI Disabled)

DQ output hold time total from DQS_t, DQS_c (DBI Disabled)

tQH

Min

MIN(tQSH, tQSL)

Unit ps
ps/mV ps/°C
ns UI ps

Notes 1 2 3
4, 5 6 6

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

349

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP AC Timing

Table 226: Read Output Timing (Continued)

Parameter

Symbol

Data output valid window time total, per pin (DBI-Disabled)

tQW_total

DQS_t, DQS_c to DQ skew total, per group, per access (DBI-Enabled)

tDQSQ_D BI

DQ output hold time total from DQS_t, DQS_c (DBI-Enabled)

tQH_DBI

Data output valid window time total, per pin (DBI-Enabled)

tQW_total_DBI

DQS_t, DQS_c differential output LOW time (DBIDisabled)

tQSL

DQS_t, DQS_c differential output HIGH time (DBIDisabled)

tQSH

DQS_t, DQS_c differential output LOW time (DBI- tQSL-DBI
Enabled)

DQS_t, DQS_c differential output HIGH time (DBI- tQSH-DBI
Enabled)

Read preamble

tRPRE

Read postamble

tRPST

DQS Low-Z from clock

tLZ(DQS)

DQ Low-Z from clock

tLZ(DQ)

DQS High-Z from clock tHZ(DQS)

DQ High-Z from clock

tHZ(DQ)

Min/ Max Min
Max
Min
Min
Min
Min
Min
Min Min Min Min Min Max Max

Data Rate 533 1066 1600 2133 2667 3200 3733 4267

0.75

0.73

0.70

0.18

MIN(tQSH_DBI, tQSL_DBI)

0.75

0.73

0.70

tCL(ABS) - 0.05

tCH(ABS) - 0.05

tCL(ABS) - 0.045

tCH(ABS) - 0.045
1.8 0.4 (or 1.4 if extra postamble is programmed in MR) (RL × tCK) + tDQSCK(MIN) - (tRPRE(MAX) × tCK) - 200ps
(RL × tCK) + tDQSCK(MIN) - 200ps (RL × tCK) + tDQSCK(MAX)+(BL/2 × tCK) + (tRPST(MAX) ×
tCK) - 100ps (RL × tCK) + tDQSCK(MAX) + tDQSQ(MAX) + (BL/2 × tCK)
- 100ps

Unit UI
UI
ps
UI
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG) tCK(AVG) tCK(AVG)
ps ps ps ps

Notes 6, 11
6 6 6, 11 9, 11 10, 11 9, 11 10, 11

Notes:

1. This parameter includes DRAM process, voltage, and temperature variation. It also includes the AC noise impact for frequencies >20 MHz and a max voltage of 45mV peakto-peak from DC-20 MHz at a fixed temperature on the package. The voltage supply noise must comply with the component MIN/MAX DC operating conditions.
2. tDQSCK_volt max delay variation as a function of DC voltage variation for VDDQ and VDD2. The voltage supply noise must comply with the component MIN/MAX DC operating conditions. The voltage variation is defined as the MAX[ABS(tDQSCK(MIN)@V1 tDQSCK(MAX)@V2), ABS(tDQSCK(MAX)@V1 - tDQSCK(MIN)@V2)]/ABS(V1 - V2).
3. tDQSCK_temp MAX delay variation as a function of temperature.
4. The same voltage and temperature are applied to tDQSCK_rank2rank.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

350

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP AC Timing

5. tDQSCK_rank2rank parameter is applied to multi-ranks per byte lane within a package consisting of the same design die.
6. DQ-to-DQS differential jitter where the total includes the sum of deterministic and random timing terms for a specified BER.
7. The deterministic component of the total timing.
8. This parameter will be characterized and guaranteed by design. 9. tQSL describes the instantaneous differential output low pulse width on DQS_t - DQS_c,
as measured from one falling edge to the next consecutive rising edge. 10. tQSH describes the instantaneous differential output high pulse width on DQS_t -
DQS_c, as measured from one falling edge to the next consecutive rising edge. 11. This parameter is a function of input clock jitter. These values assume MIN tCH(ABS) and
tCL(ABS). When the input clock jitter MIN tCH(ABS) and tCL(ABS) is 0.44 or greater than tCK(AVG), the minimum value of tQSL will be tCL(ABS) - 0.04 and tQSH will be tCH(ABS) 0.04.

Table 227: Write Timing

Note UI = tCK(AVG)(MIN)/2

Parameter

Min/ Symbol Max

Rx timing window total at VdIVW voltage levels DQ and DMI input pulse width (at VCENT_DQ)
DQ-to-DQS offset

TdIVW_t otal

Max

TdIPW Min

tDQS2DQ Min Max

DQ-to-DQ offset

tDQDQ

DQ-to-DQS offset temper- tDQS2DQ

ature variation

_temp

DQ-to-DQS offset voltage tDQS2DQ

variation

_volt

DQ-to-DQS offset rank to rank variation

tDQS2DQ _rank2ra
nk

Max Max Max
Max

WRITE command to first DQS transition

tDQSS

Min Max

DQS input HIGH-level width

tDQSH Min

DQS input LOW-level width

tDQSL Min

DQS falling edge to CK setup time

tDSS Min

DQS falling edge from CK hold time

tDSH

Min

Write postamble

tWPST Min

Data Rate 533 1066 1600 2133 2667 3200 3733 4267

0.22

0.25

Unit UI

Notes 1, 2, 3

0.45

UI

7

200 800

ps

6

30

ps

7

0.6

ps/°C

8

33

ps/50mV 9

200

ps

10, 11

0.75

tCK(AVG)

1.25

0.4

tCK(AVG)

0.4

tCK(AVG)

0.2

tCK(AVG)

0.2 0.4 (or 1.4 if extra postamble is programmed in MR)

tCK(AVG) tCK(AVG)

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

351

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP AC Timing

Table 227: Write Timing (Continued)

Note UI = tCK(AVG)(MIN)/2

Parameter

Min/

Data Rate

Symbol Max 533 1066 1600 2133 2667 3200 3733 4267

Unit

Notes

Write preamble

tWPRE Min

1.8

tCK(AVG)

Notes: 1. Data Rx mask voltage and timing parameters are applied per pin and include the DRAM DQ-to-DQS voltage AC noise impact for frequencies >20 MHz with a maximum voltage of 45mV peak-to-peak at a fixed temperature on the package. The voltage supply noise must comply to the component MIN/MAX DC operating conditions.
2. Rx differential DQ-to-DQS jitter total timing window at the VdIVW voltage levels. 3. Defined over the DQ internal VREF range. The Rx mask at the pin must be within the in-
ternal VREF(DQ) range irrespective of the input signal common mode. 4. Rx mask defined for one pin toggling with other DQ signals in a steady state.
5. DQ-only minimum input pulse width defined at the VCENT_DQ(pin_mid). 6. DQ-to-DQS offset is within byte from DRAM pin to DRAM internal latch. Includes all
DRAM process, voltage, and temperature variations.
7. DQ-to-DQ offset defined within byte from DRAM pin to DRAM internal latch for a given component.
8. tDQS2DQ(MAX) delay variation as a function of temperature. 9. tDQS2DQ(MAX) delay variation as a function of the DC voltage variation for VDDQ and
VDD2. It includes the VDDQ and VDD2 AC noise impact for frequencies >20 MHz and MAX voltage of 45mV peak-to-peak from DC-20 MHz at a fixed temperature on the package. 10. The same voltage and temperature are applied to tDQS2DQ_rank2rank. 11. tDQS2DQ_rank2rank parameter is applied to multi-ranks per byte lane within a package consisting of the same design die.

Table 228: CKE Input Timing

Parameter
CKE minimum pulse width (HIGH and LOW pulse width)
Delay from valid command to CKE input LOW
Valid clock requirement after CKE input LOW
Valid CS requirement before CKE input LOW
Valid CS requirement after CKE input LOW
Valid Clock requirement before CKE Input HIGH
Exit power-down to next valid command delay
Valid CS requirement before CKE input HIGH

Symbol tCKE
tCMDCKE tCKELCK tCSCKE tCKELCS tCKCKEH
tXP tCSCKEH

Min/ Max Min Min Min Min Min Min Min Min

1600

Data Rate 3200 3733

4267

MAX(7.5ns, 4nCK)

MAX(1.75ns, 3nCK)

MAX(5ns, 5nCK)

1.75

MAX(5ns, 5nCK)

MAX(1.75ns, 3nCK)

MAX(7.5ns, 5nCK)

1.75

Unit ns ns ns ns ns ns ns ns

Notes 1 1 1
1 1 1

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

352

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP AC Timing

Table 228: CKE Input Timing (Continued)

Parameter
Valid CS requirement after CKE input HIGH
Valid clock and CS requirement after CKE input LOW after MRW command
Valid clock and CS requirement after CKE input LOW after ZQCAL START command

Symbol tCKEHCS tMRWCKEL
tZQCKE

Min/ Max Min
Min
Min

1600

Data Rate 3200 3733

4267

MAX(7.5ns, 5nCK)

MAX(14ns, 10nCK)

MAX(1.75ns, 3nCK)

Unit ns ns
ns

Notes 1 1
1

Note: 1. Delay time has to satisfy both analog time(ns) and clock count (nCK). For example, tCMDCKE will not expire until CK has toggled through at least 3 full cycles (3tCK) and 3.75ns has transpired. The case that 3nCK is applied to is shown below.

Figure 235: tCMDCKE Timing

T-1 T0 T1 T2 T3 T4 CK_c

CK_t

tCMDCKE

CKE CS

CA Valid Valid

Command Valid

DES

Don't Care

Table 229: Command Address Input Timing

Parameter

Symbol

Command/address valid window (referenced from CA VIL/VIH to CK VIX)
Address and control input pulse width (referenced to VREF)

tcIVW tcIPW

Min/ Max Min
Min

533 0.55

Data Rate 1066 1600 2133 2667 3200 3733 4267

Unit

Notes

0.3

tCK(AVG) 1, 2, 3

0.55 0.55 0.6 0.6 0.6 0.6 0.6 tCK(AVG) 4

Notes: 1. CA Rx mask timing parameters at the pin including voltage and temperature drift. 2. Rx differential CA to CK jitter total timing window at the VcIVW voltage levels.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

353

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP AC Timing

3. Defined over the CA internal VREF range. The Rx mask at the pin must be within the internal VREF(CA) range irrespective of the input signal common mode.
4. CA only minimum input pulse width defined at the VCENT_CA(pin mid).

Table 230: Boot Timing Parameters (10­55 MHz)

Parameter
Clock cycle time
DQS output data acess time from CK DQS edge to output data edge

Symbol tCKb
tDQSCKb tDQSQb

Min/ Max Min Max Min Max
Max

Value 18 100 1.0 10.0
1.2

Unit ns ns ns

Table 231: Mode Register Timing Parameters

Parameter
MODE REGISTER WRITE (MRW) command period
MODE REGISTER SET command delay
MODE REGISTER READ (MRR) command period
Additional time after tXP has expired until the MRR command may be issued
Delay from MRW command to DQS driven out

Symbol tMRW tMRD tMRR
tMRRI
tSDO

Min/ Max Min Min Min
Min
Max

1600

Data Rate

3200

3733

MAX(10ns, 10nCK)

MAX(14ns, 10nCK)

8

4267

tRCD(MIN) + 3nCK

MAX(12nCK, 20ns)

Unit ns ns
tCK(AVG)
ns
ns

Table 232: Core Timing Parameters

Refresh rate is determined by the value in MR4 OP[2:0]

Parameter

Min/ Symbol Max 533 1066

READ latency (DBI disabled)

RL-A Min 6

10

READ latency (DBI enabled)

RL-B Min 6

12

WRITE latency (Set A)

WL-A Min 4

6

WRITE latency (Set B)

WL-B Min 4

8

1600 14
16 8 12

Data Rate 2133 2667
20 24
22 28 10 12 18 22

3200 28
32 14 26

3733 32
36 16 30

4267 36
40 18 34

Unit tCK(AVG)
tCK(AVG) tCK(AVG) tCK(AVG)

Notes

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

354

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP AC Timing

Table 232: Core Timing Parameters (Continued)

Refresh rate is determined by the value in MR4 OP[2:0]

Parameter

Min/

Data Rate

Symbol Max 533 1066 1600 2133 2667 3200 3733 4267

Unit

ACTIVATE-to-ACTIVATE command period (same bank)

tRC

Min

tRAS + tRPab
(with all-bank precharge) tRAS + tRPpb
(with per-bank precharge)

ns

Minimum self refresh time (entry to exit)

tSR

Min

MAX(15ns, 3nCK)

ns

Self refresh exit to next valid command delay

tXSR Min

MAX(tRFCab + 7.5ns, 2nCK)

ns

CAS-to-CAS delay

tCCD Min

8

tCK(AVG)

CAS-to-CAS delay masked write

tCCDMW

Min

32

tCK(AVG)

Internal READ-to-PRECHARGE command delay

tRTP

Min

MAX(7.5ns, 8nCK)

ns

RAS-to-CAS delay

tRCD Min

MAX(18ns, 4nCK)

ns

Row precharge time (single bank)

tRPpb

Min

MAX(18ns, 3nCK)

ns

Row precharge time (all banks)

tRPab Min

MAX(21ns, 3nCK)

ns

Row active time

tRAS

Min Max

MAX(42ns, 3nCK) MIN(9 × tREFI × Refresh Rate, 70.2)

ns µs

Write recovery time

tWR

Min

MAX(18ns, 4nCK)

ns

Write-to-read delay

tWTR Min

MAX(10ns, 8nCK)

ns

Active bank A to active bank B

tRRD Min

MAX(10ns, 4nCK)

MAX( 7.5ns, ns 4nCK)

Precharge-to-precharge delay

tPPD Min

4

tCK(AVG)

Four-bank activate window

tFAW Min

40

30

ns

Delay from SRE command to CKE input LOW

tESCKE

Min

MAX(1.75ns, 3nCK)

­

Notes
1 2 1 3

Notes:

1. 4267 Mb/s timing value is supported at lower data rates if the device is supporting 4266 Mb/s speed grade.
2. Precharge to precharge timing restriction does not apply to AUTO PRECHARGE commands.
3. Delay time has to satisfy both analog time (ns) and clock count (nCK). It means that tESCKE will not expire until CK has toggled through at least three full cycles (3 tCK) and 1.75ns has transpired. The case which 3nCK is applied to is shown below.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

355

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP AC Timing

Figure 236: tESCKE Timing

T-1 T0 T1 T2 T3 T4 CK_c

CK_t

tESCKE

CKE CS

CA Valid Valid

Command

SELF REFRESH Entry

DES

Don't Care

Table 233: CA Bus ODT Timing
Parameter CA ODT value update time

Symbol tODTUP

Min/ Max
Min

Data Rate 533-4267 RU(20ns/tCK(AVG))

Table 234: CA Bus Training Parameters

Parameter

Symbol

Valid clock requirement after CKE input LOW

tCKELCK

Data setup for VREF training mode Data hold for VREF training mode Asynchronous data read

tDStrain tDHtrain
tADR

CA BUS TRAINING command-to-command delay

tCACD

Valid strobe requirement before CKE LOW

tDQSCKE

First CA BUS TRAINING command following CKE LOW

tCAENT

VREF step time ­ multiple steps VREF step time ­ one step Valid clock requirement before CS HIGH

tVREFca_LONG tVREFca_SHORT
tCKPRECS

Valid clock requirement after CS HIGH

tCKPSTCS

Min/ Max Min Min Min Max Min
Min
Min Max Max Min
Min

1600

Data Rate 3200 3733
MAX(5ns, 5nCK)
2 2 20
RU(tADR/tCK)

4267

10

250
250 80 2tCK + tXP

MAX(7.5ns, 5nCK)

Unit tCK
ns ns ns tCK

Notes 1

ns

ns ns ns ­

­

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

356

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP AC Timing

Table 234: CA Bus Training Parameters (Continued)

Parameter Minimum delay from CS to DQS toggle in command bus training Minimum delay from CKE HIGH to strobe High-Z CA bus training CKE HIGH to DQ tristate ODT turn-on latency from CKE ODT turn-off latency from CKE
Exit command bus training mode to next valid command delay

Symbol tCS_VREF
tCKEHDQS
tMRZ tCKELODTon tCKEHODToff tXCBT_Short tXCBT_Middle tXCBT_Long

Min/ Max
Min
Min
Min
Min Min Min Min Min

1600

Data Rate 3200 3733
2

4267

10

1.5
20 20 MAX(200ns, 5nCK) MAX(200ns, 5nCK) MAX(250ns, 5nCK)

Unit tCK

Notes

ns

ns

ns

ns

­

2

­

2

­

2

Notes:

1. If tCACD is violated, the data for samples which violate tCACD will not be available, except for the last sample (where tCACD after this sample is met). Valid data for the last sample will be available after tADR.
2. Exit command bus training mode to next valid command delay time depends on value of VREF(CA) setting: MR12 OP[5:0] and VREF(CA) range: MR12 OP[6] of FSP-OP 0 and 1. The details are shown in tFC value mapping table. Additionally exit command bus training mode to next valid command delay time may affect VREF(DQ) setting. Settling time of VREF(DQ) level is same as VREF(CA) level.

Table 235: Asynchronous ODT Turn On and Turn Off Timing

Symbol tODTon(MIN) tODTon(MAX) tODToff(MIN) tODToff(MAX)

800­2133 MHz 1.5 3.5 1.5 3.5

Unit ns ns ns ns

Table 236: Temperature Derating Parameters

Parameter DQS output access time from CK_t/CK_c (derated) RAS-to-CAS delay (derated) ACTIVATE-to-ACTIVATE command period (same bank, derated) Row active time (derated) Row precharge time (derated)

Symbol tDQSCKd
tRCDd tRCd tRASd tRPd

Min/ Max
Max
Min
Min
Min Min

1600

Data Rate

3200

3733

3600

tRCD + 1.875

tRC + 3.75

tRAS + 1.875 tRP + 1.875

4267

Unit ps ns ns ns ns

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

357

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP AC Timing

Table 236: Temperature Derating Parameters (Continued)

Parameter Active bank A to active bank B (derated)

Symbol tRRDd

Min/ Max
Min

1600

Data Rate

3200

3733

tRRD + 1.875

4267

Unit ns

Note: 1. At higher temperatures (>85°C), AC timing derating may be required. If derating is required the device will set MR4 OP[2:0] = 110b.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

358

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP CA Rx Voltage and Timing
CA Rx Voltage and Timing
The command and address (CA), including CS input receiver compliance mask for voltage and timing, is shown in the CA Receiver (Rx) Mask figure below. All CA and CS signals apply the same compliance mask and operate in single data rate mode.
The CA input Rx mask for voltage and timing is applied across all pins, as shown in the figure below. The Rx mask defines the area that the input signal must not encroach if the DRAM input receiver is expected to successfully capture a valid input signal; it is not the valid data eye.
Figure 237: CA Receiver (Rx) Mask
tcIVW_total

VcIVW

Rx Mask VCENT_CA(pin mid)

Figure 238: Across Pin VREF (CA) Voltage Variation

CAx

CAy

CAz

VCENT_CAx

VCENT_CAy

VCENT_CAz

V(cRoEFmvpaorniaetniotn)
VCENT_CA(pin mid) is defined as the midpoint between the largest VCENT_CA voltage level and the smallest VCENT_CA voltage level across all CA and CS pins for a given DRAM component. Each CA VCENT level is defined by the center, which is, the widest opening of the cumulative data input eye, as depicted in the figure above. This clarifies that any DRAM component level variation must be accounted for within the CA Rx mask. The component-level VREF will be set by the system to account for RON and ODT settings.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

359

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP CA Rx Voltage and Timing
Figure 239: CA Timings at the DRAM Pins CK, CK Data-in at DRAM Pin
Minimum CA eye center aligned CK_c CK_t

VcIVW

CA

Rx mask DRAM pin

tcIVW
TcIVW for all CA signals is defined as centered on the CK_t/CK_c crossing at the DRAM pin.

Note:

1. All of the timing terms in above figure are measured from the CK_t/CK_c to the center (midpoint) of the TcIVW window taken at the VcIVW_total voltage levels centered around VCENT_CA(pin mid).

Figure 240: CA tcIPW and SRIN_cIVW Definition (for Each Input Pulse)

tr

tf

Rx Mask

VCENT_CA(pin mid)

VcIVW

tcIPW
Note: 1. SRIN_cIVW = VdIVW_total/(tr or tf); signal must be monotonic within tr and tf range. Figure 241: CA VIHL_AC Definition (for Each Input Pulse)

VCENT_CA

Rx Mask

Rx Mask

Rx Mask

VcIVW

VIHL(AC)min/2 VIHL(AC)min/2

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

360

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP CA Rx Voltage and Timing

Table 237: DRAM CMD/ADR, CS UI = tCK(AVG)MIN

Symbol Parameter

VclVW

Rx mask voltage peak-topeak

VIHL(AC)

CA AC input pulse amplitude peak-to-peak

SRIN_clVW Input slew rate over VclVW

DQ ­ 13337

Min Max

­

175

DQ ­ 1600/1867

Min Max

­

175

DQ ­ 3200/3733

Min Max

­

155

DQ ­ 4267

Min Max

­

145

Unit Notes mV 1, 2, 3

210

­

210

­

190

­

180

­

mV 4, 6

1

7

1

7

1

7

1

7

V/ns

5

Notes:

1. CA Rx mask voltage and timing parameters at the pin, including voltage and temperature drift.
2. Rx mask voltage VcIVW total(MAX) must be centered around VCENT_CA(pin mid). 3. Defined over the CA internal VREF range. The Rx mask at the pin must be within the in-
ternal VREF(CA) range irrespective of the input signal common mode. 4. CA-only input pulse signal amplitude into the receiver must meet or exceed VIHL(AC) at
any point over the total UI. No timing requirement above level. VIHL(AC) is the peak-topeak voltage centered around VCENT_CA(pin mid), such that VIHL(AC)/2 (MIN) must be met both above and below VCENT_CA. 5. Input slew rate over VcIVW mask is centered at VCENT_CA(pin mid). 6. VIHL(AC) does not have to be met when no transitions are occurring. 7. The Rx voltage and absolute timing requirements apply for DQ operating frequencies at or below 1333 for all speed bins. For example the tcIVW (ps) = 450ps at or below 1333 operating frequencies.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

361

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP DQ Tx Voltage and Timing

DQ Tx Voltage and Timing

DRAM Data Timing

Figure 242: Read Data Timing Definitions ­ tQH and tDQSQ Across DQ Signals per DQS Group

DQS_c

tQSH(DQS_t) tQSL(DQS_t)

DQS_t
tQH

tDQSQ

Associated DQ pins

DQS_c DQS_t

DQx

tQW

DQy

tQW

DQz

tQW

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

362

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP DQ Rx Voltage and Timing
DQ Rx Voltage and Timing
The DQ input receiver mask for voltage and timing is applied per pin, as shown in the DQ Receiver (Rx) Mask figure below. The total mask (VdIVW_total, TdIVW_total) defines the area that the input signal must not encroach in order for the DQ input receiver to successfully capture an input signal. The mask is a receiver property, and it is not the valid data eye.
Figure 243: DQ Receiver (Rx) Mask
TdIVW_total

VdIVW

Rx Mask VCENT_DQ(pin mid)

Figure 244: Across Pin VREF DQ Voltage Variation

DQx

DQy

DQz

VCENT_DQx

VCENT_DQy

VCENT_DQz

VREF variation (component)
VCENT_DQ(pin_mid) is defined as the midpoint between the largest VCENT_DQ voltage level and the smallest VCENT_DQ voltage level across all DQ pins for a given DRAM component. Each VCENT_DQ is defined by the center, which is the widest opening of the cumulative data input eye as shown in the figure above. This clarifies that any DRAM component level variation must be accounted for within the DRAM Rx mask. The componentlevel VREF will be set by the system to account for RON and ODT settings.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

363

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP DQ Rx Voltage and Timing

Figure 245: DQ-to-DQS tDQS2DQ and tDQDQ
DQ, DQS Data-in at DRAM Latch
Internal componsite data-eye center aligned to DQS DQS_c DQS_t

DQS, DQs Data-in Skews at DRAM
Nonminimum data-eye/maximum Rx mask DQS_c DQS_t
tDQS2DQ2

VdIVW_total

DQx, y, z

DQx

Rx mask DRAM pin

VdIVW_total

All DQ signals center aligned to the strobe at the device internal latch

DQy

tDQS2DQy2
Rx mask DRAM pin

tDQS2DQz2

VdIVW_total

DQz

Rx mask DRAM pin

tDQDQ

Notes:

1. These timings at the DRAM pins are referenced from the internal latch. 2. tDQS2DQ is measured at the center (midpoint) of the TdIVW window. 3. DQz represents the MAX tDQS2DQ in this example. 4. DQy represents the MIN tDQS2DQ in this example.

All of the timing terms in DQ to DQS_t are measured from the DQS_t/DQS_c to the center (midpoint) of the TdIVW window taken at the V dIVW_total voltage levels centered around VCENT_DQ(pin_mid). In figure above, the timings at the pins are referenced with respect to all DQ signals center-aligned to the DRAM internal latch. The data-to-data offset is defined as the difference between the MIN and MAX tDQS2DQ for a given component.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

364

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP DQ Rx Voltage and Timing

Figure 246: DQ tDIPW and SRIN_dIVW Definition for Each Input Pulse

UI = tCK(AVG) MIN/2

tr

tf

Rx Mask

VCENT_DQ(pin mid)

VDIVW_total

tDIPW
Note: 1. SRIN_dIVW = VdIVW_total/(tr or tf) signal must be monotonic within tr and tf range. Figure 247: DQ VIHL(AC) Definition (for Each Input Pulse)

VCENT_DQ

Rx Mask

Rx Mask

Rx Mask

VIHL(AC)min/2 VdIVW_total
VIHL(AC)min/2

Table 238: DQs In Receive Mode Note UI = tCK(AVG)(MIN)/2

Symbol VdIVW_total
VIHL(AC)
SRIN_dIVW

Parameter
Rx mask voltage ­ peak-topeak
DQ AC input pulse amplitude peak-to-peak
Input slew rate over VdIVW_total

1600/1867 Min Max
­ 140

180 ­

1

7

2133/2400 Min Max
­ 140

180 ­

1

7

3200/3733 Min Max
­ 140

180 ­

1

7

4267 Min Max
­ 120

Unit mV

Notes 1, 2, 3

170 ­ mV 5, 7

1

7 V/ns

6

Notes:

1. Data Rx mask voltage and timing parameters are applied per pin and include the DRAM DQ-to-DQS voltage AC noise impact for frequencies >20 MHz with a maximum voltage of 45mV peak-to-peak at a fixed temperature on the package. The voltage supply noise must comply to the component MIN/MAX DC operating conditions.
2. Rx mask voltage VdIVW_total(MAX) must be centered around VCENT_DQ(pin_mid). 3. Defined over the DQ internal VREF range. The Rx mask at the pin must be within the in-
ternal VREF DQ range irrespective of the input signal common mode. 4. Deterministic component of the total Rx mask voltage or timing. Parameter will be char-
acterized and guaranteed by design.
5. DQ-only input pulse amplitude into the receiver must meet or exceed VIHL(AC) at any point over the total UI. No timing requirement above level. VIHL(AC) is the peak-to-peak voltage centered around VCENT_DQ(pin_mid), such that VIHL(AC)/2 (MIN) must be met both above and below VCENT_DQ.
6. Input slew rate over VdIVW mask centered at VCENT_DQ(pin_mid).

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

365

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Clock Specification

7. VIHL(AC) does not have to be met when no transitions are occurring.
Clock Specification
The specified clock jitter is a random jitter with Gaussian distribution. Input clocks violating minimum or maximum values may result in device malfunction.

Table 239: Definitions and Calculations

Symbol tCK(avg) and nCK
tCK(abs) tCH(avg)
tCL(avg)
tJIT(per) tJIT(per),act tJIT(per), allowed tJIT(cc) tERR(nper) tERR(nper),act

Description

Calculation

 The average clock period across any consecutive

N

200-cycle window. Each clock period is calculated tCK(avg) = tCKj /N

from rising clock edge to rising clock edge.

j = 1

Unit tCK(avg) represents the actual clock average

Where N = 200

tCK(avg) of the input clock under operation. Unit

nCK represents one clock cycle of the input clock,

counting from actual clock edge to actual clock

edge.

tCK(avg) can change no more than ±1% within a 100-clock-cycle window, provided that all jitter and timing specifications are met.

The absolute clock period, as measured from one rising clock edge to the next consecutive rising clock edge.

The average HIGH pulse width, as calculated across any 200 consecutive HIGH pulses.

N
 tCH(avg) = tCHj /(N × tCK(avg)) j = 1

Where N = 200

The average LOW pulse width, as calculated across any 200 consecutive LOW pulses.

N
 tCL(avg) = tCLj /(N × tCK(avg)) j = 1 Where N = 200

The single-period jitter defined as the largest deviation of any signal tCK from tCK(avg).

tJIT(per) = min/max of

tCKi ­ tCK(avg)

Where i = 1 to 200

The actual clock jitter for a given system. The specified clock period jitter allowance.

The absolute difference in clock periods between two consecutive clock cycles. tJIT(cc) defines the

tJIT(cc) = max of

tCKi + 1 ­ tCKi

cycle-to-cycle jitter.

The cumulative error across n multiple consecutive cycles from tCK(avg).

tERR(nper) =

i + n ­ 1
 tCKj ­ (n × tCK(avg))
j = i

The actual clock jitter over n cycles for a given system.

Notes
1
1 1 1

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

366

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Clock Period Jitter

Table 239: Definitions and Calculations (Continued)

Symbol
tERR(nper), allowed

Description

Calculation

The specified clock jitter allowance over n cycles.

tERR(nper),min The minimum tERR(nper).

tERR(nper),min = (1 + 0.68LN(n)) × tJIT(per),min

tERR(nper),max The maximum tERR(nper).

tERR(nper),max = (1 + 0.68LN(n)) × tJIT(per),max

tJIT(duty)

Defined with absolute and average specifications tJIT(duty),min =

for tCH and tCL, respectively.

MIN((tCH(abs),min ­ tCH(avg),min),

(tCL(abs),min ­ tCL(avg),min)) × tCK(avg)

tJIT(duty),max = MAX((tCH(abs),max ­ tCH(avg),max), (tCL(abs),max ­ tCL(avg),max)) × tCK(avg)

Notes
2 2

Notes: 1. Not subject to production testing. 2. Using these equations, tERR(nper) tables can be generated for each tJIT(per),act value.
tCK(abs), tCH(abs), and tCL(abs)
These parameters are specified with their average values; however, the relationship between the average timing and the absolute instantaneous timing (defined in the following table) is applicable at all times.

Table 240: tCK(abs), tCH(abs), and tCL(abs) Definitions

Parameter Absolute clock period Absolute clock HIGH pulse width Absolute clock LOW pulse width

Symbol tCK(abs) tCH(abs) tCL(abs)

Minimum tCK(avg),min + tJIT(per),min tCH(avg),min + tJIT(duty),min2/tCK(avg),min tCL(avg),min + tJIT(duty),min2/tCK(avg),min

Notes: 1. tCK(avg),min is expressed in ps for this table. 2. tJIT(duty),min is a negative value.

Unit ps1 tCK(avg) tCK(avg)

Clock Period Jitter
LPDDR4 devices can tolerate some clock period jitter without core timing parameter derating. This section describes device timing requirements with clock period jitter (tJIT(per)) in excess of the values found in the AC Timing table. Calculating cycle time derating and clock cycle derating are also described.
Clock Period Jitter Effects on Core Timing Parameters
Core timing parameters (tRCD, tRP, tRTP, tWR, tWRA, tWTR, tRC, tRAS, tRRD, tFAW) extend across multiple clock cycles. Clock period jitter impacts these parameters when measured in numbers of clock cycles. Within the specification limits, the device is characterized and verified to support tnPARAM = RU[tPARAM/tCK(avg)]. During device operation where clock jitter is outside specification limits, the number of clocks, or tCK(avg), may need to be increased based on the values for each core timing parameter.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

367

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Clock Period Jitter

Cycle Time Derating for Core Timing Parameters

For a given number of clocks (tnPARAM), when tCK(avg) and tERR(tnPARAM),act exceed tERR(tnPARAM),allowed, cycle time derating may be required for core timing parameters.

CycleTimeDerating = max

tPARAM

+tERR(tnPARAM),act ­ tERR(tnPARAM),all tnPARAM

owed

­

tCK(avg)

,

0

Cycle time derating analysis should be conducted for each core timing parameter. The amount of cycle time derating required is the maximum of the cycle time deratings determined for each individual core timing parameter.

Clock Cycle Derating for Core Timing Parameters

For each core timing parameter and a given number of clocks (tnPARAM), clock cycle derating should be specified with tJIT(per).

For a given number of clocks (tnPARAM), when tCK(avg) plus (tERR(tnPARAM),act) exceed the supported cumulative tERR(tnPARAM),allowed, derating is required. If the equation below results in a positive value for a core timing parameter (tCORE), the required clock cycle derating will be that positive value (in clocks).

ClockCycleDerating = RU

tPARAM + tERR(tnPARAM),act ­ tERR(tnPARAM),allowed tCK(avg)

­ tnPARAM

Cycle-time derating analysis should be conducted for each core timing parameter.

Clock Jitter Effects on Command/Address Timing Parameters
Command/address timing parameters (tIS, tIH, tISb, tIHb) are measured from a command/address signal (CS or CA[5:0]) transition edge to its respective clock signal (CK_t/ CK_c) crossing. The specification values are not affected by the tJIT(per) applied, because the setup and hold times are relative to the clock signal crossing that latches the command/address. Regardless of clock jitter values, these values must be met.

Clock Jitter Effects on READ Timing Parameters

tRPRE

When the device is operated with input clock jitter, tRPRE must be derated by the tJIT(per),act,max of the input clock that exceeds tJIT(per),allowed,max. Output deratings are relative to the input clock:

tRPRE(min,derated) = 0.9 ­

tJIT(per),act,max ­ tJIT(per),allowed,max tCK(avg)

For example, if the measured jitter into a LPDDR4 device has tCK(avg) = 625ps, tJIT(per),act,min = ­xx, and tJIT(per),act,max = +xx ps, then tRPRE,min,derated = 0.9 (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = 0.9 - (xx - xx)/xx = yy tCK(avg).

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

368

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Clock Period Jitter

tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS)
These parameters are measured from a specific clock edge to a data signal transition (DMn or DQm, where: n = 0,1; and m = 0­15, and specified timings must be met with respect to that clock edge. Therefore, they are not affected by tJIT(per).
tQSH, tQSL
These parameters are affected by duty cycle jitter, represented by tCH(abs)min and tCL(abs)min. These parameters determine the absolute data-valid window at the device pin. The absolute minimum data-valid window at the device pin = MIN {(tQSH(abs)min - tDQSQmax), (tQSL(abs)min - tDQSQmax)}. This minimum data valid window must be met at the target frequency regardless of clock jitter.
tRPST
tRPST is affected by duty cycle jitter, represented by tCL(abs). Therefore, tRPST(abs)min can be specified by tCL(abs)min. tRPST(abs)min = tCL(abs)min - 0.05 = tQSL(abs)min.

Clock Jitter Effects on WRITE Timing Parameters

tDS, tDH

These parameters are measured from a data signal (DMIn or DQm, where n = 0, 1 and m = 0­15) transition edge to its respective data strobe signal (DQSn_t, DQSn_c: n = 0,1) crossing. The specification values are not affected by the amount of tJIT(per) applied, because the setup and hold times are relative to the data strobe signal crossing that latches the command/address. Regardless of clock jitter values, these values must be met.

tDSS, tDSH

These parameters are measured from a data signal (DQS_t, DQSn_c) crossing to its respective clock signal (CK_t, CK_c) crossing. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per)act of the input clock in excess of the allowed period jitter tJIT(per)allowed.
tDQSS

tDQSS is measured from a data strobe signal (DQSn_t, DQSn_c) crossing to its respective clock signal (CK_t, CK_c) crossing. When the device is operated with input clock jitter, this parameter must be derated by the actual tJIT(per),act of the input clock in excess of tJIT(per)allowed.

tDQSS(min,derated) = 0.75 -

tJIT(per),act,min ­ tJIT(per),allowed, min tCK(avg)

tDQSS(max,derated) = 1.25 ­

tJIT(per),act,max ­ tJIT(per),allowed, max tCK(avg)

For example, if the measured jitter into an LPDDR4 device has tCK(avg) = 625ps, tJIT(per),act,min = -xxps, and tJIT(per),act,max = +xx ps, then: tDQSS,(min,derated) = 0.75 - (-xx + yy)/625 = xxxx tCK(avg) tDQSS,(max,derated) = 1.25 - (xx ­ yy)/625 = xxxx tCK(avg)

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

369

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 1.10V VDDQ
LPDDR4 1.10V VDDQ
This section defines LPDDR4 specifications to enable 1.10 VDDQ operation of LPDDR4 devices.
Power-Up and Initialization - LPDDR4
To ensure proper functionality for power-up and reset initialization, default values for the MR settings are provided in the table below.

Table 241: Mode Register Default Settings

Item FSP-OP/WR
WLS WL RL nWR DBI-WR/RD

Mode Register Setting MR13 OP[7:6] MR2 OP[6] MR2 OP[5:3] MR2 OP[2:0] MR1 OP[6:4] MR3 OP[7:6]

CA ODT DQ ODT VREF(CA) setting VREF(CA) value VREF(DQ) setting VREF(DQ) value

MR11 OP[6:4] MR11 OP[2:0] MR12 OP[6] MR12 OP[5:0] MR14 OP[6] MR14 OP[5:0]

Default Setting 00b 0b 000b 000b 000b 00b
000b 000b
1b 001101b
1b 001101b

Description FSP-OP/WR[0] are enabled WRITE latency set A is selected WL = 4 RL = 6, nRTP = 8 nWR = 6 Write and read DBI are disabled CA ODT is disabled DQ ODT is disabled VREF(CA) range[1] is enabled Range1: 27.2% of VDD2 VREF(DQ) range[1] enabled Range1: 27.2% of VDDQ

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

370

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 1.10V VDDQ
Mode Register Definition - LPDDR4
Mode register definitions are provided in the Mode Register Assignments table. In the access column of the table, R indicates read-only; W indicates write-only; R/W indicates read- or write-capable or enabled. The MRR command is used to read from a register. The MRW command is used to write to a register.

Table 242: Mode Register Assignments

Notes 1­5 apply to entire table MR# MA[5:0] Function

0

00h Device info

1

01h Device feature 1

2

02h Device feature 2

3

03h I/O config-1

4

04h Refresh and

training

5

05h Basic config-1

6

06h Basic config-2

7

07h Basic config-3

8

08h Basic config-4

9

09h Test mode

10

0Ah I/O calibration

11

0Bh ODT

12

0Ch VREF(CA)

13

0Dh Register control

14

0Eh VREF(DQ)

15

0Fh DQI-LB

16

10h PASR_Bank

17

11h PASR_Seg

18

12h IT-LSB

19

13h IT-MSB

20

14h DQI-UB

21

15h Vendor use

22

16h ODT feature 2

23

17h DQS oscillator

stop

24

18h TRR control

25

19h PPR resources

26­29 1Ah~1D

­

h

Access R
W W W R /W
R R R R W W W R/W W R/W W W W R R W W W
W
R/W
R ­

OP7 CATR
RD-PST WR Lev DBI-WR
TUF

OP6

OP5

OP4

OP3

OP2

OP1

OP0

RFU

RFU

RZQI

RFU Latency REF mode

nWR (for AP)

RD-PRE WR-PRE

BL

WLS

WL

RL

DBI-RD

PDDS

PPRP WR-PST PU-CAL

Thermal offset PPRE SR abort

Refresh rate

Manufacturer ID

Revision ID1

Revision ID2

I/O width

Density

Type

Vendor-specific test mode

RFU

ZQ RST

RFU

CA ODT

RFU

DQ ODT

RFU

VRCA

VREF(CA)

FSP-OP FSP-WR DMD RRO VRCG VRO

RPT

CBT

RFU

VRDQ

VREF(DQ)

Lower-byte invert register for DQ calibration

PASR bank mask

PASR segment mask

DQS oscillator count ­ LSB

DQS oscillator count ­ MSB

Upper-byte invert register for DQ calibration

RFU

ODTD for x8_2ch ODTD- ODTE-CS ODTE-

CA

CK

SoC ODT

DQS oscillator run-time setting

TRR mode
B7

TRR mode BAn

Unltd MAC

MAC value

B6

B5

B4

B3

B2

B1

B0

Reserved for future use

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

371

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 1.10V VDDQ

Table 242: Mode Register Assignments (Continued)

Notes 1­5 apply to entire table MR# MA[5:0] Function

30

1Eh

Reserved for

test

31

1Fh

­

32

20h DQ calibration

pattern A

33­38 21h26h Do not use

39

27h

Reserved for

test

40

28h DQ calibration

pattern B

41­47 29h2Fh Do not use

48­63 30h3Fh Reserved

Access W
­ W
­ W
W
­ ­

OP7

OP6

OP5

OP4

OP3

OP2

SDRAM will ignore

Reserved for future use See DQ calibration section

Do not use SDRAM will ignore

See DQ calibration section

Do not use Reserved for future use

OP1

OP0

Notes:

1. RFU bits must be set to 0 during MRW commands. 2. RFU bits are read as 0 during MRR commands. 3. All mode registers that are specified as RFU or write-only shall return undefined data
when read via an MRR command. 4. RFU mode registers must not be written. 5. Writes to read-only registers will not affect the functionality of the device.

Table 243: MR0 Device Feature 0 (MA[5:0] = 00h)

OP7 CATR

OP6

OP5

RFU

OP4

OP3

RZQI

OP2 RFU

OP1 Latency mode

OP0 REF

Table 244: MR0 Op-Code Bit Definitions

Register Information Refresh mode
Latency mode
Built-in self-test for RZQ information

Type
Read only
Read only
Read only

OP OP[0] OP[1]
OP[4:3]

Definition
0b: Both legacy and modified refresh mode supported 1b: Only modified refresh mode supported
0b: Device supports normal latency
1b: Device supports byte mode latency
00b: RZQ self-test not supported
01b: ZQ may connect to VSSQ or float 10b: ZQ may short to VDDQ 11b: ZQ pin self-test completed, no error condition detected (ZQ may not connect to VSSQ, float, or short to VDDQ)

Notes 5, 6 1­4

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

372

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 1.10V VDDQ

Table 244: MR0 Op-Code Bit Definitions (Continued)

Register Information CA terminating rank

Type
Read only

OP OP[7]

Definition 0b: CA for this rank is not terminated 1b: CA for this rank is terminated

Notes 7

Notes:

1. RZQI MR value, if supported, will be valid after the following sequence:
· Completion of MPC[ZQCAL START] command to either channel · Completion of MPC[ZQCAL LATCH] command to either channel then tZQLAT is satis-
fied RZQI value will be lost after reset.
2. If ZQ is connected to VSSQ to set default calibration, OP[4:3] must be set to 01b. If ZQ is not connected to VSSQ, either OP[4:3] = 01b or OP[4:3] = 10b might indicate a ZQ pin assembly error. It is recommended that the assembly error be corrected.
3. In the case of possible assembly error, the device will default to factory trim settings for RON, and will ignore ZQ CALIBRATION commands. In either case, the device may not function as intended.
4. If the ZQ pin self-test returns OP[4:3] = 11b, the device has detected a resistor connected to the ZQ pin. However, this result cannot be used to validate the ZQ resistor value or that the ZQ resistor meets the specified limits (that is, 240 ±1%).
5. See byte mode addendum spec for byte mode latency details.
6. Byte mode latency for 2Ch. x16 device is only allowed when it is stacked in a same package with byte mode device.
7. CATR indicates whether CA for the rank will be terminated or not as a result of ODTCA pad connection and MR22 OP[5] settings for x16 devices, MR22 OP[7:5] settings for byte mode devices.

Table 245: MR3 I/O Configuration 1 (MA[5:0] = 03h)

OP7 DBI-WR

OP6 DBI-RD

OP5

OP4 PDDS

OP3

OP2 PPRP

OP1 WR-PST

OP0 PU-CAL

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

373

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 1.10V VDDQ

Table 246: MR3 Op-Code Bit Definitions

Feature PU-CAL (Pull-up calibration point)
WR-PST (WR postamble length)

Type

PPRP (Post-package repair protection) PDDS (Pull-down drive strength)
Write-only

DBI-RD (DBI-read enable)
DBI-WR (DBI-write enable)

OP OP[0] OP[1] OP[2]
OP[5:3]
OP[6] OP[7]

Definition
0b: VDDQ/2.5 1b: VDDQ/3 (default) 0b: WR postamble = 0.5 × tCK (default) 1b: WR postamble = 1.5 × tCK
0b: PPR protection disabled (default) 1b: PPR protection enabled
000b: RFU 001b: RZQ/1 010b: RZQ/2 011b: RZQ/3 100b: RZQ/4 101b: RZQ/5 110b:RZQ/6 (default) 111b: Reserved
0b: Disabled (default) 1b: Enabled
0b: Disabled (default) 1b: Enabled

Notes 1-4
2, 3, 5 6
1, 2, 3
2, 3 2, 3

Notes:

1. All values are typical. The actual value after calibration will be within the specified tolerance for a given voltage and temperature. Recalibration may be required as voltage and temperature vary.
2. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address.
3. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1.The device will operate only according to the values stored in the registers for the active set point, for example, the set point determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation.
4. For dual channel device, PU-CAL (MR3-OP[0]) must be set the same for both channels on a die. The SDRAM will read the value of only one register (Ch.A or Ch.B), vendor-specific, so both channels must be set the same.
5. 1.5 × tCK apply > 1.6 GHz clock.
6. If MR3 OP[2] is set to 1b, PPR protection mode is enabled. The PPR protection bit is a sticky bit and can only be set to 0b by a power on reset. MR4 OP[4] controls entry to PPR mode. If PPR protection is enabled then the DRAM will not allow writing of 1b to MR4 OP[4].

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

374

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 1.10V VDDQ

Table 247: MR12 Register Information (MA[5:0] = 0Ch)

OP7 RFU

OP6 VRCA

OP5

OP4

OP3

OP2

VREF(CA)

OP1

OP0

Table 248: MR12 Op-Code Bit Definitions

Feature
VREF(CA) VREF(CA) settings
VRCA VREF(CA) range

Type
Read/ Write
Read/ Write

OP OP[5:0]
OP[6]

Data
000000b­110010b: See VREF Settings Table All others: Reserved
0b: VREF(CA) range[0] enabled 1b: VREF(CA) range[1] enabled (default)

Notes 1­3, 5, 6
1, 2, 4, 5, 6

Notes:

1. This register controls the VREF(CA) levels for frequency set point[1:0]. Values from either VR(ca)[0] or VR(ca)[1] may be selected by setting MR12 OP[6] appropriately.
2. A read to MR12 places the contents of OP[7:0] on DQ[7:0]. Any RFU bits and unused DQ will be set to 0. See the MRR Operation section.
3. A write to MR12 OP[5:0] sets the internal VREF(CA) level for FSP[0] when MR13 OP[6] = 0b or sets the internal VREF(CA) level for FSP[1] when MR13 OP[6] = 1b. The time required for VREF(CA) to reach the set level depends on the step size from the current level to the new level. See the VREF(CA) training section.
4. A write to MR12 OP[6] switches the device between two internal VREF(CA) ranges. The range (range[0] or range[1]) must be selected when setting the VREF(CA) register. The value, once set, will be retained until overwritten or until the next power-on or reset event.
5. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address.
6. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. The device will operate only according to the values stored in the registers for the active set point, for example, the set point determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation.

Table 249: Mode Register 14 (MA[5:0] = 0Eh)

OP[7] RFU

OP[6] VRDQ

OP[5]

OP[4]

OP[3]

OP[2]

VREF(DQ)

OP[1]

OP[0]

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

375

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 1.10V VDDQ

Table 250: MR14 Op-Code Bit Definition

Feature
VREF(DQ) VREF(DQ) setting
VRDQ VREF(DQ) range

Type
Read/ Write

OP OP[5:0]
OP[6]

Definition
000000b­110010b: See VREF Settings table All others: Reserved
0b: VREF(DQ) range[0] enabled 1b: VREF(DQ) range[1] enabled (default)

Notes 1­3, 5, 6
1, 2, 4­6

Notes:

1. This register controls the VREF(DQ) levels for frequency set point[1:0]. Values from either VRDQ [vendor defined] or VRDQ [vendor defined] may be selected by setting OP[6] appropriately.
2. A read (MRR) to this register places the contents of OP[7:0] on DQ[7:0]. Any RFU bits and unused DQ will be set to 0. See the MRR Operation section.
3. A write to OP[5:0] sets the internal VREF(DQ) level for FSP[0] when MR13 OP[6] = 0b, or sets FSP[1] when MR13 OP[6] = 1b. The time required for VREF(DQ) to reach the set level depends on the step size from the current level to the new level. See the VREF(DQ) training section.
4. A write to OP[6] switches the device between two internal VREF(DQ) ranges. The range (range[0] or range[1]) must be selected when setting the VREF(DQ) register. The value, once set, will be retained until overwritten, or until the next power-on or reset event.
5. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address.
6. There are two physical registers assigned to each bit of this MR parameter, designated set point 0, and set point 1. The device will operate only according to the values stored in the registers for the active set point, for example, the set point determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

376

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 1.10V VDDQ

Table 251: VREF Setting for Range[0] and Range[1]

Notes 1­3 apply to entire table Range[0] Values
VREF(CA) (% of VDD2 )

Function
VREF setting for MR12 and MR14

OP OP[5:0]

VREF(DQ) (% of VDDQ ) 000000b: 10.0% 000001b: 10.4% 000010b: 10.8% 000011b: 11.2% 000100b: 11.6% 000101b: 12.0% 000110b: 12.4% 000111b: 12.8% 001000b: 13.2% 001001b: 13.6% 001010b: 14.0% 001011b: 14.4% 001100b: 14.8% 001101b: 15.2%

011010b: 20.4% 011011b: 20.8% 011100b: 21.2% 011101b: 21.6% 011110b: 22.0% 011111b: 22.4% 100000b: 22.8% 100001b: 23.2% 100010b: 23.6% 100011b: 24.0% 100100b: 24.4% 100101b: 24.8% 100110b: 25.2% 100111b: 25.6%

001110b: 15.6% 001111b: 16.0% 010000b: 16.4% 010001b: 16.8% 010010b: 17.2% 010011b: 17.6% 010100b: 18.0% 010101b: 18.4% 010110b: 18.8% 010111b: 19.2% 011000b: 19.6% 011001b: 20.0%

101000b: 26.0% 101001b: 26.4% 101010b: 26.8% 101011b: 27.2% 101100b: 27.6% 101101b: 28.0% 101110b: 28.4% 101111b: 28.8% 110000b: 29.2% 110001b: 29.6% 110010b: 30.0% All others: Reserved

Range[1] Values

VREF(CA) (% of VDD2 )

VREF(DQ) (% of VDDQ )

000000b: 22.0%

011010b: 32.4%

000001b: 22.4%

011011b: 32.8%

000010b: 22.8%

011100b: 33.2%

000011b: 23.2%

011101b: 33.6%

000100b: 23.6%

011110b: 34.0%

000101b: 24.0%

011111b: 34.4%

000110b: 24.4%

100000b: 34.8%

000111b: 24.8%

100001b: 35.2%

001000b: 25.2%

100010b: 35.6%

001001b: 25.6%

100011b: 36.0%

001010b: 26.0%

100100b: 36.4%

001011b: 26.4%

100101b: 36.8%

001100b: 26.8%

100110b: 37.2%

001101b: 27.2% default

100111b: 37.6%

001110b: 27.6%

101000b: 38.0%

001111b: 28.0%

101001b: 38.4%

010000b: 28.4%

101010b: 38.8%

010001b: 28.8%

101011b: 39.2%

010010b: 29.2%

101100b: 39.6%

010011b: 29.6%

101101b: 40.0%

010100b: 30.0%

101110b: 40.4%

010101b: 30.4%

101111b: 40.8%

010110b: 30.8%

110000b: 41.2%

010111b: 31.2%

110001b: 41.6%

011000b: 31.6%

110010b: 42.0%

011001b: 32.0%

All others: Reserved

Notes:

1. These values may be used for MR14 OP[5:0] and MR12 OP[5:0] to set the VREF(CA) or VREF(DQ) levels in the device.
2. The range may be selected in each of the MR14 or MR12 registers by setting OP[6] appropriately.
3. Each of the MR14 or MR12 registers represents either FSP[0] or FSP[1]. Two frequency set points each for CA and DQ are provided to allow for faster switching between terminated and unterminated operation or between different high-frequency settings, which may use different terminations values.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

377

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 1.10V VDDQ

Table 252: MR22 Register Information (MA[5:0] = 16h)

OP7

OP6

ODTD for x8_2ch

OP5 ODTD-CA

OP4 ODTE-CS

OP3 ODTE-CK

OP2

OP1 SOC ODT

OP0

Table 253: MR22 Register Information

Function

Type

OP Data

SOC ODT (controller ODT value for VOH calibration)

Write-only OP[2:0] 000b: Disable (default)
001b: RZQ/1 010b: RZQ/2 011b: RZQ/3 100b: RZQ/4 101b: RZQ/5 110b: RZQ/6 111b: RFU

ODTE-CK (CK ODT enabled for non-terminating rank)

Write-only OP[3] 0b: ODT-CK override disabled (default) 1b: ODT-CK override enabled

ODTE-CS (CS ODT enabled for Write-only OP[4] 0b: ODT-CS override disabled (default)

non-terminating rank)

1b: ODT-CS override enabled

ODTD-CA (CA ODT termina- Write-only OP[5] 0b: CA ODT obeys ODT_CA bond pad (default)

tion disable)

1b: CA ODT disabled

ODTD for x8_2ch (Byte) mode Write-only OP[7:6] See Byte Mode section

Notes 1, 2, 3
2, 3, 4, 6, 8 2, 3, 5, 6, 8 2, 3, 6, 7, 8

Notes:

1. All values are typical.
2. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command or read from with an MRR command to this address.
3. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. The device will operate only according to the values stored in the registers for the active set point determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device and may be changed without affecting device operation.
4. When OP[3] = 1 the CK signals will be terminated to the value set by MR11 OP[6:4] regardless of the state of the ODT_CA bond pad. This overrides the ODT_CA bond pad for configurations where CA is shared by two or more devices but CK is not, enabling CK to terminate on all devices.
5. When OP[4] = 1 the CS signal will be terminated to the value set by MR11 OP[6:4] regardless of the state of the ODT_CA bond pad. This overrides the ODT_CA bond pad for configurations where CA is shared by two or more devices but CS is not, enabling CS to terminate on all devices.
6. For system configurations where the CK, CS, and CA signals are shared between packages, the package design should provide for the ODT_CA ball to be bonded on the system board outside of the memory package. This provides the necessary control of the ODT function for all die with shared command bus signals.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

378

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 1.10V VDDQ
7. When OP[5] = 0, CA[5:0] will terminate when the ODT_CA bond pad is HIGH and MR11 OP[6:4] is valid and disable termination when ODT_CA is LOW or MR11 OP[6:4] is disabled. When OP[5] = 1, termination for CA[5:0] is disabled regardless of the state of the ODT_CA bond pad or MR11 OP[6:4].
8. To ensure proper operation in a multi-rank configuration, when CA, CK or CS ODT is enabled via MR11 OP[6:4] and also via MR22 or ODT_CA pad setting, the rank providing ODT will continue to terminate the command bus in all DRAM states including Active, Self-refresh, Self-refresh Power-down, Active Power-down and Precharge Power-down.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

379

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 1.10V VDDQ
Burst READ Operation - LPDDR4 ATE Condition
tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation tHZ and tLZ transitions occur in the same time window as valid data transitions. These parameters are referenced to a specific voltage level that specifies when the device output is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS) and tLZ(DQ). This section shows a method to calculate the point when the device is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS) and tLZ(DQ), by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. The parameters tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as single ended.
tLZ(DQS) and tHZ(DQS) Calculation for ATE (Automatic Test Equipment) Figure 248: tLZ(DQS) Method for Calculating Transitions and Endpoint
CK_t ­ CK_c crossing at the second CAS-2 of READ command
CK_t
CK_c
tLZ(DQS)

VOH

DQS_c

0.5 x VOH

VSW2 VSW1

End point: Extrapolated point
0V

Notes:

1. Conditions for calibration: Pull down driver RON = 40 ohms, VOH = VDDQ/3. 2. Termination condition for DQS_t and DQS_C = 50 ohms to VSSQ. 3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device toler-
ances. Use the actual VOH value for tHZ and tLZ measurements.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

380

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 1.10V VDDQ
Figure 249: tHZ(DQS) Method for Calculating Transitions and Endpoint CK_t ­ CK_c crossing at the second CAS-2 of READ command
CK_t
CK_c

tHZ(DQS)
VOH

End point: Extrapolated point

0.5 x VOH

VSW2 VSW1

0V

DQS_c

Notes:

1. Conditions for calibration: Pull down driver RON = 40 ohms, VOH = VDDQ/3. 2. Termination condition for DQS_t and DQS_C = 50 ohms to VSSQ. 3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device toler-
ances. Use the actual VOH value for tHZ and tLZ measurements.

Table 254: Reference Voltage for tLZ(DQS), tHZ(DQS) Timing Measurements

Measured Parameter
DQS_c Low-Z time from CK_t, CK_c
DQS_c High-Z time from CK_t, CK_c

Measured Parameter Symbol tLZ(DQS)
tHZ(DQS)

Vsw1 0.4 × VOH
0.4 × VOH

Vsw2 0.6 × VOH
0.6 × VOH

Unit V

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

381

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 1.10V VDDQ
tLZ(DQ) and tHZ(DQ) Calculation for ATE (Automatic Test Equipment) Figure 250: tLZ(DQ) Method for Calculating Transitions and Endpoint
CK_t ­ CK_c crossing at the second CAS-2 of READ command
CK_t CK_c
t LZ(DQ)

VOH

DQs

0.5 x VOH

VSW2 VSW1

End point: Extrapolated point
0V

Notes:

1. Conditions for calibration: Pull down driver RON = 40 ohms, VOH = VDDQ/3. 2. Termination condition for DQ and DMI = 50 ohms to VSSQ. 3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device toler-
ances. Use the actual VOH value for tHZ and tLZ measurements.

Figure 251: tHZ(DQ) Method for Calculating Transitions and Endpoint

CK_t ­ CK_c crossing at the second CAS-2 of READ command
CK_t

CK_c

tHZ(DQ)
VOH

End point: Extrapolated point

0.5 x VOH

VSW2 VSW1

0V

DQs

Notes: 1. Conditions for calibration: Pull down driver RON = 40 ohms, VOH = VDDQ/3.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

382

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 1.10V VDDQ

2. Termination condition for DQ and DMI = 50 ohms to VSSQ. 3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device toler-
ances. Use the actual VOH value for tHZ and tLZ measurements.

Table 255: Reference Voltage for tLZ(DQ), tHZ(DQ) Timing Measurements

Measured Parameter
DQ Low-Z time from CK_t, CK_c
DQ High-Z time from CK_t, CK_c

Measured Parameter Symbol tLZ(DQ)
tHZ(DQ)

Vsw1 0.4 × VOH
0.4 × VOH

Vsw2 0.6 × VOH
0.6 × VOH

Unit V

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

383

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 1.10V VDDQ
VREF Specifications - LPDDR4
Internal VREF(CA) Specifications The device's internal VREF(CA) specification parameters are operating voltage range, step size, VREF step time, VREF full-range step time, and VREF valid level. The voltage operating range specifies the minimum required VREF setting range for LPDDR4 devices. The minimum range is defined by V REF,max and VREF,min.

Table 256: Internal VREF(CA) Specifications

Symbol VREF(CA),max_r0
VREF(CA),min_r0
VREF(CA),max_r1
VREF(CA),min_r1
VREF(CA),step VREF(CA),set_tol

Parameter
VREF(CA) range-0 MAX operating point
VREF(CA) range-0 MIN operating point
VREF(CA) range-1 MAX operating point
VREF(CA) range-1 MIN operating point
VREF(CA) step size VREF(CA) set tolerance

tVREF_TIME-SHORT tVREF_TIME-MIDDLE
tVREF_TIME-LONG tVREF_time_weak
VREF(CA)_val_tol

VREF(CA) step time VREF(CA) valid tolerance

Min ­
10%
­
22%
0.30% ­1.00% ­0.10%
­ ­ ­ ­ ­0.10%

Typ ­
­
­
­
0.40% 0.00% 0.00%
­ ­ ­ ­ 0.00%

Max 30%
­
42%
­
0.50% 1.00% 0.10%
100 200 250
1 0.10%

Unit VDD2
VDD2
VDD2
VDD2
VDD2 VDD2 VDD2
ns ns ns ms VDD2

Notes 1, 11
1, 11
1, 11
1, 11
2 3, 4, 6 3, 5, 7
8 12 9 13, 14 10

Notes:

1. VREF(CA) DC voltage referenced to VDD2(DC). 2. VREF(CA) step size increment/decrement range. VREF(CA) at DC level. 3. VREF(CA),new = VREF(CA),old + n × VREF(CA),step; n = number of steps; if increment, use "+"; if
decrement, use "­".

4. The minimum value of VREF(CA) setting tolerance = VREF(CA),new - 1.0% × VDD2. The maximum value of VREF(CA) setting tolerance = VREF(CA),new + 1.0% × VDD2. For n > 4.
5. The minimum value of VREF(CA) setting tolerance = VREF(CA),new - 0.10% × VDD2. The maximum value of VREF(CA) setting tolerance = VREF(CA),new + 0.10% × VDD2. For n < 4.
6. Measured by recording the minimum and maximum values of the VREF(CA) output over the range, drawing a straight line between those points and comparing all other

VREF(CA) output settings to that line. 7. Measured by recording the minimum and maximum values of the VREF(CA) output across
four consecutive steps (n = 4), drawing a straight line between those points and compar-

ing all other VREF(CA) output settings to that line. 8. Time from MRW command to increment or decrement one step size for VREF(CA) . 9. Time from MRW command to increment or decrement VREF,min to VREF,max or VREF,max to
VREF,min change across the VREF(CA) range in VREF voltage. 10. Only applicable for DRAM component level test/characterization purposes. Not applica-

ble for normal mode of operation. VREF valid is to qualify the step times which will be characterized at the component level.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

384

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 1.10V VDDQ

11. DRAM range-0 or range-1 set by MR12 OP[6]. 12. Time from MRW command to increment or decrement more than one step size up to a
full range of VREF voltage within the same VREF(CA) range. 13. Applies when VRCG high current mode is not enabled, specified by MR13 [OP3] = 0b. 14. tVREF_time_weak covers all VREF(CA) range and value change conditions are applied to
tVREF_TIME-SHORT/MIDDLE/LONG.
Internal VREF(DQ) Specifications
The device's internal VREF(DQ) specification parameters are operating voltage range, step size, VREF step tolerance, VREF step time and VREF valid level.
The voltage operating range specifies the minimum required VREF setting range for LPDDR4 devices. The minimum range is defined by V REF,max and VREF,min.

Table 257: Internal VREF(DQ) Specifications

Symbol VREF(DQ),max_r0
VREF(DQ),min_r0
VREF(DQ),max_r1
VREF(DQ),min_r1
VREF(DQ),step VREF(DQ),set_tol

Parameter
VREF MAX operating point Range-0
VREF MIN operating point Range-0
VREF MAX operating point Range-1
VREF MIN operating point Range-1
VREF(DQ) step size VREF(DQ) set tolerance

tVREF_TIME-SHORT tVREF_TIME-MIDDLE tVREF_TIME-LONG
tVREF_time_weak
VREF(DQ),val_tol

VREF(DQ) step time VREF(DQ) valid tolerance

Min ­
10%
­
22%
0.30% ­1.00% ­0.10%
­ ­ ­ ­ ­0.10%

Typ ­
­
­
­
0.40% 0.00% 0.00%
­ ­ ­ ­ 0.00%

Max 30%
­
42%
­
0.50% 1.00% 0.10%
100 200 250
1 0.10%

Unit VDDQ
VDDQ
VDDQ
VDDQ
VDDQ VDDQ VDDQ
ns ns ns ms VDDQ

Notes 1, 11
1, 11
1, 11
1, 11
2 3, 4, 6 3, 5, 7
8 12 9 13, 14 10

Notes:

1. VREF(DQ) DC voltage referenced to VDDQ(DC). 2. VREF(DQ) step size increment/decrement range. VREF(DQ) at DC level. 3. VREF(DQ),new = VREF(DQ),old + n × VREF(DQ),step; n = number of steps; if increment, use "+"; if
decrement, use "­".
4. The minimum value of VREF(DQ) setting tolerance = VREF(DQ),new - 1.0% × VDDQ. The maximum value of VREF(DQ) setting tolerance = VREF(DQ),new + 1.0% × VDDQ. For n > 4.
5. The minimum value of VREF(DQ)setting tolerance = VREF(DQ),new - 0.10% × VDDQ. The maximum value of VREF(DQ) setting tolerance = VREF(DQ),new + 0.10% × VDDQ. For n < 4.
6. Measured by recording the minimum and maximum values of the VREF(DQ) output over the range, drawing a straight line between those points and comparing all other VREF(DQ) output settings to that line.
7. Measured by recording the minimum and maximum values of the VREF(DQ) output across four consecutive steps (n = 4), drawing a straight line between those points and comparing all other VREF(DQ) output settings to that line.
8. Time from MRW command to increment or decrement one step size for VREF(DQ) .

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

385

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 1.10V VDDQ
9. Time from MRW command to increment or decrement VREF,min to VREF,max or VREF,max to VREF,min change across the VREF(DQ) Range in VREF(DQ) Voltage.
10. Only applicable for DRAM component level test/characterization purposes. Not applicable for normal mode of operation. VREF valid is to qualify the step times which will be characterized at the component level.
11. DRAM range-0 or range-1 set by MR14 OP[6]. 12. Time from MRW command to increment or decrement more than one step size up to a
full range of VREF voltage within the same VREF(DQ) range. 13. Applies when VRCG high current mode is not enabled, specified by MR13 [OP3] = 0. 14. tVREF_time_weak covers all VREF(DQ) Range and Value change conditions are applied to
tVREF_TIME-SHOR/MIDDLE/LONG.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

386

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 1.10V VDDQ
Command Definitions and Timing Diagrams - LPDDR4
Pull Up/Pull Down Driver Characteristics and Calibration

Table 258: Pull-Down Driver Characteristics ­ ZQ Calibration

RONPD,nom 40 ohms 48 ohms 60 ohms 80 ohms 120 ohms 240 ohms

Register
RON40PD RON48PD RON60PD RON80PD RON120PD RON240PD

Min 0.90 0.90 0.90 0.90 0.90 0.90

Nom 1.0 1.0 1.0 1.0 1.0 1.0

Max 1.10 1.10 1.10 1.10 1.10 1.10

Unit
RZQ/6 RZQ/5 RZQ/4 RZQ/3 RZQ/2 RZQ/1

Note: 1. All value are after ZQ calibration. Without ZQ calibration, RONPD values are ±30%.

Table 259: Pull-Up Characteristics ­ ZQ Calibration

VOHPU,nom VDDQ/2.5 VDDQ/3

VOH,nom 440 367

Min 0.90 0.90

Nom 1.0 1.0

Max 1.10 1.10

Unit VOH,nom VOH,nom

Notes: 1. All value are after ZQ calibration. Without ZQ calibration, RONPD values are ±30%. 2. VOH,nom (mV) values are based on a nominal VDDQ = 1.1V.

Table 260: Terminated Valid Calibration Points

VOHPU VDDQ/2.5 VDDQ/3

240 Valid Valid

120 Valid Valid

ODT Value

80

60

Valid

DNU

Valid

Valid

48 DNU Valid

40 DNU Valid

Notes:

1. Once the output is calibrated for a given VOH(nom) calibration point, the ODT value may be changed without recalibration.
2. If the VOH(nom) calibration point is changed, then recalibration is required. 3. DNU = Do not use.

On-Die Termination for the Command/Address Bus
The on-die termination (ODT) feature allows the device to turn on/off termination resistance for CK_t, CK_c, CS, and CA[5:0] signals without the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to turn on and off termination resistance for any target DRAM devices via the mode register setting.
A simple functional representation of the DRAM ODT feature is shown below.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

387

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

Figure 252: ODT for CA

RTT =

VOUT |IOUT|

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 1.10V VDDQ

VDD2

To other circuitry like RCV, ...

ODT RTT

IOUT

CA VOUT

VSS

ODT Mode Register and ODT State Table
ODT termination values are set and enabled via MR11. The CA bus (CK_t, CK_c, CS, CA[5:0]) ODT resistance values are set by MR11 OP[6:4]. The default state for the CA is ODT disabled.
ODT is applied on the CA bus to the CK_t, CK_c, CS, and CA signals. The CA ODT of the device is designed to enable one rank to terminate the entire command bus in a multirank system, so only one termination load will be present even if multiple devices are sharing the command signals. For this reason, CA ODT remains on, even when the device is in the power-down or self refresh power-down state.
The die has a bond pad (ODT_CA) for multirank operations. When the ODT_CA pad is LOW, the die will not terminate the CA bus regardless of the state of the mode register CA ODT bits (MR11 OP[6:4]). If, however, the ODT_CA bond pad is HIGH and the mode register CA ODT bits are enabled, the die will terminate the CA bus with the ODT values found in MR11 OP[6:4]. In a multirank system, the terminating rank should be trained first, followed by the non-terminating rank(s).

Table 261: Command Bus ODT State

CA ODT MR11[6:4] Disabled1
Valid 3 Valid 3 Valid 3 Valid 3 Valid 3

ODT_CA Bond Pad
Valid2 0 0 0 0 1

ODTD-CA MR22 OP[5]
Valid3 Valid3 Valid3 Valid3 Valid3
0

ODTE-CK MR22 OP[3]
Valid3 0 0 1 1
Valid3

ODTE-CS MR22 OP[4]
Valid3 0 1 0 1
Valid3

ODT State for CA Off Off Off Off Off On

ODT State for CK Off Off Off On On On

ODT State for CS Off Off On Off On On

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

388

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 1.10V VDDQ

Table 261: Command Bus ODT State (Continued)

CA ODT MR11[6:4]
Valid 3

ODT_CA Bond Pad
1

ODTD-CA MR22 OP[5]
1

ODTE-CK MR22 OP[3]
Valid3

ODTE-CS MR22 OP[4]
Valid3

ODT State for CA
Off

ODT State for CK
On

ODT State for CS
On

Notes:

1. Default value.
2. Valid = H or L (a defined logic level)
3. Valid = 0 or 1.
4. The state of ODT_CA is not changed when the device enters power-down mode. This maintains termination for alternate ranks in multirank systems.

ODT Mode Register and ODT Characteristics

Table 262: ODT DC Electrical Characteristics for Command/Address Bus ­ up to 3200 Mb/s

RZQ = 240 ±1% over entire operating range after calibration

MR11 OP[6:4]

RTT

VOUT

001b

240

VOL(DC) = 0.1 × VDD2

VOM(DC) = 0.33 × VDD2

VOH(DC) = 0.5 × VDD2

010b

120

VOL(DC) = 0.1 × VDD2

VOM(DC) = 0.33 × VDD2

VOH(DC) = 0.5 × VDD2

011b

80

VOL(DC) = 0.1 × VDD2

VOM(DC) = 0.33 × VDD2

VOH(DC) = 0.5 × VDD2

100b

60

VOL(DC) = 0.1 × VDD2

V OM(DC) = 0.33 × VDD2

VOH(DC) = 0.5 × VDD2

101b

48

VOL(DC) = 0.1 × VDD2

VOM(DC) = 0.33 × VDD2

VOH(DC) = 0.5 × VDD2

110b

40

VOL(DC) = 0.1 × VDD2

VOM(DC) = 0.33 × VDD2

VOH(DC) = 0.5 × VDD2

Mismatch, CA -CA within clock group

0.33 × VDD2

Min 0.8 0.9 0.9 0.8 0.9 0.9 0.8 0.9 0.9 0.8 0.9 0.9 0.8 0.9 0.9 0.8 0.9 0.9 ­

Nom 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 ­

Max 1.1 1.1 1.2 1.1 1.1 1.2 1.1 1.1 1.2 1.1 1.1 1.2 1.1 1.1 1.2 1.1 1.1 1.2 2

Unit RZQ/1 RZQ/2 RZQ/3 RZQ/4 RZQ/5 RZQ/6
%

Notes 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2
1, 2, 3

Notes:

1. The tolerance limits are specified after calibration with stable temperature and voltage. To understand the behavior of the tolerance limits when voltage or temperature changes after calibration, see the section on voltage and temperature sensitivity.
2. Pull-down ODT resistors are recommended to be calibrated at 0.33 × VDD2. Other calibration points may be required to achieve the linearity specification shown above, for example, calibration at 0.5 × VDD2 and 0.1 × VDD2.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

389

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 1.10V VDDQ

3. CA to CA mismatch within clock group variation for a given component including CK_t, CK_c ,and CS (characterized).
CA-to-CA mismatch = RODT (MAX) - RODT (MIN) RODT (AVG)

Table 263: ODT DC Electrical Characteristics for Command/Address Bus ­ Beyond 3200 Mb/s

RZQ = 240 ±1% over entire operating range after calibration

MR11 OP[6:4]

RTT

VOUT

001b

240

VOL(DC) = 0.1 × VDD2

VOM(DC) = 0.33 × VDD2

VOH(DC) = 0.5 × VDD2

010b

120

VOL(DC) = 0.1 × VDD2

VOM(DC) = 0.33 × VDD2

VOH(DC) = 0.5 × VDD2

011b

80

VOL(DC) = 0.1 × VDD2

VOM(DC) = 0.33 × VDD2

VOH(DC) = 0.5 × VDD2

100b

60

VOL(DC) = 0.1 × VDD2

V OM(DC) = 0.33 × VDD2

VOH(DC) = 0.5 × VDD2

101b

48

VOL(DC) = 0.1 × VDD2

VOM(DC) = 0.33 × VDD2

VOH(DC) = 0.5 × VDD2

110b

40

VOL(DC) = 0.1 × VDD2

VOM(DC) = 0.33 × VDD2

VOH(DC) = 0.5 × VDD2

Mismatch, CA -CA within clock group

0.33 × VDD2

Min 0.8 0.9 0.9 0.8 0.9 0.9 0.8 0.9 0.9 0.8 0.9 0.9 0.8 0.9 0.9 0.8 0.9 0.9 ­

Nom 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 ­

Max 1.1 1.1 1.3 1.1 1.1 1.3 1.1 1.1 1.3 1.1 1.1 1.3 1.1 1.1 1.3 1.1 1.1 1.3 2

Unit RZQ/1

Notes 1, 2

RZQ/2

1, 2

RZQ/3

1, 2

RZQ/4

1, 2

RZQ/5

1, 2

RZQ/6

1, 2

%

1, 2, 3

Notes:

1. The tolerance limits are specified after calibration with stable temperature and voltage. To understand the behavior of the tolerance limits when voltage or temperature changes after calibration, see the section on voltage and temperature sensitivity.
2. Pull-down ODT resistors are recommended to be calibrated at 0.33 × VDD2. Other calibration points may be required to achieve the linearity specification shown above, e.g. calibration at 0.5 × VDD2 and 0.1 × VDD2.
3. CA to CA mismatch within clock group variation for a given component including CK_t, CK_c ,and CS (characterized).

CA-to-CA mismatch = RODT (MAX) - RODT (MIN) RODT (AVG)

DQ On-Die Termination
On-die termination (ODT) is a feature that allows the device to turn on/off termination resistance for each DQ, DQS, and DMI signal without the ODT control pin. The ODT

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

390

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 1.10V VDDQ

feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to turn on and off termination resistance for any target DRAM devices during WRITE or MASK WRITE operation.
The ODT feature is off and cannot be supported in power-down and self refresh modes.
The switch is enabled by the internal ODT control logic, which uses the WRITE-1 or MASK WRITE-1 command and other mode register control information. The value of RTT is determined by the MR bits.

RTT =

VOUT |IOUT|

Figure 253: Functional Representation of DQ ODT

To other circuitry like RCV, ...

VDDQ

ODT RTT

IOUT

DQ VOUT

VSSQ

Table 264: ODT DC Electrical Characteristics for DQ Bus­ up to 3200 Mb/s

RZQ = 240 ±1% over entire operating range after calibration

MR11 OP[2:0]

RTT

VOUT

001b

240

VOL(DC) = 0.1 × VDDQ

VOM(DC) = 0.33 × VDDQ

VOH(DC) = 0.5 × VDDQ

010b

120

VOL(DC) = 0.1 × VDDQ

VOM(DC) = 0.33 × VDDQ

VOH(DC) = 0.5 × VDDQ

011b

80

VOL(DC) = 0.1 × VDDQ

VOM(DC) = 0.33 × VDDQ

VOH(DC) = 0.5 × VDDQ

100b

60

VOL(DC) = 0.1 × VDDQ

V OM(DC) = 0.33 × VDDQ

VOH(DC) = 0.5 × VDDQ

Min 0.8 0.9 0.9 0.8 0.9 0.9 0.8 0.9 0.9 0.8 0.9 0.9

Nom 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0

Max 1.1 1.1 1.2 1.1 1.1 1.2 1.1 1.1 1.2 1.1 1.1 1.2

Unit RZQ/1

Notes 1, 2

RZQ/2

1, 2

RZQ/3

1, 2

RZQ/4

1, 2

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

391

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 1.10V VDDQ

Table 264: ODT DC Electrical Characteristics for DQ Bus­ up to 3200 Mb/s (Continued)

RZQ = 240 ±1% over entire operating range after calibration

MR11 OP[2:0]

RTT

VOUT

101b

48

VOL(DC) = 0.1 × VDDQ

VOM(DC) = 0.33 × VDDQ

VOH(DC) = 0.5 × VDDQ

110b

40

VOL(DC) = 0.1 × VDDQ

VOM(DC) = 0.33 × VDDQ

VOH(DC) = 0.5 × VDDQ

Mismatch error, DQ-to-DQ within a channel

0.33 × VDDQ

Min 0.8 0.9 0.9 0.8 0.9 0.9 ­

Nom 1.0 1.0 1.0 1.0 1.0 1.0 ­

Max 1.1 1.1 1.2 1.1 1.1 1.2 2

Unit RZQ/5
RZQ/6
%

Notes 1, 2
1, 2
1, 2, 3

Notes:

1. The ODT tolerance limits are specified after calibration with stable temperature and voltage. To understand the behavior of the tolerance limits when voltage or temperature changes after calibration, see the following section on voltage and temperature sensitivity.
2. Pull-down ODT resistors are recommended to be calibrated at 0.33 × VDDQ. Other calibration points may be required to achieve the linearity specification shown above, (for example, calibration at 0.5 × VDDQ and ­0.1 × VDDQ.
3. DQ-to-DQ mismatch within byte variation for a given component, including DQS (characterized).

DQ-to-DQ mismatch= RODT (MAX) - RODT (MIN) RODT (AVG)

Table 265: ODT DC Electrical Characteristics for DQ Bus ­ Beyond 3200 Mb/s

RZQ = 240 ±1% over entire operating range after calibration

MR11 OP[2:0]

RTT

VOUT

001b

240

VOL(DC) = 0.1 × VDDQ

VOM(DC) = 0.33 × VDDQ

VOH(DC) = 0.5 × VDDQ

010b

120

VOL(DC) = 0.1 × VDDQ

VOM(DC) = 0.33 × VDDQ

VOH(DC) = 0.5 × VDDQ

011b

80

VOL(DC) = 0.1 × VDDQ

VOM(DC) = 0.33 × VDDQ

VOH(DC) = 0.5 × VDDQ

100b

60

VOL(DC) = 0.1 × VDDQ

V OM(DC) = 0.33 × VDDQ

VOH(DC) = 0.5 × VDDQ

101b

48

VOL(DC) = 0.1 × VDDQ

VOM(DC) = 0.33 × VDDQ

VOH(DC) = 0.5 × VDDQ

Min 0.8 0.9 0.9 0.8 0.9 0.9 0.8 0.9 0.9 0.8 0.9 0.9 0.8 0.9 0.9

Nom 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0

Max 1.1 1.1 1.3 1.1 1.1 1.3 1.1 1.1 1.3 1.1 1.1 1.3 1.1 1.1 1.3

Unit RZQ/1

Notes 1, 2

RZQ/2

1, 2

RZQ/3

1, 2

RZQ/4

1, 2

RZQ/5

1, 2

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

392

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 1.10V VDDQ

Table 265: ODT DC Electrical Characteristics for DQ Bus ­ Beyond 3200 Mb/s (Continued)

RZQ = 240 ±1% over entire operating range after calibration

MR11 OP[2:0]

RTT

VOUT

110b

40

VOL(DC) = 0.1 × VDDQ

VOM(DC) = 0.33 × VDDQ

VOH(DC) = 0.5 × VDDQ

Mismatch error, DQ-to-DQ within a channel

0.33 × VDDQ

Min 0.8 0.9 0.9 ­

Nom 1.0 1.0 1.0 ­

Max 1.1 1.1 1.3 2

Unit RZQ/6
%

Notes 1, 2
1, 2, 3

Notes:

1. The ODT tolerance limits are specified after calibration with stable temperature and voltage. To understand the behavior of the tolerance limits when voltage or temperature changes after calibration, see the following section on voltage and temperature sensitivity.
2. Pull-down ODT resistors are recommended to be calibrated at 0.33 × VDDQ. Other calibration points may be required to achieve the linearity specification shown above, for example, calibration at 0.5 × VDDQ and ­0.1 × VDDQ.
3. DQ-to-DQ mismatch within byte variation for a given component, including DQS (characterized).

DQ-to-DQ mismatch= RODT (MAX) - RODT (MIN) RODT (AVG)

Output Driver and Termination Register Temperature and Voltage Sensitivity
When temperature and/or voltage change after calibration, the tolerance limits are widen according to the tables below.

Table 266: Output Driver and Termination Register Sensitivity Definition

Resistor
RONPD VOHPU RTT(I/O) RTT(IN)

Definition Point
0.33 × VDDQ 0.33 × VDDQ 0.33 × VDDQ 0.33 × VDD2

Min
90 - (dRONdT × |T|) - (dRONdV × |V|) 90 - (dVOHdT × |T|) - (dVOHdV × |V|) 90 - (dRONdT × |T|) - (dRONdV × |V|) 90 - (dRONdT × |T|) - (dRONdV× |V|)

Max
110 + (dRONdT × |T|) + (dRONdV × |V|) 110 + (dVOHdT × |T|) + (dVOHdV × |V|) 110 + (dRONdT × |T|) + (dRONdV × |V|) 110 + (dRONdT × |T|) + (dRONdV × |V|)

Unit %

Notes 1, 2
1, 2, 5 1, 2, 3 1, 2, 4

Notes:

1. T = T - T(@calibration), V = V - V(@calibration) 2. dRONdT, dRONdV, dVOHdT, dVOHdV, dRTTdV, and dRTTdT are not subject to production test
but are verified by design and characterization. 3. This parameter applies to input/output pin such as DQS, DQ, and DMI. 4. This parameter applies to input pin such as CK, CA, and CS. 5. Refer to Pull-up/Pull-down Driver Characteristics for VOHPU.

Table 267: Output Driver and Termination Register Temperature and Voltage Sensitivity

Symbol dRONdT dRONdV

Parameter RON temperature sensitivity RON voltage sensitivity

Min 0 0

Max 0.75 0.20

Unit %/°C %/mV

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

393

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 1.10V VDDQ

Table 267: Output Driver and Termination Register Temperature and Voltage Sensitivity (Continued)

Symbol
dVOHdT dVOHdV dRTTdT dRTTdV

Parameter
VOH temperature sensitivity VOH voltage sensitivity RTT temperature sensitivity RTT voltage sensitivity

Min 0 0 0 0

Max 0.75 0.35 0.75 0.20

Unit %/°C %/mV %/°C %/mV

AC and DC Operating Conditions - LPDDR4

Recommended DC Operating Conditions
Operation or timing that is not specified is illegal. To ensure proper operation, the device must be initialized properly.

Table 268: Recommended DC Operating Conditions

Symbol

Min

Typ

Max

DRAM

Unit

Notes

VDD1 VDD2 VDDQ

1.7

1.8

1.95

Core 1 power

V

1, 2

1.06

1.1

1.17

Core 2 power/Input buffer power

V

1, 2, 3

1.06

1.1

1.17

I/O buffer power

V

2, 3

Notes:

1. VDD1 uses significantly less power than VDD2. 2. The voltage range is for DC voltage only. DC voltage is the voltage supplied at the
DRAM and is inclusive of all noise up to 20 MHz at the DRAM package ball.
3. The voltage noise tolerance from DC to 20 MHz exceeding a peak-to-peak tolerance of 45mV at the DRAM ball is not included in the TdIVW.

Output Slew Rate and Overshoot/Undershoot specifications - LPDDR4
Single-Ended Output Slew Rate

Table 269: Single-Ended Output Slew Rate Note 1-5 applies to entire table
Parameter Single-ended output slew rate (VOH = VDDQ/3) Output slew rate matching ratio (rise to fall)

Symbol SRQse ­

Min 3.5 0.8

Value

Max 9.0 1.2

Units V/ns
­

Notes:

1. SR = Slew rate; Q = Query output; se = Single-ended signal
2. Measured with output reference load.
3. The ratio of pull-up to pull-down slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation.
4. The output slew rate for falling and rising edges is defined and measured between VOL(AC) = 0.2 × VOH(DC) and VOH(AC) = 0.8 × VOH(DC).

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

394

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 1.10V VDDQ
5. Slew rates are measured under average SSO conditions with 50% of the DQ signals per data byte switching.
Figure 254: Single-Ended Output Slew Rate Definition
TRSE

Single-Ended Output Voltage (DQ)

VOH(AC) VCENT VOL(AC)

TFSE

Time

Differential Output Slew Rate

Table 270: Differential Output Slew Rate Note 1-4 applies to entire table
Parameter Differential output slew rate (VOH = VDDQ/3)

Symbol SRQdiff

Min 7

Value

Max 18

Units V/ns

Notes:

1. SR = Slew rate; Q = Query output; se = Differential signal
2. Measured with output reference load.
3. The output slew rate for falling and rising edges is defined and measured between VOL(AC) = ­0.8 × VOH(DC) and VOH(AC) = 0.8 × VOH(DC).
4. Slew rates are measured under average SSO conditions with 50% of the DQ signals per data byte switching.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

395

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 1.10V VDDQ
Figure 255: Differential Output Slew Rate Definition
TRdiff

Differential Output Voltage (DQ)

0

TFdiff

Time

LVSTL I/O System - LPDDR4
LVSTL I/O cells are comprised of a driver pull-up and pull-down and a terminator. Figure 256: LVSTL I/O Cell
VDDQ

Pull-Up Pull-Down

DQ
ODT Enabled when receiving

VSSQ

VSSQ

To ensure that the target impedance is achieved, calibrate the LVSTL I/O cell as following example:

1. Calibrate the pull-down device against a 240 ohm resistor to VDDQ via the ZQ pin.
· Set strength control to minimum setting · Increase drive strength until comparator detects data bit is less than VDDQ/3 · NMOS pull-down device is calibrated to 120 ohms
2. Calibrate the pull-up device against the calibrated pull-down device.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

396

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP LPDDR4 1.10V VDDQ
· Set VOH target and NMOS controller ODT replica via MRS (VOH can be automatically controlled by ODT MRS)
· Set strength control to minimum setting · Increase drive strength until comparator detects data bit is greater than VOH target · NMOS pull-up device is calibrated to VOH target Figure 257: Pull-Up Calibration
VDDQ

Strength contol [N-1:0] N

Comparator

VOH target

Calibrated NMOS PD control + ODT information

Controller ODT replica could be 60 ohms, 120 ohms, ... via MRS setting
VSSQ

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

397

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary

149-Ball NAND Flash with LPDDR4/LPDDR4X MCP Revision History

Revision History

Rev. A ­ 3/2020

· Initial release.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000 www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.

CCM005-284460984-10509 149ball_nand_lpddr4_lpddr4x_j87j.pdf ­ Rev. A 3/2020 EN

398

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2020 Micron Technology, Inc. All rights reserved.

Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Micron Technology:
MT29GZ5A5BPGGA-53AAT.87J MT29GZ5A5BPGGA-53AIT.87J MT29GZ5A5BPGGA-046AAT.87J MT29GZ5A5BPGGA-046AIT.87J