User Manual for ON Semiconductor models including: EVBUM2184DB, NB7L14MNGEVB, NB7L14MNG Evaluation Board, NB7L14MNG, Evaluation Board, Board
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DocumentDocumentNB7L14MNGEVB NB7L14MNG Evaluation Board User's Manual Introduction ON Semiconductor has developed the QFN16EVB evaluation board for its high-performance devices packaged in the 16-pin QFN. This evaluation board was designed to provide a flexible and convenient platform to quickly evaluate, characterize and verify the operation of various ON Semiconductor products. Many QFN16EVBs are dedicated with a device already installed, and can be ordered from www.onsemi.com at the specific device web page. This evaluation board manual contains: · Information on 16-lead QFN Evaluation Board · Assembly Instructions · Appropriate Lab Setup · Bill of Materials This user's manual provides detailed information on board contents, layout and its use. It should be used in conjunction with an appropriate ON Semiconductor device datasheet located at www.onsemi.com. The datasheet contains the technical device specifications. http://onsemi.com EVAL BOARD USER'S MANUAL Board Layout The QFN16 Evaluation Board provides a high bandwidth, 50 W controlled impedance environment and is implemented in four layers. The first layer or primary trace layer is 0.008 thick Rogers RO4003 material, and is designed to have equal electrical length on all signal traces from the device under test (DUT) pins to the SMA connectors. The second layer is the 1.0 oz copper ground plane and is primarily dedicated for the SMA connector ground plane. FR4 dielectric material is placed between the second and third layers and between third and fourth layers. The third layer is also 1.0 oz copper plane. A portion of this layer is designated for the device VCC and DUTGND power planes. The fourth layer is the secondary trace layer. Top View Bottom View Figure 1. Top and Bottom View of the 16 QFN Evaluation Board © Semiconductor Components Industries, LLC, 2013 1 May, 2013 - Rev. 0 Downloaded from Arrow.com. Publication Order Number: EVBUM2184/D NB7L14MNGEVB Figure 2. Enlarged Bottom View Pin 13 Pin 14 Pin 15 Pin 16 Pin 12 Pin 11 Pin 10 Pin 9 VEE/DUTGND VCC SMA_GND DUT_GND SMA_GND Pin 1 Pin 2 Pin 3 Pin 4 Pin 8 Pin 7 Pin 6 Pin 5 Downloaded from Arrow.com. Figure 3. Enlarged Bottom View of the Evaluation Board SILKSCREEN (TOP SIDE) LAYER 1 (TOP SIDE) 1 OZ ROGERS 4003 0.008 in LAYER 2 (GROUND PLANE P1) 1 OZ FR-4 0.020 in LAYER 3 (GROUND, VCC & VEE, PLANE P2) 1 OZ FR-4 0.025 in LAYER 4 (BOTTOM SIDE) 1 OZ Figure 4. Evaluation Board Layout, 4 Layer 0.062 ± 0.007 http://onsemi.com 2 NB7L14MNGEVB Top View Figure 5. Evaluation Board Layout Bottom View Evaluation Board Assembly Instructions The QFN-16 evaluation board is designed for characterizing devices in a 50 W laboratory environment using high bandwidth equipment. Each signal trace on the board has a via at the DUT pin, which provides an option of placing a termination resistor on the board bottom, depending on the input/output configuration (see Table 1, Configuration for Device: NB7L14). Table 4 contains the Bill of Materials for this evaluation board. The QFN16EVB was designed to accommodate a custom QFN-16 socket. Therefore, some external components are installed on the bottom side of the board. Solder the Device on the Evaluation Board The soldering of a device to the evaluation board can be accomplished by hand soldering or solder reflow techniques using solder paste. Make sure pin 1 of the device is located properly and all the pins are aligned to the footprint pads. Solder the QFN-16 device to the evaluation board. As mentioned earlier, many QFN16EVBs are dedicated with a device already installed, and can be ordered from onsemi.com at the specific device web page. Connecting Power and Ground On the top side of the evaluation board, solder the four surface mount test point clips (anvils) to the pads labeled VCC, VEE/DUTGND, SMAGND, and ExPad. ExPad is connected to the exposed flag of the QFN package. For proper operation, the exposed flag is typically recommended to be tied to VEE/DUTGND, the negative supply of the device. The positive power supply connector is labeled VCC. Depending on the device, the negative power supply nomenclature is labeled either GND or VEE. To help avoid confusion with the use of this board, the negative supply connector is labeled VEE/DUTGND. SMAGND is the ground for the SMA connectors and is not to be confused with the device ground, VEE/DUTGND. SMAGND and DUTGND can be connected in single-supply applications. The power pin layout and typical connection of the evaluation board is shown in Figure 6. It is recommended to add bypass capacitors to reduce unwanted noise from the power supplies. Connect 0.1 mF capacitors from VCC and VEE/DUTGND to SMA_GND. Output Loading/Termination ECL/PECL/LVPECL Outputs Most ECL outputs are open emitter and need to be DC loaded and AC terminated to VCC - 2.0 V via a 50 W resistor. If no internal resistors are provided on the device, 0402 chip resistor pads are provided on the bottom side of the evaluation board to terminate the ECL driver. Solder the chip resistors to the bottom side of the board between the appropriate input device pads and the ground pads. If internal resistors are provided, the VT pins should be wired to SMAGND. (More information on termination is provided in AND8020). For standard ECL lab setup and test, a split (dual) power supply is recommended enabling the 50 W internal impedance in the oscilloscope, or other measuring instrument, to be used as an ECL output load/termination. By offsetting VCC = +2.0 V, SMAGND = VCC - 2.0 V, (SMAGND is the system ground, 0V); VCC is 2.0 V, and VEE/DUTGND is -3.0 V, -1.3 V or -0.5 V; see Table 2, Power Supply Levels). Downloaded from Arrow.com. http://onsemi.com 3 NB7L14MNGEVB CML Outputs Likewise, CML outputs need to be terminated to VCC via a 50 W resistor. If no internal resistors are provided on the device, 0402 chip resistor pads are provided on the bottom side of the evaluation board to terminate the CML driver. If internal resistors are provided, the VT pins should be wired to VCC. For CML lab setup and test, operation with negative supply voltages is recommended to enable the 50 W internal impedance in the oscilloscope, or other measuring instrument, to be used as a CML output termination; (VCC = 0 V, SMAGND = 0 V, and VEE/DUTGND = -5.0 V, -3.3 V, -2.5 V, or -1.8 V). LVDS Outputs LVDS outputs are typically terminated with 100 W across the Q/Q output pair. The 100 W can be added on the QFN16EVB, but it is not provided on the board, since there are several user dependent LVDS output measurement techniques. For LVDS lab setup and test, a single supply is typically used, ie. VCC = 3.3 V and DUTGND = 0 V. Installing the SMA Connectors Each configuration indicates the number of SMA connectors needed to populate an evaluation board for a given device. Each input and output requires one SMA connector. Install all the required SMA connectors onto the board and solder the center signal conductor pin to the board on J1 through J16. Please note that the alignment of the signal connector pin of the SMA connector to the metal trace on the board can influence lab results. The launch and reflection of the signals are largely influenced by imperfect alignment and soldering of the SMA connector. Validating the Assembled Board After assembling the evaluation board, it is recommended to perform continuity checks on all soldered areas before commencing with the evaluation process. Time Domain Reflectometry (TDR) is another highly recommended validation test. Downloaded from Arrow.com. http://onsemi.com 4 NB7L14MNGEVB NB7L14MNGEVB ASSEMBLY Table 1. CONFIGURATION FOR DEVICE: NB7L14 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 Device Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SMA Connector Yes Yes Yes Yes No Yes Yes No Yes Yes Yes Yes No Yes Yes No Wire No No No No GND No No VCC No No No No VCC No No GND NOTE: DUTGND/VEE = Exposed Pad and must be tied to DUTGND/VEE. CONFIGURATIONS VEE/DUTGND VCC SMAGND 13 14 15 16 12 1 11 ExPad 2 10 3 9 4 8 7 6 5 SMAGND J15 J16 J1 VCC J2 J3 Exposed Pad J4 J5 J6 J14 J13 J12 DUTGND/VEE J11 DUT J10 SMAGND J9 J8 J7 Top View Polarity of 22 mF: + C4 - + C2 - Bottom View Install 0.1 mF Decoupling Capacitors here and at package pins Figure 6. Power Supply Configuration for Device NB7L14 Downloaded from Arrow.com. http://onsemi.com 5 Differential Signal Generator Out Out NB7L14MNGEVB NB7L14MNGEVB TEST Power Supply VCC VEE/DUTGND VCC DUTGND/ DUT VEE ExPad SMAGND Test Measuring Equipment Channel 1 Channel 2 Trigger Trigger VEE/ DUTGND GND (0 V) Power Supply 1. Connect appropriate power supplies to VCC, VEE/DUTGND, SMAGND, and ExPad (see Table 2). 2. Connect a signal generator to the input SMA connectors. Setup input signal according to the device data sheet. 3. Connect a test measurement device to the device's output SMA connectors. NOTE: The test measurement device must contain 50 W termination. Figure 7. Basic Lab Setup (Typical) Table 2. POWER SUPPLY LEVELS Outputs Power Supply ECL/LVPECL 2.5 V ECL/LVPECL 3.3 V VCC +2.0 V +2.0 V VEE/DUTGND -0.5 V -1.3 V SMAGND 0 V 0 V ExPad (typ) VEE/DUTGND VEE/DUTGND Table 3. NB7xxx, LVPECL OUTPUTS "SPLIT" POWER SUPPLY CONFIGURATION Device Pin Power Supply Convertor "Spilt" Power Supply VCC SMAGND DUTGND VCC = +2.0 V VTT = 0 V DUTGND = -0.5 V or -1.3 V Dual Power Supplies +2.0 V +1.3 V + -+ - VCC DUTGND SMAGND Downloaded from Arrow.com. +3.3 V Offset / "Split" Power Supply Configuration Figure 8. "Split" or Dual Power Supply Connections http://onsemi.com 6 NB7L14MNGEVB Table 4. BILL OF MATERIALS Components SMA Connector Manufacturer Description Part Number Qty Rosenberger SMA Connector, Side 32K243-40ME3 12 Launch, Gold Plated Surface Mount Test Points Keystone* SMT Miniature Test 5015 4 Point Chip Capacitor AVC Corporation* 0603 0.01 mF ±10% 06035C103KAT2A na Chip Resistor Panasonic* 0603 0.1 mF ±10% 0603C104KAT2A 8 0402 50 W ±1% ERJ-2RKF49R9X na Precision Thick Film Chip Resistor Evaluation Board ON Semiconductor QFN 16 Evaluation QFN16EVB 1 Board Device Samples ON Semiconductor QFN 16 Package Device NB7L14MNG 1 *Components are available through most distributors, i.e. www.newark.com, www.digikey.com Web Site http://www.rosenberger.de http://www.rosenbergerna.com http://www.keyelco.com http://www.avxcorp.com http://www.panasonic.com http://www.onsemi.com http://www.onsemi.com Downloaded from Arrow.com. http://onsemi.com 7 NB7L14MNGEVB Top Layer Downloaded from Arrow.com. Second Layer (SMA_GND Plane) Figure 9. Gerber Files http://onsemi.com 8 NB7L14MNGEVB Third Layer (DUT_GND Trace) Downloaded from Arrow.com. Bottom Layer Figure 10. Gerber Files http://onsemi.com 9 onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba "onsemi" or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. The evaluation board/kit (research and development board/kit) (hereinafter the "board") is not a finished product and is not available for sale to consumers. The board is only intended for research, development, demonstration and evaluation purposes and will only be used in laboratory/development areas by persons with an engineering/technical training and familiar with the risks associated with handling electrical/mechanical components, systems and subsystems. This person assumes full responsibility/liability for proper and safe handling. Any other use, resale or redistribution for any other purpose is strictly prohibited. THE BOARD IS PROVIDED BY ONSEMI TO YOU "AS IS" AND WITHOUT ANY REPRESENTATIONS OR WARRANTIES WHATSOEVER. WITHOUT LIMITING THE FOREGOING, ONSEMI (AND ITS LICENSORS/SUPPLIERS) HEREBY DISCLAIMS ANY AND ALL REPRESENTATIONS AND WARRANTIES IN RELATION TO THE BOARD, ANY MODIFICATIONS, OR THIS AGREEMENT, WHETHER EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, INCLUDING WITHOUT LIMITATION ANY AND ALL REPRESENTATIONS AND WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, NON-INFRINGEMENT, AND THOSE ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE CUSTOM OR TRADE PRACTICE. onsemi reserves the right to make changes without further notice to any board. You are responsible for determining whether the board will be suitable for your intended use or application or will achieve your intended results. Prior to using or distributing any systems that have been evaluated, designed or tested using the board, you agree to test and validate your design to confirm the functionality for your application. Any technical, applications or design information or advice, quality characterization, reliability data or other services provided by onsemi shall not constitute any representation or warranty by onsemi, and no additional obligations or liabilities shall arise from onsemi having provided such information or services. onsemi products including the boards are not designed, intended, or authorized for use in life support systems, or any FDA Class 3 medical devices or medical devices with a similar or equivalent classification in a foreign jurisdiction, or any devices intended for implantation in the human body. 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FCC WARNING This evaluation board/kit is intended for use for engineering development, demonstration, or evaluation purposes only and is not considered by onsemi to be a finished end product fit for general consumer use. It may generate, use, or radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment may cause interference with radio communications, in which case the user shall be responsible, at its expense, to take whatever measures may be required to correct this interference. onsemi does not convey any license under its patent rights nor the rights of others. LIMITATIONS OF LIABILITY: onsemi shall not be liable for any special, consequential, incidental, indirect or punitive damages, including, but not limited to the costs of requalification, delay, loss of profits or goodwill, arising out of or in connection with the board, even if onsemi is advised of the possibility of such damages. In no event shall onsemi's aggregate liability from any obligation arising out of or in connection with the board, under any theory of liability, exceed the purchase price paid for the board, if any. The board is provided to you subject to the license and other terms per onsemi's standard terms and conditions of sale. For more information and documentation, please visit www.onsemi.com. ADDITIONAL INFORMATION TECHNICAL PUBLICATIONS: Technical Library: www.onsemi.com/design/resources/technical-documentation onsemi Website: www.onsemi.com ONLINE SUPPORT: www.onsemi.com/support For additional information, please contact your local Sales Representative at www.onsemi.com/support/sales Downloaded from Arrow.com. www.onsemi.com 1
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