US Patent: Method and Apparatus for Thread Execution with History Buffer

Overview

This document details a United States Patent (US 10,282,205 B2) awarded to International Business Machines Corporation.

The patent covers a method and apparatus designed to enhance the execution of threads within processing slices of a computer system. A key focus is the use of a history buffer to manage and restore architected register data efficiently, particularly during instruction execution and in response to system interruptions.

Key Concepts

• Methodology: Focuses on marking history buffer entries for restoration, sending data and control information to an Issue Queue (ISQ), issuing instructions for register file loading, and performing write-back operations.
• Architecture: Explores multi-slice processor designs where each slice includes a history buffer and a portion of a register file.
• Restoration Process: Details how result data and control information are managed to ensure data integrity and proper state recovery, especially in scenarios involving speculative execution or rollbacks.

Inventors and Assignee

• Inventors: Susan E. Eisen, Cliff Kucharski, Hung Q. Le, Dung Q. Nguyen, David R. Terry
• Assignee: International Business Machines Corporation