OPTIGA™ Trust M Security Controller

Key Features

• High-end security controller
• Common Criteria Certified EAL6+ (high) hardware
• Turnkey solution
• Up to 10kB user memory
• PG-USON-10-2,-4 package (3 x 3 mm)
• Standard & Extended temperature ranges
• I2C interface with Shielded Connection (encrypted communication)
• Cryptographic support:
  • ECC: NIST curves up to P-521, Brainpool r1 curve up to 512
  • RSA® up to 2048
  • AES key up to 256, HMAC up to SHA512
  • TLS v1.2 PRF and HKDF up to SHA512
• OPTIGA™ Trust M Software Framework on Github - github.com/Infineon/optiga-trust-m
• Crypto ToolBox commands for SHA-256, ECC and RSA® Feature, AES, HMAC and Key derivation
• Configurable device security monitor, 4 Monotonic up counters
• Protected (integrity and confidentiality) update of data, key and metadata objects
• Hibernate for zero power consumption¹
• Lifetime for Industrial Automation and Infrastructure is 20 years and 15 years for other Application Profiles

Benefits

• Protection of IP and data
• Protection of business case and corporate image
• Safeguarding of quality and safety

Applications

• Industrial control and building automation
• Consumer electronics and Smart Home
• Drones

About this document

Scope and purpose

This Datasheet provides information to enable integration of a security device, and includes package, connectivity and technical data.

Intended audience

This Datasheet is intended for device integrators and board manufacturers.

Product Variants

Table 1: Products for V1

Table 2: Products for V3

Infineon and its distribution partners offer a wide range of customization options (e.g. X.509 certificate generation and key provisioning) for the security chip. For details on offered solutions (like OPTIGA™ Trust M Express), selection guide and orders, please see the following page: www.infineon.com/cms/en/product/security-smart-card-solutions/optiga-embedded-security-solutions/optiga-trust/optiga-trust-m-sls32aia/

Technical Data Overview

Table 3: Features

System Block Diagram

The following figure depicts the system block diagram for OPTIGA™ Trust M.

The System Block Diagram is explained below for each layer.

1. Local Host

• Local Host Application – This is the target application which utilizes OPTIGA™ Trust M for its security needs.
• OPTIGA™ Trust M Host Library
  • CRYPT – Provides APIs to perform cryptographic functionalities. Any TLS stack can be integrated on Local Host as part of 3rd party Crypto Library to offload crypto operations to OPTIGA™ Trust M.
  • UTIL – Provides APIs such as read/write, protected update of data, metadata, key objects and open/close application (e.g. Hibernate).
  • CMD - Provides APIs to send and receive commands (Section 6) to and from OPTIGA™ Trust M.
  • COMMS – Provides wrapper APIs for communication (optional encrypted communication using Shielded Connection) with OPTIGA™ Trust M which internally uses Infineon I2C Protocol (IFX I2C).
  • PAL – A layer that abstracts platform specific drivers (e.g. I2C, Timer, GPIO, platform crypto library etc.).

2. OPTIGA™ Trust M

• Arbitrary Data Objects – The target application can store up to 4.5kB (~4600 bytes) of data into OPTIGA™ Trust M. The data could be additional Trust Anchors, certificates and shared secret.
• Monotonic Counters - Provides 4 monotonic counting data objects (up counters). These can be used as general purpose counter or as linked counter to other objects.
• X.509 – Up to 4 X.509 based Certificates can be stored.
• Keys - Up to 4 ECC, 2 RSA and 1 AES based keys can be stored.
• Secret - 1 Platform binding secret can be stored.
• Trust Anchors – 3 slots, for Mutual Authentication (TLS/DTLS) and Firmware Updates can be stored.
• Crypto Functions - OPTIGA™ Trust M provides cryptographic functions that can be invoked via local host.

Note: Unique AES key, ECC/RSA private keys and X.509 Certificates – During production at Infineon fab, unique asymmetric keys (private and public) are generated and symmetric key/shared secrets are provisioned. The public key is signed by customer specific CA and the resulting X.509 certificate issued is securely stored in the OPTIGA™ Trust M. Special measures are taken to prevent the leakage and modification of private key/shared secret material at the Common Criteria Certified production site.

Interface and Schematics

The following figure illustrates how to integrate OPTIGA™ Trust M with your local host.

Note: The OPTIGA™ Trust M can be integrated with IFX I2C reset option as soft reset (IFX_I2C_SOFT_RESET), or hardware reset. Value of the pullup resistors depend on the target application circuit and the target I2C frequency.

3.1 System Integration Schematics with Hibernation support

The following figure illustrates how to integrate OPTIGA™ Trust M with hibernation, with local host GPIO used as VCC.

Note: The Host GPIO pin must have sufficient current to drive the supply current, as per Table 11. Value of the pullup resistors depend on the target application circuit and the target I2C frequency.

If the host GPIO doesn't supply sufficient current to OPTIGA, additional MOSFET switching circuitry is needed to control the power supply (VCC). The below circuit diagrams depicts the options to control the power supply (VCC) using GPIO from Host with the switching logic.

Note: Due to the single P channel MOSFET (FDN304P) behavior, GPIO must be connected and drive the pin to LOW to enable the VCC supply to OPTIGA™ Trust M. This adaption must be done in the optiga host library (ifx_i2c.c), refer 11.1.1 for details. Value of the pullup resistors depend on the target application circuit and the target I2C frequency.

Note: Value of the pullup resistors depend on the target application circuit and the target I2C frequency. If GPIO pin is connected, set the GPIO pin to HIGH to enable the VCC to OPTIGA™ Trust M.

Description of packages

This chapter provides information on the package types and how the interfaces of each product are assigned to the package pins. For further information on compliance of the packages with European Parliament Directives, see "RoHS Compliance" on Page 25. For details and recommendations regarding the assembly of packages on PCBs, please see the following: www.infineon.com/cms/en/product/technology/packages/

4.1 PG-USON-10-2,-4

The package dimensions (in mm) of the controller in PG-USON-10-2,-4 packages are given below.

The following figure shows the PG-USON-10-2,-4 in top view:

4.2 Production sample marking pattern

The following figure describes the productive sample marking pattern on PG-USON-10-2,-4.

The black dot indicates pin 01 for the chip. The following Table 5 describes the sample marking pattern:

Table 5: Marking table for PG-USON-10-2,-4 packages

Indicator Convention: T&#$@ where: T indicates the OPTIGA Trust family, & indicates the product is a Trust M controller, # indicates the controller is a STR (S) variant, $ specifies the OPTIGA™ Trust M release version number, @ specifies the software version. Example: "TMS10" means 'OPTIGA™ Trust M', 'STR variant', 'release version 1', 'software version 0'.

Table 6: Contact definitions and functions of PG-USON-10-2,-4 packages

Technical Data

This section summarizes the technical data of the product. It provides the operational characteristics as well as the electrical DC and AC characteristics.

5.1 I2C Interface Characteristics

Table 7: I2C Operation Supply and Input Voltages

¹ Whichever is lower

5.1.1 I2C Standard/Fast Mode Interface Characteristics

For operation of the I2C interface, the electrical characteristics are compliant with the I²C bus specification Rev. 4 for "standard-mode" (fSCL up to 100 kHz) and "fast-mode" (fSCL up to 400 kHz), with certain deviations as stated in the table below.

Note: TA as given for the operating temperature range of the controller unless otherwise stated.

Table 8: I2C Standard Mode Interface Characteristics

5.1.2 I2C Fast Mode Plus Interface Characteristics

For operation of the I2C interface, the electrical characteristics are compliant with the I²C bus specification Rev. 4 for "fast mode plus" (fSCL up to 1 MHz), with certain deviations as stated in the table below.

Note: TA as given for the operating temperature range of the controller unless otherwise stated.

Table 9: I2C Fast Mode Interface Characteristics

5.1.2 I2C Fast Mode Plus Interface Characteristics

For operation of the I2C interface, the electrical characteristics are compliant with the I²C bus specification Rev. 4 for "fast mode plus" (fSCL up to 1 MHz), with certain deviations as stated in the table below.

Note: TA as given for the operating temperature range of the controller unless otherwise stated.

Table 10: I2C Fast Mode Plus Interface Characteristics

5.1.3 Electrical Characteristics

Note: TA as given for the operating temperature range of the controller unless otherwise stated. All currents flowing into the controller are considered positive.

5.1.3.1 DC Electrical Characteristics

TA as given for the controller's operating ambient temperature range unless otherwise stated. All currents flowing into the controller are considered positive.

Table 11: Electrical Characteristics

¹ Supply current can be limited from 6mA to 15mA by software commands.

5.1.3.2 AC Electrical Characteristics

TA as given for the controller's operating ambient temperature range unless otherwise stated. All currents flowing into the controller are considered positive.

Table 12: AC Characteristics

The Vcc ramp is depicted in Figure 9. 90% of the target supply voltage must be reached within tVCCR after it has exceeded 400 mV. Moreover, its variation must be kept within a ±10% range.

5.1.4 Start-Up of I2C Interface

There are 2 variants possible for performing the startup procedure:

• Startup after power-on
• Startup for warm resets

5.1.4.1 Startup after Power-On

The activation of the I2C interface after power-on needs the following reset procedure.

• VCC is powered up and the state of the SDA and SCL line are set to high level during power-up.
• The first transmission may start at the earliest tstartup after power-up of the device.

The following figure shows the startup timing of the I2C interface for this case.

5.1.4.2 Startup for Warm Resets

When using the reset signal for triggering a warm reset after power-on, the activation of the I2C interface needs the following reset procedure:

• VCC remains powered up.
• The terminal stops I2C communication. SDA and SCL lines are set to high level before RST is set to low level.
• After its falling edge, RST has to be kept at low level for at least t₁. At the latest t2 after the falling edge of RST, the terminal must set RST to high level.
• The first transmission may start at the earliest tstartup after the rising edge of RST.

The following figure shows the timing for this startup case.

Note: If NVM programming was requested prior to the reset, tSTARTUP will be extended from a typical value of 15 ms to a maximum of 20 ms.

Table 13: Startup of I2C Interface After Power-On

Table 14: Startup of I2C Interface for Warm Resets¹

¹ Reset triggered by software (without power off/on cycle)

OPTIGA™ Trust M External Interface

6.1 Commands

This section provides short description of the commands exposed by the OPTIGA™ Trust M security chip and mapping of these commands w.r.t Use Cases.

Table 15: Command table

Table 16: Mapping of commands with Use cases

¹ EncryptSym and DecryptSym is supported only in v3

² Secure key update is supported only in v3

6.2 Crypto Performance

The performance metrics for various schemes are provided by the Table 18 below. If not particularly mentioned, the performance is measured @ OPTIGA™ Trust M I/O interface with:

• I2C FM (400KHz)
• Without power limitation
• @ 25°C
• VCC = 3.3V
• RSA Signature scheme: RSA SSA PKCS#1 v1.5 without hashing
• ECDSA Signature scheme: ECDSA FIPS 186-3 without hashing
• Encryption/Decryption scheme: RSAES PKCS#1 v1.5
• Hash scheme: SHA256
• Key Derivation scheme: TLS v1.2 PRF SHA256, HKDF SHA256
• RSA Key size: 2048 bits
• ECC Key size: 256 bits (NIST P-256)
• AES Key size: 128 bits

Table 17: Crypto performance for V1

¹Minimum Execution of the entire sequence in milli seconds, except the External World timings

²RSA key pair generation performance is not predictable and typically have a variation in performance. This could be significantly higher or lower as the one specified in the table which is an average value over collected samples.

Table 18: Crypto performance for V3

¹ Minimum Execution of the entire sequence in milli seconds, except the External World timings

² RSA key pair generation performance is not predictable and typically have a variation in performance. This could be significantly higher or lower as the one specified in the table which is an average value over collected samples.

Security Monitor

The Security Monitor is a central component which enforces the security policy of the OPTIGA™ Trust M. It consumes security events sent by security aware parts of the OPTIGA™ Trust M embedded SW and takes actions accordingly as specified in Security Policy below.

7.1 Security Events

The events below actively influence the security monitor.

Table 19: Security Events

7.2 Security Policy

Security Monitor judges the notified security events regarding the number of occurrence over time and in case those violate the permitted usage profile of the system takes actions to throttle down the performance and thus the possible frequency of attacks.

The permitted usage profile is defined as:

1. tmax is set to 5 seconds (± 5%)
2. A Suspect System Behavior event is never permitted and will cause setting the Security Event Counter (SEC) to its maximum (= 255).
3. One protected operation (refer to Table 19) events per tmax period.

In other words it must not allow more than one out of the protected operations per tmax period (worst case, ref to bullet 3. above). This condition must be stable, at least after 500 uninterrupted executions of protected operations.

For more information, please refer to Solution Reference Manual document available as part of the package.

RoHS Compliance

On January 27, 2003 the European Parliament and the council adopted the directives:

• 2002/95/EC on the Restriction of the use of certain Hazardous Substances in electrical and electronic equipment ("RoHS")
• 2002/96/EC on Waste Electrical and Electrical and Electronic Equipment ("WEEE")

Some of these restricted (lead) or recycling-relevant (brominated flame retardants) substances are currently found in the terminations (e.g. lead finish, bumps, balls) and substrate materials or mold compounds.

The European Union has finalized the Directives. It is the member states' task to convert these Directives into national laws. Most national laws are available, some member states have extended timelines for implementation. The laws arising from these Directives have come into force in 2006 or 2007.

The electro and electronic industry has to eliminate lead and other hazardous materials from their products. In addition, discussions are on-going with regard to the separate recycling of certain materials, e.g. plastic containing brominated flame retardants.

Infineon Technologies is fully committed to giving its customers maximum support in their efforts to convert to lead-free and halogen-free¹ products. For this reason, Infineon Technologies' "Green Products" are ROHS-compliant.

Since all hazardous substances have been removed, Infineon Technologies calls its lead-free and halogen-free semiconductor packages "green." Details on Infineon Technologies' definition and upper limits for the restricted materials can be found here.

The assembly process of our high-technology semiconductor chips is an integral part of our quality strategy. Accordingly, we will accurately evaluate and test alternative materials in order to replace lead and halogen so that we end up with the same or higher quality standards for our products.

The use of lead-free solders for board assembly results in higher process temperatures and increased requirements for the heat resistivity of semiconductor packages. This issue is addressed by Infineon Technologies by a new classification of the Moisture Sensitivity Level (MSL). In a first step the existing products have been classified according to the new requirements.

[Image: A visual representation of lead-free and halogen-free components, with "green product compliant" logo.]

¹Any material used by Infineon Technologies is PBB and PBDE-free. Plastic containing brominated flame retardants, as mentioned in the WEEE directive, will be replaced if technically/economically beneficial.

Appendix A – Infineon I2C Protocol Registry Map

OPTIGA™ Trust M supports IFX I2C v2.01 and is implemented as I2C slave, which uses different address locations for status, control and data communication registers. These registers with description are outlined below in the following table.

Table 20: IFX I2C Registry Map Table

¹ In case the register returns 0xFFFFFFFF the register is not supported and the default values specified in Table 'List of protocol variations' shall be applied.

Table 21: Definition of BASE_ADDR

[Diagram: Bit allocation for BASE_ADDR register.]

Table 22: Definition of I2C_MODE

¹ In case the register returns 0xFFFFFFFF the register and its functionality is not supported

² This mode defines the adherence of the bus signals to the electrical characteristics according standard I2C bus specification

Table 23: Definition of I2C_STATE

9.1 Infineon I2C Protocol Variations

To fit best to application specific requirements the protocol might be tailored by specifying a couple of parameters which is described in the following table.

Table 24: List of Protocol Variations

Appendix B - OPTIGA™ Trust M Command/Response I2C Sample Logs

The default I2C slave address for the OPTIGA™ Trust M is 0x30 [I2C_ADDR]. All the values in this section are specified in decimal form unless stated otherwise.

10.1 Sequence of commands to read Coprocessor UID from OPTIGA™ Trust M

Pre-requisites

1. Ensure that the security device is powered up.
2. The OPTIGA™ Trust M will not acknowledge the slave address sent by a host if it is either busy or in idle state. Hence the host must retry or repeat the transaction until it is successful or timed out for 100 milliseconds (extreme case).
3. The specified guard time must be applied between each attempt of write / read operation by the Host I2C driver.
4. The log information for OPTIGA™ Trust M commands specified in below Tables contains the [IFX I2C] protocol information which comprises sequence numbers and checksum of the transactions.
   • A sequence of commands must be strict for the OPTIGA™ Trust M (e.g. OpenApplication followed by GetDataObject to read a Coprocessor UID).
   • A checksum in the data depends on the data received or sent via write/read operations. So any data change in the transaction is reflected in the check sum. Otherwise the write data transaction will not be accepted/acknowledged by the OPTIGA™ Trust M.
5. The logs specified below are without the presentation layer (used for the Shielded Connection) of [IFX I2C].

10.1.1 Check the status [I2C_STATE]

This is a very basic register read operation which ensures the behavior of the read/write operations of the local host I2C driver.

Table 25: Check I2C_STATE Register of OPTIGA™ Trust M

10.1.2 Issue OpenApplication command

Before issuing any application specific command; e.g. read Coprocessor UID using GetDataObject, it is a must to send the OpenApplication command to initialize the application on the OPTIGA™ Trust M as shown below.

Table 26: OpenApplication on OPTIGA™ Trust M

Step 2: Read the I2C_STATE register [Repeat this step until the read contains the data as specified below].

10.1.3 Read Coprocessor UID

The Coprocessor UID contains the OPTIGA™ Trust M unique ID and the build information details. The GetDataObject command is used to read the Coprocessor UID information.

Table 27: Read Coprocessor UID

Notes:

• XX is the unique ID part of the co-processor UID.
• "YY YY" is the OPTIGA™ Trust M build number in BCD (Binary Coded Decimal) format.
• ZZ ZZ is the checksum of the transaction.

Appendix C – Power Management

When operating, the power consumption of OPTIGA™ Trust M is limited to meet the requirements regarding the power limitation set by the Host. The power limitation is implemented by utilizing the current limitation feature of the underlying hardware device in steps of 1mA from 6mA to 15 mA with a precision of ±5%.

11.1 Hibernation

This maximizes power saving (zero power consumption¹), while the I2C bus stays connected. In this case OPTIGA™ Trust M saves the application context before power-off (switching off Vcc) and restores it after power-up. After power-up the application continues seamlessly from the state before hibernate.

11.1.1 Software adaption for Hibernate circuit with single MOSFET

Update the ifx_i2c.c file functions with the following change.

1. Call pal_gpio_set_low (p_ifx_i2c_context->p_slave_vdd_pin), to set the Vdd pin to High,
2. Call pal_gpio_set_high (p_ifx_i2c_context->p_slave_vdd_pin), to set the Vdd pin to Low.

[Code Snippet: C code demonstrating the update of ifx_i2c.c file for hibernate functionality.]

¹ Leakage current < 2.5µA only

11.2 Low Power Sleep Mode

The OPTIGA™ Trust M automatically enters a low-power mode after a configurable delay. Once it has entered Sleep mode, the OPTIGA™ Trust M resumes normal operation as soon as its address is detected on the I2C bus. In case no command is sent to the OPTIGA™ Trust M it behaves as shown in Figure 12.

1. As soon as the OPTIGA™ Trust M is idle it starts to count down the “delay to sleep" time (tSDY).
2. In case this time elapses the device enters the “go to sleep" procedure.
3. The "go to sleep” procedure waits until all idle tasks are finished (e.g. counting down the SEC). In case all idle tasks are finished and no command is pending, the OPTIGA™ Trust M enters sleep mode.

Revision history

Revision history