Vishay Intertechnology: Passives & Discrete Semiconductorsvishay.com/doc?91000vishay.com/doc?99912
Instructions for VISHAY models including: IRFPC60LC Siliconix Mouser India, IRFPC60LC, Siliconix Mouser India, Mouser India, India
[Vishay] IRFPC60LCPBF 반도체 > TR/FET/IGBT > MOSFET (주)엘레파츠 - 엘레파츠
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DocumentDocumentwww.vishay.com IRFPC60LC Vishay Siliconix Power MOSFET TO-247AC S D G D G S N-Channel MOSFET PRODUCT SUMMARY VDS (V) RDS(on) () Qg (max.) (nC) Qgs (nC) Qgd (nC) Configuration 600 VGS = 10 V 120 29 48 Single 0.40 FEATURES · Ultra low gate charge · Reduced gate drive requirement · Enhanced 30 V VGS rating · Reduced Ciss, Coss, Crss · Isolated central mounting hole Available · Dynamic dV/dt rated · Repetitive avalanche rated · Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 Note * This datasheet provides information about parts that are RoHS-compliant and / or parts that are non RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details DESCRIPTION This new series of low charge Power MOSFETs achieve significantly lower gate charge over conventional MOSFETs. Utilizing advanced Power MOSFETs technology the device improvements allow for reduced gate drive requirements, faster switching speeds and increased total system savings. These device improvements combined with the proven ruggedness and reliability of Power MOSFETs offer the designer a new standart in power transistors for switching applications. The TO-247AC package is preferred for commercial-industrial applications where higher power levels preclude the use of TO-220AB devices. The TO-247AC is similar but superior to the earlier TO-218 package because of its isolated mounting hole. ORDERING INFORMATION Package Lead (Pb)-free TO-247AC IRFPC60LCPbF ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL Drain-source voltage Gate-source voltage Continuous drain current Pulsed drain current a Linear derating factor Single pulse avalanche energy b Repetitive avalanche current a Repetitive avalanche energy a Maximum power dissipation Peak diode recovery dV/dt c VGS at 10 V TC = 25 °C TC = 100 °C TC = 25 °C VDS VGS ID IDM EAS IAR EAR PD dV/dt Operating junction and storage temperature range Soldering recommendations (peak temperature) for 10 s TJ, Tstg Mounting torque 6-32 or M3 screw Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11) b. VDD = 25 V, starting TJ = 25 °C, L = 7.2 mH, Rg = 25 , IAS = 16 A (see fig. 12) c. ISD 16 A, dI/dt 140 A/s, VDD VDS, TJ 150 °C d. 1.6 mm from case LIMIT 600 ± 30 16 10 64 2.2 1000 16 28 280 3.0 -55 to +150 300 d 10 1.1 UNIT V A W/°C mJ A mJ W V/ns °C lbf · in N · m S22-0096-Rev. C, 31-Jan-2022 1 Document Number: 91244 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Downloaded from Arrow.com. www.vishay.com IRFPC60LC Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER Maximum junction-to-ambient Case-to-sink, flat, greased surface Maximum junction-to-case (drain) SYMBOL RthJA RthCS RthJC TYP. - 0.24 - MAX. 40 0.45 UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. Static Drain-source breakdown voltage VDS temperature coefficient Gate-source threshold voltage Gate-source leakage Zero gate voltage drain current Drain-source on-state resistance Forward transconductance Dynamic VDS VDS/TJ VGS(th) IGSS IDSS RDS(on) gfs VGS = 0 V, ID = 250 A Reference to 25 °C, ID = 1 mA VDS = VGS, ID = 250 A VGS = ± 20 V VDS = 600 V, VGS = 0 V VDS = 480 V, VGS = 0 V, TJ = 125 °C VGS = 10 V ID = 9.6 A b VDS = 50 V, ID = 9.6 A 600 - - - 0.63 - 2.0 - 4.0 - - ± 100 - - 25 - - 250 - - 0.40 11 - - Input capacitance Output capacitance Reverse transfer capacitance Output capacitance Effective output capacitance Total gate charge Gate-source charge Gate-drain charge Turn-on delay time Internal drain inductance Internal source inductance Ciss Coss Crss Qg Qgs Qgd td(on) tr td(off) tf LD LS VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 VGS = 10 V ID = 16 A, VDS = 360 V, see fig. 6 and 13 b VDD = 300 V, ID = 16 A, Rg = 4.3 , RD = 18 , see fig. 10 b Between lead, 6 mm (0.25") from package and center of die contact D G S - 3500 - - 400 - - 39 - - - 120 - - 29 - - 48 - 17 - - 57 - - 43 - - 38 - - 5.0 - - 13 - Drain-Source Body Diode Characteristics Continuous source-drain diode current Pulsed diode forward current a IS MOSFET symbol showing the ISM integral reverse p - n junction diode D G S - - 16 - - 64 Body diode voltage Body diode reverse recovery time Body diode reverse recovery charge Forward turn-on time VSD TJ = 25 °C, IS = 16 A, VGS = 0 V b - - 1.8 trr Qrr TJ = 25 °C, IF = 16 A, dI/dt = 100 A/s - 650 980 - 6.0 9.0 ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11) b. Pulse width 300 s; duty cycle 2 % UNIT V V/°C V nA A S pF nC ns nH A V ns C S22-0096-Rev. C, 31-Jan-2022 2 Document Number: 91244 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Downloaded from Arrow.com. www.vishay.com TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) IRFPC60LC Vishay Siliconix Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 3 - Typical Transfer Characteristics Fig. 2 - Typical Output Characteristics, TC = 150 °C Fig. 4 - Normalized On-Resistance vs. Temperature S22-0096-Rev. C, 31-Jan-2022 3 Document Number: 91244 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Downloaded from Arrow.com. www.vishay.com IRFPC60LC Vishay Siliconix Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 8 - Maximum Safe Operating Area S22-0096-Rev. C, 31-Jan-2022 4 Document Number: 91244 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Downloaded from Arrow.com. www.vishay.com Fig. 9 - Maximum Drain Current vs. Case Temperature IRFPC60LC Vishay Siliconix VDS VGS RG RD D.U.T. 10 V Pulse width 1 µs Duty factor 0.1 % +- VDD Fig. 10 - Switching Time Test Circuit VDS 90 % 10 % VGS td(on) tr td(off) tf Fig. 11 - Switching Time Waveforms Fig. 12 - Maximum Effective Transient Thermal Impedance, Junction-to-Case VDS Vary tp to obtain required IAS RG 10 V tp L D.U.T IAS 0.01 + - V DD Fig. 13 - Unclamped Inductive Test Circuit VDS VDS tp VDD IAS Fig. 14 - Unclamped Inductive Waveforms S22-0096-Rev. C, 31-Jan-2022 5 Document Number: 91244 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Downloaded from Arrow.com. www.vishay.com IRFPC60LC Vishay Siliconix Fig. 15 - Maximum Avalanche Energy vs. Drain Current 10 V QGS VG QG QGD Charge Fig. 16 - Basic Gate Charge Waveform Current regulator Same type as D.U.T. 12 V 50 k 0.2 µF 0.3 µF + D.U.T. - VDS VGS 3 mA IG ID Current sampling resistors Fig. 17 - Gate Charge Test S22-0096-Rev. C, 31-Jan-2022 6 Document Number: 91244 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Downloaded from Arrow.com. www.vishay.com D.U.T. + - Peak Diode Recovery dV/dt Test Circuit + Circuit layout considerations · Low stray inductance · Ground plane · Low leakage inductance current transformer - - + IRFPC60LC Vishay Siliconix Rg · dV/dt controlled by Rg + · Driver same type as D.U.T. · ISD controlled by duty factor "D" - VDD · D.U.T. - device under test Driver gate drive P.W. Period D = P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt VDD Re-applied voltage Body diode forward drop Inductor current Ripple 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 18 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91244. S22-0096-Rev. C, 31-Jan-2022 7 Document Number: 91244 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Downloaded from Arrow.com. www.vishay.com Package Information Vishay Siliconix TO-247AC (High Voltage) VERSION 1: FACILITY CODE = 9 DIM. A A1 A2 b b1 b2 b3 b4 b5 c c1 D MILLIMETERS MIN. NOM. 4.83 5.02 2.29 2.41 1.17 1.27 1.12 1.20 1.12 1.20 1.91 2.00 1.91 2.00 2.87 3.00 2.87 3.00 0.40 0.50 0.40 0.50 20.40 20.55 MAX. 5.21 2.55 1.37 1.33 1.28 2.39 2.34 3.22 3.18 0.60 0.56 20.70 NOTES 6 6, 8 6 4 DIM. D1 D2 E E1 E2 e L L1 Ø P Ø P1 Q S MIN. 16.46 0.56 15.50 13.46 4.52 14.90 3.96 3.56 5.31 MILLIMETERS NOM. 16.76 0.66 15.70 14.02 4.91 5.46 BSC 15.15 4.06 3.61 7.19 ref. 5.50 5.51 BSC MAX. 17.06 0.76 15.87 14.16 5.49 15.40 4.16 3.65 5.69 NOTES 5 4 5 3 6 7 Notes (1) Package reference: JEDEC® TO247, variation AC (2) All dimensions are in mm (3) Slot required, notch may be rounded (4) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outermost extremes of the plastic body (5) Thermal pad contour optional with dimensions D1 and E1 (6) Lead finish uncontrolled in L1 (7) Ø P to have a maximum draft angle of 1.5° to the top of the part with a maximum hole diameter of 3.91 mm (8) Dimension b2 and b4 does not include dambar protrusion. Allowable dambar protrusion shall be 0.1 mm total in excess of b2 and b4 dimension at maximum material condition Revision: 31-Oct-2022 1 Document Number: 91360 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Downloaded from Arrow.com. www.vishay.com VERSION 2: FACILITY CODE = Y B 3 R/2 Q 4 E E/2 S 2 x R (2) D 12 3 5 L1 C L 2 x b2 3 x b 2x e b4 0.10 M C A M Lead Assignments 1. Gate 2. Drain 3. Source 4. Drain See view B Package Information Vishay Siliconix A A2 A 4 D A 7 ØP Ø k M DBM D2 (Datum B) ØP1 4 D1 4 Thermal pad A C A1 D DE E CC View B Planting 4 E1 0.01 M D B M View A - A (b1, b3, b5) Base metal (c) c1 (b, b2, b4) (4) Section C - C, D - D, E - E DIM. A A1 A2 b b1 b2 b3 b4 b5 c c1 D D1 MILLIMETERS MIN. MAX. 4.58 5.31 2.21 2.59 1.17 2.49 0.99 1.40 0.99 1.35 1.53 2.39 1.65 2.37 2.42 3.43 2.59 3.38 0.38 0.86 0.38 0.76 19.71 20.82 13.08 - NOTES DIM. D2 E E1 e Ø k L L1 Ø P Ø P1 Q R S MILLIMETERS MIN. MAX. 0.51 1.30 15.29 15.87 13.72 - 5.46 BSC 0.254 14.20 16.25 3.71 4.29 3.51 3.66 - 7.39 5.31 5.69 4.52 5.49 5.51 BSC NOTES Notes (1) Dimensioning and tolerancing per ASME Y14.5M-1994 (2) Contour of slot optional (3) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body (4) Thermal pad contour optional with dimensions D1 and E1 (5) Lead finish uncontrolled in L1 (6) Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154") (7) Outline conforms to JEDEC outline TO-247 with exception of dimension c Revision: 31-Oct-2022 2 Document Number: 91360 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Downloaded from Arrow.com. www.vishay.com VERSION 3: FACILITY CODE = N B R/2 E N Q R S D Package Information Vishay Siliconix D2 A A P1 P A2 D c1 D1 K M DBM L1 C b2 b b4 e 0.10 M C A M L C A1 Base metal E1 0.01 M D B M b1, b3, b5 c Plating b, b2, b4 MILLIMETERS MILLIMETERS DIM. MIN. A 4.65 A1 2.21 A2 1.17 b 0.99 b1 0.99 b2 1.65 b3 1.65 b4 2.59 b5 2.59 c 0.38 c1 0.38 D 19.71 D1 13.08 ECN: E22-0452-Rev. G, 31-Oct-2022 DWG: 5971 MAX. 5.31 2.59 1.37 1.40 1.35 2.39 2.34 3.43 3.38 0.89 0.84 20.70 - DIM. D2 E E1 e k L L1 N P P1 Q R S MIN. 0.51 15.29 13.46 14.20 3.71 3.56 - 5.31 4.52 5.46 BSC 0.254 7.62 BSC 5.51 BSC MAX. 1.35 15.87 - 16.10 4.29 3.66 7.39 5.69 5.49 Notes (1) Dimensioning and tolerancing per ASME Y14.5M-1994 (2) Contour of slot optional (3) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body (4) Thermal pad contour optional with dimensions D1 and E1 (5) Lead finish uncontrolled in L1 (6) Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154") Revision: 31-Oct-2022 3 Document Number: 91360 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Downloaded from Arrow.com. www.vishay.com Disclaimer Legal Disclaimer Notice Vishay ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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