Wi-Fi Module, BT Module, IoT Module Manufacturer & Supplier - Fn-Link
User Manual for Fn-Link models including: 3161A-SL Wi-Fi Single-band, Wi-Fi Single-band, Single-band, SDIO
HUNAN FN-LINK TECHNOLOGY LIMITED 3161ASL WIFI Module 3161A-SL 2AATL3161ASL 2AATL3161ASL 3161asl
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DocumentDocument3161A-SL Wi-Fi Single-band 1X1 802.11b/g/n SDIO Module Datasheet FN-LINK TECHNOLOGY LIMITED Proprietary & Confidential Information 3161A-SL Module Datasheet Office: 6 Floor, Building U6, Junxiang U8 Park, Hangcheng Avenue, Bao'an District, Shenzhen City, CHINA Factory: No.8, Litong Road, Liuyang Economic & Technical Development Zone, Changsha, Hunan, CHINA TEL: +86-755-2955-8186 Website: www.fn-link.com Customer Approval : Company Title Signature Date Fn-Link FN-LINK TECHNOLOGY LIMITED Proprietary & Confidential Information Revision History Version 1.0 1.1 Date 2020/04/22 2020/05/30 Revision Content New version Add 1line sdio application 3161A-SL Draft Lxy Lxy Approved Szs Szs FN-LINK TECHNOLOGY LIMITED Proprietary & Confidential Information CONTENTS 3161A-SL 1 Overview....................................................................................................................................1 1.1 Introduction......................................................................................................................... 1 1.2 Features.............................................................................................................................. 1 1.3 General Specification........................................................................................................ 2 1.4 Recommended Operating Rating....................................................................................2 2 Wi-Fi RF Specification........................................................................................................... 3 2.1 2.4GHz RF Specification.................................................................................................. 3 3 Pin Assignments..................................................................................................................... 3 3.1 Pin Outline...........................................................................................................................4 3.2 Pin Definition.......................................................................................................................5 4 Dimensions...............................................................................................................................7 4.1 Module Picture................................................................................................................... 7 4.2 Marking Description...........................................................................................................7 4.3 Module Physical Dimensions........................................................................................... 8 4.4 Layout Recommendation..................................................................................................8 5 Host Interface Timing Diagram......................................................................................... 10 5.1 SDIO Pin Description...................................................................................................... 10 5.2 SDIO CLK Timing Diagram............................................................................................ 10 6 Reference Design................................................................................................................. 19 6.1 Low Power Dissipation Reference Design.................................................................. 19 6.2 Normal Power dissipation Reference Design............................................................. 20 7 Ordering Information........................................................................................................... 21 8 The Key Material List........................................................................................................... 21 9 Power on Sequence............................................................................................................. 22 10 Design Attention................................................................................................................. 22 11 Recommended Reflow Profile.........................................................................................22 12 Packing Information...........................................................................................................23 12.1 Reel................................................................................................................................. 23 12.2 Carrier Tape Detail........................................................................................................ 24 12.3 Packaging Detail............................................................................................................24 12.4 Moisture sensitivity........................................................................................................ 25 FN-LINK TECHNOLOGY LIMITED Proprietary & Confidential Information 3161A-SL 1 Overview 1.1 Introduction 3161A-SL is a highly integrated 2.4 GHz Wi-Fi module that support the IEEE 802.11b/g/n baseband and RF circuit. It supports 20 MHz standard bandwidth and 5 MHz/10 MHz narrow bandwidth, and provides a physical layer rate up to 72.2 Mbit/s. Wi-Fi baseband supports the orthogonal frequency division multiplexing (OFDM) technology and is backward compatible with the direct sequence spread spectrum (DSSS) and complementary code keying (CCK) technologies, offering various data rates defined in the IEEE 802.11 b/g/n protocol. Module chipset integrates a high-performance 32-bit microprocessor, a hardware security engine, and various peripheral interfaces, including the SPI, UART, I2C, PWM, GPIO, and multi-channel ADC. In addition, it provides high-speed SDIO2.0 slave interfaces, with clock frequency up to 50 MHz. Its built-in SRAM and flash can operate independently and even programming is allowed on the flash. Block Diagram: 1.2 Features Operate at ISM frequency bands (2.4GHz) FN-LINK TECHNOLOGY LIMITED 1 Proprietary & Confidential Information 3161A-SL Maximum rate of 72.2 Mbit/s@HT20 MCS7 SDIO interface for Wi-Fi Low power dissipation High transmitting power High receiving sensitivity PHY supporting IEEE 802.11b/g/n MAC supporting IEEE802.11 d/e/h/i/k/v/w Module integrated 32K clock WFA WPA, WFA WPA2 personal, and WPS2.0 for Wi-Fi Built-in 352 KB SRAM and 288 KB ROM Main chipset Built-in 32bit MCU and 2 MB flash memory 1.3 General Specification Model Name Product Description Dimension Wi-Fi Interface Ambient temperature Storage temperature RoHS 3161A-SL Support Wi-Fi functionality L x W x H: 12 x 12 x2.3 (typical) mm Support SDIO -40°C to 85°C -40°C to 85°C All hardware components are fully compliant with EU RoHS directive 1.4 Recommended Operating Rating Ambient temperature VCC VDDIO Sleep Mode TX Test mode Power Consumption (2.4G HT20@17dbm) RX Test mode (2.4G HT20) Note: Suggested power input range in 3.3V. Min. -40 2.3 - Typ. Max. Unit 25 85 deg.C 3.3 3.6 V 1.8V/3.3V - V VCC = 3.3V(Unit:mA) 5uA 288 53 FN-LINK TECHNOLOGY LIMITED 2 Proprietary & Confidential Information 3161A-SL 2 Wi-Fi RF Specification 2.1 2.4GHz RF Specification Feature Description WLAN Standard IEEE 802.11 b/g/n Wi-Fi compliant Frequency Range 2.4002.4835GHz Wi-Fi: Number of Channels US: channel 1~11; EU: channel 1~13; Japan: channel 1~14; Spectrum Mask Min. b/g/n Typ. b/g/n Max. b/g/n Unit b/g/n 1st side lobes(to fc ± 11MHZ) - -43/-30/-40 - dBr 2st side lobes(to fc ± 22MHZ) - -52/-33/-58 - dBr Freq. Tolerance -20/-20/-20 - 20/20/20 ppm Test Items Typical Value EVM 802.11b /11Mbps : 16dBm ± 1.5 dB EVM -10dB Output Power 802.11g /54Mbps : 16dBm ± 1.5 dB EVM -25dB 802.11n /MCS7 : 16dBm ± 1.5 dB EVM -28dB Test Items Test Value Standard Value - 1Mbps PER @ -97 dBm -94 dBm SISO Receive Sensitivity - 2Mbps PER @ -95 dBm -92 dBm (11b,20MHz) @8% PER - 5.5Mbps PER @ -92 dBm -89 dBm - 11Mbps PER @ -90 dBm -87 dBm - 6Mbps PER @ -94 dBm -89 dBm - 9Mbps PER @ -92 dBm -88 dBm SISO Receive Sensitivity (11g,20MHz) @10% PER - 12Mbps - 18Mbps - 24Mbps PER @ -91 dBm PER @ -88 dBm PER @ -85 dBm -87 dBm -86 dBm -84 dBm - 36Mbps PER @ -82 dBm -80 dBm - 48Mbps PER @ -79 dBm -77 dBm - 54Mbps PER @ -77 dBm -75 dBm - MCS=0 PER @ -93 dBm -89 dBm SISO Receive Sensitivity (11n,20MHz) @10% PER - MCS=1 - MCS=2 - MCS=3 PER @ -90 dBm PER @ -89 dBm PER @ -85 dBm -86 dBm -84 dBm -82 dBm - MCS=4 PER @ -82 dBm -79 dBm FN-LINK TECHNOLOGY LIMITED 3 Proprietary & Confidential Information Maximum Input Level Antenna Reference 3161A-SL - MCS=5 PER @ -78 dBm -76 dBm - MCS=6 PER @ -76 dBm -74 dBm - MCS=7 PER @ -73 dBm -72 dBm 802.11b: -10 dBm 802.11g/n: -20 dBm PCB antenna with 0~2 dBi peak gain 3 Pin Assignments 3.1 Pin Outline <TOP VIEW> FN-LINK TECHNOLOGY LIMITED 4 Proprietary & Confidential Information 3.2 Pin Definition NO Name 1 GND 2 WL_ANT 3 GND 4 NC 5 NC 6 Host wake device Type I/O I 7 GPIO8 I/O 8 NC 9 VCC P 10 NC 11 NC 12 PMU_POWRON I 13 GPIO2 I/O 14 SDIO_DATA_2 I/O 15 SDIO_DATA_3 I/O 16 SDIO_DATA_CMD I/O 17 SDIO_DATA_CLK I 18 SDIO_DATA_0 I/O 19 SDIO_DATA_1 I/O 20 GND 21 NC 22 VDDIO P 23 NC 24 RTC_CLK O I/O 25 RTC_CLK I I 26 NC 27 NC 28 NC 29 NC 30 NC 31 GND 32 NC 3161A-SL Description Ground connections RF I/O port Ground connections Floating (Don't connected to ground) Floating (Don't connected to ground) Host Wake up Wi-Fi,GPIO06 GPIO or configured as SDIO interrupt pin. (If not used keep Floating) Floating (Don't connected to ground) Main power voltage source input 2.3V-3.6V Floating (Don't connected to ground) Floating (Don't connected to ground) Enable pin for WLAN device Defualt ON: pull high ; OFF: pull low SDIO data interrupt,or GPIO function. SDIO data line 2, GPIO09 SDIO data line 3, GPIO10 SDIO command line, GPIO11 SDIO clock line, GPIO12 SDIO data line 0, GPIO13 SDIO data line 1, GPIO14 Ground connections Floating (Don't connected to ground) I/O Voltage supply input 1.8V/3.3V Floating (Don't connected to ground) Floating(module have 32K clock), GPIO00 Floating(module have 32K clock), GPIO01 Floating (Don't connected to ground) Floating (Don't connected to ground) Floating (Don't connected to ground) Floating (Don't connected to ground) Floating (Don't connected to ground) Ground connections Floating (Don't connected to ground) Voltage VDDIO VDDIO 3.3V VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO FN-LINK TECHNOLOGY LIMITED 5 Proprietary & Confidential Information 3161A-SL 33 GND 34 NC - 35 NC 36 GND 37 UART_LOG_TX 38 UART_LOG_RX 39 WL_RST I 40 Dev_Wake_Host O 41 NC 42 NC 43 NC 44 NC P:POWER I:INPUT O:OUTPUT Ground connections Floating (Don't connected to ground) Floating (Don't connected to ground) Ground connections UART0_LOG_TX,GPIO03 For firmware download, can floating this pin UART0_LOG_RX,GPIO04 For firmware download, can floating this pin Wi-Fi reset pin. GPIO07 Low: reset enable, Defualt High: reset disable Wi-Fi wake up host. GPIO05 Floating (Don't connected to ground) Floating (Don't connected to ground) Floating (Don't connected to ground) Floating (Don't connected to ground) VDDIO VDDIO VDDIO VDDIO 3.3 Muti Pin definition 3861L all GPIO pin can configure as muti function,detail see below information. Pin NAME F.0 F.1 F.2 F.3 F.4 F.5 F.6 24 GPIO00 GPIO00 UART1_TXD SPI1_CLK PWM3 I2C1_SDA RTC_OSC_32K RTC32K_XOUT 25 GPIO01 GPIO01 UART1_RXD SPI1_RXD PWM4 I2C1_SCL / RTC32K_XINT 13 GPIO02 GPIO02 UART1_RTS SPI1_TXD PWM2 / SSI_CLK / 37 GPIO03 UART0_LOG_TX UART1_CTS SPI1_CS1 PWM5 I2C1_SDA SSI_DATA GPIO03 38 GPIO04 UART0_LOG_RX / / PWM1 I2C1_SCL / GPIO04 40 GPIO05 UART1_RXD GPIO05 I2S0_MCK PWM2 / BT_STATUS SPI0_CS1 6 GPIO06 UART1_TXD GPIO06 I2S0_TX PWM3 / COEX_SWITH SPI0_CLK 39 GPIO07 UART1_CTS GPIO07 I2S0_CLK PWM0 / BT_ACTIVE SPI0_RXD 7 GPIO08 UART1_RTS GPIO08 I2S0_WS PWM1 / WLAN_ACTIVE SPI0_TXD 14 GPIO09 GPIO09 UART2_RTS SPI0_TXD PWM0 I2C0_SCL I2S0_MCK SDIO_D2 15 GPIO10 GPIO10 UART2_CTS SPI0_CLK PWM1 I2C0_SDA I2S0_TX SDIO_D3 16 GPIO11 GPIO11 UART2_TXD SPI0_RXD PWM2 / I2S0_RX SDIO_CMD 17 GPIO12 GPIO12 UART2_RXD SPI0_CS1 PWM3 / I2S0_CLK SDIO_CLK 18 GPIO13 GPIO13 UART2_RTS UART0_LOG_TX PWM4 I2C0_SDA I2S0_WS SDIO_D0 F.7 / / / / ADC1 ADC2 / ADC3 / ADC4 / ADC5 ADC0 ADC6 F.8 / / / / / / / / / / / / / SSI_DATA FN-LINK TECHNOLOGY LIMITED 6 Proprietary & Confidential Information 19 GPIO14 GPIO14 Notes 1. IO Ispu/O. 2. 1mA. 3. 3.3/1.8V. UART2_CTS UART0_LOG_RX PWM5 I2C0_SCL / 3161A-SL SDIO_D1 / SSI_CLK 4 Dimensions 4.1 Module Picture L x W : 12 x 12 (+0.3/-0.1) mm H: 2.3 (±0.2) mm Weight 0.66g 4.2 Marking Description < TOP VIEW > FN-LINK TECHNOLOGY LIMITED 7 Proprietary & Confidential Information 3161A-SL 4.3 Module Physical Dimensions (Unit: mm) < TOP VIEW > 1,15 0,65 0,25 6 5,125 4,75 4,25 3,85 3,35 2,95 2,45 2,05 1,55 6 5,125 4,75 4,25 3,85 3,35 2,95 2,45 2,05 1,55 1,15 0,65 0,25 4.4 Layout Recommendation (Unit: mm) FN-LINK TECHNOLOGY LIMITED 8 Proprietary & Confidential Information 3161A-SL < TOP VIEW > 1,15 0,65 0,25 6,25 6 5,125 4,75 4,25 3,85 3,35 2,95 2,45 2,05 1,55 6,25 6 5,125 4,75 4,25 3,85 3,35 2,95 2,45 2,05 1,55 1,15 0,65 0,25 FN-LINK TECHNOLOGY LIMITED 9 Proprietary & Confidential Information 3161A-SL 5 Host Interface Timing Diagram 5.1 SDIO Pin Description The secure digital input/output (SDIO) interface supports three working modes: Default speed mode (DS) The maximum frequency of the interface clock is 25 MHz. The interface clock can work in 1-bit or 4-bit mode. High speed mode (HS) The maximum frequency of the interface clock is 50 MHz. SDR25 mode The maximum frequency of the interface clock is 50 MHz SDIO Pin Description SD 4-Bit Mode DATA0 Data Line 0 DATA1 Data Line 1 DATA2 Data Line 2 DATA3 Data Line 3 CLK Clock CMD Command Line 5.2 SDIO CLK Timing Diagram DS Mode The DS mode is the default mode after the SDIO is powered on. To ensure compatibility with various host components, the DS mode requires a low working rate and supports only the 25 MHz clock. FN-LINK TECHNOLOGY LIMITED 10 Proprietary & Confidential Information 3161A-SL Figure 8-6 shows the output data timing in DS mode. tISU is the setup time, that is, the stability time required by the data of the SDIO interface before clock sampling in this mode. tIH is the hold time, that is, the time required by the data of the SDIO interface to retain the original level after clock sampling in this mode. FN-LINK TECHNOLOGY LIMITED 11 Proprietary & Confidential Information 3161A-SL Figure 8-7 shows the input data timing in DS mode. Where, tODLY(max) is the maximum delay of the output data relative to the clock falling edge, and tODLY(min) is the minimum delay of the output data relative to the clock falling edge. Table 8-12 describes the timing restrictions in DS mode. FN-LINK TECHNOLOGY LIMITED 12 Proprietary & Confidential Information 3161A-SL Note: In DS mode, the output data is referenced to the clock falling edge, and the input data is referenced to the clock rising edge. HS Mode The HS mode is entered after the SDIO is powered on and initialized because a higher working rate than the DS mode is required. In HS mode, the clock supports 50 MHz. For details about the restrictions on the clock, see Table 8-13. FN-LINK TECHNOLOGY LIMITED 13 Proprietary & Confidential Information 3161A-SL Figure 8-8 shows the input data timing in HS mode. tISU is the setup time, that is, the stability time required by the data of the SDIO interface before clock sampling in this mode. tIH is the hold time, that is, the time required by the data of the SDIO interface to retain the original level after clock sampling in this mode Figure 8-9 shows the input data timing in HS mode. Where, tODLY(max) is the maximum delay of the output data relative to the clock rising edge, and tOH is the minimum delay of the output data relative to the clock rising edge. FN-LINK TECHNOLOGY LIMITED 14 Proprietary & Confidential Information 3161A-SL Table 8-15 describes the timing restrictions in HS mode. Table 8-16 Timing restrictions in HS mode (VDDIO = 1.8 V) FN-LINK TECHNOLOGY LIMITED 15 Proprietary & Confidential Information 3161A-SL Note: The data signal timing in HS mode is different from that in DS mode. The output data and input data are referenced to the clock rising edge. SDR25 Mode The SDR25 mode is entered only after the voltage of the SDIO is switched. In this mode, the maximum interface clock frequency is 50 MHz. Table 8-17 describes the clock restrictions. FN-LINK TECHNOLOGY LIMITED 16 Proprietary & Confidential Information 3161A-SL FN-LINK TECHNOLOGY LIMITED 17 Proprietary & Confidential Information 3161A-SL FN-LINK TECHNOLOGY LIMITED 18 Proprietary & Confidential Information 6 Reference Design 6.1 4line SDIO Reference Design 3161A-SL VDDIO VDDIO DEV WAKE HOST WL_RST UART0_LOG_RX UART0_LOG_TX R11 NC/4.7K R10 NC/4.7K C10 C11 NC/680pF NC/680pF 44 NC 43 NC 42 NC 41 NC 40 DEV2HOST_WAKE 39 WL_RST 38 UART_RX 37 UART_TX 36 GND 35 NC 34 NC L1 10pF C1 NP WL_ANT C2 NP HOST WAKE DEV MUTI FUNCTION 3.3V C3 4.7uF 1 GND 2 WL_ANT 3 GND 4 NC 5 NC 6 HOST2DEV_WAKE 7 GPIO8 8 NC 9 VBAT 10 NC 11 NC 33 GND 32 NC 31 GND 30 NC 29 NC 28 NC 27 NC 26 NC 25 RTC_CLK 24 RTC_CLK 23 NC 12 POW_EN 13 SD_interrupt 14 SDIO_DATA_2 15 SDIO_DATA_3 16 SDIO_DATA_CMD 17 SDIO_DATA_CLK 18 SDIO_DATA_0 19 SDIO_DATA_1 20 GND 21 NC 22 VDDIO PWRON SD_INT VDDIO 22R 22R 22R 22R 22R 22R R1 R5 R6 R7 R8 R9 VDDIO C8 4.7uF SDIO_D1 SDIO_D0 SDIO_CLK SDIO_CMD SDIO_D3 SDIO_D2 VDDIO R21 R20 R19 R18 NC/47KNC/47KNC/47KNC/47K HOST SDIO_D2 SDIO_D3 SDIO_CMD SDIO_CLK SDIO_D0 SDIO_D1 HOST WAKE DEV PWRON SD_INT C39 NC/10pf UART0_LOG_RX UART0_LOG_TX WL_RST DEV WAKE HOST MUTI FUNCTION HOST WAKE DEV PWRON SD_INT SDIO_D2 SDIO_D3 SDIO_CMD SDIO_CLK SDIO_D0 SDIO_D1 UART0_LOG_TX UART0_LOG_RX WL_RST DEV WAKE HOST GPIO Notes: 1. 4line WLAN module application, all wake function may not supported; 2. Can using Power EN pin to shut down module for power saving; FN-LINK TECHNOLOGY LIMITED 19 Proprietary & Confidential Information 6.2 1line SDIO Reference Design 3161A-SL 1. Hi3861L Hi18EV300 - GPIO8 - GPIO11 - GPIO12 - GPIO13 Hisyslink Hi3861L SDIO 1 2. 3161A WIFI (PORPower On Reset)GPIO2/GPIO6/GPIO8 Flash GPIO2/GPIO6/GPIO8 PIR USB Hi3861L POR 3. WIFI UART GPIO3/GPIO4 TX GPIO_3 RX GPIO4 UART UART 900Kbps-2Mbps UART GPIO3/4 LED ( ) FN-LINK TECHNOLOGY LIMITED 20 Proprietary & Confidential Information 3161A-SL 4. WIFI GPIO3/GPIO5/GPIO7/GPIO14 WIFI 5. GPIO7 GPIO GPIO ADC 6. WIFI IO VDDIO VDDIO 3.3V WIFI IO 3.3V button reset or UART0 LED LED PIR_OUT ADC UART0_LOG_RX UART0_LOG_TX or MCU 44 NC 43 NC 42 NC 41 NC 40 DEV2HOST_WAKE 39 WL_RST 38 UART_RX 37 UART_TX 36 GND 35 NC 34 NC GPIO03 GPIO04 GPIO07 GPIO05 or UART1 PIR PIR_OUT PIR_OUT PIR_IN PIR_IN L6 10pF C49 NP WL_ANT C50 NP ADC or GPIO GPIO SDIO INT 3.3V C48 4.7uF 1 GND 2 WL_ANT 3 GND 4 NC 5 NC 6 HOST2DEV_WAKE GPIO06 7 GPIO8 8 NC 9 VBAT 10 NC 11 NC 33 GND 32 NC 31 GND 30 NC 29 NC 28 NC 27 NC 26 NC 25 GPIO01 RTC_CLK 24 GPIO00 RTC_CLK 23 NC GPIO14 GPIO13 GPIO12 22 VDDIO 21 NC 20 GND 19 SDIO_DATA_1 18 SDIO_DATA_0 17 SDIO_DATA_CLK 16 SDIO_DATA_CMD GPIO11 GPIO10 GPIO09 GPIO02 15 SDIO_DATA_3 14 SDIO_DATA_2 13 SD_interrupt 12 POW_EN PWRON GPIO02 GPIO09 GPIO10 VDDIO VDDIO GPIO14 22R 22R 22R R36 R37 R38 I2C ADC battery charge status charge VDDIO C51 4.7uF SDIO_D0 SDIO_CLK SDIO_CMD USB R44 NC/47K PWRON SDIO_INT C54 NC/10pf HOST PWRON SD_INT SDIO_D0 SDIO_CLK SDIO_CMD 7 Ordering Information Part No. FG3161ASLX-00 FG3161ASLX-01 Description Hi3861L, b/g/n Wi-Fi, 1T1R, 12X12mm, SDIO, PCB V1.0 Halogen Free,with shielding. Hi3861L, b/g/n Wi-Fi, 1T1R, 12X12mm, SDIO, PCB V1.0 Halogen Free,no shielding. 8 The Key Material List Main 2016 2.2uH ,±20%DCR=0.125ohmIsat=1.5AIrms=1.5A Inductor MPIE201610-2R2M-LF) Main Shielding 3161A-SL-V1.0 Shielding cover, no insulation glue, no FN-LINK TECHNOLOGY LIMITED 21 Proprietary & Confidential Information 3161A-SL Main Alt. Main Main cover Crystal Crystal RTC Chipset positioning foot (material: copper) Xintai 2520 40MHZ,13.8PF,7ppm,SR:50 ,E2SB40E00000GE (HOSONIC) 2520 40MHz 15pF ±10ppm -40~85 Q40000V024 3215 32.768KHZ 12.5PF 20PPM -40~85 ° C SF32K32768D31T-12.5 () Hi3861LRNIV100 WiFi IoT Soc,802.11b/g/n, WiFi Mesh, 2M Flash, SDIO,UART,QFN32, 5x5mm () 9 Power on Sequence VCC / VDDIO supreme electrical order requirements In the process of power up, GPIO02 internal weak pull low ,the 40MHz crystal is selected.. 10 Design Attention 1. GPIO02 is the interrupt signal of SDIO, It also can be configured as dev wake host function. 2. GPIO8 can be setting as SDIO interrupt function. 3. PMU_PWRON is enable pin of the module. Default is pull high. 4. Wake function may not supported with recently applications, for power saving please using POWER EN pin enable or disable the module. 11 Recommended Reflow Profile Referred to IPC/JEDEC standard. Peak Temperature : <250°C FN-LINK TECHNOLOGY LIMITED 22 Proprietary & Confidential Information Number of Times : 2 times 3161A-SL 12 Packing Information 12.1 Reel A roll of 1500pcs FN-LINK TECHNOLOGY LIMITED 23 Proprietary & Confidential Information 3161A-SL 12.2 Carrier Tape Detail 12.3 Packaging Detail FN-LINK TECHNOLOGY LIMITED 24 Proprietary & Confidential Information 3161A-SL 12.4 Moisture sensitivity The Modules is a Moisture Sensitive Device level 3, in according with standard IPC/JEDEC J-STD-020, take care all the relatives requirements for using this kind of components. Moreover, the customer has to take care of the following conditions: a) Calculated shelf life in sealed bag: 12 months at <40°C and <90% relative humidity (RH). b) Environmental condition during the production: 30°C / 60% RH according to IPC/JEDEC J-STD-033A paragraph 5. c) The maximum time between the opening of the sealed bag and the reflow process must be 168 hours if condition b) "IPC/JEDEC J-STD-033A paragraph 5.2" is respected d) Baking is required if conditions b) or c) are not respected e) Baking is required if the humidity indicator inside the bag indicates 10% RH or more FN-LINK TECHNOLOGY LIMITED 25 Proprietary & Confidential Information