MAX153

General Description

The MAX153 is a high-speed, microprocessor (µP)-compatible, 8-bit analog-to-digital converter (ADC) that utilizes a half-flash technique to achieve a 660ns conversion time, digitizing at a rate of 1M samples per second (Msps). It operates with single +5V or dual ±5V supplies and accepts either unipolar or bipolar inputs. A POWERDN (power-down) pin reduces current consumption to a typical value of 1µA (with 5V supply). The device returns from power-down to normal operating mode in less than 200ns, providing significant reductions in supply current in applications with burst-mode input signals.

The MAX153 is DC and dynamically tested. Its µP interface appears as a memory location or input/output port that requires no external interface logic. The data outputs use latched, three-state buffered circuitry for direct connection to a µP data bus or system input port. The ADC's input/reference arrangement enables ratiometric operation.

Applications

• Cellular Telephones
• Portable Radios
• Battery-Powered Systems
• Burst-Mode Data Acquisition
• Digital-Signal Processing
• Telecommunications
• High-Speed Servo Loops

Ordering Information appears at end of data sheet.

For related parts and recommended products to use with this part, refer to www.maximintegrated.com/MAX153.related.

Features

• 660ns Conversion Time
• Power-Up/Power-Down in 200ns
• Internal Track/Hold
• 1Msps Throughput
• Low Power: 40mW (Operating Mode), 5µW (Power-Down Mode)
• 1MHz Full-Power Bandwidth
• 20-Pin Narrow DIP, SO, and SSOP Packages
• Unipolar/Bipolar Inputs
• No External Clock Required
• Single +5V or Dual ±5V Supplies
• Ratiometric Reference Inputs

Functional Diagram

A diagram shows the functional blocks of the MAX153, including the VIN, VREF+, VREF-, VDD, VSS, PWRDN, MODE, WR/RDY, RD, INT, CS, GND pins, and the internal ADC components like the 4-BIT FLASH ADC, DAC, THREE-STATE OUTPUT DRIVERS, and TIMING AND CONTROL CIRCUITRY.

Absolute Maximum Ratings

(All voltages referenced to GND.)

Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Electrical Characteristics

(VDD = +5V ±5%, VGND = 0V; Unipolar Input Range: VSS = GND, VREF+ = 5V, VREF- = GND; Bipolar Input Range: VSS = -5V ±5%, VREF+ = 2.5V, VREF- = -2.5V; 100% production tested, specifications are given for RD Mode (MODE = GND), TA = Tmin to TMAX, unless otherwise noted.)

ACCURACY

DYNAMIC SPECIFICATIONS (Note 1)

Conversion Time (WR-RD Mode) (Note 2)

Conversion Time (RD Mode)

ANALOG INPUT

REFERENCE INPUT

Electrical Characteristics (continued)

(VDD = +5V ±5%, VGND = 0V; Unipolar Input Range: VSS = GND, VREF+ = 5V, VREF- = GND; Bipolar Input Range: VSS = -5V ±5%, VREF+ = 2.5V, VREF- = -2.5V; 100% production tested, specifications are given for RD Mode (MODE = GND), TA = Tmin to TMAX, unless otherwise noted.)

LOGIC INPUTS

LOGIC OUTPUTS

POWER REQUIREMENTS

Note 1: Bipolar input range, VIN = ±2.5Vp-p. WR-RD mode.

Note 2: See Figure 1 for load circuit. Parameter defined as the time required for the output to cross +0.8V or +2.4V.

Note 3: Guaranteed by design.

Note 4: Tested with CS, RD, PWRDN at CMOS logic levels. Power-down current increases to several hundred µA at TTL levels.

TIMING CHARACTERISTICS (Note 5)

(VDD = +5V ±5%, VSS = 0V for Unipolar Input Range, VSS = -5V ±5% for Bipolar Input Range, 100% production tested, TA = +25°C, unless otherwise noted.)

Note 5: Input control signals are specified with tr = t₁ = 5ns, 10% to 90% of +5V and timed from a 1.6V voltage level.

Note 6: RL = 5.1kΩ pullup resistor.

Note 7: See Figure 2 for load circuit. Parameter defined as the time required for data lines to change 0.5V.

TIMING CHARACTERISTICS (Note 5) (continued)

Figure 1. Load Circuits for Data-Access Time Test

A diagram shows test circuits for data-access time, illustrating HIGH-Z to VOH and HIGH-Z to VOL transitions with load resistors and capacitors.

Figure 2. Load Circuits for Data-Hold Time Test

A diagram shows test circuits for data-hold time, illustrating VOH to HIGH-Z and VOL to HIGH-Z transitions with load resistors and capacitors.

Typical Operating Characteristics

Graphs illustrating various operating characteristics:

• Conversion Time vs. Ambient Temperature: Shows conversion time normalized to the value at +25°C across a temperature range of -60°C to +140°C for different VDD values.
• Effective Bits vs. Input Frequency, WR-RD Mode: Shows effective bits as a function of input frequency for different temperatures (hot +125°C, cold -55°C, room) with a sample rate of 1MHz and VIN = ±2.5V.
• Signal-to-Noise Ratio: Shows SNR as a function of frequency for an input frequency of 195.8kHz and a sample frequency of 1MHz, with SNR = 49.1dB.
• Intermodulation Distortion: Shows IMD as a function of frequency for input frequencies of 94.97kHz and 84.72kHz (±2.5V) with a sample frequency of 500kHz. 2nd-order terms are -66.2dB and 3rd-order terms are -60.0dB.

Pin Configuration

A pinout diagram for the MAX153 in PDIP/SO(W)/SSOP packages is provided, labeling each pin with its name and function.

Pin Description

*See the Digital Interface section.

Detailed Description

Converter Operation

The MAX153 employs a half-flash conversion technique, utilizing two 4-bit flash ADC sections to achieve an 8-bit result. With 15 comparators, the flash ADC compares the unknown input voltage to the reference ladder, providing the upper 4 data bits. An internal digital-to-analog converter (DAC) then uses these 4 most significant bits (MSBs) to generate an analog result from the first flash conversion and a residue voltage. This residue is compared again with the flash comparators to obtain the lower 4 data bits (LSBs).

Power-Down Mode

For burst-mode or low sample-rate applications, the MAX153 can be shut down between conversions, reducing supply current to microamp levels. A TTL/CMOS logic-low on the PWRDN pin shuts the device down, reducing supply current to typically 1µA when powered from a single 5V supply. CS must be high when power-down is used. A logic-high on PWRDN wakes up the MAX153. A new conversion can be started (WR asserted low) within 360ns of the PWRDN pin being driven high (200ns to power up plus 160ns for track/hold acquisition). If power-down mode is not required, connect PWRDN to VDD.

When the MAX153 is in power-down mode, the lowest supply current is drawn with MODE low (RD mode) due to an internal 50µA pulldown resistor at this pin. CS must remain high during shutdown, as the MAX153 may attempt to start a conversion that it cannot complete. Additionally, for minimum current consumption, other digital inputs should remain stable in power-down. RDY, an open-drain output (in RD mode), will then fall and remain low throughout. Power-down sinks additional supply current unless CS remains high. Refer to the Reference section for information on reducing reference current during power-down.

Digital Interface

The MAX153 offers two basic interface modes, determined by the status of the MODE input pin. When MODE is low, the converter operates in RD mode; when MODE is high, the converter is configured for WR-RD mode.

Read Mode (MODE = 0)

In RD mode, conversion control and data access are managed by the RD input (Figure 3). The comparator inputs track the analog input voltage for the duration of tp. A minimum of 160ns is required for the input to be acquired. A conversion is initiated by driving RD low. For µPs that can be forced into a wait state, hold RD low until output data is available. The µP starts the conversion, waits, and then reads data with a single read instruction.

WR/RDY functions as a status output (RDY) in RD mode, capable of driving the ready or wait input of a µP. RDY is an open-collector output (without an internal pullup) that goes low after the falling edge of CS and goes high at the end of the conversion. If not utilized, the WR/RDY pin can be left unconnected. The INT output goes low at the end of the conversion and returns high on the rising edge of CS or RD.

Write-Read Mode (MODE = 1)

Figures 4 and 5 illustrate the operating sequence for the write-read (WR-RD) mode. The comparator inputs track the analog input voltage for the duration of tp. A minimum of 160ns is required for the input voltage to be acquired. The conversion is initiated by a falling edge of WR. When WR returns high, the 4 MSBs flash result is latched into the output buffers, and the 4 LSBs conversion begins. INT goes low approximately 380ns later, indicating conversion completion, and the lower 4 data bits are latched into the output buffers. The data then becomes accessible 65ns to 130ns after RD goes low (refer to Timing Characteristics).

For externally controlled conversion time, drive RD low 250ns after WR goes high. This latches the lower 4 data bits and outputs the conversion result on D0–D7. A minimum 160ns delay is required from INT going low to the start of another conversion (WR going low).

Options for reading data from the converter include:

Using Internal Delay

The µP waits for the INT output to go low before reading the data (Figure 4). INT typically goes low 380ns after the rising edge of WR, indicating conversion completion, and the result is available in the output latch. With CS low, data outputs D0–D7 can be accessed by pulling RD low. INT is then reset by the rising edge of CS or RD.

Figure 3. RD Mode Timing (MODE = 0)

A timing diagram illustrates the sequence of signals (CS, RD, RDY, INT, D0-D7) in RD mode.

Figure 4. WR-RD Mode Timing (tRD > TINTL) (MODE = 1)

A timing diagram illustrates the sequence of signals (CS, WR, RD, INT, D0-D7) in WR-RD mode when tRD > TINTL.

Figure 5. WR-RD Mode Timing (tRD > TINTL), Fastest Operating Mode (MODE = 1)

A timing diagram illustrates the sequence of signals (CS, WR, RD, INT, D0-D7) in WR-RD mode, showing the fastest operating mode when tRD > TINTL.

Figure 6. Pipelined Mode Timing (WR = RD) (MODE = 1)

A timing diagram illustrates the sequence of signals (CS, WR, RD, INT, D0-D7) in pipelined mode where WR and RD are connected.

Fastest Conversion: Reading Before Delay

An external method for controlling conversion time is shown in Figure 5. The internally generated delay tINTL varies slightly with temperature and supply voltage and can be overridden with RD to achieve the fastest conversion time. INT is ignored, and RD is brought low typically 250ns after the rising edge of WR. This completes the conversion and enables the output buffers (D0–D7) containing the conversion result. INT also goes low after the falling edge of RD and is reset on the rising edge of RD or CS. The total conversion time is therefore: tCWR = twr (250ns) + tcSH (0ns) to trp (250ns) + tACC1 (160ns) = 660ns.

Pipelined Operation

In addition to the two standard WR-RD mode options, pipelined operation can be achieved by connecting WR and RD together (Figure 6). With CS low, driving WR and RD low initiates a conversion and reads the result of the previous conversion concurrently.

Analog Considerations

Reference

Figures 7a–7c show reference connections. VREF+ and VREF- inputs set the full-scale and zero-input voltages of the ADC. The voltage at VREF- determines the input that produces an output code of all zeros, and the voltage at VREF+ defines the input that produces an output code of all ones.

The internal resistances from VREF+ and VREF- may be as low as 1kΩ. Since current is still drawn by the reference inputs during power-down, reference supply current can be reduced during shutdown by using the circuit shown in Figure 7d. A logic-level n-channel MOSFET, connected between VREF- and ground, disconnects the reference load when the ADC enters power-down (PWRDN = low). The FET should have no more than 0.5Ω of on-resistance to maintain accuracy.

Figure 7a. Power Supply as Reference

A circuit diagram shows a power supply configuration for the MAX153 using VDD and VSS as reference inputs.

Figure 7b. External Reference, +2.5V Full Scale

A circuit diagram shows an external reference configuration for the MAX153 using a MAX584 for a +2.5V full-scale range.

Figure 7c. Input Not Referenced to GND

A circuit diagram shows an input configuration for the MAX153 where the input is not referenced to GND.

Figure 7d. An n-Channel MOSFET Switches Off the Reference Load During Power-Down

A circuit diagram illustrates how an n-channel MOSFET can be used to switch off the reference load during power-down.

Bypassing

A 4.7µF electrolytic capacitor in parallel with a 0.1µF ceramic capacitor should be used to bypass VDD to GND. These capacitors should have minimal lead length.

The reference inputs should be bypassed with 0.1µF capacitors, as shown in Figures 7a–7c.

Input Current

Figure 8 shows the equivalent circuit of the converter input. When the conversion starts and WR is low, VIN is connected to 16 0.6pF capacitors. During this acquisition phase, the input capacitors charge to the input voltage through the resistance of the internal analog switches (about 2kΩ). In addition, about 12pF of stray capacitance must be charged. The input can be modeled as an equivalent RC network (Figure 9). As source impedance increases, the capacitors take longer to charge.

The typical 22pF input capacitance allows source resistance as high as 2.2kΩ without setup problems. For larger resistances, the acquisition time (tp) must be increased.

Figure 8. Equivalent Input Circuit

A diagram shows the equivalent input circuit of the MAX153, including input resistance (RIN), switch resistance (RON), and capacitance (C).

Figure 9. RC Network Equivalent Input Model

A diagram shows an RC network model for the input of the MAX153.

Conversion Rate

The maximum sampling rate (fMAX) for the MAX153 is achieved in the WR-RD mode (tRD < tINTL) and is calculated as follows:

fMAX = 1 / (tWR + tRD + tRI + tp)

fMAX = 1 / (250ns + 250ns + 150ns + 165ns) = 1.23MHz

where twr = Write pulse width

tRD = Delay between WR and RD pulses

tRI = RD to INT delay

tp = Delay time between conversions

Signal-to-Noise Ratio and Effective Number of Bits

Signal-to-noise ratio (SNR) is the ratio of the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other analog-to-digital output values. The output band is limited to one-half the A/D sample (conversion) rate. This ratio usually includes distortion as well as noise components. For this reason, the ratio is sometimes referred to as signal-to-noise plus distortion.

The theoretical minimum A/D noise is caused by quantization error and results directly from the ADC's resolution: SNR = (6.02N + 1.76)dB, where N is the number of bits of resolution. Therefore, a perfect 8-bit ADC can do no better than 50dB.

The FFT plot (Typical Operating Characteristics) shows the result of sampling a pure 200kHz sinusoid at a 1MHz rate. This FFT plot of the output shows the output level in various spectral bands.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal (in the frequency band above DC and below one-half the sample rate) to the fundamental itself. This is expressed as:

THD = 20 log [√(V2² + V3² + V4² + ... + VN²) / V1]

where V1 is the fundamental RMS amplitude, and V2 to VN are the amplitudes of the 2nd through Nth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is the ratio of the fundamental RMS amplitude to the amplitude of the next largest spectral component (in the frequency band above DC and below one-half the sample rate). Usually, this peak occurs at some harmonic of the input frequency, but if the ADC is exceptionally linear, it may occur only at a random peak in the ADC's noise floor.

Intermodulation Distortion

An FFT plot of intermodulation distortion (IMD) is generated by sampling an analog input applied to the ADC. This input consists of very low distortion sine waves at two frequencies. A 2048-point plot for IMD of the MAX153 is shown in the Typical Operating Characteristics.

Ordering Information

+Denotes a lead(Pb)-free/RoHS-compliant package.

*Contact factory for dice specifications.

**Contact factory for availability of SSOP packages.

Package Information

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

Chip Information

PROCESS: BICMOS

Revision History

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