Raspberry Pi Compute Module 5

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This documentation is licensed under a Creative Commons Attribution-NoDerivatives 4.0 International (CC BY-ND).

Release: 2

Build date: 02/09/2025

Build version: cd3be3a671b6

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1. Introduction

The Raspberry Pi Compute Module 5 (CM5) is a System on Module (SoM) designed to deliver the functionality of Raspberry Pi in a compact and flexible form factor suited to embedded and industrial applications. It enables developers and system designers to leverage the Raspberry Pi hardware and software stack in their own custom systems and designs.

CM5 includes a processor, memory (RAM), eMMC flash storage, and supporting power circuitry. It also provides I/O interfaces beyond those available on standard Raspberry Pi boards, offering expanded options for more complex systems and designs.

Figure 1. A visual representation of the Raspberry Pi Compute Module 5 (CM5), showing its front (left) and back (right) views.

For support documentation for CM5, see the Compute Module section of https://www.raspberrypi.com. You can also post a question to the Forum.

1.1. Connectors

CM5 includes two 100-pin high-density connectors, providing access to nearly all CM5 interfaces. Together, these connectors transmit power, data, and control signals to a carrier board. The top connector on CM5 contains pins 1 to 100; the bottom connector of CM5 contains pins 101 to 200. For information about each pin's assignment, see Section 4.2. Pinout.

CM5 has a companion carrier board, the Raspberry Pi Compute Module 5 IO Board (CM5IO) board, which is designed to expose and enable CM5 interfaces. You can also design your own carrier board based on the CM5IO board. The CM5IO design files are freely available. For detailed specifications and pinout information about CM5IO, see the Compute Module 5 IO board documentation.

1.2. Compatibility

CM5 and CM5Lite are mostly compatible with the previous generation of Compute Module. This means that CM5 can be used in many existing designs and carrier boards with minimal changes. For a list of specific differences between CM5 and CM4, see Appendix B. CM4 and CM5 differences.

Note: The previous generation of Compute Module (CM4) is still for sale and will remain in production until at least January 2034.

CM5 connects to carrier boards through its two 100-pin connectors. The main change in the pin layout (pinout) compared to the previous Compute Module is the addition of support for two USB 3.0 ports. For a list of pin differences between CM5 and CM4, see Appendix B.1. Pinout changes.

1.3. Features

The design of CM5 is loosely based on Raspberry Pi 5. For cost-sensitive applications, CM5 is also available without the eMMC storage; this variant is called Raspberry Pi Compute Module 5 Lite (CM5Lite). Unless otherwise stated, within this document, CM5 also refers to CM5Lite.

Key features of CM5 are as follows:

• High-performance SoC: Broadcom BCM2712 quad-core Cortex-A76 (ARMv8) 64-bit processor running at 2.4 GHz.
• Compact module design: Small footprint of 55 mm x 40 mm x 4.7 mm module with four M2.5 mounting holes.
• Video decoding: Hardware-accelerated 4kp60 HEVC video decoder.
• Graphics support: OpenGL ES 3.1 and Vulkan 1.2 for modern GPU acceleration.
• Memory options: Available with 2 GB, 4 GB, 8 GB, or 16 GB LPDDR4x-4267 SDRAM with ECC support. For more information about memory options, see Section 6. Ordering information.
• Flash storage: Fast onboard eMMC flash storage with the following options:
  • Speed: An eMMC bandwidth of up to 400 MB/s, which is four times faster than previous compute modules.
  • Storage: Options for 16 GB, 32 GB, or 64 GB eMMC flash memory (for CM5), or no eMMC flash memory (CM5Lite). For more information about storage options, see Section 6. Ordering information.
• Additional SDIO interface for CM5Lite: One SDIO 2.0 interface to provide external storage or peripheral expansion in place of onboard eMMC (CM5Lite only).
• Optional certified wireless module: Option (see Section 6. Ordering information) for certified radio module with:
  • Dual-band Wi-Fi (2.4 GHz and 5.0 GHz IEEE 802.11 b/g/n/ac).
  • Bluetooth 5.0 with BLE.
  • On-board electronic antenna switch that allows selection between PCB trace or external antenna.
• Wired networking: Integrated Gigabit Ethernet PHY with IEEE 1588 precision time protocol support.
• PCIe expansion: One-lane PCIe Gen 2 (5 Gb/s) host interference for high-speed peripherals.
• USB connectivity: USB options for both High-Speed and SuperSpeed peripherals:
  • One USB 2.0 high-speed port.
  • Two USB 3.0 (SuperSpeed) ports, supporting simultaneous 5 Gb/s data transfer.
• Flexible GPIO and peripheral support: Up to 30 GPIOs, supporting 1.8 V or 3.3 V signalling, with multiple peripheral interfaces:
  • Up to five UART
  • Up to five I2C
  • Up to five SPI
  • One SDIO interface
  • One DPI (parallel RGB display)
  • One I2S
  • Up to four PWM channels
  • Up to three GPCLK outputs
• Dual HDMI outputs: Two HDMI 2.0 ports, each supporting up to 4Kp60 output simultaneously.
• Dual 4-lane MIPI interfaces: Two MIPI ports supporting both DSI (display port) and CSI-2 (camera port) functionality.
• Power input: Single 5 V power input with USB power delivery support for up to 5 A at 5 V.
• Real-time clock (RTC): Integrated RTC powered by an external battery for timekeeping when offline.
• Fan control: Dedicated 2-pin fan control with PWM for active thermal management.

2. Interfaces

CM5 includes a range of interfaces (physical connectors, control signals, and configuration mechanisms) to support diverse applications, from high-speed storage and networking to wireless communication, display outputs, and flexible GPIO expansion. These interfaces allow you to build connected and adaptable embedded systems. The following sections provide technical information on each available interface, including configuration options, routing guidelines, and design considerations.

2.1. Wireless

CM5 supports both Wi-Fi and Bluetooth functionality, allowing developers and system designers to flexibly manage wireless connectivity for a range of applications.

The wireless interfaces on CM5 are provided by the Cypress CYW43455 silicon, supporting both:

• 2.4 GHz and 5.0 GHz IEEE 802.11 b/g/n/ac Wi-Fi.
• Bluetooth 5.0 and BLE.

You can enable and disable these wireless functions independently as required. For example, in kiosk deployments, a service engineer might temporarily enable wireless to perform updates, then disable it for security and regulatory compliance.

CM5 has an on-board PCB antenna that should be positioned away from conductive materials, such as metal or ground planes. For more information, see Section 4. Specifications. Alternatively, you can connect an external antenna through a standard U.FL connector. For the location of the connector, see the CM5 mechanical diagram in Section 4.1.1. PCB dimensions. See Figure 4

Antenna selection (internal or external) is configured at boot time using the config.txt file. This selection can't be changed during operation. To select the antenna, append one of the following lines to config.txt :

• dtparam=ant1 selects the internal PCB antenna.
• dtparam=ant2 selects the external antenna through a U.FL connector.

Raspberry Pi Ltd offers a certified antenna kit for use with CM5. If you use a third-party antenna, you must obtain your own separate certification because Raspberry Pi Ltd doesn't support certification with non-approved antennas.

Important: Raspberry Pi Ltd doesn't assist with certification for third-party antennas.

To support power savings and regulatory usage requirements, two control pins, wireless (Wi-Fi) disable ( WL_nDisable ) and Bluetooth disable ( BT_nDisable ), allow hardware-level shut down of Wi-Fi and Bluetooth, respectively. These pins are reserved on Compute Modules without wireless functionality.

2.1.1. Wi-Fi disable ( WL_nDisable )

The WL_nDisable pin indicates the enable/disable state of Wi-Fi and may also be used to disable Wi-Fi. This pin may only be driven low; it can't be driven high. The software driver drives it high internally when required.

• If the pin is high (logic 1), Wi-Fi is powered up. If Wi-Fi is enabled after being disabled, you must reinitialise the Wi-Fi driver.
• When driven or tied low (logic 0), the pin prevents Wi-Fi from powering up, helping to reduce power consumption or meet requirements to physically disable Wi-Fi.

2.1.2. Bluetooth disable ( BT_nDisable )

The BT_nDisable pin indicates the enable/disable state of Bluetooth and may also be used to disable Bluetooth. This pin may only be driven low; it can't be driven high. The software driver drives it high internally when required.

• If the pin is high (logic 1), Bluetooth is powered up. If Bluetooth is enabled after being disabled, you must reinitialise the Bluetooth driver.
• When driven or tied low (logic 0), the pin prevents Bluetooth from powering up, helping to reduce power consumption or meet requirements to physically disable Bluetooth.

2.2. Ethernet

Ethernet capabilities in CM5 provide reliable, high-throughput wired connectivity for applications requiring consistent network performance or time-synchronised operation. CM5 integrates a Gigabit Ethernet physical layer (PHY) device to provide high-performance, reliable wired networking: the Broadcom BCM54210PE. Key features of this PHY include:

• Compliance with IEEE 1588-2008 for PTP support, with an additional pin that can be an input or output.
• Automatic MDI crossover, pair skew correction, and pair polarity correction.

2.2.1. Connector and design guidance

Ethernet connects to CM5 using a standard 1:1 RJ45 MagJack. For designs supporting Power over Ethernet (PoE) and Electrostatic Discharge (ESD) protection, refer to the wiring example shown in Figure 2.

Figure 2. Schematic diagram illustrating the Ethernet interface for the Raspberry Pi Compute Module 5 (CM5), including Power over Ethernet (PoE) and Electrostatic Discharge (ESD) protection components.

Route the differential Ethernet signals as 100 Ω differential pairs with appropriate spacing and clearances. Length matching between different pairs is generally not required if differences are less than 50 mm. However, the signals within each pair need to be length matched for optimal signal integrity, ideally within 0.15 mm.

2.2.2. Status LEDs and sync output

The Ethernet interface also supports up to two active-low LEDs to give status feedback. These LEDs can indicate various Ethernet link or activity states depending on operating system (OS) and driver support. To see which LED functions are supported, consult the Ethernet driver documentation for your OS.

The Ethernet interface also provides SYNC_OUT at 3.3 V signalling, supporting IEEE 1588-2008 PTP. This pin can be optionally defined as an input.

2.3. PCIe Gen 2

CM5 has an internal PCIe 2.0 host controller, offering high-speed expansion options for NVMe storage, networking cards, and other peripherals. Operation in PCIe Gen 3.0 mode is possible in some cases, but is unsupported and might not function reliably.

Important: Ensure suitable OS driver support exists for your intended PCIe device (host controller) before prototyping.

Connecting a PCIe device follows the standard PCIe convention. CM5 includes on-board AC coupling capacitors for the PCIe_TX signals. However, external AC coupling capacitors are required for PCIe_RX signals, close to the driving source (the peripheral's TX ). PCIe and NVMe cards include these capacitors on board.

To ensure reliable PCIe operation, follow the electrical routing guidance and connect all mandatory control signals outlined below.

2.3.1. Routing guidance

When designing with PCIe on CM5, observe the following conventions for signal routing and connection:

• Direct IC connection: If connecting directly to another IC, swap the transmit (TX) and receive (RX) differential pairs; this involves connecting TX to RX and RX to TX. Ensure each receive ( PCIe-Rx ) line has an AC coupling capacitor (220 nF) before it enters the IC.
• Connector-based connection: If using a PCIe connector, the signals are labelled from the host's point of view, so TX and RX lines don't need to be swapped.

PCIe differential signals should be routed as 90 Ω differential pairs with proper clearances. Length matching between pairs is unnecessary, but the signals within a pair must be length-matched, ideally within 0.1 mm, to preserve signal integrity. You may swap the positive (P) and negative (N) line within a pair.

2.3.2. Required signals

The following control and clock signals must be handled correctly for proper PCIe operation:

• PCIe_CLK_nREQ must be connected to enable clock output from CM5.
• PCIe_nRST is required for proper device reset during initialisation or reboot.
• PCIe_nWAKE is available, but currently unsupported in software.

2.4. USB interfaces

CM5 provides support for both USB 3.0 (SuperSpeed) and USB 2.0 (High-Speed) interfaces. Both USB 3.0 and USB 2.0 require 90 Ω differential impedance, with length matching within each pair. You may swap the positive (P) and negative (N) signals for USB 3.0 pairs; USB 2.0 pairs can't be P/N swapped.

2.4.1. USB 3.0 (SuperSpeed)

CM5 includes two USB 3.0 interfaces, each supporting up to 5 Gb/s signalling simultaneously. The USB differential pairs should be routed with 90 Ω differential impedance. Length matching between separate pairs is unnecessary, but the P and N signals within each differential pair must be length-matched, ideally within 0.1 mm.

Note: P/N signal swapping is allowed for USB 3.0 pairs.

2.4.2. USB 2.0 (High-Speed)

The USB 2.0 interface supports up to 480 Mb/s signalling. The differential pair should be routed with a 90 Ω differential impedance. The P and N signals within each differential pair should be length-matched, ideally within 0.15 mm.

To enable USB 2.0 functionality, add the dtoverlay=dwc2,dr_mode=host overlay setting to your config.txt file.

Note: The USB 2.0 port can operate in USB On-The-Go (OTG) mode. While not officially documented, some users have successfully enabled this functionality. The USB_OTG_ID pin determines the role (host or device) and is typically connected to the ID pin of a Micro USB connector. To use OTG functionality, it must be enabled in the operating system (OS). For fixed-role use, tie the USB_OTG_ID pin to ground.

2.5. Video and display interfaces

CM5 supports a range of high-speed video interfaces for connecting both displays and cameras. It includes two HDMI 2.0 outputs, two 4-lane MIPI interfaces that can be used for DSI displays or CSI cameras, and support for parallel DPI displays through GPIO. CM5 can support up to three simultaneous displays of any type (HDMI, DSI, or DPI).

2.5.1. Dual HDMI 2.0

CM5 includes two HDMI 2.0 interfaces, each capable of supporting a 4K display. Consider the following to ensure reliable HDMI operation:

• HDMI signals must be routed as 100 Ω differential pairs.
• Within a pair, each signal should be length-matched within 0.15 mm.
• Between pairs, length matching within 25 mm is sufficient.
• Consumer Electronics Control (CEC) is supported, with an internal 27 kΩ pull-up resistor included in CM5.
• Extended Display Identification Data (EDID) signals have internal pull-up resistors in CM5.
• Like Raspberry Pi 5, CM5 doesn't have extra ESD protection on HDMI signals because it isn't typically required. Consider whether you might need extra ESD protection and then add it if required.

2.5.2. MIPI (CSI and DSI)

CM5 supports two 4-lane MIPI interfaces for connecting cameras (CSI) and displays (DSI). The MIPI signals must be routed as 100 Ω differential pairs. Within a pair, the signals should be length-matched within 0.15 mm.

In addition to DSI, displays can also be connected using the parallel DPI interface, available using GPIO functions. For more information, see Section 2.9.2. Alternative GPIO functions.

Camera Serial Interface (CSI-2)

CM5 supports camera modules through the CSI interface. For detailed information about the CSI interface, refer to the Raspberry Pi documentation. The following camera sensors are supported by official Raspberry Pi firmware:

• OmniVision OV5647
• Sony IMX219
• Sony IMX296
• Sony IMX477
• Sony IMX708

No security device is required on Compute Module products to use these camera sensors.

Display Serial Interface (DSI)

The DSI interface supports connection to MIPI DSI-compatible displays. CM5 is compatible with displays supported either by:

• The official Raspberry Pi firmware.
• The mainline Linux kernel.

For third-party displays not officially supported, you must provide a custom driver.

2.6. I2C interfaces

CM5 provides two I2C buses that can be repurposed depending on system configuration and peripheral usage.

2.6.1. MIPI I2C bus ( SDA0 and SCL0 )

The internal I2C bus is normally allocated to the MIPI0 interface. However, it can be used as a general I2C bus or GPIO if the MIPI0 interface isn't in use:

• The serial data pin ( SDA0 ) within the MIPI0 interface is connected to GPIO38 on RP1.
• The serial clock pin ( SCL0 ) within the MIPI0 interface is connected to GPIO39 on RP1.

2.6.2. HAT EEPROM identification I2C bus ( ID_SD and ID_SC )

CM5 includes another I2C bus, with signals exposed on the ID_SD (data) and ID_SC (clock) pins. This bus is typically reserved for identifying HATs and controlling MIPI1 devices.

If the firmware isn't using this I2C bus (for example, MIPI1 isn't being used), then these pins can be repurposed as GPIO0 and GPIO1 if needed. When using these pins as GPIO pins, add force_eeprom_read=0 to the config.txt file. This prevents the firmware from checking whether there's a HAT EEPROM available.

2.7. SDIO (CM5Lite only)

This section covers external storage options for CM5Lite with the SDIO interface.

CM5Lite doesn't include eMMC storage on board. However, it exposes Secure Digital Input Output (SDIO) interface for external storage through the connector: either an external eMMC or SD card (for removable storage).

Depending on the type of storage you use, consider the following configuration signals:

• External eMMC: Set SD_VDD_OVERRIDE to high ( CM5_3.3V ) to force 1.8 V signalling on the SDIO interface.
• SD card: Use the SD_PWR_ON signal to control an external power switch for an SD card. To enable SD card boot by default, add a pull-up resistor to keep the power switch on.

Note: SD cards require a power switch controlled by SD_PWR_ON ; this is the only way to reset the SD card.

Figure 3. Diagram showing the SD card interface for the CM5Lite model, detailing connections for SD card detection and power control.

2.8. Debug UART

There is space to fit a debug UART connector for troubleshooting and diagnosing. This connector provides the same functionality as Raspberry Pi 5. The connector is a three-pin, 1 mm pitch JST-SH connector (part number BM03B-SRSS-TB). The signals are replicated on the bottom as test points, allowing you access to the debug UART signals even if the main debug connector isn't fitted or available. For information about test points, see Appendix A. Test Points.

2.9. GPIO

There are 28 general-purpose I/O (GPIO) pins available, which correspond to the GPIO pins on the Raspberry Pi 5 40-pin header. These pins have access to internal peripherals, such as SMI, DPI, I2C, PWM, SPI, and UART. Details about these features and the available multiplexing options are described in the RP1 peripherals datasheet.

To minimise electromagnetic compatibility (EMC) issues, we recommend setting the drive strength and slew rate to the lowest levels necessary. GPIO2 and GPIO3 include 1.8 kΩ pull-up resistors.

The GPIO bank is powered by the GPIO_VREF supply. This can connect to CM5_1.8V for 1.8 V signalling, or CM5_3.3V for 3.3 V signalling. Don't exceed 50 mA for total current load on all 28 GPIO pins. GPIO_VREF must be connected to either CM5_3.3v or CM5_1.8v. It's possible to use 2.5 V signalling by supplying an external 2.5 V supply to GPIO_VREF. This external supply must only be active while CM5_1.8v is on and must be fully discharged within 1 ms after CM5_1.8v is going low.

2.9.1. Alternative function assignments

Up to six alternative function assignments are available on the GPIO pins. The following table provides an overview of these alternative functions. For more detailed information about these functions, see the peripherals datasheet.

Each GPIO can have only one function at a time. Likewise, each peripheral input (for example, I2C3_SCL ) must be assigned to only one GPIO pin. If the same peripheral input is connected to multiple GPIOs, the peripheral sees the logical OR of these GPIO inputs.

Function selections without a named function in the following table are reserved.

2.9.2. Alternative GPIO functions

A variety of alternative GPIO functions accommodate diverse peripheral interfaces and communication protocols. The following list summarises the available peripherals and their supported configurations:

• Five UARTs, with standard and extended wiring options:
  • Four UARTs with 4-wire interfaces for serial communication ( TX , RX , CTS , RTS ).
  • One UART ( UART0 ) with an 8-wire interface ( TX , RX , CTS , RTS , DTR , DCD , DSR , RI ) or an IrDA interface ( IR_TX , IR_RX ).
• One 4-bit SDIO for Secure Digital Input/Output.
• Four PWM channels for pulse-width modulation.
• One I2S Master interface ( ISC0 ), quadruple lane.
• One I2S, Slave interface ( ISC1 ), quadruple lane.
• Two AUDIO_OUT PWM audio outputs, which require buffering using a low-noise PSU buffer and filtering with a 22 KHz first-order RC network.
• Two AUDIO_IN digital PDM inputs.
• Two general-purpose clock (GPCLK) outputs.
• One DPI (Display Parallel Interface) with PCLK , DE , VSYNC , HSYNC , and up to 24-bit data.
• 28 GPIO ( SYS_RIO ) pins.
• Four I2C controllers ( SDA , SCL ).
• Six SPI controllers, detailed in Table 2, below.

For conventional SPI connections, the Serial Input/Output (SIO) pins numbered 0 and 1 have specific roles:

• SIO0 is the MOSI pin (Master Out Slave In).
• SIO1 is the MISO pin (Master In Slave Out).

The other SIO pins are required for the basic SPI communication to work.

2.9.3. Camera GPIOs ( CAM_GPIO )

CM5 includes two GPIO control signals for the camera module: CAM_GPIO0 and CAM_GPIO1 .

• CAM_GPIO0 is typically routed to pin 17 on the camera connector. This signal is used to control power to the camera module. CAM_GPIO0 corresponds to GPIO34 on RP1.
• CAM_GPIO1 has been added to CM5 for future expansion, and isn't present on previous Compute Modules; we recommend routing this signal to pin 18 on the camera connector. CAM_GPIO1 corresponds to GPIO35 on RP1.

2.10. Status LEDs ( LED_nACT and LED_nPWR )

Status LEDs on CM5 provide visual feedback about the board's activity and power states. These signals replicate the green and red LEDs found on Raspberry Pi 5, helping users monitor eMMC activity, boot errors, and power status.

• LED_nACT: This pin drives an LED that indicates eMMC or SD card access, replicating the green LED on Raspberry Pi 5. Under Linux, the LED flashes to signify eMMC or SD card access. If a boot error occurs, the LED flashes an error pattern. To decode these patterns, see the LED Flash codes in the Raspberry Pi documentation.
• LED_nPWR: This pin controls an LED that indicate's the board's power status, replicating the red LED on Raspberry Pi 5. When the board is powered but shut down, the LED lights up.

2.11. Fan control ( Fan_PWM and Fan_Tacho )

CM5 provides two pins for monitoring and controlling PWM fans, allowing for fan speed regulation and tachometer feedback.

• Fan_PWM: An open-collector output pin designed to drive a variety of PWM-controlled fans.
• Fan_Tacho: An input pin with internal pull-up to CM5_3.3V for reading tachometer output signals from many PWM fans.

During CM5 shutdown, power to the Fan_PWM signal is also stopped. If the fan is powered from a 5 V supply, the fan might still continue to run after power supply shutdown. To prevent this, turn off the supply to the fan simultaneously. For example, you could share power with the external USB ports controlled by VBUS_EN. Alternatively, you could use an open-collector buffer (such as a 74LVC1G07) powered from 5 V: connect its input to CM5_3.3V and wire the output in parallel with the PWM control line.

2.12. Power management and control

The following signals relate to power state management, power supply negotiation, and system-level control for CM5. Proper use of these signals ensures reliable power sequencing, system startup, shutdown, and battery-backed real-time clock (RTC) operation.

2.12.1. USB-C signals ( CC0 and CC1 )

The USB-C connector uses the CC0 and CC1 Configuration Channel (CC) signals to negotiate power delivery. On CM5, these signals enable the system to request up to 5 V at 5 A from the power source, ensuring efficient and safe power transfer over USB-C.

2.12.2. System control signals ( PMIC_EN , PWR_BUT , VBAT , nRPI_BOOT , and EEPROM_nWP )

Table 3 lists key control pins that govern system behaviour during startup, shutdown, and battery-powered operation.

3. Power

CM5 requires a regulated 5 V supply for operation. CM5 can also supply 600 mA at 3.3 V and 1.8 V to peripherals. The following sections describe the required power-up and power-down sequences, typical and maximum power consumption, and the capabilities of the on-board voltage regulators.

3.1. Power-up sequencing

The following list summarises the power-up conditions and sequencing necessary for proper power-up of CM5:

• No pins should be powered before the 5 V rail is active.
• For write-protection of the on-board boot EEPROM, the EEPROM_nWP pin must be low before power-up.
• To boot CM5 through USB, the RPI_nBOOT pin must be low within 2 ms after the 5 V rail rises.
• The 5 V rail should rise monotonically to at least 4.75 V and remain above this level during operation.
• The power-up sequence begins after the 5 V rail is above 4.75 V and the PMIC_EN signal rises.
• The power rails and signals rise in the following order:
  • 1. 5 V rises
  • 2. PMIC_EN rises
  • 3. CM5_+3.3V rises
  • 4. CM5_+1.8V rises at least 1 ms after CM5_+3.3V

3.2. Power-down sequencing

The following list summarises the recommended power-down procedure and considerations for CM5 to ensure safe shutdown and file system integrity:

• To ensure file system consistency, shut down the operating system before removing power.
• If controlled shutdown isn't possible, consider using file systems like btrfs, f2fs, or overlayfs, which can be enabled through raspi-config.
• After the operating system has shut down, the 5 V rail can be removed or the PMIC_EN pin can be taken low to put the CM5 into the lowest power mode.
• During the shutdown sequence, CM5_+1.8V will be discharged before the CM5_3.3V rail.

3.3. Power consumption

The exact power consumption of CM5 depends on the tasks being run on it. Typical values are summarised below:

• The lowest shutdown power consumption mode occurs when PMIC_EN is driven low, typically around 1.3 μA.
• With PMIC_EN high but software shut down, the typical consumption is about 3 μA.
• Idle power consumption is typically 400 mA, but this varies depending on the operating system.
• Operating power consumption is typically around 900 mA, but, this depends on the operating system and running tasks.

3.4. Regulator outputs

CM5 has built-in voltage regulators that provide 3.3 V ( CM5_+3.3V ) and 1.8 V ( CM5_+1.8V ) power rails. These regulators can each deliver up to 600 mA of current to external devices or peripherals connected to the board. The current drawn by connected devices from these regulators isn't included in the overall power consumption figures; the reported power usage only accounts for the board itself, not the extra peripherals powered through these regulators.

4. Specifications

This section includes technical descriptions of CM5's components and capabilities, including its dimensions, antenna, pinout, electrical specifications, and thermal characteristics.

4.1. Mechanical specifications

CM5 consists of a compact PCB and an optional wireless antenna. The physical features of CM5's components are summarised in Section 4.1.1. PCB dimensions, which includes information about the module size, PCB thickness, SoC height, and stacking height options. Antenna orientation and clearance requirements are summarised in Section 4.1.2. Wireless antenna.

For complete mechanical drawings and CAD models, see the CM5 design files, included in the official design data package. These files are provided to help designers visualise and plan their hardware; they are for reference only and might change over time as the board design is updated or revised.

4.1.1. PCB dimensions

CM5 is a compact 40 mm × 55 mm module. The bare module is 4.6 mm deep; when mounted, the total height becomes either 4.94 mm or 7.44 mm, depending on the chosen stacking height. The mechanical diagram in Figure 4 illustrates the approximate shape and dimensions of CM5 as viewed from the top.

Figure 4. Mechanical diagram of the Raspberry Pi Compute Module 5, viewed from the top, illustrating its dimensions, mounting holes, and component placement.

Key mechanical specifications of CM5 are as follows:

• Mounting: CM5 has four M2.5 mounting holes inset 3.5 mm from the module edge.
• Thickness: The PCB is 1.24 mm thick ± 10%.
• SoC height: BCM2712 SoC measures 2.2 mm ± 0.15 mm in height, including solder balls.
• Stacking height: Stacking height is determined by the connector used on the carrier board:
  • Amphenol connector part number, 10164227-1001A1RLF, results in a stacking height of 1.5 mm with no clearance underneath the CM5.
  • Amphenol connector part number, 10164227-1004A1RLF, results in a stacking height of 4.0 mm with 2.5 mm clearance underneath the CM5.

4.1.2. Wireless antenna

If using the on-board PCB antenna, we recommend adhering to the following guidelines:

• Position the on-board wireless antenna so that it faces the edge of the plastic enclosure.
• To avoid degrading wireless performance, ensure any nearby metal includes appropriate cut-outs.
• Maintain a minimum clearance of 10 mm around the PCB antenna; verify actual performance in the final enclosure.
• Don't place any metal, including ground planes, directly beneath the antenna.
• Provide a ground plane cut-out of at least 6.5 mm x 11 mm; ideally, 8 mm x 15 mm or larger.

If these requirements can't be met, wireless performance might be degraded, especially in the 2.4 GHz spectrum. We recommend using the external antenna where possible. For more information about the on-board PCB antenna, see Section 2.1. Wireless.

4.2. Pinout

CM5 includes 200 pins. Each pin is configured with default software function. Table 4 provides a summary of each pin's assignment, including signal names and descriptions.

4.2.1. Pin guidelines

The following instructions provide guidance for grounding, connector usage, voltage limits, and power rail considerations, and precautions against improper voltage application.

• Grounding: Always connect all ground pins on any connector in use. If none of the signals on the second connector (pins 101 to 200) are in use, then you may omit the connector (including its ground pins) to reduce costs; however, omitting the second connector can affect mechanical stability.
• GPIO voltage limits: GPIO pins 0 to 27 are the same as the 40-pin connector on Raspberry Pi 5. Depending on your signalling, their voltage must not exceed:
  • 3.3 V ( CM5_3.3V ) when using 3.3 V signalling.
  • 1.8 V ( CM5_1.8V ) when using 1.8 V signalling.
• Power rails: If you use power rails CM5_3.3V or CM5_1.8V to supply devices other than the GPIO reference voltage ( GPIO_VREF ), you must design for safe behaviour during unexpected power loss (for example, the 5 V line falls below 4.5 V):
  • If you use the 1.8 V rail ( CM5_1.8V ), ensure that the current draw goes down to zero (no load) if power suddenly drops.
  • If you use the 3.3 V rail ( CM5_3.3V ), ensure that the 3.3 V rail voltage never falls below the 1.8 V rail voltage if power suddenly drops. The 3.3 V rail voltage usually stays above the 1.8 V rail voltage during power-down, but verify your design. If the 3.3 V rail does fall below 1.8 V, add circuitry to disconnect 3.3 V devices to prevent damage.
• Reverse voltage: Don't apply reverse voltage on any pin. This means that when CM5 is powered-down or off, there must be no external voltage applied to any pin, otherwise CM5 might not power up again.

4.2.2. Differential pairs

We recommend that positive and negative (P/N) signals within a differential pair are length-matched to within 0.15 mm. Depending on the interface, the matching tolerance can be more relaxed between different pairs. For example, HDMI pair-to-pair matching can typically be within 25 mm, so no extra matching is required on a typical board.

100 Ω differential pair signal lengths

All 100 Ω differential pairs on CM5 are length-matched to less than 0.05 mm for P/N signals. We recommend that pairs are also matched on the interface board. On CM5, pair-to-pair length matching isn't always maintained because many interfaces don't require precise matching between different pairs. Table 5 lists the track-length differences within each differential pair group on CM5. A non-zero value represents how much longer in millimetres (mm) that track is when compared to the signal with zero length difference in the group.

90 Ω differential pair signal lengths

All 90 Ω differential pairs on CM5 (including USB pairs) are length-matched to less than 0.01 mm for P/N signals. USB 3.0 pairs don't require pair-to-pair matching within a port group. We recommend that pairs are also matched on the interface board. On CM5, pair-to-pair length matching isn't always maintained because many interfaces don't require precise matching between different pairs. Table 6 lists the track-length differences within each differential pair group on CM5. A non-zero value represents how much longer in millimetres (mm) that track is when compared to the signal with zero length difference in the group.

4.3. Electrical specifications

For safe and reliable operation of CM5, observe the following electrical parameters and limitations.

4.3.1. Absolute maximum ratings

Warning: Stresses above those listed in Table 7 can cause permanent damage to the device. This is a stress rating only; functional operation of the device under these or any other conditions above those listed in the operational sections of this specification isn't implied. Exposure to absolute maximum rating conditions for extended periods can affect device reliability.

Table 7 lists the absolute maximum ratings for key voltage parameters on the CM5. These values represent the limits beyond which damage to the device can occur and shouldn't be exceeded.

Note: V_{GPIO_VREF} is the GPIO bank voltage, which must be tied to either the 3.3 V or the 1.8 V rail of CM5.

4.3.2. DC characteristics

Table 8 details the DC electrical characteristics of the GPIO pins on CM5. It describes how the GPIO pins perform under different conditions (such as different reference voltages) and provides the expected ranges for each parameter (minimum, typical, and maximum values). For the electrical details of other interfaces in CM5, see Section 2. Interfaces.

4.3.3. Current consumption

Table 9 presents key current consumption characteristics for CM5 under various operating conditions. It details the typical shutdown, idle, operational, and RTC currents measured with different input voltages and control signals. Actual figures greatly depend on the end application.

4.4. Thermal characteristics

CM5 contains less metal in the PCB and fewer connectors than Raspberry Pi 5, which means that it has less passive heat sinking than Raspberry Pi 5.

The BCM2712 SoC on CM5 has built-in thermal management that reduces its clock speed to keep the SoC temperature below 85°C. To avoid overheating, the SoC might automatically throttle its performance in high ambient temperatures. If the SoC can't reduce its temperature enough through throttling, its case temperature can exceed 85°C. Any thermal management solution must ensure that the ambient temperatures of the other silicon components on the board stay within their safe operating range.

CM5's overall operating temperature range is from -20°C to +85°C (non-condensing). Wireless RF performance is best within -20°C to +75°C.

4.5. Mean time between failure (MTBF)

Mean time between failure (MBTF) measures how long, on average, each device is expected to operate before failure. Table 10 shows the MTBF for CM5 and CM5Lite, which varies depending on environmental conditions.

5. Troubleshooting

CM5 has a number of power-up and boot stages before it starts. If an error occurs at any of these stages, CM5 might fail to start or run as expected. The following sections help you to diagnose and resolve the issue by:

• Checking hardware power rails and signals for proper voltages and load behaviour.
• Verifying bootloader firmware operation and enabling diagnostics or alternate boot modes.
• Managing EEPROM firmware updates and write protection for boot reliability.

We also recommend avoiding known issues by ensuring the system software (firmware and kernel) are up to date. Keeping your firmware up to date can resolve many system issues and improve stability because newer versions contain improvements to the system. Similarly, new kernel releases often include important security patches and performance improvements.

5.1. Hardware power rails

CM5 requires stable power to start up. Check key power rails (5 V, 3.3 V, and 1.8 V) to verify power enable signals and identify any back-feeding caused by external devices or wiring.

1. Test the 5 V supply under load: Pull PMIC_EN low and apply an external 2 A load to the 5 V supply. The voltage should remain above 4.75 V (including noise), ideally, staying above 4.9 V.
2. Check for back-feeding on 3.3 V and 1.8 V rails: Remove the external 2 A load, but keep PMIC_EN pulled low. If the voltage for 3.3 V and 1.8 V exceeds 200 mV, there might be an external power path back-feeding the board, possibly through digital pins such as Ethernet.
3. Check PMIC_EN goes high: Remove the pull-down on PMIC_EN and then check that PMIC_EN now goes high; measure the voltage on this pin or check its logic state to confirm it goes high.
4. Confirm that the voltage rails rise correctly:
   • Check the 3.3 V supply rises to more than 3.15 V. If it doesn't, this suggests there is too much load on the 3.3 V rail.
   • Check the 1.8 V supply rises to more than 1.71 V. If it doesn't, this suggests there is too much load on the 1.8 V rail.
5. Check the activity LED ( LED_nACT ) to verify the boot process: The LED should oscillate to indicate booting; check it isn't flashing an error code. To decode error code patterns, see the LED Flash codes in the Raspberry Pi documentation.

5.2. Bootloader firmware

The bootloader firmware manages the initial startup of CM5. If your CM5 fails to start correctly, verify bootloader operation, then enable diagnostic modes. To verify bootloader operation:

• Connect an HDMI cable. The bootloader has started and is running correctly if the HDMI diagnostics screen appears.
• Connect a USB serial cable to GPIO pins 14 and 15. This allows you to receive bootloader output logs (through UART), which help verify what stage the bootloader is at and diagnose any issues. For more information, see Configure UARTs.

If the bootloader isn't running as expected, enable diagnostic modes: short the nRPIBOOT pin to ground to force USB boot mode. The CM5IO board has a jumper for nRPIBOOT that you can use to enable different boot modes (for example, network boot) and UART logging. For more information, see Flash an image to a Compute Module.

5.3. EEPROM management and firmware updates

For reliable startup and system stability on your CM5, keep the bootloader EEPROM up to date, including correct management of write protection.

• Check EEPROM write-protection: The on-board EEPROM can be write-protected by shorting the EEPROM_nWP pin to ground. The CM5IO board provides a jumper for EEPROM_nWP to enable or disable write protection.
• If necessary, update or repair EEPROM: CM5 won't run recovery.bin from the eMMC (or SD card on CM5Lite); update or repair the bootloader EEPROM on your CM5 through usbboot or self-update. Ensure write protection is disabled before attempting to update the EEPROM. For more information, see Boot EEPROM.

6. Ordering information

CM5 comes in a range of variants distinguished by wireless capability, RAM size, and eMMC storage capacity. Each CM5 variant is identified by a unique order code (part number). The available product variants are detailed in the tables below. Custom configurations can also be arranged to suit specific requirements.

6.1. Order quantity and packaging

You can order a specific number of one or more CM5 devices that will arrive individually boxed, or you can make a bulk order that will come in a single shipper. Small quantities supplied in individual cardboard boxes have an internal ESD coating so that a separate ESD bag isn't required. This packaging is recyclable to reduce waste.

6.2. Part number codes

Table 11 explains the structure of part numbers for CM5 variants. It details how the model, wireless capability, RAM size, and eMMC storage capacity are encoded within the part number.

6.3. Product variants

Table 12 shows available variants for CM5 by part number, detailing wireless support, RAM size, eMMC storage capacity and RPL numbers. Other configurations can be custom ordered.

Appendix A. Test Points

CM5 contains test points: pins on the board that you can use to power the board, program it, or debug it without needing to use the main 100-pin connectors.

A.1. Test point map

Table 13 lists the coordinates (X and Y) of tests points on CM5 and what each test point is used for. Most signals replicate pins on the 100-pin connectors of CM5.

A.2. Test point connections for power and programming

Use the following test points to power, program, and boot CM5 without using the main 100-pin connectors:

• Power (Vin): Use test points TP1 and TP78 to supply 5 V power to CM5. At a minimum, connect ground to test points TP26 , TP61 , and TP8 . If possible, use more ground points.
• Debug UART: Test points TP35 ( TX ) and TP36 ( RX ) provide serial debug communication lines. Use TP46 for ground. This is useful for programming and debugging during boot.
• Raspberry Pi boot mode: Pins TP65 and TP66 serve as USB data lines. Connect TP7 as ground, and also ground TP16 ( nRPI_BOOT ) to force the board into Raspberry Pi boot mode.
• Ethernet boot: Connect test points TP69 and TP76 to an external Ethernet MagJack (the Ethernet connector with magnetics).

Appendix B. CM4 and CM5 differences

This section describes the differences between Raspberry Pi Compute Module 5 (CM5) and the previous module, Raspberry Pi Compute Module 4 (CM4).

B.1. Pinout changes

CM5 introduces specific pin-level changes from CM4, including updated pin functions and signal repurposing to support new hardware features.

B.1.1. Per-pin differences

Table 14 compares the exact per-pin changes between CM4 and CM5. It highlights updated functions and signal repurposing to reflect the new hardware capabilities and interfaces.

B.1.2. Summary of functional and hardware changes

In addition to the above, there have been broader design changes. The following list summarises the functional consequences of these changes, as well as the impact of some of the above pin changes:

• Connectors: The connectors have changed brand and have been tested to higher currents to support CM5.
• Thickness: The PCB for CM5 is 0.04 mm thicker than CM4, but the main processor is thinner.
• PCIe clock: PCIe CLK signals are no longer capacitively coupled.
• ESD protection: CM4 has extra ESD protection on the HDMI, SDA, SCL, HPD, and CEC signals. This is removed from CM5.
• Dual-purpose DSI and CSI signals: CAM1 and DSI1 signals became dual-purpose and can be used for either a CSI camera or a DSI display. For more information, see Section 2.5. Video and display interfaces.
• USB ports: For more information about USB ports on CM5, see Section 2.4. USB interfaces.
  • The CAM0 port (pins 128 to 142) on CM4 is a USB 3.0 port on CM5.
  • The DSI0 port (pins 157 to 171) on CM4 is a USB 3.0 port on CM5.
• VBUS enable pin: Pin 111 ( VDAC_COMP on CM4) has been repurposed as a VBUS enable pin controlling power to the two USB 3.0 ports on CM5. Power to the USB 3.0 ports is enabled when the pin is active high.
• PD CC signals: Pins 94 and 96, the two ADC channels on CM4, have become the Power Delivery (PD) Configuration Channel (CC) signals within the USB-C connector.

B.2. Track lengths

CM5 has updated HDMI and Ethernet track lengths compared to CM4. These changes improve pair-to-pair skew and remain well within tolerances, so no functional impact is expected for previous Compute Modules.

• HDMI0: P/N pairs remain length-matched, but the skew between pairs is now less than 1 mm. This is unlikely to make a difference because the skew between pairs can be up to 25 mm on previous Compute Modules.
• HDMI1: P/N pairs remain length-matched, but the skew between pairs is now less than 5 mm. This is unlikely to make a difference because the skew between pairs can be up to 25 mm on previous Compute Modules.
• Ethernet: P/N pairs remain length-matched, but the skew between pairs is now less than 4 mm. This is unlikely to make a difference because the skew between pairs can be up to 12 mm on previous Compute Modules.

B.3. Power budget

CM5 delivers significantly more performance than CM4, and therefore consumes more power. Power supply designs should accommodate 5 V at up to 2.5 A. If this creates an issue with an existing board design, lowering the CPU clock rate can reduce the peak power consumption.

For more information about power requirements for CM5, see Section 3.3. Power consumption.

Appendix C. Documentation history