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User Guide for GOWIN models including: GW1NRF Series Bluetooth FPGA Products Package and Pinout, GW1NRF Series, Bluetooth FPGA Products Package and Pinout, FPGA Products Package and Pinout, Products Package and Pinout, Package and Pinout, Pinout
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DocumentDocumentGW1NRF series of Bluetooth FPGA Products Package & Pinout User Guide UG893-1.0.1E, 12/15/2022 Copyright © 2022 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. is the trademark of Guangdong Gowin Semiconductor Corporation and are registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders. No part of this document may be reproduced or transmitted in any form or by any denotes, electronic, mechanical, photocopying, recording or otherwise, without the prior written consent of GOWINSEMI. Disclaimer GOWINSEMI assumes no liability and provides no warranty (either expressed or implied) and is not responsible for any damage incurred to your hardware, software, data, or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms and Conditions of Sale. GOWINSEMI may make changes to this document at any time without prior notice. Anyone relying on this documentation should contact GOWINSEMI for the current documentation and errata. Revision History Date Version 11/12/2019 1.0E 12/15/2022 1.0.1E Description Initial version published. Package diagrams updated. The note of Table 2-4 "Definition of the Pins in the GW1NRF series of Bluetooth FPGA products" in Chapter 2.5 "Pin Definitions" added. Contents Contents Contents ............................................................................................................... i List of Figures ..................................................................................................... ii List of Tables...................................................................................................... iii 1 About This Guide ............................................................................................. 1 1.1 Purpose .............................................................................................................................. 1 1.2 Related Documents ............................................................................................................ 1 1.3 Terminology and Abbreviations........................................................................................... 1 1.4 Support and Feedback ....................................................................................................... 2 2 Overview........................................................................................................... 3 2.1 PB-Free Package ............................................................................................................... 3 2.2 Package, Max. User I/O Information, and LVDS Paris ....................................................... 3 2.3 Power Pin ........................................................................................................................... 3 2.4 Pin Quantity ........................................................................................................................ 4 2.4.1 Quantity of GW1NRF-4B Pins ......................................................................................... 4 2.5 Pin Definitions ..................................................................................................................... 5 2.6 I/O BANK Introduction ........................................................................................................ 7 3 View of Pin Distribution .................................................................................. 8 3.1 View of GW1NRF-4B Pins Distribution............................................................................... 8 3.1.1 View of QN48 Pins Distribution ....................................................................................... 8 3.1.2 View of QN48E Pins Distribution ..................................................................................... 9 4 Package Diagrams......................................................................................... 10 4.1 QN48 Package Outline (6mm x 6mm).............................................................................. 10 4.2 QN48E Package Outline (6mm x 6mm) ........................................................................... 11 UG893-1.0.1E i List of Figures List of Figures Figure 2-1 GW1NRF series of Bluetooth FPGA products I/O Bank Distribution ............................... 7 Figure 3-1 View of GW1NRF-4B QN48 Pins Distribution (Top View) ................................................ 8 Figure 3-2 View of GW1NRF-4B QN48E Pins Distribution (Top View) ............................................. 9 Figure 4-1 Package Outline QN48..................................................................................................... 10 Figure 4-2 Package Outline QN48E .................................................................................................. 11 UG893-1.0.1E ii List of Tables List of Tables Table 1-1 Abbreviation and Terminology ............................................................................................ 1 Table 2-1 Package, Max. User I/O Information, and LVDS Paris ...................................................... 3 Table 2-2 Other Pins in the GW1NRF Series .................................................................................... 3 Table 2-3 Quantity of GW1NRF-4B Pins ........................................................................................... 4 Table 2-4 Definition of the Pins in the GW1NRF series of Bluetooth FPGA products ....................... 5 Table 3-1 Other pins in GW1NRF-4B QN48 ...................................................................................... 9 Table 3-2 Other pins in GW1NRF-4B QN48E.................................................................................... 9 UG893-1.0.1E iii 1 About This Guide 1.1 Purpose 1 About This Guide 1.1 Purpose This manual contains an introduction to the GW1NRF series of Bluetooth FPGA products together with a definition of the pins, list of pin numbers, distribution of pins, and package diagrams. 1.2 Related Documents The latest user guides are available on the GOWINSEMI Website. You can find the related documents at www.gowinsemi.com: 1. DS891, GW1NRF series of Bluetooth FPGA products Data Sheet 2. UG290, Gowin FPGA Products Programming and Configuration User Guide 3. UG893, GW1NRF series of Bluetooth FPGA products Package and Pinout 4. UG892, GW1NRF-4B Pinout 1.3 Terminology and Abbreviations The terminology and abbreviations used in this manual are as shown in Table 1-1 below. Table 1-1 Abbreviation and Terminology Terminology and Abbreviations FPGA SIP GPIO QN48 QN48E Full Name Field Programmable Gate Array System in Package Gowin Programmable IO QFN48 QFN48E UG893-1.0.1E 1(11) 1 About This Guide 1.4 Support and Feedback 1.4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly by the following ways. Website: www.gowinsemi.com E-mail: support@gowinsemi.com UG893-1.0.1E 2(11) 2 Overview 2.1 PB-Free Package 2 Overview The GW1NRF series of FPGA products are the first generation products in the LittleBee® family and represent one form of SoC FPGA. The GW1NRF series of FPGA products integrate 32 bits hardcore processor and support Bluetooth 5.0 Low Energy radio. They have abundant logic units, IOs, built-in B-SRAM and DSP resources, power management module, and security module. The GW1NRF series provides low power consumption, instant on, low cost, non-volatile, high security, various packages, and flexible usage. 2.1 PB-Free Package The GW1NRF series of Bluetooth FPGA products are PB free in line with the EU ROHS environmental directives. The substances used in the GW1NRF series of Bluetooth FPGA products are in full compliance with the IPC-1752 standards. 2.2 Package, Max. User I/O Information, and LVDS Paris Table 2-1 Package, Max. User I/O Information, and LVDS Paris Package Pitch (mm) Size (mm) GW1NRF-4B QN48 0.4 6 x 6 25(4) QN48E 0.4 6 x 6 25(4) Note! In this manual, abbreviations are employed to refer to the package types. See 1.3Terminology and Abbreviations. See GW1NRF series of Bluetooth FPGA Products Data Sheet for more details. The JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The data in this table is when the loaded four JTAG pins (TCK, TDI, TDO, and TMS) are used as I/O; 2.3 Power Pin Table 2-2 Other Pins in the GW1NRF Series VCC VCCO3 VCCO0 VCCX VCCO1 VSS VCCO2 UG893-1.0.1E 3(11) 2 Overview 2.4 Pin Quantity 2.4 Pin Quantity 2.4.1 Quantity of GW1NRF-4B Pins Table 2-3 Quantity of GW1NRF-4B Pins Pin Type GW1NRF-4B QN48 QN48E I/O Single end / Differential pair / LVDS[1] Max. User I/O[2] BANK0 BANK1 BANK2 BANK3 9/4/0 4/1/1 8/4/3 4/1/0 25 9/4/0 4/1/1 8/4/3 4/1/0 25 Differential Pair 10 10 True LVDS output 4 4 VCC 2 2 VCCX VCCO0/VCCO3[3] VCCO1/VCCO2[3] 1 1 1 1 1 1 VSS 2 1 MODE0 0 0 MODE1 0 0 MODE2 0 0 JTAGSEL_N 1 1 Note! [1] The number of single end/ differential/LVDS I/O includes CLK pins and download pins. [2] The JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The data in this table is when the loaded four JTAG pins (TCK, TDI, TDO, and TMS) are used as I/O; When mode [2:0] = 001, JTAGSEL_N and the four JTAG pins (TCK, TDI, TDO, and TMS) can be used as GPIO simultaneously, and the Max. user I/O plus one. [3] Pin multiplexing. UG893-1.0.1E 4(11) 2Overview 2.5Pin Definitions 2.5 Pin Definitions The location of the pins in the GW1NRF series of Bluetooth FPGA products varies according to the different packages. Table 2-4 provides a detailed overview of user I/O, multi-function pins, dedicated pins, and other pins. Table 2-4 Definition of the Pins in the GW1NRF series of Bluetooth FPGA products Pin Name I/O Max. User I/O IO[End][Row/Column Number][A/B] I/O Multi-Function Pins IO[End][Row/Column Number][A/B]/MMM RECONFIG_N I, internal weak pull-up READY I/O DONE I/O FASTRD_N /D3 I/O MCLK /D4 I/O MCS_N /D5 I/O MI /D7 I/O MO /D6 I/O SSPI_CS_N/D0 I/O Description [End] indicates the pin location, including L(left) R(right) B(bottom), and T(top) [Row/Column Number] indicates the pin Row/Column number. If [End] is T(top) or B(bottom), the pin indicates the column number of the corresponding CFU. If [End] is L(left) or R(right), the pin indicates the Row number of the corresponding CFU. [A/B] indicates differential signal pair information. /MMM represents one or more of the other functions in addition to being general purpose user I/O. These pins can be used as user I/O when the functions are not used. Start new GowinCONFIG mode when low pulse High level indicates the device can be programmed and configured currently Low level indicates the device cannot be programmed and configured currently High level indicates successful program and configure Low level indicates incomplete or failed to program and configure In MSPI mode, FASTRD_N is used as Flash access speed port. Low indicates high-speed Flash access mode; high indicates regular Flash access mode. Data port D3 in CPU mode Clock output MCLK in MSPI mode Data port D4 in CPU mode Enable signal MCS_N in MSPI mode, active-low Data port D5 in CPU mode MISO in MSPI mode: Master data input/Slave data output Data port D7 in CPU mode MISO in MSPI mode: Master data output/Slave data input Data port D6 in CPU mode Enable signal SSPI_CS_N in SSPI mod, UG893-1.0.1E 5(11) 2 Overview 2.5 Pin Definitions Pin Name I/O SO /D1 I/O SI /D2 I/O TMS I, internal weak pull-up TCK I TDI TDO JTAGSEL_N SCLK DIN DOUT I, internal weak pull-up O I, internal weak pull-up I I, internal weak pull-up O CLKHOLD_N I, internal weak pull-up WE_N I GCLKT_[x] I GCLKC_[x] I LPLL_T_fb/RPLL_T_fb LPLL_C_fb/RPLL_C_fb LPLL_T_in/RPLL_T_in LPLL_C_in/RPLL_C_in MODE2 MODE1 MODE0 Other Pins NC VSS VCC I I I I I, internal weak pull-up I, internal weak pull-up I, internal weak pull-up NA NA NA VCCO# NA Description active-low, Internal Weak Pull Up Data port D0 in CPU mode MISO in MSPI mode: Master data input/Slave data output Data port D1 in CPU mode MISO in MSPI mode: Master data output/Slave data input Data port D2 in CPU mode Serial mode input in JTAG mode Serial clock input in JTAG mode, which needs to be connected with 4.7 K drop-down resistance on PCB Serial data input in JTAG mode Serial data output in JTAG mode Select signal in JTAG mode, active-low Clock input in SSPI, SERIAL, and CPU mode Input data in SERIAL mode Output data in SERIAL mode High level, SCLK will be connected internally in SSPI mode or CPU mode Low level, SCLK will be disconnected from SSPI mode or CPU mode Select data input/output of D[7:0] in CPU mode Global clock input pin, T(True), [x]: global clock No. Differential input pin of GCLKT_[x], C(Comp), [x]: global clock No.[1] Left/Right PLL feedback input pins, T(True) Left/Right PLL feedback input pins, C(Comp) Left/Right PLL clock input pin, T(True) Left/Right PLL clock input pin, C(Comp) GowinCONFIG modes selection pin. GowinCONFIG modes selection pin. GowinCONFIG modes selection pin. Reserved. Ground pins Power supply pins for internal core logic. Power supply pins for the I/O voltage of I/O BANK#. UG893-1.0.1E 6(11) 2 Overview 2.6 I/O BANK Introduction Pin Name VCCX I/O Description NA Power supply pins for auxiliary voltage. Note! [1] When the input is single-ended, GCLKC_[x] pin is not a global clock. 2.6 I/O BANK Introduction There are four I/O Banks in the GW1NRF series of FPGA products. The I/O BANK Distribution of the GW1NRF series of Bluetooth FPGA products is as shown in Figure 2-1. Figure 2-1 GW1NRF series of Bluetooth FPGA products I/O Bank Distribution I/O BANK0 GW1NRF I/O BANK1 I/O BANK3 UG893-1.0.1E I/O BANK2 This manual provides an overview of the distribution view of the pins in the GW1NRF series of Bluetooth FPGA products. The four I/O Banks that form the GW1NRF series of Bluetooth FPGA products are marked with four different colors. Various symbols are used for the user I/O, power, and ground. The various symbols and colors used for the various pins are defined as follows: " " denotes the I/O in BANK0. The filling color changes with the BANK; " " denotes the I/O in BANK1. The filling color changes with the BANK; " " denotes the I/O in BANK2. The filling color changes with the BANK; " " denotes the I/O in BANK3. The filling color changes with the BANK; " " denotes VCC, VCCX, and VCCO. The filling color does not change; " " denotes VSS, the filling color does not change; " " denotes NC; " " denotes BLE, the filling color does not change. 7(11) 3 View of Pin Distribution 3 View of Pin Distribution 3.1 View of GW1NRF-4B Pins Distribution 3.1.1 View of QN48 Pins Distribution Figure 3-1 View of GW1NRF-4B QN48 Pins Distribution (Top View) UG893-1.0.1E 8(11) 3 View of Pin Distribution 3.1 View of GW1NRF-4B Pins Distribution Table 3-1 Other pins in GW1NRF-4B QN48 VCC VCCX VCCO0/VCCO3 VCCO1/VCCO2 VSS 11,37 36 1 25 26,2 3.1.2 View of QN48E Pins Distribution Figure 3-2 View of GW1NRF-4B QN48E Pins Distribution (Top View) Table 3-2 Other pins in GW1NRF-4B QN48E VCC VCCX VCCO0/VCCO3 VCCO1/VCCO2 VSS 11,37 36 1 25 26 UG893-1.0.1E 9(11) 4 Package Diagrams 4 Package Diagrams 4.1 QN48 Package Outline (6mm x 6mm) Figure 4-1 Package Outline QN48 TOP VIEW SIDE VIEW UG893-1.0.1E EXPOSED THERMAL PAD ZONE BOTTOM VIEW SYMBOL A A1 b c D D2 e Ne Nd E E2 L h MILLIMETER MIN NOM MAX 0.70 0.75 0.80 0 0.02 0.05 0.15 0.20 0.25 0.10 0.15 0.20 5.90 6.00 6.10 4.10 4.20 4.30 0.40BSC 4.40BSC 4.40BSC 5.90 6.00 6.10 4.10 4.20 4.30 0.35 0.40 0.45 0.30 0.35 0.40 10(11) 4 Package Diagrams 4.2 QN48E Package Outline (6mm x 6mm) 4.2 QN48E Package Outline (6mm x 6mm) Figure 4-2 Package Outline QN48E EXPOSED THERMAL PAD ZONE BOTTOM VIEW SYMBOL A A1 b c D D2 e Ne Nd E E2 L h MILLIMETER MIN NOM MAX 0.75 0 8.5 0.85 __ 0.02 0.05 0.15 0.20 0.25 0.18 0.20 0.23 5.90 6.00 6.10 4.10 4.20 4.30 0.40 BSC 4.40BSC 4.40BSC 5.90 4.10 6.00 4.20 6.10 4.30 0.35 0.40 0.45 0.30 0.35 0.40 UG893-1.0.1E 11(11)