Quanta PL3 Block Diagram

System Overview

This document provides a detailed block diagram of the Quanta PL3 motherboard, illustrating the interconnection of key components. The primary processor is an Intel Merom (35W) CPU, connected via the Front Side Bus (FSB) to the Crestline GM chipset. The Crestline GM chipset integrates various controllers and interfaces, including DDRII memory support, PCI-Express, DMI, SATA, and USB.

Key components and their connections include:

• CPU: Intel Merom (35W)
• Chipset: Crestline GM
• Memory: DDRII SODIMM slots
• Graphics: Integrated graphics within the Crestline GM
• Storage: SATA HDD connector, IDE ODD connector
• Connectivity: USB ports (0, 2, 5, 6), 4-in-1 card reader, PCIE LAN (M88E8039), RJ45 connector
• Audio: CODEC (CX20549), MAX9789A amplifier
• Display: CRT, LCD (WXGA 15.4) via LVDS
• Clock Generator: ICS9LPR363
• Power Management: Various voltage rails (VCC_CORE, VCC1.5, VCC1.05, VCC1.25, 1.8VSUS, 3VPCU, 5VPCU, etc.)
• Other Interfaces: LPC, Mini PCIE, SATA/ODD Connector, PCIE LAN, Audio Amplifier, CONEXTANT MDC, Keyboard/USB, TP/LED/SW, KBC (PC8769, PC87541), CPU CORE (MAX8736), Battery Charger, Battery Connector.

Power Rails and Sequence

The document details various voltage rails essential for system operation, including VCC_CORE, VCC1.5, VCC1.05, VCC1.25, 1.8VSUS, 3VPCU, 5VPCU, and others. A power-on sequence is also illustrated, showing the timing of key signals like ACIN, NBSWON#, PWRBTN#, RVCC_ON, SUSON, SUSC#, and VR_ON.

Component Details and Interfaces

Specific sections provide detailed schematics for various subsystems:

• Clock Generator: Details the ICS9LPR363 clock generator, including its connections to the CPU, chipset, and other peripherals, along with BSEL frequency select tables.
• CPU Power: Illustrates the power delivery network for the Intel Merom processor, including VCC_CORE, VCC1.05, VCC1.5, and sense pins.
• GMCH (VGA, DMI): Shows the Graphics and Memory Controller Hub (GMCH) connections, including DMI interface, PCI-Express lanes, VGA signals (CRT, LVDS), and DDR2 memory interface signals.
• GMCH DDR2 SD-DIMM: Provides detailed pinouts and connections for DDR2 SDRAM modules, including address, data, control, and clock signals.
• ICH8M (Host, PCIE, GPIO, Power): Details the Input/Output Controller Hub (ICH8M) and its interfaces, including Host Bus, PCI-Express, GPIO, and power management signals.
• ICH8-PCI E: Focuses on the PCI-Express interface of the ICH8M, including USB ports, LAN, and PCI routing.
• ICH8-POWER: Outlines the power distribution and management for the ICH8M.
• ICH8-GPIO: Details the General Purpose Input/Output pins of the ICH8M.
• PANEL LCD CRT: Shows the circuitry for the CRT port, LCD connector, panel VCC control, and lid switch.
• PCIE LAN 10/100M MARVELL 88E8039: Provides the schematic for the Marvell 88E8039/88E8055 Gigabit Ethernet controller.
• SATA/PATA: Includes schematics for ODD (Optical Disk Drive), SATA HDD, and HDD/ODD/cardreader LED connections.
• Audio codec (CX20549): Details the connections for the audio codec and external microphone.
• AMP MAX9789A: Shows the schematic for the audio amplifier.
• MODEM DAA: Illustrates the Data Access Arrangement (DAA) circuitry for the modem.
• EC-PC8769: Details the Embedded Controller (EC) functions, including keyboard, SMBus, PS/2, A/D, D/A, GPIO, SPI, IR, FIU, and Timer interfaces.
• SYSTEM 5V/3V: Depicts the power supply circuitry for 5V and 3V rails.
• CPU CAORE (6262A): Shows the power delivery for the CPU core using the ISL6262A controller.
• DDR2 1.8V(TP1116): Details the 1.8V power supply for DDR2 memory.
• DISCHARGE/1.5V/2.5V: Illustrates discharge circuitry and 1.5V/2.5V power supplies.
• TP/SW: Includes test points and switch circuitry.

Strap Settings

The document includes a strap table that defines various configuration options for the GMCH, such as FSB frequency selection, DMI mode, PCI Express settings, and SDVO presence. These straps are sampled with respect to the GMCH Power OK (PWROK) signal.

Layout Notes

Throughout the schematics, layout notes provide guidance on component placement and trace routing to ensure optimal signal integrity and performance. These include recommendations for decoupling capacitor placement, trace impedance, and minimizing noise coupling.