Owner's Manual for ON Semiconductor models including: FDD9409L-F085 Channel Logic Level Power Trench, FDD9409L-F085, Channel Logic Level Power Trench, Logic Level Power Trench, Level Power Trench, Power Trench
FDD9409L-F085 ON Semiconductor - РКС Компоненти - РАДІОМАГ
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DocumentDocumentFDD9409L-F085 N-Channel Logic Level PowerTrench® MOSFET FDD9409L-F085 N-Channel Logic Level PowerTrench® MOSFET 40 V, 90 A, 2.6 m N Features IG Typical RDS(on) = 2.1 m at VGS = 10V, ID = 80 A D ES Typical Qg(tot) = 52 nC at VGS = 10V, ID = 80 A D UIS Capability E RoHS Compliant EW Qualified to AEC Q101 U N Applications OR i Automotive Engine Control IND F sem ION PowerTrain Management E n T Solenoid and Motor Drivers T D o A Electronic Steering EN UR RM Integrated Starter/Alternator N M O O Distributed Power Architectures and VRM O OM T Y INF Primary Switch for 12V Systems D D G G S DTO-P-2A5K2 (TO-252) S EC AC R MOSFET Maximum Ratings TJ = 25°C unless otherwise noted. C T R ONT E FO Symbol Parameter IS O C IV VDSS N E T VGS D E IS EAS NTA ID Drain-to-Source Voltage Gate-to-Source Voltage Drain Current - Continuous (VGS=10) (Note 1) Pulsed Drain Current IC L SE EAS Single Pulse Avalanche Energy EV P E Power Dissipation D PR PD Derate Above 25oC IS E TJ, TSTG Operating and Storage Temperature TH R RJC Thermal Resistance, Junction to Case TC = 25°C TC = 25°C (Note 2) Ratings 40 ±20 90 See Figure 4 33.7 150 1 -55 to + 175 1 Units V V A mJ W W/oC oC oC/W RJA Maximum Thermal Resistance, Junction to Ambient (Note 3) 52 oC/W Notes: 1: Current is limited by bondwire configuration. 2: Starting TJ = 25°C, L = 15uH, IAS = 67A, VDD = 40V during inductor charging and VDD = 0V during time in avalanche. 3: RJA is the sum of the junction-to-case and case-to-ambient thermal resistance, where the case thermal reference is defined as the solder mounting surface presented here is of the based drain pins. RJC is on mounting on a 1 guaranteed by design, in2 pad of 2oz copper. while RJA is determined by the board design. The maximum rating Package Marking and Ordering Information Device Marking FDD9409L Device FDD9409L-F085 Package D-PAK(TO-252) Reel Size 13" Tape Width 16mm Quantity 2500units ©2016 Semiconductor Components Industries, LLC. May-2024, Rev. 3 Publication Order Number: FDD9409L-F085/D Downloaded from Arrow.com. FDD9409L-F085 N-Channel Logic Level PowerTrench® MOSFET Electrical Characteristics TJ = 25°C unless otherwise noted. Symbol Parameter Off Characteristics Test Conditions Min. Typ. Max. Units BVDSS Drain-to-Source Breakdown Voltage ID = 250A, VGS = 0V 40 IDSS Drain-to-Source Leakage Current VDS=40V, TJ = 25oC - VGS = 0V TJ = 175oC (Note 4) - IGSS Gate-to-Source Leakage Current VGS = ±20V - On Characteristics - - V - 1 A - 1 mA - ±100 nA VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250A 1.0 1.8 3.0 V N RDS(on) Drain to Source On Resistance D ESIG Dynamic Characteristics ID = 80A, VGS= 4.5V - ID = 80A, TJ = 25oC - VGS= 10V TJ = 175oC (Note 4) - 3.0 4.4 m 2.1 2.6 m 3.7 4.6 m E W D Ciss U NE Coss R Crss O i Rg IND F sem ION Qg(ToT) E n T Qg(th) T D o A Qgs EN UR RM Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance Total Gate Charge Threshold Gate Charge Gate-to-Source Gate Charge Gate-to-Drain "Miller" Charge NMM YO FO Switching Characteristics VDS = 20V, VGS = 0V, f = 1MHz - 3360 - pF - 1080 - pF - 42 - pF f = 1MHz - 2.2 - VGS = 0 to 10V VDD = 32V - VGS = 0 to 2V ID = 80A - - 52 68 nC 7 - nC 11 - nC - 8 - nC O O T IN ton C REC TAC OR td(on) N F tr T O E td(off) IS NO C IV tf IS E AT toff Turn-On Time Turn-On Delay Rise Time Turn-Off Delay Fall Time Turn-Off Time D E EAS NT Drain-Source Diode Characteristics VDD = 20V, ID = 80A, VGS = 10V, RGEN = 6 - - 47 ns - 10 - ns - 13 - ns - 36 - ns - 10 - ns - - 70 ns EVIC PL RESE VSD Source-to-Drain Diode Voltage IS D EP trr Reverse-Recovery Time TH R Qrr Reverse-Recovery Charge ISD =80A, VGS = 0V ISD = 40A, VGS = 0V IF = 80A, dISD/dt = 100A/s VDD = 32V - - 1.25 V - - 1.2 V - 59 77 ns - 57 74 nC Note: 4: The maximum value is specified by design at TJ = 175°C. Product is not tested to this condition in production. Downloaded from Arrow.com. www.onsemi.com 2 FDD9409L-F085 N-Channel Logic Level PowerTrench® MOSFET Typical Characteristics ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 CURRENT LIMITED 180 BY SILICON VGS = 10V 1.0 150 CURRENT LIMITED 0.8 BY PACKAGE 120 0.6 90 0.4 60 0.2 30 IGN 0.0 D ES 0 25 50 75 100 125 150 175 TC, CASE TEMPERATURE(oC) D Figure 1. Normalized Power Dissipation vs. Case E W Temperature NORMALIZED THERMAL IMPEDANCE, ZJC U NE 2 DUTY CYCLE - DESCENDING ORDER R i 1 O D = 0.50 IN F em N 0.20 D s IO 0.10 E n T 0.05 T D o A 0.02 N R M 0.01 0.1 ONOMMET YOUINFOR SINGLE PULSE 0 25 50 75 100 125 150 175 200 TC, CASE TEMPERATURE(oC) Figure 2. Maximum Continuous Drain Current vs. Case Temperature PDM t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC C REC TAC OR 0.01 N F 10-5 10-4 10-3 10-2 10-1 100 101 T O E t, RECTANGULAR PULSE DURATION(s) IS O C IV Figure 3. Normalized Maximum Transient Thermal Impedance IS N SE TAT 2000 THISDDEVICERPELPERAESEN 1000 VGS = 10V TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 175 - TC 150 100 IDM, PEAK CURRENT (A) SINGLE PULSE 10 10-5 10-4 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION(s) Figure 4. Peak Current Capability Downloaded from Arrow.com. www.onsemi.com 3 FDD9409L-F085 N-Channel Logic Level PowerTrench® MOSFET Typical Characteristics 1000 100 400 100 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 100us 10 STARTING TJ = 25oC OPERATION IN THIS AREA MAY BE LIMITED BY PACKAGE 1ms 10 STARTING TJ = 150oC 1 OPERATION IN THIS AREA MAY BE SINGLE PULSE 10ms LIMITED BY rDS(on) TJ = MAX RATED 100ms N 0.1 SIG 0.1 TC = 25oC 1 10 100 200 VDS, DRAIN TO SOURCE VOLTAGE (V) D DE Figure 5. Forward Bias Safe Operating Area ID, DRAIN CURRENT (A) UER NEW 200 O i PULSE DURATION = 250s IN F m N DUTY CYCLE = 0.5% MAX D se IO 160 VDD = 5V T NDE R on MAT 120 TJ = 25oC IS, REVERSE DRAIN CURRENT (A) NMME YOU FOR 80 O O T IN TJ = 175oC C C R 40 C RE TA O TJ = -55oC T N F 0 O E 1 2 3 4 5 IS NO C IV VGS, GATE TO SOURCE VOLTAGE (V) IS SE TAT Figure 7. Transfer Characteristics 1 0.001 0.01 0.1 1 10 100 tAV, TIME IN AVALANCHE (ms) NOTE: Refer to On Semiconductor Application Notes AN7514 and AN7515 Figure 6. Unclamped Inductive Switching Capability 200 100 VGS = 0 V 10 TJ = 175 oC 1 TJ = 25 oC 0.1 0.0 0.2 0.4 0.6 0.8 1.0 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 8. Forward Diode Characteristics DEVICE PLERAESEN 200 200 D P 250s PULSE WIDTH 180 HIS RE 150 Tj=25oC 160 VGS 250s PULSE WIDTH Tj=175oC T 10V Top 140 VGS 6V 5V 120 10V Top 6V 100 4.5V 4V 100 5V 4.5V 3.5V 3V Bottom 80 4V 3.5V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 60 3V Bottom 50 40 20 0 0 1 2 3 4 5 VDS, DRAIN TO SOURCE VOLTAGE (V) 0 0 1 2 3 4 5 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 9. Saturation Characteristics Figure 10. Saturation Characteristics www.onsemi.com 4 Downloaded from Arrow.com. FDD9409L-F085 N-Channel Logic Level PowerTrench® MOSFET Typical Characteristics NORMALIZED DRAIN TO SOURCE ON-RESISTANCE rDS(on), DRAIN TO SOURCE ON-RESISTANCE (m) 30 2.0 PULSE DURATION = 250s PULSE DURATION = 250s DUTY CYCLE = 0.5% MAX 1.8 DUTY CYCLE = 0.5% MAX 25 ID = 80A 1.6 20 1.4 15 1.2 1.0 10 TJ = 175oC 5 0.8 ID = 80A N 0 TJ = 25oC IG 3 4 5 6 7 8 9 10 S VGS, GATE TO SOURCE VOLTAGE (V) ED DE Figure 11. RDSON vs. Gate Voltage 0.6 0.4 -80 VGS = 10V -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE(oC) Figure 12. Normalized RDSON vs. Junction Temperature U R NEW 1.3 O i VGS = VDS IN F m N 1.2 ID = 250A D se IO 1.1 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED GATE THRESHOLD VOLTAGE T DE on AT 1.0 N R M 0.9 N ME OU OR 0.8 O OM T Y INF 0.7 C C 0.6 C RE TA OR 0.5 T N F 0.4 IS O CO IVE -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE(oC) IS N SE TAT Figure 13. Normalized Gate Threshold Voltage vs. D E A N Temperature 1.10 ID = 5mA 1.05 1.00 0.95 0.90 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC) Figure 14. Normalized Drain to Source Breakdown Voltage vs. Junction Temperature THIS DEVIC RPELPERESE 10000 10 ID = 80A Ciss 8 1000 VDD = 20V Coss 6 VDD = 24V VDD =16V 4 100 VGS, GATE TO SOURCE VOLTAGE(V) CAPACITANCE (pF) f = 1MHz VGS = 0V Crss 10 0.1 1 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) 2 0 0 5 10 15 20 25 30 35 40 45 50 Qg, GATE CHARGE(nC) Figure 15. Capacitance vs. Drain to Source Voltage Figure 16. Gate Charge vs. Gate to Source Voltage www.onsemi.com 5 Downloaded from Arrow.com. D DESIGN DISCONTINUE THIS DEVICERIPESLPNERAOESTSERECENOCTANOTTMIAVMCEETFNYODOREUDINRFFoOOnRRseMNmAEiTWION ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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