LTC4020 55V Buck-Boost Multi-Chemistry Battery Charger

Features

• Wide Voltage Range: 4.5V to 55V Input, Up to 55V Output (60V Absolute Maximums)
• Synchronous Buck-Boost DC/DC Controller
• Li-Ion and Lead-Acid Charge Algorithms
• ±0.5% Float Voltage Accuracy
• ±5% Charge Current Accuracy
• Instant-On for Heavily Discharged Batteries
• Ideal Diode Controller Provides Low Loss PowerPath When Input Power Is Limited
• Input Voltage Regulation for High Impedance Input Supplies and Solar Panel Peak Power Operation
• Onboard Timer for Protection and Termination
• Bad Battery Detection with Auto-Reset
• NTC Input for Temperature Qualified Charging
• Binary Coded Open-Collector Status Pins
• Low Profile (0.75mm) 38-Pin 5mm × 7mm QFN Package

Applications

• Portable Industrial and Medical Equipment
• Solar-Powered Systems
• Military Communications Equipment
• 12V to 24V Embedded Automotive Systems

Description

The LTC®4020 is a high voltage power manager providing PowerPath™ instant-on operation and high efficiency battery charging over a wide voltage range. An onboard buck-boost DC/DC controller operates with battery and/or system voltages above, below, or equal to the input voltage. The LTC4020 seamlessly manages power distribution between battery and converter outputs in response to load variations, battery charge requirements and input power supply limitations.

The LTC4020 battery charger can provide a constant-current/constant-voltage charge algorithm (CC/CV), constant-current charging (CC), or charging with an optimized 4-step, 3-stage lead-acid battery charge profile. Maximum converter and battery charge currents are resistor programmable.

The IC's instant-on operation ensures system load power even with a fully discharged battery. Additional safety features include preconditioning for heavily discharged batteries and an integrated timer for termination and protection.

All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. patents, including 7583113 and 8405362.

Typical Application

Absolute Maximum Ratings

Pin Configuration

Order Information

Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

Electrical Characteristics

Buck-Boost Switching Converter

Battery Charger

Typical Performance Characteristics

Reference Voltages vs Temperature

Currents vs Temperature

Currents vs Voltage

Charge Current Characteristics

Pin Functions

TG1 (Pin 1): VIN side (step-down) primary switch FET gate driver output.

BST1 (Pin 2): Boosted supply rail for VIN side (step-down) switch FETs. Connect 1µF capacitor from this pin to SW1. Connect 1A Schottky diode cathode to this pin, anode to INTVCC pin.

SGND (Pins 3, 29, Exposed Pad 39): Signal Ground Reference. Connect to the output decoupling capacitor negative terminal and battery negative terminal. The exposed pad (39) must be soldered to PCB ground (SGND) for electrical connection and rated thermal performance.

SENSGND (Pin 4): Kelvin connection for PGND used for SENSBOT current sense reference.

SENSBOT (Pin 5): Ground Referred Current Sense Amplifier Input. Inductor current is monitored via a PGND referenced current sense resistor (RSENSEB), typically in series with the source of the VIN side synchronous switch FET. Kelvin connect this pin to the associated sense resistor. Inductor current is limited to a maximum average value (ILMAX), and corresponds to 50mV across this sense resistor during normal operation. RSENSEB = 0.05/ILMAX. Set RSENSEB = RSENSEA, as described in SENSTOP. A filter capacitor (CSENSB) is typically connected from SENSBOT to SENSGND for noise reduction. CSENSB ~ 1ns/RSENSEB. See Applications Information section.

SENSTOP (Pin 6): VIN Referred Current Sense Amplifier Input. Inductor current is monitored via a VIN referenced current sense resistor (RSENSEA), typically in series with the drain of the VIN side primary switch FET. Kelvin connect this pin to the associated sense resistor. Inductor current is limited to a maximum average value (ILMAX), and corresponds to 50mV across this sense resistor during normal operation. RSENSEA = 0.05/ILMAX. Set RSENSEA = RSENSEB, as described in SENSBOT.

SENSVIN (Pin 7): Kelvin connection for input supply (VIN) used for SENSTOP current sense reference. Input power supply pin for most internal low current functions. Typical pin bias current is 0.25mA.

RT (Pin 8): System Oscillator Frequency Control Pin. Connect resistor (RRT) from this pin to ground. Resistor value can range from 50k (500kHz) to 500k (50kHz). RRT = 100k yields 250kHz operating frequency. See Applications Information.

SHDN (Pin 9): Precision Threshold Shutdown Pin. Enable threshold is 1.225V (rising), with 100mV of input hysteresis. When in shutdown, all charging functions are disabled and input supply current is reduced to 27.5µA. Typical SHDN pin input bias current is 10nA.

VIN_REG (Pin 10): Input Voltage Regulation Reference. Battery charge current is reduced when the voltage on this pin falls below 2.5V. Connecting a resistor divider from VIN to this pin enables programming of minimum operational VIN voltage for the battery charging function. This is used to program the peak power voltage for a solar panel, or to help maintain a minimum voltage on a poorly regulated input supply. This pin should not be used to program minimum operational VIN voltage with low impedance supplies. Should the input supply begin to collapse, the LTC4020 reduces the DC/DC converter input power such that programmed minimum VIN operational voltage is maintained. If the voltage regulation feature is not used, connect the VIN_REG pin to VIN or INTVCC. Typical VIN_REG pin input bias current is 10nA. See Applications Information.

MODE (Pin 11): Charger Mode Control Pin. Short this pin to ground to enable a constant-current/constant-voltage (CC/CV) charging algorithm. Connect this pin to pin INTVCC to enable a 4-step, 3-stage lead-acid charging algorithm. Float this pin to force a constant-current (CC) charging function. See Applications Information section.

STAT1 (Pin 12): Open-collector status output, typically pulled up through a resistor to a supply voltage. This status pin can be pulled up to voltages as high as 55V when the pin is disabled, and can sink currents up to 1mA when logic low (<0.4V). Pull down currents as high as 5mA (absolute maximum) are supported for higher current applications, such as lighting LEDs.

If the LTC4020 is configured for a CC/CV charging algorithm, the STAT1 pin is pulled low while battery charge currents exceed 10% of the programmed maximum (C/10). The STAT1 pin is also pulled low during NTC faults. The STAT1 pin becomes high impedance when a charge cycle is terminated or when charge current is below the C/10 threshold.

If the LTC4020 is configured for a CC charging algorithm, the STAT1 pin is pulled low during the entire charging cycle. The STAT1 pin becomes high impedance when the charge cycle is terminated.

If the LTC4020 is configured for a lead-acid charging algorithm, the STAT1 pin is used as a charge cycle stage indicator pin, and pulled low during the bulk and absorption charging stages. The pin is high impedance during the float charging period and during NTC or bad battery faults. See Applications Information section.

STAT2 (Pin 13): Open-collector status output, typically pulled up through a resistor to a supply voltage. This status pin can be pulled up to voltages as high as 55V when disabled, and can sink currents up to 1mA when enabled (<0.4V). Pull down currents as high as 5mA (absolute maximum) are supported for higher current applications, such as lighting LEDs.

If the LTC4020 is configured for a CC/CV charging algorithms, the STAT2 pin is pulled low during NTC faults or after a bad battery fault occurs.

If the LTC4020 is configured for a CC charging algorithms, the STAT2 pin is pulled low during NTC faults.

If the LTC4020 is configured for a lead-acid charging algorithm, the STAT2 pin is used as a charge cycle stage indicator pin, and pulled low during the bulk and float charging stages. The pin is high impedance during the absorption charging stage and during NTC or bad battery faults. See Applications Information section.

TIMER (Pin 14): End-Of-Cycle Timer Programming Pin. If a timer based charging algorithm is desired, connect a capacitor (CTIMER) from this pin to ground. If no timer functions are desired, connect this pin to ground. End-of-cycle time (in hours) is programmed with the value of CTIMER following the equation: TEOC = CTIMER · 1.46 · 10⁷. During CC/CV or lead-acid charging algorithms, a bad battery fault is generated if the battery voltage does not reach the precondition threshold voltage within 1/8 of TEOC, or: TPRE = CTIMER · 1.82 · 10⁶. A 0.2µF capacitor is typically used for CC/CV charging, which generates a 2.9 hour timer TEOC, and a precondition limit time of 22 minutes. A 0.47µF capacitor is typically used for a lead-acid charger, which generates a 6.8 hour absorption stage safety timeout.

RNG/SS (Pin 15): Battery Charge Current Programming Pin. This pin allows dynamic adjustment of maximum charge current, and can be used to employ a soft-start function. Setting the voltage on the RNG/SS pin reduces maximum charge current from the value programmed. The maximum charge current is reduced to the fraction of programmed current (as per the sense resistor, RCS) corresponding to the voltage set on the pin (in volts). This pin has an effective range from 0 to 1V. For example, with 0.5V RNG/SS on the pin, the maximum charge current will be reduced to 50% of the programmed value set by the sense resistor values. 50µA is sourced from the RNG/SS pin, so maximum charge current can be programmed by connecting a single resistor (RRNG/SS) from RNG/SS to ground, such that the voltage dropped across the resistor is equivalent to the desired pin voltage: VRNG/SS = 50µA · RRNG/SS. Soft-start functionality can be implemented by connecting a capacitor (CRNG/SS) from RNG/SS to ground, such that the time required to charge the capacitor is the desired soft-start interval (TSS1). The voltage that corresponds to full programmed battery charge current on the RNG/ SS pin is 1V, so the relation for this capacitor reduces to: CRNG/SS = 50µA · TSS1. The RNG/SS pin is pulled low during periods when charging is disabled, including NTC faults, bad battery faults, and normal charge cycle termination. This allows for a graceful start after faults and when initiating new charge cycles, should soft-start functionality be implemented. Both a soft-start capacitor and a programming resistor can be implemented in parallel. RNG/SS voltage can also be manipulated using an active device, such as employing a pull-down transistor to disable charge current or to dynamically servo maximum charging current. Because this pin is internally pulled to ground during fault conditions, active devices with low-impedance pull up capability cannot be used. See Applications Information section.

NTC (Pin 16): Battery Temperature Monitor Pin. Connect a 10k, β = 3380 NTC thermistor from this pin to ground. The NTC pin is the input to the negative temperature coefficient temperature monitoring circuit. This pin sources 50µA, and monitors the voltage created across the 10k thermistor. When the voltage on this pin is above 1.35V (0°C) or below 0.3V (40°C), charging is disabled and an NTC fault is signaled at the STAT1 and STAT2 status pins. If the internal timer is being used, the timer is paused, suspending the charging cycle until the NTC fault condition is relieved. There is approximately 5°C of temperature hysteresis associated with each of the temperature thresholds. The NTC function remains enabled while thermistor resistance to ground is less than 250k. If this function is not desired, leave the NTC pin unconnected or connect a 10k resistor from the NTC pin to ground. The NTC pin contains an internal clamp that prevents excursions above 2V, so the pin must not be pulled high with a low impedance source. A low impedance element can be used to pull the pin to ground.

VFB (Pin 17): Battery Voltage Feedback Pin. Battery voltages are programmed through a feedback resistor divider placed from the BAT pin to FBG. During CC/CV charging, the battery voltage references are: Float Voltage (VFLOAT) = 2.5V, Trickle Charge Voltage (VTRK) = 1.75V, Auto-Restart Voltage (VRESTART) = 2.4375. During lead-acid charging, the battery voltage references are: Absorption Voltage (VABSOR) = 2.5V, Float Charge Voltage (VFLT) = 2.3125V, Trickle Charge Voltage (VTRK) = 1.75V, Bulk Recharge Voltage (VBULK) = 2.1875V. With RFB1 connected from BAT to VFB and RFB2 connected from VFB to FBG, the ratio of (RFB1/RFB2) for the desired programmed battery float voltage (CC/CV charging) or absorption voltage (lead-acid charging) follows the relation: RFB1/RFB2 = (VFLOAT/ABSORB)/2.5 – 1.

FBG (Pin 18): Voltage Feedback Divider Return. This pin contains a low impedance path to signal ground, used as the ground reference for voltage monitoring feedback resistor dividers. When VIN is not present or the LTC4020 is in shutdown, this pin becomes high impedance, eliminating current drain from the battery associated with the feedback resistor dividers.

VFBMIN (Pin 19): Minimum voltage feedback pin for instant-on operation. Minimum DC/DC converter output voltage (VOUTMIN) is programmed using this pin for instant-on functionality. VOUTMIN is programmed through a feedback resistor divider placed from the CSP pin to FBG. If the battery voltage is below the voltage level programmed using this pin, the LTC4020 controls the external PowerPath FET as a linear pass element, allowing the DC/DC converter output to achieve the minimum programmed voltage. Maximum battery charge current is reduced as the voltage across the PowerPath FET increases to control power dissipation. The internal VFBMIN voltage reference is 2.125V. With a resistor (RMIN1) connected from CSP to VFBMIN, and a resistor (RMIN2) connected from VFBMIN to FBG, the ratio of these resistors for the desired minimum converter output voltage follows the relation: RMIN1/RMIN2 = (VOUT(MIN)/2.125) – 1. Using the same resistor values for battery voltage programming, or RFB1 = RMIN1 and RFB2 = RMIN2, yields an instant-on voltage that is 85% of VFLOAT (CC/CV charging) or VABSORB (lead-acid charging): VOUT(MIN) = 0.85 · VFLOAT/ABSORB.

BAT (Pin 20): Battery Voltage Monitor Pin. This pin serves as the positive reference for the LTC4020 ideal diode function. If a system load occurs that is large enough to collapse the DC/DC converter output while charging is terminated or disabled, and the battery is disconnected (PowerPath FET is high impedance), the ideal diode function engages the PowerPath. This function powers the system load from the battery, and modulates the PowerPath FET gate such that the system output voltage is maintained with 14mV across the PowerPath FET, provided the voltage drop due to RDS(ON) < 14mV. This allows large loads to be accommodated without excessive power dissipation in the body diode of the PowerPath FET.

BGATE (Pin 21): PowerPath FET Gate Driver Output. This pin is controls the multiple functions of the PowerPath FET. This pin is pulled low during a normal charging cycle, minimizing the FET series impedance between the DC/ DC converter output and the battery. The BGATE pin is also forced low when the DC/DC converter is disabled, maintaining a low impedance connection to power the system from the battery. When BGATE is pulled low, CSP BGATE is limited internally to 9.5V, so if CSP > 9.5V, BGATE is maintained by an internal clamp at CSP – BGATE = 9.5V. The BGATE pin must be near ground or at the clamp voltage for C/10 detection to occur. If the battery voltage is lower than the instant-on threshold (see VFBMIN), BGATE servos the PowerPath FET impedance such that a voltage drop between the CSN pin and the BAT pin is created while battery charging continues. If the VCSN – VBAT voltage exceeds 0.4V, maximum charge current is reduced to decrease power dissipation in the PowerPath FET. When the DC/DC converter is enabled, but the battery charge cycle has terminated, BGATE is pulled high to disconnect the battery from the converter output. The battery is also disconnected in the same manner during NTC faults. The ideal diode function is active during these periods, however, so if a system load occurs that is larger than what the DC/DC converter can accommodate, the battery can supply the required current, and the BGATE pin will be servo controlled to force a voltage drop of only 14mV across the PowerPath FET. The ideal diode function is disabled during bad battery faults. If a PowerPath FET is not being used, such as with a leadacid charging application, connect a 0.1nF capacitor from BGATE to CSN.

CSN (Pin 22): Battery Charger Current Sense Negative Input. Connect this pin to the negative terminal of the battery charge current sense resistor (RCS) through a 100 Ω resistor. Connect a filter capacitor between this pin and the CSP pin for ripple reduction. See Applications Information section. The value of the sense resistor is related to the maximum battery charge current (ICSMAX): RCS = 0.05/ICSMAX. This pin also serves as the negative reference for the LTC4020 ideal diode function (see BAT).

CSP (Pin 23): Battery Charger Current Sense Positive Input. Connect this pin to the positive terminal of the battery charge current sense resistor (RCS) through a 100 Ω resistor. Connect a filter capacitor between this pin and the CSN pin for ripple reduction. See Applications Information section. The value of the sense resistor is related to the maximum battery charge current (ICSMAX) such that: RCS = 0.05/ICSMAX.

CSOUT (Pin 24): Current Sense Amplifier Output and Charge Current Monitor. Connect 100pF capacitor to ground. Pin output impedance is 100k, so any loading for monitors must be high impedance. The sense output voltage follows the relation: VCSOUT = 0.25 + 20 · (VCSP – VCSN). CSOUT is only active while battery charger functions are operating. CSOUT pin voltage is pulled to 0V after charge cycle termination or during fault conditions.

ILIMIT (Pin 25): Switched Inductor Maximum Current Programming Pin. This pin allows dynamic adjustment of DC/DC converter maximum average inductor current, and can be used to employ a soft-start function. Setting the voltage on the ILIMIT pin reduces maximum average inductor current from the value programmed. The inductor current limit is reduced to the fraction of programmed current (as per the sense resistors) corresponding to the voltage set on the pin (in volts). This pin has an effective range from 0 to 1V. For example, with 0.5V on the pin, the maximum inductor current will be reduced to 50% of the programmed value set by the sense resistor values. 50µA is sourced from this pin, so maximum inductor current can be programmed by connecting a single resistor (RILIMIT) from ILIMIT to ground, such that the voltage dropped across the resistor is equivalent to the desired pin voltage: VILIMIT = 50µA · RILIMIT. Soft-start functionality can be implemented by connecting a capacitor (CILIMIT) from ILIMIT to ground, such that the time required to charge the capacitor is the desired soft-start interval (TSS2). The voltage that corresponds to full inductor current on the ILIMIT pin is 1V, so the relation for this capacitor reduces to: CILIMIT = 50µA · TSS2. ILIMIT voltage can also be manipulated using an active device, such as employing a pull-down transistor to disable DC/DC converter current or to dynamically servo maximum current. Because this pin is internally pulled to ground during portions of the converter power-up cycle, active devices with low impedance pull-up capability cannot be used.

VFBMAX (Pin 26): DC/DC Converter Output Feedback Pin. Maximum DC/DC converter output voltage (VOUTMAX) is programmed using this pin. When a battery charge cycle is terminated or disabled, and the battery is disconnected (PowerPath FET is high impedance), the converter output will servo to this maximum voltage. The internal VFBMAX voltage reference is 2.75V. With a resistor (RMAX1) connected from CSP to VFBMAX and a resistor (RMAX2) connected from VFBMAX to FBG, the ratio of RMAX1/RMAX2 for the desired maximum DC/DC converter output voltage follows the relation: RMAX1/RMAX2 = (VOUTMAX/2.75) – 1. Using the same resistor values for battery voltage programming, or RFB1 = RMAX1 and RFB2 = RMAX2, yields a voltage while not charging that is 110% of VFLOAT (CC/CV charging) or VABSORB (lead-acid charging): VOUTMAX = 1.1 · VFLOAT/ABSORB. If RMAX1/RMAX2 are chosen for a not-charging powerstage output voltage (VOUTMAX) of less than 110% of the full-charge voltage, be sure to choose RMAX1/RMAX2 to allow adequate headroom between VOUTMAX and the battery full-charge voltage to cover voltage drops in the battery-charge current-sense resistor (RCS) and the PowerPath FET. Typically, at least 100mV to 200mV of headroom is required.

ITH (Pin 27): DC/DC Converter Voltage Loop Compensation Pin. See Applications Information section for compensation component selection details.

VC (Pin 28): DC/DC Converter Current Loop Compensation Pin. See Applications Information section for compensation component selection details.

BST2 (Pin 30): Boosted supply rail for VOUT side (step-up) switch FETs. Connect a 1µF capacitor from this pin to SW2. Connect a 1A Schottky diode cathode to this pin, anode to INTVCC pin.

TG2 (Pin 31): VOUT side (step-up) synchronous switch FET gate driver output.

SW2 (Pin 32): Switched node for step-up switches. Connect the switched inductor to this pin. Connect the primary switch FET drain and synchronous switch FET source to this pin.

BG2 (Pin 33): VOUT side (step-up) primary switch FET gate driver output.

INTVCC (Pin 34): Boosted Driver Refresh Supply. This supply is regulated to 5V and is current limited to a typical value of 150mA. Connect a 2.2µF ceramic capacitor from this pin to PGND. Boosted supply refresh diode anodes are connected to this pin. Using this pin to power external 5V circuitry is not recommended. Note that internal VCC regulator has a minimum-specified current-limit value of 85mA. Since the internal regulator supplies gate drive to all four power-stage FETs, 85mA represents a maximum practical limit for total gate-drive current. See Applications Information section.

PGND (Pin 35): Switch high current return path for step-up primary and step-down synchronous switches.

PVIN (Pin 36): High Current Input Supply Pin. Connect 10µF decoupling capacitor from this pin to PGND. The PVIN pin provides input supply current for the INTVCC internal 5V linear regulator.

BG1 (Pin 37): VIN side (step-down) synchronous switch FET gate driver output.

SW1 (Pin 38): Switched node for step-down switches. Connect the switched inductor to this pin. Connect the primary switch FET source and synchronous switch FET drain to this pin.

Block Diagrams

Operation

Functional Overview

The LTC4020 is an advanced high voltage power manager and multi-chemistry battery charger designed to efficiently transfer power from a variety of sources to a system power supply rail and a battery. The LTC4020 contains a step-up/step-down DC/DC controller that allows operation with battery and system voltages that are above, below, or equal to the input voltage (VIN). A precision threshold shutdown feature allows incorporation of input voltage UVLO functionality using a simple resistor divider. When in low current shutdown mode, the IC input supply bias is reduced to only 27.5µA.

The LTC4020 charger is programmable to produce optimized charging profiles for a variety of battery chemistries. The LTC4020 can provide a constant-current/constant-voltage charge characteristic with either C/10 or timed termination for use with lithium based battery systems, a constant-current characteristic with timed termination, or an optimized 4-step, 3-stage lead-acid charge profile. Maximum battery charge current is programmable using a sense resistor, and a charge current range adjust pin allows dynamic adjustment of maximum charge current. A switcher core current limit adjust pin also allows dynamic limiting of power available to the system by virtue of limiting maximum current in the DC/DC converter inductor.

The LTC4020 preconditions heavily discharged batteries by reducing charge current to one-fifteenth of the programmed maximum. Once the battery voltage climbs above an internally set threshold, the IC automatically increases maximum charging current to the full programmed value. A bad battery detection function signals a fault and suspends charging should a battery not respond to preconditioning.

Battery temperature is monitored using a thermistor measurement system. This feature monitors battery temperature during the charging cycle, suspending the charge cycle and signaling a fault condition if the battery temperature moves outside a safe charging range of 0°C to 40°C. The charge cycle automatically resumes when the temperature returns to that safe charging range.

Instant-on PowerPath architecture ensures that an application is powered immediately after an external voltage is applied, even with a completely dead battery, by prioritizing power to the application. Since the controller output (VOUT) and the battery (BAT) are sometimes decoupled, the LTC4020 includes an ideal diode controller, which guarantees that ample power is always available to VOUT if there is insufficient power available from the DC/DC converter. Should there be no input power available (VIN), the LTC4020 makes a low impedance connection from the battery to VOUT though the PowerPath FET. Battery life is maximized during periods of input supply disconnect by reducing the LTC4020 battery standby current to less than 10µA.

The LTC4020 contains two digital open-collector outputs that provide charger status and signal fault conditions. These binary coded pins signal battery charging, standby or shutdown modes, battery temperature faults, and bad battery faults.

DC/DC Converter Operation

The LTC4020 uses a proprietary average current mode DC/DC converter architecture. As shown in Figure 3, when VIN is higher than VOUT during step-down (buck) operation, switches A (driven by pin TG1) and B (driven by pin BG1) perform the PWM required for accommodating power conversion. Ideally, switch D (driven by pin TG2) would conduct continuously and switch C (driven by pin BG2) would stay off, making PWM switching action much like that in a synchronous buck topology. Switch D uses a bootstrapped driver, however, so switch C conducts for a minimum on time of 150ns each cycle to refresh the driver and switch D is disabled to accommodate this refresh time. A 75ns non-overlap period separates the conduction of the two switches preventing shoot-through currents.

When VIN is lower than VOUT during step-up (boost) operation, switches C and D perform the PWM required for accommodating power conversion. Ideally, switch A would conduct continuously and switch B would stay off, making PWM switching action much like that in a synchronous boost topology. Since switch A also uses a bootstrapped drive, however, the B switch conducts for 100ns during this refresh period. A 75ns non-overlap period, separates the conduction of the two switches, preventing shoot-through currents.

If VIN is close to VOUT, the controller operates in 4-switch (buck-boost) mode, where both switch pairs PWM simultaneously to accommodate conversion requirements.

The LTC4020 senses the DC/DC converter output voltage using a resistor divider feedback network that drives the VFBMAX pin. The difference between the voltage on the VFBMAX pin and an internal 2.75V reference is converted into an error current by the voltage loop transconductance amplifier (EA–V). This error current is integrated by a compensation network to produce a voltage on pin ITH. The ITH compensation network is designed to optimize the response of the converter to changes in load current while the converter is in regulation. At regulation, the ITH pin will servo to a value that corresponds to the average inductor current of the DC/DC converter.

Inductor current is monitored through two like value sense resistors, placed in series with each of the VIN side converter switches, A and B. The sum of these sensed currents yields a reasonably accurate continuous representation of inductor current.

The voltage produced on the ITH pin is translated into an offset at the input of the two current sense amplifiers. The difference between this offset voltage and the sum of the voltages is sensed on the SENSTOP and SENSBOT pins, then is converted to error currents by the current sense transconductance amplifiers (EA–CA and EA–CB). These error currents are summed and integrated by a compensation network to produce a voltage on the pin VC. This compensation network is designed to optimize the response of the converter duty cycle to required changes in inductor current. The VC pin voltage is compared to an internally generated ramp, and the output of this comparison controls the duty cycle of the charger's switches.

Battery Charger Operation

During the majority of a normal battery charge cycle, the LTC4020 makes a low impedance connection between the battery and the DC/DC converter output through the PowerPath FET, as in Figure 5. This PFET is controlled by the LTC4020 through modulation of the BGATE pin, which is connected to the FET gate. When charging is disabled, the FET is disabled, disconnecting the battery from the converter output by pulling the gate of the PowerPath FET high via the BGATE pin. The converter output is regulated by VFBMAX while the FET is disabled. When normal charger operation resumes, the gate is pulled low. As the BGATE pin is a slow-moving node, C/10 detection is disabled until the BGATE pin approaches its normal operating voltage, which prevents premature C/10 detection during reconnection of the battery. The slow movement of BGATE can also cause the converter output to regulate to VFBMAX for a short time during start-up until the FET is enabled. This FET is also linearly controlled during low battery conditions to enable the instant-on function, where the converter output can be separated from a heavily discharged battery to power the rest of the system before the battery voltage responds to charging. C/10 detection is also disabled when the charger is operating in instant-on mode. This FET is also automatically configured as a 14mV ideal diode, which provides a low loss path from the battery to the output when system loads require power from the battery while the battery is disconnected from the converter output.

The battery charger takes control of the DC/DC converter operation by modulating the ITH pin voltage in response to sensed battery charge current, battery voltage, and input voltage. The converter thus provides exactly the amount of power required to satisfy both the system load and battery charger requirements.

Battery charge current is monitored via an external sense resistor connected to the pins CSP and CSN. The voltage across this resistor is amplified internally by a factor of 20, which is output onto pin CSOUT. This output voltage rides on top of a constant 250mV offset. The CSOUT pin voltage drives an internal transconductance amplifier that servos the DC/DC converter's ITH pin voltage in response to the current requirements of a charging battery. CSOUT voltage is also used internally as a charge current monitor to detect <C/10 current thresholds.

Battery voltage is monitored via the VFB pin. This voltage drives a transconductance amplifier that servos the DC/ DC converter ITH pin voltage in response to voltage developed on a charging battery. The transition from constant-current (CC) to constant-voltage (CV) charging modes is also detected using this transconductance amplifier. The VFB voltage is used for all battery voltage monitor thresholds, each being defined as a percentage of the internal 2.5V reference voltage.

Input voltage regulation is implemented via the VIN_REG pin for use with poorly regulated or high impedance supplies. This pin drives a transconductance amplifier that reduces the ITH pin voltage in response to voltage sensed on the VIN_REG pin falling through 2.5V. This transconductance amplifier remains active even while battery charging is disabled, so the input regulation feature continues to operate regardless of the state of a charge cycle.

The LTC4020 contains an internal charge cycle timer that is used for time based control of a charge cycle. This function is enabled by connecting a capacitor to the TIMER pin. Grounding this pin disables all timer functions. The timer is used to terminate a successful CC or CC/CV charge cycle after a programmed end-of-cycle (TEOC) time. This timer is also used to transition a leadacid charger to float charging if charge current does not fall adequately during the absorption phase of the charge cycle within the programmed TEOC time.

Use of the timer function also enables bad battery detection during CC/CV or lead-acid charging. This fault condition is achieved if the battery does not respond to preconditioning (VFB < 1.75V), such that the charger remains in (or enters) precondition mode after one-eighth of the programmed TEOC time. A bad battery fault halts the charging cycle, and the fault condition is reported on the status pins. The bad battery fault remains active until the battery voltage rises above the precondition threshold, or until power or SHDN is cycled.

CC/CV Charging Overview (MODE = 0V)

To program the LTC4020 for CC/CV charging, connect the MODE pin to ground. This mode is commonly used for Li-Ion, Li-Polymer, and LiFePO4 battery charging.

If the voltage on the VFB pin is below 1.75V, the LTC4020 engages precondition mode, which provides low level charge currents to gently increase voltage on heavily discharged batteries. During preconditioning, the maximum charge current is reduced to one-fifteenth of the programmed value as set by RCS, the battery charge current programming resistor. Full charge current capability is restored once the voltage on VFB rises above 1.75V. Full charge current capability remains until the VFB pin approaches the 2.5V float voltage. This is the constant-current (CC) portion of the charge cycle.

When the voltage on the VFB pin approaches the 2.5V float voltage, the charger transitions into constant-voltage (CV) mode, and charge current is reduced from the maximum programmed value. If timer termination is used, the safety timer period starts when CV mode is initiated, and the charge cycle will terminate when the timer achieves end-of-cycle (TEOC). This timer is typically programmed to achieve TEOC in three hours, but can be configured for any amount of time by setting an appropriate timing capacitor value (CTIMER).

During CV mode, the required charge current is steadily reduced as the battery voltage is maintained such that the voltage on the VFB pin remains close to 2.5V. If the charger is configured for C/10 termination, when the battery charge current falls below one-tenth of the programmed maximum current (<C/10), the charge cycle will terminate and the charger indicates not charging on the status pins.

When timer termination is used, the charger continues to operate with charging current less than one-tenth of the programmed maximum current. The STAT1 status pin, however, responds to the <C/10 current level regardless of termination scheme, so the IC will indicate a not charging status when the charging current is below the C/10 current level. The charge cycle will continue, however, and the charger will source <C/10 current into the battery. Programmed float voltage is maintained while the charger tops-off the battery with low currents until the programmed TEOC time has elapsed, at which time the charge cycle will terminate, charge current flow into the battery will be disabled, and the battery will be disconnected from the converter output.

After termination, if the battery discharges such that the voltage on the VFB pin drops to 2.4375V, or 97.5% of the programmed float voltage, a new charge cycle is automatically initiated.

Lead-Acid Charging Overview (MODE = INT_VCC)

To program the LTC4020 for lead-acid charging, connect the MODE pin to the INTVCC pin. The LTC4020 supports a 4-step, 3-stage lead-acid charging profile.

The first step of the charging profile provides low level charge current to gently increase voltage on heavily discharged batteries. If the voltage on VFB is below 1.75V, which corresponds to just over 10V for a 6-cell (12V) battery, the maximum charge current is reduced to one-fifteenth of the programmed value as set by RCS. Once the VFB voltage rises above 1.75V, full charge current capability is restored, and the bulk charging stage begins.

The bulk charging stage of the charge profile, which is the first stage of 3-stage battery charging, is a constant-current charging stage, with the maximum programmed charge current forced into the battery. This continues until the battery voltage rises such that the VFB pin approaches the 2.5V absorption reference voltage.

As the bulk charging stage completes and the voltage on the VFB pin rises to approach 2.5V, the charger transitions into the absorption stage, which is the 2nd stage of 3-stage battery charging. During the absorption stage, the required charge current is steadily reduced as the battery voltage approaches the absorption voltage. This is a constant-voltage charging stage, as the battery voltage is maintained such that the VFB pin remains close to the 2.5V absorption reference voltage. It is during this stage that the battery stored charge increases to 100% capacity. The 2.5V absorption reference typically corresponds to 14.4V for a 6-cell battery.

When the absorption stage charge current falls to one-tenth of the programmed maximum current, the charger will initiate the third stage in the charge profile, the float charging stage. The safety timer can be used with a lead-acid charger to limit the duration of the absorption stage of the charging profile. The timer is initiated at the start of the absorption stage, and forces the charger into float if the charge current does not fall to the required one-tenth of the programmed maximum current during the absorption stage before the timer reaches TEOC. A 0.47µF capacitor on the TIMER pin is typically used, which generates a 6.8-hour absorption stage safety timeout.

Once the float charging stage is initiated, the battery reference voltage is reduced to 92.5% of the absorption voltage, or 2.3125V. The battery voltage is maintained at a voltage corresponding to this reference voltage, and maximum charge current is reduced to one-fifteenth of the programmed maximum. This level corresponds to 13.3V for a 6-cell battery.

Once float charging is achieved, the LTC4020 charger remains active and will attempt to maintain the float voltage on the battery indefinitely. During float charging, if a load on the battery exceeds the maintenance charge current of one-fifteenth of the programmed maximum, the battery voltage will begin to discharge. If a load discharges the battery such that the voltage on VFB falls to 2.1875V, corresponding to 12.6V for a 6-cell battery, the LTC4020 restarts the full 3-stage charging cycle by reinitiating the bulk charging stage. Bulk charging is engaged by resetting the internal VFB reference to the 2.5V absorption voltage reference and increasing the charge current capability to the programmed maximum.

CC Charging Overview (MODE = NC)

To program the LTC4020 for CC charging, leave the MODE pin unconnected. This mode can be used for charging NiCd and NiMH batteries, supercap charging, or in any other application where a timed current source is desired. CC mode can also be used when the voltage dependent precondition mode is not desired.

In CC mode, the LTC4020 will maintain full programmed charge current capability for the duration of the timer period. The trickle charge function is disabled, although maximum charge current will be reduced during instant-on operation when the PowerPath FET is operating in linear mode. The charger will terminate the charge cycle and the PowerPath FET will become high-impedance once timer EOC is reached.

While the charge cycle is designed to be voltage independent, a maximum VBAT voltage can be programmed corresponding to VFB = 2.5V, allowing constant-voltage functionality at that level if desired.

Once the timer reaches TEOC and the charge cycle terminates, input power or SHDN must be cycled to initiate another charge cycle. If the timer function is disabled (TIMER = 0V), the current source function remains active indefinitely.

Note: For nickel-chemistry batteries (e.g. NiCd or NiMH), the possibility of overcharging must be considered. A typical method is to charge with low currents for a long period of time. NiCd and NiMH batteries can absorb a C/300 charge rate indefinitely. Shorter duration charging is possible using a timed current source charge algorithm. It is recommended to ensure a depleted battery before charging, then subsequently charge the battery to no more than 125% capacity. For example, a depleted 2000mAh NiMH battery is charged with 2.5A for one hour.

Applications Information

DC/DC CONVERTER SECTION

Output Voltage Programming

The LTC4020 DC/DC converter maximum output voltage, or voltage safety limit, is set by an external feedback resistive divider, providing feedback to the VFBMAX pin. This divider sets the output voltage that the converter will servo to when the PowerPath FET is high impedance, which occurs after charge cycle termination or during a charge cycle fault. The resultant feedback signal is compared with the internal 2.75V voltage reference by the converter error amplifier. The output voltage is given by the equation: VOUT = 2.75V · (1 + RMAX1 / RMAX2), where RMAX1 and RMAX2 are defined as in Figure 6. The values for RMAX1 and RMAX2 are typically the same as those used for the divider that programs battery voltage (to the VFB pin; see Battery Charger Section), to yield a DC/DC converter maximum regulation voltage, or safety limit, that is 10% higher than the battery charge voltage.

RSENSEA, RSENSEB: DC/DC Converter Current Programming

The LTC4020 performs inductor current sensing via two resistors connected in series with the VIN side switches (see Figure 3). The high side sense resistor (RSENSEA) is connected between VIN and the drain of the top side switch FET (A). Both nodes on the sense resistor must be Kelvin connected to the IC via the pins SENSVIN and SENSTOP. Likewise, the low side sense resistor (RSENSEB) is connected between the source of the bottom side switch FET (B) and PGND. Both nodes on the sense resistor must be Kelvin connected to the IC, via the pins SENSBOT and SENSGND. Both of these sense resistors must be of equal value, and that value programs the switched inductor maximum average current in the DC/DC converter inductor (ILMAX) such that: RSENSEA = RSENSEB = 0.05 / ILMAX.

When the converter is stepping down, or operating in buck mode, the inductor current will be roughly equivalent to the converter output current. Input supply current (IIN) will be less than the inductor current (IL), such that: IL ~ IIN · (VIN / VOUT).

When the converter is stepping up, or operating in boost mode, the inductor current will be roughly equivalent to the converter input current. Inductor current (IL) will be greater than output current (IOUT), such that: IL ~ IOUT · (VOUT / VIN).

Overcurrent Detection

The LTC4020 also contains an overcurrent detection circuit that monitors the low side current sense resistor, or SENSBOT–SENSGND input. Should that circuit detect a voltage on that input that is less than –150mV or greater than 100mV, or roughly 3x the maximum average current, all of the switches are disabled for four (4) clock cycles. Parasitic inductances on non-ideal layouts and or body-diode commutation charge can cause voltage spikes across the sense resistor at the beginning of synchronous FET conduction. The LTC4020 overcurrent circuitry is somewhat resistant to these leading edge spikes but, in some cases, the overcurrent circuit can be prematurely triggered. This is identified by the repeated 4-cycle switch off-time that occurs should premature triggering occur. Placing a ceramic capacitor across the SENSBOT–SENSGND input pins near the IC will generally eliminate premature triggering by low pass filtering the current sense signal. Setting the τ of the effective filter in the range of 1ns is generally sufficient to shunt errant signals, such that: CSENSB ~ 1ns / RSENSEB.

Programming Switching Frequency

The RT frequency adjust pin allows the user to program the LTC4020 DC/DC converter operating frequency from 50kHz to 500kHz. Higher frequency operation is desirable for smaller external inductor and capacitor values, but at the expense of increased switching losses and higher gate drive currents. Higher frequencies may also not allow sufficiently high or low duty cycle operation due to minimum on/off time constraints. Lower operating frequencies require larger external component values, but result in reduced switching losses yielding higher conversion efficiencies. Operating frequency (fO) is set by choosing an appropriate frequency setting resistor (RRT), connected from the RT pin to ground. This resistor is required for operation; do not leave this pin open. For a desired operating frequency, RRT follows the relation: RRT = 100k · (250kHz / fO)^-1.0695.

Input Supply Decoupling

The LTC4020 is typically biased directly from the charger input supply through the PVIN and SENSVIN pins. This supply provides large switched currents, so a high quality, low ESR decoupling capacitor is recommended to minimize voltage glitches on the VIN supply. Placing a smaller ceramic capacitor (0.1µF to 10µF) close to the IC in parallel with the input decoupling capacitor is also recommended for high frequency noise reduction. The SENSVIN pin is a Kelvin connection from the VIN supply at the primary VIN side switch FET (A); separate decoupling for that pin is not recommended. The charger input supply decoupling capacitor (CVIN) absorbs all input switching ripple current in the charger, so it must have an adequate ripple current rating. RMS ripple current (ICVIN(RMS)) is highest during step down operation, and follows the relation: ICVIN(RMS) ~ IMAX · DC · √(1 / DC), which has a maximum at DC = 0.5, or VIN = 2 · VOUT, where: ICVIN(RMS) = IMAX / 2. The simple worst-case of ½ · IMAX is commonly used for design, where IMAX is the programmed inductor current limit.

Bulk capacitance (CIN(BULK)) is a function of desired input ripple voltage (VIN). For step-down operation, CIN(BULK) follows the relation: CIN(BULK) ≥ IMAX · (VOUT(MAX) – VIN(MIN)) / (VIN · fO). where fO is the operating frequency, VOUT(MAX) is the DC/DC converter maximum output voltage and VIN(MIN) is the regulation voltage corresponding to 2.5V on VIN_REG. If the input regulation feature is not being used, use the minimum expected input operating voltage.

If an application does not require step-down operation, during step-up operation, input ripple current is equivalent to inductor ripple current (IMAX), so CIN(BULK) follows the relation: CIN(BULK) ≥ IMAX / (VIN · fO).

ILIMIT Pin

Maximum average inductor current can be dynamically adjusted using the ILIMIT pin as described in the Pin Functions section. Active servos can also be used to impose voltages on the ILIMIT pin, provided they can only sink current. Active circuits that source current must not be used to drive the ILIMIT pin.

Inductor Selection

The primary criterion for inductor value selection in an LTC4020 charger is the ripple current created in that inductor. Once the inductance value is determined, an inductor must also have a saturation current equal to or exceeding the maximum peak current in the inductor. An inductor value (L) is calculated based on the maximum desired amount of peak-to-peak ripple current, IMAX. The ripple current can be expressed as α, the ratio of the peak-to-peak ripple current to the maximum average inductor current, IMAX.

α = IMAX / IMAX. A range of 0.2 to 0.5 for α is typical. When stepping down, ripple current gets larger with increased VIN, and is maximized when VOUT = VIN/2. When stepping up, ripple current gets larger with increased VOUT, and is maximized when VIN = VOUT/2. The inductor value must be chosen using the greatest expected operational difference between these values.

A minimum inductor value for a given maximum ripple current and operating frequency (fO) can be determined using whichever relation yields the largest inductor value for LMIN:

If VIN > VOUT (step-down conversion): LMIN = [VOUT · (1 – VOUT/VIN(MAX)) ] / (fO · α · IMAX).

If VIN < VOUT (step-up conversion): LMIN = [VIN · (1 – VIN/VOUT(MAX)) ] / (fO · α · IMAX).

For step-down conversion, use the maximum expected operating voltage for VIN(MAX). If the expected VOUT operating range (typically from VFBMIN = 2.125V to VFBMAX = 2.75V) includes VIN(MAX)/2, use that value for VOUT. If the entire operating range is below VIN(MAX)/2, use the value corresponding to VFBMAX = 2.75V. If the entire operating range is above VIN(MAX)/2, use the value corresponding to VFBMIN = 2.125V.

For step-up conversion, use the maximum output voltage (typically corresponding to pin VFBMAX = 2.75V) for VOUT(MAX). If the expected VIN operating range includes VOUT(MAX)/2, use that value for VIN. If the entire input operating range is below VOUT(MAX)/2, use the maximum operating voltage for VIN. If the entire input operating range is above VOUT(MAX)/2, use the minimum input operating voltage for VIN.

Output Decoupling

During periods when the LTC4020 DC/DC converter output is not connected to the battery through the PowerPath FET, the system load is driven directly by the converter. The converter creates large switched currents, so a high quality, low ESR decoupling capacitor is recommended to minimize voltage glitches on the VOUT supply. Placing a smaller ceramic decoupling capacitor (0.1µF to 10µF) in parallel with the output decoupling capacitor is also recommended for high frequency noise reduction. The VOUT decoupling capacitor (CVOUT) absorbs the majority of the converter ripple current, so it must have an adequate ripple current rating. RMS ripple current (IRMS) is highest during step up operation, and follows the relation: IRMS ~ IMAX · DC · √(1 / DC), having a maximum at DC = 0.5, or VOUT = 2 · VIN, where: ICVOUT(RMS) = IMAX / 2. The simple worst-case of ½ · IMAX is commonly used for design, where IMAX is the programmed inductor current limit.

Bulk capacitance is a function of desired output ripple voltage (VOUT), and follows the relations: For step-up operation: COUT(BULK) ≥ IMAX · (VOUT(MAX) – VIN(MIN)) / (VOUT(MAX) · fO). where VOUT(MAX) is the DC/DC converter safety limit, and VIN(MIN) is the VIN regulation threshold. If the VIN regulation feature is not being used, use the minimum expected operating voltage. For step-down operation, output ripple current is equivalent to inductor ripple current (IMAX), so COUT(BULK) follows the relation: COUT(BULK) ≥ IMAX / (VOUT · fO).

Switch FET Selection

The LTC4020 requires four external N-channel power MOSFETs, as shown in Figure 3. Specified parameters used for power MOSFET selection are: breakdown voltage (VBR(DSS)), threshold voltage (VGS(TH)), on-resistance (RDS(ON)), reverse transfer capacitance (CRSS), and maximum inductor current (ILMAX). The drive voltage is set by the INTVCC supply pin, which is typically 5V. Consequently, logic-level threshold MOSFETs must be used in LTC4020 applications.

Transition Losses (PTR): During maximum power operation, all 4 switches change state once per oscillator cycle, so the maximum switching transient power losses (PTR) remain constant over condition. PTR(A, B) ≈ (k)(VIN)² (ILMAX)(CRSS)(fO). PTR(C, D) ≈ (k)(VOUT)² (ILMAX)(CRSS)(fO). PTR(A, B) is the transition loss for the VIN side switch FETs A and B, and PTR(C,D) is the transition loss for VOUT side switch FETs C and D, with the switch FETs designated as in Figure 3. The constant k, which accounts for the loss caused by reverse recovery current, is inversely proportional to the gate drive current and has a empirical value approximated by k = 1 in LTC4020 applications. ILMAX is the converter maximum inductor current as programmed by the two sense resistors. CRSS, the MOSFET reverse transfer capacitance, is specified by the MOSFET manufacturer.

Conductive Losses (PON): Conductive losses are proportional to switch duty cycle. The average conductive losses in a switch at maximum inductor current (ILMAX)is: PON = ILMAX² · T · RDS(ON) · (TON · fO), where T is a normalization factor (unity at 25°C) accounting for the significant variation in on-resistance with temperature. For a maximum junction temperature of 125°C, using a value of T = 1.5 is reasonable.

If VIN > VOUT (step-down conversion): PON(A) = ILMAX² · T · RDS(ON(A)) · (VOUT/VIN). PON(B) = ILMAX² · T · RDS(ON(B)) · (1 – VOUT/VIN). PON(C+D) = ILMAX² · T · RDS(ON(C, D)).

If VIN < VOUT (step-up conversion): PON(A+B) = ILMAX² · T · RDS(ON(A, B)). PON(C) = ILMAX² · T · RDS(ON(C)) · (1 – VIN/VOUT). PON(D) = ILMAX² · T · RDS(ON(D)) · (VIN/VOUT).

Optional Schottky Diode (Db, Dd) Selection

Schottky diodes can be placed in parallel with the synchronous FETs B and D, as shown in Figure 3 as Db and Dd. These diodes conduct during the dead time between the conduction of the power MOSFET switches and are intended to prevent the body diode of synchronous switches from storing charge. To maximize effectiveness of the diodes, the inductance between the switches and the synchronous switches must be minimized, so the diodes should be placed adjacent to their corresponding FET switch. The Dd diode also reduces power dissipation in the D switch during periods of reverse current inhibit operation, during which time the D switch is disabled. Load currents are low during reverse inhibit, and diode Db only conducts during switch dead times, so both can have current ratings well below the DC/DC converter inductor current maximum. Typically, a diode with an average current rating at or above one-tenth of ILMAX is adequate, provided the diode has an instantaneous current rating that exceeds the maximum inductor current, or ILMAX + ½ ΔIMAX. Db reverse voltage rating must exceed VIN. Dd reverse voltage rating must exceed VOUT.

INTVCC LDO Output, and BST1 and BST2 Supplies

Power for the top and bottom MOSFET drivers and most other internal circuitry is derived from the INTVCC pin. An internal 5V low dropout regulator (LDO) supplies INTVCC power from the PVIN pin. INTVCC is decoupled to PGND using a 2.2µF ceramic capacitor. The BST1 and BST2 bootstrapped supply pins power internal high side FET gate drivers, which output to pins TG1 and TG2. BST1 provides switch gate drive above the input power supply voltage for switch FET A, and BST2 provides switch gate drive above the output power supply voltage for switch FET D, as designated in Figure 3. These boosted supply pins allows the use of NFET switches for increased conversion efficiency. These bootstrapped supplies are regenerated through external Schottky diodes from the INTVCC pin. Connect two low leakage 1A Schottky diode anodes to the INTVCC pin. Connect one Schottky cathode to the BST1 pin. This diode must be rated for reverse voltage standoff exceeding the maximum input supply voltage. Connect the other diode cathode to the BST2 pin. This diode must be rated for reverse voltage standoff exceeding the converter safety limit output, VOUT(MAX). Connect a ceramic capacitor from the BST1 pin to the SW1 pin and another from BST2 pin to the SW2 pin. The value of these two capacitors should be at least 50 times greater than the equivalent total gate capacitance of the corresponding switch FET. Total FET gate charge (QG(TOT)) is typically specified at a specific gate-source voltage (VGS(Q)). Using those parameters, the required boost capacitor values (CBST) follow the relation: CBST > 50 · QG(TOT)/VGS(Q). CBST = 1µF is typically adequate for most applications. During low load operation, start-up, and nonoverlap periods, inductor current is conducted by the silicon body diode of the synchronous FET. This diode stores a significant amount of charge, so when the primary switch turns on for the next switch cycle, reverse recovery current is conducted by the main switch to discharge this diode. The resultant short-duration current spike can be orders of magnitude greater than the inductor current itself, resulting in an extremely fast dV/dt on the switched node. Consequently, parasitic inductance associated with the switch FET packaging and/or less-than-ideal layout can induce a voltage spike of 10 or more volts at the leading edge of a switching cycle. This can be particularly problematic on the step-up side of the inductor, as these voltage spikes are negative, and can cause a build-up of voltage on the BST2-SW2 capacitor. This would generally occur when the step-up synchronous switch (D) is disabled, such as during low load operation and during start-up. If voltage build-up on the boosted supply proves excessive, it could potentially violate absolute maximum voltage ratings of the IC and cause damage. This effect can be greatly reduced by implementing a Schottky diode across the step-up synchronous FET, shown as DD in Figure 3, which reduces reverse recovery charge in the synchronous FET body diode. A low current 6V Zener (0.1A) in parallel with the BST2-SW2 capacitor will also effectively shunt any errant charge and prevent excessive voltage build-up.

External Power for BST1 and BST2 Supplies: Power for the top and bottom MOSFET drivers can be supplied by an external supply, provided that a precision 5V supply is available (±5%). The INTVCC internal supply is a linear regulator, which transfers current from the VIN pin. As such, power dissipation can be excessive with high VIN pin voltages and/ or large gate drive requirements. The power dissipation in the linear pass element (PINTVCC) is: PINTVCC = (VIN – 5V) · QG(TOT)ABCD · fO, where QG(TOT)ABCD is the sum of all four switch total gate charges, and fO is the LTC4020 switching frequency.

BATTERY CHARGER SECTION

Battery Charge Voltage Programming

The LTC4020 uses an external feedback resistive divider from the BAT pin to ground to program battery voltages. This divider provides feedback to the VFB pin, and sets the final voltage that the battery charger will achieve at the end of a charge cycle. The feedback reference of 2.5V corresponds to the battery float voltage during CC/CV mode charging (MODE = 0V). The resultant feedback signal is compared with the internal 2.5V voltage reference by the converter error amplifier. The output voltage is given by the equation: V(FLOAT(CC/CV) = 2.5V · (1 + RFB1 / RFB2), where RFB1 and RFB2 are defined as in Figure 12.

If charging in CC mode (MODE = NC), RFB1 and RFB2 corresponding to VFB = 2.5V programs a maximum VBAT voltage, if constant-voltage functionality at that level if desired.

During lead-acid charging (MODE = INTVCC), the absorption mode voltage corresponds to 2.5V on the VFB pin. Battery float voltage (maintenance) corresponds to 2.3125V on the VFB pin, or 92.5% of the absorption voltage. These voltages typically correspond to 14.4V and 13.3V respectively for a 6-cell (12V) battery.

The values for RFB1 and RFB2 are typically the same as those used for the divider that programs the converter safety limit (converter output to the VFBMAX pin; see DC/ DC Converter Section), which yields a DC/DC converter maximum regulation voltage, or safety limit, that is 10% higher than the maximum battery charge voltage.

RCS: Battery Charge Current Programming

The LTC4020 senses battery charge current using a sense resistor that is connected between the CSP and CSN pins. Maximum average battery charge current (ICSMAX) is programmed by setting the value of this current sense resistor. The resistor value is selected so the desired maximum charge current through that sense resistor creates a 50mV drop, or: RCS = 0.05V / ICSMAX.

PowerPath FET Function and Instant-On

The LTC4020 controls an external PMOS with its gate connected to the BGATE pin. This PowerPath FET controls current flow to and from the battery. During a normal battery charge cycle, the BGATE pin is pulled low (clamped at VGS = 9.5V), which operates the FET as a low impedance connection from the DC/DC converter output to the battery, effectively shorting the battery to the converter output. This minimizes power dissipation from charge current passing thorough the FET. When there is no VIN power or when the IC is in shutdown, LTC4020 connects the battery to the converter output by holding the BGATE pin low, again effectively shorting the battery to the converter output. This minimizes power dissipation while the output is powered by the battery.

The LTC4020 controls the PowerPath FET to perform instant-on operation when a charge cycle is initiated into a heavily discharged battery. If the battery voltage is below a programmed minimum operational output voltage, corresponding to VFBMIN = 2.125V, the PowerPath FET is configured as a linear regulator, allowing the DC/DC converter output to rise above the battery voltage while still providing charge current into the battery. During instant-on operation, the BGATE pin is driven by the LTC4020 to maintain the minimum programmed voltage on the PowerPath FET source, the FET acting as a high impedance current source, providing charge current to the battery, independent of the battery voltage.

The resultant feedback signal is compared with the internal 2.125V voltage reference by a dedicated instant-on error amplifier, the output of which servos the BGATE pin. The output voltage is given by the equation: VOUT = 2.125V · (1 + RMIN1 / RMIN2), where RMIN1 and RMIN2 are defined as in Figure 14.

The values for RMIN1 and RMIN2 are typically the same as those used for the divider that programs battery voltage (to the VFB pin; see Battery Charger Section), to yield a DC/DC converter minimum operational regulation voltage corresponding to 85% of the battery charge voltage.

During instant-on operation, if the drain-to-source voltage across the PowerPath FET (VCSN – VBAT) exceeds 0.45V, the maximum charge current is automatically reduced. Maximum charge current is reduced linearly across the range of 0.45V < VCSN – VBAT < 1.95V to one-fifteenth of the current programmed by the battery charger sense resistor, RCS. This reduction in charge current helps to prevent excessive power dissipation in the PowerPath FET.

When the DC/DC converter is operating, but the battery charger is not in a charging cycle, the PowerPath FET is automatically configured as an ideal diode between the BAT pin (anode) and the CSN pin (cathode). The ideal diode function allows the battery to remain disconnected from the converter output while the converter is supplying power, but also allows the battery to be efficiently engaged for additional power should a load exceed the DC/DC converter's capability. This ideal diode circuit regulates the external FET to achieve low loss conduction, maintaining a voltage drop of 14mV across from the BAT pin to the CSN pin, provided the battery current load though the ideal diode does not exceed 14mV/RDS(ON). With larger currents, the FET will behave like a fixed value resistor equal to RDS(ON).

In certain applications, the PowerPath function is not required. For example, lead-acid chargers do not terminate (they remain in float charging mode indefinitely), so the battery need never be disconnected from the output, provided the instant-on feature is not desired. The PowerPath FET can be eliminated in these applications by tying the CSN side of the sense resistor to BAT, connecting VFBMIN to ground, and connecting a 100pF capacitor from the BGATE pin to CSN. See Typical Application Circuits section.

RNG/SS: Dynamic Current Limit Adjust

Maximum charge current can be dynamically adjusted using the RNG/SS pin as described in the Pin Functions section. Active servos can also be used to impose voltages on the RNG/SS pin, provided they can only sink current. Active circuits that source current cannot be used to drive the RNG/SS pin.

RNG/SS: Soft-Start

Soft-start functionality is also supported by the RNG/SS pin. 50µA is sourced from the RNG/SS pin, so connecting a capacitor from the RNG/SS pin to ground (CRNG/SS) creates a linear voltage ramp. The maximum charge current follows this voltage, thus increasing the charge current capability from zero to the full programmed value as the capacitor gets charged from 0 to 1V. The value of CRNG/SS is calculated based on the desired time to full current (TSS) following the relation: CRNG/SS = 50µA · TSS. The RNG/SS pin is pulled to ground internally when charging is terminated so each new charging cycle begins with a soft-start cycle. RNG/SS is also pulled to ground during bad battery and NTC fault conditions.

Status Pins

The LTC4020 reports charger status through two open collector outputs, the STAT1 and STAT2 pins. These pins can accept voltages as high as 55V when disabled, and can sink up to 5mA when enabled.

If the LTC4020 is configured for a CC/CV charging algorithm, the STAT1 pin is pulled low while battery charge currents exceed 10% of the programmed maximum (C/10). The STAT1 pin is also pulled low during NTC faults. The STAT2 pin is pulled low during NTC faults or after a bad battery fault occurs. The STAT1 pin becomes high impedance when a charge cycle is terminated or when charge current is below the C/10 threshold, and the STAT2 pin remains high impedance if no fault conditions are present.

If the LTC4020 is configured for a CC charging algorithm, the STAT1 pin is pulled low during the entire charging cycle, and the STAT2 pin is pulled low during NTC faults. The STAT1 pin becomes high impedance when the charge cycle is terminated.

If the LTC4020 is configured for a lead-acid charging algorithm, the STAT1 and STAT2 pins are used as charge cycle stage indicator pins. The STAT1 pin is pulled low during the bulk and absorption charging stages and is high impedance during the float charging period and during NTC or bad battery faults. The STAT2 pin is pulled low during bulk and float charging stages, and is high impedance during the absorption charging stage and during NTC or bad battery faults.

The STAT1 and STAT2 status pins are binary coded, and signal following the table below, where ON indicates pin pulled low, and OFF indicates pin high impedance:

TIMER: C/10 Termination

The LTC4020 supports a low current based termination scheme. This termination mode is engaged by shorting the TIMER pin to ground.

When in CC/CV charge mode, a battery charge cycle terminates when the current output from the charger falls to below one-tenth the maximum charge current, or ICSMAX, as programmed with RCS. The C/10 threshold current corresponds to 5mV across RCS.

During lead-acid charging, the LTC4020 initiates float charging when the absorption stage charge current is reduced to one-tenth of the programmed maximum current.

When charging in CC mode, the current source function remains active indefinitely.

There is no provision for bad battery detection if C/10 termination is used.

TIMER: Timed Functions

The LTC4020 supports timer based functions, where battery charge cycle control occurs after a specific amount of time elapses. Timer termination is engaged when a capacitor (CTIMER) is connected from the TIMER pin to ground. CTIMER for a desired end-of-cycle time (TEOC) follows the relation: CTIMER = TEOC · 6.87 · 10^-2 (µF), where TEOC is hours. A typical timer TEOC for Li-Ion charge cycle termination is three hours, which requires a 0.2µF timer capacitor. The timer cycle starts when the charger transitions from constant-current to constant-voltage charging, thus, termination at the end of the timer cycle only occurs if the charging cycle was successful. When timer termination is used, the STAT1 status pin is pulled low during a charging cycle until the battery charge current falls below the C/10 threshold. The STAT1 pin stays high impedance with charge currents below C/10, but the charger continues to top off the battery until timer TEOC, when the LTC4020 terminates the charging cycle and the PowerPath FET disconnects the battery from the DC/DC converter output.

During lead-acid charging, the timer acts as an absorption mode safety timer. Normally, the LTC4020 initiates float charging when the absorption stage charge current is reduced to one-tenth of the programmed maximum current, however, the maximum duration of absorption charging is limited by the timer. If the charge current does not fall to one-tenth of the programmed maximum current by TEOC, the LTC4020 forces the battery charger to begin float mode charging. A typical timer TEOC for lead-acid charging is six to eight hours, which is accommodated by a 0.47µF timer capacitor.

When charging in CC mode, after charge termination, once the timer reaches TEOC and the charge cycle terminates, input power or SHDN must be cycled to initiate another battery charge cycle.

A bad battery detection function is available during CC/CV or lead-acid charging. This fault condition is achieved if the battery does not respond to preconditioning (VFB < 1.75V), such that the charger remains in (or enters) precondition mode after one-eighth of the programmed TEOC time. A bad battery fault halts the charging cycle, and the fault condition is reported on the status pins. The bad battery fault remains active until the battery voltage rises above the precondition threshold, or until power or SHDN is cycled.

Battery Temperature Qualified Charging: NTC

The LTC4020 can accommodate battery temperature monitoring by using an NTC (negative temperature coefficient) thermistor close to the battery pack. The temperature monitoring function is enabled by connecting a 10k, β = 3380 NTC thermistor from the NTC pin to ground. If the NTC function is not desired, leave the pin unconnected.

The NTC pin sources 50µA, and monitors the voltage dropped across the 10k thermistor. When the voltage on this pin is above 1.35V (0°C) or below 0.3V (40°C), the battery temperature is out of range, and the LTC4020 triggers an NTC fault. The NTC fault condition remains until the voltage on the NTC pin corresponds to a temperature within the 0°C to 40°C range. Both hot and cold thresholds incorporate hysteresis that corresponds to 5°C.

If higher operational charging temperatures are desired, the temperature range can be expanded by adding series resistance to the 10k NTC resistor. Adding a 910 Ω resistor will increase the effective HOT temperature threshold to 45°C. The effect of this additional resistance on the COLD threshold is negligible.

During an NTC fault, charging is halted and an NTC fault is indicated on the status pins. If timer termination is enabled, the timer count is suspended and held until the fault condition is relieved. The RNG/SS pin is also pulled low during this fault, to accommodate a graceful restart, in the event that a soft-start function is being incorporated (see DRNG/SS: Dynamic Current Limit Adjust and RNG/ SS: Soft-Start section).

DC/DC CONVERTER: EXTERNAL COMPENSATION AND FILTERING COMPONENTS

The LTC4020 average current mode architecture employs two integrating compensation nodes. The current setting loop is compensated at the output of the current sense amplifier on the VC pin, generally with a series R-C network (RVC, CVC). The voltage generated on the VC pin is compared with an internal ramp, providing control of the converter duty cycle.

The voltage loop is compensated at the output of the error amplifier on the ITH pin, generally with a series R-C network (RITH, CITH). The voltage on the ITH pin is imposed onto the current sense amplifier, setting the current level to which the current loop will servo.

While determining compensation components, the LTC4020 should initially be configured to eliminate any functional contribution from the Battery Charger Section. This can be easily accomplished by connecting the NTC pin to ground, which disables all battery charging functions and puts the PowerPath FET into a high impedance state.

The current loop compensation (VC pin) transfer function crossover frequency is typically set to approximately one-half of the switching frequency; the voltage loop compensation (ITH pin) transfer function crossover frequency is typically set to approximately one-tenth of the switching frequency.

Compensation values must be tested at high and low input voltage operational limits, and also VIN ~ VOUT, so that stable operation during all switching modes (buck, boost, buck-boost) is verified.

If a network analyzer is not available for determining compensation values, use procedures as outlined in Application Note 19 for adjusting compensation.

VC pin compensation:

1. VNTC = VFBMAX = 0V
2. Fix VIN at typical voltage.
3. Fix VOUT at VFB regulation voltage. A charged battery, battery simulator, or a 2-quadrant power supply can be used for VOUT.
4. Impose 1V to 1.5V square wave (1kHz) on ITH pin
5. Monitor inductor current using current probe
6. Adjust compensation values as per Application Note 19 until response is critically damped

ITH pin compensation:

1. VNTC = 0V (disables charger)
2. Bring to regulation (VFBMAX = 2.75V)
3. Step load current on output (25% to 75% of IMAX)
4. Monitor VOUT voltage
5. Adjust compensation values as per Application Note 19 until response is critically damped and settled in ~10 to 25 cycles
6. VNTC = 0.8 (enable charger)
7. Exercise battery charger and verify stability in all modes

BATTERY CHARGER FUNCTIONS: FILTERING COMPONENTS

Voltage Regulation Loop (VFB)

The charger voltage regulation loop monitors battery voltage, and as such is controlled by a very slow moving node. Battery ESR, however, can produce significant AC voltages due to ripple currents, which can cause unstable operation. This ESR effect can be reduced by adding a capacitor to the VFB input, producing a low frequency pole.

Current Sense Regulation Loop (CSN, CSP)

The charger current regulation loop monitors and regulates battery charge current. Ripple voltage on the DC/DC converter output, however, gets directly imposed across the charger sense resistor, and can produce significant ripple currents. Large ripple currents can corrupt low level current sensing, and can also cause unstable operation. This ripple current effect can be greatly reduced by adding a capacitor (CCS) across the CSN and CSP pins, producing a low frequency pole with the two 100 Ω resistors that are required for those pins. The filter frequency is typically set to reduce voltage ripple across the current sense inputs at the CSP and CSN pins to less than 1mVP-P.

The ripple-reduction filter on the current sense inputs creates a phase shift in the charger current loop response, which can result in instability. A resistor (RCSZ) in series with CCS creates a zero that can be employed to recover phase margin. This zero setting resistor will reintroduce ripple error, so RCS should be minimized. CSOUT can be coupled into ITH for a similar feedforward zero with RCS = 0.

Current sense information, or differential voltage at the CSN to CSP pins, is amplified by a factor of 20 then output on pin CSOUT. This signal is compared to a reference voltage that is proportional to the maximum charge current at the input of a transconductance amplifier, which creates an error current that modulates the ITH compensation pin. A feedforward zero can be employed to recover phase margin by putting a capacitor from the CSOUT pin to the ITH pin (CCSOUT). The output impedance of the CSOUT pin is ~100k, so if compensation requirements are appropriate, the CCSOUT capacitor can perform double-duty as both the primary pole ITH capacitor along with a 100k zero-setting resistance, and as feed forward coupling from CSOUT to ITH.

Instant-On/Ideal Diode Regulation Loop (BGATE)

The instant-on function regulates the voltage across the PowerPath FET by servoing the voltage at the BGATE pin. Gate capacitance of the PowerPath FET is typically sufficient to stabilize this loop. Additional capacitance can be added to the BGATE pin (CBGATE) to stabilize the current foldback loop during instant-on operation if necessary:

LAYOUT CONSIDERATIONS

The LTC4020 is typically used in designs that involve substantial switching transients. The switch drivers on the IC are designed to drive large capacitances and, as such, generate significant transient currents themselves. Supply bypass capacitor locations must be carefully considered to avoid corrupting the signal ground reference (SGND) used by the IC. Typically, high current paths and transients from the input supply and any local drive supplies must be kept isolated from SGND, to which sensitive circuits such as the error amp reference and the current sense circuits are referred.

Effective grounding can be achieved by considering switch current in the ground plane, and the return current paths of each respective bypass capacitor. The VIN bypass return, INTVCC bypass return, and the sources of the ground-referred switch FETs carry PGND currents. SGND originates at the negative terminal of the VOUT bypass capacitor, and is the small signal reference for the LTC4020.

Do not be tempted to run small traces to separate ground paths. A good ground plane is important as always, but PGND referred bypass elements must be oriented such that transient currents in these return paths do not corrupt the SGND reference.

During the dead time between synchronous switch and main switch conduction, the body diode of the synchronous FET conducts inductor current. Commutating the body diode requires a significant charge contribution from the main switch during initiation of main switch, creating a current spike in the main switch. At the instant the body diode commutates, a current discontinuity is created between the inductor and main switch, with parasitic inductance causing the switch node to transition in response to this discontinuity. High currents and excessive parasitic inductance can generate extremely fast dV/dt times during this transition. These fast dV/dt transitions can sometimes cause avalanche breakdown in the synchronous FET body diode, generating shoot-through currents via parasitic turn-on of the synchronous FET. Layout practices and component orientations that minimize parasitic inductance on the switched nodes is critical for reducing these effects.

Orient power path components such that current paths in the ground plane do not cross through signal ground areas. Power ground currents are controlled on the LTC4020 via the PGND pin, and this ground references the high current synchronous switch drive components, as well as the local INTVCC supply. It is important to keep PGND and SGND voltages consistent with each other. Separating these grounds with thin traces is not recommended.

When a ground referenced switch FET is turned off, gate drive currents return to the LTC4020 PGND pin from the switch FET source. The BOOST supply refresh surge currents also return through this same path. The switch FETs must be oriented such that these PGND return currents do not corrupt the SGND reference.

The high i/Δt loop formed by the switch MOSFETs and the input capacitor (CVIN) should have short wide traces to minimize high frequency noise and voltage stress from inductive ringing. Surface mount components are preferred to reduce parasitic inductances from component leads. Switch path currents can be controlled by orienting switch FETs, the switched inductor, and input and output decoupling capacitors in close proximity to each other. Locate the INTVCC, BST1, and BST2 decoupling capacitors in close proximity to the IC. These capacitors carry the switch FET gate drive currents. Locate the small signal components away from high frequency switching nodes (TG1, BG1, TG2, BG2, SW1, SW2, BST1, BST2, and INTVCC). High current switching nodes are oriented across the top of the LTC4020 package to simplify layout and prevent corruption of the SGND reference.

Locate the output and battery charger feedback resistors in close proximity to the LTC4020 and minimize the length of the high impedance feedback nodes. The SENSVIN and SENSTOP traces should be routed together and SENSBOT and SENSGND should be routed together. Keep these traces as short as possible, and avoid corruption of these lines by high current switching nodes. The LTC4020 packaging has been designed to efficiently remove heat from the IC via the exposed pad on the backside of the package. The exposed pad is soldered to a copper footprint on the PCB. The exposed pad is electrically connected to SGND, so a good connection to a PCB ground plane effectively reduces the thermal resistance of the IC case to ambient air. Please refer to Application Note 136, which discusses guidelines, techniques, and considerations for switching power supply PCB design and layout.

Typical Application Schematics

Package Description

Revision History