Seeed Studio BeagleBone® Green Eco User Guide
1. Seeed Studio BeagleBone® Green Eco Overview
This document provides a comprehensive guide to the Seeed Studio BeagleBone® Green Eco, an industrial-grade open-source hardware development platform.
1.1 Introduction
The Seeed Studio BeagleBone® Green Eco is powered by the AM335x ARM Cortex-A8 processor. It features high-quality components for wide temperature ranges, enhanced power stability, and improved signal integrity, making it suitable for commercial and light industrial applications. This board is part of the Seeed Studio BeagleBone Green family, developed in partnership with BeagleBoard.org®, and is based on the BeagleBone Black's schematic design and software. It includes 16GB of onboard eMMC storage, a high-performance Gigabit Ethernet connection for substantial data throughput, and a USB Type-C port for power and communication. The familiar BeagleBoard.org® BeagleBone® form factor is preserved, along with two Grove connectors for simplified sensor integration.
Board Image Description: A top-down view of the Seeed Studio BeagleBone® Green Eco circuit board, showing various components including the AM335x processor, Kingston RAM and eMMC storage chips, Ethernet port, USB Type-C port, USB Type-A port, Grove connectors, and expansion headers (P8 and P9).
1.2 Kit Contents
This package includes:
- Seeed Studio BeagleBone® Green Eco *1
- USB Type-C Cable *1
- User Guide *1
1.3 Hardware Specification
The Seeed Studio BeagleBone® Green Eco is built around the Texas Instruments AM335x ARM Cortex-A8 processor, providing a robust foundation for diverse embedded applications. The following table details the key components and capabilities.
Category | Item | Specification |
---|---|---|
Processor | Core | TI AM335x 1GHz ARM® Cortex-A8 |
Accelerators | NEON floating-point unit & 3D graphics accelerator | |
Memory | RAM | 512MB DDR3L, 800MHz |
Flash Storage | 16GB eMMC | |
EEPROM | 32Kbit | |
External Storage | microSD card slot, supports up to 32GB | |
Power | Power Management | TI TPS6521403 PMIC |
Voltage Regulators | TI TPS62A01DRL (3.3V Buck converter), TPS2117DRL (Power Mux) | |
Input Voltage | 5V DC (via USB Type-C & Cape headers) | |
Operating Current | Max 614mA | |
Interfaces | USB | 1x USB 2.0 Host Type-A port for connecting peripherals (keyboard, mouse, WiFi adapter, etc.), 1x USB 2.0 Type-C for power and device communication |
Network | Gigabit Ethernet (10/100/1000Mbps) | |
Expansion Headers | 4x UART, 2x I2C, 1x SPI, 13x GPIO | |
Grove | 1x I2C, 1x UART | |
Buttons | 1x Reset button, 1x Wake up button, 1x User button | |
Indicators | 1x power LED, 4x user-programmable LEDs | |
Physical | Dimensions | 86.4mm x 53.3mm x 18mm |
Weight | 39.3g | |
Operating Temperature | -40~85℃ |
2. Hardware
The Seeed Studio BeagleBone® Green Eco features a high-performance, low-power system architecture based on the AM335x system-on-chip (SoC). This section details the specifications of its hardware subsystems, including processor, memory, power management, and interfaces.
2.1 Board Overview
The Seeed Studio BeagleBone® Green Eco utilizes a compact form factor with integrated components. Key functional blocks are illustrated in Figures 2-1 and 2-2, showing top and bottom PCB views.
2.2 Key Features
The Seeed Studio BeagleBone® Green Eco offers an optimized design compatible with the BeagleBoard.org® ecosystem. It features industrial-grade components, increased storage, faster networking, and modern connectivity options, ensuring reliable performance for development and production. The 4-layer PCB design balances signal integrity and manufacturing requirements. An efficient power management system ensures dependable operation across diverse applications, and familiar expansion interfaces maintain compatibility with existing hardware and software.
2.2.1 Processor
The Seeed Studio BeagleBone® Green Eco is equipped with the Texas Instruments AM335x 1GHz ARM® Cortex-A8 processor, which combines computational processing, graphics acceleration, and real-time control. It supports ARMv7-A with NEON™ SIMD engine and VFPv3 floating-point unit for efficient execution of complex tasks and power efficiency. A distinctive feature is the Programmable Real-time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS), comprising dual 32-bit RISC cores operating independently from the main ARM processor, enabling deterministic real-time control and specialized industrial communication protocols. The AM335x supports high-level operating systems like Linux and real-time operating systems via Tl's Processor SDK.
- AM335x 1GHz ARM® Cortex-A8 processor (15.0mm x 15.0mm, NFBGA (324))
- NEONT™ SIMD coprocessor and VFPv3 floating-point unit for accelerated media and signal processing
- PowerVR SGX™ Graphics Accelerator supporting OpenGL ES 2.0
- Dual 32-bit PRU-ICSS for real-time industrial communications and control
- Support for industrial interfaces including EtherCAT, PROFINET, and PROFIBUS
2.2.2 Memory and Storage
The Seeed Studio BeagleBone® Green Eco includes:
- 1x 512MB (4Gb) DDR3L RAM (Kingston D2516ECMDXGJDI-U) with 16-bit interface
- 1x 16GB eMMC onboard flash storage (Kingston EMMC16G-WW28) with MMC18-bit interface
- 1x 32Kbit EEPROM (FMD FT24C32A-ELRT) connected via I2C
- MicroSD card slot with MMC0 4-bit interface for expandable storage
2.2.3 Interfaces and Peripherals
The Seeed Studio BeagleBone® Green Eco supports:
- Gigabit Ethernet connectivity
- USB Host port for connecting external devices
- USB 2.0 Type-C port for power and communications
- 1x USB 2.0 Host Interface, Type-A
2.2.4 Expansion Connectors / Headers to Support Application Specific Capes
- Grove I2C Interface (J4)
- 1x 6-pins UARTO headers
- Two Grove connectors (One I2C and One UART) for easy connection to the Grove ecosystem of sensors and actuators
2.3 Power Requirements
The Seeed Studio BeagleBone® Green Eco is powered via its USB Type-C connector or the P9 expansion header, both serving as power input and communication interfaces. The board requires a 5V power supply.
2.3.1 Integrated Power Architecture
The board utilizes the TPS65214 Power Management IC (PMIC), an industrial-grade solution engineered for efficiency and reliability. This PMIC delivers comprehensive power management, complementing the board's industrial operating temperature range of -40°C to +85°C. The TPS65214 features three high-performance buck converters (2A, 1A, 1A) for stable power delivery and two low-dropout regulators (300mA, 500mA) for analog and sensitive components. It supports intelligent power management modes (forced-PWM and PFM) and operates at a 2.3MHz switching frequency.
2.3.2 Advanced Power Management Features
The TPS65214 incorporates a sophisticated system management architecture for reliability and flexibility. Its programmable power sequencing controller allows customization of startup and shutdown sequences. A comprehensive protection system monitors for undervoltage, overcurrent, short-circuit conditions, and thermal issues, with configurable fault response mechanisms.
2.4 Header Pin Definition
Expansion headers provide extensive I/O capabilities.
2.4.1 Cape Expansion Headers
Each digital I/O pin can be configured in 8 different modes, including GPIO. The following tables detail the pin assignments for the P8 and P9 expansion headers.
Figure 2-2. Expansion Header Pinout Diagram Description: Diagrams showing the pin layout for the P8 and P9 expansion headers, color-coded by function (Power/Ground/Reset, Available Digital, Available PWM, Shared I2C Bus, Reconfigurable Digital, Analog Inputs).
P9 | P8 | ||||||
---|---|---|---|---|---|---|---|
1 | 2 | 1 | 2 | ||||
DGND | DGND | DGND | DGND | ||||
VDD_3V3B | 3 | 4 | VDD_3V3 | GPIO1_6 | 3 | 4 | GPIO1_7 |
VDD_5V | 5 | 6 | VDD_5V | GPIO1_2 | 5 | 6 | GPIO1_3 |
SYS_5V | 7 | 8 | SYS_5V | GPIO2_2 | 7 | 8 | GPIO2_3 |
PWR_BUT | 9 | 10 | SYS_RESETn | GPIO2_5 | 9 | 10 | GPIO2_4 |
UART4_RXD | 11 | 12 | GPIO1_28 | GPIO1_13 | 11 | 12 | GPIO1_12 |
UART4_TXD | 13 | 14 | EHRPWM1A | GPIO0_23 | 13 | 14 | GPIO0_26 |
GPIO1_16 | 15 | 16 | EHRPWM1B | GPIO1_15 | 15 | 16 | GPIO1_14 |
I2C1_SCL | 17 | 18 | I2C1_SDA | GPIO0_27 | 17 | 18 | GPIO2_1 |
I2C2_SCL | 19 | 20 | I2C2_SDA | GPIO0_22 | 19 | 20 | GPIO1_31 |
UART2_TXD | 21 | 22 | UART2_RXD | GPIO1_31 | 21 | 22 | GPIO1_5 |
GPIO1_17 | 23 | 24 | UART1_TXD | GPIO1_4 | 23 | 24 | GPIO1_1 |
GPIO3_21 | 25 | 26 | UART1_RXD | GPIO1_0 | 25 | 26 | GPIO1_29 |
GPIO3_19 | 27 | 28 | SPI1_CSO | GPIO2_22 | 27 | 28 | GPIO2_24 |
SPI1_D0 | 29 | 30 | SPI1_D1 | GPIO2_23 | 29 | 30 | GPIO2_25 |
SPI1_SCLK | 31 | 32 | VDD_ADC | GPIO0_10 | 31 | 32 | GPIO0_11 |
AIN4 | 33 | 34 | GNDA_ADC | GPIO0_9 | 33 | 34 | GPIO2_17 |
AIN6 | 35 | 36 | AIN5 | GPIO0_8 | 35 | 36 | GPIO2_16 |
AIN2 | 37 | 38 | AIN3 | GPIO2_14 | 37 | 38 | GPIO2_15 |
AIN0 | 39 | 40 | AIN1 | GPIO2_12 | 39 | 40 | GPIO2_13 |
GPIO_20 | 41 | 42 | GPIO0_7 | GPIO2_10 | 41 | 42 | GPIO2_11 |
DGND | 43 | 44 | GPIO0_8 | GPIO2_8 | 43 | 44 | GPIO2_9 |
DGND | 45 | 46 | GPIO0_9 | GPIO2_6 | 45 | 46 | GPIO2_7 |
2.4.2 65 Possible Digital I/Os
In GPIO mode, each digital I/O can produce interrupts. The following tables detail the pin assignments for the P8 and P9 expansion headers.
Figure 2-3. 65 Possible Digital I/O Pinout Diagram Description: Diagrams showing the pin layout for the P8 and P9 expansion headers, color-coded by function (Power/Ground/Reset, Available Digital, Available PWM, Shared I2C Bus, Reconfigurable Digital, Analog Inputs).
P9 | P8 | ||||||
---|---|---|---|---|---|---|---|
1 | 2 | 1 | 2 | ||||
DGND | DGND | DGND | DGND | ||||
VDD_3V3 | 3 | 4 | VDD_3V3 | GPIO1_6 | 3 | 4 | GPIO1_7 |
VDD_5V | 5 | 6 | VDD_5V | GPIO1_2 | 5 | 6 | GPIO1_3 |
SYS_5V | 7 | 8 | SYS_5V | GPIO2_2 | 7 | 8 | GPIO2_3 |
PWR_BUT | 9 | 10 | SYS_RESETN | GPIO2_5 | 9 | 10 | GPIO2_4 |
GPIO0_30 | 11 | 12 | GPIO1_28 | GPIO1_13 | 11 | 12 | GPIO1_12 |
GPIO0_31 | 13 | 14 | GPIO1_18 | GPIO0_23 | 13 | 14 | GPIO0_26 |
GPIO1_16 | 15 | 16 | GPIO1_19 | GPIO1_15 | 15 | 16 | GPIO1_14 |
GPIO0_5 | 17 | 18 | GPIO0_4 | GPIO0_27 | 17 | 18 | GPIO2_1 |
GPIO0_13 | 19 | 20 | GPIO0_12 | GPIO0_22 | 19 | 20 | GPIO1_31 |
GPIO0_3 | 21 | 22 | GPIO0_2 | GPIO1_31 | 21 | 22 | GPIO1_5 |
GPIO1_17 | 23 | 24 | GPIO0_15 | GPIO1_4 | 23 | 24 | GPIO1_1 |
GPIO3_21 | 25 | 26 | GPIO0_14 | GPIO1_0 | 25 | 26 | GPIO1_29 |
GPIO3_19 | 27 | 28 | GPIO3_17 | GPIO2_22 | 27 | 28 | GPIO2_24 |
GPIO3_15 | 29 | 30 | GPIO3_16 | GPIO2_23 | 29 | 30 | GPIO2_25 |
GPIO3_14 | 31 | 32 | VDD_ADC | GPIO0_10 | 31 | 32 | GPIO0_11 |
AIN4 | 33 | 34 | GNDA_ADC | GPIO0_9 | 33 | 34 | GPIO2_17 |
AIN6 | 35 | 36 | AIN5 | GPIO0_8 | 35 | 36 | GPIO2_16 |
AIN2 | 37 | 38 | AIN3 | GPIO2_14 | 37 | 38 | GPIO2_15 |
AIN0 | 39 | 40 | AIN1 | GPIO2_12 | 39 | 40 | GPIO2_13 |
GPIO0_20 | 41 | 42 | GPIO0_7 | GPIO2_10 | 41 | 42 | GPIO2_11 |
GPIO3_20 | GPIO3_18 | GPIO2_8 | 43 | 44 | GPIO2_9 | ||
DGND | 43 | 44 | DGND | GPIO2_6 | 45 | 46 | GPIO2_7 |
DGND | 45 | 46 | DGND |
2.4.3 PWMs and Timers
Up to 8 digital I/O pins can be configured with pulse-width modulators (PWM) to produce signals to control motors or create pseudo analog voltage levels, without taking up any extra CPU cycles. The following tables detail the pin assignments for the P8 and P9 expansion headers.
Figure 2-4. PWMs and Timers Pinout Diagram Description: Diagrams showing the pin layout for the P8 and P9 expansion headers, color-coded by function (Power/Ground/Reset, Available Digital, Available PWM, Shared I2C Bus, Reconfigurable Digital, Analog Inputs).
P9 | P8 | ||||||
---|---|---|---|---|---|---|---|
1 | 2 | 1 | 2 | ||||
DGND | DGND | DGND | DGND | ||||
VDD_3V3 | 3 | 4 | VDD_3V3 | GPIO1_6 | 3 | 4 | GPIO1_7 |
VDD_5V | 5 | 6 | VDD_5V | GPIO1_2 | 5 | 6 | GPIO1_3 |
SYS_5V | 7 | 8 | SYS_5V | TIMER4 | 7 | 8 | TIMER7 |
PWR_BUT | 9 | 10 | SYS_RESETn | TIMER5 | 9 | 10 | TIMER6 |
UART4_RXD | 11 | 12 | GPIO1_28 | GPIO1_13 | 11 | 12 | GPIO1_12 |
UART4_TXD | 13 | 14 | EHRPWM1A | EHRPWM2B | 13 | 14 | GPIO1_26 |
GPIO1_16 | 15 | 16 | EHRPWM1B | GPIO1_15 | 15 | 16 | GPIO1_14 |
I2C1_SCL | 17 | 18 | I2C1_SDA | GPIO1_27 | 17 | 18 | GPIO2_1 |
I2C2_SCL | 19 | 20 | I2C2_SDA | EHRPWM2A | 19 | 20 | MMC1_CMD |
UART2_TXD | 21 | 22 | UART2_RXD | MMC1_CLK | 21 | 22 | MMC1_DAT5 |
GPIO1_17 | 23 | 24 | UART1_TXD | MMC1_DAT4 | 23 | 24 | MMC1_DAT1 |
GPIO3_21 | 25 | 26 | UART1_RXD | MMC1_DATO | 25 | 26 | GPIO1_29 |
GPIO3_19 | 27 | 28 | SPI1_CSO | LCD_VSYNC | 27 | 28 | LCD_PCLK |
SPI1_D0 | 29 | 30 | SPI1_D1 | LCD_HSYNC | 29 | 30 | LCD_DE |
SPI1_SCLK | 31 | 32 | VDD_ADC | LCD_DATA14 | 31 | 32 | LCD_DATA15 |
AIN4 | 33 | 34 | GNDA_ADC | LCD_DATA13 | 33 | 34 | LCD_DATA11 |
AIN6 | 35 | 36 | AIN5 | LCD_DATA12 | 35 | 36 | LCD_DATA10 |
AIN2 | 37 | 38 | AIN3 | LCD_DATA8 | 37 | 38 | LCD_DATA9 |
AIN0 | 39 | 40 | AIN1 | LCD_DATA6 | 39 | 40 | LCD_DATA7 |
GPIO_20 | 41 | 42 | GPIO0_7 | LCD_DATA4 | 41 | 42 | LCD_DATA5 |
DGND | 43 | 44 | GPIO0_8 | GPIO2_8 | 43 | 44 | GPIO2_9 |
DGND | 45 | 46 | GPIO0_9 | GPIO2_6 | 45 | 46 | GPIO2_7 |
2.4.4 Analog Inputs
Make sure you don't input more than 1.8V to the analog input pins. This is a single 12-bit analog-to-digital converter with 8 channels, 7 of which are made available on the headers. The following tables detail the pin assignments for the P8 and P9 expansion headers.
Figure 2-5. Analog Inputs Pinout Diagram Description: Diagrams showing the pin layout for the P8 and P9 expansion headers, color-coded by function (Power/Ground/Reset, Available Digital, Available PWM, Shared I2C Bus, Reconfigurable Digital, Analog Inputs).
P9 | P8 | ||||||
---|---|---|---|---|---|---|---|
1 | 2 | 1 | 2 | ||||
DGND | DGND | DGND | DGND | ||||
VDD_3V3 | 3 | 4 | VDD_3V3 | MMC1_DAT6 | 3 | 4 | MMC1_DAT7 |
VDD_5V | 5 | 6 | VDD_5V | MMC1_DAT2 | 5 | 6 | MMC1_DAT3 |
SYS_5V | 7 | 8 | SYS_5V | TIMER4 | 7 | 8 | TIMER7 |
PWR_BUT | 9 | 10 | SYS_RESETn | TIMER5 | 9 | 10 | TIMER6 |
UART4_RXD | 11 | 12 | GPIO1_28 | GPIO1_13 | 11 | 12 | GPIO1_12 |
UART4_TXD | 13 | 14 | EHRPWM1A | EHRPWM2B | 13 | 14 | GPIO1_26 |
GPIO1_16 | 15 | 16 | EHRPWM1B | GPIO1_15 | 15 | 16 | GPIO1_14 |
I2C1_SCL | 17 | 18 | I2C1_SDA | GPIO1_27 | 17 | 18 | GPIO2_1 |
I2C2_SCL | 19 | 20 | I2C2_SDA | EHRPWM2A | 19 | 20 | MMC1_CMD |
UART2_TXD | 21 | 22 | UART2_RXD | MMC1_CLK | 21 | 22 | MMC1_DAT5 |
GPIO1_17 | 23 | 24 | UART1_TXD | MMC1_DAT4 | 23 | 24 | MMC1_DAT1 |
GPIO3_21 | 25 | 26 | UART1_RXD | MMC1_DATO | 25 | 26 | GPIO1_29 |
GPIO3_19 | 27 | 28 | SPI1_CSO | LCD_VSYNC | 27 | 28 | LCD_PCLK |
SPI1_D0 | 29 | 30 | SPI1_D1 | LCD_HSYNC | 29 | 30 | LCD_DE |
SPI1_SCLK | 31 | 32 | VDD_ADC | LCD_DATA14 | 31 | 32 | LCD_DATA15 |
AIN4 | 33 | 34 | GNDA_ADC | LCD_DATA13 | 33 | 34 | LCD_DATA11 |
AIN6 | 35 | 36 | AIN5 | LCD_DATA12 | 35 | 36 | LCD_DATA10 |
AIN2 | 37 | 38 | AIN3 | LCD_DATA8 | 37 | 38 | LCD_DATA9 |
AIN0 | 39 | 40 | AIN1 | LCD_DATA6 | 39 | 40 | LCD_DATA7 |
GPIO_20 | 41 | 42 | GPIO0_7 | LCD_DATA4 | 41 | 42 | LCD_DATA5 |
DGND | 43 | 44 | GPIO0_8 | LCD_DATA2 | 43 | 44 | LCD_DATA3 |
DGND | 45 | 46 | GPIO0_9 | LCD_DATA0 | 45 | 46 | LCD_DATA1 |
2.4.5 UART
There is a dedicated header for the UARTO pins and connecting a debug cable. Five additional serial ports are brought to the expansion headers, but one of them only has a single direction to the headers. The following tables detail the pin assignments for the P8 and P9 expansion headers.
Figure 2-6. UART Pinout Diagram Description: Diagrams showing the pin layout for the P8 and P9 expansion headers, color-coded by function (Power/Ground/Reset, Available Digital, Available PWM, Shared I2C Bus, Reconfigurable Digital, Analog Inputs).
P9 | P8 | ||||||
---|---|---|---|---|---|---|---|
1 | 2 | 1 | 2 | ||||
DGND | DGND | DGND | DGND | ||||
VDD_3V3 | 3 | 4 | VDD_3V3 | MMC1_DAT6 | 3 | 4 | MMC1_DAT7 |
VDD_5V | 5 | 6 | VDD_5V | MMC1_DAT2 | 5 | 6 | MMC1_DAT3 |
SYS_5V | 7 | 8 | SYS_5V | TIMER4 | 7 | 8 | TIMER7 |
PWR_BUT | 9 | 10 | SYS_RESETn | TIMER5 | 9 | 10 | TIMER6 |
UART4_RXD | 11 | 12 | GPIO1_28 | GPIO1_13 | 11 | 12 | GPIO1_12 |
UART4_TXD | 13 | 14 | EHRPWM1A | EHRPWM2B | 13 | 14 | GPIO1_26 |
GPIO1_16 | 15 | 16 | EHRPWM1B | GPIO1_15 | 15 | 16 | GPIO1_14 |
I2C1_SCL | 17 | 18 | I2C1_SDA | GPIO1_27 | 17 | 18 | GPIO2_1 |
I2C2_SCL | 19 | 20 | I2C2_SDA | EHRPWM2A | 19 | 20 | MMC1_CMD |
UART2_TXD | 21 | 22 | UART2_RXD | MMC1_CLK | 21 | 22 | MMC1_DAT5 |
GPIO1_17 | 23 | 24 | UART1_TXD | MMC1_DAT4 | 23 | 24 | MMC1_DAT1 |
GPIO3_21 | 25 | 26 | UART1_RXD | MMC1_DATO | 25 | 26 | GPIO1_29 |
GPIO3_19 | 27 | 28 | SPI1_CSO | LCD_VSYNC | 27 | 28 | LCD_PCLK |
SPI1_D0 | 29 | 30 | SPI1_D1 | LCD_HSYNC | 29 | 30 | LCD_DE |
SPI1_SCLK | 31 | 32 | VDD_ADC | LCD_DATA14 | 31 | 32 | LCD_DATA15 |
AIN4 | 33 | 34 | GNDA_ADC | LCD_DATA13 | 33 | 34 | LCD_DATA11 |
AIN6 | 35 | 36 | AIN5 | LCD_DATA12 | 35 | 36 | LCD_DATA10 |
AIN2 | 37 | 38 | AIN3 | LCD_DATA8 | 37 | 38 | LCD_DATA9 |
AIN0 | 39 | 40 | AIN1 | LCD_DATA6 | 39 | 40 | LCD_DATA7 |
GPIO_20 | 41 | 42 | GPIO0_7 | LCD_DATA4 | 41 | 42 | LCD_DATA5 |
DGND | 43 | 44 | GPIO0_8 | LCD_DATA2 | 43 | 44 | LCD_DATA3 |
DGND | 45 | 46 | GPIO0_9 | LCD_DATA0 | 45 | 46 | LCD_DATA1 |
2.4.6 I2C
The first I2C bus is utilized for reading EEPROMs on cape add-on boards and cannot be used for other digital I/O operations without interfering. The second I2C bus is available for configuration and use. The following tables detail the pin assignments for the P8 and P9 expansion headers.
Figure 2-7. I2C Pinout Diagram Description: Diagrams showing the pin layout for the P8 and P9 expansion headers, color-coded by function (Power/Ground/Reset, Available Digital, Available PWM, Shared I2C Bus, Reconfigurable Digital, Analog Inputs).
P9 | P8 | ||||||
---|---|---|---|---|---|---|---|
1 | 2 | 1 | 2 | ||||
DGND | DGND | DGND | DGND | ||||
VDD_3V3B | 3 | 4 | VDD_3V3 | MMC1_DAT6 | 3 | 4 | MMC1_DAT7 |
VDD_5V | 5 | 6 | VDD_5V | MMC1_DAT2 | 5 | 6 | MMC1_DAT3 |
SYS_5V | 7 | 8 | SYS_5V | TIMER4 | 7 | 8 | TIMER7 |
PWR_BUT | 9 | 10 | SYS_RESETn | TIMER5 | 9 | 10 | TIMER6 |
UART4_RXD | 11 | 12 | GPIO1_28 | GPIO1_13 | 11 | 12 | GPIO1_12 |
UART4_TXD | 13 | 14 | EHRPWM1A | EHRPWM2B | 13 | 14 | GPIO1_26 |
GPIO1_16 | 15 | 16 | EHRPWM1B | GPIO1_15 | 15 | 16 | GPIO1_14 |
I2C1_SCL | 17 | 18 | I2C1_SDA | GPIO1_27 | 17 | 18 | GPIO2_1 |
I2C2_SCL | 19 | 20 | I2C2_SDA | EHRPWM2A | 19 | 20 | MMC1_CMD |
UART2_TXD | 21 | 22 | UART2_RXD | MMC1_CLK | 21 | 22 | MMC1_DAT5 |
GPIO1_17 | 23 | 24 | UART1_TXD | MMC1_DAT4 | 23 | 24 | MMC1_DAT1 |
GPIO3_21 | 25 | 26 | UART1_RXD | MMC1_DATO | 25 | 26 | GPIO1_29 |
GPIO3_19 | 27 | 28 | SPI1_CSO | LCD_VSYNC | 27 | 28 | LCD_PCLK |
SPI1_D0 | 29 | 30 | SPI1_D1 | LCD_HSYNC | 29 | 30 | LCD_DE |
SPI1_SCLK | 31 | 32 | VDD_ADC | LCD_DATA14 | 31 | 32 | LCD_DATA15 |
AIN4 | 33 | 34 | GNDA_ADC | LCD_DATA13 | 33 | 34 | LCD_DATA11 |
AIN6 | 35 | 36 | AIN5 | LCD_DATA12 | 35 | 36 | LCD_DATA10 |
AIN2 | 37 | 38 | AIN3 | LCD_DATA8 | 37 | 38 | LCD_DATA9 |
AIN0 | 39 | 40 | AIN1 | LCD_DATA6 | 39 | 40 | LCD_DATA7 |
CLKOUT2 | 41 | 42 | GPIO0_7 | LCD_DATA4 | 41 | 42 | LCD_DATA5 |
DGND | 43 | 44 | GPIO0_8 | LCD_DATA2 | 43 | 44 | LCD_DATA3 |
DGND | 45 | 46 | GPIO0_9 | LCD_DATA0 | 45 | 46 | LCD_DATA1 |
2.4.7 SPI
For shifting out data fast, you might consider using one of the SPI ports. The following tables detail the pin assignments for the P8 and P9 expansion headers.
Figure 2-8. SPI Pinout Diagram Description: Diagrams showing the pin layout for the P8 and P9 expansion headers, color-coded by function (Power/Ground/Reset, Available Digital, Available PWM, Shared I2C Bus, Reconfigurable Digital, Analog Inputs).
P9 | P8 | ||||||
---|---|---|---|---|---|---|---|
1 | 2 | 1 | 2 | ||||
DGND | DGND | DGND | DGND | ||||
VDD_3V3B | 3 | 4 | VDD_3V3 | MMC1_DAT6 | 3 | 4 | MMC1_DAT7 |
VDD_5V | 5 | 6 | VDD_5V | MMC1_DAT2 | 5 | 6 | MMC1_DAT3 |
SYS_5V | 7 | 8 | SYS_5V | TIMER4 | 7 | 8 | TIMER7 |
PWR_BUT | 9 | 10 | SYS_RESETn | TIMER5 | 9 | 10 | TIMER6 |
UART4_RXD | 11 | 12 | GPIO1_28 | GPIO1_13 | 11 | 12 | GPIO1_12 |
UART4_TXD | 13 | 14 | EHRPWM1A | EHRPWM2B | 13 | 14 | GPIO1_26 |
GPIO1_16 | 15 | 16 | EHRPWM1B | GPIO1_15 | 15 | 16 | GPIO1_14 |
I2C1_SCL | 17 | 18 | I2C1_SDA | GPIO1_27 | 17 | 18 | GPIO2_1 |
I2C2_SCL | 19 | 20 | I2C2_SDA | EHRPWM2A | 19 | 20 | MMC1_CMD |
UART2_TXD | 21 | 22 | UART2_RXD | MMC1_CLK | 21 | 22 | MMC1_DAT5 |
GPIO1_17 | 23 | 24 | UART1_TXD | MMC1_DAT4 | 23 | 24 | MMC1_DAT1 |
GPIO3_21 | 25 | 26 | UART1_RXD | MMC1_DATO | 25 | 26 | GPIO1_29 |
GPIO3_19 | 27 | 28 | SPI1_CSO | LCD_VSYNC | 27 | 28 | LCD_PCLK |
SPI1_D0 | 29 | 30 | SPI1_D1 | LCD_HSYNC | 29 | 30 | LCD_DE |
SPI1_SCLK | 31 | 32 | VDD_ADC | LCD_DATA14 | 31 | 32 | LCD_DATA15 |
AIN4 | 33 | 34 | GNDA_ADC | LCD_DATA13 | 33 | 34 | LCD_DATA11 |
AIN6 | 35 | 36 | AIN5 | LCD_DATA12 | 35 | 36 | LCD_DATA10 |
AIN2 | 37 | 38 | AIN3 | LCD_DATA8 | 37 | 38 | LCD_DATA9 |
AIN0 | 39 | 40 | AIN1 | LCD_DATA6 | 39 | 40 | LCD_DATA7 |
CLKOUT2 | 41 | 42 | GPIO0_7 | LCD_DATA4 | 41 | 42 | LCD_DATA5 |
DGND | 43 | 44 | GPIO0_8 | LCD_DATA2 | 43 | 44 | LCD_DATA3 |
DGND | 45 | 46 | GPIO0_9 | LCD_DATA0 | 45 | 46 | LCD_DATA1 |
2.5 Detailed Hardware Design
The following sections provide an overview of the different interfaces and circuits on the Seeed Studio BeagleBone® Green Eco. Table 2-1 (not provided in OCR) shows the interface mapping for the board.
2.5.1 USB Interface
2.5.1.1 USB 2.0 Type-A Interface
The Seeed Studio BeagleBone® Green Eco features a USB 2.0 Type-A Host port for connecting various USB peripherals. USB 2.0 Data lines DP and DM from the Type-A connector are connected to the USB1 interface of the AM335x SoC, supporting USB high-speed/full-speed communication at rates up to 480Mbps. The Type-A connector can provide 5V power to connected USB devices, with a current-limiting circuit protecting the board from excessive current draw.
2.5.1.2 USB 2.0 Type-C Interface
The Seeed Studio BeagleBone® Green Eco uses a USB 2.0 Type-C connector for both data communication and primary power input. The USB Type-C port connects to the USBO interface of the AM335x SoC and functions as a USB device (peripheral) interface, allowing connection to a host computer for programming, debugging, and serial console access. This connection also provides 5V power to the board. USB 2.0 Data lines DP and DM from the Type-C connector are equipped with common mode chokes for EMI/EMC reduction and ESD protection. The USB_5V power is routed through the TPS2117DRL power multiplexer IC.
2.5.2 Ethernet Interface
The Seeed Studio BeagleBone® Green Eco provides a 10/100/1000 Mbps Ethernet interface with an RJ45 connector for network connectivity. This allows direct connection to local networks via standard Ethernet cables. The Ethernet port features integrated link and activity indicator LEDs (green for link status, yellow for network traffic). The interface supports standard network protocols like DHCP and static IP configuration and is compatible with common Linux networking tools. The processor's Common Platform Ethernet Switch (CPSW) subsystem ensures efficient packet processing. The Ethernet port supports Wake-on-LAN functionality for remote power management. Standard CAT5e or better Ethernet cables are recommended for optimal performance.
2.5.3 Power Supply Interface
The Seeed Studio BeagleBone® Green Eco features a flexible power management architecture centered on the TPS65214 PMIC. The board is powered by a standard 5V USB power adapter or host computer via the USB Type-C connector. The TPS65214 PMIC generates regulated voltage rails for the AM335x processor, including 1.1V for the processor core (VDD_MPU) and digital logic (VDD_CORE), and 1.5V for DDR memory (VDDS_DDR). Two integrated LDOs provide 1.8V for analog domains and power the VDDS pins. The power design includes protection features like overcurrent protection, thermal shutdown, and short-circuit protection.
2.5.4 DDR3L SDRAM Interface
The Seeed Studio BeagleBone® Green Eco incorporates 512MB of DDR3L SDRAM (Kingston D2516ECMDXGJDI-U) for system memory. It communicates with the AM335x processor via a 16-bit data bus operating at speeds up to 800 MT/s. DDR3L technology operates at 1.35V, offering improved energy efficiency. The memory interface includes data, address, bank, and control signals, as well as differential data strobe signals for accurate timing. Memory address and data lines are accessible via test points for development and debugging. The memory automatically enters self-refresh mode in low-power states.
2.5.5 eMMC Flash Interface
The Seeed Studio BeagleBone® Green Eco includes a 16GB Kingston EMMC16G-WW28 eMMC storage device for non-volatile memory. The eMMC connects to the AM335x processor via an 8-bit data bus, operating at speeds up to 52MHz. It serves as the primary boot device and storage medium for the operating system and user files. The interface uses a direct connection scheme with series resistors for signal integrity. The eMMC storage is powered by the 3.3V rail and includes a decoupling capacitor network for stable operation. It appears to the OS as a standard block storage device and offers advantages like wear leveling and error correction.
2.5.6 Micro SD Card Slot Interface
The Seeed Studio BeagleBone® Green Eco includes a standard micro SD card slot (P10) for expandable storage and an alternative boot source. The slot supports SD and SDHC cards up to 32GB, and SDXC cards when formatted. The micro SD interface connects to the AM335x processor via the MMCO controller, using a 4-bit data bus for transfer rates up to 24MB/s. A card detect switch enables hot-plug functionality. Key advantages for embedded applications include an alternative boot source, easy data exchange, storage expansion, and system recovery. Users can press the BOOT button while applying power to boot from the micro SD card.
2.5.7 Grove Connector Interfaces
The Seeed Studio BeagleBone® Green Eco features two Grove connectors (J4 and J5), integrated to leverage Seeed Studio's Grove ecosystem of sensors, actuators, and modules. These standardized 4-pin interfaces provide a plug-and-play solution for rapid prototyping.
Figure 2-16. Seeed Studio's extensive Grove ecosystem Description: A collage of various Grove modules and shields, showcasing the breadth of the Seeed Studio Grove ecosystem for prototyping.
2.5.7.1 Grove I2C Interface (J4)
The J4 connector provides a dedicated I2C interface operating at 3.3V logic levels. This Grove port connects directly to the AM335x processor's I2C2 bus, with unpopulated footprints for optional 4.7k pull-up resistors. This interface supports numerous Grove I2C modules, including environmental sensors, motion sensors, and display modules.
2.5.7.2 Grove UART Interface (J5)
The J5 connector provides a UART interface, connecting to the AM335x processor's UART2 port. This Grove port enables easy integration with serial communication modules operating at 3.3V logic levels, such as wireless communication modules (Bluetooth, WiFi, LoRa), GPS receivers, and RFID readers.
Supplementary Materials
Known Hardware or Software Issues
Information not available at time of release.
Brand Uses Approval
The Seeed Studio BeagleBone® Green Eco board is a compatible board of the BeagleBoard.org BeagleBone that is licensed by BeagleBoard.org®. See https://www.beagleboard.org/partner-program for more information.
Board photos
Board Photo Description: A detailed image of the Seeed Studio BeagleBone® Green Eco circuit board, highlighting its components, ports, and headers.
Kit List
- Seeed Studio BeagleBone® Green Eco x1
- USB Type-C Cable x1
- User Guide x1
Compliance
TBD for Compliance, REACH/ROHS, and EMC.
UL E-file number for this board: E469716
FCC Requirement
Any changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter.
Note: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference, in which case the user will be required to correct the interference at his own expense.