IRFZ44 N-Channel Power MOSFET

Product Summary

Features

• Dynamic dV/dt rating
• 175 °C operating temperature
• Fast switching
• Ease of paralleling
• Simple drive requirements
• Material categorization: for definitions of compliance please see www.vishay.com/doc?99912

Description

Third generation power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance, and cost-effectiveness. The TO-220AB package is universally preferred for commercial-industrial applications at power dissipation levels to approximately 50 W. The low thermal resistance and low package cost of the TO-220AB contribute to its wide acceptance throughout the industry.

Ordering Information

Absolute Maximum Ratings (Tc = 25 °C, unless otherwise noted)

Notes:

• ^a Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
• ^b VDD = 25 V, starting Tj = 25 °C, L = 44 µH, Rg = 25 Ω, IAS = 51 A (see fig. 12).
• ^c ISD ≤ 51 A, dI/dt ≤ 250 A/µs, VDD ≤ VDS, TJ ≤ 175 °C.
• ^d 1.6 mm from case.
• ^e Current limited by the package, (die current = 51 A).

Thermal Resistance Ratings

Specifications (TJ = 25 °C, unless otherwise noted)

Static

Dynamic

Drain-Source Body Diode Characteristics

Notes:

• ^a Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
• ^b Pulse width ≤ 300 µs; duty cycle ≤ 2%.

Typical Characteristics

• Fig. 1 - Typical Output Characteristics, Tc = 25 °C: Graph displaying Drain Current (ID) versus Drain-to-Source Voltage (VDS) for various Gate-Source Voltages (VGS). These curves show current saturation at higher VDS and increased current with higher VGS.
• Fig. 2 - Typical Output Characteristics, Tc = 175 °C: Similar to Fig. 1, but showing characteristics at a higher case temperature.
• Fig. 3 - Typical Transfer Characteristics: Graph of Drain Current (ID) versus Gate-Source Voltage (VGS) at a constant VDS. It illustrates the threshold voltage and the rapid increase in drain current as VGS rises.
• Fig. 4 - Normalized On-Resistance vs. Temperature: Graph showing the normalized drain-source on-resistance (RDS(on)) as a function of Junction Temperature (TJ). RDS(on) increases with temperature.
• Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage: Graphs of input capacitance (Ciss), output capacitance (Coss), and reverse transfer capacitance (Crss) versus Drain-to-Source Voltage (VDS). Capacitances generally decrease with increasing VDS.
• Fig. 6 - Typical Gate Charge vs. Gate-Source Voltage: Graph of Total Gate Charge (Qg) versus Gate-Source Voltage (VGS). It depicts the charge accumulation required for switching, including Qgs and Qgd components.
• Fig. 7 - Typical Source-Drain Diode Forward Voltage: Graph showing the Source-Drain Diode Forward Voltage (VSD) versus Reverse Drain Current (ISD), representing the forward voltage drop of the intrinsic body diode.
• Fig. 8 - Maximum Safe Operating Area: Logarithmic plot of Drain Current (ID) versus Drain-to-Source Voltage (VDS), defining safe operating limits based on continuous and pulsed current, and power dissipation at different temperatures and pulse durations.
• Fig. 9 - Maximum Drain Current vs. Case Temperature: Graph illustrating the derating of Maximum Drain Current (ID) as Case Temperature (TC) increases.
• Fig. 10a - Switching Time Test Circuit: Schematic of a switching time test circuit, featuring the Device Under Test (D.U.T.), power supply (VDD), gate resistance (RG), and a VGS pulse source.
• Fig. 10b - Switching Time Waveforms: Waveforms showing VGS, VDS, and ID during switching, indicating turn-on delay (td(on)), rise time (tr), turn-off delay (td(off)), and fall time (tf).
• Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case: Graph of Maximum Effective Transient Thermal Impedance (Zthjc) versus Rectangular Pulse Duration, used for junction temperature calculations.
• Fig. 12a - Unclamped Inductive Test Circuit: Schematic of an unclamped inductive load test circuit for avalanche energy measurement, including the D.U.T., inductor (L), RG, VDD, and switch.
• Fig. 12b - Unclamped Inductive Waveforms: Waveforms for unclamped inductive testing, showing VDS, IAS (avalanche current), and pulse width (tp) during the avalanche event.
• Fig. 12c - Maximum Avalanche Energy vs. Drain Current: Graph showing Maximum Avalanche Energy (EAS) versus Starting Junction Temperature (TJ) for different drain current levels.
• Fig. 13a - Basic Gate Charge Waveform: Diagram illustrating the basic gate charge waveform, showing the accumulation of gate charge (Qgs, Qgd) as VGS changes.
• Fig. 13b - Gate Charge Test: Schematic of a gate charge test circuit, employing a current regulator, VGS source, and the D.U.T. with current sampling resistors.
• Fig. 14 - Peak Diode Recovery dV/dt Test Circuit and Waveforms: Schematic of a peak diode recovery dV/dt test circuit, detailing layout considerations, dV/dt control via Rg, and ISD control via duty factor. Waveforms depict reverse recovery current, body diode forward current, VDS, and re-applied voltage.

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