AN5673 Application note

1.2.1 Power-on reset (POR) / power-down reset (PDR) / brown-out reset (BOR)

The devices feature an integrated power-on reset (POR) / power-down reset (PDR), coupled with a brown-out reset (BOR) circuitry. The POR/PDR is active in all power modes. The BOR can be enabled or disabled only through option bytes. It is not available in Shutdown mode.

When the BOR is enabled, four BOR levels can be selected through option bytes, with independent configuration for rising and falling thresholds. During power-on, the BOR keeps the device under reset until the VDD supply voltage reaches the specified BOR rising threshold (VBORRx). At this point, the device reset is released and the system can start.

During power-down, when VDD drops below the selected BOR falling threshold (VBORFx), the device is put under reset again.

It is not allowed to configure BOR falling threshold (VBORFx) to a value higher than BOR rising threshold (VBORRx).

Figure 2. POR, PDR, and BOR thresholds
This graph illustrates the voltage thresholds for Power-On Reset (POR), Power-Down Reset (PDR), and Brown-Out Reset (BOR) over time. It shows different BOR rising (VBORR1-4) and falling (VBORF1-4) thresholds, the POR threshold (VPOR), and the PDR threshold (VPDR). The reset temporization (tRSTTEMPO) starts when VDD crosses the VPOR threshold.

Note: The reset temporization tRSTTEMPO starts when VDD crosses VPOR threshold, indifferently from the configuration of the BOR option bits.

Note: For more details on the brown-out reset thresholds, refer to the electrical characteristics section in the corresponding datasheet.

1.3.1 Power reset

A power reset is generated when one of the following events occurs:

• power-on reset (POR) or brown-out reset (BOR)
• exit from Standby mode
• exit from Shutdown mode

Power and brown-out reset set all registers to their reset values.

When exiting Standby mode, all registers in the VCORE domain are set to their reset value. Registers outside the VCORE domain (back up register, WKUP, IWDG, and Standby/Shutdown mode control) are not impacted.

When exiting Shutdown mode, the brown-out reset is generated, resetting all registers.

1.3.2 System reset

System reset sets all registers to their reset values, except for the reset flags in the RCC control/status register 2 (RCC_CSR2) and the registers in the RTC domain.

System reset is generated when one of the following events occurs:

• low level on the NRST pin (external reset)
• window watchdog event (WWDG reset)
• independent watchdog event (IWDG reset)
• software reset (SW reset)
• low-power mode security reset
• option byte loader reset
• power-on reset

The reset source can be identified by checking the reset flags in the RCC_CSR2 register.

Figure 3. Simplified diagram of the reset circuit
This diagram shows a simplified model of the reset circuit. It includes an external reset input, an NRST pin, a reset holder, a filter, a pulse generator (minimum 20 µs duration), and logic to combine internal reset sources to generate system reset or bidirectional reset outputs.

Note: Upon power reset or wake up from shutdown mode, the NRST pin is configured as Reset input/output and driven low by the system until it is reconfigured to the expected mode when the option bytes are loaded, in the fourth clock cycle after the end of trstempo.

Software reset
The SYSRESETREQ bit in the Cortex®-M0+ application interrupt and the reset control register must be set to force a software reset on the device (refer to the programming manual PM0223).

Low-power mode security reset
To prevent critical applications from mistakenly enter a low-power mode, three low-power mode security resets are available. If enabled in option bytes, the resets are generated in the following conditions:

• Entering Standby mode
  This type of reset is enabled by resetting nRST_STDBY bit in user option bytes. In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering Standby mode.
• Entering Stop mode
  This type of reset is enabled by resetting nRST_STOP bit in user option bytes. In this case, whenever a Stop mode entry sequence is successfully executed, the device is reset instead of entering Stop mode.
• Entering Shutdown mode
  This type of reset is enabled by resetting nRST_SHDW bit in user option bytes. In this case, whenever a Shutdown mode entry sequence is successfully executed, the device is reset instead of entering Shutdown mode.

Option byte loader reset
The option byte loader reset is generated when the OBL_LAUNCH bit (bit 27) is set in the FLASH_CR register. This bit is used to launch the option byte loading by software.

1.3.3 RTC domain reset

The RTC domain has two specific resets. An RTC domain reset is generated when one of the following events occurs:

• software reset, triggered by setting the RTCRST bit in the register RCC_CSR1
• VDD power on

An RTC domain reset only affects the LSE oscillator, the RTC, and the register RCC_CSR1.

2.1 HSE clock

The high speed external clock signal (HSE) can be generated from two possible clock sources:

• HSE external crystal/ceramic resonator
• HSE user external clock

The resonator and the load capacitors must be placed as close as possible to the oscillator pins to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.

Figure 5. HSE / LSE clock sources
These diagrams show the hardware configurations for HSE and LSE clock sources. For HSE, it illustrates connections for an external clock source and for a crystal/ceramic resonator with load capacitors. For LSE, it shows similar configurations.

External crystal/ceramic resonator (HSE crystal)
The 4 to 48 MHz external oscillator has the advantage of producing a very accurate rate on the main clock. The associated hardware configuration is shown in Figure 5. Refer to the electrical characteristics section of the datasheet for more details. The HSERDY flag in the clock control register (RCC_CR) indicates if the HSE oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the clock interrupt enable register (RCC_CIER). The HSE crystal can be switched on and off using the HSEON bit in the clock control register (RCC_CR).

External source (HSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to 48 MHz. This mode is selected by setting the HSEBYP and HSEON bits in the clock control register (RCC_CR). The external clock signal (square, sinus, or triangle) with around 40 to 60% duty cycle depending on the frequency (refer to the datasheet) must drive the OSC_IN pin, on devices where OSC_IN and OSC_OUT pins are available (see Figure 5). The OSC_OUT pin can be used as a GPIO or it can be configured as OSC_EN alternate function, to provide an enable signal to the external clock synthesizer. It makes possible to stop the external clock source when the device enters low power modes.

Note: For details on pin availability, refer to the pinout section in the corresponding device datasheet. To minimize the consumption, it is recommended to use the square signal.

2.2 HSI48 clock

The HSI48 clock signal is generated from an internal 48 MHz RC oscillator. The HSI48 RC oscillator has the advantage of providing a clock source at low cost (no external components). It also has a startup time faster than the HSE crystal oscillator. However, even after calibration, it is less accurate than an oscillator using a frequency reference such as quartz crystal or ceramic resonator.

The HSISYS clock derived from HSI48 can be selected as system clock after wake up from Stop mode. It can also be used as a backup clock source (auxiliary clock) if the HSE crystal oscillator fails.

Calibration
RC oscillator frequencies can vary from one chip to another due to manufacturing process variations. To compensate for this variation, each device is factory calibrated at TA = 25°C. After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the Internal clock source calibration register (RCC_ICSCR). Voltage or temperature variations in the application may affect the HSI48 frequency of the RC oscillator. It can be trimmed using the HSITRIM[6:0] bits in the Internal clock source calibration register (RCC_ICSCR). The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI48 RC is stable or not. At startup, the HSI48 RC output clock is not released until this bit is set by hardware. The HSI48 RC can be switched on and off using the HSION bit in the Clock control register (RCC_CR). The HSI48 signal can also be used as a backup source (auxiliary clock) if the HSE crystal oscillator fails.

2.3 LSE clock

The LSE crystal is a 32.768 kHz crystal or ceramic resonator. It has the advantage of providing a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions.

The LSE crystal is switched on and off using the LSEON bit in the Control register 1 (RCC_CSR1). The crystal oscillator driving strength can be changed. It can be changed at runtime using the LSEDRV bit in the Control register 1 (RCC_CSR1) to obtain the best compromise between low-power-consumption on one side, and robustness and short startup time on the other side. The LSE drive can be decreased to its lower capability (LSEDRV cleared) when the LSE is ON. However, once LSEDRV is selected, the drive capability cannot be increased if LSEON = 1.

The LSERDY flag in the Control register 1 (RCC_CSR1) indicates whether the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware. An interrupt can be generated if enabled in the clock interrupt enable register (RCC_CIER).

External source (LSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to 1 MHz. This mode is selected by setting the LSEBYP and LSEON bits in the AHB peripheral clock enable in the Sleep/Stop mode register (RCC_AHBSMENR). The external clock signal (square, sinus, or triangle) with around 50% duty cycle has to drive the OSCX_IN pin while the OSCX_OUT pin can be used as GPIO. See Figure 5.

2.4 LSI clock

The LSI RC acts as a low-power clock source that can be kept running in Stop and Standby mode for the independent watchdog (IWDG) and RTC. The clock frequency is 32 kHz. For more details, refer to the electrical characteristics section of the datasheets.

The LSI RC can be switched on and off using the LSION bit in the Control/status register 2 (RCC_CSR2). The LSIRDY flag in the Control/status register 2 (RCC_CSR2) indicates if the LSI oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the clock interrupt enable register (RCC_CIER).

2.5 System clock (SYSCLK) selection

One of the following clocks can be selected as system clock (SYSCLK):

• LSI
• LSE
• HSISYS
• HSE

The maximum frequency of the system clock is 48 MHz. Upon system reset, the HSISYS clock derived from the HSI48 oscillator is selected as system clock. When a clock source is used as a system clock, it is not possible to stop it.

A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay). If a clock source that is not yet ready is selected, the switch occurs when the clock source becomes ready. Status bits in the internal clock sources calibration register (RCC_ICSCR) indicate which clock(s) is (are) ready and which clock is currently used as a system clock.

2.6 Clock security system (CSS)

Software can activate the clock security system. In this case, the clock detector is enabled after the HSE oscillator startup delay. It is disabled when this oscillator is stopped.

If a failure is detected on the HSE clock:

• the HSE oscillator is automatically disabled
• a clock failure event is sent to the break input of TIM1, TIM16, and TIM17 timers
• CSSI (clock security system interrupt) is generated

The CSSI is linked to the Cortex®-M0+ NMI (nonmaskable interrupt) exception vector. It makes the software aware of an HSE clock failure to allow it to perform rescue operations.

If the CSS is enabled and the HSE clock fails, the CSSI occurs and an NMI is automatically generated. The NMI is executed infinitely unless the CSS interrupt pending bit is cleared. It is therefore necessary that the NMI ISR clears the CSSI by setting the CSSC bit in the clock interrupt clear register (RCC_CICR).

If HSE is selected directly or indirectly as system clock, and a failure of the HSE clock is detected, the system clock switches automatically to HSISYS and the HSE oscillator is disabled.

2.7 Clock security system for LSE clock (LSECSS)

A clock security system on LSE can be activated by setting the LSECSSON bit in Control register 1 (RCC_CSR1). This bit can be cleared only by a hardware reset or RTC software reset, or after LSE clock failure detection. LSECSSON must be written after LSE and LSI are enabled (LSEON and LSION enabled) and ready (LSERDY and LSIRDY flags set by hardware), and after selecting the RTC clock by RTCSEL.

The LSECSS works in all modes except Standby and Shutdown. It keeps working also under system reset (excluding power-on reset). If a failure is detected on the LSE oscillator, the LSE clock is no longer supplied to the RTC, but its registers are not impacted.

If the LSECSS is enabled and the LSE clock fails, the LSECSSI occurs and an NMI is automatically generated. The NMI is executed infinitely unless the LSECSS interrupt pending bit is cleared. It is therefore necessary that the NMI ISR clears the LSECSSI by setting the LSECSSC bit in the clock interrupt clear register (RCC_CICR).

If LSE is used as system clock, and a failure of LSE clock is detected, the system clock switches automatically to LSI. In low-power modes, an LSE clock failure generates a wake-up. The interrupt flag must then be cleared within the RCC registers.

The software must then disable the LSECSSON bit, stop the defective 32 kHz oscillator (by clearing LSEON), and change the RTC clock source (no clock, LSI or HSE, with RTCSEL), or take any appropriate action to secure the application.

The frequency of the LSE oscillator must exceed 30 kHz to avoid false positive detections.

2.8 ADC clock

The ADC clock (refer to the device datasheet for maximum frequency) is derived from the system clock or from the kernel clock output. It can be prescaled by 1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128 or 256, by configuring the ADC1_CCR register. This clock is asynchronous to the AHB clock. Alternatively, the ADC clock can be derived from the AHB clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4). This programmable factor is configured using the CKMODE bitfields in the ADC1_CCR. If the programmed factor is 1, the AHB prescaler must be set to 1.

2.9 RTC clock

The RTCCLK clock source can be either the HSE/32, LSE or LSI clock. It is selected by programming the RTCSEL[1:0] bits in the Control register 1 (RCC_CSR1). This selection cannot be modified without resetting the RTC domain. The system must always be configured so as to get a PCLK frequency greater than or equal to the RTCCLK frequency for proper RTC operation.

RTC does not operate if the VDD supply is powered off or if the internal voltage regulator is powered off (removing power from the VCORE domain). When the RTC clock is LSE or LSI, the RTC remains clocked and functional under system reset.

When the RTC clock is LSE or LSI, the RTC remains clocked and functional under system reset.

2.10 Timer clock

The timer clock TIMPCLK is derived from PCLK (used for APB). If the APB prescaler is set to 1, the TIMPCLK frequency is equal to the PCLK frequency. Otherwise, the TIMPCLK frequency is set to twice the PCLK frequency.

2.11 Watchdog clock

If a hardware option or software access starts the independent watchdog (IWDG), the LSI oscillator is forced ON, and cannot be disabled. After the LSI oscillator temporization, the clock is provided to the IWDG.

2.12 Clock-out capability

MCO and MCO2
These pins output, independently of each other, the clock selected from:

• LSI
• LSE
• SYSCLK
• HSI48
• HSE

The multiplexers for MCO and MCO2 are controlled, respectively, by the MCOSEL[2:0] and MCO2SEL[2:0] bitfields of the Clock configuration register (RCC_CFGR). Their outputs are further divided by a factor set through the MCOPRE[2:0] and MCO2PRE[2:0] bitfields of the Clock configuration register (RCC_CFGR).

LCO
The LSCO pin allows outputting of low-speed clocks:

• LSI
• LSE

The selection is controlled by the LSCOSEL bit, and enabled with the LSCOEN bit of the Control register 1 (RCC_CSR1). The configuration registers of the corresponding GPIO port must be programmed in alternate function mode. This function remains available in Stop mode.

2.13 Internal / external clock measurement with TIM14 / TIM16 / TIM17

It is possible to indirectly measure the frequency of all on-board clock sources with the TIM14, TIM16, and TIM17 channel 1 input capture, as shown in the figures in each of the corresponding subsections.

Calibration of the HSI48 oscillator
For TIM14, TIM16 and TIM17, the primary purpose of connecting the LSE to the channel 1 input capture is to be able to precisely measure the HSISYS clock (derived from HSI48) selected as system clock. Counting HSISYS clock pulses between consecutive edges of the LSE clock (the time reference) allows measuring the HSISYS (and HSI48) clock period. Such measurement can determine the HSI48 oscillator frequency with nearly the same accuracy as the accuracy of the 32.768 kHz quartz crystal used with the LSE oscillator (typically a few tens of ppm). The HSI48 oscillator can then be trimmed to compensate for deviations from target frequency, due to manufacturing, process, temperature and/or voltage variation.

The HSI48 oscillator has dedicated user-accessible calibration bits for this purpose.

The basic concept consists in providing a relative measurement (for example, the HSISYS/LSE ratio): the measurement accuracy is therefore closely related to the ratio between the two clock sources. Increasing the ratio improves the measurement accuracy.

Generated by the HSE oscillator, the HSE clock (divided by 32) used as time reference is the second best method for reaching a good HSI48 frequency measurement accuracy. It is recommended in the absence of the LSE clock.

To further improve the precision of the HSI48 oscillator calibration, it is advised to employ one, or a combination of the following measures, to increase the frequency measurement accuracy:

• set the HSISYS divider to 1 for HSISYS frequency to be equal to HSI48 frequency,
• average the results of multiple consecutive measurements,
• use the input capture prescaler of the timer (1 capture every up to eight periods).

Calibration of the LSI oscillator
The calibration of the LSI oscillator uses the same principle as that for calibrating the HSI48 oscillator. TIM16 channel1 input capture must be used for LSI clock, and HSE selected as the system clock source. The number of HSE clock pulses between consecutive edges of the LSI signal, counted by TIM16, is then representative of the LSI clock period.

2.14 Peripheral clock enable registers

Each peripheral clock can be enabled by the corresponding enable bit of the RCC_AHBENR or RCC_APBENRx registers.

Note: When the peripheral clock is not active, the peripheral registers read or write accesses are not supported. The enable bit has a synchronization mechanism to create a glitch-free clock for the peripheral. After the enable bit is set, there is a 2-clock-cycle delay for the clock to be active. The software must take into account this delay.

4.1 Introduction

The host/target interface is the hardware equipment that connects the host to the application board. This interface is made of three components: a hardware debug tool, an SWD connector and a cable connecting the host to the debug tool.

Figure 9 shows the connection of the host to the discovery board (STM32C0316-DK), which embeds the debug tools (ST-LINK). Consequently, it can be directly connected to the PC through a USB cable.

Figure 9. Host-to-board connection
This diagram illustrates the typical setup for debugging a microcontroller board. It shows a Host PC connected via a USB cable to a Debug tool (e.g., ST-LINK), which in turn connects to a Discovery board via an SWD connector.

4.2 SWD (serial wire debug) port

The STM32C0 series core integrates the serial wire debug port (SW-DP), an Arm®standard CoreSight™ debug port with a 2-pin (clock + data) interface to the debug access port.

4.3 Pinout and debug port pins

5.1 Printed circuit board

For technical reasons, it is best to use a multilayer printed circuit board (PCB) with a separate layer dedicated to ground (VSS) and another dedicated to the VDD supply. This provides good decoupling and a good shielding effect. For many applications, economical reasons prohibit the use of this type of board. In this case, the major requirement is to ensure a good structure for ground and for the power supply.

5.2 Component position

A preliminary layout of the PCB must make separate circuits:

• High-current circuits
• Low-voltage circuits
• Digital component circuits
• Circuits separated according to their EMI contribution. This reduces cross-coupling on the PCB that introduces noise.

5.3 Ground and power supply (VDD)

Every block (noisy, low-level sensitive or digital) must be grounded individually and all ground returns must be to a single point. Loops must be avoided or their area has to be minimized. To improve analog performance, the decoupling capacitors must be placed as close as possible to the device.

The power supply must be implemented close to the ground line to minimize the area of supply loops. This is because the supply loop acts as an antenna, and is therefore the main transmitter and receiver of EMI. All component-free PCB areas must be filled with additional grounding to create a shield (especially when using single-layer PCBs).

5.4 Decoupling

All power supply and ground pins must be properly connected to the power supplies. These connections, including pads, tracks, and vias must have the lowest possible impedance. This is typically achieved with thick track widths and, preferably, with the use of dedicated power supply planes in multilayer PCBs.

In addition, each power supply pair must be decoupled with 100 nF filtering ceramic capacitor and a chemical capacitor of about 4.7 µF connected between the supply pins of the device. These capacitors need to be placed as close as possible to or below the appropriate pins on the underside of the PCB. Typical values are 10 nF to 100 nF, but exact values depend on the application needs.

Figure 12. Typical layout for VDD / VSS pair
This diagram shows a recommended layout for VDD and VSS power supply pins on a PCB. It illustrates the placement of decoupling capacitors (Cap.) close to the pins, connected via vias to the respective VDD and VSS layers.

5.5 Other signals

When designing an application, the EMC performance can be improved by closely studying:

• Signals for which a temporary disturbance affects the running process permanently. Such as interrupts and handshaking strobe signals, but not LED commands. For these signals, a surrounding ground trace, shorter lengths, and the absence of noisy and sensitive traces nearby (crosstalk effect) improve the EMC performance.
• Digital signals: the best possible electrical margin must be reached for the two logical states and slow Schmitt triggers are recommended to eliminate parasitic states.
• Noisy signals (such as clock)
• Sensitive signals (such as high-Z)

5.6 Unused I/O and features

All microcontrollers are designed for a variety of applications and often a particular application does not use 100% of the MCU resources.

To increase EMC performance and avoid extra power consumption, unused clocks, counters, or I/Os, should not be left free. I/Os should be connected to a fixed logic level of 0 or 1 by an external or internal pull-up or pull-down on the unused I/O pin. The other option is to configure GPIO as output mode using software. Unused features should be frozen or disabled, which is their default value.

6.1 Description of reference design

The reference design shown in the figure below is based on STM32C031, a highly integrated microcontroller running at 48 MHz, combining the Cortex®-M0+ 32-bit RISC CPU core with 32 Kbytes of embedded flash memory and 12 Kbytes of SRAM.

Figure 13. STM32C0 series reference schematic
This is a schematic diagram of a typical reference design for the STM32C0 series microcontroller. It shows the MCU package with pin assignments, SWD connector (CN1), external clock sources (LSE crystal X2, HSE crystal X1), a reset button (B1), and various passive components like capacitors (C1, C4, C5, C6, C7, C8, C9, C10) and a resistor (R1) for power supply, clock generation, and reset functions.