DA1469x PRO Development Kit

User Manual UM-B-093

Abstract

The DA1469x Development Kit Pro hardware provides a tested reference platform, access to all signals for connecting peripherals, and advanced debugging features.

1 Terms and Definitions

BLE: Bluetooth Low Energy
CIB: Communication Interface Board
DB: Daughterboard
LRA: Linear Resonant Actuator
ERM: Eccentric Rotating Mass
GPIO: General Purpose Input Output
HDK: HW Development Kit
I2C: Inter-Integrated Circuit
JTAG: Join Test Action Group
LDO: Low Dropout
LRA: Linear Resonant Actuator
MB: Motherboard
MISO: Master In Slave Out
MOSI: Master Out Slave In
NTC: Negative temperature coefficient (resistor)
OVP: Over Voltage Protection
PCB: Printed Circuit Board
PRS: Product Requirement Specification
QSPI: Quad Serial Peripheral Interface
RF: Radio Frequency
RFIO: Radio Frequency Input Output
SDK: SW Development Kit
SIMO: Single-Inductor Multiple-Output
SOC: System on Chip
SPI: Serial Peripheral Interface
SW: Software
SWD: Serial Wire Debug
UART: Universal Asynchronous Receiver-Transmitter
USB: Universal Serial Bus

2 References

DA1469x, Datasheet, Dialog Semiconductor.
AN-B-052, DA1458x/68x Development Kit J-Link Interface, Application Note, Dialog Semiconductor.
AN-B-037, DA1468x Power Measurements, Application Note, Dialog Semiconductor.
DA1469x Pro Development Kit Mainboard Schematics, Reference Design, Dialog Semiconductor.
DA1469x Pro Development Kit VFBGA-100 Schematics, Reference Design, Dialog Semiconductor.
DA1469x Pro Development Kit VFBGA-86 Daughterboard Schematics, Reference Design, Dialog Semiconductor.

3 DA1469x DK PRO Hardware Architecture and Implementation

3.1 Introduction

The DA1469x development kit PRO is available as a mainboard providing a socket for one of two variants of daughterboard (VFBGA-100/LFBGA-86). Our engineers have paid special attention in designing this DK to provide trouble-free user experiences and to keep compatibility with existing tools from DA1458x/DA1468x/ product lines. When combined with the DA1469x SDK and SmartSnippets tools, the DA1469x DK PRO provides an easy-to-use and complete platform for software/hardware development.

3.2 Features

Flexible battery options
QSPI-Flash memory for booting
Headers for I/O monitoring and expandability
Option to support Arduino shields
Option to support MikroBUS click boards
Provisions for automated test
On-board basic peripherals for demo and development
JTAG debugger and connectivity to PC
Look and feel similar to DA14680 PRO DK
DA1469x silicon easily replaceable on a daughterboard core module

3.3 DA1469x PRO DK Hardware Block Diagram

Figure 1: System Block Diagram. This diagram illustrates the main components of the DA1469x PRO Development Kit, including the DA1469x core daughterboard, mainboard, USB hub, J-Link debugger, FTDI interface, power switch, current measurement circuit, and breakout headers.

3.4 Main Features of Mainboard in DA1469x PRO DK

Main USB connector

NOTE: USB host must support USB 2.0 high-speed for reliable power measurements.

USB hub with two downstream ports:

Port1: SEGGER JLink-OB SWD-JTAG debugger for ARM Cortex M33
Port2: FT2232H multiprotocol serial interface providing a booting/debugging/HCI UART (2-pin or 4-pin) and SPI connected to the current measurement circuit Analog/Digital converter

Low profile Connectors mating to the 69x daughterboard

Breakout Headers (Figure 2, two pieces, 2 × 20 pins in each piece) for monitoring GPIO and power signals, with markings of signal names on the PCB top silkscreen

Figure 2: DA1469x DK PRO Mainboard Breakout Headers. This figure shows the J3 and J4 breakout headers, detailing the pin assignments for GPIO and power signals on the mainboard.

Headers for the dedicated LRA/ERM haptic motor driver pins

One user button K1, connected to a GPIO through a jumper

LDO adjustable from 1.8 V up to 4.2 V to supply the VBAT pin (default 3.0 V)

Figure 3: VBAT Adjustable LDO. This schematic shows the adjustable Low Dropout Regulator (LDO) circuit that can supply the VBAT pin, adjustable from 1.8 V to 4.2 V, with a default of 3.0 V.

Circuit to measure/monitor the current from LDO to VBAT

Software trigger support for SmartSnippets Toolbox (driven from a DA1469x GPIO, P0_16, through a jumper)

DIP switch to isolate UART and JTAG signals (in case we need to secure the most accurate sleep current measurements, Figure 4)

The board is shipped with all switches at the “ON” position (all signals connected to the related DA1469x pins)

Signal names are marked on PCB top silkscreen

Figure 4: DIP Switch. This diagram illustrates the DIP switch (S1) used to isolate UART and JTAG signals for accurate sleep current measurements.

Test points (TP) for automated production test (placed on the bottom of the board)

Ground points (TP28 and TP29) for connecting crocodile clips

QSPI-RAM option (not populated)

Optional Arduino sockets (supporting 3.3 V compatible Arduino shields)

Figure 5: Arduino Sockets. These sockets on the mainboard support 3.3 V compatible Arduino shields.

Optional 2× MikroBUS sockets (supporting 3.3 V compatible click boards from MikroElektronika or other sources)

Figure 6: MikroBUS sockets. These sockets on the mainboard support 3.3 V compatible click boards from MikroElektronika.

3.5 User Accessible Elements in DA1469x PRO DK

Figure 7: Main Accessible Features in Main Board/Daughter Board in DA1469x PRO DK. This image highlights key components on the development kit, including USB connectors, CIB connector, reset button, power selector, various headers (current measurement, software trigger, LDO selection, RF coaxial, LRA/ERM), DIP switch, and breakout headers.

3.6 DA1469x PRO DK Daughterboard (db-VFBGA-100 and db-LFBGA-86)

Figure 8: DA1469x PRO DK Daughterboard. This image shows the daughterboard, featuring the DA1469x chip (U1), QSPI Flash (U2), crystals (Y1, Y2), RF antenna (ANT1), coaxial switch (J7), reset button (K1), USB connector (J3), and OVP circuit.

Figure 9: USB Overvoltage Protection. This schematic illustrates the overvoltage protection circuit on the VBUS power input of the daughterboard.

Battery/Power connectors (Figure 10):

Figure 10: Power Options. This diagram shows the power connectors on the daughterboard, including a 2-pin connector for Li-Ion/LiPo batteries, an optional coin cell holder, and a power selector switch.

Figure 11: Connection to Mainboard. This figure displays the low-profile connectors (J1, J2) on the bottom of the daughterboard that mate with the mainboard, showing their pin assignments.

CIB debugging connector (Figure 12):

SWD pins connected to Cortex M33 core
Reset from JLink-OB or button on the CIB board
2-pin UART signals connected to bootable UART pins

Figure 12: CIB Debugging Header. This diagram shows the CIB debugging header, providing SWD pins for the Cortex M33 core and UART signals.

RGB LED, (D3)

NOTE: The RGB LED is only available on the DA14699 daughterboard.

Green and Blue segments connected to dedicated LED driver pins
Red segment connected to a MOSFET driven by a GPIO
Circuit for powering the LED from either VBUS or VBAT
Option to power the LEDs from the 6.0 V available on the mainboard. If this option is chosen, the SmartSnippets Toolbox measurement will exclude the LED current

Figure 13: LED Powering Circuit. This schematic details the RGB LED circuit on the daughterboard, including its power sources (VBUS or VBAT) and connections to LED driver pins and a MOSFET.

ESD protection diodes at the most susceptible points (USB connector J3, CIB interface J4, and power selector switch SW1)

Possibility to operate stand-alone (without the mainboard), powered from one of these options:

Li-Ion/LiPo/coin Battery
USB connector
CIB interface (providing also JTAG/UART debugging functions)

3.7 Current Measurement Section in DA1469x DK PRO

Following the DA1469x DK current measurement topology and circuitry

Full scale range 250 mA
Measurement accuracy down to 1 μA
Current sense resistors of 2.37 Ω in series to VBAT
FTDI chip for transferring data to the PC
Analog processing blocks
Software trigger circuit
Fast 24-bit ADC with SPI interface
Known limitation: measurement accuracy between 500 μA and 1 mA is worse than the typical 1% we have in all other cases (from 1 µA to 250 mA)

3.8 DA1469x PRO DK Power Block Diagram

Figure 14: DA1469x PRO DK Power Distribution Diagram. This block diagram outlines the power distribution within the DA1469x system, showing various power sources like USB, battery, and CIB port, and how they are regulated through LDOs and DCDC converters to supply different components.

DA1469x system consists of the SoC, QSPI, and the peripherals that are directly connected to the chip.

Four possible power sources can be used for DA1469x system:

USB on the daughterboard (feeding VBUS pin)
Li-ion/Li-Po/coin battery on the daughterboard (VBAT)
Debugging (CIB) port on the daughterboard (VBAT)
Adjustable LDO (default) supplied by the USB connector on the main board (VBAT). This is the only option where current can be measured by SmartSnippets Toolbox. By default, the LDO provides 3.0 V.

All DCDC outputs are supplemented by automatic bypass LDOs (default at startup) and retainer LDOs and/or voltage clamps (for lower consumption in sleep mode). For more details check the [1] DA1469x datasheet.

The debugging section consists of JTAG, UART, and current sense circuitry. This section is supplied from the mainboard USB connector.

The USB Hub has its own dedicated 3.3 V LDO (U13, always on, Figure 15).

Figure 15: 3.3V LDO for USB Hub. This schematic shows the 3.3V Low Dropout Regulator (LDO) circuit powering the USB hub.

The remaining support circuits on the mainboard are powered by a second 3.3 V supply (U14). This powers SEGGER (U4), FTDI (U12), and ADC (U8).

U14 is enabled by a signal coming from the USB hub. This signal (PWR_ENABLE) goes high after the hub has successfully enumerated with a USB host. If we need to operate the system without a host, for example, with an AC wall adapter, we need to solder a header on J6 and place a jumper.

Figure 16: 3.3 V LDO for Mainboard Peripherals. This schematic illustrates the 3.3V LDO circuit that powers mainboard support circuits like SEGGER, FTDI, and ADC.

The analog/digital converter and several op-amps on the current measurement section need a clean 5.0 V power supply (Figure 17). This is generated by a step-up regulator (U18) which generates 6.0 V, and U18 is followed by a 5 V LDO (U17). U18 is also controlled by PWR_ENABLED.

Figure 17: Op-Amps/ADC 5.0 V Power Supply. This schematic shows the step-up regulator and 5V LDO circuit that provides the 5.0 V power supply required by the analog/digital converter and op-amps.

The Op-Amps also require a small negative supply (-0.232 V) generated by U20 (Figure 18).

Figure 18: Negative Supply for Op-Amps. This schematic shows the circuit generating the negative supply voltage required by the op-amps.

3.9 Voltage Level Translation (Debugging) for Avoiding Leakage

Voltage translation is required because the DA1469x I/O voltage varies depending on the battery level and setting for the I/OLDO (V30).For example, if the other side (on board interfaces, JTAG/UART) is fixed at 3.3 V, there is a leakage through the pins if the DA1469x voltage I/Os are at 3.0 V or less.

Table 1: Signals with Level Translation
Pin Name	Signal Name
P0_10	SWDIO
P0_11	SWCLK
P0_9	UTX
P0_8	URX
P1_0	URTS
P0_7	UCTS

Figure 19: Voltage Level Translation Circuit. This diagram illustrates the voltage level translation circuitry used for debugging interfaces like JTAG/UART, ensuring proper signal levels between the DA1469x and the mainboard.

3.10 Mainboard/Daughterboard Mechanical Mating

The daughterboard can be placed on top of the mainboard via two low-profile SMD connectors, which are specified for a limited number of mating cycles (50).

Table 2: Mainboard/Daughterboard Mating Connectors
Main Board	Daughter Board
Amphenol FCI 10132797-055100LF	Amphenol FCI 10132798-052100LF

NOTE: The connectors have no polarity feature, so please be careful not to connect the daughterboard rotated by 180°. Small arrows on the top silk screens of both boards are added to indicate a properly aligned placement (Figure 20). The arrows on the mainboard must point to the arrows on the daughterboard.

Figure 20: Mainboard/Daughterboard Alignment. This image provides a visual guide for correctly aligning the daughterboard onto the mainboard, indicating the placement of alignment arrows.

3.11 GPIO Assignments

Table 3: Mainboard/Daughterboard Pin Assignment
Pin Name	DK Function	Comments
P0_0	QSPIR_D0	QSPI RAM for parallel LCD framebuffer. 1.8 V only.
P0_1	QSPIR_D1
P0_2	QSPIR_D2
P0_3	QSPIR_D3
P0_4	QSPIR_CSn
P0_5	QSPIR_CLK
P0_6	GP_BUTT
P0_7	UCTS
P0_8	URXD
P0_9	UTXD
P0_10	M33 SWDIO
P0_11	M33 SWCLK
P0_12
P0_13
P0_14	USB_DP	Daughterboard USB
P0_15	USB_DM
P0_16	C_TRIG	software trigger
P0_17
P0_18
P0_19
P0_20
P0_21
P0_22	XTAL32km	Daughterboard xtal 32.768kHz
P0_23	XTAL32kp
P0_24
P0_25
P0_26
P0_27
P0_28
P0_29
P0_30
P0_31
P1_0	URTS
P1_1	RGB LED (RED)	Daughterboard LED
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
P1_8
P1_9
P1_10
P1_11
P1_12
P1_13
P1_14
P1_15
P1_16
P1_17
P1_18
P1_19
P1_20
P1_21
P1_22
LED1	RGB LED (BLUE)	Daughterboard LED
LED2	RGB LED (GREEN)
HDRVP	J10 HEADER	LRA/ERM motor driving pins
HDRVM
RSTn	RESET (active low)	Daughterboard button

Note 1: USB and XTAL32k signals are typically not connected to the mainboard breakout headers. Series resistors must be placed on the daughterboard to connect these signals.

Note 2: LCD (various types), micro-motor drive, ADC inputs, NTC (charger), and sleep mode PWM outputs are available on specific pins only. Check the DA1469x datasheet [1] for more details.

3.12 Jumper/DIP Switch Settings

Table 4: Default Jumper Settings
Jumper Block	Default Position	Comment
J5	2-3	Selects 3.0 V as default VBAT
J6	not placed
J8	1-2 & 3-4	button (K1) and C_TRIG
J9	1-2 & 3-4	Current measurement input and output
J10	1-2 no jumpers	Haptic driver outputs
	3-4	Enable reset from SEGGER

The DIP switch (S1) has all individual segments set to the “ON” position by default.

3.13 QSPI-RAM Operation

QSPI-RAM may be used in applications where we need bulk data transfers with DMA. The most common case is as an LCD framebuffer. The selected QSPI-RAM chip (APS6404L-SQ-SN) is not populated on the PCBs and it has to be added by users.

Figure 21: QSPI-RAM. This schematic shows the connection of the QSPI-RAM chip to the DA1469x.

3.14 Test Section

Table 5: Mainboard Test Points (Placed on the Bottom Of DA1469x PRO DK)
TP Name on Reference Design	Signal Name	Comments
TP1	VDD_CR	3.3V (SEGGER)
TP2	T_RESET	JTAG Reset
TP3	sERASE	SEGGER chip programming
TP4	sVCC
TP5	sRST
TP6	sDIO
TP7	sCLK
TP8	sTDI
TP9	DBLED	SEGGER LED

Table 6: Daughterboard Test Points
TP Name on Reference Design	Signal Name	Comments	Position on Daughter Board
TP1	V18	1.8 V ± 5%	top
TP2	FCS	Flash chip select	top
TP3	VBUS	5.0 V ± 5% (output of OVP circuit)	top
TP4	V30	3.0 V ± 2%	top
TP5	V18	1.8 V ± 5%	bottom
TP6	V18P	1.8 V ± 5%	bottom
TP7	V14	1.4 V ± 5%	bottom
TP8	V12	1.2 V ± 5%	bottom
TP9	VBAT	Battery (default LDO 3.0 V ± 2%)	top
TP12	GND		bottom
TP13	GND		top
TP14	GND		bottom
TP15	VBUS_IN	5.0 V ± 5% (from USB, before OVP)	top
TP16	VBATn	VBAT pin (default LDO 3.0 V ±2%)	bottom
TP17	VBUSn	5.0 V ± 5% (to DA1469x pin)	bottom
TP18	VLED	LED power (VBUS or VBAT - 0.2 V)	bottom
TP20	GND		top
TP21	V18	VFLASH 1.8 V ± 5%	bottom

Revision History

Revision	Date	Description
1.1	19-Feb-2019	To be released with DA1469x Pro DKs.
		Change details: Update document title to "DA1469x PRO Development Kit" Removed reference to Basic Kit Minor text editing Improved template compliance
1.0	15-Feb-2018	Initial version (specification)

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