STM32G4 Totem Pole PFC: Digital Solution Design Considerations

Agenda

1. Totem Pole PFC and Design Challenges
2. 3kW Totem Pole PFC Digital Solution
3. STM32G4 Mainstream Series
4. Summary

1. Totem Pole PFC and Design Challenges

How to Improve Key Factors Affecting PFC Efficiency?

Traditional Boost PFC:

Diagram Description: A traditional boost PFC circuit featuring a bridge rectifier (Si diodes), an inductor, switches (SiC), and a 400V DC link capacitor. Key elements include conduction loss from rectifier bridge diodes (Vf) and three discrete components in series on the power path.

Comparison of PFC Topologies and Efficiency Improvement

The Totem Pole configuration is beneficial for achieving high efficiency and high power density in PFC topologies.

Active Bridge PFC

• Control: Simple
• Efficiency: Excellent (~98.5%)
• Components: Many
• Cost: High (low Rds(on) MOSFETx4)

Half-Bridge PFC

• Control: Simple
• Efficiency: Excellent (~98.0%)
• Components: Many
• Inductor Utilization: Low

Totem Pole PFC

• Control: Complex
• Efficiency: Excellent++ (98.5~99%)
• Components: Few
• Power Density: High

Totem Pole PFC Positive Half-Cycle Working Principle

Switches S1, S2: High-speed switches. Switches S3, S4: Low-speed switches.

Positive Half-Cycle (VAC > 0): Main switch: S2 controls input current charging the PFC inductor to produce a sinusoidal waveform. Synchronous switch: S1 is a complementary switch, providing a discharge path for inductor current. Normally closed switch: S4. Normally open switch: S3.

Diagram Description: Circuit diagrams showing current charging (S2 closed) and discharging (S2 open) paths for the positive half-cycle, with gate control signals (VGSI, VGS2, VGS3, VGS4) plotted against time.

Totem Pole PFC Negative Half-Cycle Working Principle

Switches S1, S2: High-speed switches. Switches S3, S4: Low-speed switches.

Negative Half-Cycle (VAC < 0): Main switch: S1 controls input current charging the PFC inductor to produce a sinusoidal waveform. Synchronous switch: S2 is a complementary switch, providing a discharge path for inductor current. Normally closed switch: S3. Normally open switch: S4.

Diagram Description: Circuit diagrams showing current charging (S1 closed) and discharging (S1 open) paths for the negative half-cycle, with gate control signals (VGSI, VGS2, VGS3, VGS4) plotted against time.

Advantages of SiC MOSFETs in Totem Pole PFC

• Low reverse recovery time of the body diode.
• Excellent figure of merit leads to low switching loss.
• Low power consumption at high temperatures due to small resistance variation with temperature.

Diagram Description: Comparison of SJ MOSFET and SiC MOSFET circuits in a Totem Pole PFC configuration, highlighting the improvement in reverse recovery.

Design Challenge: Peak Current at AC Zero Crossing

When AC input transitions from positive to negative.

• Before zero crossing: Vcoss_S3=400V, S2 duty cycle Dboost=0.99, S1 duty cycle (1-Dboost)=0.01.
• After zero crossing: Vcoss_S4=400V, S1 duty cycle Dboost=0.99, S2 duty cycle (1-Dboost)=0.01.
• If Dboost changes suddenly at zero crossing, Vcoss_S3 can cause peak current.

Design Challenge: Reliable AC Zero-Crossing Detection

Mis-triggering at AC zero crossing causes short-circuit breakdown.

• Normal positive half-cycle operation: Charging path: S2 + S4. Discharging path: S1 + S4.
• If mis-triggered to negative half-cycle operation, a short-circuit path occurs: D1 + S3.

Design Challenge: AC Frequency Jump Test

When AC frequency changes (e.g., 50Hz to 60Hz), the firmware continues to operate with negative half-cycle logic. S3 remains closed, causing a large current spike through D1 and S3.

Diagram Description: Oscilloscope traces showing the effect of an AC frequency jump, illustrating the current spike caused by incorrect logic during the transition.

2. 3kW TTP PFC Digital Solution

3kW CCM Totem Pole PFC Solution

Power density up to 82W/inch³.

Compliant with IEC61000-4-11 and IEC61000-3-2.

Key Features:

• Input AC voltage: 90VAC to 264VAC
• DC output voltage: 400VDC
• Switching frequency: 70kHz
• Operation mode: CCM
• Peak efficiency: 98.5% @ 230VAC
• Power factor: >0.98 @ 100% load
• iTHD: <5% @ 100% load
• Peak inrush current: <30A

Applications:

• Telecom and 5G PSU
• Data Center and Server PSU

Digital Platform - STM32G474

Ideal for applications requiring advanced and rich analog peripherals.

• Core: 32-bit Arm® Cortex®-M4, up to 170MHz
• Features: Floating Point Unit (FPU) - helpful for power loop calculations. 32 KB CCM-SRAM. CORDIC and FMAC (mathematical accelerators). High-resolution PWM timers (184ps) for precise power control. 5 ADCs (4Msps) with hardware oversampling. Faster response to emergency protection: Comparators, DACs, Op-amps. Reduced component count. UART, SPI, CAN, USB.
• USB Type-C Power Delivery (PD).
• +/- 1% internal clock.

Main Applications:

• Commercial, architectural and street lighting
• Server/Telecom
• Welding
• Charging station
• UPS & Data center Power supply
• Solar inverters

Functional Block Diagram

Key Digital Features:

• Solution for AC zero-crossing current spikes with blanking + soft-start.
• Hardware ZCD + software PLL for reliable AC phase detection.
• FMAC for current loop control to reduce CPU workload.

Diagram Description: A block diagram illustrating the PFC control system, including AC input, EMI filter, inrush current control, PFC choke, switches (S1-S4), bulk capacitor, and various control modules like ZCD, current sensing, OCP, PWM, OVP, fan control, temperature monitoring, PLL, reset, input metering, and UART communication.

Current Sampling Strategy in Totem Pole

Sampling Considerations and Configuration:

• Active switches are exchanged based on AC polarity.
• Inductor current is sampled at the midpoint of the active switch ON time.
• The interrupt setting is at the PWM counter period and reset points, effectively doubling the switching frequency for interrupts.

Positive Half-Cycle: Sample current at PWM count period, then PI calculation.

Negative Half-Cycle: Sample current at PWM count reset point, then PI calculation.

Diagram Description: Waveforms showing current sampling points for positive and negative half-cycles, along with corresponding gate control signals (VGSI, VGS2) and AC voltage (VAC).

FMAC (Mathematical Filter Accelerator)

FMAC frees up CPU/interrupt resources, allowing more software algorithms (non-linear control, feedforward, etc.). FMAC is built around 2x16-bit multipliers and 26-bit accumulators for FIR and IIR filters.

Diagram Description: Illustrates the IIR filter structure and shows how the FMAC unit replaces software-based PID/nPnZ calculations for the current loop ISR, optimizing performance.

AC Zero-Crossing Detection

HW ZCD circuit + HW/SW filters: Simple but sensitive to noise. HW ZCD signal updates only every half AC cycle, limiting response speed.

SW PLL (Frequency/Phase Tracking): Uses HW ZCD, MCU frequency detection, frequency/phase identification, sync error, LPF, VCO.

Diagram Description: Compares HW ZCD with HW/SW filters against a SW PLL approach for AC zero-crossing detection, showing signal processing blocks and waveforms.

PFC Control Algorithm

• Voltage outer loop with input voltage feedforward compensation.
• Current inner loop using built-in hardware digital filter (FMAC).
• PLL for synchronizing AC input, enabling blanking + soft-start.
• Km is a proportionality constant.

Diagram Description: Control loop block diagram showing VAC input processed through ADC, RMS, 1/Vrms², Gv, Km, and FMAC (Gi) to control MOSFETs. Vbulk and IL are also fed into ADCs. Voltage loop operates at 10kHz, current loop at 70kHz.

Peak Current Elimination Solution

During blanking, all MOSFETs are turned off to ensure safe power switch control and prevent short-circuiting the output DC capacitor.

Blanking + Soft-Starting Solution: Active switches S1 or S2 are controlled by soft duty cycle.

Diagram Description: Shows the Totem Pole PFC circuit during blanking and soft-starting phases, with waveforms illustrating VAC, IL, and gate signals (S1, S2, S3, S4) over time.

Peak Current Elimination Solution

Suspend control loop during blanking to avoid the current loop integrator generating large PWM pulses, causing current spikes.

Suspend current loop during blanking.

Diagram Description: Illustrates the control loop suspension during the blanking time, showing the current loop computation being halted and restarted, with a block diagram of the PI controller (Kp, Ki, Kd).

AC Frequency Jump Solution

Use high-speed comparators to handle reverse current. Dynamically set thresholds for positive/negative half-cycles. Turn off all PWM via comparators upon triggering the threshold. Once reverse current occurs, it will be clamped.

Diagram Description: Shows AC waveforms and oscilloscope traces demonstrating the solution for AC frequency jumps, highlighting how fast comparators and PWM control prevent current spikes.

3. STM32G4 Mainstream Series

STM32G474 MCU

Ideal for digital control with high-precision PWM and rich analog peripherals.

Connectivity:

• 4x SPI, 4x I2C, 6x UART
• 2x USB 2.0 FS, 1x USB-C PD3.0 (+PHY)
• 3x CAN-FD
• 2x I2S half duplex, SAI

External Interface:

• FSMC 8-/16-bit (TFT-LCD, SRAM, NOR, NAND)
• Quad SPI

Accelerators:

• ART Accelerator™
• 32-Kbyte CCM-SRAM

Math Accelerators:

• CORDIC (trigo...)
• FMAC

Timers:

• 5x 16-bit timers
• 2x 16-bit basic timers
• 3x 16-bit advanced motor control timers
• 2x 32-bit timers
• 1x 16-bit LP timer
• 1x HR timer (D-Power) 12-channel w/ 184ps (Δ delay line)

Analog:

• 5x 12-bit ADC w/ HW oversampling
• 7x Comparators
• 7x DAC (3x buff + 4x non-buff)
• 6x Op-Amp (PGA)
• 1x temperature sensor
• Internal voltage reference

Core:

• 32-bit Arm® Cortex®-M4, up to 170MHz
• CCM-SRAM program execution accelerator up to 32 KB
• Mathematical hardware accelerators (CORDIC / FMAC)
• High-resolution timers (184ps) for precise PWM control
• Rich, advanced analog features
• USB Type-C Power Delivery (PD)
• +/- 1% internal clock

Main Applications:

• Commercial, architectural and street lighting
• Server/Telecom
• Welding
• Charging station
• UPS & Data center Power supply
• Solar inverters

STM32G4 Product Matrix

Shows different STM32G4 series (G484, G474, G483, G473, G441, G431) with varying Flash/RAM sizes and pin counts. Legend: Crypto AES-256.

Diagram Description: A matrix displaying STM32G4 microcontroller variants based on Flash memory/RAM size and pin count, categorizing devices by series.

STM32G4 Hardware Solutions

Accelerate evaluation, prototyping, and design speed.

STM32 Nucleo:

• Flexible prototyping
• NUCLEO-G431RB
• NUCLEO-G474RE
• NUCLEO-G431KB

Evaluation Boards:

• Full-featured STM32G4 evaluation
• STM32G484E-EVAL
• STM32G474-EVAL

Motor Control Kits:

• Full-featured, for motor control and analog applications
• P-NUCLEO-IHM03

Discovery Kits:

• Key feature prototypes
• B-G474E-DPOW1
• B-G431B-ESC1

STM32G4 Software Tools

Full support for the Arm Cortex-M ecosystem.

STM32CubeMX:

• Configuration and code generation
• Conflict resolver

IDE Compilation and Debugging:

• Flexible solutions: partner IDEs like IAR and Keil.
• Free Eclipse-based IDE: STM32CubeIDE.

STM32 Programming Tools:

• STM32CubeProgrammer for flash programming via GUI or command line interface.

Digital Power Workshops developed with Biricha

Combines industry-leading ST MCUs with Biricha's tools and training.

Biricha digital power:

• World-leading digital power expertise and training.
• Workshop based on STM32F334 Nucleo and dedicated digital power expansion board.
• Learn how to implement digital power and power factor correction.

4. Summary

STM32G4 digital control solutions help achieve high performance and reliability for continuous mode Totem Pole PFC.

• Compared to traditional PFC, Totem Pole PFC offers advantages like high efficiency and fewer components.
• To address Totem Pole PFC design challenges, good peak current control strategies and reliable zero-crossing detection are needed.
• Based on the 3kW reference design, detailed design considerations and concepts for continuous mode Totem Pole PFC are proposed.
• The STM32G4 ecosystem provides a complete design environment and a satisfactory development experience.