The RL78/G23 manual is separated into two parts: this manual and the ... Refer to the separate document RL78 Family User's Manual: ... I18/E.
Renesas Electronics with respect to maximum ratings, operating power supply voltage ... The RL78/G23 manual is separated into two parts: this manual and the ...
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products.
Cover
User's Manual
RL78/G23
16
User's Manual: Hardware
16-Bit Single-Chip Microcontrollers
All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (http://www.renesas.com).
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Rev.1.00 Apr 2021
Notice
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General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products
The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
1. Precaution against Electrostatic Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices.
2. Processing at power-on The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the level at which resetting is specified.
3. Input of signal during power-off state Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during power-off state as described in your product documentation.
4. Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible.
5. Clock signals After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable.
6. Voltage application waveform at input pin Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.).
7. Prohibition of access to reserved addresses Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these addresses as the correct operation of the LSI is not guaranteed.
8. Differences between products Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a systemevaluation test for the given product.
How to Use This Manual
Readers
Purpose Organization
This manual is intended for user engineers who wish to understand the functions of the RL78/G23 and design and develop application systems and programs for these devices. The target products are as follows.
· 30-pin: R7F100GAx (x = F, G, H, J)
· 52-pin: R7F100GJx (x = F, G, H, J, K, L, N)
· 32-pin: R7F100GBx (x = F, G, H, J)
· 64-pin: R7F100GLx
· 36-pin: R7F100GCx (x = F, G, H, J)Note
(x = F, G, H, J, K, L, N)Note
· 40-pin: R7F100GEx (x = F, G, H, J)Note
· 80-pin: R7F100GMx (x = G, H, J, K, L, N)
· 44-pin: R7F100GFx (x = F, G, H, J, K, L, N) · 100-pin: R7F100GPx (x = G, H, J, K, L, N)
· 48-pin: R7F100GGx
· 128-pin: R7F100GSx (x = J, K, L, N)
(x = F, G, H, J, K, L, N)Note
Note The 36-pin plastic WFLGA, 40-pin plastic HWQFN, 48-pin plastic HWQFN, and 64-pin plastic WFLGA products are in planning. Contact a Renesas Electronics sales office for details.
This manual is intended to give users an understanding of the functions described in the Organization below.
The RL78/G23 manual is separated into two parts: this manual and the software edition (common to the RL78 family).
RL78/G23 User's Manual
Hardware (This Manual)
RL78 Family User's Manual
Software
· Pin functions · Internal block functions · Interrupts · Other on-chip peripheral functions · Electrical specifications
· CPU functions · Instruction set · Explanation of each instruction
How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. · To gain a general understanding of functions: Read this manual in the order of the CONTENTS. The mark "<R>" shows major revised points. The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field. · How to interpret the register format: For a bit number enclosed in angle brackets, the bit name is defined as a reserved word in the assembler, and is defined as an sfr variable using the #pragma sfr directive in the compiler. · To know details of the RL78/G23 Microcontroller instructions: Refer to the separate document RL78 Family User's Manual: Software (R01US0015E).
Conventions
Data significance: Active low representations: Note: Caution: Remark: Numerical representations:
Higher digits on the left and lower digits on the right (overscore over pin and signal name) Footnote for item marked with Note in the text Information requiring particular attention Supplementary information Binary.................. or B Decimal ............... Hexadecimal .......H
Related Documents
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.
Documents Related to Devices Document Name
RL78/G23 User's Manual Hardware RL78 Family User's Manual Software
Document No. This manual R01US0015E
Documents Related to Flash Memory Programming (User's Manual) Document Name
PG-FP6 Flash Memory Programmer User's Manual E2 Emulator User's Manual E2 Lite Emulator User's Manual Renesas Flash Programmer Flash Memory Programming Software User's Manual Renesas Flash Development Toolkit User's Manual
Document No. R20UT4025E R20UT3538E R20UT3240E
R20UT4066E
R20UT0508E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing.
Other Documents Document Name
Renesas Microcontrollers RL78 Family Semiconductor Package Mount Manual Semiconductor Reliability Handbook
Document No. R01CP0003E R50ZZ0003E R51ZZ0001E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing.
All trademarks and registered trademarks are the property of their respective owners. EEPROM is a trademark of Renesas Electronics Corporation. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan.
Caution: This product uses SuperFlash technology licensed from Silicon Storage Technology, Inc.
CONTENTS
1. OUTLINE ......................................................................................................................................... 1 1.1 Features .................................................................................................................................... 1 1.2 List of Part Numbers .................................................................................................................. 5 1.3 Pin Configuration (Top View) ..................................................................................................... 9 1.3.1 30-pin products ...................................................................................................................... 9 1.3.2 32-pin products .................................................................................................................... 10 1.3.3 36-pin products .....................................................................................................................11 1.3.4 40-pin products .................................................................................................................... 12 1.3.5 44-pin products .................................................................................................................... 13 1.3.6 48-pin products .................................................................................................................... 14 1.3.7 52-pin products .................................................................................................................... 15 1.3.8 64-pin products .................................................................................................................... 16 1.3.9 80-pin products .................................................................................................................... 19 1.3.10 100-pin products .................................................................................................................. 20 1.3.11 128-pin products .................................................................................................................. 22 1.4 Pin Identification ...................................................................................................................... 23 1.5 Block Diagram ......................................................................................................................... 24 1.6 Outline of Functions ................................................................................................................. 25
2. PIN FUNCTIONS ........................................................................................................................... 31 2.1 Functions of Port Pins ............................................................................................................. 31 2.1.1 30-pin products .................................................................................................................... 32 2.1.2 32-pin products .................................................................................................................... 34 2.1.3 36-pin products .................................................................................................................... 36 2.1.4 40-pin products .................................................................................................................... 38 2.1.5 44-pin products .................................................................................................................... 40 2.1.6 48-pin products .................................................................................................................... 42 2.1.7 52-pin products .................................................................................................................... 44 2.1.8 64-pin products .................................................................................................................... 47 2.1.9 80-pin products .................................................................................................................... 50 2.1.10 100-pin products .................................................................................................................. 53 2.1.11 128-pin products .................................................................................................................. 57 2.2 Pin Functions other than Port Pin Functions ........................................................................... 61 2.2.1 Functions for each product .................................................................................................. 61 2.2.2 Description of pin functions ................................................................................................. 68 2.3 Connection of Unused Pins ..................................................................................................... 70 2.4 Block Diagrams of Pins ........................................................................................................... 71
3. CPU ARCHITECTURE ................................................................................................................ 108 3.1 Memory Space ....................................................................................................................... 109 3.1.1 Internal program memory space .........................................................................................119 3.1.2 Mirror area ......................................................................................................................... 123 3.1.3 Internal data memory space .............................................................................................. 125 3.1.4 Special function register (SFR) area .................................................................................. 126 3.1.5 Extended special function register (2nd SFR: 2nd special function register) area ............ 126
Index - 1
3.1.6 Data memory addressing .................................................................................................. 127 3.2 Processor Registers .............................................................................................................. 128
3.2.1 Control registers ................................................................................................................ 128 3.2.2 General-purpose registers ................................................................................................. 130 3.2.3 ES and CS registers .......................................................................................................... 131 3.2.4 Special function registers (SFRs) ...................................................................................... 132 3.2.5 Extended special function registers (2nd SFRs) ............................................................... 137 3.3 Instruction Address Addressing ............................................................................................. 153 3.3.1 Relative addressing ........................................................................................................... 153 3.3.2 Immediate addressing ....................................................................................................... 153 3.3.3 Table indirect addressing ................................................................................................... 154 3.3.4 Register indirect addressing .............................................................................................. 155 3.4 Addressing for Processing Data Addresses .......................................................................... 156 3.4.1 Implied addressing ............................................................................................................ 156 3.4.2 Register addressing ........................................................................................................... 157 3.4.3 Direct addressing ............................................................................................................... 158 3.4.4 Short direct addressing ...................................................................................................... 159 3.4.5 SFR addressing ................................................................................................................. 160 3.4.6 Register indirect addressing .............................................................................................. 161 3.4.7 Based addressing .............................................................................................................. 162 3.4.8 Based indexed addressing ................................................................................................ 165 3.4.9 Stack addressing ............................................................................................................... 166
4. PORT FUNCTIONS ..................................................................................................................... 169
4.1 Port Functions ....................................................................................................................... 169 4.2 Port Configuration .................................................................................................................. 169
4.2.1 Port 0 ................................................................................................................................. 171 4.2.2 Port 1 ................................................................................................................................. 171 4.2.3 Port 2 ................................................................................................................................. 172
4.2.4 Port 3 ................................................................................................................................. 172
4.2.5 Port 4 ................................................................................................................................. 172
4.2.6 Port 5 ................................................................................................................................. 173
4.2.7 Port 6 ................................................................................................................................. 173
4.2.8 4.2.9 4.2.10 4.2.11
Port 7 ................................................................................................................................. 173 Port 8 ................................................................................................................................. 174 Port 9 ................................................................................................................................. 174 Port 10 ............................................................................................................................... 174
4.2.12 Port 11 ............................................................................................................................... 174
4.2.13 Port 12 ............................................................................................................................... 175
4.2.14 Port 13 ............................................................................................................................... 175
4.2.15 Port 14 ............................................................................................................................... 176
4.2.16 Port 15 ............................................................................................................................... 176 4.3 Registers to Control the Port Function .................................................................................. 177
4.3.1 Port mode registers (PMxx) ............................................................................................... 185 4.3.2 Port registers (Pxx) ............................................................................................................ 186 4.3.3 Pull-up resistor option registers (PUxx) ............................................................................. 187
4.3.4 Port input mode registers (PIMxx) ..................................................................................... 188
4.3.5 Port output mode registers (POMxx) ................................................................................. 189
4.3.6 Port digital input disable registers (PDIDISxx) ................................................................... 190
Index - 2
4.3.7 Port mode control A registers (PMCAxx) ........................................................................... 191 4.3.8 Port mode control T registers (PMCTxx) ........................................................................... 192 4.3.9 Port mode control E registers (PMCEx) ............................................................................ 193 4.3.10 Peripheral I/O redirection register (PIOR) ......................................................................... 194 4.3.11 Global digital input disable register (GDIDIS) .................................................................... 196 4.3.12 Output current control enable register (CCDE) ................................................................. 197 4.3.13 Output current select registers (CCSx) .............................................................................. 199 4.3.14 40-mA port output control register (PTDC) ........................................................................ 200 4.3.15 Port function output enable registers (PFOEx) .................................................................. 202 4.3.16 Port mode select register (PMS) ....................................................................................... 203 4.4 Port Function Operations ....................................................................................................... 204 4.4.1 Writing to I/O port .............................................................................................................. 204 4.4.2 Reading from I/O port ........................................................................................................ 204 4.4.3 Operations on I/O port ....................................................................................................... 204 4.4.4 Handling different potential (1.8 V, 2.5 V, or 3 V) by using EVDD VDD ............................ 204 4.4.5 Handling different potential (1.8 V, 2.5 V, or 3 V) by using I/O buffers ............................... 205 4.5 Register Settings When Using Alternate Function ................................................................. 208 4.5.1 Basic concept when using alternate function .................................................................... 208 4.5.2 Register settings for alternate function whose output function is not used ........................ 210 4.5.3 Register settings and port pin state ....................................................................................211 4.5.4 Examples of register settings for port and alternate functions ............................................211 4.6 Cautions When Using Port Function ..................................................................................... 248 4.6.1 Cautions on 1-bit manipulation instruction for port register n (Pn) .................................... 248 4.6.2 Notes on specifying the pin settings .................................................................................. 249
5. OPERATION STATE CONTROL ................................................................................................. 250
5.1 Configuration of Operation State Control ............................................................................... 250 5.2 Registers to Control the Operation State Control .................................................................. 252
5.2.1 Flash operating mode select register (FLMODE) .............................................................. 252
5.2.2 Flash operating mode protect register (FLMWRP) ............................................................ 254
5.3 Initial Setting of Flash Operation Modes ................................................................................ 255
5.4 Transitions between Flash Operation Modes ........................................................................ 256
5.5 Details of Flash Operation Modes ......................................................................................... 257
5.5.1 5.5.2 5.5.3 5.5.4
Details of HS (high-speed main) mode .............................................................................. 257 Details of LS (low-speed main) mode ................................................................................ 258 Details of LP (low-power main) mode ................................................................................ 259 Details on SUB mode ........................................................................................................ 260
6. CLOCK GENERATOR ................................................................................................................. 261
6.1 Functions of Clock Generator ................................................................................................ 261 6.2 Configuration of Clock Generator .......................................................................................... 263 6.3 Registers to Control the Clock Generator .............................................................................. 266
6.3.1 Clock operation mode control register (CMC) ................................................................... 267 6.3.2 System clock control register (CKC) .................................................................................. 270 6.3.3 Clock operation status control register (CSC) ................................................................... 272 6.3.4 Oscillation stabilization time counter status register (OSTC) ............................................. 273 6.3.5 Oscillation stabilization time select register (OSTS) .......................................................... 275 6.3.6 Peripheral enable registers 0, 1 (PER0, PER1) ................................................................ 277 6.3.7 Subsystem clock supply mode control register (OSMC) ................................................... 282
Index - 3
6.3.8 Subsystem clock select register (CKSEL) ......................................................................... 284 6.3.9 High-speed on-chip oscillator frequency select register (HOCODIV) ................................ 285 6.3.10 Middle-speed on-chip oscillator frequency select register (MOCODIV) ............................ 286 6.3.11 High-speed system clock division register (MOSCDIV) .................................................... 287 6.3.12 High-speed on-chip oscillator trimming register (HIOTRM) ............................................... 288 6.3.13 Middle-speed on-chip oscillator trimming register (MIOTRM) ........................................... 289 6.3.14 Low-speed on-chip oscillator trimming register (LIOTRM) ................................................ 290 6.3.15 Standby mode release setting register (WKUPMD) .......................................................... 291 6.4 System Clock Oscillator ......................................................................................................... 292 6.4.1 X1 oscillator ....................................................................................................................... 292 6.4.2 XT1 oscillator ..................................................................................................................... 292 6.4.3 High-speed on-chip oscillator ............................................................................................ 296 6.4.4 Middle-speed on-chip oscillator ......................................................................................... 296 6.4.5 Low-speed on-chip oscillator ............................................................................................. 296 6.5 Operations of the Clock Generator ........................................................................................ 297 6.6 Controlling Clocks .................................................................................................................. 299 6.6.1 Example of setting the high-speed on-chip oscillator ........................................................ 299 6.6.2 Example of setting the X1 oscillator clock ......................................................................... 301 6.6.3 Example of setting the XT1 oscillator clock ....................................................................... 302 6.6.4 State transitions of the CPU clock ..................................................................................... 303 6.6.5 Conditions before changing the CPU clock and processing
after changing the CPU clock ............................................................................................ 308 6.6.6 Time required for switchover of the CPU clock and main system clock ............................ 313 6.6.7 Conditions before clock oscillation is stopped ................................................................... 315 6.7 Resonator and Oscillator Constants ...................................................................................... 316
7. TIMER ARRAY UNIT (TAU) ......................................................................................................... 317
7.1 Functions of Timer Array Unit ................................................................................................ 319 7.1.1 Independent channel operation function ........................................................................... 319
7.1.2 Simultaneous channel operation function .......................................................................... 321
7.1.3 8-bit timer operation function (channels 1 and 3 only) ....................................................... 322
7.1.4 LIN-bus supporting function (channel 7 of unit 0 only) ...................................................... 322
7.2 Configuration of Timer Array Unit .......................................................................................... 323 7.2.1 Timer counter register mn (TCRmn) .................................................................................. 329 7.2.2 Timer data register mn (TDRmn) ....................................................................................... 331
7.3 Registers to Control the Timer Array Unit .............................................................................. 332 7.3.1 Peripheral enable register 0 (PER0) .................................................................................. 333 7.3.2 Peripheral reset control register 0 (PRR0) ........................................................................ 334
7.3.3 Timer clock select register m (TPSm) ................................................................................ 335
7.3.4 Timer mode register mn (TMRmn) .................................................................................... 339
7.3.5 Timer status register mn (TSRmn) .................................................................................... 347
7.3.6 7.3.7 7.3.8 7.3.9 7.3.10 7.3.11
Timer channel enable status register m (TEm) .................................................................. 348 Timer channel start register m (TSm) ................................................................................ 349 Timer channel stop register m (TTm) ................................................................................ 351 Timer input select register 0 (TIS0) ................................................................................... 352 Timer input select register 1 (TIS1) ................................................................................... 353 Timer output enable register m (TOEm) ............................................................................ 354
7.3.12 Timer output register m (TOm) .......................................................................................... 355
7.3.13 Timer output level register m (TOLm) ................................................................................ 356
Index - 4
7.3.14 Timer output mode register m (TOMm) ............................................................................. 357 7.3.15 Input switch control register (ISC) ..................................................................................... 358 7.3.16 Noise filter enable registers 1, 2 (NFEN1, NFEN2) ........................................................... 359 7.3.17 Registers controlling port functions of pins to be used for timer I/O .................................. 363 7.4 Basic Rules of Timer Array Unit ............................................................................................. 364 7.4.1 Basic rules of simultaneous channel operation function .................................................... 364 7.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only) ................................ 366 7.5 Operations of Counters ......................................................................................................... 367 7.5.1 Count clock (fTCLK) ............................................................................................................ 367 7.5.2 Timing of the start of counting ........................................................................................... 369 7.5.3 Operations of Counters ..................................................................................................... 370 7.6 Channel Output (TOmn Pin) Control ..................................................................................... 375 7.6.1 TOmn pin output circuit configuration ................................................................................ 375 7.6.2 TOmn pin output setting .................................................................................................... 376 7.6.3 Cautions on channel output operation ............................................................................... 377 7.6.4 Collective manipulation of TOmn bit .................................................................................. 383 7.6.5 Timer interrupts and TOmn outputs when counting is started ........................................... 384 7.7 Timer Input (TImn) Control .................................................................................................... 385 7.7.1 TImn input circuit configuration .......................................................................................... 385 7.7.2 Noise filter .......................................................................................................................... 385 7.7.3 Cautions on channel input operation ................................................................................. 386 7.8 Independent Channel Operation Function of Timer Array Unit .............................................. 387 7.8.1 Operation as an interval timer or for square wave output .................................................. 387 7.8.2 Operation as an external event counter ............................................................................ 391 7.8.3 Operation as a frequency divider (channel 0 of unit 0 only) .............................................. 395 7.8.4 Operation for input pulse interval measurement ................................................................ 400 7.8.5 Operation for input signal high-/low-level width measurement .......................................... 405 7.8.6 Operation as a delay counter ............................................................................................ 409 7.9 Simultaneous Channel Operation Function of Timer Array Unit ............................................ 413 7.9.1 Operation for the one-shot pulse output function .............................................................. 413 7.9.2 Operation for the PWM function ........................................................................................ 420 7.9.3 Operation for the multiple PWM output function ................................................................ 427 7.10 Cautions When Using Timer Array Unit ................................................................................. 435 7.10.1 Cautions when using timer output ..................................................................................... 435 7.10.2 Point for caution when a timer output is to be used as an event input for the ELCL ......... 435
8. REALTIME CLOCK (RTC) ........................................................................................................... 436
8.1 Functions of Realtime Clock .................................................................................................. 436 8.2 Configuration of the Realtime Clock ...................................................................................... 437 8.3 Registers to Control the Realtime Clock ................................................................................ 439
8.3.1 Peripheral enable register 0 (PER0) .................................................................................. 440 8.3.2 Subsystem clock supply mode control register (OSMC) ................................................... 441 8.3.3 Realtime clock control register 0 (RTCC0) ........................................................................ 442 8.3.4 Realtime clock control register 1 (RTCC1) ........................................................................ 444 8.3.5 Second count register (SEC) ............................................................................................. 446 8.3.6 Minute count register (MIN) ............................................................................................... 446 8.3.7 Hour count register (HOUR) .............................................................................................. 447 8.3.8 Day count register (DAY) ................................................................................................... 449 8.3.9 Day-of-week count register (WEEK) .................................................................................. 450
Index - 5
8.3.10 Month count register (MONTH) ......................................................................................... 451 8.3.11 Year count register (YEAR) ............................................................................................... 451 8.3.12 Time error correction register (SUBCUD) .......................................................................... 452 8.3.13 Alarm minute register (ALARMWM) .................................................................................. 453 8.3.14 Alarm hour register (ALARMWH) ...................................................................................... 453 8.3.15 Alarm day-of-week register (ALARMWW) ......................................................................... 454 8.3.16 Port mode register 3 (PM3) ............................................................................................... 454 8.3.17 Port register 3 (P3) ............................................................................................................ 455 8.4 Operations of the Realtime Clock .......................................................................................... 456 8.4.1 Starting the Realtime Clock Operation .............................................................................. 456 8.4.2 Shifting to HALT or STOP mode after starting operation ................................................... 457 8.4.3 Reading from and writing to the counters of the realtime clock ......................................... 458 8.4.4 Setting alarm by the realtime clock .................................................................................... 460 8.4.5 1 Hz output by the realtime clock ...................................................................................... 461 8.4.6 Example of time error correction by the realtime clock ...................................................... 462
9. 32-BIT INTERVAL TIMER (TML32) ............................................................................................. 467
9.1 Overview ................................................................................................................................ 467 9.2 Registers to Control the 32-bit Interval Timer ........................................................................ 469
9.2.1 Peripheral enable register 1 (PER1) .................................................................................. 470
9.2.2 Peripheral reset control register 1 (PRR1) ........................................................................ 471
9.2.3 Interval timer compare registers 0mn (ITLCMP0mn) (mn = 00, 01, 12, 13) ...................... 472
9.2.4 Interval timer compare registers 0n (ITLCMP0n) (n = 0, 1) ............................................... 472
9.2.5 Interval timer capture register 00 (ITLCAP00) ................................................................... 473
9.2.6 9.2.7 9.2.8 9.2.9 9.2.10
Interval timer control register (ITLCTL0) ............................................................................ 474 Interval timer clock select register 0 (ITLCSEL0) .............................................................. 476 Interval timer frequency division register 0 (ITLFDIV00) ................................................... 477 Interval timer frequency division register 1 (ITLFDIV01) ................................................... 479 Interval timer capture control register 0 (ITLCC0) ............................................................. 481
9.2.11 Interval timer status register (ITLS0) ................................................................................. 483
9.2.12 Interval timer match detection mask register (ITLMKF0) ................................................... 485
9.3 Operation ............................................................................................................................... 486
9.3.1 Counter mode settings ...................................................................................................... 486
9.3.2 9.3.3 9.3.4 9.3.5
Capture mode settings ...................................................................................................... 489 Timer operation .................................................................................................................. 490 Capture operation .............................................................................................................. 491 Interval timer setting procedures ....................................................................................... 493
9.3.6 Points for caution when the 32-bit interval timer is to be used .......................................... 497
10. CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER (PCLBUZ) .............................................. 499
10.1 Functions of Clock Output/Buzzer Output Controller ............................................................. 499 10.2 Configuration of Clock Output/Buzzer Output Controller ....................................................... 501 10.3 Registers to Control the Clock Output/Buzzer Output Controller ........................................... 501
10.3.1 Clock output select registers n (CKSn) .............................................................................. 501 10.3.2 Registers controlling port functions of pins to be used for clock or buzzer output ............ 503 10.4 Operations of the Clock Output/Buzzer Output Controller ..................................................... 504 10.4.1 Operation of Output Pins ................................................................................................... 504 10.5 Point for Caution when the Clock Output/Buzzer Output Controller is to be Used ................ 504
Index - 6
11. WATCHDOG TIMER (WDT) ........................................................................................................ 505
11.1 Functions of Watchdog Timer ................................................................................................ 505 11.2 Configuration of Watchdog Timer .......................................................................................... 506
11.3 Register to Control the Watchdog Timer ................................................................................ 507
11.3.1 Watchdog timer enable register (WDTE) ........................................................................... 507
11.4 Operation of Watchdog Timer ................................................................................................ 508
11.4.1 11.4.2 11.4.3 11.4.4
Controlling operation of watchdog timer ............................................................................ 508 Setting overflow time of watchdog timer ............................................................................ 509 Setting window open period of watchdog timer ................................................................. 510 Setting watchdog timer interval interrupt ........................................................................... 512
12. A/D CONVERTER (ADC) ............................................................................................................ 513
12.1 Function of A/D Converter ..................................................................................................... 513 12.2 Configuration of A/D Converter ............................................................................................. 516 12.3 Registers to Control the A/D Converter ................................................................................. 518
12.3.1 Peripheral enable register 0 (PER0) .................................................................................. 519 12.3.2 Peripheral reset control register 0 (PRR0) ........................................................................ 520 12.3.3 A/D converter mode register 0 (ADM0) ............................................................................. 521 12.3.4 A/D converter mode register 1 (ADM1) ............................................................................. 538 12.3.5 A/D converter mode register 2 (ADM2) ............................................................................. 539 12.3.6 12-bit/10-bit A/D conversion result register (ADCRn) ........................................................ 543 12.3.7 8-bit A/D conversion result register (ADCRnH) ................................................................. 544 12.3.8 Analog input channel specification register (ADS) ............................................................ 545 12.3.9 Conversion result comparison upper limit setting register (ADUL) .................................... 548 12.3.10 Conversion result comparison lower limit setting register (ADLL) ..................................... 548 12.3.11 A/D test register (ADTES) ................................................................................................. 549 12.3.12 Registers controlling port function of analog input pins ..................................................... 550 12.4 A/D Converter Operations ..................................................................................................... 551 12.5 Input Voltage and Conversion Results ................................................................................... 553 12.6 A/D Converter Operation Modes ........................................................................................... 554 12.6.1 Software trigger no-wait mode (select mode, sequential conversion mode) ..................... 554 12.6.2 Software trigger no-wait mode (select mode, one-shot conversion mode) ....................... 555 12.6.3 Software trigger no-wait mode (scan mode, sequential conversion mode) ....................... 556 12.6.4 Software trigger no-wait mode (scan mode, one-shot conversion mode) ......................... 557 12.6.5 Software trigger wait mode (select mode, sequential conversion mode) .......................... 558 12.6.6 Software trigger wait mode (select mode, one-shot conversion mode) ............................. 559 12.6.7 Software trigger wait mode (scan mode, sequential conversion mode) ............................ 560 12.6.8 Software trigger wait mode (scan mode, one-shot conversion mode) .............................. 561 12.6.9 Hardware trigger no-wait mode (select mode, sequential conversion mode) .................... 562 12.6.10 Hardware trigger no-wait mode (select mode, one-shot conversion mode) ...................... 563 12.6.11 Hardware trigger no-wait mode (scan mode, sequential conversion mode) ..................... 564 12.6.12 Hardware trigger no-wait mode (scan mode, one-shot conversion mode) ........................ 565 12.6.13 Hardware trigger wait mode (select mode, sequential conversion mode) ......................... 567 12.6.14 Hardware trigger wait mode (select mode, one-shot conversion mode) ........................... 568 12.6.15 Hardware trigger wait mode (scan mode, sequential conversion mode) ........................... 569 12.6.16 Hardware trigger wait mode (scan mode, one-shot conversion mode) ............................. 570 12.7 A/D Converter Setup Flowchart ............................................................................................. 571 12.7.1 Setting up software trigger no-wait mode .......................................................................... 571 12.7.2 Setting up software trigger wait mode ............................................................................... 572
Index - 7
12.7.3 Setting up hardware trigger no-wait mode ......................................................................... 573 12.7.4 Setting up hardware trigger wait mode .............................................................................. 574 12.7.5 Example of using the ADC when selecting the temperature sensor output voltage
or internal reference voltage, and software trigger no-wait mode and one-shot conversion mode ......................................................................................... 575 12.7.6 Setting up test mode .......................................................................................................... 576 12.8 SNOOZE Mode Function ....................................................................................................... 577 12.8.1 A/D conversion by inputting a software trigger .................................................................. 577 12.8.2 A/D conversion by inputting a hardware trigger ................................................................. 579 12.9 How to Read A/D Converter Characteristics Table ................................................................ 583 12.10 Points for Caution when the A/D Converter is to be Used ..................................................... 588
13. D/A CONVERTER (DAC) ............................................................................................................ 592 13.1 Functions of D/A Converter ................................................................................................... 592 13.2 Configuration of D/A Converter ............................................................................................. 593 13.3 Registers to Control the D/A Converter ................................................................................. 594 13.3.1 Peripheral enable register 1 (PER1) .................................................................................. 594 13.3.2 Peripheral reset control register 1 (PRR1) ........................................................................ 595 13.3.3 D/A converter mode register (DAM) .................................................................................. 596 13.3.4 D/A conversion value setting register i (DACSi) (i = 0, 1) .................................................. 596 13.3.5 Registers controlling the event output from the logic and event link controller .................. 597 13.3.6 Registers controlling port functions of analog input pins ................................................... 597 13.4 Operations of D/A Converter ................................................................................................. 598 13.4.1 Operation in normal mode ................................................................................................. 598 13.4.2 Operation in realtime output mode .................................................................................... 599 13.4.3 Timing for outputting D/A conversion value ....................................................................... 600 13.5 Points for Caution when the D/A Converter is to be Used ..................................................... 601
14. COMPARATOR (CMP) ................................................................................................................ 602 14.1 Functions of Comparator ....................................................................................................... 602 14.2 Configuration of Comparator ................................................................................................. 603 14.3 Registers to Control the Comparator ..................................................................................... 604 14.3.1 Peripheral enable register 1 (PER1) .................................................................................. 604 14.3.2 Peripheral reset control register 1 (PRR1) ........................................................................ 605 14.3.3 Comparator mode setting register (COMPMDR) ............................................................... 606 14.3.4 Comparator filter control register (COMPFIR) ................................................................... 608 14.3.5 Comparator output control register (COMPOCR) .............................................................. 610 14.3.6 Registers controlling port functions of analog input pins ....................................................611 14.4 Operation ............................................................................................................................... 612 14.4.1 Comparator i digital filter (i = 0, 1) ..................................................................................... 614 14.4.2 Comparator i (i = 0, 1) interrupts ........................................................................................ 615 14.4.3 Event signal output for the logic and event link controller (ELCL) ..................................... 615 14.4.4 Comparator i output (i = 0, 1) ............................................................................................. 616 14.4.5 Stopping or supplying comparator clock ............................................................................ 616
15. SERIAL ARRAY UNIT (SAU) ....................................................................................................... 617 15.1 Functions of Serial Array Unit ................................................................................................ 619 15.1.1 3-wire Serial SPI (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) ............... 619 15.1.2 UART (UART0 to UART3) ................................................................................................. 620
Index - 8
15.1.3 Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) ............................... 621 15.2 Configuration of Serial Array Unit .......................................................................................... 622
15.2.1 Shift Register ..................................................................................................................... 625 15.2.2 Lower 8 or 9 bits of the serial data register mn (SDRmn) .................................................. 625 15.3 Registers to Control the Serial Array Unit .............................................................................. 627 15.3.1 Peripheral enable register 0 (PER0) .................................................................................. 628 15.3.2 Peripheral reset control register 0 (PRR0) ........................................................................ 630 15.3.3 Serial clock select register m (SPSm) ............................................................................... 631 15.3.4 Serial mode register mn (SMRmn) .................................................................................... 632 15.3.5 Serial communication operation setting register mn (SCRmn) .......................................... 634 15.3.6 Serial data register mn (SDRmn) ...................................................................................... 638 15.3.7 Serial flag clear trigger register mn (SIRmn) ..................................................................... 640 15.3.8 Serial status register mn (SSRmn) .................................................................................... 641 15.3.9 Serial channel start register m (SSm) ................................................................................ 645 15.3.10 Serial channel stop register m (STm) ................................................................................ 646 15.3.11 Serial channel enable status register m (SEm) ................................................................. 647 15.3.12 Serial output enable register m (SOEm) ............................................................................ 648 15.3.13 Serial output register m (SOm) .......................................................................................... 649 15.3.14 Serial output level register m (SOLm) ............................................................................... 651 15.3.15 Serial standby control register m (SSCm) ......................................................................... 653 15.3.16 Input switch control register (ISC) ..................................................................................... 655 15.3.17 Noise filter enable register 0 (NFEN0) ............................................................................... 657 15.3.18 Registers controlling port functions of serial input/output pins .......................................... 659 15.3.19 UART loopback select register (ULBS) ............................................................................. 660 15.4 Operation Stop Mode ............................................................................................................. 661 15.4.1 Stopping the Operation by Units ........................................................................................ 661 15.4.2 Stopping the Operation by Channels ................................................................................. 662 15.5 Operation of 3-Wire Serial SPI (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30,
CSI31) Communication ......................................................................................................... 663 15.5.1 Master Transmission ......................................................................................................... 666 15.5.2 Master Reception .............................................................................................................. 675 15.5.3 Master Transmission/Reception ........................................................................................ 685 15.5.4 Slave Transmission ........................................................................................................... 695 15.5.5 Slave Reception ................................................................................................................ 705 15.5.6 Slave Transmission/Reception .......................................................................................... 713 15.5.7 SNOOZE Mode Function ................................................................................................... 723 15.5.8 Calculating Transfer Clock Frequency ............................................................................... 728 15.5.9 Procedure for Processing Errors that Occurred During 3-wire Serial SPI (CSI00,
CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) Communication .............................. 730 15.6 Operation of UART (UART0 to UART3) Communication ...................................................... 731
15.6.1 UART Transmission ........................................................................................................... 734 15.6.2 UART Reception ................................................................................................................ 744 15.6.3 SNOOZE Mode Function ................................................................................................... 751 15.6.4 Calculating Baud Rate ....................................................................................................... 758 15.6.5 Procedure for Processing Errors that Occurred During UART (UART0 to UART3)
Communication .................................................................................................................. 762 15.7 LIN Communication Operation .............................................................................................. 763
15.7.1 LIN Transmission ............................................................................................................... 763 15.7.2 LIN Reception .................................................................................................................... 766
Index - 9
15.8 Operation of Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) Communication ...................................................................................................................... 772
15.8.1 Address Field Transmission .............................................................................................. 775 15.8.2 Data Transmission ............................................................................................................. 781 15.8.3 Data Reception .................................................................................................................. 785 15.8.4 Stop Condition Generation ................................................................................................ 789 15.8.5 Calculating Transfer Rate .................................................................................................. 791 15.8.6 Procedure for Processing Errors that Occurred during Simplified I2C (IIC00, IIC01,
IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) Communication .................................................. 794
16. SERIAL INTERFACE IICA (IICA) ................................................................................................ 795 16.1 Functions of Serial Interface IICA .......................................................................................... 795 16.2 Configuration of Serial Interface IICA .................................................................................... 798 16.3 Registers to Control Serial Interface IICA .............................................................................. 801 16.3.1 Peripheral enable register 0 (PER0) .................................................................................. 802 16.3.2 Peripheral reset control register 0 (PRR0) ........................................................................ 803 16.3.3 IICA control register n0 (IICCTLn0) ................................................................................... 804 16.3.4 IICA status register n (IICSn) ............................................................................................. 810 16.3.5 IICA flag register n (IICFn) ................................................................................................. 814 16.3.6 IICA control register n1 (IICCTLn1) ................................................................................... 816 16.3.7 IICA low-level width setting register n (IICWLn) ................................................................ 819 16.3.8 IICA high-level width setting register n (IICWHn) .............................................................. 819 16.3.9 Registers to control the port function multiplexed with the IICA I/O pins ........................... 820 16.4 I2C Bus Mode Functions ........................................................................................................ 821 16.4.1 Pin Configuration ............................................................................................................... 821 16.4.2 Setting transfer clock by using IICWLn and IICWHn registers .......................................... 822 16.5 I2C Bus Definitions and Control Methods .............................................................................. 824 16.5.1 Start Conditions ................................................................................................................. 824 16.5.2 Address ............................................................................................................................. 825 16.5.3 Transfer Direction Specification ......................................................................................... 825 16.5.4 Acknowledge (ACK) .......................................................................................................... 826 16.5.5 Stop Condition ................................................................................................................... 827 16.5.6 Clock stretching ................................................................................................................. 828 16.5.7 Release from clock stretching ........................................................................................... 830 16.5.8 Timing of Generation of the Interrupt Request Signal (INTIICAn) and Control of Clock Stretching ............................................................................................................. 831 16.5.9 Address Match Detection Method ..................................................................................... 832 16.5.10 Error Detection .................................................................................................................. 832 16.5.11 Extension Code ................................................................................................................. 833 16.5.12 Arbitration .......................................................................................................................... 834 16.5.13 Wakeup Function ............................................................................................................... 836 16.5.14 Communication Reservation ............................................................................................. 839 16.5.15 Cautions ............................................................................................................................ 843 16.5.16 Communication Operations ............................................................................................... 844 16.5.17 Timing of I2C Interrupt Request Signal (INTIICAn) Occurrence ........................................ 852 16.6 Timing Charts ........................................................................................................................ 873
17. SERIAL INTERFACE UARTA (UARTA) ....................................................................................... 888 17.1 Overview ................................................................................................................................ 888
Index - 10
17.2 Registers to Control the Serial Interface UARTA ................................................................... 890 17.2.1 Peripheral enable register 1 (PER1) .................................................................................. 891 17.2.2 Transmit buffer register (TXBAn) (n = 0, 1) ....................................................................... 892 17.2.3 Receive buffer register (RXBAn) (n = 0, 1) ........................................................................ 893 17.2.4 Operation mode setting register 0 (ASIMAn0) (n = 0, 1) ................................................... 894 17.2.5 Operation mode setting register 1 (ASIMAn1) (n = 0, 1) ................................................... 896 17.2.6 Baud rate generator control register (BRGCAn) (n = 0, 1) ................................................ 897 17.2.7 Status register (ASISAn) (n = 0, 1) .................................................................................... 898 17.2.8 Status clear trigger register (ASCTAn) (n = 0, 1) ............................................................... 900 17.2.9 UARTA clock select register 0 (UTA0CK) .......................................................................... 901 17.2.10 UARTA clock select register 1 (UTA1CK) .......................................................................... 902 17.2.11 UART loopback select register (ULBS) ............................................................................. 903
17.3 Operation ............................................................................................................................... 904 17.3.1 Operation Stop Mode ......................................................................................................... 904 17.3.2 UART Mode ....................................................................................................................... 904 17.3.3 Receive Data Noise Filter .................................................................................................. 918 17.3.4 Baud Rate Generator ........................................................................................................ 919
17.4 Points for Caution when the Serial Interface UARTA is to be Used ...................................... 926 17.4.1 Port Setting for RxDAn Pin ................................................................................................ 926 17.4.2 Serial Interfaces ................................................................................................................. 926 17.4.3 Point for Caution when Selecting the UARTAn Operation Clock (fUTAn) ........................... 926
18. REMOTE CONTROL SIGNAL RECEIVER (REMC) ................................................................... 927
18.1 Remote Control Signal Receiver ........................................................................................... 927 18.2 Registers to Control the Remote Control Signal Receiver ..................................................... 929
18.2.1 Peripheral enable register 1 (PER1) .................................................................................. 930 18.2.2 Peripheral reset control register 1 (PRR1) ........................................................................ 931 18.2.3 Function select register 0 (REMCON0) ............................................................................. 932 18.2.4 Function select register 1 (REMCON1) ............................................................................. 934 18.2.5 Status register (REMSTS) ................................................................................................. 936 18.2.6 Interrupt control register (REMINT) ................................................................................... 940 18.2.7 Compare control register (REMCPC) ................................................................................ 941 18.2.8 Compare value setting register (REMCPD) ....................................................................... 942 18.2.9 Header pattern minimum width setting register (HDPMIN) ................................................ 942 18.2.10 Header pattern maximum width setting register (HDPMAX) ............................................. 943 18.2.11 Data '0' pattern minimum width setting register (D0PMIN) ................................................ 943 18.2.12 Data '0' pattern maximum width setting register (D0PMAX) .............................................. 944 18.2.13 Data '1' pattern minimum width setting register (D1PMIN) ................................................ 944 18.2.14 Data '1' pattern maximum width setting register (D1PMAX) .............................................. 945 18.2.15 Special data pattern minimum width setting register (SDPMIN) ........................................ 945 18.2.16 Special data pattern maximum width setting register (SDPMAX) ...................................... 946 18.2.17 Pattern end setting register (REMPE) ............................................................................... 946 18.2.18 Receiver standby control register (REMSTC) ................................................................... 947 18.2.19 Receive bit count register (REMRBIT) .............................................................................. 948 18.2.20 Receive data 0 register (REMDAT0) ................................................................................ 949 18.2.21 Receive data j register (REMDATj) (j = 1 to 7) .................................................................. 950 18.2.22 Measurement result register (REMTIM) ............................................................................ 951 18.3 Operation ............................................................................................................................... 952 18.3.1 Overview of REMC Operation ........................................................................................... 952
Index - 11
18.3.2 Initial Setting ...................................................................................................................... 952 18.3.3 Pattern Setting ................................................................................................................... 954 18.3.4 Operating Clock ................................................................................................................ 957
18.3.4.1 When using fSXP as the REMC operating clock ............................................................ 957 18.3.4.2 When using INTTM06 as the REMC operating clock .................................................... 957 18.3.5 RIN0 Input ......................................................................................................................... 958 18.3.6 Pattern Detection ............................................................................................................... 960 18.3.6.1 Header pattern detection ............................................................................................... 961 18.3.6.2 Data `0' pattern detection ............................................................................................... 961 18.3.6.3 Data `1' pattern detection ............................................................................................... 962 18.3.6.4 Special data pattern detection ....................................................................................... 962 18.3.6.5 Examples of setting pattern setting registers ................................................................. 963 18.3.6.6 Updating status flags upon pattern detection ................................................................ 963 18.3.7 Pattern End ........................................................................................................................ 965 18.3.8 Receive Data Buffer ........................................................................................................... 966 18.3.9 Compare Function ............................................................................................................. 970 18.3.10 Error Pattern Reception ..................................................................................................... 971 18.3.11 Storing Base Timer Value When Pattern is Detected ........................................................ 973 18.3.12 Interrupts ........................................................................................................................... 974 18.3.13 SNOOZE Mode Function ................................................................................................... 975 18.4 Points for Caution when the Remote Control Signal Receiver is to be Used ........................ 979 18.4.1 Register Access when Starting Operation of the Remote Control Signal Receiver ........... 979 18.4.2 Timing of Changing the Register Values ........................................................................... 979 18.4.3 RIN0 Input Control ............................................................................................................. 979 18.4.4 Changing the Operating Clock .......................................................................................... 979 18.4.5 Reading Registers ............................................................................................................. 980
19. DATA TRANSFER CONTROLLER (DTC) ................................................................................... 981
19.1 Functions of DTC ................................................................................................................... 981
19.2 Configuration of DTC ............................................................................................................. 983
19.3 Registers to Control the DTC ................................................................................................ 984
19.3.1 Allocation of DTC control data area and DTC vector table area ........................................ 985
19.3.2 Control data allocation ....................................................................................................... 986
19.3.3 19.3.4 19.3.5 19.3.6
Vector table ........................................................................................................................ 988 Peripheral enable register 1 (PER1) .................................................................................. 990 DTC control register j (DTCCRj) (j = 0 to 23) ..................................................................... 991 DTC block size register j (DTBLSj) (j = 0 to 23) ................................................................. 993
19.3.7 DTC transfer count register j (DTCCTj) (j = 0 to 23) .......................................................... 994
19.3.8 DTC transfer count reload register j (DTRLDj) (j = 0 to 23) ............................................... 994
19.3.9 DTC source address register j (DTSARj) (j = 0 to 23) ....................................................... 995
19.3.10 DTC destination address register j (DTDARj) (j = 0 to 23) ................................................ 995
19.3.11 DTC activation enable register i (DTCENi) (i = 0 to 4) ....................................................... 996 19.3.12 DTC base address register (DTCBAR) ............................................................................. 999 19.4 DTC Operation .................................................................................................................... 1000 19.4.1 Activation sources ........................................................................................................... 1001 19.4.2 Normal mode ................................................................................................................... 1002
19.4.3 Repeat mode ................................................................................................................... 1005
19.4.4 Chain transfers ................................................................................................................ 1009
Index - 12
19.5 Points for Caution when the DTC is to be Used ...................................................................1011 19.5.1 Setting DTC control data and vector table ........................................................................1011 19.5.2 Allocation of DTC control data area and DTC vector table area .......................................1011 19.5.3 DTC pending instruction .................................................................................................. 1012 19.5.4 Operation when accessing data flash memory space ..................................................... 1012 19.5.5 Number of DTC execution clock cycles ........................................................................... 1013 19.5.6 DTC response time .......................................................................................................... 1014 19.5.7 DTC activation sources ................................................................................................... 1014 19.5.8 Operation in standby mode ............................................................................................. 1015
20. LOGIC AND EVENT LINK CONTROLLER (ELCL) ................................................................... 1016 20.1 Functions of ELCL ............................................................................................................... 1016 20.2 Configuration of ELCL ......................................................................................................... 1016 20.3 Registers to Control the ELCL ............................................................................................. 1026 20.3.1 Input signal select registers n (ELISELn) (n = 0 to 11) .................................................... 1027 20.3.2 Event link L1 signal select registers n (ELL1SELn) (n = 0 to 3) ...................................... 1032 20.3.3 Event link L1 signal select registers n (ELL1SELn) (n = 4, 5) ......................................... 1034 20.3.4 Event link L1 signal select register 6 (ELL1SEL6) ........................................................... 1035 20.3.5 Logic cell block L1 control register (ELL1CTL) ................................................................ 1036 20.3.6 Event link L1 output select registers n (ELL1LNKn) (n = 0 to 3) ...................................... 1037 20.3.7 Event link L1 output select registers n (ELL1LNKn) (n = 4, 5) ......................................... 1038 20.3.8 Event link L1 output select register 6 (ELL1LNK6) .......................................................... 1039 20.3.9 Event link L2 signal select registers n (ELL2SELn) (n = 0 to 3) ...................................... 1040 20.3.10 Event link L2 signal select registers n (ELL2SELn) (n = 4, 5) ......................................... 1042 20.3.11 Event link L2 signal select register 6 (ELL2SEL6) ........................................................... 1043 20.3.12 Logic cell block L2 control register (ELL2CTL) ................................................................ 1044 20.3.13 Event link L2 output select registers n (ELL2LNKn) (n = 0 to 3) ...................................... 1045 20.3.14 Event link L2 output select registers n (ELL2LNKn) (n = 4, 5) ......................................... 1046 20.3.15 Event link L2 output select register 6 (ELL2LNK6) .......................................................... 1047 20.3.16 Event link L3 signal select registers n (ELL3SELn) (n = 0 to 3) ...................................... 1048 20.3.17 Event link L3 signal select registers n (ELL3SELn) (n = 4, 5) ......................................... 1050 20.3.18 Event link L3 signal select register 6 (ELL3SEL6) ........................................................... 1051 20.3.19 Logic cell block L3 control register (ELL3CTL) ................................................................ 1052 20.3.20 Event link L3 output select registers n (ELL3LNKn) (n = 0 to 3) ...................................... 1053 20.3.21 Event link L3 output select registers n (ELL3LNKn) (n = 4, 5) ......................................... 1054 20.3.22 Event link L3 output select register 6 (ELL3LNK6) .......................................................... 1055 20.3.23 Output signal select registers n (ELOSELn) (n = 0 to 7) ................................................. 1056 20.3.24 Output signal enable register (ELOENCTL) .................................................................... 1058 20.3.25 Output signal monitor register (ELOMONI) ..................................................................... 1060 20.4 ELCL Operation ................................................................................................................... 1061 20.5 Procedure of Setting the ELCL ............................................................................................ 1062 20.6 Points for Caution when the ELCL is to be Used ................................................................. 1065
21. INTERRUPT FUNCTIONS ........................................................................................................ 1066 21.1 Interrupt Function Types ...................................................................................................... 1066 21.2 Interrupt Sources and Configuration .................................................................................... 1066 21.3 Registers to Control the Interrupt Functions ........................................................................ 1073 21.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L, IF3H) ........... 1079
Index - 13
21.3.2 Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L, MK3H) ............................................................................................................................. 1081
21.3.3 Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR03H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L, PR13H) ..... 1083
21.3.4 External interrupt rising edge enable registers (EGP0, EGP1), External interrupt falling edge enable registers (EGN0, EGN1) ...................................... 1087
21.3.5 Program status word (PSW) ............................................................................................ 1089 21.4 Interrupt Servicing Operations ............................................................................................. 1090
21.4.1 Maskable interrupt request acknowledgment .................................................................. 1090 21.4.2 Software interrupt request acknowledgment ................................................................... 1093 21.4.3 Multiple interrupt servicing ............................................................................................... 1093 21.4.4 Interrupt request held pending ......................................................................................... 1097
22. KEY INTERRUPT FUNCTION .................................................................................................. 1098 22.1 Functions of the Key Interrupt ............................................................................................. 1098 22.2 Configuration of the Key Interrupt ........................................................................................ 1098 22.3 Registers to Control the Key Interrupt ..................................................................................1100 22.3.1 Key return control register (KRCTL) .................................................................................1100 22.3.2 Key return mode register 0 (KRM0) ..................................................................................1101 22.3.3 Key return flag register (KRF) ...........................................................................................1102 22.3.4 Port mode registers 7 (PM7) ............................................................................................1103
23. STANDBY FUNCTION ...............................................................................................................1104 23.1 Standby Function ..................................................................................................................1104 23.2 Registers to Control the Standby Function ...........................................................................1105 23.2.1 Standby mode release setting register (WKUPMD) .........................................................1106 23.2.2 Memory power reduction control register (PSMCR) .........................................................1107 23.3 Standby Function Operation .................................................................................................1109 23.3.1 HALT mode .......................................................................................................................1109 23.3.2 STOP mode ...................................................................................................................... 1115 23.3.3 SNOOZE mode ................................................................................................................1121
24. RESET FUNCTION ....................................................................................................................1126 24.1 Timing of Reset Operation ....................................................................................................1128 24.2 Registers to Control the Reset Function ...............................................................................1132 24.2.1 Reset control flag register (RESF) ....................................................................................1132 24.2.2 Power-on-reset status register (PORSR) .........................................................................1135 24.2.3 Peripheral reset control register 0 (PRR0) .......................................................................1136 24.2.4 Peripheral reset control register 1 (PRR1) .......................................................................1137
25. POWER-ON-RESET CIRCUIT (POR) ........................................................................................1138 25.1 Functions of Power-on-reset Circuit .....................................................................................1138 25.2 Configuration of Power-on-reset Circuit ................................................................................1139 25.3 Operation of Power-on-reset Circuit .....................................................................................1139
26. VOLTAGE DETECTOR (LVD) ....................................................................................................1142 26.1 Functions of Voltage Detector ...............................................................................................1142 26.2 Configuration of Voltage Detector .........................................................................................1143
Index - 14
26.3 Registers to Control the Voltage Detector ............................................................................1144 26.3.1 Voltage detection register (LVIM) ......................................................................................1144 26.3.2 LVD detection flag clearing register (LVDFCLR) ..............................................................1145 26.3.3 Voltage detection level register (LVIS) ..............................................................................1146
26.4 Operation of Voltage Detector ..............................................................................................1148 26.4.1 When used as reset mode ................................................................................................1148 26.4.2 When used as interrupt mode ..........................................................................................1151
26.5 Points for Caution when the Voltage Detector is to be Used ................................................1154
27. SAFETY FUNCTIONS ................................................................................................................1157 27.1 Overview of Safety Functions ...............................................................................................1157 27.2 Registers to Control the Safety Functions ............................................................................1158 27.3 Operation of Safety Functions ..............................................................................................1158 27.3.1 Flash memory CRC operation function (high-speed CRC) ..............................................1158 27.3.1.1 Flash memory CRC control register (CRC0CTL) ........................................................ 1159 27.3.1.2 Flash memory CRC operation result register (PGCRCL) ............................................ 1161 27.3.2 CRC operation (general-purpose CRC) ...........................................................................1163 27.3.2.1 CRC input register (CRCIN) ........................................................................................ 1163 27.3.2.2 CRC data register (CRCD) .......................................................................................... 1164 27.3.3 Flash memory guard function ...........................................................................................1165 27.3.3.1 Code flash memory guard register (GFLASH0) .......................................................... 1165 27.3.3.2 Data flash memory guard register (GFLASH1) ........................................................... 1166 27.3.3.3 Flash security area guard register (GFLASH2) ........................................................... 1167 27.3.4 RAM parity error detection ................................................................................................1168 27.3.4.1 RAM parity error control register (RPECTL) ................................................................ 1168 27.3.5 RAM guard function ..........................................................................................................1170 27.3.5.1 Invalid memory access detection control register (IAWCTL) ....................................... 1170 27.3.6 SFR guard function ...........................................................................................................1171 27.3.6.1 Invalid memory access detection control register (IAWCTL) ....................................... 1171 27.3.7 Illicit memory access detection .........................................................................................1172 27.3.7.1 Invalid memory access detection control register (IAWCTL) ....................................... 1173 27.3.8 Guard function of invalid memory access detection control register ................................1174 27.3.8.1 Guard register of IAWCTL register (GIAWCTL) .......................................................... 1174 27.3.9 Frequency detection .........................................................................................................1175 27.3.9.1 Timer input select register 0 (TIS0) ............................................................................. 1176 27.3.10 Testing of the A/D converter .............................................................................................1177 27.3.10.1A/D test register (ADTES) ........................................................................................... 1179 27.3.10.2Analog input channel specification register (ADS) ...................................................... 1180 27.3.11 Detection of the digital output signal level of the I/O pins .................................................1182 27.3.11.1Port mode select register (PMS) ................................................................................. 1182 27.3.12 UART loopback ................................................................................................................1183 27.3.12.1UART loopback select register (ULBS) ....................................................................... 1183
28. SECURITY FUNCTIONS ............................................................................................................1185 28.1 True Random Number Generator .........................................................................................1185 28.1.1 Function of the true random number generator ................................................................1185 28.1.2 Registers to control the true random number generator ...................................................1185 28.1.2.1 Random number seed command register 0 (TRNGSCR0) ......................................... 1186 28.1.2.2 Random number seed data register (TRNGSDR) ....................................................... 1187
Index - 15
28.1.3 Operations of the true random number generator ............................................................1188 28.2 Flash Read Protection ..........................................................................................................1189
28.2.1 Function of flash read protection ......................................................................................1189 28.2.2 Setting of flash read protection .........................................................................................1189 28.2.3 Operation ..........................................................................................................................1191 28.3 Unique ID ..............................................................................................................................1192 28.3.1 Function of a unique ID ....................................................................................................1192 28.3.2 ASCII codes representing the product name ....................................................................1192
29. SNOOZE MODE SEQUENCER (SMS) ......................................................................................1194 29.1 Functions of the SNOOZE Mode Sequencer .......................................................................1194 29.2 Configuration of the SNOOZE Mode Sequencer ..................................................................1194 29.3 Registers to Control the SNOOZE Mode Sequencer ...........................................................1195 29.3.1 Peripheral enable register 1 (PER1) .................................................................................1195 29.3.2 Peripheral reset control register 1 (PRR1) .......................................................................1196 29.3.3 Sequencer instruction registers p (SMSIp) (p = 0 to 31) ..................................................1197 29.3.4 Sequencer general-purpose registers n (SMSGn) (n = 0 to 15) ...................................... 1200 29.3.5 Sequencer control register (SMSC) ................................................................................. 1202 29.3.6 Sequencer status register (SMSS) .................................................................................. 1204 29.4 Operations of the SNOOZE Mode Sequencer .................................................................... 1205 29.4.1 Internal operations of the SNOOZE mode sequencer ..................................................... 1205 29.4.2 Memory space allocated to the sequencer ...................................................................... 1206 29.4.3 Sequencer flags ............................................................................................................... 1208 29.4.4 Procedures for running the SNOOZE mode sequencer .................................................. 1209 29.4.5 States of the SNOOZE mode sequencer ..........................................................................1211 29.5 Commands for Use in Processing by the Sequencer .......................................................... 1212 29.5.1 8-bit data transfer 1 ......................................................................................................... 1213 29.5.2 8-bit data transfer 2 ......................................................................................................... 1214 29.5.3 16-bit data transfer 1 ....................................................................................................... 1215 29.5.4 16-bit data transfer 2 ....................................................................................................... 1216 29.5.5 1-bit data setting .............................................................................................................. 1217 29.5.6 1-bit data clearing ............................................................................................................ 1218 29.5.7 1-bit data transfer ............................................................................................................ 1219 29.5.8 Word addition .................................................................................................................. 1220 29.5.9 Word subtraction ............................................................................................................. 1221 29.5.10 Word comparison ............................................................................................................. 1222 29.5.11 Logical shift right .............................................................................................................. 1223 29.5.12 Branch 1 (SCY = 1) ......................................................................................................... 1224 29.5.13 Branch 2 (SCY = 0) ......................................................................................................... 1225 29.5.14 Branch 3 (SZ = 1) ............................................................................................................ 1226 29.5.15 Branch 4 (SZ = 0) ............................................................................................................ 1227 29.5.16 Wait .................................................................................................................................. 1228 29.5.17 Conditional wait 1 (bit = 1) ............................................................................................... 1230 29.5.18 Conditional wait 2 (bit = 0) ............................................................................................... 1231 29.5.19 Termination ...................................................................................................................... 1232 29.5.20 Interrupt plus termination ................................................................................................. 1233 29.5.21 DTC activation ................................................................................................................. 1234 29.6 Operation in Standby Modes ............................................................................................... 1235
Index - 16
30. CAPACITIVE SENSING UNIT (CTSU2L) .................................................................................. 1236
30.1 Overview .............................................................................................................................. 1238 30.2 Registers to Control the Capacitive Sensing Unit ................................................................ 1240
30.2.1 Peripheral enable register 1 (PER1) ................................................................................ 1241
30.2.2 Peripheral reset control register 1 (PRR1) ...................................................................... 1241
30.2.3 CTSU control registers AL and AH (CTSUCRAL, CTSUCRAH) ..................................... 1242
30.2.4 30.2.5 30.2.6
30.2.7
CTSU control registers BL and BH (CTSUCRBL, CTSUCRBH) ..................................... 1249 CTSU measurement channel registers L and H (CTSUMCHL, CTSUMCHH) ................ 1252 CTSU channel enable control registers AL, AH, BL, and BH (CTSUCHACAL, CTSUCHACAH, CTSUCHACBL, CTSUCHACBH) ............................. 1254 CTSU channel transmit/receive control registers AL, AH, BL, and BH (CTSUCHTRCAL, CTSUCHTRCAH, CTSUCHTRCBL, CTSUCHTRCBH) .................... 1256
30.2.8 CTSU status register L (CTSUSRL) ................................................................................ 1258
30.2.9 CTSU sensor offset registers 0 and 1 (CTSUSO0, CTSUSO1) ...................................... 1261
30.2.10 CTSU sensor counter registers L and H (CTSUSC, CTSUUC) ...................................... 1263
30.2.11 CTSU calibration registers L and H (CTSUDBGR0, CTSUDBGR1) ............................... 1264 30.2.12 CTSU sensor unit clock control registers AL, AH, BL, and BH
(CTSUSUCLK0, CTSUSUCLK1, CTSUSUCLK2, CTSUSUCLK3) ................................. 1267 30.2.13 CTSU trimming registers AL and AH (CTSUTRIM0, CTSUTRIM1) ................................ 1269 30.2.14 CTSU trimming registers BL and BH (CTSUTRIM2, CTSUTRIM3) ................................ 1271
31. REGULATOR ............................................................................................................................. 1272 31.1 Overview .............................................................................................................................. 1272
32. OPTION BYTES ........................................................................................................................ 1273
32.1 Functions of Option Bytes ................................................................................................... 1273 32.1.1 User option bytes (000C0H to 000C2H or 040C0H to 040C2H) ..................................... 1273 32.1.2 On-chip debug option byte (000C3H or 040C3H) ........................................................... 1274
32.2 Format of User Option Bytes ............................................................................................... 1275 32.3 Format of On-chip Debug Option Byte ................................................................................ 1280 32.4 Setting of Option Bytes ........................................................................................................ 1281
33. FLASH MEMORY ...................................................................................................................... 1282
33.1 Serial Programming Using Flash Memory Programmer ...................................................... 1283 33.1.1 Programming environment .............................................................................................. 1285 33.1.2 Communication mode ...................................................................................................... 1285
33.2 Serial Programming Using External Device (that Incorporates UART) ............................... 1286 33.2.1 Programming environment .............................................................................................. 1286 33.2.2 Communication mode ...................................................................................................... 1287
33.3 Connection of Pins on Board ............................................................................................... 1288 33.3.1 P40/TOOL0 pin ................................................................................................................ 1288 33.3.2 RESET pin ....................................................................................................................... 1289 33.3.3 Port pins .......................................................................................................................... 1289 33.3.4 REGC pin ........................................................................................................................ 1289 33.3.5 X1 and X2 pins ................................................................................................................ 1289 33.3.6 Power supply ................................................................................................................... 1289
33.4 Programming Method .......................................................................................................... 1290 33.4.1 Serial programming procedure ........................................................................................ 1290 33.4.2 Flash memory programming mode .................................................................................. 1291
Index - 17
33.4.3 Selecting communication mode ....................................................................................... 1292 33.4.4 Communication commands ............................................................................................. 1293 33.5 Processing Times for Commands When the Dedicated Flash Memory Programmer Is
in Use (Reference Values) ................................................................................................... 1295 33.6 Self-Programming ................................................................................................................ 1296
33.6.1 Self-programming procedure ........................................................................................... 1297 33.6.2 Registers to control the flash memory ............................................................................. 1298
33.6.2.1 Flash address pointer registers H and L (FLAPH, FLAPL) .......................................... 1300 33.6.2.2 Flash end address pointer registers H and L (FLSEDH, FLSEDL) ............................. 1301 33.6.2.3 Flash write buffer registers H and L (FLWH, FLWL) ................................................... 1303 33.6.2.4 Flash protect command register (PFCMD) .................................................................. 1304 33.6.2.5 Flash status register (PFS) .......................................................................................... 1305 33.6.2.6 Flash programming mode control register (FLPMC) ................................................... 1306 33.6.2.7 Flash area selection register (FLARS) ........................................................................ 1307 33.6.2.8 Flash memory sequencer initial setting register (FSSET) ........................................... 1308 33.6.2.9 Flash memory sequencer control register (FSSQ) ...................................................... 1310 33.6.2.10Flash extra sequencer control register (FSSE) ........................................................... 1312 33.6.2.11Flash registers initialization register (FLRST) .............................................................. 1313 33.6.2.12Flash memory sequencer status registers H and L (FSASTH, FSASTL) .................... 1314 33.6.2.13Flash security flag monitoring register (FLSEC) .......................................................... 1316 33.6.2.14Flash FSW monitoring register E (FLFSWE) ............................................................... 1317 33.6.2.15Flash FSW monitoring register S (FLFSWS) ............................................................... 1318 33.6.2.16Data flash control register (DFLCTL) ........................................................................... 1319 33.6.2.17Interrupt vector jump enable register (VECTCTRL) .................................................... 1320 33.6.2.18Interrupt vector change registers 0 and 1 (FLSIVC0, FLSIVC1) ................................. 1321 33.6.3 Setting the flash memory control mode ........................................................................... 1322 33.6.3.1 Procedure for executing the specific sequence ........................................................... 1322 33.6.3.2 Procedure for entry to the code flash programming mode .......................................... 1322 33.6.3.3 Procedure for entry to the data flash programming mode ........................................... 1322 33.6.3.4 Procedure for entry to the rewrite-disabled mode ....................................................... 1323 33.6.4 Clearing the registers for use with the flash memory sequencer ..................................... 1324 33.6.5 Setting the operating frequency of the flash memory sequencer .................................... 1324 33.6.6 Commands for use with the flash memory sequencer in the respective areas ............... 1325 33.6.6.1 Overview ...................................................................................................................... 1325 33.6.6.2 Selecting the area to be rewritten ................................................................................ 1325 33.6.6.3 Commands for use with the code/data flash memory area sequencer ....................... 1325 33.6.6.4 Operations for rewriting the code flash memory area ................................................. 1326 33.6.6.5 Operations for rewriting the data flash memory area .................................................. 1327 33.6.6.6 Commands for use with the extra area sequencer ...................................................... 1328 33.6.6.7 Operations for rewriting the extra area ........................................................................ 1328 33.6.6.8 Data to be set for the commands for use with the extra area sequencer .................... 1329 33.6.6.9 Procedures for checking completion of the commands for use
with the flash memory sequencer in the respective areas ........................................... 1332 33.6.6.10Procedure for forcibly terminating a command for use
with the code/data flash memory area sequencer ....................................................... 1332 33.6.7 Boot swap function .......................................................................................................... 1333 33.6.8 Flash shield window function ........................................................................................... 1335 33.6.9 Interrupts in code flash programming mode .................................................................... 1336
33.6.9.1 Overview ...................................................................................................................... 1336
Index - 18
33.6.9.2 Operation to change the branch destinations of the interrupts .................................... 1336 33.6.9.3 Operation to change the interrupt branch destination ................................................. 1337 33.6.10 Example of executing the commands to rewrite the flash memory areas ....................... 1338 33.6.10.1Example of executing the commands to rewrite the code flash memory area ............ 1338 33.6.10.2Example of executing the commands to rewrite the data flash memory area ............. 1339 33.6.10.3Example of executing the commands to rewrite the extra area ................................... 1340 33.6.11 Notes on self-programming ............................................................................................. 1341 33.7 Security Settings .................................................................................................................. 1342 33.8 Data Flash Memory ............................................................................................................. 1344 33.8.1 Overview of the data flash memory ................................................................................. 1344 33.8.2 Procedure for accessing the data flash memory ............................................................. 1345
34. ON-CHIP DEBUGGING ............................................................................................................. 1346 34.1 Connection between the E2 or E2 Lite On-chip Debugging Emulator and RL78/G23 ........ 1346 34.2 Connection between the External Device that Incorporates UART and RL78/G23 ............. 1347 34.3 Security ID Codes for On-Chip Debugging .......................................................................... 1347 34.4 Allocation of Memory Spaces to User Resources ................................................................ 1347
35. BCD CORRECTION CIRCUIT .................................................................................................. 1349 35.1 BCD Correction Circuit Function .......................................................................................... 1349 35.2 Register to Control the BCD Correction Circuit ................................................................... 1349 35.2.1 BCD correction result register (BCDADJ) ........................................................................ 1349 35.3 BCD Correction Circuit Operation ........................................................................................ 1350
36. INSTRUCTION SET .................................................................................................................. 1352 36.1 Conventions Used in Operation List .................................................................................... 1353 36.1.1 Operand identifiers and specification methods ................................................................ 1353 36.1.2 Description of operation column ...................................................................................... 1354 36.1.3 Description of flag operation column ............................................................................... 1355 36.1.4 PREFIX instruction .......................................................................................................... 1355 36.2 Operation List ...................................................................................................................... 1356
37. ELECTRICAL CHARACTERISTICS TA = -40 to +105°C .......................................................... 1374 37.1 Absolute Maximum Ratings ................................................................................................. 1374 37.2 Characteristics of the Oscillators ......................................................................................... 1376 37.2.1 Characteristics of the X1 and XT1 oscillators .................................................................. 1376 37.2.2 Characteristics of the On-chip Oscillators ....................................................................... 1377 37.3 DC Characteristics ............................................................................................................... 1378 37.3.1 Pin characteristics ........................................................................................................... 1378 37.3.2 Supply current characteristics ......................................................................................... 1387 37.4 AC Characteristics ............................................................................................................... 1395 37.5 Characteristics of the Peripheral Functions ........................................................................ 1401 37.5.1 Serial array unit ............................................................................................................... 1401 37.5.2 Serial interface UARTA .................................................................................................... 1430 37.5.3 Serial interface IICA ......................................................................................................... 1431 37.6 Analog Characteristics ......................................................................................................... 1434 37.6.1 A/D converter characteristics ........................................................................................... 1434 37.6.2 Temperature sensor/internal reference voltage characteristics ....................................... 1438 37.6.3 D/A converter characteristics ........................................................................................... 1438
Index - 19
37.6.4 Comparator characteristics .............................................................................................. 1438 37.6.5 POR circuit characteristics .............................................................................................. 1439 37.6.6 LVD circuit characteristics ............................................................................................... 1440 37.6.7 Power supply voltage rising slope characteristics ........................................................... 1442 37.7 RAM Data Retention Characteristics ................................................................................... 1443 37.8 Flash Memory Programming Characteristics ....................................................................... 1443 37.9 Dedicated Flash Memory Programmer Communication (UART) ......................................... 1445 37.10 Timing of Entry to Flash Memory Programming Modes ...................................................... 1445
38. PACKAGE DRAWINGS ............................................................................................................. 1446
38.1 30-Pin Products ................................................................................................................... 1446
38.2 32-Pin Products ................................................................................................................... 1447
38.3 36-Pin Products ................................................................................................................... 1449
38.4 40-Pin Products ................................................................................................................... 1450
38.5 44-Pin Products ................................................................................................................... 1451
38.6 38.7 38.8 38.9 38.10
48-Pin Products ................................................................................................................... 1452 52-Pin Products ................................................................................................................... 1454 64-Pin Products ................................................................................................................... 1455 80-Pin Products ................................................................................................................... 1458 100-Pin Products ................................................................................................................. 1460
38.11 128-Pin Products ................................................................................................................. 1462
APPENDIX A REVISION HISTORY ................................................................................................... 1463 A.1 Major Revisions in This Edition ........................................................................................... 1463 A.2 Revision History of Preceding Editions ................................................................................ 1467
Index - 20
RL78/G23
RENESAS MCU
CHAPTER 1 OUTLINE
R01UH0896EJ0100 Rev.1.00
Apr 13, 2021
1.1
Features
Ultra-low power consumption technology · VDD = single power supply voltage of 1.6 to 5.5 V · HALT mode · STOP mode High-speed wakeup from the STOP mode is possible. · SNOOZE mode
RL78 CPU core · CISC architecture with 3-stage pipeline · Minimum instruction execution time: Can be changed from high speed (0.03125 µs @ 32 MHz operation with the high-speed on-chip oscillator clock) to ultra-low speed (30.5 µs @ 32.768 kHz operation with the subsystem clock) · Multiply/divide/multiply & accumulate instructions are supported. · Address space: 1 MB · General-purpose registers: (8-bit register × 8) × 4 banks · On-chip RAM: 12 to 48 KB
Code flash memory · Code flash memory: 96 to 768 KB · Block size: 2 KB · Prohibition of block erase and rewriting (security function) · On-chip debugging · Self-programming (with boot swapping and flash shield window)
Data flash memory · Data flash memory: 8 KB · Back ground operation (BGO): Instructions can be executed from the program memory while rewriting the data flash memory. · Number of rewrites: 1,000,000 times (typ.)
High-speed on-chip oscillator · Select from 32 MHz, 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, or 1 MHz · High accuracy: ±1.0% (VDD = 1.8 to 5.5 V, TA = -20 to +85°C)
Middle-speed on-chip oscillator · Select from 4 MHz, 3 MHz, 2 MHz, or 1 MHz (with adjustability)
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 1 of 1478
RL78/G23
CHAPTER 1 OUTLINE
Low-speed on-chip oscillator · 32.768 kHz (typ.) (with adjustability)
Operating ambient temperature · TA = -40 to +85°C (2D: Consumer applications) · TA = -40 to +105°C (3C: Industrial applications)
Power management and reset function · On-chip power-on-reset (POR) circuit · On-chip voltage detectors (LVD0 and LVD1)
Data transfer controller (DTC) · Transfer modes: Normal transfer mode, repeat transfer mode, block transfer mode · Activation sources: Activated by interrupt sources. · Chain transfer function
SNOOZE mode sequencer (SMS) · Calculations and comparison of values by the commands for use in processing by the sequencer can realize intermittent operations where the RL78/G23 does not have to return to normal operation. · Sequentially handling a total of 32 processes with the use of desired commands from among 21 different ones · The SNOOZE mode sequencer offers operation with low power consumption without using the CPU, flash memory, and RAM.
Logic and event link controller (ELCL) · Event signals can be set up between specified peripheral functions. · The signals can be generated by the input of multiple event signals to the logic circuit. · Flip-flop circuits are incorporated to handle setting and resetting functions.
Serial interface · SPI (CSINote): 3 to 8 channels · UART/UART (LIN-bus supported)/UARTA: 3 to 6 channels · I2C/Simplified I2C: 4 to 10 channels
Remote control signal receiver · 1 channel · Matching of 4 waveform patterns (header, data 0, data 1, and special data)
Timer · 16-bit timer: 8 to 16 channels · 32-bit interval timer: 1 channel in 32-bit mode 2 channels in 16-bit mode 4 channels in 8-bit mode · Realtime clock: 1 channel (counting of one second to 99 years, alarm interrupt, and clock correction) · Watchdog timer: 1 channel (operates with the dedicated low-speed on-chip oscillator clock)
<R> Note
Although the CSI function is generally called SPI, it is also called CSI in this product, so it is referred to as such in this manual.
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RL78/G23
CHAPTER 1 OUTLINE
A/D converter · 8-/10-/12-bit resolution A/D converter (VDD = 1.6 to 5.5 V) · Analog input: 8 to 26 channels · Internal reference voltage (1.48 V) and temperature sensor
D/A converter · 8-bit resolution D/A converter (VDD = 1.6 to 5.5 V) · Analog output: 2 channels · Output voltage: 0 V to VDD · Realtime output function
Comparator · 2 channels · Operating modes: Comparator high-speed mode and comparator low-speed mode · The external reference voltage and the internal reference voltage or D/A converter output are selectable as the reference voltage.
Capacitive sensing unit
<R>
· CTSU2L operating voltage condition: VDD = 1.8 to 5.5 V
· Self-capacitance method: A single pin configures a single key, supporting up to 32 keys
· Mutual capacitance method: Matrix configuration with 8 × 8 pins, supporting up to 64 keys
Input/output port pins · Number of port pins: 26 to 120 (N-ch open drain I/O [withstand voltage of 6 V]: 2 to 4, N-ch open drain I/O [VDD withstand voltage Note 1/EVDD withstand voltageNote 2]: 10 to 33, output current control pins: 6 to 8) · Can be set to N-ch open drain or TTL input buffer, and use of an on-chip pull-up resistor can be specified. · Connectable to a device with different voltage (1.8, 2.5, or 3 V)
Others · BCD (binary-coded decimal) correction circuit · Key interrupt input · Clock output/buzzer output controller
Note 1. Note 2.
This applies to the 30- to 52-pin products. This applies to the 64- to 128-pin products.
Remark The functions mounted depend on the product. See 1.6 Outline of Functions.
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RL78/G23
CHAPTER 1 OUTLINE
ROM, RAM capacities
Flash ROM
Data flash
RAM
30 pins
768 KB 8 KB 48 KB --
512 KB 8 KB 48 KB --
384 KB 8 KB 32 KB --
256 KB 8 KB 24 KB R7F100GAJ
192 KB 8 KB 20 KB R7F100GAH
128 KB 8 KB 16 KB R7F100GAG
96 KB 8 KB 12 KB R7F100GAF
32 pins -- -- -- R7F100GBJ R7F100GBH R7F100GBG R7F100GBF
RL78/G23
36 pins
40 pins
--
--
--
--
--
--
R7F100GCJ R7F100GEJ
R7F100GCH R7F100GEH
R7F100GCG R7F100GEG
R7F100GCF R7F100GEF
44 pins R7F100GFN R7F100GFL R7F100GFK R7F100GFJ R7F100GFH R7F100GFG R7F100GFF
48 pins R7F100GGN R7F100GGL R7F100GGK R7F100GGJ R7F100GGH R7F100GGG R7F100GGF
Flash Data ROM flash 768 KB 8 KB 512 KB 8 KB 384 KB 8 KB 256 KB 8 KB 192 KB 8 KB 128 KB 8 KB 96 KB 8 KB
RAM
48 KB 48 KB 32 KB 24 KB 20 KB 16 KB 12 KB
52 pins R7F100GJN R7F100GJL R7F100GJK R7F100GJJ R7F100GJH R7F100GJG R7F100GJF
64 pins R7F100GLN R7F100GLL R7F100GLK R7F100GLJ R7F100GLH R7F100GLG R7F100GLF
RL78/G23 80 pins
R7F100GMN R7F100GML R7F100GMK R7F100GMJ R7F100GMH R7F100GMG --
100 pins R7F100GPN R7F100GPL R7F100GPK R7F100GPJ R7F100GPH R7F100GPG --
128 pins R7F100GSN R7F100GSL R7F100GSK R7F100GSJ -- -- --
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RL78/G23
1.2
List of Part Numbers
<R> Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G23
CHAPTER 1 OUTLINE
Ordering part number
Product name
R 7 F 1 0 0 G L J 3 x x x C F B # AA0
Packaging specification #BA0, #AA0: Tray (LFQFP, LQFP, LSSOP, HWQFN) #BC0, #AC0: Tray (WFLGA) #HA0: Embossed tape (LFQFP, LQFP, LSSOP, HWQFN) #HC0: Embossed tape (WFLGA)
Package type SP: LSSOP, 0.65-mm pitch FP: LQFP, 0.80-mm pitch FA: LQFP, 0.65-mm pitch FB: LFQFP, 0.50-mm pitch NP: HWQFN, 0.50-mm pitch LA: WFLGA, 0.50-mm pitch BG: VFBGA, 0.40-mm pitch
Fields of application C: Industrial applications D: Consumer applications
ROM number (omitted with blank products)
Ambient operating temperature range 2: -40 to +85°C 3: -40 to +105°C
ROM capacity F: 96 KB G: 128 KB H: 192 KB J: 256 KB K: 384 KB L: 512 KB N: 768 KB
Pin count A: 30 pins B: 32 pins C: 36 pins E: 40 pins F: 44 pins G: 48 pins J: 52 pins L: 64 pins M: 80 pins P: 100 pins S: 128 pins
RL78/G23
Device type F: Flash memory
Renesas MCU
Renesas semiconductor product
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RL78/G23
CHAPTER 1 OUTLINE
<R>
Table 1 - 1 List of Ordering Part Numbers (1/3)
Pin count
Package
Fields of Application
Note 1
Ordering Part Number Product Name
30 pins 30-pin plastic LSSOP
C
(7.62 mm (300), 0.65-mm pitch)
R7F100GAF3CSP, R7F100GAG3CSP, R7F100GAH3CSP, R7F100GAJ3CSP
D
R7F100GAF2DSP, R7F100GAG2DSP,
R7F100GAH2DSP, R7F100GAJ2DSP
32 pins 32-pin plastic HWQFN
C
(5 × 5 mm, 0.5-mm pitch)
R7F100GBF3CNP, R7F100GBG3CNP, R7F100GBH3CNP, R7F100GBJ3CNP
D
R7F100GBF2DNP, R7F100GBG2DNP,
R7F100GBH2DNP, R7F100GBJ2DNP
32 pins 32-pin plastic LQFP
C
(7 × 7 mm, 0.80-mm pitch)
R7F100GBF3CFP, R7F100GBG3CFP, R7F100GBH3CFP, R7F100GBJ3CFP
D
R7F100GBF2DFP, R7F100GBG2DFP,
R7F100GBH2DFP, R7F100GBJ2DFP
36 pins 36-pin plastic WFLGA
C
(4 × 4 mm, 0.50-mm pitch)
R7F100GCF3CLA, R7F100GCG3CLA, R7F100GCH3CLA, R7F100GCJ3CLA
Packaging Renesas Code Specification #AA0, #BA0 PLSP0030JB-B #HA0
#AA0, #BA0 PWQN0032KE-A #HA0
#AA0, #BA0 PLQP0032GB-A #HA0
#BC0, #AC0 Note 2 #HC0
D
40 pins 40-pin plastic HWQFN
C
(6 × 6 mm, 0.50-mm pitch)
D
44 pins 44-pin plastic LQFP
C
(10 × 10 mm, 0.80-mm pitch)
D
48 pins 48-pin plastic LFQFP
C
(7 × 7 mm, 0.50-mm pitch)
D
48 pins 48-pin plastic HWQFN
C
(7 × 7 mm, 0.50-mm pitch)
D
R7F100GCF2DLA, R7F100GCG2DLA, R7F100GCH2DLA, R7F100GCJ2DLA
R7F100GEF3CNP, R7F100GEG3CNP, R7F100GEH3CNP, R7F100GEJ3CNP
R7F100GEF2DNP, R7F100GEG2DNP, R7F100GEH2DNP, R7F100GEJ2DNP
R7F100GFF3CFP, R7F100GFG3CFP, R7F100GFH3CFP, R7F100GFJ3CFP, R7F100GFK3CFP, R7F100GFL3CFP, R7F100GFN3CFP
R7F100GFF2DFP, R7F100GFG2DFP, R7F100GFH2DFP, R7F100GFJ2DFP, R7F100GFK2DFP, R7F100GFL2DFP, R7F100GFN2DFP
R7F100GGF3CFB, R7F100GGG3CFB, R7F100GGH3CFB, R7F100GGJ3CFB, R7F100GGK3CFB, R7F100GGL3CFB, R7F100GGN3CFB
R7F100GGF2DFB, R7F100GGG2DFB, R7F100GGH2DFB, R7F100GGJ2DFB, R7F100GGK2DFB, R7F100GGL2DFB, R7F100GGN2DFB
R7F100GGF3CNP, R7F100GGG3CNP, R7F100GGH3CNP, R7F100GGJ3CNP, R7F100GGK3CNP, R7F100GGL3CNP, R7F100GGN3CNP
R7F100GGF2DNP, R7F100GGG2DNP, R7F100GGH2DNP, R7F100GGJ2DNP, R7F100GGK2DNP, R7F100GGL2DNP, R7F100GGN2DNP
#AA0, #BA0 PWQN0040KD-A #HA0
#AA0, #BA0 PLQP0044GC-A #HA0
#AA0, #BA0 PLQP00048KB-B #HA0
#AA0, #BA0 PWQN0048KC-A #HA0
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RL78/G23
CHAPTER 1 OUTLINE
<R>
Table 1 - 1 List of Ordering Part Numbers (2/3)
Pin count
Package
Fields of Application
Note 1
Ordering Part Number Product Name
Packaging Specification
Renesas Code
52 pins 52-pin plastic LQFP
C
(10 × 10 mm, 0.65-mm pitch)
R7F100GJF3CFA, R7F100GJG3CFA, R7F100GJH3CFA, R7F100GJJ3CFA, R7F100GJK3CFA, R7F100GJL3CFA, R7F100GJN3CFA
#AA0, #BA0 PLQP0052JA-A #HA0
D
R7F100GJF2DFA, R7F100GJG2DFA,
R7F100GJH2DFA, R7F100GJJ2DFA,
R7F100GJK2DFA, R7F100GJL2DFA,
R7F100GJN2DFA
64 pins 64-pin plastic LQFP
C
(12 × 12 mm, 0.65-mm pitch)
R7F100GLF3CFA, R7F100GLG3CFA, R7F100GLH3CFA, R7F100GLJ3CFA, R7F100GLK3CFA, R7F100GLL3CFA, R7F100GLN3CFA
#AA0, #BA0 PLQP0064JA-A #HA0
D
R7F100GLF2DFA, R7F100GLG2DFA,
R7F100GLH2DFA, R7F100GLJ2DFA,
R7F100GLK2DFA, R7F100GLL2DFA,
R7F100GLN2DFA
64 pins 64-pin plastic LFQFP
C
(10 × 10 mm, 0.50-mm pitch)
R7F100GLF3CFB, R7F100GLG3CFB, R7F100GLH3CFB, R7F100GLJ3CFB, R7F100GLK3CFB, R7F100GLL3CFB, R7F100GLN3CFB
#AA0, #BA0 PLQP0064KB-C #HA0
D
R7F100GLF2DFB, R7F100GLG2DFB,
R7F100GLH2DFB, R7F100GLJ2DFB,
R7F100GLK2DFB, R7F100GLL2DFB,
R7F100GLN2DFB
64 pins 64-pin plastic WFLGA
C
(5 × 5 mm, 0.50-mm pitch)
R7F100GLF3CLA, R7F100GLG3CLA, R7F100GLH3CLA, R7F100GLJ3CLA, R7F100GLK3CLA, R7F100GLL3CLA, R7F100GLN3CLA
#BC0, #AC0 Note 3 #HC0
D
R7F100GLF2DLA, R7F100GLG2DLA,
R7F100GLH2DLA, R7F100GLJ2DLA,
R7F100GLK2DLA, R7F100GLL2DLA,
R7F100GLN2DLA
80 pins 80-pin plastic LQFP
C
(14 × 14 mm, 0.65-mm pitch)
R7F100GMG3CFA, R7F100GMH3CFA, R7F100GMJ3CFA, R7F100GMK3CFA, R7F100GML3CFA, R7F100GMN3CFA
#AA0, #BA0 PLQP0080JA-B #HA0
D
R7F100GMG2DFA, R7F100GMH2DFA,
R7F100GMJ2DFA, R7F100GMK2DFA,
R7F100GML2DFA, R7F100GMN2DFA
80 pins 80-pin plastic LFQFP
C
(12 × 12 mm, 0.50-mm pitch)
R7F100GMG3CFB, R7F100GMH3CFB, R7F100GMJ3CFB, R7F100GMK3CFB, R7F100GML3CFB, R7F100GMN3CFB
#AA0, #BA0 PLQP0080KB-B #HA0
D
R7F100GMG2DFB, R7F100GMH2DFB,
R7F100GMJ2DFB, R7F100GMK2DFB,
R7F100GML2DFB, R7F100GMN2DFB
100 pins 100-pin plastic LFQFP
C
(14 × 14 mm, 0.50-mm pitch)
R7F100GPG3CFB, R7F100GPH3CFB, R7F100GPJ3CFB, R7F100GPK3CFB, R7F100GPL3CFB, R7F100GPN3CFB
#AA0, #BA0 PLQP0100KB-B #HA0
D
R7F100GPG2DFB, R7F100GPH2DFB,
R7F100GPJ2DFB, R7F100GPK2DFB,
R7F100GPL2DFB, R7F100GPN2DFB
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RL78/G23
CHAPTER 1 OUTLINE
<R> <R>
Table 1 - 1 List of Ordering Part Numbers (3/3)
Pin count
Package
100 pins 100-pin plastic LQFP (14 × 20 mm, 0.65-mm pitch)
Fields of Application
Note 1
Ordering Part Number Product Name
C
R7F100GPG3CFA, R7F100GPH3CFA,
R7F100GPJ3CFA, R7F100GPK3CFA,
R7F100GPL3CFA, R7F100GPN3CFA
Packaging Renesas Code Specification
#AA0, #BA0 PLQP0100JC-A #HA0
D
R7F100GPG2DFA, R7F100GPH2DFA,
R7F100GPJ2DFA, R7F100GPK2DFA,
R7F100GPL2DFA, R7F100GPN2DFA
128 pins 128-pin plastic LFQFP
C
(14 × 20 mm, 0.50-mm pitch)
R7F100GSJ3CFB, R7F100GSK3CFB, R7F100GSL3CFB, R7F100GSN3CFB
#AA0, #BA0 PLQP0128KD-A #HA0
Note 1.
D
R7F100GSJ2DFB, R7F100GSK2DFB,
R7F100GSL2DFB, R7F100GSN2DFB
For the fields of application, see Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G23.
Note 2. Note 3.
The 36-pin plastic WFLGA products are in planning. Contact a Renesas Electronics sales office for details. The 64-pin plastic WFLGA products are in planning. Contact a Renesas Electronics sales office for details.
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RL78/G23
1.3
Pin Configuration (Top View)
1.3.1 30-pin products
· 30-pin plastic LSSOP (7.62 mm (300), 0.65-mm pitch)
CHAPTER 1 OUTLINE
P20/ ANI0/ AVREFP/EI20
1
P01 /ANI16 /TS 27 Note/EI01 /EO 01 /TO00 /RxD1
2
P00/ ANI17/TS26Note/EI 00/TI00/TxD1
3
P120 /ANI19/IVCMP1/EI120
4
P40/TOOL0
5
RESET
6
P137 / EI137 / INTP0
7
P122/X2/EXCLK /XT2/EXCLKS/EI122
8
P121 / X1/ XT1/EI 121
9
REGC
10
V SS
11
VD D
12
P 60 /EO60 / CCD04 /SCLA 0
13
P61 /EO 61/ CCD05 /SDAA 0
14
P31/TS01/EI31/TI03/TO03/INTP4/PCLBUZ 0
15
RL78/G23 (Top View)
30
P21/ ANI1/ AVREFM /EI21
29
P22/ ANI2/ ANO0/ TS20Note/EI 22
28
P23/ ANI3/ ANO1/ IVREF0/TS21Note/EI 23
27
P 147 /ANI18 / IVCMP0/ EI147
26
P 10/ EI10 /EO 10 /SCK 00/ SCL00 /(TI07 )/(TO07 )
25
P 11/ EI11 /EO 11 /SI 00 /RxD0 /TOOLRxD/ SDA00 /(TI06 )/(TO06 )
24
P12/EI12/EO12/SO00/TxD0/TOOLTxD /(TI05)/(TO05)
23
P 13/ IVREF1 /EO13 / TxD2 /SO 20/(SDAA 0 )/(TI04 )/(TO04 )
22
P 14/ VCOUT1/EO 14 /RxD2/SI 20 /SDA20 /(SCLA 0 )/(TI03 )/(TO03 )
21
P15/EO15/PCLBUZ 1/SCK20/SCL20/(TI02)/(TO02)
20
P 16/ EO16 /CCD00 /TI01 /TO01 /INTP 5/(RxD0 )
19
P 17/ EO17 /CCD01 /TI02 /TO02 /(TxD0)
18
P 51/ EI51 /EO 51 /CCD02 / INTP2/SO 11
17
P 50/ TS00 /EI 50/ EO50 /CCD03 /INTP1 /SI11 /SDA 11
16
P 30/ VCOUT0/TS CAP/EI 30 /INTP3 /RTC1 HZ/ SCK11 /SCL 11
Note
Not present in products with 128 or fewer Kbytes of code flash memory.
Caution Connect the REGC pin to VSS via a capacitor (0.47 to 1 µF).
Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR).
Refer to Figure 4 - 10 Format of Peripheral I/O Redirection Register (PIOR).
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RL78/G23
1.3.2 32-pin products
· 32-pin plastic HWQFN (5 × 5 mm, 0.50-mm pitch) · 32-pin plastic LQFP (7 × 7 mm, 0.80-mm pitch)
CHAPTER 1 OUTLINE
P10/EI10/EO10/SCK00/SCL00/(TI07)/(TO07) P11/EI11/EO11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/EI12/EO12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/IVREF1/EO13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/VCOUT1/EO14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/EO15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/EO16/CCD00/TI01/TO01/INTP5/(RxD0) P17/EO17/CCD01/TI02/TO02/(TxD0)
P147/ANI18/IVCMP0/EI147 P23/ANI3/ANO1/IVREF0/TS21Note 1/EI23
P22/ANI2/ANO0/TS20Note 1/EI22
P21/ANI1/AVREFM/EI21
P20/ANI0/AVREFP/EI20 P01/ANI16/TS27Note 1/EI01/EO01/TO00/RxD1
P00/ANI17/TS26Note 1/EI00/TI00/TxD1
P120/ANI19/IVCMP1/EI120
24 23 22 21 2019 18 17
25
16
26
15
27
14
28 RL78/G23 13
29 (Top View) 12
30
11
31
10
32
9
12 3 4 5 6 78
Exposed die padNote 2
P51/EI51/EO51/CCD02/INTP2/SO11 P50/TS00/EI50/EO50/CCD03/INTP1/SI11/SDA11 P30/VCOUT0/TSCAP/EI30/INTP3/RTC1HZ/SCK11/SCL11 P70/RIN0/TS02 P31/TS01/EI31/TI03/TO03/INTP4/PCLBUZ0 P62/CCD06 P61/EO61/CCD05/SDAA0 P60/EO60/CCD04/SCLA0
INDEX MARK
P40/TOOL0 RESET
P137/EI137/INTP0 P122/X2/EXCLK/XT2/EXCLKS/EI122
P121/X1/XT1/EI121 REGC VSS VDD
Note 1. Note 2.
Not present in products with 128 or fewer Kbytes of code flash memory. The 32-pin plastic LQFP (7 × 7 mm, 0.80-mm pitch) products do not have an exposed die pad.
Caution Connect the REGC pin to VSS via a capacitor (0.47 to 1 µF).
Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR).
Refer to Figure 4 - 10 Format of Peripheral I/O Redirection Register (PIOR). Remark 3. It is recommended to connect an exposed die pad to VSS.
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RL78/G23
1.3.3 36-pin products
· 36-pin plastic WFLGA (4 × 4 mm, 0.50-mm pitch)
Top View
6
5
RL78/G23
4
(Top View)
3
2
1
ABC DEF
INDE X MARK
Bottom View FEDCBA
CHAPTER 1 OUTLINE
A
B
C
D
E
F
6 P60/EO60/CCD04/
VDD
SCLA0
P121/X1/XT1/EI121
P122/X2/EXCLK/XT2/ P137/EI137/INTP0 EXCLKS/EI122
P40/TOOL0
5 P62/CCD06
P61/EO61/CCD05/SD VSS AA0
REGC
RESET
P120/ANI19/IVCMP1/ EI120
4 P72/TS04/SO21/ TxDA0
P71/TS03/SI21/ SDA21/RxDA0
P14/VCOUT1/EO14/
RxD2/SI20/SDA20/ (SCLA0)/(TI03)/ (TO03)
P31/TS01/EI31/TI03/ TO03/INTP4/ PCLBUZ0
P00/TS26Note/EI00/ TI00/TxD1
P01/TS27Note/EI01/ EO01/TO00/RxD1
3 P50/TS00/EI50/EO50/ P70/TS02/RIN0/ CCD03/INTP1/SI11/ SCK21/SCL21 SDA11
P15/EO15/PCLBUZ1/ SCK20/SCL20/ (TI02)/(TO02)
P22/ANI2/ANO0/ TS20Note/EI22
P20/ANI0/AVREFP/
EI20
P21/ANI1/AVREFM/
EI21
2 P30/VCOUT0/TSCAP/ P16/EO16/CCD00/
EI30/INTP3/RTC1HZ/ TI01/TO01/INTP5/
SCK11/SCL11
(RxD0)
P12/EI12/EO12/SO00/ P11/EI11/EO11/SI00/
TxD0/TOOLTxD/
RxD0/TOOLRxD/
(TI05)/(TO05)
SDA00/(TI06)/(TO06)
P24/ANI4/TS22Note
P23/ANI3/ANO1/ IVREF0/TS21Note/ EI23
1 P51/EI51/EO51/ CCD02/INTP2/ SO11
P17/EO17/CCD01/ TI02/TO02/(TxD0)
P13/IVREF1/EO13/ TxD2/SO20/(SDAA0)/ (TI04)/(TO04)
P10/EI10/EO10/ SCK00/SCL00/ (TI07)/(TO07)
P147/ANI18/IVCMP0/ P25/ANI5/TS23Note EI147
Note
Not present in products with 128 or fewer Kbytes of code flash memory.
Caution Connect the REGC pin to VSS via a capacitor (0.47 to 1 µF).
Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR).
Refer to Figure 4 - 10 Format of Peripheral I/O Redirection Register (PIOR).
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RL78/G23
1.3.4 40-pin products
· 40-pin plastic HWQFN (6 × 6 mm, 0.50-mm pitch)
CHAPTER 1 OUTLINE
P147/ANI 18/IVCMP0/EI147 P 10/EI10/ EO10/S CK 00/SCL00/(TI07)/(TO07) P11/EI11/ EO11/SI00/RxD0/TOOLRxD/ SDA00/(TI06)/(TO 06) P12/EI12/ EO12/SO00/TxD0/TOO LTxD/(TI 05)/(TO05) P13/IVREF1/EO 13/TxD2/SO 20/(SDAA0)/ (TI04)/(TO04) P14/VCOUT1/ EO14/RxD2/SI20/SDA20/(SCLA0)/ (TI03)/(TO03) P15/EO15/PCLBUZ1/SCK20/SCL20/(TI02)/ (TO02) P16/EO16/CCD00/TI01/TO01/I NTP5/(RxD0) P 17 /EO1 7/ CCD01 /TI0 2/TO0 2/( TxD0) P51/EI51/ EO51/CCD02/ INTP2/ SO11
P 26 /ANI6 /TS24 N ote P 25 /ANI5 /TS23 N ote P 24 /ANI4 /TS22 N ote P23/ANI3/ANO1/IVREF 0/TS21Note/EI23 P22/ANI 2/ANO 0/TS20Note/ EI22
P21/ANI 1/AVREFM/ EI21
P20/ANI 0/AVREFP/ EI20 P01/TS27Note/EI 01/EO 01/TO00/RxD1
P00/ TS26Note/EI 00/ TI00/TxD1
P120 / ANI19 /IVCMP1 /EI 120
30 29 28 27 26 25 24 23 22 21
31
20
32 Exposed die pad
19
33
18
34 RL78/G23 17
35
16
36 (Top View) 15
37
14
38
13
39
12
40 1 2 3 4 5 6 7 8 9 1011
P50 /TS00 /EI 50 /EO 50 /CCD03 /INTP1 /SI 11 /SDA11 P30 /VCOUT0 /TSCAP/ EI30 /INTP 3/RTC1HZ/SCK11 / SCL11 P70 /TS02 /RIN0 /KR0/ SCK21 /SCL 21 KR0/ SCK21 /SCL 21 P71/TS03/KR 1/SI21/SDA21/RxDA0 P72/TS04/KR 2/SO21/TxDA0
P73/TS05/KR 3 P31/TS01/EI31/TI03/TO03/INTP4/PCLBUZ 0 P62/CCD06
P61 /EO 61 /CCD05 /SDAA 0 P60 /EO 60 /CCD04 /SCLA 0
INDEX MARK
P40/TOO L0 RESE T
P1 24 /XT2 /EX CL KS P1 23 /XT1
P137/ EI137/INTP0 P122/X2/EXCLK/ EI122
P121/X1/VBAT/ EI121 REG C V SS VD D
Note
Not present in products with 128 or fewer Kbytes of code flash memory.
Caution Connect the REGC pin to VSS via a capacitor (0.47 to 1 µF).
Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR).
Refer to Figure 4 - 10 Format of Peripheral I/O Redirection Register (PIOR). Remark 3. It is recommended to connect an exposed die pad to VSS.
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 12 of 1478
RL78/G23
1.3.5 44-pin products
· 44-pin plastic LQFP (10 × 10 mm, 0.80-mm pitch)
CHAPTER 1 OUTLINE
P147/ANI18/IVCMP0/EI147 P146 P10/EI10/EO10/SCK00/SCL00/(TI07)/(TO07) P11/EI11/EO11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/EI12/EO12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/IVREF1/EO13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/VCOUT1/EO14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/EO15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/EO16/CCD00/TI01/TO01/INTP5/(RxD0) P17/EO17/CCD01/TI02/TO02/(TxD0) P51/EI51/EO51/CCD02/INTP2/SO11
P27/ANI7/TS25Note P26/ANI6/TS24Note P25/ANI5/TS23Note P24/ANI4/TS22Note P23/ANI3/ANO1/IVREF0/TS21Note/EI23 P22/ANI2/ANO0/TS20Note/EI22
P21/ANI1/AVREFM/EI21
P20/ANI0/AVREFP/EI20 P01/TS27Note/EI01/EO01/TO00/RxD1
P00/TS26Note/EI00/TI00/TxD1
P120/ANI19/IVCMP1/TxDA1/EI120
33 32 31 30 29 28 27 26 25 24 23
34
22
35
21
36
20
37
19
38
RL78/G23
18
39 40
(Top View)
17 16
41
15
42
14
43
13
44
12
1 2 3 4 5 6 7 8 9 10 11
P50/TS00/EI50/EO50/CCD03/INTP1/SI11/SDA11 P30/VCOUT0/TSCAP/EI30/INTP3/RTC1HZ/SCK11/SCL11 P70/TS02/RIN0/KR0/SCK21/SCL21 P71/TS03/KR1/SI21/SDA21/RxDA0 P72/TS04/KR2/SO21/TxDA0 P73/TS05/KR3 P31/TS01/EI31/TI03/TO03/INTP4/PCLBUZ0 P63/CCD07/SDAA1 P62/CCD06/SCLA1 P61/EO61/CCD05/SDAA0 P60/EO60/CCD04/SCLA0
P41/RxDA1/TI07/TO07 P40/TOOL0 RESET
P124/XT2/EXCLKS P123/XT1
P137/EI137/INTP0 P122/X2/EXCLK/EI122
P121/X1/VBAT/EI121 REGC VSS VDD
Note
Not present in products with 128 or fewer Kbytes of code flash memory.
Caution Connect the REGC pin to VSS via a capacitor (0.47 to 1 µF).
Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR).
Refer to Figure 4 - 10 Format of Peripheral I/O Redirection Register (PIOR).
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 13 of 1478
RL78/G23
1.3.6 48-pin products
· 48-pin plastic LFQFP (7 × 7 mm, 0.50-mm pitch) · 48-pin plastic HWQFN (7 × 7 mm, 0.50-mm pitch)
CHAPTER 1 OUTLINE
P140/PCLBUZ0/INTP6 P00/TS26Note 1/EI00/TI00/TxD1 P01/TS27Note 1/EI01/EO01/TO00/RxD1 P130 P20/ANI0/AVREFP/EI20 P21/ANI1/AVREFM/EI21 P22/ANI2/ANO0/TS20Note 1/EI22 P23/ANI3/ANO1/IVREF0/TS21Note 1/EI23 P24/ANI4/TS22Note 1 P25/ANI5/TS23Note 1 P26/ANI6/TS24Note 1 P27/ANI7/TS25Note 1
P120/ANI19/IVCMP1/TxDA1/EI120 P41/RxDA1/TI07/TO07 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/EI137/INTP0 P122/X2/EXCLK/EI122 P121/X1/VBAT/EI121 REGC VSS VDD
36 35 34 33 32 31 30 29 28 27 26 25
37
24
38
23
39
22
40
21
41 42
RL78/G23
20 19
43
(Top View)
18
44
17
45
16
46
15
47
14
48
13
1 2 3 4 5 6 7 8 9 10 11 12
Exposed die padNote 2
P147/ANI18/IVCMP0/EI147 P146 P10/EI10/EO10/SCK00/SCL00/(TI07)/(TO07) P11/EI11/EO11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/EI12/EO12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/IVREF1/EO13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/VCOUT1/EO14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/EO15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/EO16/CCD00/TI01/TO01/INTP5/(RxD0) P17/EO17/CCD01/TI02/TO02/(TxD0) P51/EI51/EO51/CCD02/INTP2/SO11 P50/TS00/EI50/EO50/CCD03/INTP1/SI11/SDA11
P60/EO60/CCD04/SCLA0 P61/EO61/CCD05/SDAA0
P62/CCD06/SCLA1 P63/CCD07/SDAA1 P31/TS01/EI31/TI03/TO03/INTP4/(PCLBUZ0) P75/TS07/KR5/INTP9/SCK01/SCL01 P74/TS06/KR4/INTP8/SI01/SDA01 P73/TS05/KR3/SO01 P72/TS04/KR2/SO21/TxDA0 P71/TS03/KR1/SI21/SDA21/RxDA0 P70/TS02/RIN0/KR0/SCK21/SCL21 P30/VCOUT0/TSCAP/EI30/INTP3/RTC1HZ/SCK11/SCL11
Note 1. Note 2.
Not present in products with 128 or fewer Kbytes of code flash memory. The 32-pin plastic LQFP (7 × 7 mm, 0.80-mm pitch) products do not have an exposed die pad.
Caution Connect the REGC pin to VSS via a capacitor (0.47 to 1 µF).
Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR).
Refer to Figure 4 - 10 Format of Peripheral I/O Redirection Register (PIOR).
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 14 of 1478
RL78/G23
1.3.7 52-pin products
· 52-pin plastic LQFP (10 × 10 mm, 0.65-mm pitch)
CHAPTER 1 OUTLINE
P147/ANI18/IVCMP0/EI147 P146 P10/EI10/EO10/SCK00/SCL00/(TI07)/(TO07) P11/EI11/EO11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/EI12/EO12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/IVREF1/EO13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/VCOUT1/EO14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/EO15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/EO16/CCD00/TI01/TO01/INTP5/(RxD0) P17/EO17/CCD01/TI02/TO02/(TxD0) P51/EI51/EO51/CCD02/INTP2/SO11 P50/TS00/EI50/EO50/CCD03/INTP1/SI11/SDA11 P30/VCOUT0/TSCAP/EI30/INTP3/RTC1HZ/SCK11/SCL11
P27/ANI7/TS25Note P26/ANI6/TS24Note P25/ANI5/TS23Note P24/ANI4/TS22Note P23/ANI3/ANO1/IVREF0/TS21Note/EI23 P22/ANI2/ANO0/TS20Note/EI22
P21/ANI1/AVREFM/EI21
P20/ANI0/AVREFP/EI20
P130 P03/ANI16/TS29Note/RxD1 P02/ANI17/TS28Note/TxD1 P01/TS27Note/EI01/EO01/TO00
P00/TS26Note/EI00/TI00
39 38 37 36 35 34 33 32 31 30 29 28 27
40
26
41
25
42
24
43
23
44
22
45
RL78/G23
21
46
20
47
(Top View)
19
48
18
49
17
50
16
51
15
52
14
1 2 3 4 5 6 7 8 9 10 11 12 13
P70/TS02/RIN0/KR0/SCK21/SCL21 P71/TS03/KR1/SI21/SDA21/RxDA0 P72/TS04/KR2/SO21/TxDA0 P73/TS05/KR3/SO01 P74/TS06/KR4/INTP8/SI01/SDA01 P75/TS07/KR5/INTP9/SCK01/SCL01 P76/TS08/KR6/INTP10/(RxD2) P77/TS09/KR7/INTP11/(TxD2) P31/TS01/EI31/TI03/TO03/INTP4/(PCLBUZ0) P63/CCD07/SDAA1 P62/CCD06/SCLA1 P61/EO61/CCD05/SDAA0 P60/EO60/CCD04/SCLA0
P140/PCLBUZ0/INTP6 P120/ANI19/IVCMP1/TxDA1/EI120
P41/RxDA1/TI07/TO07 P40/TOOL0 RESET
P124/XT2/EXCLKS P123/XT1
P137/EI137/INTP0 P122/X2/EXCLK/EI122
P121/X1/VBAT/EI121 REGC VSS VDD
Note
Not present in products with 128 or fewer Kbytes of code flash memory.
Caution Connect the REGC pin to VSS via a capacitor (0.47 to 1 µF).
Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR).
Refer to Figure 4 - 10 Format of Peripheral I/O Redirection Register (PIOR).
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 15 of 1478
RL78/G23
1.3.8 64-pin products
· 64-pin plastic LQFP (12 × 12 mm, 0.65-mm pitch) · 64-pin plastic LFQFP (10 × 10 mm, 0.50-mm pitch)
CHAPTER 1 OUTLINE
P147/ANI18/IVCMP0/EI147 P146 P10/EI10/EO10/SCK00/SCL00/(TI07)/(TO07) P11/EI11/EO11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/EI12/EO12/SO00/TxD0/TOOLTxD/(INTP5)/(TI05)/(TO05) P13/IVREF1/EO13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/VCOUT1/EO14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/EO15/SCK20/SCL20/(TI02)/(TO02) P16/EO16/CCD00/TI01/TO01/INTP5/(SI00)/(RxD0) P17/EO17/CCD01/TI02/TO02/(SO00)/(TxD0) P55/(PCLBUZ1)/(SCK00) P54 P53/(INTP11) P52/(INTP10) P51/EI51/EO51/CCD02/INTP2/SO11 P50/TS00/EI50/EO50/CCD03/INTP1/SI11/SDA11
P27/ANI7/TS25Note P26/ANI6/TS24Note P25/ANI5/TS23Note P24/ANI4/TS22Note P23/ANI3/ANO1/IVREF0/TS21Note/EI23 P22/ANI2/ANO0/TS20Note/EI22
P21/ANI1/AVREFM/EI21 P20/ANI0/AVREFP/EI20
P130
P04/SCK10/SCL10 P03/ANI16/TS29Note/SI10/RxD1/SDA10
P02/ANI17/TS28Note/SO10/TxD1 P01/TS27Note/EI01/EO01/TO00 P00/TS26Note/EI00/TI00
P141/PCLBUZ1/INTP7
P140/PCLBUZ0/INTP6
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
1 2 3
32
31
30
29
28
27
RL78/G23
26
25
(Top View)
24
23
22
21
20
19
18
17 4 5 6 7 8 9 10 11 12 13 14 15 16
P30/VCOUT0/TSCAP/EI30/INTP3/RTC1HZ/SCK11/SCL11 P05/TS10/TI05/TO05 P06/TS11/TI06/TO06/CLKA0 P70/TS02/RIN0/KR0/SCK21/SCL21 P71/TS03/KR1/SI21/SDA21/RxDA0 P72/TS04/KR2/SO21/TxDA0 P73/TS05/KR3/SO01 P74/TS06/KR4/INTP8/SI01/SDA01 P75/TS07/KR5/INTP9/SCK01/SCL01 P76/TS08/KR6/INTP10/(RxD2) P77/TS09/KR7/INTP11/(TxD2) P31/TS01/EI31/TI03/TO03/INTP4/(PCLBUZ0) P63/CCD07/SDAA1 P62/CCD06/SCLA1 P61/EO61/CCD05/SDAA0 P60/EO60/CCD04/SCLA0
P120/ANI19/IVCMP1/EI120 P43/CLKA1
P42/TxDA1/TI04/TO04 P41/RxDA1/TI07/TO07
P40/TOOL0 RESET
P124/XT2/EXCLKS P123/XT1
P137/EI137/INTP0 P122/X2/EXCLK/EI122
P121/X1/VBAT/EI121 REGC VSS EVSS0 VDD EVDD0
Note
Not present in products with 128 or fewer Kbytes of code flash memory.
Caution 1. Connect the EVSS0 pin to the same ground as the VSS pin. Caution 2. Make sure that the voltage on the VDD pin is no less than that on the EVDD0 pin. Caution 3. Connect the REGC pin to VSS via a capacitor (0.47 to 1 µF).
Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it
is recommended to supply separate powers to the VDD and EVDD0 pins and connect the VSS and EVSS0 pins to separate ground lines. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4 - 10 Format of Peripheral I/O Redirection Register (PIOR).
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 16 of 1478
RL78/G23
CHAPTER 1 OUTLINE
· 64-pin plastic WFLGA (5 × 5 mm, 0.50-mm pitch)
Top View
8
7
6
RL78/G23
5
(Top View)
4
3
2
1
A B CDE F GH
Index mark
Bottom View H G FED CBA
A
B
C
D
E
F
G
H
8 EVDD0
EVSS0
P121/X1/EI121/ P122/X2/EXCLK P137/INTP0/
VBAT
/EI122
EI137
P123/XT1
P124/XT2/ EXCLKS
P120/ANI19/ IVCMP1/EI120
7 P60/CCD04/
VDD
VSS
REGC
RESET
P01/TS27Note/ P00/TS26Note/ P140/PCLBUZ0/
SCLA0/EO60
EI01/EO01/
EI00/TI00
INTP6
TO00
6 P61/CCD05/ SDAA0/EO61
P62/CCD06/ SCLA1
P63/CCD07/ SDAA1
P40/TOOL0
P41/TI07/TO07/ P43/CLKA1 RxDA1
P02/ANI17/ TS28Note/ SO10/TxD1
P141/PCLBUZ1/ INTP7
5 P77/KR7/TS09/ P31/TI03/TO03/ P53/(INTP11) INTP11/(TxD2) INTP4/TS01/ EI31/(PCLBUZ0)
P42/TI04/TO04/ TxDA1
P03/ANI16/ TS29Note/ SI10/RxD1/ SDA10
P04/SCK10/ SCL10
P130
P20/ANI0/ AVREFP/EI20
4 P75/KR5/TS07/ P76/KR6/TS08/ P52/(INTP10) P54 INTP9/SCK01/ INTP10/(RxD2) SCL01
P16/CCD00/ TI01/TO01/ INTP5/EO16/ (SI00)/(RxD0)
P21/ANI1/ AVREFM/EI21
P22/ANI2/ANO0 /EI22/TS20Note
P23/ANI3/ANO1 /IVREF0/EI23/ TS21Note
3 P70/KR0/TS02/ P73/KR3/TS05/ P74/KR4/TS06/ P17/CCD01/
RIN0/SCK21/ SO01
INTP8/SI01/
TI02/TO02/
SCL21
SDA01
EO17/(SO00)/
(TxD0)
P15/SCK20/ SCL20/EO15/ (TI02)/(TO02)
P12/SO00/TxD0 P24/ANI4/ /TOOLTxD/EI12/ TS22Note EO12/(INTP5)/ (TI05)/(TO05)
P26/ANI6/ TS24Note
2 P30/INTP3/ TSCAP/ RTC1HZ/EI30/ VCOUT0/ SCK11/SCL11
P72/KR2/TS04/ SO21/TxDA0
P71/KR1/TS03/ SI21/SDA21/ RxDA0
P06/TS11/TI06/ TO06/CLKA0
P14/RxD2/ SI20/SDA20/ VCOUT1/EO14/ (SCLA0)/(TI03)/ (TO03)
P11/SI00/RxD0/ TOOLRxD/ SDA00/EI11/ EO11/(TI06)/ (TO06)
P25/ANI5/ TS23Note
P27/ANI7/ TS25Note
1 P05/TS10/TI05/ P50/CCD03/
TO05
TS00/EI50/
EO50/INTP1/
SI11/SDA11
P51/CCD02/ EI51/EO51/ INTP2/SO11
P55/(PCLBUZ1)/ P13/TxD2/SO20 P10/SCK00/
(SCK00)
/IVREF1/EO13/ SCL00/EI10/
(SDAA0)/(TI04)/ EO10/(TI07)/
(TO04)
(TO07)
P146
P147/ANI18/ EI147/IVCMP0
Note
Not present in products with 128 or fewer Kbytes of code flash memory.
Caution 1. Connect the EVSS0 pin to the same ground as the VSS pin.
Caution 2. Make sure that the voltage on the VDD pin is no less than that on the EVDD0 pin.
Caution 3. Connect the REGC pin to VSS via a capacitor (0.47 to 1 µF).
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 17 of 1478
RL78/G23
CHAPTER 1 OUTLINE
Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it
is recommended to supply separate powers to the VDD and EVDD0 pins and connect the VSS and EVSS0 pins to separate ground lines. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4 - 10 Format of Peripheral I/O Redirection Register (PIOR).
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 18 of 1478
RL78/G23
1.3.9 80-pin products
· 80-pin plastic LQFP (14 × 14 mm, 0.65-mm pitch) · 80-pin plastic LFQFP (12 × 12 mm, 0.50-mm pitch)
CHAPTER 1 OUTLINE
P153/ANI11/TS33 P100/ANI20 P147/ANI18/EI147/IVCMP0 P146 P111/(INTP11) P110/(INTP10) P10/SCK00/SCL00/EI10/EO10/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/EI11/EO11/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/EI12/EO12/(INTP5)/(TI05)/(TO05) P13/TxD2/SO20/IVREF1/EO13/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/VCOUT1/EO14/(SCLA0)/(TI03)/(TO03) P15/SCK20/SCL20/EO15/(TI02)/(TO02) P16/CCD00/TI01/TO01/INTP5/EO16/(SI00)/(RxD0) P17/CCD01/TI02/TO02/EO17/(SO00)/(TxD0) P55/(PCLBUZ1)/(SCK00) P54/SCK31/SCL31 P53/SI31/SDA31 P52/SO31 P51/CCD02/EI51/EO51/INTP2/SO11 P50/CCD03/TS00/EI50/EO50/INTP1/SI11/SDA11
P152/ANI10/TS32 P151/ANI9/TS31 P150/ANI8/TS30 P27/ANI7/TS25 P26/ANI6/TS24 P25/ANI5/TS23 P24/ANI4/TS22
P23/ANI3/ANO1/IVREF0/EI23/TS21 P22/ANI2/ANO0/EI22/TS20 P21/ANI1/AVREFM/EI21 P20/ANI0/AVREFP/EI20 P130 P04/SCK10/SCL10
P03/ANI16/TS29/SI10/RxD1/SDA10 P02/ANI17/TS28/SO10/TxD1 P01/TS27/EI01/EO01/TO00 P00/TS26/EI00/TI00 P144/SO30/TxD3 P143/SI30/RxD3/SDA30 P142/SCK30/SCL30
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
61
40
62
39
63
38
64
37
65
36
66
35
67
34
68
33
69
32
70
RL78/G23
31
71 72
(Top View)
30 29
73
28
74
27
75
26
76
25
77
24
78
23
79
22
80
21
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
P30/INTP3/TSCAP/RTC1HZ/EI30/VCOUT0/SCK11/SCL11 P05/TS10/TI05/TO05 P06/TS11/TI06/TO06/CLKA0 P70/KR0/TS02/RIN0/SCK21/SCL21 P71/KR1/TS03/SI21/SDA21/RxDA0 P72/KR2/TS04/SO21/TxDA0 P73/KR3/TS05 P74/KR4/TS06/INTP8 P75/KR5/TS07/INTP9 P76/KR6/TS08/INTP10/(RxD2) P77/KR7/TS09/INTP11/(TxD2) P67/TI13/TO13/TS15 P66/TI12/TO12/TS14 P65/TI11/TO11/TS13 P64/TI10/TO10/TS12 P31/TI03/TO03/INTP4/TS01/EI31/(PCLBUZ0) P63/CCD07/SDAA1 P62/CCD06/SCLA1 P61/CCD05/SDAA0/EO61 P60/CCD04/SCLA0/EO60
P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 P120/ANI19/IVCMP1/EI120
P45/SO01 P44/SI01/SDA01 P43/SCK01/SCL01/CLKA1 P42/TI04/TO04/TxDA1 P41/TI07/TO07/RxDA1
P40/TOOL0 RESET
P124/XT2/EXCLKS P123/XT1
P137/INTP0/EI137 P122/X2/EXCLK/EI122
P121/X1/EI121/VBAT REGC VSS EVSS0 VDD EVDD0
Caution 1. Connect the EVSS0 pin to the same ground as the VSS pin. Caution 2. Make sure that the voltage on the VDD pin is no less than that on the EVDD0 pin. Caution 3. Connect the REGC pin to VSS via a capacitor (0.47 to 1 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced,
it is recommended to supply separate powers to the VDD and EVDD0 pins and connect the VSS and EVSS0 pins to separate ground lines. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4 - 10 Format of Peripheral I/O Redirection Register (PIOR).
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 19 of 1478
RL78/G23
1.3.10 100-pin products
· 100-pin plastic LFQFP (14 × 14 mm, 0.50-mm pitch)
CHAPTER 1 OUTLINE
P100/ANI20 P147/ANI18/EI147/IVCMP0 P146/(INTP4) P111/(INTP11) P110/(INTP10) P101 P10/SCK00/SCL00/EI10/EO10/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/EI11/EO11/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/EI12/EO12/(INTP5)/(TI05)/(TO05) P13/TxD2/SO20/IVREF1/EO13/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/VCOUT1/EO14/(SCLA0)/(TI03)/(TO03) P15/SCK20/SCL20/EO15/(TI02)/(TO02) P16/CCD00/TI01/TO01/INTP5/EO16/(SI00)/(RxD0) P17/CCD01/TI02/TO02/EO17/(SO00)/(TxD0) P57/(INTP3) P56/(INTP1) P55/(PCLBUZ1)/(SCK00) P54/SCK31/SCL31 P53/SI31/SDA31 P52/SO31 P51/CCD02/EI51/EO51/SO11 P50/CCD03/TS00/EI50/EO50/SI11/SDA11 EVDD1 P30/INTP3/TSCAP/RTC1HZ/EI30/VCOUT0/SCK11/SCL11 P87/(INTP9)
P156/ANI14 P155/ANI13/TS35 P154/ANI12/TS34 P153/ANI11/TS33 P152/ANI10/TS32
P151/ANI9/TS31 P150/ANI8/TS30
P27/ANI7/TS25 P26/ANI6/TS24 P25/ANI5/TS23 P24/ANI4/TS22 P23/ANI3/ANO1/IVREF0/EI23/TS21 P22/ANI2/ANO0/EI22/TS20 P21/ANI1/AVREFM/EI21 P20/ANI0/AVREFP/EI20
P130 P102/TI06/TO06 P04/SCK10/SCL10 P03/ANI16/TS29/SI10/RxD1/SDA10 P02/ANI17/TS28/SO10/TxD1 P01/TS27/EI01/EO01/TO00 P00/TS26/EI00/TI00 P145/TI07/TO07 P144/SO30/TxD3 P143/SI30/RxD3/SDA30
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
50
77
49
78
48
79
47
80
46
81
45
82
44
83
43
84
42
85
41
86
40
87
RL78/G23
39
88
38
89
(Top View)
37
90
36
91
35
92
34
93
33
94
32
95
31
96
30
97
29
98
28
99
27
100
26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
P86/(INTP8) P85/(INTP7)/CLKA0 P84/(INTP6)/RxDA0 P83/TxDA0 P82/(SO10)/(TxD1) P81/(SI10)/(RxD1)/(SDA10) P80/(SCK10)/(SCL10) EVSS1 P05/TS10 P06/TS11 P70/KR0/TS02/RIN0/SCK21/SCL21 P71/KR1/TS03/SI21/SDA21 P72/KR2/TS04/SO21 P73/KR3/TS05 P74/KR4/TS06/INTP8 P75/KR5/TS07/INTP9 P76/KR6/TS08/INTP10/(RxD2) P77/KR7/TS09/INTP11/(TxD2) P67/TI13/TO13/TS15 P66/TI12/TO12/TS14 P65/TI11/TO11/TS13 P64/TI10/TO10/TS12 P31/TI03/TO03/INTP4/TS01/EI31/(PCLBUZ0) P63/CCD07/SDAA1 P62/CCD06/SCLA1
P142/SCK30/SCL30 P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 P120/ANI19/IVCMP1/EI120
P47/INTP2 P46/INTP1/TI05/TO05
P45/SO01 P44/SI01/SDA01 P43/SCK01/SCL01/CLKA1 P42/TI04/TO04/TxDA1
P41/RxDA1 P40/TOOL0
RESET P124/XT2/EXCLKS
P123/XT1 P137/INTP0/EI137 P122/X2/EXCLK/EI122 P121/X1/EI121/VBAT
REGC VSS
EVSS0 VDD
EVDD0 P60/CCD04/SCLA0/EO60 P61/CCD05/SDAA0/EO61
Caution 1. Connect the EVSS0 and EVSS1 pins to the same ground as the VSS pin. Caution 2. Make sure that the voltage on the VDD pin is no less than that on the EVDD0 and EVDD1 pins. Also make sure that
the voltage on the EVDD0 is the same as that on the EVDD1 pin. Caution 3. Connect the REGC pin to VSS via a capacitor (0.47 to 1 µF). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it
is recommended to supply separate powers to the VDD, EVDD0, and EVDD1 pins and connect the VSS, EVSS0, and EVSS1 pins to separate ground lines. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4 - 10 Format of Peripheral I/O Redirection Register (PIOR).
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 20 of 1478
RL78/G23 · 100-pin plastic LQFP (14 × 20 mm, 0.65-mm pitch)
CHAPTER 1 OUTLINE
P1 40 /PCLB UZ0 /INTP6 P1 41 /PCLB UZ1 /INTP7 P1 42 /SCK3 0/S CL30 P1 43 /SI3 0/ RxD3 /SDA3 0 P1 44 /SO3 0/ TxD3 P145/TI07/TO07 P0 0/TS 26 /EI0 0/TI 00 P0 1/TS 27 /EI0 1/E O01 /TO0 0 P0 2/A NI17 /TS2 8/S O10 /TxD1 P0 3/A NI16 /TS2 9/S I10 /RxD1 /SDA 10 P0 4/S CK10 /SCL 10 P102/TI06/TO06 P130 P20/ANI0/AVREFP/ EI20 P2 1/A NI1/A VREFM/ EI2 1 P2 2/A NI2/A NO0/E I22 /TS2 0 P2 3/A NI3/A NO1/I VREF0/ EI2 3/TS 21 P2 4/A NI4/TS 22 P2 5/A NI5/TS 23 P2 6/A NI6/TS 24 P2 7/A NI7/TS 25 P150/ANI8/TS30 P151/ANI9/TS31 P152/ANI10/TS32 P153/ANI11/TS33 P154/ANI12/TS34 P155/ANI13/TS35 P156/ANI14 P100/ANI20 P1 47 /ANI1 8/E I14 7/I VCMP 0
P120 /ANI 19 /IVCMP1 /EI120
P47 /INTP2 P46/ INTP1/TI05/TO05
P45 /SO 01 P 44 /SI01 /SDA 01
P43 /SCK 01 /SCL01 /CLKA 1 P 42 /TI04 /TO04 /TxDA1 P41 /RxDA1 P40 / TOOL0
RESET P124/XT 2/EXCLKS
P 123 /XT1
P137 /INTP0/EI137 P122/X2/EXCLK /EI122
P121 /X1/EI121 /VBAT REGC
VSS EVSS 0
V DD EVDD0
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81
50
82
49
83
48
84
47
85
46
86
45
87
44
88
43
89 90
RL78/G23
42 41
91
(Top View)
40
92
39
93
38
94
37
95
36
96
35
97
34
98
33
99
32
100
31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 1516 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P 146 /( INTP4 ) P 111 /( INTP11 ) P 110 /( INTP10 )
P 101 P 10 /SCK00 /SCL 00 /EI 10/ EO10 /(TI07 )/(TO07 ) P 11 /SI00 /RxD0/ TOOLRxD/SDA 00 /EI11 /EO 11 /(TI06 )/(TO06 ) P 12 /SO00 /TxD0 /TOOLTxD/EI 12 /EO 12 /(INTP 5)/(TI05 )/(TO05 )
P 13 /TxD2 /SO 20 /IVREF1 /EO 13/(SDAA 0 )/(TI04 )/(TO04 ) P14/RxD2/SI 20/SDA20/VCOUT1/EO14/(SCLA0)/(TI03)/(TO03) P 15 /SCK20 /SCL 20 /EO 15/( TI02 )/(TO02 ) P 16 /CCD00 /TI01 /TO 01/ INTP5/ EO16 /(SI00 )/(RxD0 ) P 17 /CCD01 /TI02 /TO 02/ EO17 /(SO 00)/(TxD0)
P 57 /(INTP 3) P 56 /(INTP 1) P55/(PCLBUZ 1)/(SCK00) P 54 /SCK31 /SCL 31
P 53 /SI31 /SDA 31 P 52 /SO31 P 51 /CCD02 /EI 51 /EO51 / SO11 P 50 /CCD03 /TS00 / EI50 /EO 50 /SI11 / SDA11
P 60/ CCD04 /SCL A0/ EO6 0 P 61 /CCD0 5/S DA A0/ EO6 1
P62/CCD06/SCLA1 P63/CCD07/SDAA1 P3 1/TI 03/ TO03 /INTP4 /TS01 /EI 31 /(P CLBUZ0) P6 4/ TI 10 /TO10 /TS1 2 P6 5/ TI 11 /TO11 /TS1 3 P6 6/ TI 12 /TO12 /TS1 4 P6 7/ TI 13 /TO13 /TS1 5 P7 7/K R7 /TS0 9/I NTP 11/ (TxD2) P7 6/K R6 /TS0 8/I NTP 10 /(RxD2) P7 5/K R5 /TS0 7/I NTP 9 P7 4/K R4 /TS0 6/I NTP 8
P73/KR3/TS05 P7 2/ KR2/TS 04/ SO2 1 P71 /KR1 /TS03 /SI 21 /SDA2 1 P7 0/ KR0/TS 02/ RI N0 /SCK 21/ SCL2 1
P06/TS11 P05/TS10
EV SS1 P8 0/( SCK 10) /( SCL 10) P 81 /( SI1 0) /( RxD1 )/( SDA 10)
P 82/ (S O10 )/ (TxD1) P 83/ TxDA 0
P8 4/ (INTP6 )/RxDA 0 P8 5/ (INTP7 )/CLKA 0
P86/(INTP8) P87/(INTP9) P3 0/INTP3 /TSCAP /RTC1 HZ/EI3 0/V COUT0 /SCK 11/ SCL1 1
E VD D1
Caution 1. Connect the EVSS0 and EVSS1 pins to the same ground as the VSS pin. Caution 2. Make sure that the voltage on the VDD pin is no less than that on the EVDD0 and EVDD1 pins. Also make sure that
the voltage on the EVDD0 is the same as that on the EVDD1 pin. Caution 3. Connect the REGC pin to VSS via a capacitor (0.47 to 1 µF).
Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it
is recommended to supply separate powers to the VDD, EVDD0, and EVDD1 pins and connect the VSS, EVSS0, and EVSS1 pins to separate ground lines. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4 - 10 Format of Peripheral I/O Redirection Register (PIOR).
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 21 of 1478
RL78/G23
1.3.11 128-pin products
· 128-pin plastic LFQFP (14 × 20 mm, 0.50-mm pitch)
CHAPTER 1 OUTLINE
P 10 0/A NI 20 P 14 7/A NI 18 /EI1 47 /IVCM P0 P 14 6/(INTP4 ) P 11 1/(INTP1 1) P 11 0/(INTP1 0) P 10 1 P 11 7/A NI 24 P 11 6/A NI 25 P 11 5/A NI 26 P 11 4 P 11 3 P 11 2 P 97 /SO1 1 P 96 /SI1 1/ SDA11 P 95 /SCK1 1/S CL11 P 94 P 93 P 92 P 91 P 90 P 10 /SCK0 0/S CL00 /EI 10 /EO1 0/(TI0 7)/( TO07 ) P 11 /SI0 0/ RxD0 /TOOL RxD/S DA 00 /EI1 1/ EO1 1/(TI06 )/(TO 06 ) P12/SO00/TxD0/TOOLTxD/ EI12/EO12/(INTP5)/(TI05)/ (TO05) P13/TxD2/SO20/IVREF1/EO 13/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI 20/SDA20/VCO UT1/EO 14/(SCLA0)/(TI03)/(TO03) P 15 /SCK2 0/S CL20 /EO 15 /(TI 02)/(TO0 2) P16/CCD00/TI01/TO 01/INTP5/EO16/(SI00)/(RxD0) P17/CCD01/TI02/TO 02/EO17/(SO00)/(TxD0) P 57 /( INTP 3) P 56 /( INTP 1) P 55 /( PCLBUZ1 )/(SCK 00) P 54 /SCK3 1/S CL31 P 53 /SI3 1/ SDA31 P 52 /SO3 1 P51/CCD02/EI51/EO 51 P 50 /CCD0 3/TS 00/ EI5 0/E O50 P 30 /INTP3 /TSCAP/ RTC1 HZ/E I30 /VCOUT0 P 87 /( INTP 9)
P156 /ANI14
P155 /ANI 13 /TS35 P154 /ANI 12 /TS34 P153 /ANI 11 /TS33 P152 /ANI 10 /TS32
P151 /ANI9/TS31 P150 /ANI8/TS30 P 27 /ANI7 /TS25 P 26 /ANI6 /TS24 P 25 /ANI5 /TS23 P 24 /ANI4 /TS22 P23/ANI3/ANO1/IVREF 0/EI23/TS21 P22/ANI2/ANO 0/EI22/TS20 P21/ANI 1/AVREFM/ EI21
P20/ANI 0/AVREFP/ EI20 P 130
P102 /TI06/TO06 P07
P04 /SCK10 / SCL10 P03 /ANI16 /TS 29 /SI10 /RxD1/ SDA10
P02/ANI 17/TS28/SO10/TxD1
P01 /TS 27/ EI01 /EO 01 /TO00 P00/TS26/EI 00/TI00 P145 /TI07/TO07 P 144 /SO 30 /TxD3
P143 /SI30/RxD3/SDA30
102101100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
103
64
104
63
105
62
106
61
107
60
108
59
109
58
110
57
111
56
112
55
113
54
114
RL78/G23
53
115
52
116
(Top View)
51
117
50
118
49
119
48
120
47
121
46
122
45
123
44
124
43
125
42
126
41
127
40
128
39
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1920 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
P 86 /(INTP 8) P 85 /(INTP 7) /CLKA 0 P 84 /(INTP 6) /RxDA0
P 83 /TxDA0 P82/(SO 10)/(TxD1) P 81 /(SI 10 )/(RxD1)/(SDA10 ) P 80 /(SCK 10 ) /(SCL 10 ) EV D D1
EVSS 1 P 05 /TS10 P 06 /TS11 P 70 /KR0/ TS02 /RIN0/SCK 21 /SCL21
P 71 /KR1/ TS03 /SI21 / SDA21 P 72 /KR2/ TS04 /SO21 P 73 /KR3/ TS05 P 74 /KR4/ TS06 /INTP8 P 75 /KR5/ TS07 /INTP9
P 76 /KR6/ TS08 /INTP10 /(RxD2 ) P 77 /KR7/ TS09 /INTP11 /(TxD2) P 67 /TI13 /TO13 /TS15 P 66 /TI12 /TO12 /TS14
P 65 /TI11 /TO11 /TS13 P 64 /TI10 /TO10 /TS12 P 31 /TI03 /TO03 /INTP4 /TS01 /EI 31 /( PCLBUZ0 ) P 63 /CCD07 /SDAA 1 P 62 /CCD06 /SCLA 1
P1 42 /SCK3 0/S CL 30 P1 41 /PCLB UZ1 /INTP7 P1 40 /PCLB UZ0 /INTP6 P12 0/A NI19 /IVCM P1 /EI1 20
P37/ ANI21 P36/ ANI22 P35/ ANI23 P34/TxDA1 P33/RxDA1 P32/CLKA1 P10 6/ TI 17 /TO17 P10 5/ TI 16 /TO16 P10 4/ TI 15 /TO15 P10 3/ TI 14 /TO14 P47/INTP2 P46/ INTP1/TI05/TO05 P4 5/S O01 P 44 /SI0 1/S DA01 P 43 /SCK0 1/S CL 01 P4 2/ TI 04 /TO04
P41 P4 0/ TO OL0
P1 27 P1 26 P1 25 RES ET P 12 4/X T2/E XCLKS P 123 /XT1 P1 37 /INTP0 /EI1 37 P12 2/X 2/E XCLK /EI1 22 P1 21 /X1 /EI1 21 /VB AT RE GC
VSS EVS S0
V DD EV DD0 P6 0/CCD04 /SCLA 0/E O60 P6 1/CCD05 /SDAA 0/E O61
Caution 1. Connect the EVSS0 and EVSS1 pins to the same ground as the VSS pin. Caution 2. Make sure that the voltage on the VDD pin is no less than that on the EVDD0 and EVDD1 pins. Also make sure that
the voltage on the EVDD0 is the same as that on the EVDD1 pin. Caution 3. Connect the REGC pin to VSS via a capacitor (0.47 to 1 µF).
Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it
is recommended to supply separate powers to the VDD, EVDD0, and EVDD1 pins and connect the VSS, EVSS0, and EVSS1 pins to separate ground lines. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4 - 10 Format of Peripheral I/O Redirection Register (PIOR).
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 22 of 1478
RL78/G23
1.4
Pin Identification
ANI0 to ANI14,
ANI16 to ANI26:
Analog input
ANO0, ANO1:
Analog output
AVREFM:
Analog reference voltage minus
AVREFP:
Analog reference voltage plus
CCD00 to CCD07:
Controlled current drive output
CLKA0, CLKA1:
Asynchronous serial clock output
EI00, EI01, EI10 to EI12,
EI20 to EI23, EI30, EI31,
EI50, EI51,
EI120 to EI122,
EI137, EI147:
Logic & event link controller input
EO01, EO10 to EO17,
EO50, EO51,
EO60, EO61:
Logic & event link controller output
EVDD0, EVDD1:
Power supply for port
EVSS0, EVSS1:
Ground for port
EXCLK:
External clock input
(main system clock)
EXCLKS:
External clock input
(subsystem clock)
INTP0 to INTP11:
Interrupt request from
Peripheral
IVCMP0, IVCMP1:
Comparator input
IVREF0, IVREF1:
Comparator reference input
KR0 to KR7:
Key return
P00 to P07:
Port 0
P10 to P17:
Port 1
P20 to P27:
Port 2
P30 to P37:
Port 3
P40 to P47:
Port 4
P50 to P57:
Port 5
P60 to P67:
Port 6
P70 to P77:
Port 7
P80 to P87:
Port 8
P90 to P97:
Port 9
P100 to P106:
Port 10
P110 to P117:
Port 11
P120 to P127:
Port 12
P130, P137:
Port 13
P140 to P147:
Port 14
P150 to P156:
Port 15
CHAPTER 1 OUTLINE
PCLBUZ0, PCLBUZ1:
Programmable clock output/buzzer
Output
REGC:
Regulator capacitance
RESET:
Reset
RIN0:
IR remote controller input
RTC1HZ:
Realtime clock correction clock (1 Hz)
Output
RxD0 to RxD3,
RxDA0, RxDA1:
Receive data
SCLA0, SCLA1,
SCK00, SCK01, SCK10,
SCK11, SCK20, SCK21,
SCK30, SCK31:
Serial clock input/output
SCLA0, SCLA1, SCL00,
SCL01, SCL10, SCL11,
SCL20, SCL21, SCL30,
SCL31:
Serial clock output
SDAA0, SDAA1, SDA00,
SDA01, SDA10, SDA11,
SDA20, SDA21, SDA30,
SDA31:
Serial data input/output
SI00, SI01, SI10, SI11,
SI20, SI21, SI30, SI31:
Serial data input
SO00, SO01, SO10,
SO11, SO20, SO21,
SO30, SO31:
Serial data output
TSCAP:
Touch sensor capacitance
TI00 to TI07, TI10 to TI17:
Timer input
TO00 to TO07,
TO10 to TO17:
Timer output
TOOL0:
Data input/output for tool
TOOLRxD, TOOLTxD:
Data input/output for external device
TS00 to TS15, TS20 to TS35: Capacitive sensor
TxD0 to TxD3,
TxDA0, TxDA1:
Transmit data
VBAT:
Battery backup power supply
VCOUT0, VCOUT1:
Comparator output
VDD:
Power supply
VSS:
Ground
X1, X2:
Crystal oscillator (main system clock)
XT1, XT2:
Crystal oscillator (subsystem clock)
TOOL0:
Data input/output for tool
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 23 of 1478
RL78/G23
1.5
Block Diagram
CHAPTER 1 OUTLINE
TImn TOmn
RTC1HZ
TIMER ARRAY UNIT m CHn
32-BIT INTERVAL TIMER
REALTIME CLOCK
VDD, VSS, TOOLRxD/P11, EVDD0, EVSS0, TOOLTxD/P12 EVDD1 EVSS1
DATA FLASH CODE FLASH
MEMORY
MEMORY
RxDq TxDq
SCKp SIp
SOp
SCLr SDAr
SCLAn SDAAn
RxDAn TxDAn
SERIAL ARRAY UNIT m UARTq
CSIp
IICr
SERIAL INTERFACE IICAn
SERIAL INTERFACE UARTAn
RIN0 TOOL0
REMOTE CONTROL SIGNAL RECEIVER
ON-CHIP DEBUG
SAFETY FUNCTION
SECURITY FUNCTION
RL78 CPU CORE
MULTIPLIER& DIVIDER, MULTIPLY-
ACCUMULATOR
RAM
CLOCK GENERATOR +
RESET GENERATOR
RESET
High-Speed SYSTEM CLOCK
OSCILLATOR 1 to 20 MHz
X1 X2/EXCLK
SUBSYSTEM CLOCK
OSCILLATOR 32.768 kHz
High- Speed ON- CHIP OSCILLATOR 1 to 32 MHz
Middle- Speed ON- CHIP
OSCILLATOR 1 to 4 MHz
Low-Speed ON-CHIP OSCILLATOR 32.768 kHz
XT1 XT2/EXCLKS
POR/LVD CONTROL POWER ON RESET/
VOLTAGE DETECTOR
RESET CONTROL
WINDOW WATCHDOG TIMER
BCD CORRECTION
CRC
PORTx
Pxx
KEY RETURN
A/ D CONVERTER
D/ A CONVERTER
COMPARATOR
KRn
ANIn AVREFP AVREFM
ANOn
VOUTn IVCMPn IVREFn
BUZZER OUTPUT
CLOCK OUTPUT CONTROL
PCLBUZn
CAPACITIVE SENSING UINT
DATA TRANSFER CONTROLLER
SNOOZE MODE SEQUENCER
LOGIC& EVENT LINK CONTROLLER
INTERRUPT CONTROL
TSn TSCAP
EOn EIn INTPn
VOLTAGE REGULATOR
REGC
Caution 1. 32- to 128-pin products incorporate the remote control signal receiver. Caution 2. 36- to 128-pin products incorporate the serial interface UARTA. Caution 3. 40- to 128-pin products incorporate the key return function.
Remark m: Unit number, n: Channel number, p: CSI number, q: UART number, r: Simplified I2C number, xx: Port number
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 24 of 1478
RL78/G23
CHAPTER 1 OUTLINE
1.6
Outline of Functions
[30-, 32-, 36-, 40-, 44-, and 48-pin products] Caution This outline describes the functions at the time when peripheral I/O redirection register (PIOR) is set
to 00H.
(1/3)
30-pin
32-pin
36-pin
40-pin
44-pin
48-pin
Item
R7F100GAx R7F100GBx R7F100GCx R7F100GEx R7F100GFx R7F100GGx
Code flash memory
96 to 256 KB 96 to 256 KB 96 to 256 KB 96 to 256 KB 96 to 768 KB 96 to 768 KB
Data flash memory
8 KB
8 KB
8 KB
8 KB
8 KB
8 KB
RAM
12 to 24 KB 12 to 24 KB 12 to 24 KB 12 to 24 KB 12 to 48 KB 12 to 48 KB
Address space
1 MB
CPU/peripheral hardware clock frequency (fCLK)
Main system clock HS mode: 1 to 32 MHz (VDD = 1.8 to 5.5 V) Main system clock HS mode: 1 to 4 MHzNote 1 (VDD = 1.6 to 5.5 V) Main system clock LS mode: 1 to 24 MHz (VDD = 1.8 to 5.5 V) Main system clock LS mode: 1 to 4 MHzNote 1 (VDD = 1.6 to 5.5 V) Main system clock LP mode: 1 to 2 MHzNote 2 (VDD = 1.6 to 5.5 V)
Subsystem clock: 32.768 kHz (VDD = 1.6 to 5.5 V)
Main system High-speed system
clock
clock (fMX)
1 to 20 MHz
High-speed on-chip oscillator clock (fIH)
1 MHz, 2 MHz, 3 MHz, 4 MHz, 6 MHz, 8 MHz, 12 MHz, 16 MHz 24 MHz, 32 MHz
Middle-speed on-chip 1 MHz, 2 MHz, 4 MHz oscillator clock (fIM)
Subsystem Subsystem clock X
clock
(fSX)
32.768 kHz (VDD = 2.4 to 5.5 V)
32.768 kHz (VDD = 1.6 to 5.5 V)
Low-speed on-chip oscillator clock (fIL)
32.768 kHz (typ.)
General-purpose registers
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time 0.03125 µs (at the 32-MHz operation with the high-speed on-chip oscillator clock (fIH))
Instruction set
· Data transfer (8/16 bits) · Adder and subtractor/logical operation (8/16 bits) · Multiplication (8 bits × 8 bits, 16 bits × 16 bits), division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits) · Multiplication and accumulation (16 bits × 16 bits + 32 bits) · Rotate, barrel shift, and bit manipulation (set, reset, test, and Boolean operation), etc.
I/O port
Total number of pins 26
28
32
36
40
44
CMOS I/O
23 (N-ch open drain I/O [VDD withstand voltage]: 10)
24 (N-ch open drain I/O [VDD withstand voltage]: 10)
28 (N-ch open drain I/O [VDD withstand voltage]: 12)
30 (N-ch open drain I/O [VDD withstand voltage]: 12)
33 (N-ch open drain I/O [VDD withstand voltage]: 12)
36 (N-ch open drain I/O [VDD withstand voltage]: 13)
CMOS input
1
1
1
3
3
3
CMOS output
--
--
--
--
--
1
N-ch open drain I/O
2
3
3
3
4
4
(withstand voltage: 6 V)
Output current control 6
7
7
7
8
8
port
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CHAPTER 1 OUTLINE
Timers
Item
16-bit timer Watchdog timer Realtime clock (RTC)
30-pin R7F100GAx 8 channels 1 channel 1 channel
32-pin R7F100GBx
36-pin R7F100GCx
40-pin R7F100GEx
44-pin R7F100GFx
(2/3)
48-pin R7F100GGx
32-bit interval timer (TML32)
1 channel in 32-bit mode, 2 channels in 16-bit mode, 4 channels in 8-bit mode
Timer output
4 channels (PWM outputs: 3Note 3), 8 channels (PWM outputs: 7Note 3)Note 4
5 channels (PWM outputs: 4Note 3),
8 channels (PWM outputs: 7Note 3)Note 4
RTC output
1 channel
Clock output/buzzer output
2
· 3.91 kHz, 7.81 kHz, 15.63 kHz, 2 MHz, 4 MHz, 8 MHz, 16 MHz (at the 32-MHz operation with the main system clock (fMAIN))
· 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (at the 32.768-kHz operation with the low-speed peripheral clock (fSXP))
8-/10-/12-bit resolution A/D converter 8 channels 8 channels 8 channels 9 channels 10 channels 10 channels
D/A converter
2 channels 2 channels 2 channels 2 channels 2 channels 2 channels
Comparator
2 channels 2 channels 2 channels 2 channels 2 channels 2 channels
Serial interface
[30- and 32-pin products] · SPI (CSI): 1 channel/simplified I2C: 1 channel/UART: 1 channel · SPI (CSI): 1 channel/simplified I2C: 1 channel/UART: 1 channel · SPI (CSI): 1 channel/simplified I2C: 1 channel/UART (UART supporting LIN-bus): 1 channel [36-, 40-, and 44-pin products] · SPI (CSI): 1 channel/simplified I2C: 1 channel/UART: 1 channel · SPI (CSI): 1 channel/simplified I2C: 1 channel/UART: 1 channel · SPI (CSI): 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN-bus): 1 channel [48-pin products] · SPI (CSI): 2 channels/simplified I2C: 2 channels/UART: 1 channel · SPI (CSI): 1 channel/simplified I2C: 1 channel/UART: 1 channel · SPI (CSI): 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN-bus): 1 channel
UARTA
--
1 channel
1 channel
2 channels 2 channels
I2C bus
1 channel
1 channel
1 channel
1 channel
2 channels 2 channels
Remote control signal receiver
--
1 channel
1 channel
1 channel
1 channel
1 channel
Data transfer controller (DTC)
30 sources 30 sources 32 sources 33 sources 35 sources 36 sources
Logic and event link controller (ELCL) 1
SNOOZE mode sequencer (SMS)
1
Capacitive sensing unit
6
7
11
13
14
16
Vectored interrupt sources
Internal External
31
32
35
35
39
39
6
6
6
7
7
10
Key interrupt
--
--
--
4
4
6
Reset
· Reset by RESET pin · Internal reset by watchdog timer · Internal reset by power-on-reset · Internal reset by voltage detectors (LVD0 and LVD1) · Internal reset by illegal instruction executionNote 5 · Internal reset by RAM parity error · Internal reset by illegal-memory access
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CHAPTER 1 OUTLINE
Item Power-on-reset circuit
30-pin
32-pin
R7F100GAx R7F100GBx
Detection voltage · 1.50 V (typ.)
36-pin R7F100GCx
40-pin R7F100GEx
44-pin R7F100GFx
(3/3)
48-pin R7F100GGx
Voltage detector
Detection voltage · Rising edge: 1.67 to 4.00 V (6 stages) for LVD0
1.67 to 4.16 V (18 stages) for LVD1 · Falling edge : 1.63 to 3.92 V (6 stages) for LVD0
1.63 to 4.08 V (18 stages) for LVD1
On-chip debugging
Available (tracing supported)
Power supply voltage
VDD = 1.6 to 5.5 V (2D: Consumer applications), VDD = 1.8 to 5.5 V (3C: Industrial applications)
Operating ambient temperature
TA = -40 to +85°C (2D: Consumer applications), TA = -40 to +105°C (3C: Industrial applications)
Note 1. Overwrite the flash memory during operation at 2 MHz or a lower frequency.
Note 2. When the flash memory is to be overwritten, switch to high-speed main (HS) mode or low-speed main (LS) mode.
Note 3. The number of PWM outputs varies depending on the setting of channels in use (the number of masters and slaves).
For details, see 7.9.3 Operation for the multiple PWM output function.
Note 4. This applies when the setting of the PIOR0 bit is 1.
Note 5. In normal operation, executing the instruction code FFH triggers an internal reset, but this is not the case during emulation
by the in-circuit emulator or on-chip debugging emulator.
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CHAPTER 1 OUTLINE
[52-, 64-, 80-, 100-, and 128-pin products] Caution This outline describes the functions at the time when peripheral I/O redirection register (PIOR) is set
to 00H.
(1/3)
52-pin
64-pin
80-pin
100-pin
128-pin
Item
R7F100GJx
R7F100GLx
R7F100GMx
R7F100GPx
R7F100GSx
Code flash memory
96 to 768 KB 96 to 768 KB 128 to 768 KB 128 to 768 KB 256 to 768 KB
Data flash memory
8 KB
8 KB
8 KB
8 KB
8 KB
RAM
12 to 48 KB
12 to 48 KB
16 to 48 KB
16 to 48 KB
24 to 48 KB
Address space
1 MB
CPU/peripheral hardware clock frequency (fCLK)
Main system clock HS mode: 1 to 32 MHz (VDD = 1.8 to 5.5 V) Main system clock HS mode: 1 to 4 MHzNote 1 (VDD = 1.6 to 5.5 V)
Main system clock LS mode: 1 to 24 MHz (VDD = 1.8 to 5.5 V) Main system clock LS mode: 1 to 4 MHzNote 1 (VDD = 1.6 to 5.5 V) Main system clock LP mode: 1 to 2 MHzNote 2 (VDD = 1.6 to 5.5 V)
Subsystem clock: 32.768 kHz (VDD = 1.6 to 5.5 V)
Main system clock
High-speed system clock (fMX)
High-speed on-chip oscillator clock (fIH)
1 to 20 MHz 1 MHz, 2 MHz, 3 MHz, 4 MHz, 6 MHz, 8 MHz, 12 MHz, 16 MHz 24 MHz, 32 MHz
Middle-speed on-chip oscillator clock (fIM)
1 MHz, 2 MHz, 4 MHz
Subsystem clock
Subsystem clock X (fSX)
Low-speed on-chip oscillator clock (fIL)
32.768 kHz (VDD = 1.6 to 5.5 V) 32.768 kHz (typ.)
General-purpose registers
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time
0.03125 µs (at the 32-MHz operation with the high-speed on-chip oscillator clock (fIH))
Instruction set
· Data transfer (8/16 bits) · Adder and subtractor/logical operation (8/16 bits) · Multiplication (8 bits × 8 bits, 16 bits × 16 bits), division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits) · Multiplication and accumulation (16 bits × 16 bits + 32 bits) · Rotate, barrel shift, and bit manipulation (set, reset, test, and Boolean operation), etc.
I/O port
Total number of pins
48
58
74
92
120
CMOS I/O
40 (N-ch open drain I/O [VDD withstand voltage]: 15)
50 (N-ch open drain I/O [EVDD withstand voltage]: 22Note 6/ 18Note 7)
66 (N-ch open drain I/O [EVDD withstand voltage]: 27)
84 (N-ch open drain I/O [EVDD withstand voltage]: 31)
112 (N-ch open drain I/O [EVDD withstand voltage]: 33)
CMOS input
3
3
3
3
3
CMOS output
1
1
1
1
1
N-ch open drain I/O
4
4
4
4
4
(withstand voltage: 6 V)
Output current control port 8
8
8
8
8
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Timers
Item 16-bit timer Watchdog timer Realtime clock (RTC) 32-bit interval timer (TML32)
Timer output
RTC output Clock output/buzzer output
8-/10-/12-bit resolution A/D converter D/A converter Comparator Serial interface
UARTA
I2C bus Remote control signal receiver
Data transfer controller (DTC) Logic and event link controller (ELCL) SNOOZE mode sequencer (SMS) Capacitive sensing unit
52-pin R7F100GJx 8 channels
64-pin R7F100GLx
80-pin R7F100GMx 12 channels
100-pin R7F100GPx
(2/3)
128-pin R7F100GSx 16 channels
1 channel
1 channel
1 channel in 32-bit mode, 2 channels in 16-bit mode, 4 channels in 8-bit mode
5 channels (PWM outputs: 4Note 3), 8 channels (PWM outputs: 7Note 3)Note 4
8 channels (PWMoutputs: 7Note 3)
1 channel
12 channels (PWM outputs: 10Note 3)
16 channels (PWM outputs: 14Note 3)
2
2
2
2
2
· 3.91 kHz, 7.81 kHz, 15.63 kHz, 2 MHz, 4 MHz, 8 MHz, 16 MHz (at the 32-MHz operation with the main system clock (fMAIN))
· 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (at the 32.768-kHz operation with the low-speed peripheral clock (fSXP))
12 channels
12 channels
17 channels
20 channels
26 channels
2 channels
2 channels
2 channels
2 channels
2 channels
2 channels
2 channels
2 channels
2 channels
2 channels
[52-pin products] · SPI (CSI): 2 channels/simplified I2C: 2 channels/UART: 1 channel · SPI (CSI): 1 channel/simplified I2C: 1 channel/UART: 1 channel · SPI (CSI): 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN-bus): 1 channel [64-pin products] · SPI (CSI): 2 channels/simplified I2C: 2 channels/UART: 1 channel · SPI (CSI): 2 channels/simplified I2C: 2 channels/UART: 1 channel · SPI (CSI): 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN-bus): 1 channel [80-, 100-, and 128-pin products] · SPI (CSI): 2 channels/simplified I2C: 2 channels/UART: 1 channel · SPI (CSI): 2 channels/simplified I2C: 2 channels/UART: 1 channel · SPI (CSI): 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN-bus): 1 channel · SPI (CSI): 2 channels/simplified I2C: 2 channels/UART: 1 channel
2 channels
2 channels
2 channels
2 channels
2 channels
2 channels
2 channels
2 channels
2 channels
2 channels
1 channel
1 channel
1 channel
1 channel
1 channel
36 sources
37 sources
39 sources
1
1
20
22
30
32
32
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CHAPTER 1 OUTLINE
(3/3)
52-pin
64-pin
80-pin
100-pin
128-pin
Item
R7F100GJx
R7F100GLx
R7F100GMx
R7F100GPx
R7F100GSx
Vectored interrupt sources
Internal External
39
39
44
44
48
12
13
13
13
13
Key interrupt
8
8
8
8
8
Reset
· Reset by RESET pin · Internal reset by watchdog timer · Internal reset by power-on-reset · Internal reset by voltage detectors (LVD0 and LVD1) · Internal reset by illegal instruction executionNote 5 · Internal reset by RAM parity error · Internal reset by illegal-memory access
Power-on-reset circuit
Detection voltage · 1.50 V (typ.)
Voltage detector
Detection voltage · Rising edge: 1.67 to 4.00 V (6 stages) for LVD0
1.67 to 4.16 V (18 stages) for LVD1 · Falling edge: 1.63 to 3.92 V (6 stages) for LVD0
1.63 to 4.08 V (18 stages) for LVD1
On-chip debugging
Available (tracing supported)
Power supply voltage
VDD = 1.6 to 5.5 V (2D: Consumer applications), VDD = 1.8 to 5.5 V (3C: Industrial applications)
Operating ambient temperature
TA = -40 to +85°C (2D: Consumer applications), TA = -40 to +105°C (3C: Industrial applications)
Note 1. Overwrite the flash memory during operation at 2 MHz or a lower frequency.
Note 2. When the flash memory is to be overwritten, switch to high-speed main (HS) mode or low-speed main (LS) mode.
Note 3. The number of PWM outputs varies depending on the setting of channels in use (the number of masters and slaves).
For details, see 7.9.3 Operation for the multiple PWM output function.
Note 4. This applies when the setting of the PIOR0 bit is 1.
Note 5. In normal operation, executing the instruction code FFH triggers an internal reset, but this is not the case during emulation
Note 6. Note 7.
by the in-circuit emulator or on-chip debugging emulator. This only applies to the products with 96- and 128-Kbyte flash memory. This only applies to the products with 192- to 768-Kbyte flash memory.
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CHAPTER 2 PIN FUNCTIONS
CHAPTER 2 PIN FUNCTIONS
2.1
Functions of Port Pins
Pin I/O buffer power supplies depend on the product. The relationship between these power supplies and the pins is shown below.
Table 2 - 1 Pin I/O Buffer Power Supplies
(1) 30-, 32-, 36-, 40-, 44-, 48-, and 52-pin products
Power Supply
VDD
All pins
Corresponding Pins
(2) 64-pin products
Power Supply EVDD0 VDD
Corresponding Pins
· Port pins other than P20 to P27, P121 to P124, and P137
· P20 to P27, P121 to P124, and P137 · RESET, REGC
(3) 80-pin products
Power Supply EVDD0
VDD
Corresponding Pins
· Port pins other than P20 to P27, P121 to P124, P137, and P150 to P153
· P20 to P27, P121 to P124, P137, and P150 to P153 · RESET, REGC
(4) 100- and 128-pin products
Power Supply
Corresponding Pins
EVDD0, EVDD1
· Port pins other than P20 to P27, P121 to P124, P137, and P150 to P156
VDD
· P20 to P27, P121 to P124, P137, and P150 to P156
· RESET, REGC
Caution EVDD0 and EVDD1 should have the same potential.
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CHAPTER 2 PIN FUNCTIONS
2.1.1 30-pin products
Function Name
Pin Type
P00
7-33-4
P01
8-33-2
P10
8-1-11
P11
P12
7-1-12
P13
8-6-9
P14
8-1-11
P15
P16
8-38-1
P17
8-38-2
P20
4-3-5
P21
P22
4-35-1
P23
4-37-1
P30
7-31-2
P31
P40
7-1-3
(1/2)
I/O
After Reset Release
Alternate Function
Function
I/O
Analog function ANI17/TS26Note 2/
Port 0.
EI00/TI00/TxD1
2-bit I/O port.
ANI16/TS27Note 2/ EI01/EO01/TO00/RxD1
Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port.
Input of P01 can be set to TTL input buffer.
Output of P00 can be set to N-ch open-drain output
(VDD tolerance).
P00 and P01 can be set for the analog pin
functionsNote 1.
I/O Input port
EI10/EO10/SCK00/SCL00/ Port 1.
(TI07)/(TO07)
8-bit I/O port.
EI11/EO11/SI00/RxD0/ TOOLRxD/SDA00/(TI06)/ (TO06)
Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P10, P11, and P13 to P17 can be set to TTL
EI12/EO12/SO00/TxD0/ TOOLTxD/(TI05)/(TO05)
input buffer. Output of P10 to P15 and P17 can be set to N-ch open-drain output (VDD tolerance).
Analog function IVREF1/EO13/TxD2/SO20/ P16 and P17 can be set as output current control port
(SDAA0)/(TI04)/(TO04) pins.
Input port
VCOUT1/EO14/RxD2/SI20/ P13 can be set for the analog pin functionNote 1.
SDA20/(SCLA0)/(TI03)/
(TO03)
EO15/PCLBUZ1/SCK20/ SCL20/(TI02)/(TO02)
EO16/CCD00/TI01/TO01/ INTP5/(RxD0)
EO17/CCD01/TI02/TO02/ (TxD0)
I/O
Analog function ANI0/AVREFP/EI20
Port 2.
ANI1/AVREFM/EI21
4-bit I/O port. Input or output can be specified in 1-bit units.
ANI2/ANO0/TS20Note 2/ EI22
P20 to P23 can be set for the analog pin functions Note 1.
ANI3/ANO1/IVREF0/ TS21Note 2/EI23
I/O Input port
VCOUT0/TSCAP/EI30/ INTP3/RTC1HZ/SCK11/ SCL11
TS01/EI31/TI03/TO03/ INTP4/PCLBUZ0
Port 3. 2-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port.
I/O Input port
TOOL0
Port 4. 1-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port.
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(2/2)
Function Name
Pin Type
I/O
After Reset Release
Alternate Function
Function
P50
7-39-1
I/O Input port
TS00/EI50/EO50/CCD03/ Port 5.
INTP1/SI11/SDA11
2-bit I/O port.
P51
7-38-1
Output of P50 can be set to N-ch open-drain output
EI51/EO51/CCD02/INTP2/ (VDD tolerance).
SO11
Input or output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by
a software setting at input port.
P50 and P51 can be set as output current control port
pins.
P60
12-38-3
I/O Input port
EO60/CCD04/SCLA0
Port 6.
2-bit I/O port.
P61
EO61/CCD05/SDAA0
Input or output can be specified in 1-bit units.
The outputs of P60 and P61 are N-ch open-drain (6-V
tolerance).
P60 and P61 can be set as output current control port
pins.
P120 P121 P122
7-9-6 7-2-1
I/O Analog function ANI19/IVCMP1/EI120
Port 12.
Input port
X1/XT1/EI121
3-bit I/O port. Input or output can be specified in 1-bit units.
X2/EXCLK/XT2/EXCLKS/ EI122
Use of an on-chip pull-up resistor can be specified by a software setting at input port. Output of P120 can be set to N-ch open-drain output
(VDD tolerance).
P120 can be set for the analog pin functionNote 1.
P137
2-1-3
Input Input port
EI137/INTP0
Port 13. 1-bit input-only port.
P147
7-9-5
I/O Analog function ANI18/IVCMP0/EI147
Port 14. 1-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P147 can be set for the analog pin functionNote 1.
RESET
Note 1. Note 2.
2-1-1
Input --
--
Input-only pin for the external reset signal. When an external reset signal is not in use, connect this pin to VDD, either directly or via a resistor.
Digital or analog for each pin can be selected with the port mode control A register x (PMCAx) (can be set in 1-bit unit). These functions are not present in products with 128 or fewer Kbytes of code flash memory.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4 - 10 Format of Peripheral I/O Redirection Register (PIOR).
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CHAPTER 2 PIN FUNCTIONS
2.1.2 32-pin products
Function Name
Pin Type
P00
7-33-4
P01
8-33-2
P10
8-1-11
P11
P12
7-1-12
P13
8-6-9
P14
8-1-11
P15
P16
8-38-1
P17
8-38-2
P20
4-3-5
P21
P22
4-35-1
P23
4-37-1
P30
7-31-2
P31
P40
7-1-3
I/O I/O I/O
I/O I/O I/O
(1/2)
After Reset Release
Alternate Function
Function
Analog function ANI17/TS26Note 2/ EI00/TI00/TxD1
ANI16/TS27Note 2/ EI01/EO01/TO00/RxD1
Port 0. 2-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P01 can be set to TTL input buffer. Output of P00 can be set to N-ch open-drain output (VDD tolerance). P00 and P01 can be set for the analog pin functionsNote 1.
Input port
Analog function Input port
EI10/EO10/SCK00/SCL00/ (TI07)/(TO07)
EI11/EO11/SI00/RxD0/ TOOLRxD/SDA00/(TI06)/ (TO06)
EI12/EO12/SO00/TxD0/ TOOLTxD/(TI05)/(TO05)
IVREF1/EO13/TxD2/SO20/ (SDAA0)/(TI04)/(TO04)
VCOUT1/EO14/RxD2/ SI20/SDA20/(SCLA0)/ (TI03)/(TO03)
Port 1. 8-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P10, P11, and P13 to P17 can be set to TTL input buffer. Output of P10 to P15 and P17 can be set to N-ch open-drain output (VDD tolerance). P16 and P17 can be set as output current control port pins. P13 can be set for the analog pin functionNote 1.
EO15/PCLBUZ1/SCK20/ SCL20/(TI02)/(TO02)
EO16/CCD00/TI01/TO01/ INTP5/(RxD0)
EO17/CCD01/TI02/TO02/ (TxD0)
Analog function ANI0/AVREFP/EI20
ANI1/AVREFM/EI21
ANI2/ANO0/TS20Note 2/ EI22
Port 2. 4-bit I/O port. Input or output can be specified in 1-bit units. P20 to P23 can be set for the analog pin functionsNote 1.
ANI3/ANO1/IVREF0/ TS21Note 2/EI23
Input port
VCOUT0/TSCAP/EI30/ INTP3/RTC1HZ/SCK11/ SCL11
TS01/EI31/TI03/TO03/ INTP4/PCLBUZ0
Port 3. 2-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port.
Input port
TOOL0
Port 4. 1-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port.
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CHAPTER 2 PIN FUNCTIONS
(2/2)
Function Name
Pin Type
I/O
After Reset Release
Alternate Function
Function
P50
7-39-1
I/O Input port
TS00/EI50/EO50/CCD03/ Port 5.
INTP1/SI11/SDA11
2-bit I/O port.
P51
7-38-1
Output of P50 can be set to N-ch open-drain output
EI51/EO51/CCD02/INTP2/ (VDD tolerance).
SO11
Input or output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by
a software setting at input port.
P50 and P51 can be set as output current control
port pins.
P60
12-38-3
I/O Input port
EO60/CCD04/SCLA0
Port 6.
3-bit I/O port.
P61
EO61/CCD05/SDAA0
Input or output can be specified in 1-bit units.
P62
12-38-1
CCD06
The outputs of P60 to P62 are N-ch open-drain (6-V tolerance).
P60 to P62 can be set as output current control port
pins.
P70
7-31-2
I/O Input port
RIN0/TS02
Port 7. 1-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port.
P120 P121 P122
7-9-6 7-2-1
I/O Analog function ANI19/IVCMP1/EI120
Port 12.
Input port
X1/XT1/EI121
3-bit I/O port. Input or output can be specified in 1-bit units.
X2/EXCLK/XT2/EXCLKS/ EI122
Use of an on-chip pull-up resistor can be specified by a software setting at input port. Output of P120 can be set to N-ch open-drain output
(VDD tolerance).
P120 can be set for the analog pin functionNote 1.
P137
2-1-3
Input Input port
EI137/INTP0
Port 13. 1-bit input-only port.
P147
7-9-5
I/O Analog function ANI18/IVCMP0/EI147
Port 14. 1-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P147 can be set for the analog pin functionNote 1.
RESET
Note 1. Note 2.
2-1-1
Input --
--
Input-only pin for the external reset signal. When an external reset signal is not in use, connect this pin to VDD, either directly or via a resistor.
Digital or analog for each pin can be selected with the port mode control A register x (PMCAx) (can be set in 1-bit unit). These functions are not present in products with 128 or fewer Kbytes of code flash memory.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4 - 10 Format of Peripheral I/O Redirection Register (PIOR).
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CHAPTER 2 PIN FUNCTIONS
2.1.3 36-pin products
Function Name
Pin Type
P00
7-31-3
P01
8-31-1
P10
8-1-11
P11
P12
7-1-12
P13
8-6-9
P14
8-1-11
P15
P16
8-38-1
P17
8-38-2
P20
4-3-5
P21
P22
4-35-1
P23
4-37-1
P24
4-33-1
P25
P30
7-31-2
P31
P40
7-1-3
I/O I/O I/O
I/O I/O I/O
(1/2)
After Reset Release
Alternate Function
Function
Input port
TS26Note 2/ EI00/TI00/TxD1
TS27Note 2/EI01/EO01/ TO00/RxD1
Port 0. 2-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P01 can be set to TTL input buffer. Output of P00 can be set to N-ch open-drain output (VDD tolerance).
Input port
Analog function Input port
EI10/EO10/SCK00/SCL00/ (TI07)/(TO07)
EI11/EO11/SI00/RxD0/ TOOLRxD/SDA00/(TI06)/ (TO06)
EI12/EO12/SO00/TxD0/ TOOLTxD/(TI05)/(TO05)
IVREF1/EO13/TxD2/SO20/ (SDAA0)/(TI04)/(TO04)
VCOUT1/EO14/RxD2/ SI20/SDA20/(SCLA0)/ (TI03)/(TO03)
Port 1. 8-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P10, P11, and P13 to P17 can be set to TTL input buffer. Output of P10 to P15 and P17 can be set to N-ch open-drain output (VDD tolerance). P16 and P17 can be set as output current control port pins. P13 can be set for the analog pin functionNote 1.
EO15/PCLBUZ1/SCK20/ SCL20/(TI02)/(TO02)
EO16/CCD00/TI01/TO01/ INTP5/(RxD0)
EO17/CCD01/TI02/TO02/ (TxD0)
Analog function ANI0/AVREFP/EI20
ANI1/AVREFM/EI21
ANI2/ANO0/TS20Note 2/ EI22
Port 2. 6-bit I/O port. Input or output can be specified in 1-bit units. P20 to P25 can be set for the analog pin functionsNote 1.
ANI3/ANO1/IVREF0/ TS21Note 2/EI23
ANI4/TS22Note 2
ANI5/TS23Note 2
Input port
VCOUT0/TSCAP/EI30/ INTP3/RTC1HZ/SCK11/ SCL11
TS01/EI31/TI03/TO03/ INTP4/PCLBUZ0
Port 3. 2-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port.
Input port
TOOL0
Port 4. 1-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port.
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Function Name
Pin Type
I/O
After Reset Release
Alternate Function
Function
P50
7-39-1
I/O Input port
TS00/EI50/EO50/CCD03/ Port 5.
INTP1/SI11/SDA11
2-bit I/O port.
P51
7-38-1
Output of P50 can be set to N-ch open-drain output
EI51/EO51/CCD02/INTP2/ (VDD tolerance).
SO11
Input or output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by
a software setting at input port.
P50 and P51 can be set as output current control
port pins.
P60
12-38-3
I/O Input port
EO60/CCD04/SCLA0
Port 6.
3-bit I/O port.
P61
EO61/CCD05/SDAA0
Input or output can be specified in 1-bit units.
P62
12-38-1
CCD06
The outputs of P60 to P62 are N-ch open-drain (6-V tolerance).
P60 to P62 can be set as output current control port
pins.
P70
7-31-2
I/O Input port
TS02/RIN0/SCK21/SCL21 Port 7.
P71
8-31-2
3-bit I/O port. TS03/SI21/SDA21/RxDA0 Input of P71 can be set to TTL input buffer.
P72
7-31-3
TS04/SO21/TxDA0
Output of P71 and P72 can be set to N-ch opendrain output (VDD tolerance).
Input or output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by
a software setting at input port.
P120 P121 P122
7-9-6 7-2-1
I/O Analog function ANI19/IVCMP1/EI120
Port 12.
Input port
X1/XT1/EI121
3-bit I/O port. Input or output can be specified in 1-bit units.
X2/EXCLK/XT2/EXCLKS/ EI122
Use of an on-chip pull-up resistor can be specified by a software setting at input port. Output of P120 can be set to N-ch open-drain output
(VDD tolerance).
P120 can be set for the analog pin functionNote 1.
P137
2-1-3
Input Input port
EI137/INTP0
Port 13. 1-bit input-only port.
P147
7-9-5
I/O Analog function ANI18/IVCMP0/EI147
Port 14. 1-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P147 can be set for the analog pin functionNote 1.
RESET
Note 1. Note 2.
2-1-1
Input --
--
Input-only pin for the external reset signal. When an external reset signal is not in use, connect this pin to VDD, either directly or via a resistor.
Digital or analog for each pin can be selected with the port mode control A register x (PMCAx) (can be set in 1-bit unit). These functions are not present in products with 128 or fewer Kbytes of code flash memory.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4 - 10 Format of Peripheral I/O Redirection Register (PIOR).
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CHAPTER 2 PIN FUNCTIONS
2.1.4 40-pin products
Function Name
Pin Type
P00
7-31-3
P01
8-31-1
P10
8-1-11
P11
P12
7-1-12
P13
8-6-9
P14
8-1-11
P15
P16
8-38-1
P17
8-38-2
P20
4-3-5
P21
P22
4-35-1
P23
4-37-1
P24
4-33-1
P25
P26
P30
7-31-2
P31
P40
7-1-3
I/O I/O I/O
I/O
I/O I/O
(1/2)
After Reset Release
Alternate Function
Function
Input port
TS26Note 2/ EI00/TI00/TxD1
TS27Note 2/EI01/EO01/ TO00/RxD1
Port 0. 2-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P01 can be set to TTL input buffer. Output of P00 can be set to N-ch open-drain output (VDD tolerance).
Input port
Analog function Input port
EI10/EO10/SCK00/SCL00/ (TI07)/(TO07)
EI11/EO11/SI00/RxD0/ TOOLRxD/SDA00/(TI06)/ (TO06)
EI12/EO12/SO00/TxD0/ TOOLTxD/(TI05)/(TO05)
IVREF1/EO13/TxD2/SO20/ (SDAA0)/(TI04)/(TO04)
VCOUT1/EO14/RxD2/ SI20/SDA20/(SCLA0)/ (TI03)/(TO03)
Port 1. 8-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P10, P11, and P13 to P17 can be set to TTL input buffer. Output of P10 to P15 and P17 can be set to N-ch open-drain output (VDD tolerance). P16 and P17 can be set as output current control port pins. P13 can be set for the analog pin functionNote 1.
EO15/PCLBUZ1/SCK20/ SCL20/(TI02)/(TO02)
EO16/CCD00/TI01/TO01/ INTP5/(RxD0)
EO17/CCD01/TI02/TO02/ (TxD0)
Analog function ANI0/AVREFP/EI20
ANI1/AVREFM/EI21
ANI2/ANO0/TS20Note 2/ EI22
Port 2. 7-bit I/O port. Input or output can be specified in 1-bit units. P20 to P26 can be set for the analog pin functionsNote 1.
ANI3/ANO1/IVREF0/ TS21Note 2/EI23
ANI4/TS22Note 2
ANI5/TS23Note 2
ANI6/TS24Note 2
Input port
VCOUT0/TSCAP/EI30/ INTP3/RTC1HZ/SCK11/ SCL11
TS01/EI31/TI03/TO03/ INTP4/PCLBUZ0
Port 3. 2-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port.
Input port
TOOL0
Port 4. 1-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port.
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Function Name
Pin Type
I/O
After Reset Release
Alternate Function
Function
P50
7-39-1
I/O Input port
TS00/EI50/EO50/CCD03/ Port 5.
INTP1/SI11/SDA11
2-bit I/O port.
P51
7-38-1
Output of P50 can be set to N-ch open-drain output
EI51/EO51/CCD02/INTP2/ (VDD tolerance).
SO11
Input or output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by
a software setting at input port.
P50 and P51 can be set as output current control
port pins.
P60
12-38-3
I/O Input port
EO60/CCD04/SCLA0
Port 6.
3-bit I/O port.
P61
EO61/CCD05/SDAA0
Input or output can be specified in 1-bit units.
P62
12-38-1
CCD06
The outputs of P60 to P62 are N-ch open-drain (6-V tolerance).
P60 to P62 can be set as output current control port
pins.
P70
7-31-2
I/O Input port
TS02/RIN0/KR0/SCK21/ Port 7.
SCL21
4-bit I/O port.
P71
8-31-2
TS03/KR1/SI21/SDA21/ RxDA0
Input of P71 can be set to TTL input buffer. Output of P71 and P72 can be set to N-ch opendrain output (VDD tolerance).
P72
7-31-3
P73
7-31-2
TS04/KR2/SO21/TxDA0 TS05/KR3
Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port.
P120 P121 P122 P123 P124
7-9-6 7-2-1
2-2-1
I/O Input
Analog function ANI19/IVCMP1/EI120
Input port
X1/VBAT/EI121
X2/EXCLK/EI122
XT1
XT2/EXCLKS
Port 12. 3-bit I/O port and 2-bit input-only port. For P120 to P122, input or output can be specified in 1-bit units. For P120 to P122, use of an on-chip pull-up resistor can be specified by a software setting at input port. Output of P120 can be set to N-ch open-drain output (VDD tolerance). P120 can be set for the analog pin functionNote 1.
P137
2-1-3
Input Input port
EI137/INTP0
Port 13. 1-bit input-only port.
P147
7-9-5
I/O Analog function ANI18/IVCMP0/EI147
Port 14. 1-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P147 can be set for the analog pin functionNote 1.
RESET
Note 1. Note 2.
2-1-1
Input --
--
Input-only pin for the external reset signal. When an external reset signal is not in use, connect this pin to VDD, either directly or via a resistor.
Digital or analog for each pin can be selected with the port mode control A register x (PMCAx) (can be set in 1-bit unit). These functions are not present in products with 128 or fewer Kbytes of code flash memory.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4 - 10 Format of Peripheral I/O Redirection Register (PIOR).
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CHAPTER 2 PIN FUNCTIONS
2.1.5 44-pin products
Function Name
Pin Type
P00
7-31-3
P01
8-31-1
P10
8-1-11
P11
P12
7-1-12
P13
8-6-9
P14
8-1-11
P15
P16
8-38-1
P17
8-38-2
P20
4-3-5
P21
P22
4-35-1
P23
4-37-1
P24
4-33-1
P25
P26
P27
P30
7-31-2
P31
P40
7-1-3
P41
8-1-3
I/O I/O I/O
I/O
I/O I/O
(1/2)
After Reset Release
Alternate Function
Function
Input port
TS26Note 2/ EI00/TI00/TxD1
TS27Note 2/EI01/EO01/ TO00/RxD1
Port 0. 2-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P01 can be set to TTL input buffer. Output of P00 can be set to N-ch open-drain output (VDD tolerance).
Input port
Analog function Input port
EI10/EO10/SCK00/SCL00/ (TI07)/(TO07)
EI11/EO11/SI00/RxD0/ TOOLRxD/SDA00/(TI06)/ (TO06)
EI12/EO12/SO00/TxD0/ TOOLTxD/(TI05)/(TO05)
IVREF1/EO13/TxD2/SO20/ (SDAA0)/(TI04)/(TO04)
VCOUT1/EO14/RxD2/ SI20/SDA20/(SCLA0)/ (TI03)/(TO03)
Port 1. 8-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P10, P11, and P13 to P17 can be set to TTL input buffer. Output of P10 to P15 and P17 can be set to N-ch open-drain output (VDD tolerance). P16 and P17 can be set as output current control port pins. P13 can be set for the analog pin functionNote 1.
EO15/PCLBUZ1/SCK20/ SCL20/(TI02)/(TO02)
EO16/CCD00/TI01/TO01/ INTP5/(RxD0)
EO17/CCD01/TI02/TO02/ (TxD0)
Analog function ANI0/AVREFP/EI20
ANI1/AVREFM/EI21
ANI2/ANO0/TS20Note 2/ EI22
Port 2. 8-bit I/O port. Input or output can be specified in 1-bit units. P20 and P27 can be set for the analog pin functionsNote 1.
ANI3/ANO1/IVREF0/ TS21Note 2/EI23
ANI4/TS22Note 2
ANI5/TS23Note 2
ANI6/TS24Note 2
ANI7/TS25Note 2
Input port
VCOUT0/TSCAP/EI30/ INTP3/RTC1HZ/SCK11/ SCL11
TS01/EI31/TI03/TO03/ INTP4/PCLBUZ0
Port 3. 2-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port.
Input port
TOOL0 RxDA1/TI07/TO07
Port 4. 2-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P41 can be set to TTL input buffer.
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Function Name
Pin Type
I/O
After Reset Release
Alternate Function
Function
P50
7-39-1
I/O Input port
TS00/EI50/EO50/CCD03/ Port 5.
INTP1/SI11/SDA11
2-bit I/O port.
P51
7-38-1
Output of P50 can be set to N-ch open-drain output
EI51/EO51/CCD02/INTP2/ (VDD tolerance).
SO11
Input or output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by
a software setting at input port.
P50 and P51 can be set as output current control
port pins.
P60
12-38-3
I/O Input port
EO60/CCD04/SCLA0
Port 6.
4-bit I/O port.
P61
EO61/CCD05/SDAA0
Input or output can be specified in 1-bit units.
P62
12-38-2
CCD06/SCLA1
The outputs of P60 to P63 are N-ch open-drain (6-V tolerance).
P63
CCD07/SDAA1
P60 to P63 can be set as output current control port
pins.
P70
7-31-2
I/O Input port
TS02/RIN0/KR0/SCK21/ Port 7.
SCL21
4-bit I/O port.
P71
8-31-2
TS03/KR1/SI21/SDA21/ RxDA0
Input of P71 can be set to TTL input buffer. Output of P71 and P72 can be set to N-ch opendrain output (VDD tolerance).
P72
7-31-3
P73
7-31-2
TS04/KR2/SO21/TxDA0 TS05/KR3
Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port.
P120
P121 P122 P123 P124
7-9-6 7-2-1 2-2-1
I/O Input
Analog function ANI19/IVCMP1/TxDA1/ EI120
Input port
X1/VBAT/EI121
X2/EXCLK/EI122
XT1
XT2/EXCLKS
Port 12. 3-bit I/O port and 2-bit input-only port. For P120 to P122, input or output can be specified in 1-bit units. For P120 to P122, use of an on-chip pull-up resistor can be specified by a software setting at input port. Output of P120 can be set to N-ch open-drain output (VDD tolerance). P120 can be set for the analog pin functionNote 1.
P137
2-1-3
Input Input port
EI137/INTP0
Port 13. 1-bit input-only port.
P146 P147
7-1-3 7-9-5
I/O Input port
--
Analog function ANI18/IVCMP0/EI147
Port 14. 2-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P147 can be set for the analog pin functionNote 1.
RESET
Note 1. Note 2.
2-1-1
Input --
--
Input-only pin for the external reset signal. When an external reset signal is not in use, connect this pin to VDD, either directly or via a resistor.
Digital or analog for each pin can be selected with the port mode control A register x (PMCAx) (can be set in 1-bit unit). These functions are not present in products with 128 or fewer Kbytes of code flash memory.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4 - 10 Format of Peripheral I/O Redirection Register (PIOR).
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CHAPTER 2 PIN FUNCTIONS
2.1.6 48-pin products
Function Name
Pin Type
P00
7-31-3
P01
8-31-1
P10
8-1-11
P11
P12
7-1-12
P13
8-6-9
P14
8-1-11
P15
P16
8-38-1
P17
8-38-2
P20
4-3-5
P21
P22
4-35-1
P23
4-37-1
P24
4-33-1
P25
P26
P27
P30
7-31-2
P31
P40
7-1-3
P41
8-1-3
I/O I/O I/O
I/O
I/O I/O
(1/2)
After Reset Release
Alternate Function
Function
Input port
TS26Note 2/ EI00/TI00/TxD1
TS27Note 2/EI01/EO01/ TO00/RxD1
Port 0. 2-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P01 can be set to TTL input buffer. Output of P00 can be set to N-ch open-drain output (VDD tolerance).
Input port
Analog function Input port
EI10/EO10/SCK00/SCL00/ (TI07)/(TO07)
EI11/EO11/SI00/RxD0/ TOOLRxD/SDA00/(TI06)/ (TO06)
EI12/EO12/SO00/TxD0/ TOOLTxD/(TI05)/(TO05)
IVREF1/EO13/TxD2/SO20/ (SDAA0)/(TI04)/(TO04)
VCOUT1/EO14/RxD2/ SI20/SDA20/(SCLA0)/ (TI03)/(TO03)
Port 1. 8-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P10, P11, and P13 to P17 can be set to TTL input buffer. Output of P10 to P15 and P17 can be set to N-ch open-drain output (VDD tolerance). P16 and P17 can be set as output current control port pins. P13 can be set for the analog pin functionNote 1.
EO15/PCLBUZ1/SCK20/ SCL20/(TI02)/(TO02)
EO16/CCD00/TI01/TO01/ INTP5/(RxD0)
EO17/CCD01/TI02/TO02/ (TxD0)
Analog function ANI0/AVREFP/EI20
ANI1/AVREFM/EI21
ANI2/ANO0/TS20Note 2/ EI22
Port 2. 8-bit I/O port. Input or output can be specified in 1-bit units. P20 to P27 can be set for the analog pin functionsNote 1.
ANI3/ANO1/IVREF0/ TS21Note 2/EI23
ANI4/TS22Note 2
ANI5/TS23Note 2
ANI6/TS24Note 2
ANI7/TS25Note 2
Input port
VCOUT0/TSCAP/EI30/ INTP3/RTC1HZ/SCK11/ SCL11
TS01/EI31/TI03/TO03/ INTP4/(PCLBUZ0)
Port 3. 2-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port.
Input port
TOOL0 RxDA1/TI07/TO07
Port 4. 2-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P41 can be set to TTL input buffer.
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(2/2)
Function Name
Pin Type
I/O
After Reset Release
Alternate Function
Function
P50
7-39-1
I/O Input port
TS00/EI50/EO50/CCD03/ Port 5.
INTP1/SI11/SDA11
2-bit I/O port.
P51
7-38-1
Output of P50 can be set to N-ch open-drain output
EI51/EO51/CCD02/INTP2/ (VDD tolerance).
SO11
Input or output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by
a software setting at input port.
P50 and P51 can be set as output current control
port pins.
P60
12-38-3
I/O Input port
EO60/CCD04/SCLA0
Port 6.
4-bit I/O port.
P61
EO61/CCD05/SDAA0
Input or output can be specified in 1-bit units.
P62
12-38-2
CCD06/SCLA1
The outputs of P60 to P63 are N-ch open-drain (6-V tolerance).
P63
CCD07/SDAA1
P60 to P63 can be set as output current control port
pins.
P70
7-31-2
I/O Input port
TS02/RIN0/KR0/SCK21/ Port 7.
SCL21
6-bit I/O port.
P71
8-31-2
TS03/KR1/SI21/SDA21/ RxDA0
Input of P71 can be set to TTL input buffer. Output of P71, P72, and P74 can be set to N-ch open-drain output (VDD tolerance).
P72
7-31-3
P73
7-31-2
TS04/KR2/SO21/TxDA0 TS05/KR3/SO01
Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port.
P74
7-31-3
TS06/KR4/INTP8/SI01/ SDA01
P75
7-31-2
TS07/KR5/INTP9/SCK01/ SCL01
P120
P121 P122 P123 P124
7-9-6 7-2-1 2-2-1
I/O Input
Analog function ANI19/IVCMP1/TxDA1/ EI120
Input port
X1/VBAT/EI121
X2/EXCLK/EI122
XT1
XT2/EXCLKS
Port 12. 3-bit I/O port and 2-bit input-only port. For P120 to P122, input or output can be specified in 1-bit units. For P120 to P122, use of an on-chip pull-up resistor can be specified by a software setting at input port. Output of P120 can be set to N-ch open-drain output (VDD tolerance). P120 can be set for the analog pin functionNote 1.
P130 P137
1-1-1 2-1-3
Output Output port Input Input port
-- EI137/INTP0
Port 13. 1-bit output-only port and 1-bit input-only port.
P140 P146 P147
7-1-3 7-9-5
I/O Input port
PCLBUZ0/INTP6
--
Analog function ANI18/IVCMP0/EI147
Port 14. 3-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P147 can be set for the analog pin functionNote 1.
RESET
Note 1. Note 2.
2-1-1
Input --
--
Input-only pin for the external reset signal. When an external reset signal is not in use, connect this pin to VDD, either directly or via a resistor.
Digital or analog for each pin can be selected with the port mode control A register x (PMCAx) (can be set in 1-bit unit). These functions are not present in products with 128 or fewer Kbytes of code flash memory.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4 - 10 Format of Peripheral I/O Redirection Register (PIOR).
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2.1.7 52-pin products
Function Name
Pin Type
P00
7-31-3
P01
8-31-1
P02
7-33-4
P03
8-33-3
P10
8-1-11
P11
P12
7-1-12
P13
8-6-9
P14
8-1-11
P15
P16
8-38-1
P17
8-38-2
P20
4-3-5
P21
P22
4-35-1
P23
4-37-1
P24
4-33-1
P25
P26
P27
P30
7-31-2
P31
P40
7-1-3
P41
8-1-3
I/O I/O I/O
I/O
I/O I/O
(1/3)
After Reset Release
Alternate Function
Function
Input port
TS26Note 2/EI00/TI00
TS27Note 2/ EI01/EO01/TO00
Analog function ANI17/TS28Note 2/TxD1
ANI16/TS29Note 2/RxD1
Port 0. 4-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P01 and P03 can be set to TTL input buffer. Output of P00, P02, and P03 can be set to N-ch open-drain output (VDD tolerance). P02 and P03 can be set for the analog pin functions Note 1.
Input port
Analog function Input port
EI10/EO10/SCK00/SCL00/ (TI07)/(TO07)
EI11/EO11/SI00/RxD0/ TOOLRxD/SDA00/(TI06)/ (TO06)
EI12/EO12/SO00/TxD0/ TOOLTxD/(TI05)/(TO05)
IVREF1/EO13/TxD2/SO20/ (SDAA0)/(TI04)/(TO04)
VCOUT1/EO14/RxD2/ SI20/SDA20/(SCLA0)/ (TI03)/(TO03)
Port 1. 8-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P10, P11, and P13 to P17 can be set to TTL input buffer. Output of P10 to P15 and P17 can be set to N-ch open-drain output (VDD tolerance). P16 and P17 can be set as output current control port pins. P13 can be set for the analog pin functionNote 1.
EO15/PCLBUZ1/SCK20/ SCL20/(TI02)/(TO02)
EO16/CCD00/TI01/TO01/ INTP5/(RxD0)
EO17/CCD01/TI02/TO02/ (TxD0)
Analog function ANI0/AVREFP/EI20
ANI1/AVREFM/EI21
ANI2/ANO0/TS20Note 2/ EI22
Port 2. 8-bit I/O port. Input or output can be specified in 1-bit units. P20 to P27 can be set for the analog pin functionsNote 1.
ANI3/ANO1/IVREF0/ TS21Note 2/EI23
ANI4/TS22Note 2
ANI5/TS23Note 2
ANI6/TS24Note 2
ANI7/TS25Note 2
Input port
VCOUT0/TSCAP/EI30/ INTP3/RTC1HZ/SCK11/ SCL11
TS01/EI31/TI03/TO03/ INTP4/(PCLBUZ0)
Port 3. 2-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port.
Input port
TOOL0 RxDA1/TI07/TO07
Port 4. 2-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P41 can be set to TTL input buffer.
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Function Name
Pin Type
P50
7-39-1
P51
7-38-1
P60 P61 P62 P63
P70
P71
P72 P73 P74
P75
P76 P77 P120
P121 P122 P123 P124 P130 P137 P140 P146 P147
12-38-3 12-38-2
7-31-2 8-31-2 7-31-3 7-31-2 7-31-3 7-31-2
7-9-6 7-2-1 2-2-1
1-1-1 2-1-3 7-1-3 7-9-5
(2/3)
I/O
After Reset Release
Alternate Function
Function
I/O Input port
TS00/EI50/EO50/CCD03/ INTP1/SI11/SDA11
EI51/EO51/CCD02/INTP2/ SO11
Port 5. 2-bit I/O port. Output of P50 can be set to N-ch open-drain output (VDD tolerance). Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P50 and P51 can be set as output current control port pins.
I/O Input port
EO60/CCD04/SCLA0 EO61/CCD05/SDAA0 CCD06/SCLA1 CCD07/SDAA1
Port 6. 4-bit I/O port. Input or output can be specified in 1-bit units. The outputs of P60 to P63 are N-ch open-drain (6-V tolerance). P60 to P63 can be set as output current control port pins.
I/O Input port
TS02/RIN0/KR0/SCK21/ SCL21
TS03/KR1/SI21/SDA21/ RxDA0
TS04/KR2/SO21/TxDA0
TS05/KR3/SO01
Port 7. 8-bit I/O port. Input of P71 can be set to TTL input buffer. Output of P71, P72, and P74 can be set to N-ch open-drain output (VDD tolerance). Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port.
TS06/KR4/INTP8/SI01/ SDA01
TS07/KR5/INTP9/SCK01/ SCL01
TS08/KR6/INTP10/(RxD2)
TS09/KR7/INTP11/(TxD2)
I/O Input
Analog function ANI19/IVCMP1/TxDA1/ EI120
Input port
X1/VBAT/EI121
X2/EXCLK/EI122
XT1
XT2/EXCLKS
Port 12. 3-bit I/O port and 2-bit input-only port. For P120 to P122, input or output can be specified in 1-bit units. For P120 to P122, use of an on-chip pull-up resistor can be specified by a software setting at input port. Output of P120 can be set to N-ch open-drain output (VDD tolerance). P120 can be set for the analog pin functionNote 1.
Output Output port Input Input port
-- EI137/INTP0
Port 13. 1-bit output-only port and 1-bit input-only port.
I/O Input port
PCLBUZ0/INTP6
--
Analog function ANI18/IVCMP0/EI147
Port 14. 3-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P147 can be set for the analog pin functionNote 1.
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(3/3)
Function Name
Pin Type
I/O
After Reset Release
Alternate Function
Function
RESET
Note 1. Note 2.
2-1-1
Input --
--
Input-only pin for the external reset signal. When an external reset signal is not in use, connect this pin to VDD, either directly or via a resistor.
Digital or analog for each pin can be selected with the port mode control A register x (PMCAx) (can be set in 1-bit unit). These functions are not present in products with 128 or fewer Kbytes of code flash memory.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4 - 10 Format of Peripheral I/O Redirection Register (PIOR).
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CHAPTER 2 PIN FUNCTIONS
2.1.8 64-pin products
Function Name
Pin Type
P00
7-31-3
P01
8-31-1
P02
7-33-4
P03
8-33-3
P04
8-1-10
P05
7-31-2
P06
P10
8-1-11
P11
P12
7-1-12
P13
8-6-9
P14
8-1-11
P15
P16
8-38-1
P17
8-38-2
P20
4-3-5
P21
P22
4-35-1
P23
4-37-1
P24
4-33-1
P25
P26
P27
P30
7-31-2
P31
I/O I/O I/O
I/O I/O
(1/3)
After Reset Release
Alternate Function
Function
Input port
TS26Note 2/EI00/TI00
TS27Note 2/ EI01/EO01/TO00
Analog function ANI17/TS28Note 2/ SO10/TxD1
ANI16/TS29Note 2/ SI10/RxD1/SDA10
Input port
SCK10/SCL10
Port 0. 7-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P01, P03, and P04 can be set to TTL input buffer. Output of P00 and P02 to P04 can be set to N-ch open-drain output (EVDD tolerance). P02 and P03 can be set for the analog pin functions Note 1.
TS10/TI05/TO05
TS11/TI06/TO06/CLKA0
Input port Analog function
EI10/EO10/SCK00/SCL00/ (TI07)/(TO07)
EI11/EO11/SI00/RxD0/ TOOLRxD/SDA00/(TI06)/ (TO06)
EI12/EO12/SO00/TxD0/ TOOLTxD/ (INTP5)/ (TI05)/(TO05)
IVREF1/EO13/TxD2/SO20/ (SDAA0)/(TI04)/(TO04)
Port 1. 8-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P10, P11, and P13 to P17 can be set to TTL input buffer. Output of P10 to P15 and P17 can be set to N-ch open-drain output (EVDD tolerance). P16 and P17 can be set as output current control port pins. P13 can be set for the analog pin functionNote 1.
Input port
VCOUT1/EO14/RxD2/ SI20/SDA20/(SCLA0)/ (TI03)/(TO03)
EO15/SCK20/SCL20/ (TI02)/(TO02)
EO16/CCD00/TI01/TO01/ INTP5/(SI00)/(RxD0)
EO17/CCD01/TI02/TO02/ (SO00)/(TxD0)
Analog function ANI0/AVREFP/EI20
ANI1/AVREFM/EI21
ANI2/ANO0/TS20Note 2/ EI22
Port 2. 8-bit I/O port. Input or output can be specified in 1-bit units. P20 to P27 can be set for the analog pin functionsNote 1.
ANI3/ANO1/IVREF0/ TS21Note 2/EI23
ANI4/TS22Note 2
ANI5/TS23Note 2
ANI6/TS24Note 2
ANI7/TS25Note 2
Input port
VCOUT0/TSCAP/EI30/ INTP3/RTC1HZ/SCK11/ SCL11
TS01/EI31/TI03/TO03/ INTP4/(PCLBUZ0)
Port 3. 2-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port.
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Function Name
Pin Type
P40
7-1-3
P41
8-1-3
P42
7-1-11
P43
8-1-10
P50
P51
P52 P53 P54 P55 P60 P61 P62 P63
P70
P71
P72 P73 P74
P75
P76 P77 P120 P121 P122 P123 P124
7-39-1 7-38-1 7-1-11 8-1-10
12-38-3 12-38-2
7-31-2 8-31-2 7-31-3 7-31-2 7-31-3 7-31-2
7-9-6 7-2-1 2-2-1
P130 P137
1-1-1 2-1-3
(2/3)
I/O
After Reset Release
Alternate Function
Function
I/O Input port
TOOL0 RxDA1/TI07/TO07 TxDA1/TI04/TO04 CLKA1
Port 4. 4-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P41 and P43Note 2 can be set to TTL input buffer. Output of P42 and P43Note 2 can be set to N-ch open-drain output (EVDD tolerance).
I/O Input port
TS00/EI50/EO50/CCD03/ INTP1/SI11/SDA11
EI51/EO51/CCD02/INTP2/ SO11
(INTP10)
(INTP11)
--
(PCLBUZ1)/(SCK00)
Port 5. 6-bit I/O port. Input of P53Note 2, P54Note 2, and P55 can be set to TTL input buffer. Output of P50, P52 to 54Note 2, and P55 can be set to N-ch open-drain output (EVDD tolerance). Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P50 and P51 can be set as output current control port pins.
I/O Input port
EO60/CCD04/SCLA0 EO61/CCD05/SDAA0 CCD06/SCLA1 CCD07/SDAA1
Port 6. 4-bit I/O port. Input or output can be specified in 1-bit units. The outputs of P60 to P63 are N-ch open-drain (6-V tolerance). P60 to P63 can be set as output current control port pins.
I/O Input port
TS02/RIN0/KR0/SCK21/ SCL21
TS03/KR1/SI21/SDA21/ RxDA0
TS04/KR2/SO21/TxDA0
TS05/KR3/SO01
Port 7. 8-bit I/O port. Input of P71 can be set to TTL input buffer. Output of P71, P72, and P74 can be set to N-ch open-drain output (EVDD tolerance). Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port.
TS06/KR4/INTP8/SI01/ SDA01
TS07/KR5/INTP9/SCK01/ SCL01
TS08/KR6/INTP10/(RxD2)
TS09/KR7/INTP11/(TxD2)
I/O Input
Analog function ANI19/IVCMP1/EI120
Input port
X1/VBAT/EI121
X2/EXCLK/EI122
XT1
XT2/EXCLKS
Output Output port Input Input port
-- EI137/INTP0
Port 12. 3-bit I/O port and 2-bit input-only port. For P120 to P122, input or output can be specified in 1-bit units. For P120 to P122, use of an on-chip pull-up resistor can be specified by a software setting at input port. Output of P120 can be set to N-ch open-drain output (EVDD tolerance). P120 can be set for the analog pin functionNote 1.
Port 13. 1-bit output-only port and 1-bit input-only port.
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(3/3)
Function Name
Pin Type
I/O
After Reset Release
Alternate Function
Function
P140 P141 P146 P147
7-1-3 7-9-5
I/O Input port
PCLBUZ0/INTP6
PCLBUZ1/INTP7
--
Analog function ANI18/IVCMP0/EI147
Port 14. 4-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P147 can be set for the analog pin functionNote 1.
RESET
Note 1. Note 2.
2-1-1
Input --
--
Input-only pin for the external reset signal. When an external reset signal is not in use, connect this pin to VDD, either directly or via a resistor.
Digital or analog for each pin can be selected with the port mode control A register x (PMCAx) (can be set in 1-bit unit). These functions are not present in products with 128 or fewer Kbytes of code flash memory.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4 - 10 Format of Peripheral I/O Redirection Register (PIOR).
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2.1.9 80-pin products
Function Name
Pin Type
P00
7-31-3
P01
8-31-1
P02
7-33-4
P03
8-33-3
P04
8-1-10
P05
7-31-2
P06
P10
8-1-11
P11
P12
7-1-12
P13
8-6-9
P14
8-1-11
P15
P16
8-38-1
P17
8-38-2
P20
4-3-5
P21
P22
4-35-1
P23
4-37-1
P24
4-33-1
P25
P26
P27
P30
7-31-2
P31
I/O I/O I/O
I/O I/O
(1/3)
After Reset Release
Alternate Function
Function
Input port
TS26/EI00/TI00
TS27/EI01/EO01/TO00
Analog function ANI17/TS28/SO10/TxD1
ANI16/TS29/SI10/RxD1/ SDA10
Input port
SCK10/SCL10
TS10/TI05/TO05
TS11/TI06/TO06/CLKA0
Port 0. 7-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P01, P03, and P04 can be set to TTL input buffer. Output of P00 and P02 to P04 can be set to N-ch open-drain output (EVDD tolerance). P02 and P03 can be set for the analog pin functionsNote .
Input port Analog function
EI10/EO10/SCK00/SCL00/ (TI07)/(TO07)
EI11/EO11/SI00/RxD0/ TOOLRxD/SDA00/(TI06)/ (TO06)
EI12/EO12/SO00/TxD0/ TOOLTxD/(INTP5)/(TI05)/ (TO05)
IVREF1/EO13/TxD2/SO20/ (SDAA0)/(TI04)/(TO04)
Port 1. 8-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P10, P11, and P13 to P17 can be set to TTL input buffer. Output of P10 to P15 and P17 can be set to N-ch open-drain output (EVDD tolerance). P16 and P17 can be set as output current control port pins. P13 can be set for the analog pin functionNote .
Input port
VCOUT1/EO14/RxD2/ SI20/SDA20/(SCLA0)/ (TI03)/(TO03)
EO15/SCK20/SCL20/ (TI02)/(TO02)
EO16/CCD00/TI01/TO01/ INTP5/(SI00)/(RxD0)
EO17/CCD01/TI02/TO02/ (SO00)/(TxD0)
Analog function
ANI0/AVREFP/EI20 ANI1/AVREFM/EI21 ANI2/ANO0/TS20/EI22 ANI3/ANO1/IVREF0/TS21/ EI23
Port 2. 8-bit I/O port. Input or output can be specified in 1-bit units. P20 to P27 can be set for the analog pin functionsNote .
ANI4/TS22
ANI5/TS23
ANI6/TS24
ANI7/TS25
Input port
VCOUT0/TSCAP/EI30/ INTP3/RTC1HZ/SCK11/ SCL11
TS01/EI31/TI03/TO03/ INTP4/(PCLBUZ0)
Port 3. 2-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port.
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Function Name
Pin Type
P40
7-1-3
P41
8-1-3
P42
7-1-11
P43
8-1-10
P44
P45
7-1-11
P50
7-39-1
P51
7-38-1
P52
7-1-11
P53
8-1-10
P54
P55
P60
12-38-3
P61
P62
12-38-2
P63
P64
7-31-2
P65
P66
P67
P70
7-31-2
P71
8-31-2
P72 P73 P74 P75 P76 P77 P100
7-31-3 7-31-2 7-31-3 7-31-2
7-3-3
P110 P111
7-1-3
I/O I/O I/O I/O
I/O
I/O I/O
(2/3)
After Reset Release
Alternate Function
Function
Input port
TOOL0 RxDA1/TI07/TO07 TxDA1/TI04/TO04 SCK01/SCL01/CLKA1 SI01/SDA01 SO01
Port 4. 6-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P41, P43, and P44 can be set to TTL input buffer. Output of P42 to P45 can be set to N-ch open-drain output (EVDD tolerance).
Input port
TS00/EI50/EO50/CCD03/ INTP1/SI11/SDA11
EI51/EO51/CCD02/INTP2/ SO11
SO31
SI31/SDA31
SCK31/SCL31
Port 5. 6-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P53 to P55 can be set to TTL input buffer. Output of P50 and P52 to P55 can be set to N-ch open-drain output (EVDD tolerance). P50 and P51 can be set as output current control port pins.
(PCLBUZ1)/(SCK00)
Input port
EO60/CCD04/SCLA0 EO61/CCD05/SDAA0 CCD06/SCLA1 CCD07/SDAA1 TS12/TI10/TO10 TS13/TI11/TO11
Port 6. 8-bit I/O port. Input or output can be specified in 1-bit units. The outputs of P60 to P63 are N-ch open-drain (6-V tolerance). For P64 to P67, use of an on-chip pull-up resistor can be specified by a software setting at input port. P60 to P63 can be set as output current control port pins.
TS14/TI12/TO12
TS15/TI13/TO13
Input port
TS02/RIN0/KR0/SCK21/ SCL21
TS03/KR1/SI21/SDA21/ RxDA0
TS04/KR2/SO21/TxDA0
TS05/KR3
Port 7. 8-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P71 can be set to TTL input buffer. Output of P71, P72, and P74 can be set to N-ch open-drain output (EVDD tolerance).
TS06/KR4/INTP8
TS07/KR5/INTP9
TS08/KR6/INTP10/(RxD2)
TS09/KR7/INTP11/(TxD2)
Analog function ANI20
Port 10. 1-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P100 can be set for the analog pin functionNote .
Input port
(INTP10) (INTP11)
Port 11. 2-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port.
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(3/3)
Function Name
Pin Type
I/O
After Reset Release
Alternate Function
Function
P120 P121 P122 P123 P124
7-9-6 7-2-1
2-2-1
I/O Input
Analog function ANI19/IVCMP1/EI120
Input port
X1/VBAT/EI121
X2/EXCLK/EI122
XT1
XT2/EXCLKS
Port 12. 3-bit I/O port and 2-bit input-only port. For P120 to P122, input or output can be specified in 1-bit units. For P120 to P122, use of an on-chip pull-up resistor can be specified by a software setting at input port. Output of P120 can be set to N-ch open-drain output (EVDD tolerance). P120 can be set for the analog pin functionNote .
P130 P137
1-1-1 2-1-3
Output Output port Input Input port
-- EI137/INTP0
Port 13. 1-bit output-only port and 1-bit input-only port.
P140 P141 P142 P143 P144 P146 P147
7-1-3
8-1-10
7-1-11 7-1-3 7-9-5
I/O Input port
PCLBUZ0/INTP6
PCLBUZ1/INTP7
SCK30/SCL30
SI30/RxD3/SDA30
SO30/TxD3
--
Analog function ANI18/IVCMP0/EI147
Port 14. 7-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P142 and P143 can be set to TTL input buffer. Output of P142 to P144 can be set to N-ch opendrain output (EVDD tolerance). P147 can be set for the analog pin functionNote .
P150 P151 P152 P153
4-33-1
I/O Analog function ANI8/TS30 ANI9/TS31 ANI10/TS32 ANI11/TS33
Port 15. 4-bit I/O port. Input or output can be specified in 1-bit units. P150 to P157 can be set for the analog pin functionsNote .
RESET Note
2-1-1
Input --
--
Input-only pin for the external reset signal. When an external reset signal is not in use, connect this pin to VDD, either directly or via a resistor.
Digital or analog for each pin can be selected with the port mode control A register x (PMCAx) (can be set in 1-bit unit).
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4 - 10 Format of Peripheral I/O Redirection Register (PIOR).
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2.1.10 100-pin products
Function Name
Pin Type
P00
7-31-3
P01
8-31-1
P02
7-33-4
P03
8-33-3
P04
8-1-10
P05
7-31-2
P06
P10
8-1-11
P11
P12
7-1-12
P13
8-6-9
P14
8-1-11
P15
P16
8-38-1
P17
8-38-2
P20
4-3-5
P21
P22
4-35-1
P23
4-37-1
P24
4-33-1
P25
P26
P27
P30
7-31-2
P31
I/O I/O I/O
I/O I/O
(1/4)
After Reset Release
Alternate Function
Function
Input port
TS26/EI00/TI00
TS27/EI01/EO01/TO00
Analog function ANI17/TS28/SO10/TxD1
ANI16/TS29/SI10/RxD1/ SDA10
Input port
SCK10/SCL10
TS10
TS11
Port 0. 7-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P01, P03, and P04 can be set to TTL input buffer. Output of P00 and P02 to P04 can be set to N-ch open-drain output (EVDD tolerance). P02 and P03 can be set for the analog pin functionsNote .
Input port Analog function
EI10/EO10/SCK00/SCL00/ (TI07)/(TO07)
EI11/EO11/SI00/RxD0/ TOOLRxD/SDA00/(TI06)/ (TO06)
EI12/EO12/SO00/TxD0/ TOOLTxD/(INTP5)/(TI05)/ (TO05)
IVREF1/EO13/TxD2/SO20/ (SDAA0)/(TI04)/(TO04)
Port 1. 8-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P10, P11, and P13 to P17 can be set to TTL input buffer. Output of P10 to P15 and P17 can be set to N-ch open-drain output (EVDD tolerance). P16 and P17 can be set as output current control port pins. P13 can be set for the analog pin functionNote .
Input port
VCOUT1/EO14/RxD2/ SI20/SDA20/(SCLA0)/ (TI03)/(TO03)
EO15/SCK20/SCL20/ (TI02)/(TO02)
EO16/CCD00/TI01/TO01/ INTP5/(SI00)/(RxD0)
EO17/CCD01/TI02/TO02/ (SO00)/(TxD0)
Analog function
ANI0/AVREFP/EI20 ANI1/AVREFM/EI21 ANI2/ANO0/TS20/EI22 ANI3/ANO1/IVREF0/TS21/ EI23
Port 2. 8-bit I/O port. Input or output can be specified in 1-bit units. P20 to P27 can be set for the analog pin functionsNote .
ANI4/TS22
ANI5/TS23
ANI6/TS24
ANI7/TS25
Input port
VCOUT0/TSCAP/EI30/ INTP3/RTC1HZ/SCK11/ SCL11
TS01/EI31/TI03/TO03/ INTP4/(PCLBUZ0)
Port 3. 2-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port.
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Function Name
Pin Type
P40
7-1-3
P41
8-1-3
P42
7-1-11
P43
8-1-10
P44
P45
7-1-11
P46
7-1-3
P47
P50
7-39-1
P51
7-38-1
P52
7-1-11
P53
8-1-10
P54
P55
P56
7-1-3
P57
I/O I/O
I/O
After Reset Release
Input port
Input port
(2/4)
Alternate Function
Function
TOOL0 RxDA1 TxDA1/TI04/TO04 SCK01/SCL01/CLKA1 SI01/SDA01 SO01
Port 4. 8-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P41, P43, and P44 can be set to TTL input buffer. Output of P42 to P45 can be set to N-ch open-drain output (EVDD tolerance).
INTP1/TI05/TO05
INTP2
TS00/EI50/EO50/CCD03/ SI11/SDA11 EI51/EO51/CCD02/SO11 SO31 SI31/SDA31 SCK31/SCL31 (PCLBUZ1)/(SCK00)
Port 5. 8-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P53 to P55 can be set to TTL input buffer. Output of P50 and P52 to P55 can be set to N-ch open-drain output (EVDD tolerance). P50 and P51 can be set as output current control port pins.
(INTP1)
(INTP3)
P60
12-38-3
I/O Input port
EO60/CCD04/SCLA0
Port 6.
8-bit I/O port.
P61
EO61/CCD05/SDAA0
Input or output can be specified in 1-bit units.
P62
12-38-2
CCD06/SCLA1
The outputs of P60 to P63 are N-ch open-drain (6-V tolerance).
P63
CCD07/SDAA1
For P64 to P67, use of an on-chip pull-up resistor
P64
7-31-2
TS12/TI10/TO10
can be specified by a software setting at input port. P60 to P63 can be set as output current control port
P65
TS13/TI11/TO11
pins.
P66
TS14/TI12/TO12
P67
TS15/TI13/TO13
P70
7-31-2
I/O Input port
TS02/RIN0/KR0/SCK21/ Port 7.
SCL21
8-bit I/O port.
P71
8-31-2
TS03/KR1/SI21/SDA21
Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by
P72
7-31-3
P73
7-31-2
TS04/KR2/SO21 TS05/KR3
a software setting at input port. Input of P71 can be set to TTL input buffer. Output of P71, P72, and P74 can be set to N-ch
P74
7-31-3
TS06/KR4/INTP8
open-drain output (EVDD tolerance).
P75
7-31-2
TS07/KR5/INTP9
P76
TS08/KR6/INTP10/(RxD2)
P77
TS09/KR7/INTP11/(TxD2)
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Function Name
Pin Type
P80
8-1-10
P81
P82
7-1-11
P83
P84
8-1-3
P85
7-1-3
P86
P87
P100
7-3-3
P101
7-1-3
P102
P110 P111
7-1-3
P120 P121 P122 P123 P124
7-9-6 7-2-1
2-2-1
P130 P137 P140 P141 P142 P143 P144 P145 P146 P147 P150 P151 P152 P153 P154 P155 P156
1-1-1 2-1-3 7-1-3 8-1-10 7-1-11 7-1-3 7-9-5 4-33-1
4-3-5
I/O I/O
I/O
After Reset Release
Alternate Function
Input port
(SCK10)/(SCL10)
(SI10)/(RxD1)/(SDA10)
(SO10)/(TxD1)
TxDA0
RxDA0/(INTP6)
CLKA0/(INTP7)
(INTP8)
(INTP9)
Analog function ANI20
Input port
--
TI06/TO06
I/O Input port
(INTP10) (INTP11)
I/O Input
Analog function ANI19/IVCMP1/EI120
Input port
X1/VBAT/EI121
X2/EXCLK/EI122
XT1
XT2/EXCLKS
Output Output port
--
Input Input port
EI137/INTP0
I/O Input port
PCLBUZ0/INTP6
PCLBUZ1/INTP7
SCK30/SCL30
SI30/RxD3/SDA30
SO30/TxD3
TI07/TO07
(INTP4)
Analog function ANI18/IVCMP0/EI147
I/O Analog function ANI8/TS30
ANI9/TS31
ANI10/TS32
ANI11/TS33
ANI12/TS34
ANI13/TS35
ANI14
(3/4)
Function
Port 8. 8-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P80, P81, and P84 can be set to TTL input buffer. Output of P80 to P83 can be set to N-ch open-drain output (EVDD tolerance).
Port 10. 3-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P100 can be set for the analog pin functionNote .
Port 11. 2-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port.
Port 12. 3-bit I/O port and 2-bit input-only port. For P120 to P122, input or output can be specified in 1-bit units. For P120 to P122, use of an on-chip pull-up resistor can be specified by a software setting at input port. Output of P120 can be set to N-ch open-drain output (EVDD tolerance). P120 can be set for the analog pin functionNote .
Port 13. 1-bit output-only port and 1-bit input-only port.
Port 14. 8-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P142 and P143 can be set to TTL input buffer. Output of P142 to P144 can be set to N-ch opendrain output (EVDD tolerance). P147 can be set for the analog pin functionNote .
Port 15. 7-bit I/O port. Input or output can be specified in 1-bit units. P150 to P156 can be set for the analog pin functionsNote .
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(4/4)
Function Name
Pin Type
I/O
After Reset Release
Alternate Function
Function
RESET Note
2-1-1
Input --
--
Input-only pin for the external reset signal. When an external reset signal is not in use, connect this pin to VDD, either directly or via a resistor.
Digital or analog for each pin can be selected with the port mode control A register x (PMCAx) (can be set in 1-bit unit).
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4 - 10 Format of Peripheral I/O Redirection Register (PIOR).
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CHAPTER 2 PIN FUNCTIONS
2.1.11 128-pin products
Function Name
Pin Type
P00
7-31-3
P01
8-31-1
P02
7-33-4
P03
8-33-3
P04
8-1-10
P05
7-31-2
P06
P07
7-1-3
P10
8-1-11
P11
P12
7-1-12
P13
8-6-9
P14
8-1-11
P15
P16
8-38-1
P17
8-38-2
P20
4-3-5
P21
P22
4-35-1
P23
4-37-1
P24
4-33-1
P25
P26
P27
I/O I/O I/O
I/O
(1/4)
After Reset Release
Alternate Function
Function
Input port
TS26/EI00/TI00
TS27/EI01/EO01/TO00
Analog function ANI17/TS28/SO10/TxD1
ANI16/TS29/SI10/RxD1/ SDA10
Input port
SCK10/SCL10
TS10
TS11
Port 0. 8-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P01, P03, and P04 can be set to TTL input buffer. Output of P00 and P02 to P04 can be set to N-ch open-drain output (EVDD tolerance). P02 and P03 can be set for the analog pin functionsNote .
--
Input port Analog function
EI10/EO10/SCK00/SCL00/ (TI07)/(TO07)
EI11/EO11/SI00/RxD0/ TOOLRxD/ SDA00/(TI06)/(TO06)
EI12/EO12/SO00/TxD0/ TOOLTxD/ (INTP5)/(TI05)/(TO05)
IVREF1/EO13/TxD2/SO20/ (SDAA0)/(TI04)/(TO04)
Port 1. 8-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P10, P11, and P13 to P17 can be set to TTL input buffer. Output of P10 to P15 and P17 can be set to N-ch open-drain output (EVDD tolerance). P16 and P17 can be set as output current control port pins. P13 can be set for the analog pin functionNote .
Input port
VCOUT1/EO14/RxD2/ SI20/SDA20/(SCLA0)/ (TI03)/(TO03)
EO15/SCK20/SCL20/ (TI02)/(TO02)
EO16/CCD00/TI01/TO01/ INTP5/(SI00)/(RxD0)
EO17/CCD01/TI02/TO02/ (SO00)/(TxD0)
Analog function
ANI0/AVREFP/EI20 ANI1/AVREFM/EI21 ANI2/ANO0/TS20/EI22 ANI3/ANO1/IVREF0/TS21/ EI23
Port 2. 8-bit I/O port. Input or output can be specified in 1-bit units. P20 to P27 can be set for the analog pin functionsNote .
ANI4/TS22
ANI5/TS23
ANI6/TS24
ANI7/TS25
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Function Name
Pin Type
P30
7-31-2
P31
P32
7-1-3
P33
8-1-3
P34
7-1-11
P35
7-3-3
P36
P37
P40
7-1-3
P41
8-1-3
P42
7-1-11
P43
8-1-10
P44
P45
7-1-11
P46
7-1-3
P47
P50
7-39-1
P51
7-38-1
P52
7-1-11
P53
8-1-10
P54
P55
P56
7-1-3
P57
P60
12-38-3
P61
P62
12-38-2
P63
P64
7-31-2
P65
P66
P67
I/O I/O
I/O I/O I/O
After Reset Release
Alternate Function
Input port
VCOUT0/TSCAP/EI30/ INTP3/RTC1HZ
TS01/EI31/TI03/TO03/ INTP4/(PCLBUZ0)
CLKA1
RxDA1
TxDA1
Analog function ANI23
ANI22
ANI21
Input port
TOOL0
--
TI04/TO04
SCK01/SCL01
SI01/SDA01
SO01
INTP1/TI05/TO05
INTP2
Input port
TS00/EI50/EO50/CCD03
EI51/EO51/CCD02
SO31
SI31/SDA31
SCK31/SCL31
(PCLBUZ1)/(SCK00)
(INTP1)
(INTP3)
Input port
EO60/CCD04/SCLA0
EO61/CCD05/SDAA0
CCD06/SCLA1
CCD07/SDAA1
TS12/TI10/TO10
TS13/TI11/TO11
TS14/TI12/TO12
TS15/TI13/TO13
(2/4)
Function
Port 3. 8-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P33 can be set to TTL input buffer. Output of P34 can be set to N-ch open-drain output (EVDD tolerance). P35 to P37 can be set for the analog pin functionsNote .
Port 4. 8-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P41, P43, and P44 can be set to TTL input buffer. Output of P42 to P45 can be set to N-ch open-drain output (EVDD tolerance).
Port 5. 8-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P53 to P55 can be set to TTL input buffer. Output of P50 and P52 to P55 can be set to N-ch open-drain output (EVDD tolerance). P50 and P51 can be set as output current control port pins.
Port 6. 8-bit I/O port. Input or output can be specified in 1-bit units. The outputs of P60 to P63 are N-ch open-drain (6-V tolerance). For P64 to P67, use of an on-chip pull-up resistor can be specified by a software setting at input port. P60 to P63 can be set as output current control port pins.
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Function Name
Pin Type
P70
7-31-2
P71 P72 P73 P74 P75 P76 P77 P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P93 P94 P95 P96 P97 P100 P101 P102 P103 P104 P105 P106 P110 P111 P112 P113 P114 P115 P116 P117
8-31-2 7-31-3 7-31-2 7-31-3 7-31-2
8-1-10 7-1-11 8-1-3 7-1-3
7-1-3
7-1-11 7-1-3 7-3-3 7-1-3
7-1-3
7-3-3
I/O I/O
I/O I/O I/O I/O
(3/4)
After Reset Release
Alternate Function
Function
Input port
TS02/RIN0/KR0/SCK21/ SCL21 TS03/KR1/SI21/SDA21 TS04/KR2/SO21 TS05/KR3 TS06/KR4/INTP8
Port 7. 8-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P71 can be set to TTL input buffer. Output of P71, P72, and P74 can be set to N-ch open-drain output (EVDD tolerance).
TS07/KR5/INTP9
TS08/KR6/INTP10/(RxD2)
TS09/KR7/INTP11/(TxD2)
Input port
(SCK10)/(SCL10) (SI10)/(RxD1)/(SDA10) (SO10)/(TxD1) TxDA0 RxDA0/(INTP6) CLKA0/(INTP7)
Port 8. 8-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P80, P81, and P84 can be set to TTL input buffer. Output of P80 to P83 can be set to N-ch open-drain output (EVDD tolerance).
(INTP8)
(INTP9)
Input port
--
--
--
--
--
Port 9. 8-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Output of P96 can be set to N-ch open-drain output (EVDD tolerance).
SCK11/SCL11
SI11/SDA11
SO11
Analog function ANI20
Input port
--
TI06/TO06
TI14/TO14
Port 10. 7-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P100 can be set for the analog pin functionNote .
TI15/TO15
TI16/TO16
TI17/TO17
Input port
(INTP10) (INTP11) -- -- --
Port 11. 8-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P115 to P117 can be set for the analog pin functionsNote .
Analog function ANI26
ANI25
ANI24
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(4/4)
Function Name
Pin Type
I/O
After Reset Release
Alternate Function
Function
P120 P121 P122 P123 P124 P125 P126
7-9-6 7-2-1 2-2-1
7-1-3
I/O Input I/O
Analog function ANI19/IVCMP1/EI120
Input port
X1/VBAT/EI121
X2/EXCLK/EI122
XT1
XT2/EXCLKS
--
--
Port 12. 6-bit I/O port and 2-bit input-only port. For P120 to P122 and P125 to P127, input or output can be specified in 1-bit units. For P120 to P122 and P125 to P127, use of an onchip pull-up resistor can be specified by a software setting at input port. Output of P120 can be set to N-ch open-drain output (EVDD tolerance). P120 can be set for the analog pin functionNote .
P127
--
P130 P137
1-1-1 2-1-3
Output Output port Input Input port
-- EI137/INTP0
Port 13. 1-bit output-only port and 1-bit input-only port.
P140 P141 P142 P143 P144 P145 P146
7-1-3
8-1-10
7-1-11 7-1-3
I/O Input port
PCLBUZ0/INTP6 PCLBUZ1/INTP7 SCK30/SCL30 SI30/RxD3/SDA30 SO30/TxD3 TI07/TO07 (INTP4)
Port 14. 8-bit I/O port. Input or output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P142 and P143 can be set to TTL input buffer. Output of P142 to P144 can be set to N-ch opendrain output (EVDD tolerance). P147 can be set for the analog pin functionNote .
P147
7-9-5
Analog function ANI18/IVCMP0/EI147
P150 P151 P152 P153
4-33-1
I/O Analog function ANI8/TS30 ANI9/TS31 ANI10/TS32 ANI11/TS33
Port 15. 7-bit I/O port. Input or output can be specified in 1-bit units. P150 to P156 can be set for the analog pin functionsNote .
P154
ANI12/TS34
P155
ANI13/TS35
P156
4-3-5
ANI14
RESET Note
2-1-1
Input --
--
Input-only pin for the external reset signal. When an external reset signal is not in use, connect this pin to VDD, either directly or via a resistor.
Digital or analog for each pin can be selected with the port mode control A register x (PMCAx) (can be set in 1-bit unit).
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4 - 10 Format of Peripheral I/O Redirection Register (PIOR).
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2.2
Pin Functions other than Port Pin Functions
2.2.1 Functions for each product
Function Name ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 ANI12 ANI13 ANI14 ANI16 ANI17 ANI18 ANI19 ANI20 ANI21 ANI22 ANI23 ANI24 ANI25 ANI26 ANO0 ANO1 IVCMP0 IVCMP1 IVREF0 IVREF1 VCOUT0 VCOUT1 TS00 TS01
128-pin 100-pin
--
--
--
--
--
--
80-pin -- -- -- -- -- -- -- -- --
64-pin -- -- -- -- -- -- -- -- -- -- -- -- -- --
52-pin -- -- -- -- -- -- -- -- -- -- -- -- -- --
48-pin -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
44-pin -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
40-pin -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
36-pin -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
32-pin -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
(1/7)
30-pin -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
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CHAPTER 2 PIN FUNCTIONS
Function Name TS02 TS03 TS04 TS05 TS06 TS07 TS08 TS09 TS10 TS11 TS12 TS13 TS14 TS15 TS20 TS21 TS22 TS23 TS24 TS25 TS26 TS27 TS28 TS29 TS30 TS31 TS32 TS33 TS34 TS35 TSCAP CCD00 CCD01 CCD02 CCD03 CCD04 CCD05 CCD06 CCD07
128-pin 100-pin
80-pin -- --
64-pin -- -- -- --
Note Note Note Note Note Note Note Note Note Note
-- -- -- -- -- --
52-pin -- -- -- -- -- --
Note Note Note Note Note Note Note Note Note Note
-- -- -- -- -- --
48-pin -- -- -- -- -- -- -- --
Note Note Note Note Note Note Note Note
-- -- -- -- -- -- -- --
44-pin -- -- -- -- -- -- -- -- -- --
Note Note Note Note Note Note Note Note
-- -- -- -- -- -- -- --
40-pin -- -- -- -- -- -- -- -- -- --
Note Note Note Note Note
-- Note Note
-- -- -- -- -- -- -- -- --
36-pin -- -- -- -- -- -- -- -- -- -- --
Note Note Note Note
-- -- Note Note -- -- -- -- -- -- -- -- --
32-pin -- -- -- -- -- -- -- -- -- -- -- -- --
Note Note
-- -- -- -- Note Note -- -- -- -- -- -- -- -- --
(2/7)
30-pin -- -- -- -- -- -- -- -- -- -- -- -- -- --
Note Note
-- -- -- -- Note Note -- -- -- -- -- -- -- -- -- --
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CHAPTER 2 PIN FUNCTIONS
Function Name INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTP7 INTP8 INTP9 INTP10 INTP11 KR0 KR1 KR2 KR3 KR4 KR5 KR6 KR7 PCLBUZ0 PCLBUZ1 REGC RTC1HZ RESET RIN0 RxD0 RxD1 RxD2 RxD3 TxD0 TxD1 TxD2 TxD3 RxDA0 RxDA1 TxDA0 TxDA1 CLKA0 CLKA1
128-pin 100-pin
80-pin
64-pin -- --
52-pin -- -- -- -- --
48-pin -- -- -- -- -- -- -- -- --
44-pin -- -- -- -- -- -- -- -- -- -- -- -- -- --
40-pin -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
36-pin -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
32-pin -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
(3/7)
30-pin -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
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CHAPTER 2 PIN FUNCTIONS
Function Name SCK00 SCK01 SCK10 SCK11 SCK20 SCK21 SCK30 SCK31 SCL00 SCL01 SCL10 SCL11 SCL20 SCL21 SCL30 SCL31 SDA00 SDA01 SDA10 SDA11 SDA20 SDA21 SDA30 SDA31 SI00 SI01 SI10 SI11 SI20 SI21 SI30 SI31 SO00 SO01 SO10 SO11 SO20 SO21 SO30 SO31
128-pin 100-pin
80-pin
64-pin -- -- -- -- -- -- -- -- -- --
52-pin -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
48-pin -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
44-pin -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
40-pin -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
36-pin -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
32-pin -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
(4/7)
30-pin -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
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CHAPTER 2 PIN FUNCTIONS
Function Name SCLA0 SCLA1 SDAA0 SDAA1 TI00 TI01 TI02 TI03 TI04 TI05 TI06 TI07 TI10 TI11 TI12 TI13 TI14 TI15 TI16 TI17 TO00 TO01 TO02 TO03 TO04 TO05 TO06 TO07 TO10 TO11 TO12 TO13 TO14 TO15 TO16 TO17 EI00 EI01 EI10 EI11
128-pin 100-pin
--
--
--
--
--
--
--
--
80-pin -- -- -- -- -- -- -- --
64-pin -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
52-pin () () () -- -- -- -- -- -- -- -- () () () -- -- -- -- -- -- -- --
48-pin () () () -- -- -- -- -- -- -- -- () () () -- -- -- -- -- -- -- --
44-pin () () () -- -- -- -- -- -- -- -- () () () -- -- -- -- -- -- -- --
40-pin -- -- () () () () -- -- -- -- -- -- -- -- () () () () -- -- -- -- -- -- -- --
36-pin -- -- () () () () -- -- -- -- -- -- -- -- () () () () -- -- -- -- -- -- -- --
32-pin -- -- () () () () -- -- -- -- -- -- -- -- () () () () -- -- -- -- -- -- -- --
(5/7)
30-pin -- -- () () () () -- -- -- -- -- -- -- -- () () () () -- -- -- -- -- -- -- --
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CHAPTER 2 PIN FUNCTIONS
Function Name EI12 EI20 EI21 EI22 EI23 EI30 EI31 EI50 EI51 EI120 EI121 EI122 EI137 EI147 EO01 EO10 EO11 EO12 EO13 EO14 EO15 EO16 EO17 EO50 EO51 EO60 EO61 X1 X2 EXCLK XT1 XT2 EXCLKS VDD EVDD0 EVDD1 VBAT AVREFP AVREFM VSS
128-pin
100-pin
80-pin --
64-pin --
52-pin -- --
48-pin -- --
44-pin -- --
40-pin -- --
36-pin -- -- --
32-pin -- -- --
(6/7)
30-pin -- -- --
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CHAPTER 2 PIN FUNCTIONS
Function Name 128-pin 100-pin 80-pin 64-pin 52-pin 48-pin 44-pin
EVSS0
--
--
--
EVSS1
--
--
--
--
--
TOOLRxD
TOOLTxD
TOOL0 Note
Not present in products with 128 or fewer Kbytes of code flash memory.
40-pin -- --
36-pin -- --
32-pin -- --
(7/7)
30-pin -- --
Remark The checked function is available only when the bit corresponding to the function in the peripheral I/O redirection register (PIOR) is set to 1.
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CHAPTER 2 PIN FUNCTIONS
2.2.2 Description of pin functions
(1/2)
Function Name
I/O
Function
ANI0 to ANI14, ANI16 to ANI26 Input Analog voltage inputs of the A/D converter (see Figure 12 - 52 Connections of VDD, AVREFP, and Analog Input Pins)
ANO0, ANO1
Output D/A converter outputs
IVCMP0, IVCMP1
Input Analog voltage inputs of the comparator
IVREF0, IVREF1
Input Reference voltage inputs of the comparator
VCOUT0, VCOUT1
Output Comparator outputs
TS00 to TS15, TS20 to TS35 Output Electrostatic capacitance measurement pins (touch sensor)
TSCAP
Output Pin for connecting a power supply stabilization capacitor for the touch sensor interface. Connect this pin to Vss via a capacitor (10 nF). Also, use a capacitor with good characteristics, since it is used to stabilize internal voltage.
CCD00 to CCD07
Output Output current control port
INTP0 to INTP11
Input External interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified.
KR0 to KR7
Input Key interrupt inputs
PCLBUZ0, PCLBUZ1
Output Clock output/buzzer output
REGC
--
Pin for connecting regulator output stabilization capacitance for internal operation.
Connect this pin to Vss via a capacitor (0.47 to 1 µF).
Also, use a capacitor with good characteristics, since it is used to stabilize internal voltage.
RTC1HZ
Output Realtime clock correction clock (1 Hz) output
RESET
Input This is the active-low system reset input pin. When the external reset pin is not used, connect this pin directly or via a resistor to VDD.
RIN0
Input External pulse signal input pin for the remote control signal reception circuit
RxD0 to RxD3
Input Serial data input pins of serial interfaces UART0, UART1, UART2, and UART3
TxD0 to TxD3
Output Serial data output pins of serial interfaces UART0, UART1, UART2, and UART3
RxDA0, RxDA1
Input Serial data input pins of serial interfaces UARTA0 and UARTA1
TxDA0, TxDA1
Output Serial data output pins of serial interfaces UARTA0 and UARTA1
CLKA0, CLKA1
Output Clock output pins of serial interfaces UARTA0 and UARTA1
SCK00, SCK01, SCK10, SCK11, I/O SCK20, SCK21, SCK30, SCK31
Serial clock I/O pins of serial interfaces CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, and CSI31
SCL00, SCL01, SCL10, SCL11, Output Serial clock output pins of serial interfaces IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, and
SCL20, SCL21, SCL30, SCL31
IIC31
SDA00, SDA01, SDA10, SDA11, I/O SDA20, SDA21, SDA30, SDA31
Serial data I/O pins of serial interfaces IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, and IIC31
SI00, SI01, SI10, SI11, SI20, SI21, SI30, SI31
Input Serial data input pins of serial interfaces CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, and CSI31
SO00, SO01, SO10, SO11, SO20, SO21, SO30, SO31
Output Serial data output pins of serial interfaces CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, and CSI31
SCLA0, SCLA1
I/O Clock I/O pins of serial interfaces IICA0 and IICA1
SDAA0, SDAA1
I/O Serial data I/O pins of serial interfaces IICA0 and IICA1
TI00 to TI07, TI10 to TI17
Input The pins for inputting an external count clock/capture trigger to 16-bit timers 00 to 07 and 10 to 17
TO00 to TO07, TO10 to TO17 Output Timer output pins of 16-bit timers 00 to 07 and 10 to 17
EIxx
Input ELCL input
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CHAPTER 2 PIN FUNCTIONS
Function Name EOxx X1, X2 EXCLK XT1, XT2 EXCLKS VDD
EVDD0, EVDD1 VBAT AVREFP AVREFM VSS
EVSS0, EVSS1 TOOLRxD TOOLTxD TOOL0
(2/2)
I/O
Function
Output ELCL output
--
Resonator connection for main system clock
Input External clock input for main system clock
--
Resonator connection for subsystem clock
Input External clock input for subsystem clock
--
<30-, 32-, 36-, 40-, 44-, 48-, and 52-pin products>
Positive power supply for all pins
<64-, 80-, 100-, and 128-pin products>
Positive power supply for P20 to P27, P121 to P124, P137, P150 to P156, and pins in
use for functions other than port functions
--
Positive power supply for port pins (other than P20 to P27, P121 to P124, P137, and P150 to
P156)
--
Power supply pin for battery backup
Input Positive reference voltage input of the A/D converter
Input Negative reference voltage input of the A/D converter
--
<30-, 32-, 36-, 40-, 44-, 48-, and 52-pin products>
Ground voltage for all pins
<64-, 80-, 100-, and 128-pin products>
Ground voltage for P20 to P27, P121 to P124, P137, P150 to P156, and pins in use for
functions other than port functions
--
Ground voltage for port pins (other than P20 to P27, P121 to P124, P137, and P150 to P156)
Input UART reception pin for the external device connection used during flash memory programming
Output UART transmission pin for the external device connection used during flash memory programming
I/O Data I/O for flash memory programmer or debugger
Caution
The relationship between the voltage on P40/TOOL0 and the operating mode after release from the reset state is as follows.
Table 2 - 2 Relationships between the Voltage on P40/TOOL0 and Operating Mode After Release from the Reset State
P40/TOOL0
Operating Mode
EVDD
Normal operating mode
0 V
Flash memory programming mode
For details, see 33.4 Programming Method.
Remark
Use bypass capacitors (about 0.1 µF) as noise and latch up countermeasures with relatively thick wires at the shortest distance to VDD to VSS, EVDD0 to EVSS0, and EVDD1 to EVSS1 lines.
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CHAPTER 2 PIN FUNCTIONS
2.3
Connection of Unused Pins
Table 2 - 3 shows the connections of unused pins.
Remark
The pins mounted depend on the product. Refer to 1.3 Pin Configuration (Top View) and 2.1 Functions of Port Pins.
Table 2 - 3 Connections of Unused Pins
Pin Name
I/O
Recommended Connection of Unused Pins
P00 to P07
I/O
Input: Independently connect to EVDD0, EVDD1 or EVSS0, EVSS1 via a resistor.
P10 to P17
Output: Leave open.
P20 to P27
Input: Independently connect to VDD or VSS via a resistor. Output: Leave open.
P30 to P37
Input: Independently connect to EVDD0, EVDD1 or EVSS0, EVSS1 via a resistor. Output: Leave open.
P40/TOOL0
Input: Independently connect to EVDD0, EVDD1 or leave open. Output: Leave open.
P41 to P47 P50 to P57
Input: Independently connect to EVDD0, EVDD1 or EVSS0, EVSS1 via a resistor. Output: Leave open.
P60 to P63
Input: Independently connect to EVDD0, EVDD1 or EVSS0, EVSS1 via a resistor. Output: Set the port's output latch to 0 and leave the pins open, or set the port's output latch to 1 and
independently connect the pins to EVDD0 and EVDD1 or EVSS0 and EVSS1 via a resistor.
P64 to P67 P70 to P77
Input: Independently connect to EVDD0, EVDD1 or EVSS0, EVSS1 via a resistor. Output: Leave open.
P80 to P87
P90 to P97
P100 to P106
P110 to P117
P120
P121, P122
Input: Independently connect to VDD or VSS via a resistor. Output: Leave open.
P123, P124
Input
Set the EXCLKS bit in the clock operation mode control register (CMC) to 0, set the XTSTOP bit in the clock operation status control register (CSC) to 1, and leave the pin open-circuit. Alternatively, provide the pin with an independent connection to VDD or VSS via a resistor.
P125 to P127
I/O
Input: Independently connect to EVDD0, EVDD1 or EVSS0, EVSS1 via a resistor. Output: Leave open.
P130
Output Leave open.
P137
Input
Set the PDIDIS137 bit in the port digital input disable register (PDIDIS) to 1, and leave the pin opencircuit. Alternatively, provide the pin with an independent connection to VDD or VSS via a resistor.
P140 to P147
I/O
Input: Independently connect to EVDD0, EVDD1 or EVSS0, EVSS1 via a resistor. Output: Leave open.
P150 to P156
I/O
Input: Independently connect to VDD or VSS via a resistor. Output: Leave open.
RESET
Input
Connect directly or via a resistor to VDD.
REGC
--
Connect to VSS via capacitor (0.47 to 1 µF).
Remark For products that do not have an EVDD0, EVDD1, EVSS0, or EVSS1 pin, read EVDD0 and EVDD1 as VDD, and EVSS0 and EVSS1 as VSS.
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CHAPTER 2 PIN FUNCTIONS
2.4
Block Diagrams of Pins
Figures 2 - 1 to 2 - 33 show the block diagrams of the pins described in 2.1.1 30-pin products to 2.1.11 128-pin products.
Figure 2 - 1 Pin Block Diagram for Pin Type 1-1-1
Internal bus
RD
WRPORT
Output latch (Pmn)
EVDD
P-ch N-ch
Pmn
EVSS
Figure 2 - 2 Pin Block Diagram for Pin Type 2-1-1
RESET
RESET
Figure 2 - 3 Pin Block Diagram for Pin Type 2-1-3
Internal bus
Alternate function RD
WRPDIDIS PDIDIS register (PDIDISmn)
Remark For alternate functions, see 2.1 Functions of Port Pins.
Pmn
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RL78/G23 Figure 2 - 4 Pin Block Diagram for Pin Type 2-2-1
CHAPTER 2 PIN FUNCTIONS
Internal bus
Clock generator
CMC
OSCSELS
RD
Alternate
function
CMC EXCLKS, OSCSELS
RD
Alternate function
P124/XT2/EXCLKS/Alternate function N-ch P-ch
P123/XT1/Alternate function
Remark For alternate functions, see 2.1 Functions of Port Pins.
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RL78/G23 Figure 2 - 5 Pin Block Diagram for Pin Type 4-3-5
Internal bus
WRPMCA
PMCA register (PMCAmn)
RDPORT 1
0 WRPORT
Output latch (Pmn)
WRPM
PM register (PMmn)
WRPMS
PMS register
0: Digital I/O 1: Analog input
1 0
A/D converter
P-ch N-ch
CHAPTER 2 PIN FUNCTIONS
VDD P-ch N-ch
VSS
Pmn
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RL78/G23 Figure 2 - 6 Pin Block Diagram for Pin Type 4-33-1
Internal bus
WRPMCT
PMCT register (PMCTmn)
WRPMCA
PMCTmn
PMCA register (PMCAmn)
RDPORT 1
0 WRPORT
Output latch (Pmn)
WRPM
PM register (PMmn)
0: Digital I/O 1: Analog input
1 0
WRPMS
PMS register
A/D converter
PMCAmn PMCTmn
Touch sensor output data signal
P-ch N-ch
CHAPTER 2 PIN FUNCTIONS
VDD P-ch N-ch
VSS
Pmn
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RL78/G23 Figure 2 - 7 Pin Block Diagram for Pin Type 4-35-1
CHAPTER 2 PIN FUNCTIONS
Internal bus
WRPMCT
PMCT register (PMCTmn)
WRPMCA
PMCTmn
PMCA register (PMCAmn)
RDPORT 1
0 WRPORT
WRPM
Output latch (Pmn)
PM register (PMmn)
WRPMS
0: Digital I/O 1: Analog I/O
1 0
PMS register
D/A converter output
A/D converter
PMCAmn PMCTmn
P-ch N-ch
Touch sensor output data signal
VDD P-ch N-ch
VSS
Pmn
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RL78/G23 Figure 2 - 8 Pin Block Diagram for Pin Type 4-37-1
CHAPTER 2 PIN FUNCTIONS
Internal bus
WRPMCT
PMCT register (PMCTmn)
WRPMCA
PMCTmn
PMCA register (PMCAmn)
RDPORT 1
0 WRPORT
WRPM
Output latch (Pmn)
PM register (PMmn)
WRPMS
0: Digital I/O 1: Analog I/O
1 0
PMS register
Comparator input
D/A converter output
A/D converter
PMCAmn PMCTmn
P-ch N-ch
Touch sensor output data signal
VDD P-ch N-ch
VSS
Pmn
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RL78/G23 Figure 2 - 9 Pin Block Diagram for Pin Type 7-1-3
WRPU
Alternate function
PU register (PUmn)
Internal bus
RDPORT
1 1
WRPORT
0 0
Output latch (Pmn)
WRPMS
WRPM
PMS register
PM register (PMmn)
Alternate function (SAU and UARTA)
Note 1
Alternate function (other than SAU and UARTA) Note 2
Note 1. Note 2.
This excludes the clock output from UARTA. This includes the clock output from UARTA.
Remark 1. For alternate functions, see 2.1 Functions of Port Pins. Remark 2. SAU: Serial array unit
CHAPTER 2 PIN FUNCTIONS
EVDD P-ch
EVDD
P-ch N-ch EVSS
Pmn
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RL78/G23 Figure 2 - 10 Pin Block Diagram for Pin Type 7-1-11
CHAPTER 2 PIN FUNCTIONS
Internal bus
WRPU
Alternate function
PU register (PUmn)
RDPORT
1 1
WRPORT
0 0
Output latch (Pmn)
WRPMS
WRPM WRPOM
PMS register
PM register (PMmn)
POM register (POMmn)
Alternate function (SAU and UARTA)
Note 1
WRPDIDIS
Alternate function (other than SAU and
UARTA) Note 2
PDIDIS register (PDIDISmn)
EVDD P-ch
PDIDISmn
EVDD
P-ch N-ch EVSS
Pmn
Note 1. Note 2.
This excludes the clock output from UARTA. This includes the clock output from UARTA.
Caution
The input buffer is enabled even if the type 7-1-11 pin is operating as an output when the N-ch open-drain output mode is selected by the corresponding bit in the port output mode register (POMx). This may lead to a through current flowing through the type 7-1-11 pin when the voltage level on this pin is intermediate. However, setting the corresponding bit of the given PDIDISx register to 1 prevents the flow of a through current.
Remark 1. For alternate functions, see 2.1 Functions of Port Pins. Remark 2. SAU: Serial array unit
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RL78/G23 Figure 2 - 11 Pin Block Diagram for Pin Type 7-1-12
WRPU
Alternate function
PU register (PUmn)
Internal bus
RDPORT
1 1
WRPORT
0 0
Output latch (Pmn)
WRPMS
WRPM WRPOM
PMS register
PM register (PMmn)
POM register (POMmn)
Alternate function (SAU and UARTA)
Note 1
WRPDIDIS
Alternate function (other than SAU and
UARTA) Note 2
WRPMCE
PDIDIS register (PDIDISmn)
PMCE register (PMCEmn)
CHAPTER 2 PIN FUNCTIONS
EVDD P-ch PDIDISmn
PMCEmn 0
ELCL function 1
EVDD
P-ch N-ch EVSS
Pmn
Note 1. Note 2.
This excludes the clock output from UARTA. This includes the clock output from UARTA.
Caution
The input buffer is enabled even if the type 7-1-12 pin is operating as an output when the N-ch open-drain output mode is selected by the corresponding bit in the port output mode register (POMx). This may lead to a through current flowing through the type 7-1-12 pin when the voltage level on this pin is intermediate. However, setting the corresponding bit of the given PDIDISx register to 1 prevents the flow of a through current.
Remark 1. For alternate functions, see 2.1 Functions of Port Pins. Remark 2. SAU: Serial array unit
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RL78/G23 Figure 2 - 12 Pin Block Diagram for Pin Type 7-2-1
CHAPTER 2 PIN FUNCTIONS
Internal bus
Clock generator
CMC
OSCSEL
RD
Alternate
function
<1> <3>
CMC EXCLK, OSCSEL
RD
Alternate
function
<2> <4>
WRPU
PU register (PUmn)
PMmn
1
<1>
<2>
1
0
0 WRPORT
Output latch (Pmn)
WRPM
PM register (PMmn)
WRPMS PMS register
P122/X2/EXCLK/Alternate function <5>
N-ch P-ch
P121/X1/VBAT/Alternate function <6>
EVDD P-ch
<3>
<5>
<4>
<6>
VDD
P-ch <5> <6>
N-ch
VSS
Internal bus
Internal bus
Remark For alternate functions, see 2.1 Functions of Port Pins.
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RL78/G23 Figure 2 - 13 Pin Block Diagram for Pin Type 7-3-3
WRPU
PU register (PUmn)
WRPMCA
PMCA register (PMCAmn)
Internal bus
RDPORT WRPORT
Alternate function
1 1
0 0
Output latch (Pmn)
WRPMS
WRPM
PMS register
PM register (PMmn)
Alternate function (SAU and UARTA)
Note 1
Alternate function (other than SAU and
UARTA) Note 2
A/D converter
Note 1. Note 2.
This excludes the clock output from UARTA. This includes the clock output from UARTA.
Remark 1. For alternate functions, see 2.1 Functions of Port Pins. Remark 2. SAU: Serial array unit
P-ch N-ch
CHAPTER 2 PIN FUNCTIONS
EVDD P-ch
EVDD
P-ch N-ch EVSS
Pmn
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RL78/G23 Figure 2 - 14 Pin Block Diagram for Pin Type 7-9-5
CHAPTER 2 PIN FUNCTIONS
WRPU
PU register (PUmn)
WRPMCA
PMCA register (PMCAmn)
EVDD P-ch
Internal bus
RDPORT WRPORT
Alternate function
1 1
0 0
Output latch (Pmn)
WRPMS
WRPM
PMS register
PM register (PMmn)
EVDD
P-ch N-ch EVSS
Pmn
Alternate function (SAU and UARTA)
Note 1
Alternate function (other than SAU and
UARTA) Note 2
A/D converter
Note 1. Note 2.
This excludes the clock output from UARTA. This includes the clock output from UARTA.
Remark 1. For alternate functions, see 2.1 Functions of Port Pins. Remark 2. SAU: Serial array unit
Comparator input P-ch N-ch
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RL78/G23 Figure 2 - 15 Pin Block Diagram for Pin Type 7-9-6
CHAPTER 2 PIN FUNCTIONS
WRPU
PU register (PUmn)
WRPMCA
PMCA register (PMCAmn)
PDIDISmn
EVDD P-ch
RDPORT WRPORT
Alternate function
1 1
0 0
Output latch (Pmn)
WRPMS WRPM WRPOM
PMS register
PM register (PMmn)
POM register (POMmn)
EVDD
P-ch N-ch EVSS
Pmn
Alternate function (SAU and UARTA)
Note 1
WRPDIDIS
Alternate function (other than SAU and
UARTA) Note 2
PDIDIS register (PDIDISmn)
Comparator input
A/D converter
P-ch N-ch
Internal bus
Note 1. Note 2.
This excludes the clock output from UARTA. This includes the clock output from UARTA.
Caution
The input buffer is enabled even if the type 7-9-6 pin is operating as an output when the N-ch open-drain output mode is selected by the corresponding bit in the port output mode register (POMx). This may lead to a through current flowing through the type 7-9-6 pin when the voltage level on this pin is intermediate. However, setting the corresponding bit of the given PDIDISx register to 1 prevents the flow of a through current.
Remark 1. For alternate functions, see 2.1 Functions of Port Pins. Remark 2. SAU: Serial array unit
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RL78/G23 Figure 2 - 16 Pin Block Diagram for Pin Type 7-31-2
WRPU
PU register (PUmn)
WRPMCT
PMCT register (PMCTmn)
Internal bus
RDPORT WRPORT
Alternate function
1 1
0 0
Output latch (Pmn)
WRPMS WRPM
PMS register
PM register (PMmn)
Alternate function (SAU and UARTA)
Note 1
Alternate function (other than SAU and
UARTA) Note 2
PMCTmn
Touch sensor output data signal
Note 1. Note 2.
This excludes the clock output from UARTA. This includes the clock output from UARTA.
Remark 1. For alternate functions, see 2.1 Functions of Port Pins. Remark 2. SAU: Serial array unit
CHAPTER 2 PIN FUNCTIONS
EVDD P-ch
EVDD
P-ch N-ch EVSS
Pmn
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RL78/G23 Figure 2 - 17 Pin Block Diagram for Pin Type 7-31-3
WRPU
PU register (PUmn)
WRPMCT
PMCT register (PMCTmn)
PDIDISmn
RDPORT WRPORT
Alternate function
1 1
0 0
Output latch (Pmn)
WRPMS WRPM WRPOM
PMS register
PM register (PMmn)
POM register (POMmn)
Alternate function (SAU and UARTA)
Note 1
WRPDIDIS
Alternate function (other than SAU and
UARTA) Note 2
PMCTmn
PDIDIS register Touch sensor output data signal (PDIDISmn)
Internal bus
CHAPTER 2 PIN FUNCTIONS
EVDD P-ch
EVDD
P-ch N-ch EVSS
Pmn
Note 1. Note 2.
This excludes the clock output from UARTA. This includes the clock output from UARTA.
Caution
The input buffer is enabled even if the type 7-31-3 pin is operating as an output when the N-ch open-drain output mode is selected by the corresponding bit in the port output mode register (POMx). This may lead to a through current flowing through the type 7-31-3 pin when the voltage level on this pin is intermediate. However, setting the corresponding bit of the given PDIDISx register to 1 prevents the flow of a through current.
Remark 1. For alternate functions, see 2.1 Functions of Port Pins. Remark 2. SAU: Serial array unit
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RL78/G23 Figure 2 - 18 Pin Block Diagram for Pin Type 7-33-4
CHAPTER 2 PIN FUNCTIONS
Internal bus
WRPU
PU register (PUmn)
WRPMCA
PMCTmn
PMCA register (PMCAmn)
PDIDISmn
RDPORT WRPORT
Alternate function
1 1
0 0
Output latch (Pmn)
WRPMS WRPM WRPOM
PMS register
PM register (PMmn)
POM register (POMmn)
Alternate function (SAU and UARTA)
Note 1
WRPMCT WRPDIDIS
Alternate function (other than SAU and
UARTA) Note 2
PMCT register (PMCTmn)
PDIDIS register (PDIDISmn)
A/D converter
PMCAmn PMCTmn Touch sensor output data signal
EVDD P-ch
EVDD
P-ch N-ch EVSS
Pmn
P-ch N-ch
Note 1. This excludes the clock output from UARTA. Note 2. This includes the clock output from UARTA. Caution The input buffer is enabled even if the type 7-33-4 pin is operating as an output when the N-ch open-drain output
mode is selected by the corresponding bit in the port output mode register (POMx). This may lead to a through current flowing through the type 7-33-4 pin when the voltage level on this pin is intermediate. However, setting the corresponding bit of the given PDIDISx register to 1 prevents the flow of a through current. Remark 1. For alternate functions, see 2.1 Functions of Port Pins. Remark 2. SAU: Serial array unit
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RL78/G23 Figure 2 - 19 Pin Block Diagram for Pin Type 7-38-1
CHAPTER 2 PIN FUNCTIONS
WRPU
Alternate function
PU register (PUmn)
EVDD P-ch
Internal bus
RDPORT
1 1
WRPORT
0 0
Output latch (Pmn)
WRPMS
WRPM
PMS register
PM register (PMmn)
Alternate function (SAU and UARTA)
Note 1
WRCCDE WRPMCE
Alternate function (other than SAU and
UARTA) Note 2
CCDE register (CCDE0x)
PMCE register (PMCEmn)
PMS CCDE0x
PMCEmn 0
ELCL function 1
EVDD
P-ch
0 CCSx
1
N-ch EVSS
Pmn
PMCEmn Pmn
PMmn CCDE0x
Note 1. Note 2.
This excludes the clock output from UARTA. This includes the clock output from UARTA.
Remark 1. For alternate functions, see 2.1 Functions of Port Pins. Remark 2. SAU: Serial array unit
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RL78/G23 Figure 2 - 20 Pin Block Diagram for Pin Type 7-39-1
CHAPTER 2 PIN FUNCTIONS
WRPU
Alternate function
PU register (PUmn)
PMCTmn
EVDD P-ch
Internal bus
RDPORT 1
WRPORT WRPMS WRPM WRPM
0
Output latch (Pmn)
PMS register
PM register (PMmn)
POM register (POMmn)
Alternate function (SAU and UARTA)
Note 1
Alternate function (other than SAU and
UARTA) Note 2
WRCCDE
CCDE register (CCDE0x)
WRPDIDIS
PDIDIS register (PDIDISmn)
WRPMCT WRPMCE
PMCT register (PMCTmn)
PMCE register (PMCEmn)
PMCTmn
PDIDISmn 1
0
PMCEmn
EVDD
0
ELCL function 1 PMCTmn
0 CCSx 1
P-ch N-ch
EVSS
PMCTmn PMCEmn
Pmn PMmn CCDE0x
PMCTmn Touch sensor output data signal
PMS CCDE0x
Pmn
Note 1. This excludes the clock output from UARTA. Note 2. This includes the clock output from UARTA. Caution The input buffer is enabled even if the type 7-39-1 pin is operating as an output when the N-ch open-drain output
mode is selected by the corresponding bit in the port output mode register (POMx). This may lead to a through current flowing through the type 7-39-1 pin when the voltage level on this pin is intermediate. However, setting the corresponding bit of the given PDIDISx register to 1 prevents the flow of a through current. Remark 1. For alternate functions, see 2.1 Functions of Port Pins. Remark 2. SAU: Serial array unit
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RL78/G23 Figure 2 - 21 Pin Block Diagram for Pin Type 8-1-3
CHAPTER 2 PIN FUNCTIONS
WRPU WRPIM
PU register (PUmn)
PIM register (PIMmn)
RDPORT WRPORT WRPMS
Alternate function
1 1
0 0
Output latch (Pmn)
PMS register
WRPM
PM register (PMmn)
EVDD P-ch
CMOS TTL
EVDD
P-ch N-ch EVSS
Pmn
Internal bus
Alternate function (SAU and UARTA)
Note 1
Alternate function (other than SAU and
UARTA) Note 2
Note 1. Note 2.
This excludes the clock output from UARTA. This includes the clock output from UARTA.
Caution
When the type 8-1-3 pin is set to TTL input buffer by the corresponding bit in the port input mode register (PIMx) and is driven high, a through current may flow through the type 8-1-3 pin due to the configuration of the TTL input buffer. Drive the type 8-1-3 pin low to prevent the through current.
Remark 1. For alternate functions, see 2.1 Functions of Port Pins. Remark 2. SAU: Serial array unit
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RL78/G23 Figure 2 - 22 Pin Block Diagram for Pin Type 8-1-10
WRPU WRPIM
PU register (PUmn)
PIM register (PIMmn)
RDPORT WRPORT WRPMS
Alternate function
1 1
0 0
Output latch (Pmn)
PMS register
WRPM WRPOM
PM register (PMmn)
POM register (POMmn)
Internal bus
CHAPTER 2 PIN FUNCTIONS
EVDD P-ch
CMOS TTL
PDIDISmn
EVDD
P-ch N-ch EVSS
Pmn
Alternate function (SAU and UARTA)
Note 1
Alternate function (other than SAU and
UARTA) Note 2
WRPDIDIS
PDIDIS register (PDIDISmn)
Note 1. Note 2.
This excludes the clock output from UARTA. This includes the clock output from UARTA.
Caution 1. The input buffer is enabled even if the type 8-1-10 pin is operating as an output when the N-ch open-drain output mode is selected by the corresponding bit in the port output mode register (POMx). This may lead to a through current flowing through the type 8-1-10 pin when the voltage level on this pin is intermediate. However, setting the corresponding bit of the given PDIDISx register to 1 prevents the flow of a through current.
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RL78/G23
CHAPTER 2 PIN FUNCTIONS
Caution 2. When the type 8-1-10 pin is set to TTL input buffer by the corresponding bit in the port input mode register (PIMx) and is driven high, a through current may flow through the type 8-1-10 pin due to the configuration of the TTL input buffer. Drive the type 8-1-10 pin low to prevent the through current.
Remark 1. For alternate functions, see 2.1 Functions of Port Pins. Remark 2. SAU: Serial array unit
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RL78/G23 Figure 2 - 23 Pin Block Diagram for Pin Type 8-1-11
CHAPTER 2 PIN FUNCTIONS
WRPU WRPIM
PU register (PUmn)
PIM register (PIMmn)
RDPORT WRPORT
Alternate function
1 1
0 0
Output latch (Pmn)
WRPMS
PMS register
WRPM WRPOM
PM register (PMmn)
POM register (POMmn)
EVDD P-ch
PMCEmn 0
ELCL function 1
CMOS TTL
PDIDISmn
EVDD
P-ch N-ch EVSS
Pmn
Internal bus
Alternate function (SAU and UARTA)
Note 1
WRPDIDIS
Alternate function (other than SAU and
UARTA) Note 2
WRPMCE
PDIDIS register (PDIDISmn)
PMCE register (PMCEmn)
Note 1. Note 2.
This excludes the clock output from UARTA. This includes the clock output from UARTA.
Caution 1. The input buffer is enabled even if the type 8-1-11 pin is operating as an output when the N-ch open-drain output mode is selected by the corresponding bit in the port output mode register (POMx). This may lead to a through current flowing through the type 8-1-11 pin when the voltage level on this pin is intermediate. However, setting the corresponding bit of the given PDIDISx register to 1 prevents the flow of a through current.
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RL78/G23
CHAPTER 2 PIN FUNCTIONS
Caution 2. When the type 8-1-11 pin is set to TTL input buffer by the corresponding bit in the port input mode register (PIMx) and is driven high, a through current may flow through the type 8-1-11 pin due to the configuration of the TTL input buffer. Drive the type 8-1-11 pin low to prevent the through current.
Remark 1. For alternate functions, see 2.1 Functions of Port Pins. Remark 2. SAU: Serial array unit
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RL78/G23 Figure 2 - 24 Pin Block Diagram for Pin Type 8-6-9
CHAPTER 2 PIN FUNCTIONS
WRPU WRPIM WRPMCA
PU register (PUmn)
PIM register (PIMmn)
PMCA register (PMCAmn)
RDPORT WRPORT
Alternate function
1
1 0
0
Output latch (Pmn)
WRPMS WRPM WRPOM
PMS register
PM register (PMmn)
POM register (POMmn)
PDIDISmn
EVDD P-ch
CMOS TTL
PMCEmn 0
ELCL function
1
EVDD
P-ch N-ch EVSS
Pmn
Internal bus
Alternate function (SAU and UARTA)
Note 1
WRPDIDIS WRPMCE
Alternate function (other than SAU and
UARTA) Note 2
PDIDIS register (PDIDISmn)
PMCE register (PMCEImn)
Comparator input
Note 1. Note 2.
This excludes the clock output from UARTA. This includes the clock output from UARTA.
Caution 1. The input buffer is enabled even if the type 8-6-9 pin is operating as an output when the N-ch open-drain output mode is selected by the corresponding bit in the port output mode register (POMx). This may lead to a through current flowing through the type 8-6-9 pin when the voltage level on this pin is intermediate. However, setting the corresponding bit of the given PDIDISx register to 1 prevents the flow of a through current.
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RL78/G23
CHAPTER 2 PIN FUNCTIONS
Caution 2. When the type 8-6-9 pin is set to TTL input buffer by the corresponding bit in the port input mode register (PIMx) and is driven high, a through current may flow through the type 8-6-9 pin due to the configuration of the TTL input buffer. Drive the type 8-6-9 pin low to prevent the through current.
Remark 1. For alternate functions, see 2.1 Functions of Port Pins. Remark 2. SAU: Serial array unit
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RL78/G23 Figure 2 - 25 Pin Block Diagram for Pin Type 8-31-1
CHAPTER 2 PIN FUNCTIONS
Alternate function
WRPU WRPMCT WRPIM
PU register (PUmn)
PMCT register (PMCTmn)
PIM register (PIMmn)
RDPORT
WRPORT WRPMS WRPM WRPMCE
1 1
0 0
Output latch (Pmn)
PMS register
PM register (PMmn)
PMCE register (PMCEmn)
EVDD P-ch
TTL
PMCEmn 0
ELCL function
1
EVDD P-ch
N-ch EVSS
Pmn
Internal bus
Alternate function (SAU and UARTA)
Note 1
Alternate function (other than SAU and
UARTA) Note 2
PMCTmn Touch sensor output data signal
Note 1. Note 2.
This excludes the clock output from UARTA. This includes the clock output from UARTA.
Caution
When the type 8-31-1 pin is set to TTL input buffer by the corresponding bit in the port input mode register (PIMx) and is driven high, a through current may flow through the type 8-31-1 pin due to the configuration of the TTL input buffer. Drive the type 8-31-1 pin low to prevent the through current.
Remark 1. For alternate functions, see 2.1 Functions of Port Pins. Remark 2. SAU: Serial array unit
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RL78/G23 Figure 2 - 26 Pin Block Diagram for Pin Type 8-31-2
WRPU WRPIM WRPMCT
PU register (PUmn)
PIM register (PIMmn)
PMCT register (PMCTmn)
RDPORT WRPORT
Alternate function
1
1 0
0
Output latch (Pmn)
WRPMS
WRPM WRPOM
PMS register
PM register (PMmn)
POM register (POMmn)
PDIDISmn
Alternate function (SAU and UARTA)
Note 1
WRPDIDIS
Alternate function (other than SAU and
UARTA) Note 2
PDIDIS register (PDIDISmn)
PMCTmn Touch sensor output data signal
Internal bus
CHAPTER 2 PIN FUNCTIONS
EVDD P-ch
CMOS TTL
EVDD
P-ch N-ch EVSS
Pmn
Note 1. Note 2.
This excludes the clock output from UARTA. This includes the clock output from UARTA.
Caution 1. The input buffer is enabled even if the type 8-31-2 pin is operating as an output when the N-ch open-drain output mode is selected by the corresponding bit in the port output mode register (POMx). This may lead to a through current flowing through the type 8-31-2 pin when the voltage level on this pin is intermediate. However, setting the corresponding bit of the given PDIDISx register to 1 prevents the flow of a through current.
Caution 2. When the type 8-31-2 pin is set to TTL input buffer by the corresponding bit in the port input mode register (PIMx) and is driven high, a through current may flow through the type 8-31-2 pin due to the configuration of the TTL input buffer. Drive the type 8-31-2 pin low to prevent the through current.
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RL78/G23
Remark 1. For alternate functions, see 2.1 Functions of Port Pins. Remark 2. SAU: Serial array unit
CHAPTER 2 PIN FUNCTIONS
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RL78/G23 Figure 2 - 27 Pin Block Diagram for Pin Type 8-33-2
CHAPTER 2 PIN FUNCTIONS
Internal bus
Alternate function
WRPU
PU register (Pumn)
WRPMCA
PMCA register (PMCAmn)
WRPIM
PMCTmn
PIM register (PIMmn)
RDPORT
1
01
0
WRPORT WRPMS
Output latch (Pmn)
PMS register
WRPM PM register (PMmn)
WRPMCE PMCE register (PMCEmn)
ELCL function
PMCEmn 0
1
EVDD
TTL
EVDD VSS
Alternate function (SAU and UARTA)
Note 1
Alternate function (other than SAU and UARTA) Note 2
PMCAmn PMCTmn Touch sensor output data signal
WRPMCT PMCT register (PMCTmn)
A/D converter
Note 1. Note 2.
This excludes the clock output from UARTA. This includes the clock output from UARTA.
Caution
When the type 8-33-2 pin is set to TTL input buffer by the corresponding bit in the port input mode register (PIMx) and is driven high, a through current may flow through the type 8-33-2 pin due to the configuration of the TTL input buffer. Drive the type 8-33-2 pin low to prevent the through current.
Remark 1. For alternate functions, see 2.1 Functions of Port Pins. Remark 2. SAU: Serial array unit
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RL78/G23 Figure 2 - 28 Pin Block Diagram for Pin Type 8-33-3
CHAPTER 2 PIN FUNCTIONS
Internal bus
WRPU WRPIM WRPMCA
PU register (PUmn)
PIM register (PIMmn)
PMCTmn PMCA register
(PMCAmn)
RDPORT WRPORT
Alternate function
1
1 0
0
Output latch (Pmn)
WRPMS
WRPM WRPOM
PMS register
PM register (PMmn)
POM register (POMmn)
PDIDISmn
Alternate function (SAU and UARTA)
Note 1
WRPMCT WRPDIDIS
Alternate function (other than SAU and
UARTA) Note 2
PMCT register (PMCTmn)
PDIDIS register (PDIDISmn)
A/D converter
PMCAmn PMCTmn Touch sensor output data signal
EVDD P-ch
CMOS TTL
EVDD
P-ch N-ch EVSS
Pmn
P-ch N-ch
Note 1. Note 2.
This excludes the clock output from UARTA. This includes the clock output from UARTA.
Caution 1. The input buffer is enabled even if the type 8-33-3 pin is operating as an output when the N-ch open-drain output mode is selected by the corresponding bit in the port output mode register (POMx). This may lead to a through current flowing through the type 8-33-3 pin when the voltage level on this pin is intermediate. However, setting the corresponding bit of the given PDIDISx register to 1 prevents the flow of a through current.
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RL78/G23
CHAPTER 2 PIN FUNCTIONS
Caution 2. When the type 8-33-3 pin is set to TTL input buffer by the corresponding bit in the port input mode register (PIMx) and is driven high, a through current may flow through the type 8-33-3 pin due to the configuration of the TTL input buffer. Drive the type 8-33-3 pin low to prevent the through current.
Remark 1. For alternate functions, see 2.1 Functions of Port Pins. Remark 2. SAU: Serial array unit
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RL78/G23 Figure 2 - 29 Pin Block Diagram for Pin Type 8-38-1
CHAPTER 2 PIN FUNCTIONS
WRPU WRPIM
PU register (PUmn)
PIM register (PIMmn)
RDPORT WRPORT WRPMS
Alternate function
1 1
0 0
Output latch (Pmn)
PMS register
WRPM
PM register (PMmn)
EVDD P-ch
CMOS TTL
PMS CCDE0x
PMCEmn 0
EVDD
ELCL function 1
P-ch
0
1 CCSx
N-ch EVSS
Pmn
Internal bus
Alternate function (SAU and UARTA)
Note 1
Alternate function (other than SAU and
UARTA) Note 2
WRCCDE
CCDE register (CCDE0x)
WRPMCE
PMCE register (PMCEmn)
PMCEmn Pmn
PMmn
CCDE0x
Note 1. Note 2.
This excludes the clock output from UARTA. This includes the clock output from UARTA.
Caution
When the type 8-38-1 pin is set to TTL input buffer by the corresponding bit in the port input mode register (PIMx) and is driven high, a through current may flow through the type 8-38-1 pin due to the configuration of the TTL input buffer. Drive the type 8-38-1 pin low to prevent the through current.
Remark 1. For alternate functions, see 2.1 Functions of Port Pins. Remark 2. SAU: Serial array unit
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RL78/G23 Figure 2 - 30 Pin Block Diagram for Pin Type 8-38-2
CHAPTER 2 PIN FUNCTIONS
WRPU WRPIM
PU register (PUmn)
PIM register (PIMmn)
RDPORT
WRPORT WRPMS WRPM WRPOM
Alternate function
1 1
0 0
Output latch (Pmn)
PMS register
PM register (PMmn)
POM register (POMmn)
EVDD P-ch
CMOS TTL
PMS CCDE0x
PDIDISmn
PMCEmn 0
EVDD
ELCL function 1
P-ch
0
1 CCSx
N-ch
EVSS
Pmn
Internal bus
Alternate function (SAU and UARTA)
Note 1
WRCCDE
Alternate function (other than SAU and
UARTA) Note 2
CCDE register (CCDE0x)
WRPDIDIS
PDIDIS register (PDIDISEmn)
WRPMCE
PMCE register (PMCEmn)
PMCEmn Pmn
PMmn
CCDE0x
Note 1. Note 2.
This excludes the clock output from UARTA. This includes the clock output from UARTA.
Caution 1. The input buffer is enabled even if the type 8-38-2 pin is operating as an output when the N-ch open-drain output mode is selected by the corresponding bit in the port output mode register (POMx). This may lead to a through current flowing through the type 8-38-2 pin when the voltage level on this pin is intermediate. However, setting the corresponding bit of the given PDIDISx register to 1 prevents the flow of a through current.
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RL78/G23
CHAPTER 2 PIN FUNCTIONS
Caution 2. When the type 8-38-2 pin is set to TTL input buffer by the corresponding bit in the port input mode register (PIMx) and is driven high, a through current may flow through the type 8-38-2 pin due to the configuration of the TTL input buffer. Drive the type 8-38-2 pin low to prevent the through current.
Remark 1. For alternate functions, see 2.1 Functions of Port Pins. Remark 2. SAU: Serial array unit
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RL78/G23 Figure 2 - 31 Pin Block Diagram for Pin Type 12-38-1
Alternate function
CHAPTER 2 PIN FUNCTIONS
RDPORT
1
0
1
0
WRPORT
Output latch (Pmn)
WRPMS
WRPM
PMS register
PM register (PMmn)
PMS
CCDE0x
0 CCSx
1
N-ch EVSS1
Pmn
Internal bus
Alternate function (SAU and UARTA)
Note 1
WRCCDE
Alternate function (other than SAU and
UARTA) Note 2
CCDE register (CCDE0x)
Pmn PMmn CCDE0x
Note 1. Note 2.
This excludes the clock output from UARTA. This includes the clock output from UARTA.
Caution The input buffer is enabled even if the type 12-38-1 pin is operating as an output. This may lead to a through current flowing through the type 12-38-1 pin when the voltage level on this pin is intermediate.
Remark 1. For alternate functions, see 2.1 Functions of Port Pins. Remark 2. SAU: Serial array unit
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RL78/G23 Figure 2 - 32 Pin Block Diagram for Pin Type 12-38-2
WRPER0 RDPORT
Alternate function
PER0 (IICAjEN)
1
0
1
0
WRPORT
Output latch (Pmn)
WRPMS
WRPM
PMS register
PM register (PMmn)
Alternate function (SAU and UARTA)
Note 1
Alternate function (other than SAU and
UARTA) Note 2
WRCCDE CCDE register (CCDE0x)
Internal bus
CHAPTER 2 PIN FUNCTIONS
PMS
CCDE0x
0
CCSx 1
N-ch VSS
Pmn
Pmn PMmn CCDE0x
Note 1. Note 2.
This excludes the clock output from UARTA. This includes the clock output from UARTA.
Caution The input buffer is enabled even if the type 12-38-2 pin is operating as an output. This may lead to a through current flowing through the type 12-38-2 pin when the voltage level on this pin is intermediate.
Remark 1. For alternate functions, see 2.1 Functions of Port Pins. Remark 2. SAU: Serial array unit
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RL78/G23 Figure 2 - 33 Pin Block Diagram for Pin Type 12-38-3
CHAPTER 2 PIN FUNCTIONS
Internal bus
WRPER0 RDPORT
Alternate function
PER0 (IICAjEN)
1
0
1
0
WRPORT
Output latch (Pmn)
WRPMS
WRPM
PMS register
PM register (PMmn)
Alternate function (SAU and UARTA)
Note 1
WRCCDE
Alternate function (other than SAU and
UARTA) Note 2
WRPMCE
CCDE register (CCDE0x)
PMCE register (PMCEmn)
PMS
CCDE0x
PMCEmn 0
ELCL function 1
0 CCSx
1
Pmn N-ch VSS
PMCEmn Pmn
PMmn CCDE0x
Note 1. Note 2.
This excludes the clock output from UARTA. This includes the clock output from UARTA.
Caution The input buffer is enabled even if the type 12-38-3 pin is operating as an output. This may lead to a through current flowing through the type 12-38-3 pin when the voltage level on this pin is intermediate.
Remark 1. For alternate functions, see 2.1 Functions of Port Pins. Remark 2. SAU: Serial array unit
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RL78/G23
CHAPTER 3 CPU ARCHITECTURE
CHAPTER 3 CPU ARCHITECTURE
The RL78/G23 is a microcontroller that has the RL78-S3 CPU core. The CPU core in the RL78-S3 employs the Harvard architecture which has independent instruction fetch bus, address bus and data bus. In addition, through the adoption of three-stage pipeline control of fetch, decode, and memory access, the operation efficiency is remarkably improved over the conventional CPU core. The CPU core features high performance and highly functional instruction processing, and can be suited for use in various applications that require high speed and highly functional processing.
· 3-stage pipeline CISC architecture · Address space: 1 Mbyte · Minimum instruction execution time: One instruction per clock cycle · General-purpose registers: Eight 8-bit registers · Type of instruction: 81
The following multiply/divide instructions are available only in the RL78-S3 CPU core. MULHU (unsigned 16-bit multiplication) MULH (signed 16-bit multiplication) DIVHU (unsigned 16-bit division) DIVWU (unsigned 32-bit division) MACHU (unsigned multiplication/accumulation (16 bits × 16 bits) + 32 bits) MACH (signed multiplication/accumulation (16 bits × 16 bits) + 32 bits)
· Data allocation: Little endian
The RL78/G23 supports an OCD trace function.
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RL78/G23
CHAPTER 3 CPU ARCHITECTURE
3.1
Memory Space
Products in the RL78/G23 can access a 1 MB address space. Figure 3 - 1 to Figure 3 - 3 show the memory maps.
Figure 3 - 1 Memory Map (R7F100GxF (x = A, B, C, E, F, G, J, L))
FFFFFH
FFF00H FFEFFH FFEE0H FFEDFH
FCF00H FCEFFH
F3000H F2FFFH
F1000H F0FFFH F0800H F07FFH
Data memory space
F0000H EFFFFH
Special function registers (SFRs) 256 bytes
General-purpose registers 32 bytes
RAM Note 1 12 Kbytes
Mirror 39.75 Kbytes
Data flash memory 8 Kbytes
Reserved
Extended special function registers (2nd SFRs) 2 Kbytes
Reserved
18000H 17FFFH
00000H
Code flash memory 96 Kbytes
17FFFH
Program area
040CEH 040CDH
040C4H 040C3H 040C0H 040BFH
04080H 0407FH
04000H 03FFFH
000CEH 000CDH
000C4H 000C3H 000C0H 000BFH
00080H 0007FH
00000H
On-chip debug security ID setting area Note 2 10 bytes Option bytes area Note 2 4 bytes CALLT table 64 bytes
Vector table area 128 bytes
Program area
On-chip debug security ID setting area Note 2 10 bytes Option bytes area Note 2 4 bytes CALLT table 64 bytes
Vector table area 128 bytes
07FFFH Boot cluster 1
Boot cluster 0 Note 3
Note 1. Note 2.
Note 3.
Instructions can be executed from the RAM area excluding the general-purpose register area. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH. When boot swap is used: Set the option bytes to 000C0H to 000C3H and 040C0H to 040C3H, and the on-chip debug security IDs to 000C4H to 000CDH and 040C4H to 040CDH. Writing boot cluster 0 can be prohibited depending on the setting of security (see 33.7 Security Settings).
Caution
While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data access is to proceed and the RAM area + 10 bytes when instructions are fetched from RAM areas, respectively. RAM parity error resets become enabled (RPERDIS = 0) following a reset. For details, see 27.3.4 RAM parity error detection.
Remark The code flash memory area is divided into blocks, with each block being 2 Kbytes. For the correspondence between addresses and block numbers, see Table 3 - 1.
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RL78/G23 Figure 3 - 2 Memory Map (R7F100GxG (x = A, B, C, E, F, G, J, L, M, P))
CHAPTER 3 CPU ARCHITECTURE
FFFFFH
FFF00H FFEFFH FFEE0H FFEDFH
FBF00H FBEFFH
F3000H F2FFFH
F1000H F0FFFH F0800H F07FFH
Data memory space
F0000H EFFFFH
Special function registers (SFRs) 256 bytes
General-purpose registers 32 bytes RAM Note 1 16 Kbytes
Mirror 35.75 Kbytes
Data flash memory 8 Kbytes
Reserved
Extended special function registers (2nd SFRs) 2 Kbytes
Reserved
20000H 1FFFFH
00000H
Code flash memory 128 Kbytes
1FFFFH
Program area
040CEH 040CDH
040C4H 040C3H 040C0H 040BFH
04080H 0407FH
04000H 03FFFH
000CEH 000CDH
000C4H 000C3H 000C0H 000BFH
00080H 0007FH
00000H
On-chip debug security ID setting area Note 2 10 bytes Option bytes area Note 2 4 bytes CALLT table 64 bytes
Vector table area 128 bytes
Program area
On-chip debug security ID setting area Note 2 10 bytes Option bytes area Note 2 4 bytes CALLT table 64 bytes
Vector table area 128 bytes
07FFFH Boot cluster 1
Boot cluster 0 Note 3
Note 1. Note 2.
Note 3.
Instructions can be executed from the RAM area excluding the general-purpose register area. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH. When boot swap is used: Set the option bytes to 000C0H to 000C3H and 040C0H to 040C3H, and the on-chip debug security IDs to 000C4H to 000CDH and 040C4H to 040CDH. Writing boot cluster 0 can be prohibited depending on the setting of security (see 33.7 Security Settings).
Caution
While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data access is to proceed and the RAM area + 10 bytes when instructions are fetched from RAM areas, respectively. RAM parity error resets become enabled (RPERDIS = 0) following a reset. For details, see 27.3.4 RAM parity error detection.
Remark The code flash memory area is divided into blocks, with each block being 2 Kbytes. For the correspondence between addresses and block numbers, see Table 3 - 1.
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RL78/G23 Figure 3 - 3 Memory Map (R7F100GxH (x = A, B, C, E, F, G, J, L, M, P))
CHAPTER 3 CPU ARCHITECTURE
FFFFFH
FFF00H FFEFFH FFEE0H FFEDFH
FAF00H FAEFFH
F3000H F2FFFH
F1000H F0FFFH F0800H F07FFH
Data memory space
F0000H EFFFFH
Special function registers (SFRs) 256 bytes
General-purpose registers 32 bytes RAM Note 1 20 Kbytes
Mirror 31.75 Kbytes
Data flash memory 8 Kbytes
Reserved
Extended special function registers (2nd SFRs) 2 Kbytes
Reserved
30000H 2FFFFH
00000H
Code flash memory 192 Kbytes
2FFFFH
Program area
040CEH 040CDH
040C4H 040C3H 040C0H 040BFH
04080H 0407FH
04000H 03FFFH
000CEH 000CDH
000C4H 000C3H 000C0H 000BFH
00080H 0007FH
00000H
On-chip debug security ID setting area Note 2 10 bytes Option bytes area Note 2 4 bytes CALLT table 64 bytes
Vector table area 128 bytes
Program area
On-chip debug security ID setting area Note 2 10 bytes Option bytes area Note 2 4 bytes CALLT table 64 bytes
Vector table area 128 bytes
07FFFH Boot cluster 1
Boot cluster 0 Note 3
Note 1. Note 2.
Note 3.
Instructions can be executed from the RAM area excluding the general-purpose register area. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH. When boot swap is used: Set the option bytes to 000C0H to 000C3H and 040C0H to 040C3H, and the on-chip debug security IDs to 000C4H to 000CDH and 040C4H to 040CDH. Writing boot cluster 0 can be prohibited depending on the setting of security (see 33.7 Security Settings).
Caution
While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data access is to proceed and the RAM area + 10 bytes when instructions are fetched from RAM areas, respectively. RAM parity error resets become enabled (RPERDIS = 0) following a reset. For details, see 27.3.4 RAM parity error detection.
Remark The code flash memory area is divided into blocks, with each block being 1 Kbyte. For the correspondence between addresses and block numbers, see Table 3 - 1.
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RL78/G23 Figure 3 - 4 Memory Map (R7F100GxJ (x = A, B, C, E, F, G, J, L, M, P, S))
CHAPTER 3 CPU ARCHITECTURE
FFFFFH
FFF00H FFEFFH FFEE0H FFEDFH
F9F00H F9EFFH
F3000H F2FFFH
F1000H F0FFFH F0800H F07FFH
Data memory space
F0000H EFFFFH
Special function registers (SFRs) 256 bytes
General-purpose registers 32 bytes RAM Note 1 24 Kbytes
Mirror 27.75 Kbytes
Data flash memory 8 Kbytes
Reserved Extended special function registers
(2nd SFRs) 2 Kbytes
Reserved
40000H 3FFFFH
00000H
Code flash memory 256 Kbytes
3FFFFH
Program area
040CEH 040CDH
040C4H 040C3H 040C0H 040BFH
04080H 0407FH
04000H 03FFFH
000CEH 000CDH
000C4H 000C3H 000C0H 000BFH
00080H 0007FH
00000H
On-chip debug security ID setting area Note 2 10 bytes Option bytes area Note 2 4 bytes CALLT table 64 bytes
Vector table area 128 bytes
Program area
On-chip debug security ID setting area Note 2 10 bytes Option bytes area Note 2 4 bytes CALLT table 64 bytes
Vector table area 128 bytes
07FFFH Boot cluster 1
Boot cluster 0 Note 3
Note 1. Note 2.
Note 3.
Instructions can be executed from the RAM area excluding the general-purpose register area. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH. When boot swap is used: Set the option bytes to 000C0H to 000C3H and 040C0H to 040C3H, and the on-chip debug security IDs to 000C4H to 000CDH and 040C4H to 040CDH. Writing boot cluster 0 can be prohibited depending on the setting of security (see 33.7 Security Settings).
Caution
While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data access is to proceed and the RAM area + 10 bytes when instructions are fetched from RAM areas, respectively. RAM parity error resets become enabled (RPERDIS = 0) following a reset. For details, see 27.3.4 RAM parity error detection.
Remark The code flash memory area is divided into blocks, with each block being 2 Kbytes. For the correspondence between addresses and block numbers, see Table 3 - 1.
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RL78/G23 Figure 3 - 5 Memory Map (R7F100GxK (x = F, G, J, L, M, P, S))
CHAPTER 3 CPU ARCHITECTURE
FFFFFH
FFF00H FFEFFH FFEE0H FFEDFH
F7F00H F7EFFH
F3000H F2FFFH
F1000H F0FFFH F0800H F07FFH
Data memory space
F0000H EFFFFH
Special function registers (SFRs) 256 bytes
General-purpose registers 32 bytes RAM Note 1 32 Kbytes
Mirror 19.75 Kbytes
Data flash memory 8 Kbytes
Reserved Extended special function registers
(2nd SFRs) 2 Kbytes
Reserved
60000H 5FFFFH
00000H
Code flash memory 384 Kbytes
5FFFFH
Program area
040CEH 040CDH
040C4H 040C3H 040C0H 040BFH
04080H 0407FH
04000H 03FFFH
000CEH 000CDH
000C4H 000C3H 000C0H 000BFH
00080H 0007FH
00000H
On-chip debug security ID setting area Note 2 10 bytes Option bytes area Note 2 4 bytes CALLT table 64 bytes
Vector table area 128 bytes
Program area
On-chip debug security ID setting area Note 2 10 bytes Option bytes area Note 2 4 bytes CALLT table 64 bytes
Vector table area 128 bytes
07FFFH Boot cluster 1
Boot cluster 0 Note 3
Note 1. Note 2.
Note 3.
Instructions can be executed from the RAM area excluding the general-purpose register area. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH. When boot swap is used: Set the option bytes to 000C0H to 000C3H and 040C0H to 040C3H, and the on-chip debug security IDs to 000C4H to 000CDH and 040C4H to 040CDH. Writing boot cluster 0 can be prohibited depending on the setting of security (see 33.7 Security Settings).
Caution
While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data access is to proceed and the RAM area + 10 bytes when instructions are fetched from RAM areas, respectively. RAM parity error resets become enabled (RPERDIS = 0) following a reset. For details, see 27.3.4 RAM parity error detection.
Remark The code flash memory area is divided into blocks, with each block being 2 Kbytes. For the correspondence between addresses and block numbers, see Table 3 - 1.
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RL78/G23 Figure 3 - 6 Memory Map (R7F100GxL (x = F, G, J, L, M, P, S))
CHAPTER 3 CPU ARCHITECTURE
FFFFFH
FFF00H FFEFFH FFEE0H FFEDFH
F3F00H F3EFFH
F3000H F2FFFH
F1000H F0FFFH F0800H F07FFH
Data memory space
F0000H EFFFFH
Special function registers (SFRs) 256 bytes
General-purpose registers 32 bytes RAM Note 1 48 Kbytes
Mirror 3.75 Kbytes
Data flash memory 8 Kbytes
Reserved
Extended special function registers (2nd SFRs) 2 Kbytes
Reserved
80000H 7FFFFH
00000H
Code flash memory 512 Kbytes
7FFFFH
Program area
040CEH 040CDH
040C4H 040C3H 040C0H 040BFH
04080H 0407FH
04000H 03FFFH
000CEH 000CDH
000C4H 000C3H 000C0H 000BFH
00080H 0007FH
00000H
On-chip debug security ID setting area Note 2 10 bytes Option bytes area Note 2 4 bytes CALLT table 64 bytes
Vector table area 128 bytes
Program area
On-chip debug security ID setting area Note 2 10 bytes Option bytes area Note 2 4 bytes CALLT table 64 bytes
Vector table area 128 bytes
07FFFH Boot cluster 1
Boot cluster 0 Note 3
Note 1. Note 2.
Note 3.
Instructions can be executed from the RAM area excluding the general-purpose register area. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH. When boot swap is used: Set the option bytes to 000C0H to 000C3H and 040C0H to 040C3H, and the on-chip debug security IDs to 000C4H to 000CDH and 040C4H to 040CDH. Writing boot cluster 0 can be prohibited depending on the setting of security (see 33.7 Security Settings).
Caution
While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data access is to proceed and the RAM area + 10 bytes when instructions are fetched from RAM areas, respectively. RAM parity error resets become enabled (RPERDIS = 0) following a reset. For details, see 27.3.4 RAM parity error detection.
Remark The code flash memory area is divided into blocks, with each block being 2 Kbytes. For the correspondence between addresses and block numbers, see Table 3 - 1.
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RL78/G23 Figure 3 - 7 Memory Map (R7F100GxN (x = F, G, J, L, M, P, S))
CHAPTER 3 CPU ARCHITECTURE
FFFFFH
FFF00H FFEFFH FFEE0H FFEDFH
F3F00H F3EFFH
F3000H F2FFFH
F1000H F0FFFH F0800H F07FFH
Data memory space
F0000H EFFFFH
Special function registers (SFRs) 256 bytes
General-purpose registers 32 bytes RAM Note 1 48 Kbytes
Mirror 3.75 Kbytes
Data flash memory 8 Kbytes
Reserved
Extended special function registers (2nd SFRs) 2 Kbytes
Reserved
C0000H BFFFFH
00000H
Code flash memory 768 Kbytes
BFFFFH
Program area
040CEH 040CDH
040C4H 040C3H 040C0H 040BFH
04080H 0407FH
04000H 03FFFH
000CEH 000CDH
000C4H 000C3H 000C0H 000BFH
00080H 0007FH
00000H
On-chip debug security ID setting area Note 2 10 bytes Option bytes area Note 2 4 bytes CALLT table 64 bytes
Vector table area 128 bytes
Program area
On-chip debug security ID setting area Note 2 10 bytes Option bytes area Note 2 4 bytes CALLT table 64 bytes
Vector table area 128 bytes
07FFFH Boot cluster 1
Boot cluster 0 Note 3
Note 1. Note 2.
Note 3.
Instructions can be executed from the RAM area excluding the general-purpose register area. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH. When boot swap is used: Set the option bytes to 000C0H to 000C3H and 040C0H to 040C3H, and the on-chip debug security IDs to 000C4H to 000CDH and 040C4H to 040CDH. Writing boot cluster 0 can be prohibited depending on the setting of security (see 33.7 Security Settings).
Caution
While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data access is to proceed and the RAM area + 10 bytes when instructions are fetched from RAM areas, respectively. RAM parity error resets become enabled (RPERDIS = 0) following a reset. For details, see 27.3.4 RAM parity error detection.
Remark The code flash memory area is divided into blocks, with each block being 2 Kbytes. For the correspondence between addresses and block numbers, see Table 3 - 1.
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RL78/G23
CHAPTER 3 CPU ARCHITECTURE
Correspondence between the addresses and block numbers in the flash memory are shown below.
Table 3 - 1 Correspondence between Addresses and Block Numbers in Flash Memory (1/3)
Address
Block Number
Address
Block Number
Address
Block Number
Address
Block Number
00000H to 007FFH 000H 10000H to 107FFH 020H 20000H to 207FFH 040H 30000H to 307FFH 060H
00800H to 00FFFH 001H 10800H to 10FFFH 021H 20800H to 20FFFH 041H 30800H to 30FFFH 061H
01000H to 017FFH 002H 11000H to 117FFH 022H 21000H to 217FFH 042H 31000H to 317FFH 062H
01800H to 01FFFH 003H 11800H to 11FFFH 023H 21800H to 21FFFH 043H 31800H to 31FFFH 063H
02000H to 027FFH 004H 12000H to 127FFH 024H 22000H to 227FFH 044H 32000H to 327FFH 064H
02800H to 02FFFH 005H 12800H to 12FFFH 025H 22800H to 22FFFH 045H 32800H to 32FFFH 065H
03000H to 037FFH 006H 13000H to 137FFH 026H 23000H to 237FFH 046H 33000H to 337FFH 066H
03800H to 03FFFH 007H 13800H to 13FFFH 027H 23800H to 23FFFH 047H 33800H to 33FFFH 067H
04000H to 047FFH 008H 14000H to 147FFH 028H 24000H to 247FFH 048H 34000H to 347FFH 068H
04800H to 04FFFH 009H 14800H to 14FFFH 029H 24800H to 24FFFH 049H 34800H to 34FFFH 069H
05000H to 057FFH 00AH 15000H to 157FFH 02AH 25000H to 257FFH 04AH 35000H to 357FFH 06AH
05800H to 05FFFH 00BH 15800H to 15FFFH 02BH 25800H to 25FFFH 04BH 35800H to 35FFFH 06BH
06000H to 067FFH 00CH 16000H to 167FFH 02CH 26000H to 267FFH 04CH 36000H to 367FFH 06CH
06800H to 06FFFH 00DH 16800H to 16FFFH 02DH 26800H to 26FFFH 04DH 36800H to 36FFFH 06DH
07000H to 077FFH 00EH 17000H to 177FFH 02EH 27000H to 277FFH 04EH 37000H to 377FFH 06EH
07800H to 07FFFH 00FH 17800H to 17FFFH 02FH 27800H to 27FFFH 04FH 37800H to 37FFFH 06FH
08000H to 087FFH 010H 18000H to 187FFH 030H 28000H to 287FFH 050H 38000H to 387FFH 070H
08800H to 08FFFH 011H 18800H to 18FFFH 031H 28800H to 28FFFH 051H 38800H to 38FFFH 071H
09000H to 097FFH 012H 19000H to 197FFH 032H 29000H to 297FFH 052H 39000H to 397FFH 072H
09800H to 09FFFH 013H 19800H to 19FFFH 033H 29800H to 29FFFH 053H 39800H to 39FFFH 073H
0A000H to 0A7FFH 014H 1A000H to 1A7FFH 034H 2A000H to 2A7FFH 054H 3A000H to 3A7FFH 074H
0A800H to 0AFFFH 015H 1A800H to 1AFFFH 035H 2A800H to 2AFFFH 055H 3A800H to 3AFFFH 075H
0B000H to 0B7FFH 016H 1B000H to 1B7FFH 036H 2B000H to 2B7FFH 056H 3B000H to 3B7FFH 076H
0B800H to 0BFFFH 017H 1B800H to 1BFFFH 037H 2B800H to 2BFFFH 057H 3B800H to 3BFFFH 077H
0C000H to 0C7FFH 018H 1C000H to 1C7FFH 038H 2C000H to 2C7FFH 058H 3C000H to 3C7FFH 078H
0C800H to 0CFFFH 019H 1C800H to 1CFFFH 039H 2C800H to 2CFFFH 059H 3C800H to 3CFFFH 079H
0D000H to 0D7FFH 01AH 1D000H to 1D7FFH 03AH 2D000H to 2D7FFH 05AH 3D000H to 3D7FFH 07AH
0D800H to 0DFFFH 01BH 1D800H to 1DFFFH 03BH 2D800H to 2DFFFH 05BH 3D800H to 3DFFFH 07BH
0E000H to 0E7FFH 01CH 1E000H to 1E7FFH 03CH 2E000H to 2E7FFH 05CH 3E000H to 3E7FFH 07CH
0E800H to 0EFFFH 01DH 1E800H to 1EFFFH 03DH 2E800H to 2EFFFH 05DH 3E800H to 3EFFFH 07DH
0F000H to 0F7FFH 01EH 1F000H to 1F7FFH 03EH 2F000H to 2F7FFH 05EH 3F000H to 3F7FFH 07EH
0F800H to 0FFFFH 01FH 1F800H to 1FFFFH 03FH 2F800H to 2FFFFH 05FH 3F800H to 3FFFFH 07FH
Remark
R7F100GxF (x = A, B, C, E, F, G, J, L): Block numbers 000H to 02FH R7F100GxG (x = A, B, C, E, F, G, J, L, M, P): Block numbers 000H to 03FH R7F100GxH (x = A, B, C, E, F, G, J, L, M, P): Block numbers 000H to 05FH R7F100GxJ (x = A, B, C, E, F, G, J, L, M, P, S): Block numbers 000H to 07FH
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RL78/G23
CHAPTER 3 CPU ARCHITECTURE
Table 3 - 2 Correspondence between Addresses and Block Numbers in Flash Memory (2/3)
Address
Block Number
Address
Block Number
Address
Block Number
Address
Block Number
40000H to 407FFH 080H 50000H to 507FFH 0A0H 60000H to 607FFH 0C0H 70000H to 707FFH 0E0H
40800H to 40FFFH 081H 50800H to 50FFFH 0A1H 60800H to 60FFFH 0C1H 70800H to 70FFFH 0E1H
41000H to 417FFH 082H 51000H to 517FFH 0A2H 61000H to 617FFH 0C2H 71000H to 717FFH 0E2H
41800H to 41FFFH 083H 51800H to 51FFFH 0A3H 61800H to 61FFFH 0C3H 71800H to 71FFFH 0E3H
42000H to 427FFH 084H 52000H to 527FFH 0A4H 62000H to 627FFH 0C4H 72000H to 727FFH 0E4H
42800H to 42FFFH 085H 52800H to 52FFFH 0A5H 62800H to 62FFFH 0C5H 72800H to 72FFFH 0E5H
43000H to 437FFH 086H 53000H to 537FFH 0A6H 63000H to 637FFH 0C6H 73000H to 737FFH 0E6H
43800H to 43FFFH 087H 53800H to 53FFFH 0A7H 63800H to 63FFFH 0C7H 73800H to 73FFFH 0E7H
44000H to 447FFH 088H 54000H to 547FFH 0A8H 64000H to 647FFH 0C8H 74000H to 747FFH 0E8H
44800H to 44FFFH 089H 54800H to 54FFFH 0A9H 64800H to 64FFFH 0C9H 74800H to 74FFFH 0E9H
45000H to 457FFH 08AH 55000H to 557FFH 0AAH 65000H to 657FFH 0CAH 75000H to 757FFH 0EAH
45800H to 45FFFH 08BH 55800H to 55FFFH 0ABH 65800H to 65FFFH 0CBH 75800H to 75FFFH 0EBH
46000H to 467FFH 08CH 56000H to 567FFH 0ACH 66000H to 667FFH 0CCH 76000H to 767FFH 0ECH
46800H to 46FFFH 08DH 56800H to 56FFFH 0ADH 66800H to 66FFFH 0CDH 76800H to 76FFFH 0EDH
47000H to 477FFH 08EH 57000H to 577FFH 0AEH 67000H to 677FFH 0CEH 77000H to 777FFH 0EEH
47800H to 47FFFH 08FH 57800H to 57FFFH 0AFH 67800H to 67FFFH 0CFH 77800H to 77FFFH 0EFH
48000H to 487FFH 090H 58000H to 587FFH 0B0H 68000H to 687FFH 0D0H 78000H to 787FFH 0F0H
48800H to 48FFFH 091H 58800H to 58FFFH 0B1H 68800H to 68FFFH 0D1H 78800H to 78FFFH 0F1H
49000H to 497FFH 092H 59000H to 597FFH 0B2H 69000H to 697FFH 0D2H 79000H to 797FFH 0F2H
49800H to 49FFFH 093H 59800H to 59FFFH 0B3H 69800H to 69FFFH 0D3H 79800H to 79FFFH 0F3H
4A000H to 4A7FFH 094H 5A000H to 5A7FFH 0B4H 6A000H to 6A7FFH 0D4H 7A000H to 7A7FFH 0F4H
4A800H to 4AFFFH 095H 5A800H to 5AFFFH 0B5H 6A800H to 6AFFFH 0D5H 7A800H to 7AFFFH 0F5H
4B000H to 4B7FFH 096H 5B000H to 5B7FFH 0B6H 6B000H to 6B7FFH 0D6H 7B000H to 7B7FFH 0F6H
4B800H to 4BFFFH 097H 5B800H to 5BFFFH 0B7H 6B800H to 6BFFFH 0D7H 7B800H to 7BFFFH 0F7H
4C000H to 4C7FFH 098H 5C000H to 5C7FFH 0B8H 6C000H to 6C7FFH 0D8H 7C000H to 7C7FFH 0F8H
4C800H to 4CFFFH 099H 5C800H to 5CFFFH 0B9H 6C800H to 6CFFFH 0D9H 7C800H to 7CFFFH 0F9H
4D000H to 4D7FFH 09AH 5D000H to 5D7FFH 0BAH 6D000H to 6D7FFH 0DAH 7D000H to 7D7FFH 0FAH
4D800H to 4DFFFH 09BH 5D800H to 5DFFFH 0BBH 6D800H to 6DFFFH 0DBH 7D800H to 7DFFFH 0FBH
4E000H to 4E7FFH 09CH 5E000H to 5E7FFH 0BCH 6E000H to 6E7FFH 0DCH 7E000H to 7E7FFH 0FCH
4E800H to 4EFFFH 09DH 5E800H to 5EFFFH 0BDH 6E800H to 6EFFFH 0DDH 7E800H to 7EFFFH 0FDH
4F000H to 4F7FFH 09EH 5F000H to 5F7FFH 0BEH 6F000H to 6F7FFH 0DEH 7F000H to 7F7FFH 0FEH
4F800H to 4FFFFH 09FH 5F800H to 5FFFFH 0BFH 6F800H to 6FFFFH 0DFH 7F800H to 7FFFFH 0FFH
Remark R7F100GxK (x = F, G, J, L, M, P, S): Block numbers 000H to 0BFH R7F100GxL (x = F, G, J, L, M, P, S): Block numbers 000H to 0FFH
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Table 3 - 3 Correspondence between Addresses and Block Numbers in Flash Memory (3/3)
Address
Block Number
Address
Block Number
Address
Block Number
Address
Block Number
80000H to 807FFH 100H 90000H to 907FFH 120H A0000H to A07FFH 140H B0000H to B07FFH 160H
80800H to 80FFFH 101H 90800H to 90FFFH 121H A0800H to A0FFFH 141H B0800H to B0FFFH 161H
81000H to 817FFH 102H 91000H to 917FFH 122H A1000H to A17FFH 142H B1000H to B17FFH 162H
81800H to 81FFFH 103H 91800H to 91FFFH 123H A1800H to A1FFFH 143H B1800H to B1FFFH 163H
82000H to 827FFH 104H 92000H to 927FFH 124H A2000H to A27FFH 144H B2000H to B27FFH 164H
82800H to 82FFFH 105H 92800H to 92FFFH 125H A2800H to A2FFFH 145H B2800H to B2FFFH 165H
83000H to 837FFH 106H 93000H to 937FFH 126H A3000H to A37FFH 146H B3000H to B37FFH 166H
83800H to 83FFFH 107H 93800H to 93FFFH 127H A3800H to A3FFFH 147H B3800H to B3FFFH 167H
84000H to 847FFH 108H 94000H to 947FFH 128H A4000H to A47FFH 148H B4000H to B47FFH 168H
84800H to 84FFFH 109H 94800H to 94FFFH 129H A4800H to A4FFFH 149H B4800H to B4FFFH 169H
85000H to 857FFH 10AH 95000H to 957FFH 12AH A5000H to A57FFH 14AH B5000H to B57FFH 16AH
85800H to 85FFFH 10BH 95800H to 95FFFH 12BH A5800H to A5FFFH 14BH B5800H to B5FFFH 16BH
86000H to 867FFH 10CH 96000H to 967FFH 12CH A6000H to A67FFH 14CH B6000H to B67FFH 16CH
86800H to 86FFFH 10DH 96800H to 96FFFH 12DH A6800H to A6FFFH 14DH B6800H to B6FFFH 16DH
87000H to 877FFH 10EH 97000H to 977FFH 12EH A7000H to A77FFH 14EH B7000H to B77FFH 16EH
87800H to 87FFFH 10FH 97800H to 97FFFH 12FH A7800H to A7FFFH 14FH B7800H to B7FFFH 16FH
88000H to 887FFH 110H 98000H to 987FFH 130H A8000H to A87FFH 150H B8000H to B87FFH 170H
88800H to 88FFFH 111H 98800H to 98FFFH 131H A8800H to A8FFFH 151H B8800H to B8FFFH 171H
89000H to 897FFH 112H 99000H to 997FFH 132H A9000H to A97FFH 152H B9000H to B97FFH 172H
89800H to 89FFFH 113H 99800H to 99FFFH 133H A9800H to A9FFFH 153H B9800H to B9FFFH 173H
8A000H to 8A7FFH 114H 9A000H to 9A7FFH 134H AA000H to AA7FFH 154H BA000H to BA7FFH 174H
8A800H to 8AFFFH 115H 9A800H to 9AFFFH 135H AA800H to AAFFFH 155H BA800H to BAFFFH 175H
8B000H to 8B7FFH 116H 9B000H to 9B7FFH 136H AB000H to AB7FFH 156H BB000H to BB7FFH 176H
8B800H to 8BFFFH 117H 9B800H to 9BFFFH 137H AB800H to ABFFFH 157H BB800H to BBFFFH 177H
8C000H to 8C7FFH 118H 9C000H to 9C7FFH 138H AC000H to AC7FFH 158H BC000H to BC7FFH 178H
8C800H to 8CFFFH 119H 9C800H to 9CFFFH 139H AC800H to ACFFFH 159H BC800H to BCFFFH 179H
8D000H to 8D7FFH 11AH 9D000H to 9D7FFH 13AH AD000H to AD7FFH 15AH BD000H to BD7FFH 17AH
8D800H to 8DFFFH 11BH 9D800H to 9DFFFH 13BH AD800H to ADFFFH 15BH BD800H to BDFFFH 17BH
8E000H to 8E7FFH 11CH 9E000H to 9E7FFH 13CH AE000H to AE7FFH 15CH BE000H to BE7FFH 17CH
8E800H to 8EFFFH 11DH 9E800H to 9EFFFH 13DH AE800H to AEFFFH 15DH BE800H to BEFFFH 17DH
8F000H to 8F7FFH 11EH 9F000H to 9F7FFH 13EH AF000H to AF7FFH 15EH BF000H to BF7FFH 17EH
8F800H to 8FFFFH 11FH 9F800H to 9FFFFH 13FH AF800H to AFFFFH 15FH BF800H to BFFFFH 17FH
Remark R7F100GxN (x = F, G, J, L, M, P, S): Block numbers 000H to 17FH
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3.1.1 Internal program memory space
The internal program memory holds the program and table data. The RL78/G23 products incorporate the internal ROM (flash memory) with the capacity shown below.
Table 3 - 4 Internal ROM Capacity
Part Number
R7F100GxF (x = A, B, C, E, F, G, J, L) R7F100GxG (x = A, B, C, E, F, G, J, L, M, P) R7F100GxH (x = A, B, C, E, F, G, J, L, M, P) R7F100GxJ (x = A, B, C, E, F, G, J, L, M, P, S) R7F100GxK (x = F, G, J, L, M, P, S) R7F100GxL (x = F, G, J, L, M, P, S) R7F100GxN (x = F, G, J, L, M, P, S)
Structure Flash memory
Internal ROM Capacity
98304 × 8 bits (00000H to 17FFFH) 131072 × 8 bits (00000H to 1FFFFH) 196608 × 8 bits (00000H to 2FFFFH) 262144 × 8 bits (00000H to 3FFFFH) 393216 × 8 bits (00000H to 5FFFFH) 524288 × 8 bits (00000H to 7FFFFH) 786432 × 8 bits (00000H to BFFFFH)
The internal program memory space is divided into the following areas.
(1) Vector table area The 128-byte area 00000H to 0007FH is reserved as a vector table area. The program start addresses for branch upon reset or generation of each interrupt request are stored in the vector table area. Furthermore, the interrupt jump address is a 64 K address of 00000H to 0FFFFH, because the vector code is assumed to be 2 bytes. Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses. To use the boot swap function, set a vector table also at 01000H to 0107FH. Table 3 - 5 lists the vector table. "" indicates an interrupt source which is supported. "--" indicates an interrupt source which is not supported. The vector table address can be changed to an address in RAM when self-programming is to proceed. For details, see 33.6.2.18 Interrupt vector change registers 0 and 1 (FLSIVC0, FLSIVC1).
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Table 3 - 5 Vector Table (1/2)
Vector Table Address
Interrupt Source
128- 100- 80pin pin pin
00000H
RESET, POR, LVD, WDT, TRAP, IAW, RPE
00004H
INTWDTI
00006H
INTLVI
00008H
INTP0
0000AH
INTP1
0000CH
INTP2
0000EH
INTP3
00010H
INTP4
00012H
INTP5
00014H
INTST2/INTCSI20/INTIIC20
00016H
INTSR2/INTCSI21/INTIIC21
00018H
INTSRE2
INTTM11H
0001AH
INTELCL
0001CH
INTSMSE
0001EH
INTST0/INTCSI00/INTIIC00
00020H
INTTM00
00022H
INTSRE0
INTTM01H
00024H
INTST1/INTCSI10/INTIIC10
00026H
INTSR1/INTCSI11/INTIIC11
00028H
INTSRE1
INTTM03H
0002AH
INTIICA0
0002CH
INTSR0/INTCSI01/INTIIC01
0002EH
INTTM01
00030H
INTTM02
00032H
INTTM03
00034H
INTAD
00036H
INTRTC
00038H
INTITL
0003AH
INTKR
0003CH
INTST3/INTCSI30/INTIIC30
0003EH
INTSR3/INTCSI31/INTIIC31
00040H
INTTM13
00042H
INTTM04
00044H
INTTM05
00046H
INTTM06
00048H
INTTM07
64- 52- 48- 44- 40- 36- 32- 30pin pin pin pin pin pin pin pin
Note 1 Note 1
Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2
Note 3 Note 3 Note 3 Note 3 Note 3
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Table 3 - 5 Vector Table (2/2)
Vector Table Address
Interrupt Source
0004AH
INTP6
0004CH
INTP7
0004EH
INTP8
00050H
INTP9
00052H
INTFL
00054H
INTP10
INTCMP0
00056H
INTP11
INTCMP1
00058H
INTURE0
INTTM10
0005AH
INTURE1
INTTM11
0005CH
INTTM12
0005EH
INTSRE3
INTTM13H
00060H
INTCTSUWR
00062H
INTIICA1
00064H
INTCTSURD
00066H
INTCTSUFN
00068H
INTREMC
0006AH
INTUT0
0006CH
INTUR0
0006EH
INTUT1
00070H
INTUR1
00072H
INTTM14
00074H
INTTM15
00076H
INTTM16
00078H
INTTM17
0007AH
0007CH
0007EH
Note 1. Note 2. Note 3.
BRK
INTSR2 is only present in this product. INTST1 is only present in this product. INTSR0 is only present in this product.
CHAPTER 3 CPU ARCHITECTURE
128- 100- 80- 64- 52- 48- 44- 40- 36- 32- 30pin pin pin pin pin pin pin pin pin pin pin
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(2) CALLT instruction table area The 64-byte area 00080H to 000BFH can store the subroutine entry address of a 2-byte call instruction (CALLT). Set the subroutine entry address to a value in a range of 00000H to 0FFFFH (because an address code is 2 bytes). To use the boot swap function, set a CALLT instruction table also at 04080H to 040BFH.
(3) Option bytes area A 4-byte area of 000C0H to 000C3H can be used as an option bytes area. Set the option byte at 040C0H to 040C3H when the boot swap is used. For details, see CHAPTER 32 OPTION BYTES.
(4) On-chip debug security ID setting area A 10-byte area of 000C4H to 000CDH and 040C4H to 040CDH can be used as an on-chip debug security ID setting area. Set the on-chip debug security ID of 10 bytes at 000C4H to 000CDH when the boot swap is not used and at 000C4H to 000CDH and at 040C4H to 040CDH when the boot swap is used. For details, see CHAPTER 34 ON-CHIP DEBUGGING.
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3.1.2 Mirror area
The RL78/G23 mirrors the code flash area of 00000H to 0FFFFH, to F0000H to FFFFFH (the code flash area to be mirrored is set by the processor mode control register (PMC)). By reading data from F0000H to FFFFFH, an instruction that does not have the ES register as an operand can be used, and thus the contents of the code flash can be read with the shorter code. However, the code flash area is not mirrored to the special function registers (SFRs), extended special function registers (2nd SFRs), RAM, data flash memory, and use prohibited areas. See 3.1 Memory Space for the mirror area of each product. The mirror area can only be read and no instruction can be fetched from this area. The following show examples.
Example R7F100GxG (x = A, B, C, E, F, G, J, L, M, P) (Flash memory: 128 Kbytes, RAM: 16 Kbytes)
FFFFFH
Special function registers (SFRs) 256 bytes
FFF00H FFEFFH FFEE0 H FFEDFH
FBF00 H FBEFFH
General -purpose registers 32 bytes
RAM 16 Kbytes
Mirror (same data as in 03000 H to 0BEFFH)
F30 00H F2FFFH
F1000 H F0 FFFH F0800 H F07 FFH
F0000 H EFFFFH
Data flash memory
Reserved
Extended special function registers (2nd SFRs) 2 Kbytes
Mirror
Reserved
For example, 03789 H is mirrored
to F3789 H. Data can therefore be read by MOV A , !3789 H, instead
of MOV ES, #00H and A , ES:!3789 H.
20000 H 1FFFFH
0BEFFH
03000 H 02FFFH 00000 H
Code flash memory Code flash memory Code flash memory
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The PMC register is described below. · Processor mode control register (PMC)
This register sets the flash memory space for mirroring to area from F0000H to FFFFFH. The PMC register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 3 - 8 Format of Processor Mode Control Register (PMC)
Address: After reset: R/W:
FFFFEH 00H R/W
Symbol
7
6
5
4
3
2
1
<0>
PMC
0
0
0
0
0
0
0
MAA
MAA
Selection of flash memory space for mirroring to area from F0000H to FFFFFH
0
00000H to 0FFFFH is mirrored to F0000H to FFFFFH
1
10000H to 1FFFFH is mirrored to F0000H to FFFFFH
Caution 1. After setting the PMC register, wait for at least one instruction and access the mirror area. Caution 2. When boot swapping is executed while bit 0 (MAA) is 0, data at 03000H to 07FFFH are mirrored at
F3000H to F7FFFH after boot swapping.
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3.1.3 Internal data memory space
The RL78/G23 products incorporate the RAM with the capacity shown below.
Table 3 - 6 Internal RAM Capacity
Part Number R7F100GxF (x = A, B, C, E, F, G, J, L) R7F100GxG (x = A, B, C, E, F, G, J, L, M, P) R7F100GxH (x = A, B, C, E, F, G, J, L, M, P) R7F100GxJ (x = A, B, C, E, F, G, J, L, M, P, S) R7F100GxK (x = F, G, J, L, M, P, S) R7F100GxL (x = F, G, J, L, M, P, S) R7F100GxN (x = F, G, J, L, M, P, S)
Internal RAM 12288 × 8 bits (FCF00H to FFEFFH) 16384 × 8 bits (FBF00H to FFEFFH) 20480 × 8 bits (FAF00H to FFEFFH) 24576 × 8 bits (F9F00H to FFEFFH) 32768 × 8 bits (F7F00H to FFEFFH) 49152 × 8 bits (F3F00H to FFEFFH) 49152 × 8 bits (F3F00H to FFEFFH)
The internal RAM can be used as a data area and a program area where instructions are fetched (the space to which the general-purpose registers are allocated cannot be used for instruction fetching). Four general-purpose register banks consisting of eight 8-bit registers per bank are assigned to the 32-byte area of FFEE0H to FFEFFH of the internal RAM area. The internal RAM is used as stack memory. Some areas in the internal memory can be placed in shutdown mode for low-power operation. Data cannot be retained in the areas placed in shutdown mode. For details, see 23.2.2 Memory power reduction control register (PSMCR).
Caution 1. The space to which the general-purpose registers are allocated (FFEE0H to FFEFFH) cannot be used for instruction fetching or the stack.
Caution 2. The internal RAM area in the following products cannot be used as stack memory when using the onchip debugging trace function. R7F100GxG (x = A, B, C, E, F, G, J, L, M, P): FC300H to FC6FFH R7F100GxJ (x = A, B, C, E, F, G, J, L, M, P, S): FA300H to FA6FFH R7F100GxL, R7F100GxN (x = F, G, J, L, M, P, S): F4300H to F46FFH
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3.1.4 Special function register (SFR) area
On-chip peripheral hardware special function registers (SFRs) are allocated in the area FFF00H to FFFFFH (see Table 3 - 7 in 3.2.4 Special function registers (SFRs)).
Caution Do not access addresses to which SFRs are not assigned.
3.1.5 Extended special function register (2nd SFR: 2nd special function register) area
On-chip peripheral hardware special function registers (2nd SFRs) are allocated in the area F0000H to F07FFH (see Table 3 - 8 in 3.2.5 Extended special function registers (2nd SFRs)).
Caution 1. Do not access addresses to which extended SFRs are not assigned. Caution 2. The registers of the capacitive sensing unit (CTSU2L) and random number generator (RNG) are
allocated to the respective address ranges from F0500H to F0535H and F0540H to F0547H in the area for the extended special function registers. The CPU is placed in the wait state and does not proceed to the next instruction during access to the register range for either module. Accordingly, the CPU entering this state lengthens the number of clock cycles to execute an instruction by the number of cycles of waiting. The CPU waits during access to the registers of the capacitive sensing unit (CTSU2L) and random number generator (RNG) in cases of both reading and writing.
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3.1.6 Data memory addressing
Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the RL78/G23, based on operability and other considerations. For areas containing data memory in particular, special addressing methods designed for the functions of the special function registers (SFRs) and general-purpose registers are available for use. Figure 3 - 9 shows correspondence between data memory and addressing. For details of each addressing, see 3.4 Addressing for Processing Data Addresses.
Figure 3 - 9 Correspondence Between Data Memory and Addressing
FFFFFH FFF20H FFF1FH FFF00H FFEFFH
FFEE0 H FFEDFH FFE20 H FFE1FH
Special function registers (SFRs) 256 bytes
General -purpose registers 32 bytes
RAM 12 to 48 Kbytes
SFR addressing Register addressing
Mirror area
F3000H F2FFFH
F0800H F07FFH
Data flash memory 8 Kbytes
Reserved
Extended special function registers (2nd SFRs)
F0000H EFFFFH
Short direct addressing
Direct addressing Register indirect addressing Based addressing Based indexed addressing
Reserved
00000 H
Code flash memory 96 to 768 Kbytes
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3.2
Processor Registers
The RL78/G23 products incorporate the following processor registers.
3.2.1 Control registers
The control registers control the program sequence, state, and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP).
(1) Program counter (PC) The program counter is a 20-bit register that holds the address information of the next program to be executed. In normal operation, PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data and register contents are set. The values of the reset vector table at addresses 0000H and 0001H are set in the program counter following a reset.
Figure 3 - 10 Format of Program Counter
Symbol 19
0
PC
(2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags set/reset by instruction execution. Program status word contents are stored in the stack area upon vectored interrupt request is acknowledged or PUSH PSW instruction execution and are restored upon execution of the RETB, RETI and POP PSW instructions. The value of the PSW is 06H following a reset.
Figure 3 - 11 Format of Program Status Word
Symbol
7
PSW
IE
0
Z
RBS1
AC
RBS0
ISP1
ISP0
CY
(a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupt requests are disabled. When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgment is controlled with an in-service priority flag (ISP1, ISP0), an interrupt mask flag for various interrupt sources, and a priority specification flag. The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI instruction execution.
(b) Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
(c) Register bank select flags (RBS0, RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored.
(d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases.
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(e) In-service priority flags (ISP1, ISP0) This flag manages the priority of acknowledgeable maskable vectored interrupts. Vectored interrupt requests specified lower than the value of ISP0 and ISP1 flags by the priority specification flag registers (PRn0L, PRn0H, PRn1L, PRn1H, PRn2L, PRn2H, PRn3L, and PRn3H; see 21.3.3 Priority specification flag registers) cannot be acknowledged. Actual request acknowledgment is controlled by the interrupt enable flag (IE).
Remark n = 0, 1
(f) Carry flag (CY) This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution.
(3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal RAM area can be set as the stack area.
Figure 3 - 12 Format of Stack Pointer
Symbol
15
14
13
12
11
10
9
8
SP SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
7
6
5
4
3
2
1
0
SP7
SP6
SP5
SP4
SP3
SP2
SP1
0
In stack addressing through a stack pointer, the SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore) from the stack memory.
Caution 1. Since the contents of the SP become undefined following a reset, be sure to initialize the SP before using the stack.
Caution 2. The space to which the general-purpose registers are allocated (FFEE0H to FFEFFH) cannot be used for instruction fetching or the stack.
Caution 3. The internal RAM area in the following products cannot be used as stack memory when using the onchip debugging trace function. R7F100GxG (x = A, B, C, E, F, G, J, L, M, P): FC300H to FC6FFH R7F100GxJ (x = A, B, C, E, F, G, J, L, M, P, S): FA300H to FA6FFH R7F100GxL, R7F100GxN (x = F, G, J, L, M, P, S): F4300H to F46FFH
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3.2.2 General-purpose registers
General-purpose registers are mapped at particular addresses (FFEE0H to FFEFFH) of the data memory. The generalpurpose registers consist of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL). Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of the 4register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupt processing for each bank.
Caution
The space to which the general-purpose registers are allocated (FFEE0H to FFEFFH) cannot be used for instruction fetching or the stack.
Figure 3 - 13 Configuration of General-Purpose Registers (a) Function name
FFEFFH FFEF8H
Register bank 0
FFEF0H
Register bank 1
FFEE8H
Register bank 2
FFEE0H
Register bank 3
16-bit processing HL
DE
BC
AX
15
0
8-bit processing H
L
D
E
B
C
A
X
7
0
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3.2.3 ES and CS registers
The ES register and CS register are used to specify the higher address for data access and when a branch instruction is executed (register indirect addressing), respectively. The default value of the ES register after reset is 0FH, and that of the CS register is 00H.
Figure 3 - 14 Configuration of ES and CS Registers
Symbol
7
6
5
4
ES
0
0
0
0
Symbol
7
6
5
4
CS
0
0
0
0
3
2
1
0
ES3
ES2
ES1
ES0
3
2
1
0
CS3
CS2
ES1
ES0
Though the data area which can be accessed with 16-bit addresses is the 64 Kbytes from F0000H to FFFFFH, using the ES register as well extends this to the 1 Mbyte from 00000H to FFFFFH.
Figure 3 - 15 Extension of Data Area Which Can Be Accessed
!addr16 ES:!addr16
F 0000H to FFFFH 0H to FH 0000H to FFFFH
FFFFFH Special function registers (SFRs) 256 bytes
!addr16
ES:!addr16
Extended special function registers
F0000H
(2nd SFRs) 2 Kbytes
EFFFFH
Data memory space
00000H
Code flash memory
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3.2.4 Special function registers (SFRs)
Unlike a general-purpose register, each SFR has a special function. SFRs are allocated to the FFF00H to FFFFFH area. SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions. The manipulable bit units, 1, 8, and 16, depend on the SFR type. Each manipulation bit unit can be specified as follows.
· 1-bit manipulation Describe as follows for the 1-bit manipulation instruction operand (sfr.bit). When the bit name is defined: <Bit name> When the bit name is not defined: <Register name>, <Bit number> or <Address>, <Bit number> · 8-bit manipulation Describe the symbol defined by the assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified with an address. · 16-bit manipulation Describe the symbol defined by the assembler for the 16-bit manipulation instruction operand (sfrp). When specifying an address, describe an even address.
Table 3 - 7 give lists of the SFRs. The meanings of items in the table are as follows.
· Symbol This item indicates the address of a special function register. It is a reserved word in the assembler, and is defined as an sfr variable using the #pragma sfr directive in the compiler. When using the assembler, debugger, and simulator, symbols can be written as an instruction operand. · R/W This item indicates whether the corresponding SFR can be read or written. R/W: Read/write enable R: Read only W: Write only · Manipulable bit units "" indicates the manipulable bit unit (1, 8, or 16). "--" indicates a bit unit for which manipulation is not possible. · After reset Items in this column indicate the states (values) of each of the registers after generation of a reset signal.
Caution Do not access addresses to which SFRs are not assigned.
Remark For extended SFRs (2nd SFRs), see 3.2.5 Extended special function registers (2nd SFRs).
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Table 3 - 7 List of Special Function Registers (SFRs) (1/4)
Address
Special Function Register (SFR) Name
Symbol
R/W
FFF00H FFF01H FFF02H
Port register 0 Port register 1 Port register 2
P0
R/W
P1
R/W
P2
R/W
FFF03H Port register 3
P3
R/W
FFF04H FFF05H FFF06H FFF07H FFF08H
Port register 4 Port register 5 Port register 6 Port register 7 Port register 8
P4
R/W
P5
R/W
P6
R/W
P7
R/W
P8
R/W
FFF09H Port register 9
P9
R/W
FFF0AH FFF0BH FFF0CH FFF0DH FFF0EH
Port register 10 Port register 11 Port register 12 Port register 13 Port register 14
P10
R/W
P11
R/W
P12
R/W
P13
R/W
P14
R/W
FFF0FH Port register 15
P15
R/W
FFF10H Serial data register 00
FFF11H FFF12H
Serial data register 01
FFF13H FFF14H
Serial data register 12
FFF15H
TXD0/ SDR00 R/W SIO00
RXD0/ SDR01 R/W SIO01
TXD3/ SDR12 R/W SIO30
FFF16H Serial data register 13
RXD3/ SDR13 R/W SIO31
FFF17H
FFF18H FFF19H FFF1AH FFF1BH FFF1EH
Timer data register 00 Timer data register 01 12-bit/10-bit A/D conversion result register
TDR00
R/W
TDR01L TDR01 R/W
TDR01H
ADCR
R
FFF1FH
8-bit A/D conversion result register
ADCRH
R
FFF20H FFF21H FFF22H FFF23H FFF24H
Port mode register 0 Port mode register 1 Port mode register 2 Port mode register 3 Port mode register 4
PM0
R/W
PM1
R/W
PM2
R/W
PM3
R/W
PM4
R/W
FFF25H Port mode register 5
PM5
R/W
FFF26H FFF27H FFF28H FFF29H FFF2AH
Port mode register 6 Port mode register 7 Port mode register 8 Port mode register 9 Port mode register 10
PM6
R/W
PM7
R/W
PM8
R/W
PM9
R/W
PM10
R/W
FFF2BH Port mode register 11
PM11
R/W
FFF2CH FFF2EH FFF2FH
Port mode register 12 Port mode register 14 Port mode register 15
PM12
R/W
PM14
R/W
PM15
R/W
Manipulable Bit Range After Reset
1 bit 8 bits 16 bits
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
Undefined
Undefined
00H
00H
0000H
0000H
0000H
0000H
0000H
00H
00H
0000H
00H
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
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Table 3 - 7 List of Special Function Registers (SFRs) (2/4)
Address
Special Function Register (SFR) Name
Symbol
R/W
FFF30H A/D converter mode register 0
ADM0
R/W
FFF31H Analog input channel specification register
ADS
R/W
FFF32H A/D converter mode register 1
ADM1
R/W
FFF34H Key return control register
KRCTL
R/W
FFF35H Key return flag register
KRF
R/W
FFF37H Key return mode register 0
KRM0
R/W
FFF38H External interrupt rising edge enable register 0
EGP0
R/W
FFF39H External interrupt falling edge enable register 0
EGN0
R/W
FFF3AH External interrupt rising edge enable register 1
EGP1
R/W
FFF3BH External interrupt falling edge enable register 1
EGN1
R/W
FFF44H Serial data register 02
FFF45H FFF46H
Serial data register 03
FFF47H FFF48H
Serial data register 10
FFF49H
TXD1/ SDR02 R/W SIO10
RXD1/ SDR03 R/W SIO11
TXD2/ SDR10 R/W SIO20
FFF4AH Serial data register 11
RXD2/ SDR11 R/W SIO21
FFF4BH
FFF50H FFF51H FFF52H FFF54H FFF55H
IICA shift register 0 IICA status register 0 IICA flag register 0 IICA shift register 1 IICA status register 1
IICA0
R/W
IICS0
R
IICF0
R/W
IICA1
R/W
IICS1
R
FFF56H IICA flag register 1
IICF1
R/W
FFF64H FFF65H FFF66H FFF67H FFF68H
Timer data register 02 Timer data register 03 Timer data register 04
TDR02
R/W
TDR03L TDR03 R/W
TDR03H
TDR04
R/W
FFF69H
FFF6AH FFF6BH FFF6CH FFF6DH FFF6EH
Timer data register 05 Timer data register 06 Timer data register 07
TDR05
R/W
TDR06
R/W
TDR07
R/W
FFF6FH
FFF70H FFF71H FFF72H FFF73H FFF74H
Timer data register 10 Timer data register 11 Timer data register 12
TDR10
R/W
TDR11L TDR11 R/W
TDR11H
TDR12
R/W
FFF75H
FFF76H FFF77H
Timer data register 13
TDR13L TDR13 R/W TDR13H
Manipulable Bit Range After Reset
1 bit 8 bits 16 bits
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
0000H
0000H
0000H
0000H
00H
00H
00H
00H
00H
00H
0000H
00H 00H
0000H
0000H
0000H
0000H
0000H
00H 00H
0000H
00H 00H
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Table 3 - 7 List of Special Function Registers (SFRs) (3/4)
Address
Special Function Register (SFR) Name
Symbol
Manipulable Bit Range
R/W
After Reset
1 bit 8 bits 16 bits
FFF78H Timer data register 14
TDR14
R/W
0000H
FFF79H
FFF7AH Timer data register 15
TDR15
R/W
0000H
FFF7BH
FFF7CH Timer data register 16
TDR16
R/W
0000H
FFF7DH
FFF7EH Timer data register 17
TDR17
R/W
0000H
FFF7FH
FFFA0H Clock operation mode control register
CMC
R/W
00H
FFFA1H Clock operation status control register
CSC
R/W
C0H
FFFA2H Oscillation stabilization time counter status register OSTC
R
00H
FFFA3H Oscillation stabilization time select register
OSTS
R/W
07H
FFFA4H System clock control register
CKC
R/W
00H
FFFA5H Clock output select register 0
CKS0
R/W
00H
FFFA6H Clock output select register 1
CKS1
R/W
00H
FFFA7H Subsystem clock select register
CKSEL
R/W
00H
FFFA8H Reset control flag register
RESF
R
Undefined
Note 1
FFFA9H Voltage detection register
LVIM
R/W
00HNote 2
FFFAAH Voltage detection level register
LVIS
R/W
19H
FFFABH Watchdog timer enable register
WDTE
R/W
9AH/
1AHNote 3
FFFACH CRC input register
CRCIN
R/W
00H
FFFD0H Interrupt request flag register 2
IF2L
IF2
R/W
00H
FFFD1H
IF2H
R/W
00H
FFFD2H Interrupt request flag register 3
IF3L
IF3
R/W
00H
FFFD3H
IF3H
R/W
00H
FFFD4H Interrupt mask flag register 2
MK2L MK2
R/W
FFH
FFFD5H
MK2H
R/W
FFH
FFFD6H Interrupt mask flag register 3
MK3L MK3
R/W
FFH
FFFD7H
MK3H
R/W
FFH
FFFD8H Priority specification flag register 02
PR02L PR02 R/W
FFH
FFFD9H
PR02H
R/W
FFH
FFFDAH Priority specification flag register 03
PR03L PR03 R/W
FFH
FFFDBH
PR03H
R/W
FFH
FFFDCH Priority specification flag register 12
PR12L PR12 R/W
FFH
FFFDDH
PR12H
R/W
FFH
FFFDEH Priority specification flag register 13
PR13L PR13 R/W
FFH
FFFDFH
PR13H
R/W
FFH
FFFE0H Interrupt request flag register 0
IF0L
IF0
R/W
00H
FFFE1H
IF0H
R/W
00H
FFFE2H Interrupt request flag register 1
IF1L
IF1
R/W
00H
FFFE3H
IF1H
R/W
00H
FFFE4H Interrupt mask flag register 0
MK0L MK0
R/W
FFH
FFFE5H
MK0H
R/W
FFH
FFFE6H Interrupt mask flag register 1
MK1L MK1
R/W
FFH
FFFE7H
MK1H
R/W
FFH
FFFE8H Priority specification flag register 00
PR00L PR00 R/W
FFH
FFFE9H
PR00H
R/W
FFH
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Table 3 - 7 List of Special Function Registers (SFRs) (4/4)
Address
Special Function Register (SFR) Name
Symbol
Manipulable Bit Range
R/W
After Reset
1 bit 8 bits 16 bits
FFFEAH Priority specification flag register 01
PR01L PR01 R/W
FFH
FFFEBH
PR01H
R/W
FFH
FFFECH Priority specification flag register 10
PR10L PR10 R/W
FFH
FFFEDH
PR10H
R/W
FFH
FFFEEH Priority specification flag register 11
PR11L PR11 R/W
FFH
FFFEFH
PR11H
R/W
FFH
FFFF0H Multiply and accumulation register (L)
MACRL
R/W
0000H
FFFF1H
FFFF2H Multiply and accumulation register (H)
MACRH
R/W
0000H
FFFF3H
FFFFEH Processor mode control register
PMC
R/W
00H
Note 1. For the reset resources, see CHAPTER 24 RESET FUNCTION.
Note 2. The initial value depends on the source of the reset. See 26.3.1 Voltage detection register (LVIM).
Note 3. The reset value of the WDTE register is determined by the setting of the option byte.
Remark For extended SFRs (2nd SFRs), see Table 3 - 8 List of Extended Special Function Registers (2nd SFRs).
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CHAPTER 3 CPU ARCHITECTURE
3.2.5 Extended special function registers (2nd SFRs)
Unlike a general-purpose register, each extended SFR (2nd SFR) has a special function. Extended SFRs are allocated to the F0000H to F07FFH area. SFRs other than those in the SFR area (FFF00H to FFFFFH) are allocated to this area. An instruction that accesses the extended SFR area, however, is 1 byte longer than an instruction that accesses the SFR area. Extended SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions. The manipulable bit units, 1, 8, and 16, depend on the SFR type. Each manipulation bit unit can be specified as follows.
· 1-bit manipulation Describe as follows for the 1-bit manipulation instruction operand (!addr16.bit) When the bit name is defined: <Bit name> When the bit name is not defined: <Register name>, <Bit number> or <Address>, <Bit number> · 8-bit manipulation Describe the symbol defined by the assembler for the 8-bit manipulation instruction operand (!addr16). This manipulation can also be specified with an address. · 16-bit manipulation Describe the symbol defined by the assembler for the 16-bit manipulation instruction operand (!addr16). When specifying an address, describe an even address. Table 3 - 8 give lists of the extended SFRs. The meanings of items in the table are as follows. · Symbol This item indicates the address of an extended SFR. It is a reserved word in the assembler, and is defined as an sfr variable using the #pragma sfr directive in the compiler. When using the assembler, debugger, and simulator, symbols can be written as an instruction operand. · R/W This item indicates whether the corresponding extended SFR can be read or written. R/W: Read/write enable R: Read only W: Write only · Manipulable bit units "" indicates the manipulable bit unit (1, 8, or 16). "" indicates a bit unit for which manipulation is not possible. · After reset Items in this column indicate the states (values) of each of the registers after generation of a reset signal.
Caution Do not access addresses to which extended SFRs (2nd SFRs) are not assigned. Remark For SFRs in the SFR area, see 3.1.4 Special function register (SFR) area.
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Table 3 - 8 List of Extended Special Function Registers (2nd SFRs) (1/15)
Address Special Function Register (SFR) Name
Symbol
R/W
F0010H A/D converter mode register 2
F0011H Conversion result comparison upper limit setting register
F0012H Conversion result comparison lower limit setting register
F0013H A/D test register
F0020H 12-bit/10-bit A/D conversion result register 0
F0021H
8-bit A/D conversion result register 0
F0022H 12-bit/10-bit A/D conversion result register 1
F0023H
8-bit A/D conversion result register 1
F0024H 12-bit/10-bit A/D conversion result register 2
F0025H
8-bit A/D conversion result register 2
F0026H 12-bit/10-bit A/D conversion result register 3
F0027H
8-bit A/D conversion result register 3
F0030H Pull-up resistor option register 0
F0031H Pull-up resistor option register 1
F0033H Pull-up resistor option register 3
F0034H Pull-up resistor option register 4
F0035H Pull-up resistor option register 5
F0036H Pull-up resistor option register 6
F0037H Pull-up resistor option register 7
F0038H Pull-up resistor option register 8
F0039H Pull-up resistor option register 9
F003AH Pull-up resistor option register 10
F003BH Pull-up resistor option register 11
F003CH Pull-up resistor option register 12
F003EH Pull-up resistor option register 14
F0040H Port input mode register 0
F0041H Port input mode register 1
F0043H Port input mode register 3
F0044H Port input mode register 4
F0045H Port input mode register 5
F0047H Port input mode register 7
F0048H Port input mode register 8
F004EH Port input mode register 14
F0050H Port output mode register 0
F0051H Port output mode register 1
F0053H Port output mode register 3
F0054H Port output mode register 4
F0055H Port output mode register 5
F0057H Port output mode register 7
F0058H Port output mode register 8
F0059H Port output mode register 9
F005CH Port output mode register 12
F005EH Port output mode register 14
F0060H Port mode control A register 0
F0061H Port mode control A register 1
F0062H Port mode control A register 2
ADM2 ADUL
ADLL
ADTES ADCR0H ADCR1H ADCR2H ADCR3H PU0 PU1 PU3 PU4 PU5 PU6 PU7 PU8 PU9 PU10 PU11 PU12 PU14 PIM0 PIM1 PIM3 PIM4 PIM5 PIM7 PIM8 PIM14 POM0 POM1 POM3 POM4 POM5 POM7 POM8 POM9 POM12 POM14 PMCA0 PMCA1 PMCA2
R/W R/W
R/W
R/W ADCR0 R
R ADCR1 R
R ADCR2 R
R ADCR3 R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Manipulable Bit Range 1-bit 8-bit 16-bit
After Reset
00H FFH
00H
00H
0000H
00H
0000H
00H
0000H
00H
0000H
00H
00H
00H
00H
01H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
FFH
FFH
FFH
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Table 3 - 8 List of Extended Special Function Registers (2nd SFRs) (2/15)
Address Special Function Register (SFR) Name
Symbol
R/W
F0063H Port mode control A register 3
PMCA3
R/W
F006AH Port mode control A register 10
PMCA10
R/W
F006BH Port mode control A register 11
PMCA11
R/W
F006CH Port mode control A register 12
PMCA12
R/W
F006EH Port mode control A register 14
PMCA14
R/W
F006FH Port mode control A register 15
PMCA15
R/W
F0070H Noise filter enable register 0
NFEN0
R/W
F0071H Noise filter enable register 1
NFEN1
R/W
F0072H Noise filter enable register 2
NFEN2
R/W
F0073H Input switch control register
ISC
R/W
F0074H Timer input select register 0
TIS0
R/W
F0075H Timer input select register 1
TIS1
R/W
F0077H Peripheral I/O redirection register
PIOR
R/W
F0078H Invalid memory access detection control
IAWCTL
R/W
register
F0079H UART loop back select register
ULBS
R/W
F007BH Port mode select register
PMS
R/W
F007DH Global digital input disable register
GDIDIS
R/W
F0090H Data flash control register
DFLCTL
R/W
F00A0H High-speed on-chip oscillator trimming register HIOTRM
R/W
F00A8H High-speed on-chip oscillator frequency select HOCODIV
R/W
register
F00AAH Flash operating mode select register
FLMODE
R/W
F00ABH Flash operating mode protect register
FLMWRP
R/W
F00B0H Flash security flag monitor register
FLSEC
R
F00B2H Flash FSW monitor register S
FLFSWS
R
F00B4H Flash FSW monitor register E
FLFSWE
R
F00B6H Flash memory sequencer initial setting register FSSET
R/W
F00B7H Flash extra sequencer control register
FSSE
R/W
F00C0H Flash protect command register
PFCMD
R/W
F00C1H Flash status register
PFS
R
F00F0H Peripheral enable register 0
PER0
R/W
F00F1H Peripheral reset control register 0
PRR0
R/W
F00F2H Middle-speed on-chip oscillator frequency MOCODIV
R/W
select register
F00F3H Subsystem clock supply mode control register OSMC
R/W
F00F5H RAM parity error control register
RPECTL
R/W
F00F9H Power-on-reset status register
PORSR
R/W
F00FAH Peripheral enable register 1
PER1
R/W
F00FBH Peripheral reset control register 1
PRR1
R/W
F00FEH BCD correction result register
BCDADJ
R
F00FFH Interrupt vector jump enable register
VECTCTRL
R/W
F0100H Serial status register 00
SSR00L
SSR00
R
F0101H
F0102H Serial status register 01
SSR01L
SSR01
R
F0103H
F0104H Serial status register 02
SSR02L
SSR02
R
F0105H
Manipulable Bit Range 1-bit 8-bit 16-bit
After Reset
FFH FFH FFH FFH FFH FFH 00H 00H 00H 00H 00H 00H 00H 00H
00H
00H
00H
00H
Undefined
Note 1
Undefined
Note 2
40H/80H/C0H
Note 3
00H
Undefined
Undefined
Undefined
00H
00H
00H
00H
00H
00H
Undefined
00H
00H
00H
00H
Undefined
00H
0000H
0000H
0000H
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CHAPTER 3 CPU ARCHITECTURE
Table 3 - 8 List of Extended Special Function Registers (2nd SFRs) (3/15)
Address Special Function Register (SFR) Name
Symbol
R/W
F0106H Serial status register 03 F0107H F0108H Serial flag clear trigger register 00 F0109H F010AH Serial flag clear trigger register 01 F010BH F010CH Serial flag clear trigger register 02 F010DH F010EH Serial flag clear trigger register 03 F010FH F0110H Serial mode register 00 F0111H F0112H Serial mode register 01 F0113H F0114H Serial mode register 02 F0115H F0116H Serial mode register 03 F0117H F0118H Serial communication operation setting F0119H register 00 F011AH Serial communication operation setting F011BH register 01 F011CH Serial communication operation setting F011DH register 02 F011EH Serial communication operation setting F011FH register 03 F0120H Serial channel enable status register 0 F0121H F0122H Serial channel start register 0 F0123H F0124H Serial channel stop register 0 F0125H F0126H Serial clock select register 0 F0127H F0128H Serial output register 0 F0129H F012AH Serial output enable register 0 F012BH F0134H Serial output level register 0 F0135H F0138H Serial standby control register 0 F0139H F0140H Serial status register 10 F0141H F0142H Serial status register 11 F0143H F0144H Serial status register 12 F0145H
SSR03L SIR00L SIR01L SIR02L SIR03L SMR00
SMR01
SMR02
SMR03
SCR00
SCR01
SCR02
SCR03
SE0L SS0L ST0L SPS0L SO0
SOE0L SOL0L SSC0L SSR10L SSR11L SSR12L
SSR03
R
SIR00 R/W
SIR01 R/W
SIR02 R/W
SIR03 R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SE0
R
SS0
R/W
ST0
R/W
SPS0
R/W
R/W
SOE0 R/W
SOL0
R/W
SSC0
R/W
SSR10
R
SSR11
R
SSR12
R
Manipulable Bit Range 1-bit 8-bit 16-bit
After Reset 0000H 0000H 0000H 0000H 0000H 0020H
0020H
0020H
0020H
0087H
0087H
0087H
0087H
0000H 0000H 0000H 0000H 0F0FH
0000H 0000H 0000H 0000H 0000H 0000H
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CHAPTER 3 CPU ARCHITECTURE
Table 3 - 8 List of Extended Special Function Registers (2nd SFRs) (4/15)
Address Special Function Register (SFR) Name
Symbol
R/W
F0146H Serial status register 13 F0147H F0148H Serial flag clear trigger register 10 F0149H F014AH Serial flag clear trigger register 11 F014BH F014CH Serial flag clear trigger register 12 F014DH F014EH Serial flag clear trigger register 13 F014FH F0150H Serial mode register 10 F0151H F0152H Serial mode register 11 F0153H F0154H Serial mode register 12 F0155H F0156H Serial mode register 13 F0157H F0158H Serial communication operation setting F0159H register 10 F015AH Serial communication operation setting F015BH register 11 F015CH Serial communication operation setting F015DH register 12 F015EH Serial communication operation setting F015FH register 13 F0160H Serial channel enable status register 1 F0161H F0162H Serial channel start register 1 F0163H F0164H Serial channel stop register 1 F0165H F0166H Serial clock select register 1 F0167H F0168H Serial output register 1 F0169H F016AH Serial output enable register 1 F016BH F0174H Serial output level register 1 F0175H F0178H Serial standby control register 1 F0179H F0180H Timer counter register 00 F0181H F0182H Timer counter register 01 F0183H F0184H Timer counter register 02 F0185H
SSR13L SIR10L SIR11L SIR12L SIR13L SMR10
SMR11
SMR12
SMR13
SCR10
SCR11
SCR12
SCR13
SE1L SS1L ST1L SPS1L SO1
SOE1L SOL1L SSC1L TCR00
TCR01
TCR02
SSR13
R
SIR10 R/W
SIR11 R/W
SIR12 R/W
SIR13 R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SE1
R
SS1
R/W
ST1
R/W
SPS1
R/W
R/W
SOE1 R/W
SOL1
R/W
SSC1
R/W
R
R
R
Manipulable Bit Range 1-bit 8-bit 16-bit
After Reset 0000H 0000H 0000H 0000H 0000H 0020H
0020H
0020H
0020H
0087H
0087H
0087H
0087H
0000H 0000H 0000H 0000H 0F0FH
0000H 0000H 0000H FFFFH
FFFFH
FFFFH
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RL78/G23
CHAPTER 3 CPU ARCHITECTURE
Table 3 - 8 List of Extended Special Function Registers (2nd SFRs) (5/15)
Address Special Function Register (SFR) Name
Symbol
R/W
F0186H Timer counter register 03 F0187H F0188H Timer counter register 04 F0189H F018AH Timer counter register 05 F018BH F018CH Timer counter register 06 F018DH F018EH Timer counter register 07 F018FH F0190H Timer mode register 00 F0191H F0192H Timer mode register 01 F0193H F0194H Timer mode register 02 F0195H F0196H Timer mode register 03 F0197H F0198H Timer mode register 04 F0199H F019AH Timer mode register 05 F019BH F019CH Timer mode register 06 F019DH F019EH Timer mode register 07 F019FH F01A0H Timer status register 00 F01A1H F01A2H Timer status register 01 F01A3H F01A4H Timer status register 02 F01A5H F01A6H Timer status register 03 F01A7H F01A8H Timer status register 04 F01A9H F01AAH Timer status register 05 F01ABH F01ACH Timer status register 06 F01ADH F01AEH Timer status register 07 F01AFH F01B0H Timer channel enable status register 0 F01B1H F01B2H Timer channel start register 0 F01B3H F01B4H Timer channel stop register 0 F01B5H
TCR03
TCR04
TCR05
TCR06
TCR07
TMR00
TMR01
TMR02
TMR03
TMR04
TMR05
TMR06
TMR07
TSR00L TSR01L TSR02L TSR03L TSR04L TSR05L TSR06L TSR07L TE0L TS0L TT0L
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TSR00
R
TSR01
R
TSR02
R
TSR03
R
TSR04
R
TSR05
R
TSR06
R
TSR07
R
TE0
R
TS0
R/W
TT0
R/W
Manipulable Bit Range 1-bit 8-bit 16-bit
After Reset FFFFH
FFFFH
FFFFH
FFFFH
FFFFH
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H
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RL78/G23
CHAPTER 3 CPU ARCHITECTURE
Table 3 - 8 List of Extended Special Function Registers (2nd SFRs) (6/15)
Address Special Function Register (SFR) Name
Symbol
R/W
F01B6H Timer clock select register 0 F01B7H F01B8H Timer output register 0 F01B9H F01BAH Timer output enable register 0 F01BBH F01BCH Timer output level register 0 F01BDH F01BEH Timer output mode register 0 F01BFH F01C0H Timer counter register 10 F01C1H F01C2H Timer counter register 11 F01C3H F01C4H Timer counter register 12 F01C5H F01C6H Timer counter register 13 F01C7H F01C8H Timer counter register 14 F01C9H F01CAH Timer counter register 15 F01CBH F01CCH Timer counter register 16 F01CDH F01CEH Timer counter register 17 F01CFH F01D0H Timer mode register 10 F01D1H F01D2H Timer mode register 11 F01D3H F01D4H Timer mode register 12 F01D5H F01D6H Timer mode register 13 F01D7H F01D8H Timer mode register 14 F01D9H F01DAH Timer mode register 15 F01DBH F01DCH Timer mode register 16 F01DDH F01DEH Timer mode register 17 F01DFH F01E0H Timer status register 10 F01E1H F01E2H Timer status register 11 F01E3H F01E4H Timer status register 12 F01E5H
TPS0
TO0L TOE0L TOL0L TOM0L TCR10
TCR11
TCR12
TCR13
TCR14
TCR15
TCR16
TCR17
TMR10
TMR11
TMR12
TMR13
TMR14
TMR15
TMR16
TMR17
TSR10L TSR11L TSR12L
R/W
TO0
R/W
TOE0
R/W
TOL0
R/W
TOM0 R/W
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TSR10
R
TSR11
R
TSR12
R
Manipulable Bit Range 1-bit 8-bit 16-bit
After Reset 0000H
0000H 0000H 0000H 0000H FFFFH
FFFFH
FFFFH
FFFFH
FFFFH
FFFFH
FFFFH
FFFFH
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H 0000H 0000H
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 143 of 1478
RL78/G23
CHAPTER 3 CPU ARCHITECTURE
Table 3 - 8 List of Extended Special Function Registers (2nd SFRs) (7/15)
Address Special Function Register (SFR) Name
Symbol
R/W
F01E6H Timer status register 13
TSR13L
TSR13
R
F01E7H
F01E8H Timer status register 14
TSR14L
TSR14
R
F01E9H
F01EAH Timer status register 15
TSR15L
TSR15
R
F01EBH
F01ECH Timer status register 16
TSR16L
TSR16
R
F01EDH
F01EEH Timer status register 17
TSR17L
TSR17
R
F01EFH
F01F0H Timer channel enable status register 1
TE1L
TE1
R
F01F1H
F01F2H Timer channel start register 1
TS1L
TS1
R/W
F01F3H
F01F4H Timer channel stop register 1
TT1L
TT1
R/W
F01F5H
F01F6H Timer clock select register 1
TPS1
R/W
F01F7H
F01F8H Timer output register 1
TO1L
TO1
R/W
F01F9H
F01FAH Timer output enable register 1
TOE1L
TOE1
R/W
F01FBH
F01FCH Timer output level register 1
TOL1L
TOL1
R/W
F01FDH
F01FEH Timer output mode register 1
TOM1L
TOM1 R/W
F01FFH
F0212H Middle-speed on-chip oscillator trimming
MIOTRM
R/W
register
F0213H Low-speed on-chip oscillator trimming register LIOTRM
R/W
F0214H High-speed system clock division register
MOSCDIV
R/W
F0215H Standby mode release setting register
WKUPMD
R/W
F0216H Memory power reduction control register
PSMCR
R/W
F0218H LVD detection flag clear register
LVDFCLR
R/W
F0220H Second count register
SEC
R/W
F0221H Minute count register
MIN
R/W
F0222H Hour count register
HOUR
R/W
F0223H Day-of-week count register
WEEK
R/W
F0224H Day count register
DAY
R/W
F0225H Month count register
MONTH
R/W
F0226H Year count register
YEAR
R/W
F0227H Time error correction register
SUBCUD
R/W
F0228H Alarm minute register
ALARMWM
R/W
F0229H Alarm hour register
ALARMWH
R/W
F022AH Alarm day-of-week register
ALARMWW
R/W
F022BH Realtime clock control register 0
RTCC0
R/W
F022CH Realtime clock control register 1
RTCC1
R/W
F0230H IICA control register 00
IICCTL00
R/W
F0231H IICA control register 01
IICCTL01
R/W
F0232H IICA low-level width setting register 0
IICWL0
R/W
Manipulable Bit Range 1-bit 8-bit 16-bit
After Reset 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 80H
80H
00H
00H
00H
00H
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
00H
Undefined
Undefined
Undefined
00H
00H
00H
00H
FFH
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Page 144 of 1478
RL78/G23
CHAPTER 3 CPU ARCHITECTURE
Table 3 - 8 List of Extended Special Function Registers (2nd SFRs) (8/15)
Address Special Function Register (SFR) Name
Symbol
R/W
F0233H IICA high-level width setting register 0
IICWH0
R/W
F0234H Slave address register 0
SVA0
R/W
F0238H IICA control register 10
IICCTL10
R/W
F0239H IICA control register 11
IICCTL11
R/W
F023AH IICA low-level width setting register 1
IICWL1
R/W
F023BH IICA high-level width setting register 1
IICWH1
R/W
F023CH Slave address register 1
SVA1
R/W
F0260H Port mode control T register 0
PMCT0
R/W
F0262H Port mode control T register 2
PMCT2
R/W
F0263H Port mode control T register 3
PMCT3
R/W
F0265H Port mode control T register 5
PMCT5
R/W
F0266H Port mode control T register 6
PMCT6
R/W
F0267H Port mode control T register 7
PMCT7
R/W
F026FH Port mode control T register 15
PMCT15
R/W
F0280H Port mode control E register 0
PMCE0
R/W
F0281H Port mode control E register 1
PMCE1
R/W
F0285H Port mode control E register 5
PMCE5
R/W
F0286H Port mode control E register 6
PMCE6
R/W
F02A0H Output current select register 0
CCS0
R/W
F02A4H Output current select register 4
CCS4
R/W
F02A5H Output current select register 5
CCS5
R/W
F02A6H Output current select register 6
CCS6
R/W
F02A7H Output current select register 7
CCS7
R/W
F02A8H Output current control enable register
CCDE
R/W
F02A9H 40-mA port output control register
PTDC
R/W
F02AAH Port function output enable register 0
PFOE0
R/W
F02ABH Port function output enable register 1
PFOE1
R/W
F02B0H Port digital input disable register 0
PDIDIS0
R/W
F02B1H Port digital input disable register 1
PDIDIS1
R/W
F02B3H Port digital input disable register 3
PDIDIS3
R/W
F02B4H Port digital input disable register 4
PDIDIS4
R/W
F02B5H Port digital input disable register 5
PDIDIS5
R/W
F02B7H Port digital input disable register 7
PDIDIS7
R/W
F02B8H Port digital input disable register 8
PDIDIS8
R/W
F02B9H Port digital input disable register 9
PDIDIS9
R/W
F02BCH Port digital input disable register 12
PDIDIS12
R/W
F02BDH Port digital input disable register 13
PDIDIS13
R/W
F02BEH Port digital input disable register 14
PDIDIS14
R/W
F02C0H Flash programming mode control register
FLPMC
R/W
F02C1H Flash area selection register
FLARS
R/W
F02C2H Flash address pointer register L
FLAPL
R/W
F02C4H Flash address pointer register H
FLAPH
R/W
F02C5H Flash memory sequencer control register
FSSQ
R/W
F02C6H Flash end address pointer register L
FLSEDL
R/W
F02C8H Flash end address pointer register H
FLSEDH
R/W
F02C9H Flash registers initialization register
FLRST
R/W
F02CAH Flash memory sequencer status register L FSASTL
R
F02CBH Flash memory sequencer status register H FSASTH
R
Manipulable Bit Range 1-bit 8-bit 16-bit
After Reset
FFH 00H 00H 00H FFH FFH 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H FFH FFH 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 08H 00H 0000H 00H 00H 0000H 00H 00H 00H 00H
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Page 145 of 1478
RL78/G23
CHAPTER 3 CPU ARCHITECTURE
Table 3 - 8 List of Extended Special Function Registers (2nd SFRs) (9/15)
Address Special Function Register (SFR) Name
Symbol
R/W
F02CCH Flash write buffer register L F02CEH Flash write buffer register H F02E0H DTC base address register F02E8H DTC activation enable register 0 F02E9H DTC activation enable register 1 F02EAH DTC activation enable register 2 F02EBH DTC activation enable register 3 F02ECH DTC activation enable register 4 F02F0H Flash memory CRC control register F02F2H Flash memory CRC operation result register F02FAH CRC data register F0300H Transmit buffer register 0 F0301H Receive buffer register 0 F0302H Operation mode setting register 00 F0303H Operation mode setting register 01 F0304H Baud rate generator control register 0 F0305H Status register 0 F0306H Status clear trigger register 0 F0308H Transmit buffer register 1 F0309H Receive buffer register 1 F030AH Operation mode setting register 10 F030BH Operation mode setting register 11 F030CH Baud rate generator control register 1 F030DH Status register 1 F030EH Status clear trigger register 1 F0310H UARTA clock select register 0 F0311H UARTA clock select register 1 F0330H D/A conversion value setting register 0 F0331H D/A conversion value setting register 1 F0332H D/A converter mode register F0340H Comparator mode setting register F0341H Comparator filter control register F0342H Comparator output control register F0360H Interval timer compare register 00 F0361H F0362H Interval timer compare register 01 F0363H F0364H Interval timer capture register 00 F0365H F0366H Interval timer control register F0367H Interval timer clock select register 0 F0368H Interval timer division register 0 F0369H Interval timer division register 1 F036AH Interval timer capture control register 0 F036BH Interval timer status register F036CH Interval timer match detection mask register F0380H Sequencer instruction register 0 F0381H
FLWL FLWH DTCBAR DTCEN0 DTCEN1 DTCEN2 DTCEN3 DTCEN4 CRC0CTL PGCRCL CRCD TXBA0 RXBA0 ASIMA00 ASIMA01 BRGCA0 ASISA0 ASCTA0 TXBA1 RXBA1 ASIMA10 ASIMA11 BRGCA1 ASISA1 ASCTA1 UTA0CK UTA1CK DACS0 DACS1 DAM COMPMDR COMPFIR COMPOCR ITLCMP000 ITLCMP001 ITLCMP012 ITLCMP013 ITLCAP00
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R R/W R/W R/W
R R/W R/W
R R/W R/W R/W
R R/W R/W R/W R/W R/W R/W R/W R/W R/W ITLCMP0 R/W 0
ITLCMP0 R/W 1
R
ITLCTL0
R/W
ITLCSEL0
R/W
ITLFDIV00
R/W
ITLFDIV01
R/W
ITLCC0
R/W
ITLS0
R/W
ITLMKF0
R/W
SMSI0
R/W
Manipulable Bit Range 1-bit 8-bit 16-bit
After Reset
0000H 0000H FDH 00H 00H 00H 00H 00H 00H 0000H 0000H FFH FFH 01H 1AH FFH 00H 00H FFH FFH 01H 1AH FFH 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H FFFFH
FFFFH
0000H
00H
00H
00H
00H
00H
00H
00H
0000H
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Page 146 of 1478
RL78/G23
CHAPTER 3 CPU ARCHITECTURE
Table 3 - 8 List of Extended Special Function Registers (2nd SFRs) (10/15)
Address Special Function Register (SFR) Name
Symbol
R/W
F0382H Sequencer instruction register 1
SMSI1
R/W
F0383H
F0384H Sequencer instruction register 2
SMSI2
R/W
F0385H
F0386H Sequencer instruction register 3
SMSI3
R/W
F0387H
F0388H Sequencer instruction register 4
SMSI4
R/W
F0389H
F038AH Sequencer instruction register 5
SMSI5
R/W
F038BH
F038CH Sequencer instruction register 6
SMSI6
R/W
F038DH
F038EH Sequencer instruction register 7
SMSI7
R/W
F038FH
F0390H Sequencer instruction register 8
SMSI8
R/W
F0391H
F0392H Sequencer instruction register 9
SMSI9
R/W
F0393H
F0394H Sequencer instruction register 10
SMSI10
R/W
F0395H
F0396H Sequencer instruction register 11
SMSI11
R/W
F0397H
F0398H Sequencer instruction register 12
SMSI12
R/W
F0399H
F039AH Sequencer instruction register 13
SMSI13
R/W
F039BH
F039CH Sequencer instruction register 14
SMSI14
R/W
F039DH
F039EH Sequencer instruction register 15
SMSI15
R/W
F039FH
F03A0H Sequencer instruction register 16
SMSI16
R/W
F03A1H
F03A2H Sequencer instruction register 17
SMSI17
R/W
F03A3H
F03A4H Sequencer instruction register 18
SMSI18
R/W
F03A5H
F03A6H Sequencer instruction register 19
SMSI19
R/W
F03A7H
F03A8H Sequencer instruction register 20
SMSI20
R/W
F03A9H
F03AAH Sequencer instruction register 21
SMSI21
R/W
F03ABH
F03ACH Sequencer instruction register 22
SMSI22
R/W
F03ADH
F03AEH Sequencer instruction register 23
SMSI23
R/W
F03AFH
F03B0H Sequencer instruction register 24
SMSI24
R/W
F03B1H
Manipulable Bit Range 1-bit 8-bit 16-bit
After Reset 0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
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Page 147 of 1478
RL78/G23
CHAPTER 3 CPU ARCHITECTURE
Table 3 - 8 List of Extended Special Function Registers (2nd SFRs) (11/15)
Address Special Function Register (SFR) Name
Symbol
R/W
F03B2H Sequencer instruction register 25
SMSI25
R/W
F03B3H
F03B4H Sequencer instruction register 26
SMSI26
R/W
F03B5H
F03B6H Sequencer instruction register 27
SMSI27
R/W
F03B7H
F03B8H Sequencer instruction register 28
SMSI28
R/W
F03B9H
F03BAH Sequencer instruction register 29
SMSI29
R/W
F03BBH
F03BCH Sequencer instruction register 30
SMSI30
R/W
F03BDH
F03BEH Sequencer instruction register 31
SMSI31
R/W
F03BFH
F03C0H Sequencer general-purpose register 0
SMSG0
R
F03C1H
F03C2H Sequencer general-purpose register 1
SMSG1
R/W
F03C3H
F03C4H Sequencer general-purpose register 2
SMSG2
R/W
F03C5H
F03C6H Sequencer general-purpose register 3
SMSG3
R/W
F03C7H
F03C8H Sequencer general-purpose register 4
SMSG4
R/W
F03C9H
F03CAH Sequencer general-purpose register 5
SMSG5
R/W
F03CBH
F03CCH Sequencer general-purpose register 6
SMSG6
R/W
F03CDH
F03CEH Sequencer general-purpose register 7
SMSG7
R/W
F03CFH
F03D0H Sequencer general-purpose register 8
SMSG8
R/W
F03D1H
F03D2H Sequencer general-purpose register 9
SMSG9
R/W
F03D3H
F03D4H Sequencer general-purpose register 10
SMSG10
R/W
F03D5H
F03D6H Sequencer general-purpose register 11
SMSG11
R/W
F03D7H
F03D8H Sequencer general-purpose register 12
SMSG12
R/W
F03D9H
F03DAH Sequencer general-purpose register 13
SMSG13
R/W
F03DBH
F03DCH Sequencer general-purpose register 14
SMSG14
R/W
F03DDH
F03DEH Sequencer general-purpose register 15
SMSG15
R
F03DFH
F03E0H Sequencer control register
SMSC
R/W
F03E1H Sequencer status register
SMSS
R
Manipulable Bit Range 1-bit 8-bit 16-bit
After Reset 0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
FFFFH
00H
00H
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 148 of 1478
RL78/G23
CHAPTER 3 CPU ARCHITECTURE
Table 3 - 8 List of Extended Special Function Registers (2nd SFRs) (12/15)
Address Special Function Register (SFR) Name
Symbol
R/W
F0480H Interrupt vector change register 0
FLSIVC0
R/W
F0481H
F0482H Interrupt vector change register 1
FLSIVC1
R/W
F0483H
F0488H Code flash memory guard register 0
GFLASH0
R/W
F0489H
F048AH Code flash memory guard register 1
GFLASH1
R/W
F048BH
F048CH Flash security area guard register
GFLASH2
R/W
F048DH
F048EH Guard register of IAWCTL register
GIAWCTL
R/W
F048FH
F0500H CTSU control register AL F0501H
CTSUCR0 CTSUCR1
CTSUCR R/W AL
F0502H CTSU control register AH F0503H
CTSUCR2 CTSUCR3
CTSUCR R/W AH
F0504H CTSU control register BL F0505H
CTSUSDPRS CTSUCR R/W CTSUSST BL
F0506H CTSU control register BH F0507H
CTSUCR R/W
CTSUDCLKC BH
F0508H CTSU measurement channel register L F0509H
CTSUMCH0 CTSUMC R/W CTSUMCH1 HL
F050AH CTSU measurement channel register H F050BH
CTSUMFAF CTSUMC R/W
HH
F050CH CTSU channel enable control register AL F050DH
CTSUCHAC0 CTSUCH R/W CTSUCHAC1 ACAL
F050EH CTSU channel enable control register AH F050FH
CTSUCHAC2 CTSUCH R/W CTSUCHAC3 ACAH
F0510H CTSU channel enable control register BL F0511H
CTSUCHAC4 CTSUCH R/W CTSUCHAC5 ACBL
F0512H CCTSU channel enable control register BH F0513H
CTSUCHAC6 CTSUCH R/W CTSUCHAC7 ACBH
F0514H CTSU channel transmit/receive control register CTSUCHTR CTSUCH R/W
AL
C0
TRCAL
F0515H
CTSUCHTR C1
F0516H CTSU channel transmit/receive control register CTSUCHTR CTSUCH R/W
AH
C2
TRCAH
F0517H
CTSUCHTR C3
F0518H CTSU channel transmit/receive control register CTSUCHTR CTSUCH R/W
BL
C4
TRCBL
F0519H
CTSUCHTR C5
F051AH CTSU channel transmit/receive control register CTSUCHTR CTSUCH R/W
BH
C6
TRCBH
F051BH
CTSUCHTR C7
F051CH CTSU status register L F051DH
CTSUST1 CTSUST
CTSUSR R/W L
Manipulable Bit Range 1-bit 8-bit 16-bit
After Reset 0000H
000FH
0000H
0000H
0000H
0000H
0000H 0000H 0000H 0000H 3F3FH 0000H 0000H 0000H 0000H 0000H 0000H
0000H
0000H
0000H
0000H
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Table 3 - 8 List of Extended Special Function Registers (2nd SFRs) (13/15)
Address Special Function Register (SFR) Name
Symbol
R/W
F0520H CTSU sensor offset register 0
CTSUSO0
R/W
F0521H
F0522H CTSU sensor offset register 1
CTSUSO1
R/W
F0523H
F0524H CTSU sensor counter register L
CTSUSC
R
F0525H
F0526H CTSU sensor counter register H
CTSUUC
R
F0527H
F0528H CTSU calibration register L
CTSUDBGR0
R/W
F0529H
F052AH CTSU calibration register H
CTSUDBGR1
R/W
F052BH
F052CH CTSU sensor unit clock control register AL CTSUSUCLK0
R/W
F052DH
F052EH CTSU sensor unit clock control register AH CTSUSUCLK1
R/W
F052FH
F0530H CTSU sensor unit clock control register BL CTSUSUCLK2
R/W
F0531H
F0532H CTSU sensor unit clock control register BH CTSUSUCLK3
R/W
F0533H
F0540H TRNG seed data register
TRNGSDR
R
F0542H TRNG command register 0
TRNGSCR0
R/W
F0600H CTSU trimming register AL F0601H
RTRIM DACTRIM
CTSUTRI R/W M0
F0602H CTSU trimming register AH F0603H
SUADJD
CTSUTRI R/W
TRESULT4 M1
F0604H CTSU trimming register BL F0605H
TRESULT0 CTSUTRI R/W TRESULT1 M2
F0606H CTSU trimming register BH F0607H
TRESULT2 CTSUTRI R/W TRESULT3 M3
F0640H Function select register 0
REMCON0
R/W
F0641H Function select register 1
REMCON1
R/W
F0642H Status register
REMSTS
R/W
F0643H Interrupt control register
REMINT
R/W
F0645H Compare control register
REMCPC
R/W
F0646H Compare value setting register
REMCPD
R/W
F0647H
F0648H Header pattern minimum width setting register HDPMIN
R/W
F0649H
F064AH Header pattern maximum width setting register HDPMAX
R/W
F064BH
F064CH Data '0' pattern minimum width setting register D0PMIN
R/W
F064DH Data '0' pattern maximum width setting register D0PMAX
R/W
F064EH Data '1' pattern minimum width setting register D1PMIN
R/W
F064FH Data '1' pattern maximum width setting register D1PMAX
R/W
F0650H Special data pattern minimum width setting SDPMIN
R/W
F0651H register
Manipulable Bit Range 1-bit 8-bit 16-bit
After Reset 0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
00H
00H
Undefined
Note 1
Undefined
Note 1
Undefined
Note 1
Undefined
Note 1
00H
00H
00H
00H
00H
0000H
0000H
0000H
00H
00H
00H
00H
0000H
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Table 3 - 8 List of Extended Special Function Registers (2nd SFRs) (14/15)
Address Special Function Register (SFR) Name
Symbol
R/W
F0652H Special data pattern maximum width setting SDPMAX
R/W
F0653H register
F0654H Pattern end setting register
REMPE
R/W
F0655H
F0656H Receiver standby control register
REMSTC
R/W
F0657H Receive bit count register
REMRBIT
R/W
F0658H Receive data 0 register
REMDAT0
R/W
F0659H Receive data 1 register
REMDAT1
R
F065AH Receive data 2 register
REMDAT2
R
F065BH Receive data 3 register
REMDAT3
R
F065CH Receive data 4 register
REMDAT4
R
F065DH Receive data 5 register
REMDAT5
R
F065EH Receive data 6 register
REMDAT6
R
F065FH Receive data 7 register
REMDAT7
R
F0660H Measurement result register
REMTIM
R
F0661H
F0680H Input signal select register 0
ELISEL0
R/W
F0681H Input signal select register 1
ELISEL1
R/W
F0682H Input signal select register 2
ELISEL2
R/W
F0683H Input signal select register 3
ELISEL3
R/W
F0684H Input signal select register 4
ELISEL4
R/W
F0685H Input signal select register 5
ELISEL5
R/W
F0686H Input signal select register 6
ELISEL6
R/W
F0687H Input signal select register 7
ELISEL7
R/W
F0688H Input signal select register 8
ELISEL8
R/W
F0689H Input signal select register 9
ELISEL9
R/W
F068AH Input signal select register 10
ELISEL10
R/W
F068BH Input signal select register 11
ELISEL11
R/W
F0690H Event link L1 signal select register 0
ELL1SEL0
R/W
F0691H Event link L1 signal select register 1
ELL1SEL1
R/W
F0692H Event link L1 signal select register 2
ELL1SEL2
R/W
F0693H Event link L1 signal select register 3
ELL1SEL3
R/W
F0694H Event link L1 signal select register 4
ELL1SEL4
R/W
F0695H Event link L1 signal select register 5
ELL1SEL5
R/W
F0696H Event link L1 signal select register 6
ELL1SEL6
R/W
F0697H Logic cell block L1 control register
ELL1CTL
R/W
F0698H Event link L1 output select register 0
ELL1LNK0
R/W
F0699H Event link L1 output select register 1
ELL1LNK1
R/W
F069AH Event link L1 output select register 2
ELL1LNK2
R/W
F069BH Event link L1 output select register 3
ELL1LNK3
R/W
F069CH Event link L1 output select register 4
ELL1LNK4
R/W
F069DH Event link L1 output select register 5
ELL1LNK5
R/W
F069EH Event link L1 output select register 6
ELL1LNK6
R/W
F06A0H Event link L2 signal select register 0
ELL2SEL0
R/W
F06A1H Event link L2 signal select register 1
ELL2SEL1
R/W
F06A2H Event link L2 signal select register 2
ELL2SEL2
R/W
F06A3H Event link L2 signal select register 3
ELL2SEL3
R/W
F06A4H Event link L2 signal select register 4
ELL2SEL4
R/W
Manipulable Bit Range 1-bit 8-bit 16-bit
After Reset 0000H
0000H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
0000H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
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Table 3 - 8 List of Extended Special Function Registers (2nd SFRs) (15/15)
Address Special Function Register (SFR) Name
Symbol
Manipulable Bit Range
R/W
After Reset
1-bit 8-bit 16-bit
F06A5H Event link L2 signal select register 5
ELL2SEL5
R/W
00H
F06A6H Event link L2 signal select register 6
ELL2SEL6
R/W
00H
F06A7H Logic cell block L2 control register
ELL2CTL
R/W
00H
F06A8H Event link L2 output select register 0
ELL2LNK0
R/W
00H
F06A9H Event link L2 output select register 1
ELL2LNK1
R/W
00H
F06AAH Event link L2 output select register 2
ELL2LNK2
R/W
00H
F06ABH Event link L2 output select register 3
ELL2LNK3
R/W
00H
F06ACH Event link L2 output select register 4
ELL2LNK4
R/W
00H
F06ADH Event link L2 output select register 5
ELL2LNK5
R/W
00H
F06AEH Event link L2 output select register 6
ELL2LNK6
R/W
00H
F06B0H Event link L3 signal select register 0
ELL3SEL0
R/W
00H
F06B1H Event link L3 signal select register 1
ELL3SEL1
R/W
00H
F06B2H Event link L3 signal select register 2
ELL3SEL2
R/W
00H
F06B3H Event link L3 signal select register 3
ELL3SEL3
R/W
00H
F06B4H Event link L3 signal select register 4
ELL3SEL4
R/W
00H
F06B5H Event link L3 signal select register 5
ELL3SEL5
R/W
00H
F06B6H Event link L3 signal select register 6
ELL3SEL6
R/W
00H
F06B7H Logic cell block L3 control register
ELL3CTL
R/W
00H
F06B8H Event link L3 output select register 0
ELL3LNK0
R/W
00H
F06B9H Event link L3 output select register 1
ELL3LNK1
R/W
00H
F06BAH Event link L3 output select register 2
ELL3LNK2
R/W
00H
F06BBH Event link L3 output select register 3
ELL3LNK3
R/W
00H
F06BCH Event link L3 output select register 4
ELL3LNK4
R/W
00H
F06BDH Event link L3 output select register 5
ELL3LNK5
R/W
00H
F06BEH Event link L3 output select register 6
ELL3LNK6
R/W
00H
F06C0H Output signal select register 0
ELOSEL0
R/W
00H
F06C1H Output signal select register 1
ELOSEL1
R/W
00H
F06C2H Output signal select register 2
ELOSEL2
R/W
00H
F06C3H Output signal select register 3
ELOSEL3
R/W
00H
F06C4H Output signal select register 4
ELOSEL4
R/W
00H
F06C5H Output signal select register 5
ELOSEL5
R/W
00H
F06C6H Output signal select register 6
ELOSEL6
R/W
00H
F06C7H Output signal select register 7
ELOSEL7
R/W
00H
F06C8H Output signal enable register
ELOENCTL
R/W
00H
F06C9H Output signal monitor register
ELOMONI
R
00H
Note 1. The value after a reset is adjusted at the time of shipment.
Note 2. The value after a reset is a value set in FRQSEL2 to FRQSEL0 of the option byte (000C2H).
Note 3. The initial value of the FLMODE register is set to the value of the MODE1 and MODE0 bits updated with the set value of
the CMODE1 and CMODE0 bits in the option byte at address 000C2H.
Remark For SFRs in the SFR area, see Table 3 - 7 List of Special Function Registers (SFRs).
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3.3
Instruction Address Addressing
3.3.1 Relative addressing
[Function] Relative addressing stores in the program counter (PC) the result of adding a displacement value included in the instruction word (signed complement data: .128 to +127 or .32768 to +32767) to the program counter (PC)'s value (the start address of the next instruction), and specifies the program address to be used as the branch destination. Relative addressing is applied only to branch instructions.
Figure 3 - 16 Outline of Relative Addressing
PC OP code
DISPLACE 8/16 bits
3.3.2 Immediate addressing
[Function] Immediate addressing stores immediate data of the instruction word in the program counter, and specifies the program address to be used as the branch destination. For immediate addressing, CALL !!addr20 or BR !!addr20 is used to specify 20-bit addresses and CALL !addr16 or BR !addr16 is used to specify 16-bit addresses. 0000 is set to the higher 4 bits when specifying 16-bit addresses.
Figure 3 - 17 Example of CALL !!addr20/BR !!addr20 PC
Figure 3 - 18 Example of CALL !addr16/BR !addr16
PC
PCS PCH PCL
0000
OP code Low Addr. High Addr. Seg Addr.
OP code Low Addr. High Addr.
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3.3.3 Table indirect addressing
[Function] Table indirect addressing specifies a table address in the CALLT table area (0080H to 00BFH) with the 5-bit immediate data in the instruction word, stores the contents at that table address and the next address in the program counter (PC) as 16-bit data, and specifies the program address. Table indirect addressing is applied only for CALLT instructions. In the RL78 microcontrollers, branching is enabled only to the 64-Kbyte space from 00000H to 0FFFFH.
Figure 3 - 19 Outline of Table Indirect Addressing
OP code
00000000 10
0
Table address
0000
High Addr. Low Addr.
Memory
PC
PCS PCH PCL
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3.3.4 Register indirect addressing
[Function] Register indirect addressing stores in the program counter (PC) the contents of a general-purpose register pair (AX/BC/DE/HL) and CS register of the current register bank specified with the instruction word as 20-bit data, and specifies the program address. Register indirect addressing can be applied only to the CALL AX, BC, DE, HL, and BR AX instructions.
Figure 3 - 20 Outline of Register Indirect Addressing CS
OP code rp
PC
PCS
PCH
PCL
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3.4
Addressing for Processing Data Addresses
3.4.1 Implied addressing
[Function] Instructions for accessing registers (such as accumulators) that have special functions are directly specified with the instruction word, without using any register specification field in the instruction word.
[Operand format] Implied addressing can be applied only to MULU X.
Figure 3 - 21 Outline of Implied Addressing
OP code
A register
Memory (register area)
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3.4.2 Register addressing
[Function] Register addressing accesses a general-purpose register as an operand. The instruction word of 3-bit long is used to select an 8-bit register and the instruction word of 2-bit long is used to select a 16-bit register.
[Operand format]
Identifier r rp
X, A, C, B, E, D, L, H AX, BC, DE, HL
Description
Figure 3 - 22 Outline of Register Addressing
OP code
A register
Memory (register area)
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3.4.3 Direct addressing
[Function] Direct addressing uses immediate data in the instruction word as an operand address to directly specify the target address.
[Operand format]
Identifier !addr16 ES:!addr16
Description Label or 16-bit immediate data (only the space from F0000H to FFFFFH is specifiable) Label or 16-bit immediate data (higher 4-bit addresses are specified by the ES register)
Figure 3 - 23 Example of !addr16
MOV !addr 16, A <1>
Instruction code OP -code Low Addr.
< 1> High Addr.
· A 16-bit address <1> in the 64-Kbyte area from F0000H to FFFFFH specifies the target location (for use in access to the 2nd SFRs etc.).
FFFFFH Target memory
F0000 H
Memory
Figure 3 - 24 Example of ES:!addr16
ES: !addr 16 <1 > <2 >
Instruction code
OP -code
Low Addr .
<2>
High Addr .
Specifies the address in memory
X0000 H Specifies a
ES
64-Kbyte area
· The ES register <1> specifies a 64-Kbyte area within the overall 1-Mbyte space as the four higher-order bits, X, of the address range.
· A 16-bit address <2> in the area from X0000 H to XFFFFH and the ES register <1> specify the target location; this is used for access to fixed data other than that in mirrored areas.
FFFFFH
Target memory
Area from X0000 H to XFFFFH
Memory
00000 H
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3.4.4 Short direct addressing
[Function] Short direct addressing directly specifies the target addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFE20H to FFF1FH.
[Operand format]
Identifier SADDR
SADDRP
Description
Label, FFE20H to FFF1FH immediate data, or 0FE20H to 0FF1FH immediate data (only the space from FFE20H to FFF1FH is specifiable)
Label, FFE20H to FFF1FH immediate data, or 0FE20H to 0FF1FH immediate data (even address only) (only the space from FFE20H to FFF1FH is specifiable)
Figure 3 - 25 Outline of Short Direct Addressing
OP code saddr
saddr
FFF1FH FFE20H
Memory
Remark
SADDR and SADDRP are used to describe the values of addresses FE20H to FF1FH with 16-bit immediate data (higher 4 bits of actual address are omitted), and the values of addresses FFE20H to FFF1FH with 20-bit immediate data. Regardless of whether SADDR or SADDRP is used, addresses within the space from FFE20H to FFF1FH are specified for the memory.
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3.4.5 SFR addressing
[Function] SFR addressing directly specifies the target SFR addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFF00H to FFFFFH.
[Operand format]
Identifier SFR SFRP
Description SFR name 16-bit-manipulatable SFR name (even address)
Figure 3 - 26 Outline of SFR Addressing
OP code SFR
SFR
FFFFFH FFF00H
Memory
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3.4.6 Register indirect addressing
[Function] Register indirect addressing directly specifies the target addresses using the contents of the register pair specified with the instruction word as an operand address.
[Operand format]
Identifier -- --
Description [DE], [HL] (only the space from F0000H to FFFFFH is specifiable) ES:[DE], ES:[HL] (higher 4-bit addresses are specified by the ES register)
Figure 3 - 27 Example of [DE], [HL]
[DE], [HL] <1> <1>
Instruction code <1 >
OP-code
rp (HL/DE)
<1> Specifies the address in memory
FFFFFH Target memory
F0000H
· Either pair of registers <1 > specifies the target location as an address in the 64-Kbyte area from F0000 H to FFFFFH.
Memory
Figure 3 - 28 Example of ES:[DE], ES:[HL]
ES: [DE], ES: [HL] <1 > <2> <1 > <2>
FFFFFH
Instruction code <2>
OP-code
rp (HL/DE)
<1> ES
<2> Specifies the address in memory
X 0000H <1> Specifies a 64-Kbyte area
· The ES register <1> specifies a 64-Kbyte area within the overall 1-Mbyte space as the four higher-order bits, X, of the address range .
· Either pair of registers <2 > and the ES register <1> specify the target location in the area from X0000 H to XFFFFH.
Target memory
Area from X0000 H to XFFFFH
Memory
00000 H
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3.4.7 Based addressing
[Function] Based addressing uses the contents of a register pair specified with the instruction word or 16-bit immediate data as a base address, and 8-bit immediate data or 16-bit immediate data as offset data. The sum of these values is used to specify the target address.
[Operand format]
Identifier -- -- -- -- -- --
Description [HL + byte], [DE + byte], [SP + byte] (only the space from F0000H to FFFFFH is specifiable) word[B], word[C] (only the space from F0000H to FFFFFH is specifiable) word[BC] (only the space from F0000H to FFFFFH is specifiable) ES:[HL + byte], ES:[DE + byte] (higher 4-bit addresses are specified by the ES register) ES:word[B], ES:word[C] (higher 4-bit addresses are specified by the ES register) ES:word[BC] (higher 4-bit addresses are specified by the ES register)
Figure 3 - 29 Example of [SP+byte]
Instruction code <1>
<2> byte
SP
<2> Offset
<1>
Specifies a stack area
FFFFFH
Target memory
Stack area
F0000H
· SP (stack pointer) <1> indicates the stack as the target. · By indicating an offset from the address (top of the stack)
currently pointed to by the stack pointer, "byte" <2> indicates the target memory (SP + byte).
Memory
Figure 3 - 30 Example of [HL + byte], [DE + byte]
[HL + byte], [DE + byte] <1> <2> <1> <2>
Instruction code
OP-code <2> byte
<2> Offset
rp (HL/DE)
<1> Address of an array
FFFFFH
Target memory
Target array of data
Other data in the array F0000H
· Either pair of registers <1> specifies the address where the target array of data starts in the 64-Kbyte area from F0000H to FFFFFH.
· "byte" <2> specifies an offset within the array to the target location in memory.
Memory
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Figure 3 - 31 Example of word [B], word [C]
word [B], word [C] <1> <2> <1> <2>
Instruction code OP-code Low Addr. High Addr.
<2>
<2> r (B/C)
Offset
<1> Address of a word within an array
· "word" <1> specifies the address where the target array of wordsized data starts in the 64-Kbyte area from F0000H to FFFFFH.
· Either register <2> specifies an offset within the array to the target location in memory.
FFFFFH
Target memory
Array of word-sized data
F0000H
Memory
Figure 3 - 32 Example of word [BC]
word [BC] <1> <2>
Instruction code
OP-code
Low Addr. <1>
High Addr.
<2>
<2>
Offset
rp (BC)
<1> Address of a word within an array
FFFFFH
Target memory
Array of word-sized data
F0000H
· "word" <1> specifies the address where the target array of word-sized data starts in the 64-Kbyte area from F0000H to FFFFFH.
· A pair of registers <2> specifies an offset within the array to the target location in memory.
Memory
Figure 3 - 33 Example of ES:[HL + byte], ES:[DE + byte]
ES: [HL + byte], ES: [DE + byte] <1> <2> <3> <1> <2> <3>
Instruction code OP-code <3> byte
<2>
<3> Offset
<2> Address of
rp (HL/DE)
an array
X0000H
<1> ES
<1> Specifies a 64-Kbyte area
XFFFFH
Target memory
Target array of data
Other data in the array X0000H
· The ES register <1> specifies a 64-Kbyte area within the overall 1-Mbyte space as the four higher-order bits, X, of the address range.
· Either pair of registers <2> specifies the address where the target array of data starts in the 64-Kbyte area specified in the ES register <1>.
· "byte" <3> specifies an offset within the array to the target location in memory.
Memory
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Figure 3 - 34 Example of ES:word [B], ES:word [C]
ES: word [B], ES: word [C] <1> <2> <3><1> <2> <3>
Instruction code
OP-code
Low Addr. <2>
High Addr.
<3>
<3>
Offset <2> r (B/C)
Address of a word within an array
<1> ES
X0000H <1> Specifies a 64-Kbyte area
Target memory
XFFFFH
Array of word-sized data
X0000H
· The ES register <1> specifies a 64-Kbyte area within the overall 1-Mbyte space as the four higher-order bits, X, of the address range.
· "word" <2> specifies the address where the target array of word-sized data starts in the 64-Kbyte area specified in the ES register <1>.
· Either register <3> specifies an offset within the array to the target location in memory.
Memory
Figure 3 - 35 Example of ES:word [BC]
ES: word [BC] <1> <2> <3>
Instruction code OP-code
Low Addr. <2>
High Addr.
<3>
<3>
Offset rp (BC)
<2>
Address of a word within an array
<1> ES
X0000H <1> Specifies a 64-Kbyte area
· The ES register <1> specifies a 64-Kbyte area within the overall 1-Mbyte space as the four higher-order bits, X, of the address range.
· "word" <2> specifies the address where the target array of word-sized data starts in the 64-Kbyte area specified in the ES register <1>.
· A pair of registers <3> specifies an offset within the array to the target location in memory.
Target memory
XFFFFH
Array of word-sized data
X0000H
Memory
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3.4.8 Based indexed addressing
[Function] Based indexed addressing uses the contents of a register pair specified with the instruction word as the base address, and the content of the B register or C register similarly specified with the instruction word as offset address. The sum of these values is used to specify the target address.
[Operand format]
Identifier -- --
Description [HL+B], [HL+C] (only the space from F0000H to FFFFFH is specifiable) ES:[HL+B], ES:[HL+C] (higher 4-bit addresses are specified by the ES register)
Figure 3 - 36 Example of [HL + B], [HL + C]
[HL + B], [HL + C] <1> <2> <1> <2>
FFFFFH
Instruction code OP-code
r (B/C)
<2> Offset
rp (HL)
<1> Address of an array
Target memory
Target array of data
Other data in the array F0000H
· A pair of registers <1> specifies the address where the target array of data starts in the 64-Kbyte area from F0000H to FFFFFH.
· Either register <2> specifies an offset within the array to the target location in memory.
Memory
Figure 3 - 37 Example of ES:[HL + B], ES:[HL + C]
ES: [HL + B], ES: [HL + C] <1><2> <3> <1> <2> <3>
Instruction code OP-code <3> byte
<3> <2> <1>
r (B/C) rp (HL)
<3> Offset
<2> Address of an array
X0000H
<1> Specifies a
ES
64-Kbyte area
XFFFFH
Target memory
Target array of data
Other data in the array X0000H
· The ES register <1> specifies a 64-Kbyte area within the overall 1-Mbyte space as the four higher-order bits, X, of the address range.
· A pair of registers <2> specifies the address where the target array of data starts in the 64-Kbyte area specified in the ES register <1>.
· Either register <3> specifies an offset within the array to the target location in memory.
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CHAPTER 3 CPU ARCHITECTURE
3.4.9 Stack addressing
[Function] The stack area is indirectly addressed with the stack pointer (SP) values. This addressing is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon generation of an interrupt request. Only the internal RAM area can be set as the stack area.
[Operand format]
Identifier --
PUSH PSW AX/BC/DE/HL POP PSW AX/BC/DE/HL CALL/CALLT RET BRK RETB (Interrupt request generated) RETI
Description
The data to be saved/restored by each stack operation is shown in Figure 3 - 38 to Figure 3 - 43.
Figure 3 - 38 Example of PUSH rp
PUSH rp <1> <2>
Instruction code OP-code
<1> <2>
SP
SP-1 Higher-order byte of rp
<3> SP-2 Lower-order byte of rp Stack area SP
rp
· Stack addressing is specified <1>. · The higher-order and lower-order bytes of the pair of registers
indicated by rp <2> are stored in addresses SP-1 and SP- 2, respectively. · The value of SP <3> is decreased by two (if rp is the program status word (PSW), the value of the PSW is stored in SP-1 and 0 is stored in SP- 2).
F0000H Memory
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RL78/G23 Figure 3 - 39 Example of POP
POP rp <1> <2>
<1> Instruction code
SP
OP-code
<2>
SP
SP + 2 SP + 1 SP
rp
· Stack addressing is specified <1>. · The contents of addresses SP and SP + 1 are stored in the
lower-order and higher-order bytes of the pair of registers indicated by rp <2>, respectively. · The value of SP <3> is increased by two (if rp is the program status word (PSW), the content of address SP + 1 is stored in the PSW).
CHAPTER 3 CPU ARCHITECTURE
(SP + 1) (SP)
Stack area
F0000H
Memory
Figure 3 - 40 Example of CALL, CALLT
CALL <1>
Instruction code
<1>
OP-code
SP SP-1
SP-2
SP-3
SP
<3> SP-4
<2> PC
· Stack addressing is specified <1>. The value of the program counter (PC) changes to indicate the address of the instruction following the CALL instruction.
· 00H, the values of PC bits 19 to 16, 15 to 8, and 7 to 0 are stored in addresses SP-1, SP-2, SP-3, and SP-4, respectively <2>.
· The value of the SP <3> is decreased by 4.
00H PC19 to PC16 PC15 to PC8
PC7 to PC0
Stack area
F0000H
Memory
Figure 3 - 41 Example of RET
RET <1>
Instruction code
OP-code
<1>
SP
SP + 4 SP + 3
SP + 2
SP + 1
SP
<3> SP
<2> PC
· Stack addressing is specified <1>. · The contents of addresses SP, SP + 1, and SP + 2 are
stored in PC bits 7 to 0, 15 to 8, and 19 to 16, respectively <2>. · The value of SP <3> is increased by four.
(SP + 3) (SP + 2) (SP + 1)
(SP)
Stack area
F0000H
Memory
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Figure 3 - 42 Example of Interrupt, BRK
Instruction code <1> OP-code or Interrupt
PSW SP
SP
<2>
SP-1 SP-2 SP-3 <3> SP-4
<2> PC
· Stack addressing is specified <1>. In response to a BRK instruction or acceptance of an interrupt, the value of the program counter (PC) changes to indicate the address of the next instruction.
· The values of the PSW, PC bits 19 to 16, 15 to 8, and 7 to 0 are stored in addresses SP-1, SP-2, SP-3, and SP-4, respectively <2>.
· The value of the SP <3> is decreased by 4.
CHAPTER 3 CPU ARCHITECTURE
PSW PC19 to PC16 PC15 to PC8
PC7 to PC0
Stack area
F0000H
Memory
Figure 3 - 43 Example of RETI, RETB
RETI, RETB <1>
Instruction code
OP-code
PSW
<1>
SP
SP + 4 SP + 3
SP + 2
SP + 1
SP
<3> SP
<2>
PC
· Stack addressing is specified <1>. · The contents of addresses SP, SP + 1, SP + 2, and SP + 3
are stored in PC bits 7 to 0, 15 to 8, 19 to 16, and the PSW, respectively <2>. · The value of SP <3> is increased by four.
(SP + 3) (SP + 2) (SP + 1)
(SP)
Memory
Stack area F0000H
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CHAPTER 4 PORT FUNCTIONS
4.1
Port Functions
The RL78/G23 microcontrollers are provided with digital I/O ports, which enable variety of control operations. In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate functions, see CHAPTER 2 PIN FUNCTIONS.
4.2
Port Configuration
Ports include the following hardware.
Table 4 - 1 Port Configuration (1/2)
Item
Configuration
Control registers
Port mode registers (PM0 to PM12, PM14, PM15) Port registers (P0 to P15) Pull-up resistor option registers (PU0, PU1, PU3 to PU12, PU14) Port input mode registers (PIM0, PIM1, PIM3, PIM4, PIM5, PIM7, PIM8, PIM14) Port output mode registers (POM0, POM1, POM3 to POM5, POM7 to POM9, POM12, POM14) Port digital input disable registers (PDIDIS0, PDIDIS1, PDIDIS3 to PDIDIS5, PDIDIS7 to PDIDIS9, PDIDIS12, PDIDIS13, PDIDIS14) Port mode control A registers (PMCA0 to PMCA3, PMCA10 to PMCA12, PMCA14, PMCA15) Port mode control T registers (PMCT0, PMCT2, PMCT3, PMCT5 to PMCT7, PMCT15) Port mode control E registers (PMCE0, PMCE1, PMCE5, PMCE6) Peripheral I/O redirection register (PIOR) Global digital input disable register (GDIDIS) Output current control enable register (CCDE) Output current select registers (CCS0, CCS4 to CCS7) 40-mA port output control register (PTDC) Port function output enable registers (PFOE0, PFOE1) Port mode select register (PMS)
Port
· 30-pin products
Total: 26 (CMOS I/O: 23 (N-ch open drain I/O [VDD tolerance]: 10, output current control port: 6), CMOS
input: 1, N-ch open drain I/O [6-V tolerance]: 2)
· 32-pin products
Total: 28 (CMOS I/O: 24 (N-ch open drain I/O [VDD tolerance]: 10, output current control port: 7), CMOS
input: 1, N-ch open drain I/O [6-V tolerance]: 3)
· 36-pin products
Total: 32 (CMOS I/O: 28 (N-ch open drain I/O [VDD tolerance]: 12, output current control port: 7), CMOS
input: 1, N-ch open drain I/O [6-V tolerance]: 3)
· 40-pin products
Total: 36 (CMOS I/O: 30 (N-ch open drain I/O [VDD tolerance]: 12, output current control port: 7), CMOS
input: 3, N-ch open drain I/O [6-V tolerance]: 3)
· 44-pin products
Total: 40 (CMOS I/O: 33 (N-ch open drain I/O [VDD tolerance]: 12, output current control port: 8), CMOS
input: 3, N-ch open drain I/O [6-V tolerance]: 4)
· 48-pin products
Total: 44 (CMOS I/O: 36 (N-ch open drain I/O [VDD tolerance]: 13, output current control port: 8), CMOS
input: 3, CMOS output: 1, N-ch open drain I/O [6-V tolerance]: 4)
· 52-pin products
Total: 48 (CMOS I/O: 40 (N-ch open drain I/O [VDD tolerance]: 15, output current control port: 8), CMOS
input: 3, CMOS output: 1, N-ch open drain I/O [6-V tolerance]: 4)
· 64-pin products
Total: 58 (CMOS I/O: 50 (N-ch open drain I/O [EVDD tolerance]: 22Note 1/18Note 2, output current control
port: 8), CMOS input: 3, CMOS output: 1, N-ch open drain I/O [6-V tolerance]: 4)
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Table 4 - 1 Port Configuration (2/2)
Item
Configuration
Port
· 80-pin products
Total: 74 (CMOS I/O: 66 (N-ch open drain I/O [EVDD tolerance]: 27, output current control port: 8), CMOS
input: 3, CMOS output: 1, N-ch open drain I/O [6-V tolerance]: 4)
· 100-pin products
Total: 92 (CMOS I/O: 84 (N-ch open drain I/O [EVDD tolerance]: 31, output current control port: 8), CMOS
input: 3, CMOS output: 1, N-ch open drain I/O [6-V tolerance]: 4)
· 128-pin products
Total: 120 (CMOS I/O: 112 (N-ch open drain I/O [EVDD tolerance]: 33, output current control port: 8), CMOS
input: 3, CMOS output: 1, N-ch open drain I/O [6-V tolerance]: 4)
Pull-up resistor
· 30-pin products · 32-pin products · 36-pin products · 40-pin products · 44-pin products · 48-pin products · 52-pin products · 64-pin products · 80-pin products · 100-pin products · 128-pin products
Total: 19 Total: 20 Total: 22 Total: 23 Total: 25 Total: 28 Total: 32 Total: 42 Total: 54 Total: 69 Total: 97
Note 1. Note 2.
For products with 96-Kbyte or 128-Kbyte flash memory For products with 192-Kbyte to 768-Kbyte flash memory
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4.2.1 Port 0
Port 0 is an I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units by port mode register 0 (PM0). When the P00 to P07 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0). Input to the P01, P03 and P04 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units by port input mode register 0 (PIM0). Output from the P00 and P02 to P04 pins can be specified as N-ch open-drain output (VDD tolerance Note 1/EVDD tolerance Note 2) in 1-bit units by port output mode register 0 (POM0). This port can also be used for timer I/O, A/D converter analog input, serial interface data I/O and clock I/O, capacitance measurement, and logic and event link controller I/O. Use the registers shown in 4.3 Registers to Control the Port Function to specify the states of each of the pins. For the correspondence between register settings and pin state, see Table 4 - 6. The settings of the port pins following a reset are as follows. · P00 and P01 pins of the 30- and 32-pin products ... Analog input · P00, P01 and P04 to P07 pins of the 36- to 128-pin products ... Input mode · P02 and P03 pins of the 36- to 128-pin products ... Analog input
Note 1. Note 2.
For 30- to 52-pin products For 64- to 128-pin products
4.2.2 Port 1
Port 1 is an I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units by port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1). Input to the P10, P11, and P13 to P17 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units by port input mode register 1 (PIM1). Output from the P10 to P15 and P17 pins can be specified as N-ch open-drain output (VDD tolerance Note 1/EVDD tolerance Note 2) in 1-bit units by port output mode register 1 (POM1). Output from the P16 and P17 pins can be specified as output current control ports in 1-bit units by the output current control enable register (CCDE). This port can also be used for serial interface data I/O and clock I/O, UART data transmission and reception for external device connection when programming flash memory, clock/buzzer output, timer I/O, external interrupt request input, comparator reference voltage input, comparator output, and logic and event link controller I/O. Use the registers shown in 4.3 Registers to Control the Port Function to specify the states of each of the pins. For the correspondence between register settings and pin state, see Table 4 - 6. P10 to P12 and P14 to P17 are set to input mode and P13 is set to analog input following a reset.
Note 1. Note 2.
For 30- to 52-pin products For 64- to 128-pin products
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4.2.3 Port 2
Port 2 is an I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units by port mode register 2 (PM2). This port can also be used for A/D converter analog input, A/D converter reference voltage input (+ side and - side), D/A converter output, comparator reference voltage input, capacitance measurement, and logic and event link controller input. Use the registers shown in 4.3 Registers to Control the Port Function to specify the states of each of the pins. For the correspondence between register settings and pin state, see Table 4 - 6. Port 2 is set to analog input following a reset.
4.2.4 Port 3
Port 3 is an I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units by port mode register 3 (PM3). When the P30 to P37 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 3 (PU3). Input to the P33 pin can be specified through a normal input buffer or a TTL input buffer in 1-bit units by port input mode register 3 (PIM3). Output from the P34 pin can be specified as N-ch open-drain output (VDD tolerance Note 1/EVDD tolerance Note 2) in 1-bit units by port output mode register 3 (POM3). This port can also be used for external interrupt request input, realtime clock correction clock output, clock/buzzer output, timer I/O, serial interface data I/O and clock I/O, A/D converter analog input, comparator output, capacitance measurement, and logic and event link controller input. Use the registers shown in 4.3 Registers to Control the Port Function to specify the states of each of the pins. For the correspondence between register settings and pin state, see Table 4 - 6. P30 to P34 are set to input mode and P35 to P37 are set to analog input following a reset.
Note 1. Note 2.
For 30- to 52-pin products For 64- to 128-pin products
4.2.5 Port 4
Port 4 is an I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units by port mode register 4 (PM4). When the P40 to P47 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 4 (PU4). Input to the P41, P43, and P44 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units by port input mode register 4 (PIM4). Output from the P42 to P45 pins can be specified as N-ch open-drain output (VDD tolerance Note 1/EVDD tolerance Note 2) in 1-bit units by port output mode register 4 (POM4). This port can also be used for data I/O for a flash memory programmer/debugger, timer I/O, serial interface data I/O and clock I/O, and external interrupt request input. Use the registers shown in 4.3 Registers to Control the Port Function to specify the states of each of the pins. For the correspondence between register settings and pin state, see Table 4 6. Port 4 is set to input mode following a reset.
Note 1. Note 2.
For 30- to 52-pin products For 64- to 128-pin products
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4.2.6 Port 5
Port 5 is an I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units by port mode register 5 (PM5). When the P50 to P57 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 5 (PU5). Input to the P53 to P55 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units by port input mode register 5 (PIM5). Output from the P50 and P52 to P55 pins can be specified as N-ch open-drain output (VDD tolerance Note 1/EVDD tolerance Note 2) in 1-bit units by port output mode register 5 (POM5). Output from the P50 and P51 pins can be specified as output current control port pins in 1-bit units by the output current control enable register (CCDE). This port can also be used for external interrupt request input, serial interface data I/O and clock I/O, capacitance measurement, and logic and event link controller I/O. Use the registers shown in 4.3 Registers to Control the Port Function to specify the states of each of the pins. For the correspondence between register settings and pin state, see Table 4 - 6. Port 5 is set to input mode following a reset.
Note 1. Note 2.
For 30- to 52-pin products For 64- to 128-pin products
4.2.7 Port 6
Port 6 is an I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units by port mode register 6 (PM6). When the P64 to P67 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 6 (PU6). Output from the P60 to P63 pins is N-ch open-drain output (6-V tolerance). Output from the P60 to P63 pins can be specified as output current control port pins in 1-bit units by the output current control enable register (CCDE). This port can also be used for serial interface data I/O and clock I/O, timer I/O, capacitance measurement, and logic and event link controller I/O. Use the registers shown in 4.3 Registers to Control the Port Function to specify the states of each of the pins. For the correspondence between register settings and pin state, see Table 4 - 6. Port 6 is set to input mode following a reset.
4.2.8 Port 7
Port 7 is an I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units by port mode register 7 (PM7). When this port is used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 7 (PU7). Input to the P71 pin can be specified through a normal input buffer or a TTL input buffer in 1-bit units by port input mode register 7 (PIM7). Output from the P71, P72, and P74 pins can be specified as N-ch open-drain output (VDD tolerance Note 1/EVDD tolerance Note 2) in 1-bit units by port output mode register 7 (POM7). This port can also be used for key interrupt input, serial interface data I/O and clock I/O, external interrupt request input, capacitance measurement, and external pulse signal input for the remote controller signal reception function. Use the registers shown in 4.3 Registers to Control the Port Function to specify the states of each of the pins. For the correspondence between register settings and pin state, see Table 4 - 6. Port 7 is set to input mode following a reset.
Note 1. Note 2.
For 32- to 52-pin products For 64- to 128-pin products
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4.2.9 Port 8
Port 8 is an I/O port with an output latch. Port 8 can be set to the input mode or output mode in 1-bit units by port mode register 8 (PM8). When this port is used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 8 (PU8). Input to the P80, P81, and P84 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units by port input mode register 8 (PIM8). Output from the P80 to P83 pins can be specified as N-ch open-drain output (EVDD tolerance) in 1-bit units by port output mode register 8 (POM8). This port can also be used for serial interface data I/O. Use the registers shown in 4.3 Registers to Control the Port Function to specify the states of each of the pins. For the correspondence between register settings and pin state, see Table 4 - 6. Port 8 is set to input mode following a reset.
4.2.10 Port 9
Port 9 is an I/O port with an output latch. Port 9 can be set to the input mode or output mode in 1-bit units by port mode register 9 (PM9). When this port is used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 9 (PU9). Output from the P96 pin can be specified as N-ch open-drain output (EVDD tolerance) in 1-bit units by port output mode register 9 (POM9). This port can also be used for serial interface data I/O and clock I/O. Use the registers shown in 4.3 Registers to Control the Port Function to specify the states of each of the pins. For the correspondence between register settings and pin state, see Table 4 - 6. Port 9 is set to input mode following a reset.
4.2.11 Port 10
Port 10 is an I/O port with an output latch. Port 10 can be set to the input mode or output mode in 1-bit units by port mode register 10 (PM10). When this port is used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 10 (PU10). This port can also be used for timer I/O and A/D converter analog input. Use the registers shown in 4.3 Registers to Control the Port Function to specify the states of each of the pins. For the correspondence between register settings and pin state, see Table 4 - 6. P100 is set to analog input and P101 to P106 are set to input mode following a reset.
4.2.12 Port 11
Port 11 is an I/O port with an output latch. Port 11 can be set to the input mode or output mode in 1-bit units by port mode register 11 (PM11). When this port is used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 11 (PU11). This port can also be used for A/D converter analog input. Use the registers shown in 4.3 Registers to Control the Port Function to specify the states of each of the pins. For the correspondence between register settings and pin state, see Table 4 - 6. P110 to P114 are set to input mode and P115 to P117 are set to analog input following a reset.
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CHAPTER 4 PORT FUNCTIONS
4.2.13 Port 12
P120 to P122 and P125 to 127 are a 6-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units by port mode register 12 (PM12). When this port is used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12). Output from the P120 pin can be specified as N-ch open-drain output (VDD tolerance Note 1/EVDD tolerance Note 2) by port output mode register 12 (POM12). P123 and P124 are 2-bit input-only ports. This port can also be used for A/D converter analog input, comparator analog input, connection of a resonator for the main system clock, connection of a resonator for the subsystem clock, external clock input for the main system clock, external clock input for the subsystem clock, logic and event link controller input, and power supply for battery backup. Use the registers shown in 4.3 Registers to Control the Port Function to specify the states of each of the pins. For the correspondence between register settings and pin state, see Table 4 - 6. P120 is set to analog input and P121 to P127 are set to input mode following a reset.
Note 1. Note 2.
For 30- to 52-pin products For 64- to 128-pin products
4.2.14 Port 13
P130 is a 1-bit output-only port with an output latch. P137 is a 1-bit input-only port. P130 is fixed to output mode, and P137 is fixed to input mode. This port can also be used for external interrupt request input and logic and event link controller input. Use the registers shown in 4.3 Registers to Control the Port Function to specify the states of each of the pins. For the correspondence between register settings and pin state, see Table 4 - 6.
Remark
When a reset signal is applied, P130 outputs a low-level signal. If P130 is set to a mode for outputting a highlevel signal before a reset signal is applied, the P130 signal can be used to indicate a CPU reset.
Reset signal
P130
Set by software
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4.2.15 Port 14
Port 14 is an I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units by port mode register 14 (PM14). When the P140 to P147 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 14 (PU14). Input to the P142 and P143 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units by port input mode register 14 (PIM14). Output from the P142 to P144 pins can be specified as N-ch open-drain output (EVDD tolerance) in 1-bit units by port output mode register 14 (POM14). This port can also be used for clock/buzzer output, external interrupt request input, A/D converter analog input, serial interface data I/O and clock I/O, timer I/O, comparator analog input, and logic and event link controller input. Use the registers shown in 4.3 Registers to Control the Port Function to specify the states of each of the pins. For the correspondence between register settings and pin state, see Table 4 - 6. P140 to P146 are set to input mode and P147 is set to analog input following a reset.
4.2.16 Port 15
Port 15 is an I/O port with an output latch. Port 15 can be set to the input mode or output mode in 1-bit units by port mode register 15 (PM15). This port can also be used for A/D converter analog input and capacitance measurement. Use the registers shown in 4.3 Registers to Control the Port Function to specify the states of each of the pins. For the correspondence between register settings and pin state, see Table 4 - 6. Port 15 is set to analog input following a reset.
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4.3
Registers to Control the Port Function
The following registers are used to control the port functions.
· Port mode registers (PMxx) · Port registers (Pxx) · Pull-up resistor option registers (PUxx) · Port input mode registers (PIMxx) · Port output mode registers (POMxx) · Port digital input disable registers (PDIDISxx) · Port mode control A registers (PMCAxx) · Port mode control T registers (PMCTxx) · Port mode control E registers (PMCEx) · Peripheral I/O redirection register (PIOR) · Global digital input disable register (GDIDIS) · Output current control enable register (CCDE) · Output current select registers (CCSx) · 40-mA port output control register (PTDC) · Port function output enable registers (PFOEx) · Port mode select register (PMS)
Caution
Which registers and bits are included depends on the product. For registers and bits implemented in each product, see Tables 4 - 2 and 4 - 3. Be sure to set the bits that are not implemented to their initial values.
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Table 4 - 2
PMxx, Pxx, PUxx, PIMxx, POMxx, PDIDISxx, PMCAxx, PMCTxx, and PMCEx Registers and the Bits Implemented in Each Product (30-Pin to 64-Pin Products with 96-Kbyte or 128-Kbyte Flash Memory) (1/3)
Port
PMxx register
Pxx register
PUxx register
Bit name
PIMxx POMxx PDIDISxx PMCAxx PMCTxx register register register register register
64 52 48 44 40 36 32 30 PMCEx pins pins pins pins pins pins pins pins register
Port 0 0 PM00 P00 PU00
-- POM00 PDIDIS00 PMCA00 --
Note
--
1 PM01 P01 PU01 PIM01 --
-- PMCA01 -- PMCE01
Note
2 PM02 P02 PU02
-- POM02 PDIDIS02 PMCA02 --
--
------------
3 PM03 P03 PU03 PIM03 POM03 PDIDIS03 PMCA03 --
--
------------
4 PM04 P04 PU04 PIM04 POM04 PDIDIS04 --
--
--
--------------
5 PM05 P05 PU05
--
--
--
-- PMCT05 --
--------------
6 PM06 P06 PU06
--
--
--
-- PMCT06 --
--------------
7--
--
--
--
--
--
--
--
-- ----------------
Port 1 0 PM10 P10 PU10 PIM10 POM10 PDIDIS10 --
-- PMCE10
1 PM11 P11 PU11 PIM11 POM11 PDIDIS11 --
-- PMCE11
2 PM12 P12 PU12
-- POM12 PDIDIS12 --
-- PMCE12
3 PM13 P13 PU13 PIM13 POM13 PDIDIS13 PMCA13 -- PMCE13
4 PM14 P14 PU14 PIM14 POM14 PDIDIS14 --
-- PMCE14
5 PM15 P15 PU15 PIM15 POM15 PDIDIS15 --
-- PMCE15
6 PM16 P16 PU16 PIM16 --
--
--
-- PMCE16
7 PM17 P17 PU17 PIM17 POM17 PDIDIS17 --
-- PMCE17
Port 2 0 PM20 P20
--
--
--
-- PMCA20 --
--
1 PM21 P21
--
--
--
-- PMCA21 --
--
2 PM22 P22
--
--
--
-- PMCA22 --
--
3 PM23 P23
--
--
--
-- PMCA23 --
--
4 PM24 P24
--
--
--
-- PMCA24 --
--
----
5 PM25 P25
--
--
--
-- PMCA25 --
--
----
6 PM26 P26
--
--
--
-- PMCA26 --
--
------
7 PM27 P27
--
--
--
-- PMCA27 --
--
--------
Port 3 0 PM30 P30 PU30 --
--
--
-- PMCT30 --
1 PM31 P31 PU31
--
--
--
-- PMCT31 --
2--
--
--
--
--
--
--
--
-- ----------------
3--
--
--
--
--
--
--
--
-- ----------------
4--
--
--
--
--
--
--
--
-- ----------------
5--
--
--
--
--
--
--
--
-- ----------------
6--
--
--
--
--
--
--
--
-- ----------------
7--
--
--
--
--
--
--
--
-- ----------------
Port 4 0 PM40 P40 PU40 --
--
--
--
--
--
1 PM41 P41 PU41 PIM41 --
--
--
--
--
--------
2 PM42 P42 PU42
-- POM42 PDIDIS42 --
--
--
--------------
3 PM43 P43 PU43
--
--
--
--
--
--
--------------
4--
--
--
--
--
--
--
--
-- ----------------
5--
--
--
--
--
--
--
--
-- ----------------
6--
--
--
--
--
--
--
--
-- ----------------
7--
--
--
--
--
--
--
--
-- ----------------
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 178 of 1478
RL78/G23
CHAPTER 4 PORT FUNCTIONS
Table 4 - 2
PMxx, Pxx, PUxx, PIMxx, POMxx, PDIDISxx, PMCAxx, PMCTxx, and PMCEx Registers and the Bits Implemented in Each Product (30-Pin to 64-Pin Products with 96-Kbyte or 128-Kbyte Flash Memory) (2/3)
Port
PMxx register
Pxx register
PUxx register
Bit name
PIMxx POMxx PDIDISxx PMCAxx PMCTxx register register register register register
64 52 48 44 40 36 32 30 PMCEx pins pins pins pins pins pins pins pins register
Port 5 0 PM50 P50 PU50
-- POM50 PDIDIS50 -- PMCT50 PMCE50
1 PM51 P51 PU51
--
--
--
--
-- PMCE51
2 PM52 P52 PU52
--
--
--
--
--
--
--------------
3 PM53 P53 PU53
--
--
--
--
--
--
--------------
4 PM54 P54 PU54
--
--
--
--
--
--
--------------
5 PM55 P55 PU55 PIM55 POM55 PDIDIS55 --
--
--
--------------
6--
--
--
--
--
--
--
--
-- ----------------
7--
--
--
--
--
--
--
--
-- ----------------
Port 6 0 PM60 P60
--
--
--
--
--
-- PMCE60
1 PM61 P61
--
--
--
--
--
-- PMCE61
2 PM62 P62
--
--
--
--
--
--
--
--
3 PM63 P63
--
--
--
--
--
--
--
--------
4--
--
--
--
--
--
--
--
-- ----------------
5--
--
--
--
--
--
--
--
-- ----------------
6--
--
--
--
--
--
--
--
-- ----------------
7--
--
--
--
--
--
--
--
-- ----------------
Port 7 0 PM70 P70 PU70 --
--
--
-- PMCT70 --
--
1 PM71 P71 PU71 PIM71 POM71 PDIDIS71 -- PMCT71 --
----
2 PM72 P72 PU72
-- POM72 PDIDIS72 -- PMCT72 --
----
3 PM73 P73 PU73
--
--
--
-- PMCT73 --
------
4 PM74 P74 PU74
-- POM74 PDIDIS74 -- PMCT74 --
----------
5 PM75 P75 PU75
--
--
--
-- PMCT75 --
----------
6 PM76 P76 PU76
--
--
--
-- PMCT76 --
------------
7 PM77 P77 PU77
--
--
--
-- PMCT77 --
------------
Port 8 -- --
--
--
--
--
--
--
--
-- ----------------
Port 9 -- --
--
--
--
--
--
--
--
-- ----------------
Port 10 -- --
--
--
--
--
--
--
--
-- ----------------
Port 11 -- --
--
--
--
--
--
--
--
-- ----------------
Port 12 0 PM120 P120 PU120 -- POM120 PDIDIS PMCA --
120
120
--
1 PM121 P121 PU121 --
--
--
--
--
--
2 PM122 P122 PU122 --
--
--
--
--
--
3
--
P123
--
--
--
--
--
--
--
------
4
--
P124
--
--
--
--
--
--
--
------
5--
--
--
--
--
--
--
--
-- ----------------
6--
--
--
--
--
--
--
--
-- ----------------
7--
--
--
--
--
--
--
--
-- ----------------
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 179 of 1478
RL78/G23
CHAPTER 4 PORT FUNCTIONS
Table 4 - 2
PMxx, Pxx, PUxx, PIMxx, POMxx, PDIDISxx, PMCAxx, PMCTxx, and PMCEx Registers and the Bits Implemented in Each Product (30-Pin to 64-Pin Products with 96-Kbyte or 128-Kbyte Flash Memory) (3/3)
Port
PMxx register
Pxx register
PUxx register
Bit name
PIMxx POMxx PDIDISxx PMCAxx PMCTxx register register register register register
64 52 48 44 40 36 32 30 PMCEx pins pins pins pins pins pins pins pins register
Port 13 0 -- P130 --
--
--
--
--
--
--
----------
1--
--
--
--
--
--
--
--
-- ----------------
2--
--
--
--
--
--
--
--
-- ----------------
3--
--
--
--
--
--
--
--
-- ----------------
4--
--
--
--
--
--
--
--
-- ----------------
5--
--
--
--
--
--
--
--
-- ----------------
6--
--
--
--
--
--
--
--
-- ----------------
7
--
P137
--
--
-- PDIDIS --
--
--
137
Port 14 0 PM140 P140 PU140 --
--
--
--
--
--
----------
1 PM141 P141 PU141 --
--
--
--
--
--
--------------
2--
--
--
--
--
--
--
--
-- ----------------
3--
--
--
--
--
--
--
--
-- ----------------
4--
--
--
--
--
--
--
--
-- ----------------
5--
--
--
--
--
--
--
--
-- ----------------
6 PM146 P146 PU146 --
--
--
--
--
--
--------
7 PM147 P147 PU147 --
--
--
PMCA --
147
Port 15 -- --
--
--
--
--
--
--
--
Note
This bit is only present in the 30- and 32-pin products.
--
-- ----------------
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 180 of 1478
RL78/G23
CHAPTER 4 PORT FUNCTIONS
Table 4 - 3
PMxx, Pxx, PUxx, PIMxx, POMxx, PDIDISxx, PMCAxx, PMCTxx, and PMCEx Registers and the Bits Implemented in Each Product (Products with 192-Kbyte to 768-Kbyte Flash Memory and 80-Pin and 100Pin Products with 128-Kbyte Flash Memory) (1/4)
Bit name
Port
128 100 80 64 52 48 44 40 36 32 30
PMxx
Pxx
PUxx PIMxx POMxx PDIDISxx PMCAxx PMCTxx PMCEx pins pins pins pins pins pins pins pins pins pins pins
register register register register register register register register register
Port 0 0 PM00 P00 PU00
-- POM00 PDIDIS00 PMCA00 PMCT00 --
Note
1 PM01 P01 PU01 PIM01
--
-- PMCA01 PMCT01 PMCE01
Note
2 PM02 P02 PU02
-- POM02 PDIDIS02 PMCA02 PMCT02 --
------------
3 PM03 P03 PU03 PIM03 POM03 PDIDIS03 PMCA03 PMCT03 --
------------
4 PM04 P04 PU04 PIM04 POM04 PDIDIS04 --
--
--
--------------
5 PM05 P05 PU05
--
--
--
-- PMCT05 --
--------------
6 PM06 P06 PU06
--
--
--
-- PMCT06 --
--------------
7 PM07 P07 PU07
--
--
--
--
--
--
--------------------
Port 1 0 PM10 P10 PU10 PIM10 POM10 PDIDIS10 --
-- PMCE10
1 PM11 P11 PU11 PIM11 POM11 PDIDIS11 --
-- PMCE11
2 PM12 P12 PU12
-- POM12 PDIDIS12 --
-- PMCE12
3 PM13 P13 PU13 PIM13 POM13 PDIDIS13 PMCA13 -- PMCE13
4 PM14 P14 PU14 PIM14 POM14 PDIDIS14 --
-- PMCE14
5 PM15 P15 PU15 PIM15 POM15 PDIDIS15 --
-- PMCE15
6 PM16 P16 PU16 PIM16
--
--
--
-- PMCE16
7 PM17 P17 PU17 PIM17 POM17 PDIDIS17 --
-- PMCE17
Port 2 0 PM20 P20
--
--
--
-- PMCA20 --
--
1 PM21 P21
--
--
--
-- PMCA21 --
--
2 PM22 P22
--
--
--
-- PMCA22 PMCT22 --
3 PM23 P23
--
--
--
-- PMCA23 PMCT23 --
4 PM24 P24
--
--
--
-- PMCA24 PMCT24 --
----
5 PM25 P25
--
--
--
-- PMCA25 PMCT25 --
----
6 PM26 P26
--
--
--
-- PMCA26 PMCT26 --
------
7 PM27 P27
--
--
--
-- PMCA27 PMCT27 --
--------
Port 3 0 PM30 P30 PU30
--
--
--
-- PMCT30 --
1 PM31 P31 PU31
--
--
--
-- PMCT31 --
2 PM32 P32 PU32
--
--
--
--
--
--
--------------------
3 PM33 P33 PU33 PIM33
--
--
--
--
--
--------------------
4 PM34 P34 PU34
-- POM34 PDIDIS34 --
--
--
--------------------
5 PM35 P35 PU35
--
--
-- PMCA35 --
--
--------------------
6 PM36 P36 PU36
--
--
-- PMCA36 --
--
--------------------
7 PM37 P37 PU37
--
--
-- PMCA37 --
--
--------------------
Port 4 0 PM40 P40 PU40
--
--
--
--
--
--
1 PM41 P41 PU41 PIM41
--
--
--
--
--
--------
2 PM42 P42 PU42
-- POM42 PDIDIS42 --
--
--
--------------
3 PM43 P43 PU43 PIM43 POM43 PDIDIS43 --
--
--
--------------
4 PM44 P44 PU44 PIM44 POM44 PDIDIS44 --
--
--
----------------
5 PM45 P45 PU45
-- POM45 PDIDIS45 --
--
--
----------------
6 PM46 P46 PU46
--
--
--
--
--
--
------------------
7 PM47 P47 PU47
--
--
--
--
--
--
------------------
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 181 of 1478
RL78/G23
CHAPTER 4 PORT FUNCTIONS
Table 4 - 3
PMxx, Pxx, PUxx, PIMxx, POMxx, PDIDISxx, PMCAxx, PMCTxx, and PMCEx Registers and the Bits Implemented in Each Product (Products with 192-Kbyte to 768-Kbyte Flash Memory and 80-Pin and 100Pin Products with 128-Kbyte Flash Memory) (2/4)
Bit name
Port
128 100 80 64 52 48 44 40 36 32 30
PMxx
Pxx
PUxx PIMxx POMxx PDIDISxx PMCAxx PMCTxx PMCEx pins pins pins pins pins pins pins pins pins pins pins
register register register register register register register register register
Port 5 0 PM50 P50 PU50
-- POM50 PDIDIS50 -- PMCT50 PMCE50
1 PM51 P51 PU51
--
--
--
--
-- PMCE51
2 PM52 P52 PU52
-- POM52 PDIDIS52 --
--
--
--------------
3 PM53 P53 PU53 PIM53 POM53 PDIDIS53 --
--
--
--------------
4 PM54 P54 PU54 PIM54 POM54 PDIDIS54 --
--
--
--------------
5 PM55 P55 PU55 PIM55 POM55 PDIDIS55 --
--
--
--------------
6 PM56 P56 PU56
--
--
--
--
--
--
------------------
7 PM57 P57 PU57
--
--
--
--
--
--
------------------
Port 6 0 PM60 P60
--
--
--
--
--
-- PMCE60
1 PM61 P61
--
--
--
--
--
-- PMCE61
2 PM62 P62
--
--
--
--
--
--
--
--
3 PM63 P63
--
--
--
--
--
--
--
--------
4 PM64 P64 PU64
--
--
--
-- PMCT64 --
----------------
5 PM65 P65 PU65
--
--
--
-- PMCT65 --
----------------
6 PM66 P66 PU66
--
--
--
-- PMCT66 --
----------------
7 PM67 P67 PU67
--
--
--
-- PMCT67 --
Port 7 0 PM70 P70 PU70
--
--
--
-- PMCT70 --
1 PM71 P71 PU71 PIM71 POM71 PDIDIS71 -- PMCT71 --
2 PM72 P72 PU72
-- POM72 PDIDIS72 -- PMCT72 --
3 PM73 P73 PU73
--
--
--
-- PMCT73 --
---------------- -- ---- ---- ------
4 PM74 P74 PU74
-- POM74 PDIDIS74 -- PMCT74 --
----------
5 PM75 P75 PU75
--
--
--
-- PMCT75 --
----------
6 PM76 P76 PU76
--
--
--
-- PMCT76 --
------------
7 PM77 P77 PU77
--
--
--
-- PMCT77 --
Port 8 0 PM80 P80 PU80 PIM80 POM80 PDIDIS80 --
--
--
1 PM81 P81 PU81 PIM81 POM81 PDIDIS81 --
--
--
2 PM82 P82 PU82
-- POM82 PDIDIS82 --
--
--
------------ ------------------ ------------------ ------------------
3 PM83 P83 PU83
-- POM83 PDIDIS83 --
--
--
------------------
4 PM84 P84 PU84 PIM84
--
--
--
--
--
------------------
5 PM85 P85 PU85
--
--
--
--
--
--
------------------
6 PM86 P86 PU86
--
--
--
--
--
--
------------------
7 PM87 P87 PU87
--
--
--
--
--
--
------------------
Port 9 0 PM90 P90 PU90
--
--
--
--
--
--
--------------------
1 PM91 P91 PU91
--
--
--
--
--
--
--------------------
2 PM92 P92 PU92
--
--
--
--
--
--
--------------------
3 PM93 P93 PU93
--
--
--
--
--
--
--------------------
4 PM94 P94 PU94
--
--
--
--
--
--
--------------------
5 PM95 P95 PU95
--
--
--
--
--
--
--------------------
6 PM96 P96 PU96
-- POM96 PDIDIS96 --
--
--
--------------------
7 PM97 P97 PU97
--
--
--
--
--
--
--------------------
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 182 of 1478
RL78/G23
CHAPTER 4 PORT FUNCTIONS
Table 4 - 3
PMxx, Pxx, PUxx, PIMxx, POMxx, PDIDISxx, PMCAxx, PMCTxx, and PMCEx Registers and the Bits Implemented in Each Product (Products with 192-Kbyte to 768-Kbyte Flash Memory and 80-Pin and 100Pin Products with 128-Kbyte Flash Memory) (3/4)
Bit name
Port
128 100 80 64 52 48 44 40 36 32 30
PMxx
Pxx
PUxx PIMxx POMxx PDIDISxx PMCAxx PMCTxx PMCEx pins pins pins pins pins pins pins pins pins pins pins
register register register register register register register register register
Port 10 0 PM100 P100 PU100 --
--
--
PMCA
--
100
--
----------------
1 PM101 P101 PU101 --
--
--
--
--
--
------------------
2 PM102 P102 PU102 --
--
--
--
--
--
------------------
3 PM103 P103 PU103 --
--
--
--
--
--
--------------------
4 PM104 P104 PU104 --
--
--
--
--
--
--------------------
5 PM105 P105 PU105 --
--
--
--
--
--
--------------------
6 PM106 P106 PU106 --
--
--
--
--
--
--------------------
7--
--
--
--
--
--
--
--
-- -- --------------------
Port 11 0 PM110 P110 PU110 --
--
--
--
--
--
----------------
1 PM111 P111 PU111
--
--
--
--
--
--
----------------
2 PM112 P112 PU112 --
--
--
--
--
--
--------------------
3 PM113 P113 PU113 --
--
--
--
--
--
--------------------
4 PM114 P114 PU114 --
--
--
--
--
--
--------------------
5 PM115 P115 PU115 --
--
--
PMCA
--
115
6 PM116 P116 PU116 --
--
--
PMCA
--
116
7 PM117 P117 PU117 --
--
--
PMCA
--
117
Port 12 0 PM120 P120 PU120
-- POM120 PDIDIS PMCA
--
120
120
--
--------------------
--
--------------------
--
--------------------
--
1 PM121 P121 PU121 --
--
--
--
--
--
2 PM122 P122 PU122 --
--
--
--
--
--
3--
P123
--
--
--
--
--
--
--
------
4--
P124
--
--
--
--
--
--
--
------
5 PM125 P125 PU125 --
--
--
--
--
--
--------------------
6 PM126 P126 PU126 --
--
--
--
--
--
--------------------
7 PM127 P127 PU127 --
--
--
--
--
--
--------------------
Port 13 0 --
P130
--
--
--
--
--
--
--
----------
1--
--
--
--
--
--
--
--
-- -- --------------------
2--
--
--
--
--
--
--
--
-- -- --------------------
3--
--
--
--
--
--
--
--
-- -- --------------------
4--
--
--
--
--
--
--
--
-- -- --------------------
5--
--
--
--
--
--
--
--
-- -- --------------------
6--
--
--
--
--
--
--
--
-- -- --------------------
7--
P137
--
--
--
PDIDIS
--
--
--
137
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 183 of 1478
RL78/G23
CHAPTER 4 PORT FUNCTIONS
Table 4 - 3
PMxx, Pxx, PUxx, PIMxx, POMxx, PDIDISxx, PMCAxx, PMCTxx, and PMCEx Registers and the Bits Implemented in Each Product (Products with 192-Kbyte to 768-Kbyte Flash Memory and 80-Pin and 100Pin Products with 128-Kbyte Flash Memory) (4/4)
Bit name
Port
128 100 80 64 52 48 44 40 36 32 30
PMxx
Pxx
PUxx PIMxx POMxx PDIDISxx PMCAxx PMCTxx PMCEx pins pins pins pins pins pins pins pins pins pins pins
register register register register register register register register register
Port 14 0 PM140 P140 PU140 --
--
--
--
--
--
----------
1 PM141 P141 PU141 --
--
--
--
--
--
--------------
2 PM142 P142 PU142 PIM142 POM142 PDIDIS
--
--
--
----------------
142
3 PM143 P143 PU143 PIM143 POM143 PDIDIS
--
--
--
----------------
143
4 PM144 P144 PU144
-- POM144 PDIDIS
--
--
--
----------------
144
5 PM145 P145 PU145 --
--
--
--
--
--
------------------
6 PM146 P146 PU146 --
--
7 PM147 P147 PU147 --
--
--
--
--
--
PMCA
--
147
--
--------
--
Port 15 0 PM150 P150
--
--
--
--
PMCA PMCT
--
----------------
150
150
1 PM151 P151
--
--
--
--
PMCA PMCT
--
----------------
151
151
2 PM152 P152
--
--
--
3 PM153 P153
--
--
--
4 PM154 P154
--
--
--
5 PM155 P155
--
--
--
--
PMCA PMCT
--
----------------
152
152
--
PMCA PMCT
--
----------------
153
153
--
PMCA PMCT
--
------------------
154
154
--
PMCA PMCT
--
------------------
155
155
6 PM156 P156
--
--
--
--
PMCA
--
156
--
------------------
7--
--
--
--
--
--
--
--
Note
This bit is only present in the 30- and 32-pin products.
-- -- --------------------
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 184 of 1478
RL78/G23
CHAPTER 4 PORT FUNCTIONS
4.3.1 Port mode registers (PMxx)
These registers specify input or output mode for the ports in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. The value of each PMxx register is FFH following a reset. To use an alternate function of a port pin, set the port mode register by referencing 4.5 Register Settings When Using Alternate Function.
Figure 4 - 1 Format of Port Mode Registers
Symbol 7
6
5
4
3
2
1
0
Address
After reset
R/W
PM0 PM07 PM06 PM05 PM04 PM03 PM02 PM01 PM00
FFF20H
FFH
R/W
PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10
FFF21H
FFH
R/W
PM2 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20
FFF22H
FFH
R/W
PM3 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30
FFF23H
FFH
R/W
PM4 PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40
FFF24H
FFH
R/W
PM5 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50
FFF25H
FFH
R/W
PM6 PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60
FFF26H
FFH
R/W
PM7 PM77 PM76 PM75 PM74 PM73 PM72 PM71 PM70
FFF27H
FFH
R/W
PM8 PM87 PM86 PM85 PM84 PM83 PM82 PM81 PM80
FFF28H
FFH
R/W
PM9 PM97 PM96 PM95 PM94 PM93 PM92 PM91 PM90
FFF29H
FFH
R/W
PM10 1 PM106 PM105 PM104 PM103 PM102 PM101 PM100 FFF2AH
FFH
R/W
PM11 PM117 PM116 PM115 PM114 PM113 PM112 PM111 PM110 FFF2BH
FFH
R/W
PM12 PM127 PM126 PM125 1
1 PM122 PM121 PM120 FFF2CH
FFH
R/W
PM14 PM147 PM146 PM145 PM144 PM143 PM142 PM141 PM140 FFF2EH
FFH
R/W
PM15 1 PM156 PM155 PM154 PM153 PM152 PM151 PM150 FFF2FH
FFH
R/W
PMmn
0 1 Caution
Pmn pin I/O mode selection (m = 0 to 12, 14, 15; n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off) Be sure to set bits that are not implemented to their initial values.
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4.3.2 Port registers (Pxx)
These registers set the output latch values of ports. If data is read in the input mode, the pin level is read. If data is read in the output mode, the output latch value is readNote. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. The value of each Pxx register is 00H following a reset.
Note
If P00 to P03, P13, P20 to P27, P35 to P37, P100, P115 to P117, P120, P147, or P150 to P156 is set up as an analog function port, when the port is read in the input mode, 0 is always returned instead of the pin level.
Caution
If P00 to P03, P05, P06, P22 to P27, P30, P31, P50, P64 to P67, P70 to P77, or P150 to P155 is set up as a capacitance measurement port, when the port is read in the input mode, 0 is always returned instead of the pin level.
Figure 4 - 2 Format of Port Registers
Symbol 7
6
5
4
3
2
1
0
P0 P07 P06 P05 P04 P03 P02 P01 P00
P1 P17 P16 P15 P14 P13 P12 P11 P10
P2 P27 P26 P25 P24 P23 P22 P21 P20
P3 P37 P36 P35 P34 P33 P32 P31 P30
P4 P47 P46 P45 P44 P43 P42 P41 P40
P5 P57 P56 P55 P54 P53 P52 P51 P50
P6 P67 P66 P65 P64 P63 P62 P61 P60
P7 P77 P76 P75 P74 P73 P72 P71 P70
P8 P87 P86 P85 P84 P83 P82 P81 P80
P9 P97 P96 P95 P94 P93 P92 P91 P90
P10 0 P106 P105 P104 P103 P102 P101 P100
P11 P117 P116 P115 P114 P113 P112 P111 P110
P12 P127 P126 P125 P124 P123 P122 P121 P120
P13 P137 0
0
0
0
0
0 P130
P14 P147 P146 P145 P144 P143 P142 P141 P140
P15 0 P156 P155 P154 P153 P152 P151 P150
Address
FFF00H FFF01H FFF02H FFF03H FFF04H FFF05H FFF06H FFF07H FFF08H FFF09H FFF0AH FFF0BH FFF0CH FFF0DH FFF0EH FFF0FH
After reset
R/W
00H (output latch) 00H (output latch) 00H (output latch) 00H (output latch) 00H (output latch) 00H (output latch) 00H (output latch) 00H (output latch) 00H (output latch) 00H (output latch) 00H (output latch) 00H (output latch)
Undefined Note 2
00H (output latch) 00H (output latch)
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WNote 1 R/WNote 1 R/W R/W
Pmn
0
1 Note 1. Note 2.
Output data control (in output mode) Output 0
Output 1
P123, P124, and P137 are read-only. P137: Undefined P130: 0 (output latch)
Input data read (in input mode) Input low level Input high level
Caution Be sure to set bits that are not implemented to their initial values.
Remark m = 0 to 15; n = 0 to 7
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4.3.3 Pull-up resistor option registers (PUxx)
These registers specify whether to use the on-chip pull-up resistors. On-chip pull-up resistors can be used in 1-bit units only for the bits set to both normal output mode (POMmn = 0) and input mode (PMmn = 1) for the pins to which the use of an on-chip pull-up resistor has been specified in these registers. On-chip pull-up resistors are not connected to bits set to output mode and bits used as alternate-function output pins, regardless of the settings of these registers. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. The value of the PU4 register is 01H following a reset, and that of the other PUxx is 00H.
Caution
When data is input from a different-potential device to the TTL buffer for a port with the PIMn register, set PUmn = 0 and pull up to the power supply of the different-potential device via an external resistor.
Figure 4 - 3 Format of Pull-up Resistor Option Registers
Symbol 7
6
5
4
3
2
1
0
Address
After reset
R/W
PU0 PU07 PU06 PU05 PU04 PU03 PU02 PU01 PU00
F0030H
00H
R/W
PU1 PU17 PU16 PU15 PU14 PU13 PU12 PU11 PU10
F0031H
00H
R/W
PU3 PU37 PU36 PU35 PU34 PU33 PU32 PU31 PU30
F0033H
00H
R/W
PU4 PU47 PU46 PU45 PU44 PU43 PU42 PU41 PU40
F0034H
01H
R/W
PU5 PU57 PU56 PU55 PU54 PU53 PU52 PU51 PU50
F0035H
00H
R/W
PU6 PU67 PU66 PU65 PU64 0
0
0
0
F0036H
00H
R/W
PU7 PU77 PU76 PU75 PU74 PU73 PU72 PU71 PU70
F0037H
00H
R/W
PU8 PU87 PU86 PU85 PU84 PU83 PU82 PU81 PU80
F0038H
00H
R/W
PU9 PU97 PU96 PU95 PU94 PU93 PU92 PU91 PU90
F0039H
00H
R/W
PU10 0 PU106 PU105 PU104 PU103 PU102 PU101 PU100 F003AH
00H
R/W
PU11 PU117 PU116 PU115 PU114 PU113 PU112 PU111 PU110 F003BH
00H
R/W
PU12 PU127 PU126 PU125 0
0 PU122 PU121 PU120 F003CH
00H
R/W
PU14 PU147 PU146 PU145 PU144 PU143 PU142 PU141 PU140 F003EH
00H
R/W
PUmn
0 1 Caution
Pmn pin on-chip pull-up resistor selection (m = 0, 1, 3 to 12, 14; n = 0 to 7)
On-chip pull-up resistor not connected On-chip pull-up resistor connected Be sure to set bits that are not implemented to their initial values.
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4.3.4 Port input mode registers (PIMxx)
These registers set the input buffer in 1-bit units. TTL input buffer can be selected during serial communication with an external device of the different potential. Port input mode registers can be set by a 1-bit or 8-bit memory manipulation instruction. The value of each PIMxx register is 00H following a reset.
Figure 4 - 4 Format of Port Input Mode Registers (128-pin products)
Symbol 7
6
5
4
3
2
1
0
Address
After reset
R/W
PIM0 0
0
0 PIM04 PIM03 0 PIM01 0
F0040H
00H
R/W
PIM1 PIM17 PIM16 PIM15 PIM14 PIM13 0 PIM11 PIM10
F0041H
00H
R/W
PIM3 0
0
0
0 PIM33 0
0
0
F0043H
00H
R/W
PIM4 0
0
0 PIM44 PIM43 0 PIM41 0
F0044H
00H
R/W
PIM5 0
0 PIM55 PIM54 PIM53 0
0
0
F0045H
00H
R/W
PIM7 0
0
0
0
0
0 PIM71 0
F0047H
00H
R/W
PIM8 0
0
0 PIM84 0
0 PIM81 PIM80
F0048H
00H
R/W
PIM14 0
0
0
0 PIM143 PIM142 0
0
F004EH
00H
R/W
PIMmn
0 1 Caution
Pmn pin input buffer selection (m = 0, 1, 3, 4, 5, 7, 8, 14; n = 0 to 7) Normal input buffer TTL input buffer Be sure to set bits that are not implemented to their initial values.
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4.3.5 Port output mode registers (POMxx)
These registers set the output mode in 1-bit units. N-ch open drain output (VDD tolerance Note 1/EVDD tolerance Note 2) mode can be selected during serial communication with an external device of the different potential, and for the SDA00, SDA01, SDA10, SDA11, SDA20, SDA21, SDA30, and SDA31 pins during simplified I2C communication with an external device of the same potential. In addition, POMxx registers are used in combination with PUxx registers to specify whether to use on-chip pull-up resistors. The POMxx registers can be set by a 1-bit or 8-bit memory manipulation instruction. The value of each POMxx register is 00H following a reset.
Caution
An on-chip pull-up resistor is not connected to a bit for which N-ch open drain output (VDD tolerance Note 1/EVDD tolerance Note 2) mode (POMmn = 1) is set.
Figure 4 - 5 Format of Port Input Mode Registers
Symbol 7
6
5
4
3
2
1
0
Address
After reset
R/W
POM0 0
0
0 POM04 POM03 POM02 0 POM00 F0050H
00H
R/W
POM1 POM17 0 POM15 POM14 POM13 POM12 POM11 POM10 F0051H
00H
R/W
POM3 0
0
0 POM34 0
0
0
0
F0053H
00H
R/W
POM4 0
0 POM45 POM44 POM43 POM42 0
0
F0054H
00H
R/W
POM5 0
0 POM55 POM54 POM53 POM52 0 POM50 F0055H
00H
R/W
POM7 0
0
0 POM74 0 POM72 POM71 0
F0057H
00H
R/W
POM8 0
0
0
0 POM83 POM82 POM81 POM80 F0058H
00H
R/W
POM9 0 POM96 0
0
0
0
0
0
F0059H
00H
R/W
POM12 0
0
0
0
0
0
0
POM 120
F005CH
00H
R/W
POM14 0
0
0
POM POM POM 144 143 142
0
0
F005EH
00H
R/W
POMmn
0 1 Note 1. Note 2.
Pmn pin output mode selection (m = 0, 1, 3 to 5, 7 to 9, 12, 14; n = 0 to 7) Normal output mode N-ch open-drain output (VDD tolerance Note 1/EVDD tolerance Note 2) mode For 30- to 52-pin products For 64- to 128-pin products
Caution Be sure to set bits that are not implemented to their initial values.
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4.3.6 Port digital input disable registers (PDIDISxx)
These registers are used to prevent through-current flowing into input buffers. When N-ch open drain output is selected for serial communications with an external device of the different potential or an input port is not used, low power consumption can be achieved by setting the corresponding PDIDIS register bit to 1. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. The value of each PDIDISxx register is 00H following a reset.
Figure 4 - 6 Format of Port Digital Input Disable Registers
Symbol 7
6
5
4
3
2
1
0
Address
After reset
R/W
PDIDIS0 0
0
0
PDIDIS PDIDIS PDIDIS
04
03
02
0
PDIDIS 00
F02B0H
00H
R/W
PDIDIS1 PDIDIS 17
0
PDIDIS PDIDIS PDIDIS PDIDIS PDIDIS PDIDIS
15
14
13
12
11
10
F02B1H
00H
R/W
PDIDIS3 0
0
0
PDIDIS 34
0
0
0
0
F02B3H
00H
R/W
PDIDIS4 0
0
PDIDIS PDIDIS PDIDIS PDIDIS
45
44
43
42
0
0
F02B4H
00H
R/W
PDIDIS5 0
0
PDIDIS PDIDIS PDIDIS PDIDIS
55
54
53
52
0
PDIDIS 50
F02B5H
00H
R/W
PDIDIS7 0
0
0
PDIDIS 74
0
PDIDIS PDIDIS
72
71
0
F02B7H
00H
R/W
PDIDIS8 0
0
0
0
PDIDIS PDIDIS PDIDIS PDIDIS
83
82
81
80
F02B8H
00H
R/W
PDIDIS9
0
PDIDIS 96
0
0
0
0
0
0
F02B9H
00H
R/W
PDIDIS12 0
0
0
0
0
0
0
PDIDIS 120
F02BCH
00H
R/W
PDIDIS13 PDIDIS 137
0
0
0
0
0
0
0
F02BDH
00H
R/W
PDIDIS14 0
0
0
PDIDIS PDIDIS PDIDIS 144 143 142
0
0
F02BEH
00H
R/W
PDIDISmn
Setting of input buffers (m = 0, 1, 3 to 5, 7 to 9, 12 to 14; n = 0 to 7)
0
Input to the input buffer is enabled (default)
1
Input to the input buffer is disabled. Through-current flowing into the input buffer is prevented.
Caution Be sure to set bits that are not implemented to their initial values.
Remark
For P123 and P124, low power consumption can be achieved by setting the EXCLKS bit to 0 and the OSCSELS bit to 1 in the clock operation mode control register (CMC) and setting the XTSTOP bit to 1 in the clock operation status control register (CSC).
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4.3.7 Port mode control A registers (PMCAxx)
These registers specify the digital I/O or analog input function in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. The value of each PMCAxx register is FFH following a reset.
Figure 4 - 7 Format of Port Mode Control A Registers
Symbol 7
6
5
4
3
2
1
0
Address
After reset
R/W
PMCA0 1
1
1
1
PMCA0 PMCA0 PMCA0 PMCA0
3
2
1
0
F0060H
FFH
R/W
PMCA1 1
1
1
1
PMCA1 3
1
1
1
F0061H
FFH
R/W
PMCA2 PMCA2 PMCA2 PMCA2 PMCA2 PMCA2 PMCA2 PMCA2 PMCA2 F0062H
FFH
R/W
7
6
5
4
3
2
1
0
PMCA3 PMCA3 PMCA3 PMCA3
7
6
5
1
1
1
1
1
F0063H
FFH
R/W
PMCA10 1
1
1
1
1
1
1
PMCA1 00
F006AH
FFH
R/W
PMCA11 PMCA1 PMCA1 PMCA1
17
16
15
1
1
1
1
1
F006BH
FFH
R/W
PMCA12 1
1
1
1
1
1
1
PMCA1 20
F006CH
FFH
R/W
PMCA14 PMCA1 47
1
1
1
1
1
1
1
F006EH
FFH
R/W
PMCA15
1
PMCA1 PMCA1 PMCA1 PMCA1 PMCA1 PMCA1 PMCA1
56
55
54
53
52
51
50
F006FH
FFH
R/W
PMCAmn
Selection of digital I/O or analog input function for Pmn pin (m = 0 to 3, 10 to 12, 14, 15; n = 0 to 7)
0
Digital I/O
1
Analog input function
Caution 1. Select input mode by using port mode register 0 to 3, 10 to 12, 14, or 15 (PM0 to PM3, PM10 to PM12, PM14, or PM15) for the port which is set to the analog input function by the PMCAxx register.
Caution 2. Do not set the pin that is specified as digital I/O by the PMCAxx register to the analog function by the analog input channel specification register (ADS).
Caution 3. Be sure to set bits that are not implemented to their initial values.
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4.3.8 Port mode control T registers (PMCTxx)
These registers specify the digital I/O or capacitance measurement function in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. The value of each PMCTxx register is 00H following a reset.
Figure 4 - 8 Format of Port Mode Control T Registers
Symbol 7
6
5
4
3
2
1
0
Address
After reset
R/W
PMCT0
0
PMCT0 PMCT0
6
5
0
PMCT0 PMCT0 PMCT0 PMCT0
3
2
1
0
F0260H
00H
R/W
PMCT2 PMCT2 PMCT2 PMCT2 PMCT2 PMCT2 PMCT2
7
6
5
4
3
2
0
0
F0262H
00H
R/W
PMCT3 0
0
0
0
0
0
PMCT3 PMCT3
1
0
F0263H
00H
R/W
PMCT5 0
0
0
0
0
0
0
PMCT5 0
F0265H
00H
R/W
PMCT6 PMCT6 PMCT6 PMCT6 PMCT6
7
6
5
4
0
0
0
0
F0266H
00H
R/W
PMCT7 PMCT7 PMCT7 PMCT7 PMCT7 PMCT7 PMCT7 PMCT7 PMCT7 F0267H
00H
R/W
7
6
5
4
3
2
1
0
PMCT15 0
0
PMCT1 PMCT1 PMCT1 PMCT1 PMCT1 PMCT1
55
54
53
52
51
50
F026FH
00H
R/W
PMCTmn
Selection of digital I/O or capacitance measurement function for Pmn pin (m = 0, 2, 3, 5 to 7, 15; n = 0 to 7)
0
Digital I/O
1
Capacitance measurement function
Caution Be sure to set bits that are not implemented to their initial values.
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4.3.9 Port mode control E registers (PMCEx)
These registers specify the digital I/O or ELCL output function in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. The value of each PMCEx register is 00H following a reset.
Figure 4 - 9 Format of Port Mode Control E Registers
Symbol 7
6
5
4
3
2
1
0
Address
After reset
R/W
PMCE0 0
0
0
0
0
0
PMCE0 1
0
F0280H
00H
R/W
PMCE1 PMCE1 PMCE1 PMCE1 PMCE1 PMCE1 PMCE1 PMCE1 PMCE1 F0281H
00H
R/W
7
6
5
4
3
2
1
0
PMCE5 0
0
0
0
0
0
PMCE5 PMCE5
1
0
F0285H
00H
R/W
PMCE6 0
0
0
0
0
0
PMCE6 PMCE6
1
0
F0286H
00H
R/W
PMCEmn
Selection of digital I/O or ELCL output function for Pmn pin (m = 0, 1, 5, 6; n = 0 to 7)
0
Digital I/O
1
ELCL output function
Caution Be sure to set bits that are not implemented to their initial values.
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4.3.10 Peripheral I/O redirection register (PIOR)
This register is used to specify whether to enable or disable the peripheral I/O redirect function. This function is used to switch ports to which alternate functions are assigned. Use the PIOR register to assign a port to the function to redirect and then enable the function. In addition, the settings for redirection can be changed only until operation of the function is enabled. The PIOR register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 4 - 10 Format of Peripheral I/O Redirection Register (PIOR)
Address: F0077H
After reset: 00H
R/W:
R/W
Symbol
7
PIOR
0
6
5
4
3
2
1
0
0
PIOR5
PIOR4
PIOR3
PIOR2
PIOR1
PIOR0
128- and
40-, 36-, 32-,
80-pin
64-pin
52-pin
48-pin
44-pin
Alternative
100-pin
and 30-pin
Bit
function Setting value Setting value Setting value Setting value Setting value Setting value Setting value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PIOR5 INTP1
P46 P56
INTP3
P30 P57
INTP4
P31 P146
INTP6
P140 P84
INTP7
P141 P85
INTP8
P74 P86
INTP9
P75 P87
These functions are not available for use. Set this bit to 0 (default value).
TxD1
P02 P82
RxD1
P03 P81
SCL10
P04 P80
SDA10
P03 P81
SI10
P03 P81
SO10
P02 P82
SCK10
P04 P80
PIOR4 PCLBUZ1 P141 P55 P141 P55 P141 P55
INTP5
P16 P12 P16 P12 P16 P12
PIOR3 PCLBUZ0 P140 P31 P140 P31 P140 P31 P140 P31 P140 P31
PIOR2 SCLA0
P60 P14 P60 P14 P60 P14 P60 P14 P60 P14 P60 P14 P60 P14
SDAA0
P61 P13 P61 P13 P61 P13 P61 P13 P61 P13 P61 P13 P61 P13
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128- and
80-pin
64-pin
Alternative
100-pin
Bit
function Setting value Setting value Setting value
0
1
0
1
0
1
PIOR1 INTP10
P76 P110 P76 P110 P76 P52
INTP11
P77 P111 P77 P111 P77 P53
TxD2
P13 P77 P13 P77 P13 P77
RxD2
P14 P76 P14 P76 P14 P76
SCL20
P15 -- P15 -- P15 --
SDA20
P14 -- P14 -- P14 --
SI20
P14 -- P14 -- P14 --
SO20
P13 -- P13 -- P13 --
SCK20
P15 -- P15 -- P15 --
TxD0
P12 P17 P12 P17 P12 P17
RxD0
P11 P16 P11 P16 P11 P16
SCL00
P10 -- P10 -- P10 --
SDA00
P11 -- P11 -- P11 --
SI00
P11 P16 P11 P16 P11 P16
SO00
P12 P17 P12 P17 P12 P17
SCK00
P10 P55 P10 P55 P10 P55
PIOR0 TI02/TO02 P17 P15 P17 P15 P17 P15
TI03/TO03 P31 P14 P31 P14 P31 P14
TI04/TO04 P42 P13 P42 P13 P42 P13
TI05/TO05 P46 P12 P05 P12 P05 P12
TI06/TO06 P102 P11 P06 P11 P06 P11
TI07/TO07 P145 P10 P41 P10 P41 P10 Remark --: These functions are not available for use.
52-pin
Setting value
0
1
P76 --
P77 --
P13 P77
P14 P76
P15 --
P14 --
P14 --
P13 --
P15 --
P12 P17
P11 P16
P10 --
P11 --
P11 --
P12 --
P10 --
P17 P15
P31 P14
-- P13
-- P12
-- P11
P41 P10
48-pin
Setting value
0
1
--
--
--
--
P13 --
P14 --
P15 --
P14 --
P14 --
P13 --
P15 --
P12 P17
P11 P16
P10 --
P11 --
P11 --
P12 --
P10 --
P17 P15
P31 P14
-- P13
-- P12
-- P11
P41 P10
44-pin
Setting value
0
1
--
--
--
--
P13 --
P14 --
P15 --
P14 --
P14 --
P13 --
P15 --
P12 P17
P11 P16
P10 --
P11 --
P11 --
P12 --
P10 --
P17 P15
P31 P14
-- P13
-- P12
-- P11
P41 P10
40-, 36-, 32-,
and 30-pin
Setting value
0
1
--
--
--
--
P13 --
P14 --
P15 --
P14 --
P14 --
P13 --
P15 --
P12 P17
P11 P16
P10 --
P11 --
P11 --
P12 --
P10 --
P17 P15
P31 P14
-- P13
-- P12
-- P11
-- P10
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4.3.11 Global digital input disable register (GDIDIS)
This register is used to prevent through-current flowing into the input buffers of input ports which use EVDD as the power supply when the EVDD power supply is turned off. When none of the I/O ports using EVDD as the power supply are used, low power consumption can be achieved by setting the GDIDIS register (setting the GDIDIS0 bit to 1) to turn off the EVDD power supply. By setting the GDIDIS0 bit to 1, input to any input buffer using EVDD as the power supply is prohibited, preventing through-current from flowing when the EVDD power supply is turned off. The GDIDIS register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Remark The GDIDIS register is equipped with 64-, 80-, 100-, and 128-pin products.
Figure 4 - 11 Format of Global Digital Input Disable Register (GDIDIS)
Address: F007DH
After reset: 00H
R/W:
R/W
Symbol
7
6
5
4
3
2
1
GDIDIS
0
0
0
0
0
0
0
GDIDIS0 0 1
Setting of input buffers using EVDD power supply Input to input buffers permitted (default) Input to input buffers prohibited. No through-current flows to the input buffers.
0 GDIDIS0
Turn off the EVDD power supply with the following procedure. 1. Prohibit input to input buffers (set GDIDIS0 = 1). 2. Turn off the EVDD power supply.
Turn on again the EVDD power supply with the following procedure. 1. Turn on the EVDD power supply. 2. Permit input to input buffers (set GDIDIS0 = 0).
Caution 1. Do not input an input voltage equal to or greater than EVDD to an input port that uses EVDD as the power supply. Caution 2. When input to input buffers is prohibited (GDIDIS0 = 1), the value read from the port register (Pxx) of a port that
uses EVDD as the power supply is 1. When 1 is set in the port output mode register (POMxx) (N-ch open drain output (EVDD tolerance) mode), the value read from the port register (Pxx) is 0.
Remark 1. The GDIDIS register is equipped with 64-, 80-, 100-, and 128-pin products. Remark 2. Even when input to input buffers is prohibited (GDIDIS0 = 1), peripheral functions which do not use port functions having
EVDD as the power supply can be used.
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4.3.12 Output current control enable register (CCDE)
This register is used to specify the use of P16, P17, P50, P51, and P60 to P63 as output current control port pins in 1-bit units. The setting of the corresponding output current select register (CCSx) controls a pin for which this function is selected to be at the low level and produce the selected output current (low-level output current) or to be in the highimpedance state. The CCDE register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 4 - 12 Format of Output Current Control Enable Register (CCDE)
Address: F02A8H
After reset: 00H
R/W:
R/W
Symbol
7
CCDE CCDE07
6 CCDE06
5 CCDE05
4 CCDE04
3 CCDE03
2 CCDE02
1 CCDE01
0 CCDE00
CCDE07 0 1
Selection of digital I/O or output current control function for CCD07 (P63) pin Digital I/O (alternate function other than current control function) Current control function
CCDE06 0 1
Selection of digital I/O or output current control function for CCD06 (P62) pin Digital I/O (alternate function other than current control function) Current control function
CCDE05 0 1
Selection of digital I/O or output current control function for CCD05 (P61) pin Digital I/O (alternate function other than current control function) Current control function
CCDE04 0 1
Selection of digital I/O or output current control function for CCD04 (P60) pin Digital I/O (alternate function other than current control function) Current control function
CCDE03 0 1
Selection of digital I/O or output current control function for CCD03 (P50) pin Digital I/O (alternate function other than current control function) Current control function
CCDE02 0 1
Selection of digital I/O or output current control function for CCD02 (P51) pin Digital I/O (alternate function other than current control function) Current control function
CCDE01 0 1
Selection of digital I/O or output current control function for CCD01 (P17) pin Digital I/O (alternate function other than current control function) Current control function
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<R>
CCDE00
Selection of digital I/O or output current control function for CCD00 (P16) pin
0
Digital I/O (alternate function other than current control function)
1
Current control function
Caution 1. When a port pin is to be used with output current control, make the setting for the output current control function and then set the corresponding bit in the PMxx register for output mode.
Caution 2. The state of a pin takes 10 µs to become stable after 1 having been written to the corresponding bit of the CCDE register.
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4.3.13 Output current select registers (CCSx)
These registers are used to set the current control for the port pins selected for output current control in the output current control enable register (CCDE) or to place them in the high-impedance state. For current control, the pins are at the low level and produce output currents controlled to be 2 mA, 5 mA, 10 mA, or 15 mA. The CCSx registers can be set by an 8-bit memory manipulation instruction. The value of each CCSx register is 00H following a reset.
Figure 4 - 13 Format of Output Current Select Registers (CCSx)
Symbol 7
6
5
4
3
2
1
0
Address
After reset
R/W
CCS0 0
0
0
0
0 CCS02 CCS01 CCS00 F02A0H
00H
R/W
CCS4 0
0
0
0
0 CCS42 CCS41 CCS40 F02A4H
00H
R/W
CCS5 0
0
0
0
0 CCS52 CCS51 CCS50 F02A5H
00H
R/W
CCS6 0
0
0
0
0 CCS62 CCS61 CCS60 F02A6H
00H
R/W
CCS7 0
0
0
0
0 CCS72 CCS71 CCS70 F02A7H
00H
R/W
CCSn2
0 0 0 0 1
CCSn1
0 0 1 1 0
Others
CCSn0
0 1 0 1 0
n = 0 CCD00 to
CCD03
Hi-Z
2 mA
5 mA
10 mA
Setting prohibited
Setting prohibited
Setting for the Low-Level Output Current
n = 4 CCD04
n = 5 CCD05
n = 6 CCD06
Hi-Z 2 mA 5 mA 10 mA 15 mA
Hi-Z 2 mA 5 mA 10 mA 15 mA
Hi-Z 2 mA 5 mA 10 mA 15 mA
Setting prohibited
Setting prohibited
Setting prohibited
n = 7 CCD07
Hi-Z 2 mA 5 mA 10 mA 15 mA
Setting prohibited
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4.3.14 40-mA port output control register (PTDC)
This register is used to set the allowable output current to 40 mA when P70, P51, P17, P10, P101, P04, or P120 is an output at the low level. The pins among those stated above which can be set for 40-mA output depend on the product. Table 4 - 4 is a list by product of port pins which can be set for 40-mA output
Table 4 - 4 Products Having 40-mA Output Port Pins and the Pins Supporting 40-mA Output
Number of Pins
Product Names
Port Pins Supporting 40-mA Output
100
R7F100GPN, R7F100GPL, R7F100GPK
P04, P10, P101, P120
(products with 768, 512, or 384 Kbytes of flash memory)
80
R7F100GMN, R7F100GML, R7F100GMK
P04, P10, P120
(products with 768, 512, or 384 Kbytes of flash memory)
64
R7F100GLN, R7F100GLL, R7F100GLK
P04, P10, P120
(products with 768, 512, or 384 Kbytes of flash memory)
52
R7F100GJN, R7F100GJL, R7F100GJK, R7F100GJJ, R7F100GJH,
P17, P51, P70
R7F100GJG, R7F100GJF
48
R7F100GGN, R7F100GGL, R7F100GJK, R7F100GGJ, R7F100GGH,
P17, P51, P70
R7F100GGG, R7F100GGF
44
R7F100GFN, R7F100GFL, R7F100GFK, R7F100GFJ, R7F100GFH,
P17, P51, P70
R7F100GFG, R7F100GFF
40
R7F100GEJ, R7F100GEH, R7F100GEG, R7F100GEF
P17, P51, P70
36
R7F100GCJ, R7F100GCH, R7F100GCG, R7F100GCF
P17, P51, P70
32
R7F100GBJ, R7F100GBH, R7F100GBG, R7F100GBF
P17, P51, P70
30
R7F100GAJ, R7F100GAH, R7F100GAG, R7F100GAF
P17, P51
The PTDC register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
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Figure 4 - 14 Format of 40-mA Port Output Control Register (PTDC)
Address: F02A9H
After reset: 00H
R/W:
R/W
Symbol
7
PTDC
0
6 PTDC6
5 PTDC5
4 PTDC4
3 PTDC3
2 PTDC2
1 PTDC1
0 PTDC0
PTDC6 0 1
Allowable output current when a low level is output from P120 pinNote 1 IOL1 = 20.0 mA IOL1 = 40.0 mA
PTDC5 0 1
Allowable output current when a low level is output from P04 pinNote 1 IOL1 = 20.0 mA IOL1 = 40.0 mA
PTDC4 0 1
Allowable output current when a low level is output from P101 pinNote 2 IOL1 = 20.0 mA IOL1 = 40.0 mA
PTDC3 0 1
Allowable output current when a low level is output from P10 pinNote 1 IOL1 = 20.0 mA IOL1 = 40.0 mA
PTDC2 0 1
Allowable output current when a low level is output from P17 pinNote 3 IOL1 = 20.0 mA IOL1 = 40.0 mA
PTDC1 0 1
Allowable output current when a low level is output from P51 pinNote 3 IOL1 = 20.0 mA IOL1 = 40.0 mA
PTDC0 0 1
Allowable output current when a low level is output from P70 pinNote 4 IOL1 = 20.0 mA IOL1 = 40.0 mA
Note 1. Note 2. Note 3. Note 4.
Available in the 64-pin to 100-pin products with 384-Kbyte to 768-Kbyte code flash memory. Available in the 100-pin products with 384-Kbyte to 768-Kbyte code flash memory. Available in the 30-pin to 52-pin products. Available in the 32-pin to 52-pin products.
Caution The PTDC register is not implemented in the 128-pin products.
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4.3.15 Port function output enable registers (PFOEx)
This register is used to enable timer output, serial clock output, serial data output, and clock output for pins on which these functions are multiplexed. Disable the output when timer output, serial data output, and serial clock output are only to be input to the ELCL. The PFOEx registers can be set by a 1-bit or 8-bit memory manipulation instruction. The value of each PFOEx register is FFH following a reset.
Figure 4 - 15 Format of Port Function Output Enable Register 0 (PFOE0)
Address: F02AAH
After reset: FFH
R/W:
R/W
Symbol
7
PFOE0 PFOE07
6 PFOE06
5 PFOE05
4 PFOE04
3 PFOE03
2 PFOE02
1 PFOE01
0 PFOE00
PFOE0n 0
1
TO0n pin output enable (n = 0 to 7)
Timer output to the TO0n pin is disabled. The TO0n signal is only to be used for input to the ELCL and not for external output. The TO0n pin is available for use for a multiplexed function other than the port pin function.
Timer output to the TO0n pin is enabled. If the timer is not in use, the TO0n pin is available for use for a multiplexed function other than the port pin function.
Figure 4 - 16 Format of Port Function Output Enable Register 1 (PFOE1)
Address: F02ABH
After reset: FFH
R/W:
R/W
Symbol
7
PFOE1
1
6
5
4
3
2
1
0
1
PFOE15 PFOE14 PFOE13 PFOE12 PFOE11 PFOE10
PFOE15 0
1
CLKA0 pin output enable
Serial clock output to the CLKA0 pin is disabled. The CLKA0 signal is only to be used for input to the ELCL and not for external output. Set this bit to 0 when the CLKA0 pin is to be used for a multiplexed function other than the port pin function.
Serial clock output to the CLKA0 pin is enabled.
PFOE14 0
1
TxDA0 pin output enable
Serial data output to the TxDA0 pin is disabled. Set this bit to 0 when the TxDA0 signal is only to be used for input to the ELCL and not for external output.
Serial data output to the TxDA0 pin is enabled. Also set this bit to 1 if the TxDA0 pin is to be used for the port pin function.
PFOE13 0
1
SCK01 and SCL01 pins output enable
Serial clock output to the SCK01 and SCL01 pins is disabled. Set this bit to 0 when the SCK01 and SCL01 signals are only to be used for input to the ELCL and not for external output.
Serial clock output to the SCK01 and SCL01 pins is enabled. Also set this bit to 1 if the SCK01 and SCL01 pins are to be used for the port pin function.
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PFOE12 0
1
SCK00 and SCL00 pins output enable
Serial clock output to the SCK00 and SCL00 pins is disabled. Set this bit to 0 when the SCK00 and SCL00 signals are only to be used for input to the ELCL and not for external output.
Serial clock output to the SCK00 and SCL00 pins is enabled. Also set this bit to 1 if the SCK00 and SCL00 pins are to be used for the port pin function.
PFOE11 0
1
SO01 pin output enable
Serial data output to the SO01 pin is disabled. Set this bit to 0 when the SO01 signal is only to be used for input to the ELCL and not for external output.
Serial data output to the SO01 pin is enabled. Also set this bit to 1 if the SO01 pin is to be used for the port pin function.
PFOE10 0
1
SO00 and TxD0 pins output enable
Serial data output to the SO00 and TxD0 pins is disabled. Set this bit to 0 when the SO00 and TxD0 signals are only to be used for input to the ELCL and not for external output.
Serial data output to the SO00 and TxD0 pins is enabled. Also set this bit to 1 if the SO00 and TxD0 pins are to be used for the port pin function.
4.3.16 Port mode select register (PMS)
This register is used to specify whether the value in the output latch for a port is read or the output level on a port pin is read when the pin is in output mode (the PMmn bit of the port mode register (PMm) is 0). For details, see 27.3.11.1 Port mode select register (PMS).
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4.4
Port Function Operations
Port operations differ depending on whether the input or output mode is selected, as shown below.
4.4.1 Writing to I/O port
(1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared when a reset signal is generated.
(2) Input mode A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin state does not change. Therefore, byte data can be written to the ports used for both input and output. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared when a reset signal is generated.
4.4.2 Reading from I/O port
(1) Output mode The output latch contents are read by a transfer instruction. The output latch contents do not change.
(2) Input mode The pin state is read by a transfer instruction. The output latch contents do not change.
4.4.3 Operations on I/O port
(1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared when a reset signal is generated.
(2) Input mode The pin level is read and an operation is performed on the read value. The result of the operation is written to the output latch, but since the output buffer is off, the pin state does not change. Therefore, byte data can be written to the ports used for both input and output. The data of the output latch is cleared when a reset signal is generated.
4.4.4
Handling different potential (1.8 V, 2.5 V, or 3 V) by using EVDD VDD
When connecting an external device operating on a different potential (1.8 V, 2.5 V, or 3 V), it is possible to connect the I/O pins of general ports by changing EVDD to accord with the power supply of the connected device.
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4.4.5 Handling different potential (1.8 V, 2.5 V, or 3 V) by using I/O buffers
It is possible to connect an external device operating on a different potential (1.8 V, 2.5 V, or 3 V) by switching I/O buffers with the port input mode registers (PIMxx) and port output mode register (POMxx). When receiving input from an external device with a different potential (1.8 V, 2.5 V, or 3 V), set the port input mode registers 0, 1, 4, 5, 8, and 14 (PIM0, PIM1, PIM4, PIM5, PIM8, and PIM14) on a bit-by-bit basis to switch between normal input (CMOS) and TTL input buffer. When outputting data to an external device with a different potential (1.8 V, 2.5 V, or 3 V), set the port output mode registers 0, 1, 4, 5, 8, and 14 (POM0, POM1, POM4, POM5, POM8, and POM14) on a bit-by-bit basis to switch between normal output (CMOS) and N-ch open drain (VDD tolerance Note 1/EVDD tolerance Note 2). The connection of a serial interface is described in the following.
Note 1. Note 2.
For 30- to 52-pin products For 64- to 128-pin products
(1) Setting procedure when using input pins of UART0 to UART3, UARTA0, UARTA1, CSI00, CSI01, CSI10, CSI20, CSI30, and CSI31 functions in the TTL input buffer mode In case of UART0: P11 (P16) In case of UART1: P03 (P81) In case of UART2: P14 In case of UART3: P143 In case of UARTA0: P84 In case of UARTA1: P33 In case of CSI00: P10, P11 (P55, P16) In case of CSI01: P43, P44 In case of CSI10: P03, P04 (P81, P80) In case of CSI20: P14, P15 In case of CSI30: P142, P143 In case of CSI31: P53, P54
Remark
Functions can be assigned to the pins in parentheses via settings in the peripheral I/O redirection register
(PIOR).
<1> Using an external resistor, pull up externally the input pin to be used to the power supply of the target device (on-chip pull-up resistor cannot be used).
<2> Set the corresponding bit of the PIM0, PIM1, PIM3 to PIM5, PIM8, and PIM14 registers to 1 to switch to the TTL input buffer. For VIH and VIL, refer to the DC characteristics when the TTL input buffer is selected.
<3> Enable the operation of the serial array unit and set the mode to the UART/SPI (CSINote) mode.
<R> Note
Although the CSI function is generally called SPI, it is also called CSI in this product, so it is referred to as such in this manual.
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(2) Setting procedure when using output pins of UART0 to UART3, UARTA0, UARTA1, CSI00, CSI01, CSI10, CSI20, CSI30, and CSI31 functions in N-ch open-drain output mode In case of UART0: P12 (P17) In case of UART1: P02 (P82) In case of UART2: P13 In case of UART3: P144 In case of UARTA0: P83 In case of UARTA1: P34 In case of CSI00: P10, P12 (P55, P17) In case of CSI01: P43, P45 In case of CSI10: P02, P04 (P82, P80) In case of CSI20: P13, P15 In case of CSI30: P142, P144 In case of CSI31: P52, P54
Remark
Functions can be assigned to the pins in parentheses via settings in the peripheral I/O redirection register
(PIOR).
<1> Using an external resistor, pull up externally the output pin to be used to the power supply of the target device (on-chip pull-up resistor cannot be used).
<2> After reset release, the ports are in the input mode (Hi-Z). <3> Set the output latch of the corresponding port to 1. <4> Set the corresponding bit of the POM0, POM1, POM3 to POM5, POM8, and POM14 registers to 1 to set
the N-ch open drain output (VDD tolerance Note 1/EVDD tolerance Note 2) mode. <5> Enable the operation of the serial array unit and set the mode to the UART/SPI (CSI) mode. <6> Set the corresponding bit of the PM0, PM1, PM3 to PM5, PM8, and PM14 registers to the output mode.
At this time, the output data is high level, so the pin is in the Hi-Z state.
Note 1. Note 2.
For 30- to 52-pin products For 64- to 128-pin products
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(3) Setting procedure when using I/O pins of IIC00, IIC01, IIC10, IIC20, IIC30, and IIC31 functions with a different potential (1.8 V, 2.5 V, or 3 V) In case of IIC00: P10, P11 In case of IIC01: P43, P44 In case of IIC10: P03, P04 (P81, P80) In case of IIC20: P14, P15 In case of IIC30: P142, P143 In case of IIC31: P53, P54
Remark
Functions can be assigned to the pins in parentheses via settings in the peripheral I/O redirection register
(PIOR).
<1> Using an external resistor, pull up externally the input pin to be used to the power supply of the target device (on-chip pull-up resistor cannot be used).
<2> After reset release, the ports are in the input mode (Hi-Z). <3> Set the output latch of the corresponding port to 1. <4> Set the corresponding bit of the POM0, POM1, POM4, POM5, POM8, and POM14 registers to 1 to set
the N-ch open drain output (VDD tolerance Note 1/EVDD tolerance Note 2) mode. <5> Set the corresponding bit of the PIM0, PIM1, PIM4, PIM5, PIM8, and PIM14 registers to 1 to switch to
the TTL input buffer. For VIH and VIL, refer to the DC characteristics when the TTL input buffer is selected. <6> Enable the operation of the serial array unit and set the mode to the simplified I2C mode. <7> Set the corresponding bit of the PM0, PM1, PM4, PM5, PM8, and PM14 registers to the output mode (data I/O is possible in the output mode). At this time, the output data is high level, so the pin is in the HiZ state.
Note 1. Note 2.
For 30- to 52-pin products For 64- to 128-pin products
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4.5
Register Settings When Using Alternate Function
4.5.1 Basic concept when using alternate function
In the beginning, for a pin that is also assigned to the analog function, use the corresponding port mode control A register (PMCAxx) to specify whether to use the pin for the analog function or digital input/output. For a pin that is also assigned to the capacitance measurement function, use the corresponding port mode control T register (PMCTxx) to specify whether to use the pin for the capacitance measurement function or digital input/output. For a pin that is also assigned to the logic and event link controller output, use the corresponding port mode control E register (PMCEx) to specify whether to use the pin for the logic and even link controller function. Figure 4 - 17 shows the basic configuration of the output circuit for a pin used for digital input/output. The outputs from multiplexed SAU and UARTA functions (excluding the clock output from the UARTA) and the outputs from the output latches for the port-pin functions are input to an AND gate. The output of the AND gate is input to an OR gate. The outputs of multiplexed functions other than the SAU and UARTA (timer array unit, realtime clock, clock/buzzer output, IICA, etc.) are connected to other input pins of the OR gate. When such a pin is used for the port function or an alternate function, the unused alternate function must not hinder the output of the function to be used. A concept of basic settings for this case is shown in Table 4 - 5.
Figure 4 - 17 Basic Configuration of Output Circuit for a Pin
Internal bus
WRPORT
Output latch (Pmn)
WRPM
PM register (PMmn)
WRPOM
POM register (POMmn)
Note 1
Alternate function (SAU and UARTA)
Note 4
Note 2
Alternate function (other than SAU and
UARTA)Note 5
Note 3
VDD
P-ch N-ch VSS
Pmn/ Alternate function
To input circuit
Note 1. Note 2. Note 3. Note 4. Note 5.
When there is no POM register, this signal should be considered to be low level (0). When there is no alternate function, this signal should be considered to be high level (1). When there is no alternate function, this signal should be considered to be low level (0). This excludes the clock outputs from the UARTA. This includes the clock outputs from the UARTA.
Remark m: Port number (m = 0 to 15); n: Bit number (n = 0 to 7)
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Table 4 - 5 Concept of Basic Settings
Output Function of Used Pin
Output Settings of Unused Alternate Function
Port-pins Output Function
Output Functions of the SAU Output Functions other than those
and UARTANote 2
of the SAU and UARTANote 3
Port-pins output function
--
Output is high (1)
Output is low (0)
Output functions of the SAU and UARTANote 2
High (1)
Output is high (1)
Output is low (0)
Output functions other than those of the SAU and UARTANote 3
Low (0)
Don't care
Output is low (0)Note 1
Note 1.
Note 2. Note 3.
The output of the multiplexed functions which are not in use must be set to the low level (0) because two or more output functions other than the SAU and UARTA may be multiplexed on the same pin. The output of the multiplexed functions which are not in use must be set to the high level (1) because two or more output functions other than the SAU and UARTA may be multiplexed on the same pin. For details on the setting method, see 4.5.2 Register settings for alternate function whose output function is not used. This excludes the clock outputs from the UARTA. This includes the clock outputs from the UARTA.
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4.5.2 Register settings for alternate function whose output function is not used
When the output of an alternate function of the pin is not used, the following settings should be made. Note that when the peripheral I/O redirection function is applicable to an alternate function, the output can be switched to another pin by setting the peripheral I/O redirection register (PIOR). This allows usage of the port function or other alternate function assigned to the target pin.
(1) SOp = 1, TxDq = 1 (settings when the serial output (SOp/TxDq) of SAU is not used) When the serial output (SOp/TxDq) is not used, such as a case in which only the serial input of SAU is used, set the bit in serial output enable register m (SOEm) which corresponds to the unused output to 0 (output disabled) and set the SOmn bit in serial output register m (SOm) to 1 (high). When SOp and TxDq pins are to be used for the port pin functions, set the PFOE1x bits corresponding to the SOp, TxDq, and SCKp pins to 1. If a pin is to be used for a multiplexed function other than the port pin function, the corresponding PFOE1x bit can be set to 0. These are the same settings as the initial state.
(2) SCKp = 1, SDAr = 1, SCLr = 1 (settings when channel n in SAU is not used) When SAU is not used, set bit n (SEmn) in serial channel enable status register m (SEm) to 0 (operation stopped state), set the bit in serial output enable register m (SOEm) which corresponds to the unused output to 0 (output disabled), and set the SOmn and CKOmn bits in serial output register m (SOm) to 1 (high). When SCKp, SDAr, and SCLr pins are to be used for the port pin functions, set the PFOE1x bits corresponding to the SOp, TxDq, and SCKp pins to 1. If a pin is to be used for a multiplexed function other than the port pin function, the corresponding PFOE1x bit can be set to 0. These are the same settings as the initial state.
(3) TOmn = 0 (settings when the output of channel n in TAU is not used) When the TOmn output of TAU is not used, set the bit in timer output enable register 0 (TOE0) which corresponds to the unused output to 0 (output disabled) and set the corresponding bit in timer output register 0 (TO0) to 0 (low). These are the same settings as the initial state. Regardless of the selection for timer output operation, a TOmn output can also be stopped by setting the PFOE0x bit corresponding to the TOmn pin to 0.
(4) SDAAn = 0, SCLAn = 0 (setting when IICA is not used) When IICA is not used, set the IICEn bit in IICA control register n0 (IICCTLn0) to 0 (operation stopped). This is the same setting as the initial state.
(5) PCLBUZn = 0 (setting when clock/buzzer output is not used) When the clock/buzzer output is not used, set the PCLOEn bit in clock output select register n (CKSn) to 0 (output disabled). This is the same setting as the initial state.
(6) TxDAn = 1, CLKAn = 0 (settings when the UARTA is not used) When the UARTA is not used, set the UARTAENn, TXEAn, and RXEAn bits in operation mode setting register 0 (ASIMAn0) to 0 (operation disabled). When TxDAn and CLKAn pins are to be used for the port pin functions, set the PFOE1x bit corresponding to the TxDAn pin to 1. These are the same settings as the initial state. Output of the CLKA0 signal from the CLKA0 pin can also be stopped by setting the PFOE1x bit corresponding to CLKA0 to 0 regardless of the selection for UARTA operation.
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4.5.3 Register settings and port pin state
The correspondence between register settings and port pin state is shown in Table 4 - 6.
Table 4 - 6 Correspondence between Register Settings and Port Pin State
PMCAxx PMCTxx PMCEx
PMxx
Pxx
PUxx CCDE0x
1
X
X
X
X
X
X
0
1
X
X
X
X
X
0
0
1
0
X
X
X
0
0
X
1
X
1
X
0
0
X
1
X
0
X
0
0
0
0
1
X
X
0
0
0
0
0
X
1
0
0
0
0
0
X
1
0
0
0
0
0
X
0
CCSx X X X X X X
000 001 010 011 100
X
Pin State Analog input/output Capacitance measurement ELCL output Pulled up Hi-Z High-level port output Hi-Z Output current control port
Low-level port output
4.5.4 Examples of register settings for port and alternate functions
Examples of register settings for port and alternate functions are shown in Table 4 - 7 and Table 4 - 8. The registers used to control the port functions should be set as shown in Table 4 - 7 and Table 4 - 8. See the following remark for legends used in Table 4 - 7 and Table 4 - 8.
Remark --:
Not supported
×:
Don't care
PIOR:
Peripheral I/O redirection register
POMxx:
Port output mode registers
PMCAxx: Port mode control A registers
PMCTxx: Port mode control T registers
PMCEx:
Port mode control E registers
CCDE:
Output current control enable register
CCSx:
Output current select registers
PMxx:
Port mode registers
Pxx:
Port output latch
Functions in parentheses can be assigned via settings in the peripheral I/O redirection register (PIOR).
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Table 4 - 7 Examples of Register and Output Latch Settings for Alternate Functions (30-Pin to 64-Pin Products with 96Kbyte or 128-Kbyte Flash Memory) (1/17)
Pin Name PIOR POMxx
PMCAxx PMCTxx PMCEx
PMxx Pxx
Function Used
Function Name
I/O
P00 P00
Input
Alternate Function Output
SAU and
Other than
UARTA
SAU and 30- 32- 36- 40- 44- 48- 52- 64-
(excluding
UARTA
pin pin pin pin pin pin pin pin
clock output (including clock
from the output from the
UARTA)
UARTA)
-- × 0 ---- 1 ×
×
Note 1
--
Output
-- 0 0 -- -- 0 0/1 TxD1 = 1
--
Note 1
Note 2
N-ch open drain output
-- 1 0 -- -- 0 0/1
Note 1
ANI17
Analog input
-- × 1 ---- 1 ×
×
EI00
Input
-- × 0 ---- 1 ×
×
Note 1
--
------------
--
TI00
Input
-- × 0 ---- 1 ×
×
Note 1
--
TxD1
Output
-- 0/1 0 -- -- 0 1
×
Note 1
--
----
P01 P01
Input
----0--0 1 ×
--
Note 1
×
Output
-- -- 0 -- 0 0 0/1
--
Note 1
TO00 = 0
ANI16
Analog input
----1--0 1 ×
--
EI01
Input
----0--0 1 ×
--
Note 1
×
------------
×
EO01
Output
----0--1 0 ×
--
Note 1
--
TO00
Output
----0--0 0 0
--
Note 1
×
RxD1
Input
----0--0 1 ×
--
Note 1
×
----
P02 P02
ANI17 TxD1 SO10 P03 P03
ANI16 SI10 RxD1 SDA10
Input Output N-ch open drain output Analog input Output Output Input Output N-ch open drain output Analog input Input Input I/O
-- × 0 ---- 1 ×
×
-- 0 0 -- -- 0 0/1
TxD1/
SO10 = 1
-- 1 0 -- -- 0 0/1
Note 3
--×1 -- 0/1 0 -- 0/1 0 --×0 --00 --10
---- ---- ---- ---- ---- ----
1×
×
01
×
01
×
1×
×
0 0/1 SDA10 = 1
Note 3
0 0/1
-- × 1 ---- 1 ×
×
-- × 0 ---- 1 ×
×
-- × 0 ---- 1 ×
×
-- 1 0 ---- 0 1
×
--
------------
--
--
------------
--
------------
--
--------------
--
------------
--
--
------------
--
--------------
--
------------
--
--------------
Note 1. Note 2. Note 3.
This setting is only applicable in the 30- and 32-pin products. This setting is only applicable in the 30- to 48-pin products. This setting is only applicable in the 64-pin products.
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Table 4 - 7 Examples of Register and Output Latch Settings for Alternate Functions (30-Pin to 64-Pin Products with 96Kbyte or 128-Kbyte Flash Memory) (2/17)
Pin Name PIOR POMxx
PMCAxx PMCTxx PMCEx
PMxx Pxx
Function Used
Function Name
I/O
P04 P04
Input
Output
N-ch open drain output
Alternate Function Output
SAU and UARTA (excluding clock output from the UARTA)
Other than SAU and UARTA (including clock output from the UARTA)
30pin
32pin
36pin
40pin
44pin
48pin
52pin
64pin
--
× ------ 1 ×
×
--
--------------
--
0 -- -- -- 0 0/1 SCK10/
--
SCL10 = 1
--
1 -- -- -- 0 0/1
SCK10
SCL10 P05 P05
TS10 TI05 TO05 P06 P06
Input Output Output Input Output I/O Input Output Input Output
--
× ------
--
0/1 -- -- --
--
0/1 -- -- --
--
---- 0 --
--
---- 0 --
--
---- 1 --
PIOR0 = 0 -- -- 0 --
PIOR0 = 0 -- -- 0 --
--
---- 0 --
--
---- 0 --
1× 01 01 1× 0 0/1 1× 1× 00 1× 0 0/1
×
--
--------------
×
--
--------------
×
--
--------------
--
×
--------------
--
TO05 = 0
--
×
--------------
--
×
--------------
--
×
--------------
--
×
--------------
--
TO06 = 0
CLKA0 = 0
TS11 TI06 TO06 CLKA0
I/O Input Output Output
--
---- 1 -- 1 ×
PIOR0 = 0 -- -- 0 -- 1 ×
PIOR0 = 0 -- -- 0 -- 0 0
--
---- 0 -- 0 0
--
×
--------------
--
×
--------------
--
CLKA0 = 0 -- -- -- -- -- -- --
--
TO06 = 0 -- -- -- -- -- -- --
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Table 4 - 7 Examples of Register and Output Latch Settings for Alternate Functions (30-Pin to 64-Pin Products with 96Kbyte or 128-Kbyte Flash Memory) (3/17)
Function Used
Alternate Function Output
Pin Name PIOR POMxx
PMCAxx PMCEx CCDE CCSx PMxx
Pxx
Function Name
I/O
SAU and Other than
UARTA (excluding
clock
SAU and UARTA (including
30- 32- 36- 40- 44- 48- 52- 64pin pin pin pin pin pin pin pin
output from clock output
the
from the
UARTA) UARTA)
P10 P10
Input
--
Output
--
N-ch open
--
drain output
×
--
0
----
1
×
×
×
0
--
0
----
0 0/1 SCK00/ (TO07) = 0
SCL00 = 1
1
--
0
----
0 0/1
EI10 EO10 SCK00
SCL00
Input Output Input Output Output
--
×
--
0
----
1
×
--
0/1 --
1
----
0
×
PIOR1 = 0 ×
--
0
----
1
×
PIOR1 = 0 0/1 --
0
----
0
1
PIOR1 = 0 0/1 --
0
----
0
1
×
×
×
×
×
×
×
(TO07) = 0
×
(TO07) = 0
(TI07) Input
PIOR0 = 1 ×
--
0
----
1
×
×
×
(TO07) Output
PIOR0 = 1 0
--
0
----
0
0
×
×
P11 P11
Input
--
×
--
0
----
1
×
×
×
Output
--
N-ch open
--
drain output
0
--
0
----
0 0/1 SDA00 = 1 (TO06) = 0
1
--
0
----
0 0/1
EI11 EO11
Input Output
--
×
--
0
----
1
×
×
--
0/1 --
1
----
0
×
×
×
×
SI00
Input
PIOR1 = 0 ×
--
0
----
1
×
×
×
RxD0
Input
PIOR1 = 0 ×
--
0
----
1
×
×
×
SDA00 I/O
PIOR1 = 0 1
--
0
----
0
1
×
(TO06) = 0
(TI06) Input
PIOR0 = 1 ×
--
0
----
1
×
×
×
(TO06) Output
PIOR0 = 1 0
--
0
----
0
0
×
×
P12 P12
Input
--
×
--
0
----
1
×
×
×
Output
--
N-ch open
--
drain output
0
--
0
----
0 0/1 SO00/ (TO05) = 0
TxD0 = 1
1
--
0
----
0 0/1
EI12 EO12 SO00 TxD0 (INTP5) (TI05)
Input Output Output Output Input Input
--
×
--
0
----
1
×
--
0/1 --
1
----
0
×
PIOR1 = 0 0/1 --
0
----
0
1
PIOR1 = 0 0/1 --
0
----
0
1
PIOR4 = 1 ×
--
0
----
1
×
PIOR0 = 1 ×
--
0
----
1
×
×
×
×
×
×
(TO05) = 0
×
(TO05) = 0
×
×
--------------
×
×
(TO05) Output
PIOR0 = 1 0
--
0
----
0
0
×
×
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Table 4 - 7 Examples of Register and Output Latch Settings for Alternate Functions (30-Pin to 64-Pin Products with 96Kbyte or 128-Kbyte Flash Memory) (4/17)
Pin Name PIOR POMxx
PMCAxx PMCEx CCDE CCSx PMxx
Pxx
Function Used
Function Name
I/O
P13 P13
Input
--
Output
--
N-ch open
--
drain output
Alternate Function Output
SAU and UARTA (excluding clock output from the UARTA)
Other than SAU and UARTA
(including clock output from the
UARTA)
30- 32- 36- 40- 44- 48- 52- 64pin pin pin pin pin pin pin pin
× 0 0 ---- 1 ×
×
×
0 0 0 -- -- 0 0/1
TxD2/
SO20 = 1 1 0 0 -- -- 0 0/1
(TO04) = 0 (SDAA0) = 0
EO13
Output
--
0/1 0 1 -- -- 0 ×
×
×
TxD2
Output
PIOR1 = 0 0/1 0 0 -- -- 0 1
×
(TO04) = 0
(SDAA0) = 0
SO20
Output
PIOR1 = 0 0/1 0 0 -- -- 0 1
×
(TO04)= 0 (SDAA0)= 0
(SDAA0) I/O
PIOR2 = 1 1 0 0 -- -- 0 0
×
(TO04) = 0
(TI04)
Input
PIOR0 = 1 × 0 0 -- -- 1 ×
×
×
(TO04) Output
PIOR0 = 1 0 0 0 -- -- 0 0
×
(SDAA0) = 0
IVREF0 Analog input
--
× 1 0 ---- 1 ×
×
×
P14 P14
Input
--
× -- 0 ---- 1 ×
×
×
Output
--
N-ch open
--
drain output
0 -- 0 -- -- 0 0/1 SDA20 = 1 VCOUT1 = 0
1 -- 0 -- -- 0 0/1
(TO03) = 0 (SCLA0) = 0
EO14
Output
VCOUT1 Output
--
0/1 -- 1 -- -- 0 ×
×
×
--
0 -- 0 ---- 0 0
×
(TO03) = 0
(SCLA0) = 0
RxD2
Input
PIOR1 = 0 × -- 0 -- -- 1 ×
×
×
SI20
Input
PIOR1 = 0 × -- 0 -- -- 1 ×
×
×
SDA20 I/O
PIOR1 = 0 1 -- 0 -- -- 0 1
×
VCOUT1 = 0
(TO03) = 0
(SCLA0) = 0
(SCLA0) I/O
PIOR2 = 1 1 -- 0 -- -- 0 0
×
VCOUT1 = 0
(TO03) = 0
(TI03)
Input
PIOR0 = 1 × -- 0 -- -- 1 ×
×
×
(TO03) Output
PIOR0 = 1 0 -- 0 -- -- 0 0
×
VCOUT1 = 0
(SCLA0) = 0
P15 P15
Input
--
× -- 0 ---- 1 ×
×
×
Output
--
N-ch open
--
drain output
0 -- 0 -- -- 0 0/1
SCK20/ PCLBUZ1 = 0Note
SCL20 = 1 1 -- 0 -- -- 0 0/1
(TO02) = 0
EO15
Output
PCLBUZ1 Output
SCK20 Input
Output
SCL20 Output
(TI02) (TO02)
Input Output
--
0/1 -- 1 -- -- 0 ×
--
0 -- 0 ---- 0 0
PIOR1 = 0 × -- 0 -- -- 1 ×
PIOR1 = 0 0/1 -- 0 -- -- 0 1
PIOR1 = 0 0/1 -- 0 -- -- 0 1
PIOR0 = 1 × -- 0 -- -- 1 × PIOR0 = 1 0 -- 0 -- -- 0 0
×
×
×
(TO02) = 0 --
×
×
×
PCLBUZ1 = 0Note
(TO02) = 0
×
PCLBUZ1 = 0Note
(TO02) = 0
×
×
×
PCLBUZ1 = 0Note
Note
This setting is only applicable in the 30- to 52-pin products.
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<R>
Table 4 - 7 Examples of Register and Output Latch Settings for Alternate Functions (30-Pin to 64-Pin Products with 96Kbyte or 128-Kbyte Flash Memory) (5/17)
Pin Name PIOR POMxx
PMCAxx PMCEx CCDE CCSx PMxx
Pxx
Function Used
Function Name
I/O
P16 P16
Input
Output
CCD00 Output
EO16 TI01 TO01 INTP5
Output Input Output Input
Alternate Function Output
SAU and UARTA (excluding clock output from the UARTA)
Other than SAU and UARTA (including clock output from the UARTA)
30- 32- 36- 40- 44- 48- 52- 64pin pin pin pin pin pin pin pin
--
-- -- 0 CCDE00 = 0 CCS0x = xxx 1 ×
×
×
--
-- -- 0 CCDE00 = 0 CCS0x = xxx 0 0/1
×
TO01 = 0
--
-- -- 0 CCDE00 = 1 CCS0x = 0 0
×
TO01 = 0
001 to 011
--
-- -- 1 CCDE00 = 0 CCS0x = xxx 0 ×
×
×
--
-- -- 0 CCDE00 = 0 CCS0x = xxx 1 ×
×
×
--
-- -- 0 CCDE00 = 0 CCS0x = xxx 0 0
×
×
PIOR4 = 0 -- -- 0 CCDE00 = 0 CCS0x = xxx 1 ×
×
Note
×
(SI00) Input
PIOR1 = 1 -- --
(RxD0) Input
PIOR1 = 1 -- --
P17 P17
Input
--
×--
Output
--
0--
N-ch open
--
drain output
1--
CCD01 Output
--
0/1 --
EO17 Output TI02 Input TO02 Output (TxD0) Output (SO00) Output
--
0/1 --
PIOR0 = 0 × --
PIOR0 = 0 0 --
PIOR1 = 1 0/1 --
PIOR1 = 1 0/1 --
0 CCDE00 = 0 CCS0x = xxx 1 0 CCDE00 = 0 CCS0x = xxx 1 0 CCDE01 = 0 CCS0x = xxx 1 0 CCDE01 = 0 CCS0x = xxx 0 0 CCDE01 = 0 CCS0x = xxx 0
×
×
×
×
×
×
0/1 (TxD0) = 1
(SO00) = 1
0/1
Note
× × × TO02 = 0
--------------
0 CCDE01 = 1 CCS0x = 0 0
×
TO02 = 0
001 to 011
1 CCDE01 = 0 CCS0x = xxx 0 ×
×
×
0 CCDE01 = 0 CCS0x = xxx 1 ×
×
×
0 CCDE01 = 0 CCS0x = xxx 0 0
×
×
0 CCDE01 = 0 CCS0x = xxx 0 1
×
TO02 = 0
0 CCDE01 = 0 CCS0x = xxx 0 1
×
TO02 = 0 -- -- -- -- -- -- --
Note
This setting is only applicable in the 64-pin products.
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Table 4 - 7 Examples of Register and Output Latch Settings for Alternate Functions (30-Pin to 64-Pin Products with 96Kbyte or 128-Kbyte Flash Memory) (6/17)
Pin Name
Function Used
Function Name
I/O
PMCAxx
PMxx
Pxx
30-pin 32-pin 36-pin 40-pin 44-pin 48-pin 52-pin 64-pin
P20 P20
Input
0
1
×
Output
0
0
0/1
ANI0
Analog input
1
1
×
AVREFP Reference
1
1
×
voltage
EI20
Input
0
1
×
P21 P21
Input Output
0
1
×
0
0
0/1
ANI1
Analog input
1
1
×
AVREFM Reference
1
1
×
voltage
EI21 P22 P22
Input Input
0
1
×
0
1
×
Output
0
0
0/1
ANI2
Analog input
1
1
×
ANO0
Analog output
1
1
×
EI22
Input
0
1
×
P23 P23
Input
0
1
×
Output
0
0
0/1
ANI3
Analog input
1
1
×
ANO1
Analog output
1
1
×
IVREF0 Analog input
1
1
×
EI23 P24 P24
Input Input
0
1
×
0
1
×
--
--
Output
0
ANI4
Analog input
1
0
0/1
1
×
--
--
P25 P25
Input Output
0
1
×
--
--
0
0
0/1
ANI5
Analog input
1
1
×
--
--
P26 P26
Input
0
1
×
--
--
--
Output
0
0
0/1
ANI6
Analog input
1
1
×
--
--
--
P27 P27
Input
0
1
×
--
--
--
--
Output
0
ANI7
Analog input
1
0
0/1
1
×
--
--
--
--
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Table 4 - 7 Examples of Register and Output Latch Settings for Alternate Functions (30-Pin to 64-Pin Products with 96Kbyte or 128-Kbyte Flash Memory) (7/17)
Function Used
Pin Name
Function Name
I/O
P30 P30
Input Output
TSCAP EI30 VCOUT0 INTP3 RTC1HZ SCK11
I/O Input Output Input Output Input Output
SCL11
Output
P31 P31
Input Output
TS01 EI31 TI03 TO03
I/O Input Input Output
INTP4
Input
PCLBUZ0 Output
(PCLBUZ0) Output
PIOR PMCTxx PMxx
--
0
1
--
0
0
--
1
1
--
0
1
--
0
0
--
0
1
--
0
0
--
0
1
--
0
0
--
0
0
--
0
1
--
0
0
--
1
1
--
0
1
PIOR0 = 0
0
1
PIOR0 = 0
0
0
--
0
1
--
0
0
PIOR3 = 1
0
0
Alternate Function Output
Pxx
SAU and UARTA Other than SAU and 30- 32- 36- 40- 44- 48- 52- 64-
(excluding clock
UARTA (including pin pin pin pin pin pin pin pin
output from the clock output from the
UARTA)
UARTA)
×
×
×
0/1 SCK11/SCL11 = 1
VCOUT0 = 0 RTC1HZ = 0
×
×
×
×
×
×
0
×
RTC1HZ = 0
×
×
×
0
×
VCOUT0 = 0
×
×
×
1
×
VCOUT0 = 0
RTC1HZ = 0
1
×
VCOUT0 = 0
RTC1HZ = 0
×
--
×
0/1
--
TO03 = 0
PLCBUZ0 = 0Note 1
(PCLBUZ0) = 0Note 2
×
×
×
×
--
×
×
--
×
0
--
PLCBUZ0 = 0Note 1
(PCLBUZ0) = 0Note 2
×
--
×
0
--
TO03 = 0
------
0
--
TO03 = 0
----------
Note 1. Note 2.
This setting is only applicable in the 30- to 44-pin products. This setting is only applicable in the 48- to 64-pin products.
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Table 4 - 7 Examples of Register and Output Latch Settings for Alternate Functions (30-Pin to 64-Pin Products with 96Kbyte or 128-Kbyte Flash Memory) (8/17)
Pin Name
Function Used
Function Name
I/O
PIOR
POMxx PMxx
Alternate Function Output
Pxx
SAU and UARTA Other than SAU and 30- 32- 36- 40- 44- 48- 52- 64(excluding clock UARTA (including pin pin pin pin pin pin pin pin
output from the clock output from
UARTA)
the UARTA)
P40 P40
Input
--
--
1
×
--
Output
--
--
0
0/1
--
P41 P41
Input
--
--
1
×
--
Output
--
--
0
0/1
--
RxDA1 Input
--
--
1
×
--
TI07
Input
PIOR0 = 0 --
1
×
--
TO07
Output
PIOR0 = 0 --
0
0
--
P42 P42
Input
--
×
1
×
×
Output
--
0
0
0/1
TxDA1 = 1
N-ch open
--
drain output
1
0
0/1
-- -- × TO07 = 0 × × × × TO04 = 0
--------
-------- -------- -------- -------------- -------------- --------------
TxDA1
Output
--
0/1
0
1
×
TI04
Input
PIOR0 = 0
×
1
×
×
TO04
Output
PIOR0 = 0
0
0
0
×
P43 P43
Input
--
--
1
×
--
Output
--
--
0
0/1
--
CLKA1 Output
--
--
0
0
--
TO04 = 0 × × ×
CLKA1 = 0 ×
-------------- -------------- -------------- -------------- -------------- --------------
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CHAPTER 4 PORT FUNCTIONS
<R>
Table 4 - 7 Examples of Register and Output Latch Settings for Alternate Functions (30-Pin to 64-Pin Products with 96Kbyte or 128-Kbyte Flash Memory) (9/17)
Pin Name PIOR POMxx
PMCTxx PMCEx CCDE CCSx PMxx
Pxx
Function Used
Function Name
I/O
P50 P50
Input
--
×
0
Output
--
0
0
N-ch open
--
1
0
drain output
TS00 I/O
--
×
1
EI50 Input
--
×
0
EO50 Output
-- 0/1 0
CCD03 Output
-- 0/1 0
INTP1 Input
SI11
Input
SDA11 I/O
P51 P51
Input
Output
EI51 Input
EO51 Output
CCD02 Output
--
×
0
--
×
0
--
1
0
-- ----
-- ----
-- ----
-- ----
-- ----
INTP2 Input
SO11 Output
P52 P52
Input
Output
(INTP10) Input
-- ---- -- ---- -- ---- -- ---- PIOR1 -- -- = 1
0 CCDE03 = 0 CCS0x = xxx 1 0 CCDE03 = 0 CCS0x = xxx 0 0 CCDE03 = 0 CCS0x = xxx 0
0 CCDE03 = 0 CCS0x = xxx 1
0 CCDE03 = 0 CCS0x = xxx 1
1 CCDE03 = 0 CCS0x = xxx 0
0 CCDE03 = 1 CCS0x =
0
001 to 011
0 CCDE03 = 0 CCS0x = xxx 1
0 CCDE03 = 0 CCS0x = xxx 1
0 CCDE03 = 0 CCS0x = xxx 0
0 CCDE02 = 0 CCS0x = xxx 1
0 CCDE02 = 0 CCS0x = xxx 0
0 CCDE02 = 0 CCS0x = xxx 1
1 CCDE02 = 0 CCS0x = xxx 0
0 CCDE02 = 1 CCS0x =
0
001 to 011
0 CCDE02 = 0 CCS0x = xxx 1
0 CCDE02 = 0 CCS0x = xxx 0
--
--
--
1
--
--
--
0
--
--
--
1
Alternate Function Output
SAU and UARTA (excluding
clock output from the UARTA)
Other than SAU and UARTA (including clock output from the UARTA)
30pin
32pin
36pin
40pin
44pin
48pin
52pin
64pin
×
×
--
0/1 SDA11 = 1
--
0/1
×
×
×
×
×
×
0
×
--
--
--
--
×
×
--
×
×
--
1
×
--
×
×
--
0/1 SO11 = 1
--
×
×
--
×
×
--
0
×
--
×
×
1
×
×
--
0/1
--
×
--
--
--
--
--------------
--
--
--------------
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CHAPTER 4 PORT FUNCTIONS
Table 4 - 7 Examples of Register and Output Latch Settings for Alternate Functions (30-Pin to 64-Pin Products with 96Kbyte or 128-Kbyte Flash Memory) (10/17)
Pin Name PIOR POMxx
PMCTxx PMCEx CCDE CCSx PMxx
Pxx
Function Used
Function Name
I/O
P53 P53
Input
--
----------
Output
--
----------
(INTP11) Input
PIOR1 = 1 -- -- -- -- --
P54 P54
Input
--
----------
Output
--
----------
P55 P55
Input
--
× --------
Output
--
0 --------
N-ch open
--
drain output
1 --------
(PCLBUZ1) Output
PIOR4 = 1 0 -- -- -- --
(SCK00) Input
PIOR1 = 1 × -- -- -- --
Output
PIOR1 = 1 0/1 -- -- -- --
Alternate Function Output
SAU and UARTA (excluding clock output from the UARTA)
Other than SAU and UARTA
(including clock output from the
UARTA)
30- 32- 36- 40- 44- 48- 52- 64pin pin pin pin pin pin pin pin
1×
--
--
--------------
0 0/1
--
--
1×
--
--
--------------
1×
--
--
--------------
0 0/1
--
--
1×
×
×
--------------
0 0/1 (SCK00) = 1 (PCLBUZ1) = 0
0 0/1
00 1× 01
×
×
--------------
×
×
--------------
×
(PCLBUZ1) = 0 -- -- -- -- -- -- --
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CHAPTER 4 PORT FUNCTIONS
Table 4 - 7 Examples of Register and Output Latch Settings for Alternate Functions (30-Pin to 64-Pin Products with 96Kbyte or 128-Kbyte Flash Memory) (11/17)
Pin Name PIOR PMCEx CCDE CCSx PMxx Pxx
Function Used
Function Name
I/O
P60 P60
Input
--
0
CCDE04 = 0 CCS4x = 000
1
N-ch open
--
drain output
(6-V tolerance)
0
CCDE04 = 0 CCS4x = 000
0
EO60
Output
--
1
CCDE04 = 0 CCS4x = 000
0
CCD04 Output
--
0
CCDE04 = 1 CCS4x =
0
001 to 100
SCLA0 I/O
PIOR2 = 0 0
CCDE04 = 0 CCS4x = 000
0
P61 P61
Input
--
0
CCDE05 = 0 CCS5x = 000
1
N-ch open
--
drain output
(6-V tolerance)
0
CCDE05 = 0 CCS5x = 000
0
EO61
Output
--
1
CCDE05 = 0 CCS5x = 000
0
CCD05 Output
--
0
CCDE05 = 1 CCS5x =
0
001 to 100
SDAA0 I/O
PIOR2 = 0 0
CCDE05 = 0 CCS5x = 000
0
P62 P62
Input
--
--
CCDE06 = 0 CCS6x = 000
1
N-ch open
--
drain output
(6-V tolerance)
--
CCDE06 = 0 CCS6x = 000
0
CCD06 Output
--
--
CCDE06 = 1
CCS6x =
0
001 to 100
SCLA1 I/O
--
--
CCDE06 = 0 CCS6x = 000
0
P63 P63
Input
--
--
CCDE07 = 0 CCS7x = 000
1
N-ch open
--
drain output
(6-V tolerance)
--
CCDE07 = 0 CCS7x = 000
0
CCD07 Output
--
--
CCDE07 = 1
CCS7x =
0
001 to 100
SDAA1 I/O
--
--
CCDE07 = 0 CCS7x = 000
0
Alternate Function Output
SAU and UARTA (excluding clock output from the UARTA)
Other than SAU and UARTA
(including clock output from the
UARTA)
30pin
32pin
36pin
40pin
44pin
48pin
52pin
64pin
×
--
×
0/1
--
SCLA0 = 0
×
--
0
--
0
--
×
--
0/1
--
× SCLA0 = 0
× × SDAA0 = 0
×
--
×
0
--
SDAA0 = 0
0
--
×
×
--
×
--
0/1
--
SCLA1 = 0Note
0
--
SCLA1 = 0Note --
0
--
×
--------
×
--
×
--------
0/1
--
SDAA1 = 0Note
0
--
SDAA1 = 0Note -- -- -- --
0
--
×
--------
Note
This setting is only applicable in the 44- to 64-pin products.
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RL78/G23
CHAPTER 4 PORT FUNCTIONS
Table 4 - 7 Examples of Register and Output Latch Settings for Alternate Functions (30-Pin to 64-Pin Products with 96Kbyte or 128-Kbyte Flash Memory) (12/17)
Pin Name PIOR POMxx
PMCTxx PMxx Pxx
Function Used
Function Name
I/O
P70 P70
Input Output
----
0
----
0
Alternate Function Output
SAU and UARTA (excluding clock output from the
UARTA)
Other than SAU and UARTA 30-
(including clock pin
output from the
UARTA)
32pin
36pin
40pin
44pin
48pin
52pin
64pin
1
×
×
--
--
0 0/1 SCK21/SCL21 = 1
--
Note 1
TS02 RIN0 KR0 SCK21
SCL21 P71 P71
TS03 KR1 SI21 SDA21 RxDA0 P72 P72
TS04 KR2 SO21 TxDA0 P73 P73
TS05 KR3 SO01
I/O Input Input Input Output Output Input Output N-ch open drain output I/O Input Input I/O Input Input Output N-ch open drain output I/O Input Output Output Input Output I/O Input Output
----
1
----
0
----
0
----
0
----
0
----
0
--
×
0
--
0
0
--
1
0
--
×
1
--
×
0
--
×
0
--
1
0
--
×
0
--
×
0
--
0
0
--
1
0
--
×
1
--
×
0
-- 0/1 0
-- 0/1 0
----
0
----
0
----
1
----
0
----
0
1
×
1
×
1
×
1
×
0
1
0
1
1
×
0 0/1
0 0/1
× × × × × × × SDA21 = 1
1
×
1
×
1
×
0
1
1
×
1
×
0 0/1
0 0/1
× × × × × × SO21 = 1 TxDA0 = 1
1
×
×
1
×
×
0
1
TxDA0 = 1
0
1
SO21 = 1
1
×
×
0
0/1
SO01 = 1Note 2
1
×
×
1
×
×
0
1
×
--
--
--
--
--
------
--
----
--
----
--
----
--
----
--
--
----
--
------
--
----
--
----
--
----
--
----
--
--
----
--
------
--
----
--
----
--
------
--
--
------
--
------
--
----------
Note 1. Note 2.
This setting is only applicable in the 36- to 64-pin products. This setting is only applicable in the 48- to 64-pin products.
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CHAPTER 4 PORT FUNCTIONS
Table 4 - 7 Examples of Register and Output Latch Settings for Alternate Functions (30-Pin to 64-Pin Products with 96Kbyte or 128-Kbyte Flash Memory) (13/17)
Function Used
Alternate Function Output
Pin Name PIOR POMxx
PMCTxx PMxx Pxx
Function Name
I/O
SAU and UARTA (excluding clock output from the
UARTA)
Other than SAU and UARTA (including clock output from the UARTA)
30- 32pin pin
36- 40pin pin
44- 48pin pin
52- 64pin pin
P74 P74
Input
--
×
0
1
×
×
--
----------
Output
--
0
0
0 0/1
SDA01 = 1
--
N-ch open
--
drain output
1
0
0 0/1
TS06
I/O
--
×
1
1
×
×
--
----------
KR4
Input
--
×
0
1
×
×
--
----------
INTP8
Input
--
×
0
1
×
×
--
----------
SI01
Input
--
×
0
1
×
×
--
----------
SDA01
I/O
--
1
0
0
1
×
--
----------
P75 P75
Input
--
--
0
1
×
×
--
----------
Output
--
--
0
0 0/1 SCK01/SCL01 = 1
--
TS07
I/O
--
--
1
1
×
×
--
----------
KR5
Input
--
--
0
1
×
×
--
----------
INTP9
Input
--
--
0
1
×
×
--
----------
SCK01
Input
--
--
0
1
×
×
--
----------
Output
--
--
0
0
1
×
--
----------
SCL01
Output
--
--
0
0
1
×
--
----------
P76 P76
Input
--
--
0
1
×
--
--
------------
Output
--
--
0
0 0/1
--
--
TS08
I/O
--
--
1
1
×
--
--
------------
KR6
Input
--
--
0
1
×
--
--
------------
INTP10
Input
PIOR1 = 0 --
0
1
×
--
--
------------
(RxD2)
Input
PIOR1 = 1 --
0
1
×
--
--
------------
P77 P77
Input
--
--
0
1
×
×
--
------------
Output
--
--
0
0 0/1
(TxD2) = 1
--
TS09
I/O
--
--
1
1
×
×
--
------------
KR7
Input
--
--
0
1
×
×
--
------------
INTP11
Input
PIOR1 = 0 --
0
1
×
×
--
------------
(TxD2)
Output
PIOR1 = 1 --
0
0
1
×
--
------------
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CHAPTER 4 PORT FUNCTIONS
Table 4 - 7 Examples of Register and Output Latch Settings for Alternate Functions (30-Pin to 64-Pin Products with 96Kbyte or 128-Kbyte Flash Memory) (14/17)
Pin Name POMxx PMCAxx PMxx Pxx
Function Used
Function Name
I/O
Alternate Function Output
SAU and UARTA (excluding clock output from the UARTA)
Other than SAU and UARTA (including clock output from the UARTA)
30pin
32pin
36pin
40pin
44pin
48pin
52pin
64pin
P120 P120
Input
×
0
1
×
×
--
Output
0
0
0
0/1 TxDA1 = 1
--
N-ch open
1
0
0
0/1
drain output
ANI19
Analog input
×
1
1
×
×
--
IVCMP1 Analog input
×
1
1
×
×
--
EI120
Input
×
0
1
×
×
--
TxDA1
Output
0/1
0
0
1
×
--
-------- --
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CHAPTER 4 PORT FUNCTIONS
Table 4 - 7 Examples of Register and Output Latch Settings for Alternate Functions (30-Pin to 64-Pin Products with 96Kbyte or 128-Kbyte Flash Memory) (15/17)
Pin Name
Function Used
Function Name
I/O
CMC
EXCLK, OSCSEL, EXCLKS, OSCSELS
PMxx XTSEL
Pxx
30- 32- 36- 40- 44- 48- 52- 64pin pin pin pin pin pin pin pin
P121 P121
Input
00 xx / 10 xx / 11 xx
0
1
×
xx 00 / xx 10 / xx 11
1Note
Output
00 xx / 10 xx / 11 xx
0
0
0/1
xx 00 / xx 10 / xx 11
1Note
EI121
Input
00 xx / 10 xx / 11 xx
0
1
×
xx 00 / xx 10 / xx 11
1Note
VBAT
Input
00 xx / 10 xx / 11 xx
0
0
1
------
X1
--
01 xx
0
1
×
XT1
--
xx 01
1
1
×
----------
P122 P122
Input
00 xx / 10 xx
0
1
×
xx 00 / xx 10
1Note
Output
00 xx / 10 xx
0
0
0/1
xx 00 / xx 10
1Note
EI122
Input
00 xx / 10 xx
0
1
×
xx 00 / xx 10
1Note
X2
--
01 xx
0
1
×
XT2
--
xx 01
1
1
×
----------
EXCLK Input
11 xx
0
1
×
EXCLKS Input
xx 11
1
1
×
----------
P123 P123
Input
xx 00 / xx 10 / xx11
0
--
×
------
XT1
--
xx 01
0
--
×
------
P124 P124
Input
xx 00 / xx 10
0
--
×
------
XT2
--
xx 01
0
--
×
------
EXCLKS Input
xx 11
0
--
×
------
Note
This setting is only applicable in the 30- to 36-pin products.
Table 4 - 7 Examples of Register and Output Latch Settings for Alternate Functions (30-Pin to 64-Pin Products with 96Kbyte or 128-Kbyte Flash Memory) (16/17)
Pin Name
Function Used
Function Name
I/O
PMxx
Pxx
30-pin 32-pin 36-pin 40-pin 44-pin 48-pin 52-pin 64-pin
P130 P130
Output
--
0/1
--
--
--
--
--
P137 P137
Input
--
×
EI137
Input
--
×
INTP0
Input
--
×
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RL78/G23
CHAPTER 4 PORT FUNCTIONS
Table 4 - 7 Examples of Register and Output Latch Settings for Alternate Functions (30-Pin to 64-Pin Products with 96Kbyte or 128-Kbyte Flash Memory) (17/17)
Pin Name PIOR POMxx
PMCAxx PMxx Pxx
Function Used
Function Name
I/O
Alternate Function Output
SAU and UARTA (excluding clock output from the UARTA)
Other than SAU and UARTA (including clock output from the UARTA)
30- 32- 36- 40- 44- 48- 52- 64pin pin pin pin pin pin pin pin
P140 P140
Input
--
----
1
×
--
×
----------
Output
--
----
0
0/1
--
PCLBUZ0 = 0
PCLBUZ0 Output
PIOR3 = 0 -- --
0
0
--
×
----------
INTP6
Input
--
----
1
×
--
×
----------
P141 P141
Input
--
----
1
×
--
×
--------------
Output
--
----
0
0/1
--
PCLBUZ1 = 0
PCLBUZ1 Output
PIOR4 = 0 -- --
0
0
--
×
--------------
INTP7
Input
--
----
1
×
--
×
--------------
P146 P146
Input
--
----
1
×
--
--
--------
Output
--
----
0
0/1
--
--
P147 P147
Input
--
--
0
1
×
--
--
Output
--
--
0
0 0/1
--
--
ANI18
Analog input
--
--
1
1
×
--
--
IVCMP0 Analog input
--
--
1
1
×
--
--
EI147
Input
--
--
0
1
×
--
--
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RL78/G23
CHAPTER 4 PORT FUNCTIONS
Table 4 - 8 Examples of Register and Output Latch Settings for Alternate Functions (Products with 192-Kbyte to 768Kbyte Flash Memory and 80-Pin and 100-Pin Products with 128-Kbyte Flash Memory) (1/21)
Pin Name PIOR POMxx
PMCAxx PMCTxx PMCEx
PMxx Pxx 30-pin 32-pin 36-pin 40-pin 44-pin 48-pin 52-pin 64-pin 80-pin 100-pin 128-pin
Function Used
Function Name
I/O
Alternate Function Output
SAU and UARTA (excluding clock output from the UARTA)
Other than SAU and UARTA (including clock output from the UARTA)
P00 P00
Input
--
× 0Note 1 0
--
1
×
×
--
Output
--
0 0Note 1 0
--
0 0/1 TxD1 = 1
--
Note 2
N-ch open
--
1 0Note 1 0
--
0 0/1
drain output
ANI17 Analog input
--
×
1
0--
1
×
×
--
------------------
TS26 I/O
--
× 0Note 1 1
--
1
×
×
--
EI00 Input
--
× 0Note 1 0
--
1
×
×
--
TI00 Input
--
× 0Note 1 0
--
1
×
×
--
TxD1 Output
--
0/1 0Note 1 0
--
0
1
×
--
----------
P01 P01
Input
--
-- 0Note 1 0
0
1
×
--
×
Output
--
-- 0Note 1 0
0
0 0/1
--
TO00 = 0
ANI16 Analog input
--
--
1
0
0
1
×
--
×
------------------
TS27 I/O
--
-- 0Note 1 1
0
1
×
--
×
EI01 Input
--
-- 0Note 1 0
0
1
×
--
×
EO01 Output
--
-- 0Note 1 0
1
0
×
--
×
TO00 Output
--
-- 0Note 1 0
0
0
0
--
×
RxD1 Input
--
-- 0Note 1 0
0
1
×
--
×
----------
P02 P02
Input
--
×
0
0--
1
×
×
--
------------
Output
--
0
0
0 -- 0 0/1 TxD1 = 1
--
N-ch open
--
drain output
SO10 = 1
1
0
0 -- 0 0/1
Note 4
ANI17 Analog input
--
×
1
0--
1
×
×
--
------------
TS28 Output
--
×
0
1--
1
×
×
--
------------
TxD1 Output
PIOR5 = 0 0/1
0
0--
0
1
×
Note 3
--
------------
SO10 Output
PIOR5 = 0 0/1
0
0--
0
1
×
Note 3
--
--------------
P03 P03
Input
--
×
0
0--
1
×
×
--
------------
Output
--
N-ch open
--
drain output
0
0
0 -- 0 0/1 SDA10 = 1
--
Note 4
1
0
0 -- 0 0/1
ANI16 Analog input
--
×
1
0--
1
×
×
--
------------
TS29 Output
--
×
0
1--
1
×
×
--
------------
SI10 Input
PIOR5 = 0 ×
0
0--
1
×
×
Note 3
--
--------------
RxD1 Input
PIOR5 = 0 ×
0
0--
1
×
×
Note 3
--
------------
SDA10 I/O
PIOR5 = 0 1
0
0--
0
1
×
Note 3
--
--------------
Note 1. Note 2. Note 3. Note 4.
This setting is only applicable in the 30- and 32-pin products. This setting is only applicable in the 30- to 48-pin products. This setting is only applicable in the 100- and 128-pin products. This setting is only applicable in the 64- to 128-pin products.
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CHAPTER 4 PORT FUNCTIONS
Table 4 - 8 Examples of Register and Output Latch Settings for Alternate Functions (Products with 192-Kbyte to 768Kbyte Flash Memory and 80-Pin and 100-Pin Products with 128-Kbyte Flash Memory) (2/21)
Pin Name PIOR POMxx
PMCAxx PMCTxx PMCEx
PMxx Pxx 30-pin 32-pin 36-pin 40-pin 44-pin 48-pin 52-pin 64-pin 80-pin 100-pin 128-pin
Function Used
Function Name
I/O
P04 P04
Input
--
×
Output
--
0
N-ch open
--
1
drain output
SCK10 Input
PIOR5 = 0 ×
Note 1
------ ------ ------
------
Alternate Function Output
SAU and UARTA (excluding clock output from the UARTA)
Other than SAU and UARTA
(including clock output from the
UARTA)
1×
×
--
--------------
0 0/1 SCK10/
--
SCL10 = 1 0 0/1
1×
×
--
--------------
Output
PIOR5 = 0 0/1 -- -- -- 0 1
×
Note 1
--
--------------
SCL10 Output
PIOR5 = 0 0/1 -- -- -- 0 1
×
Note 1
--
--------------
P05 P05
TS10 TI05
Input Output I/O Input
--
---- 0 -- 1 ×
--
×
--------------
--
-- -- 0 -- 0 0/1
--
TO05 = 0Note 2
--
---- 1 -- 1 ×
--
×
--------------
PIOR0 = 0 -- -- 0 -- 1 ×
--
Note 2
×
-------------- ----
TO05 Output
PIOR0 = 0 -- -- 0 -- 0 0
--
Note 2
×
-------------- ----
P06 P06
Input Output
TS11 I/O
TI06 Input
TO06 Output
CLKA0 Output
P07 P07
Input
Output
--
---- 0 -- 1 ×
--
-- -- 0 -- 0 0/1
--
---- 1 --
PIOR0 = 0 -- -- 0 --
PIOR0 = 0 -- -- 0 --
--
---- 0 --
--
--------
--
--------
1× 1× 00 00 1× 0 0/1
--
×
--------------
--
TO06 = 0Note 2
CLKA0 = 0Note 2
--
×
--------------
--
×
-------------- ----
--
CLKA0 = 0 -- -- -- -- -- -- -- -- --
--
TO06 = 0 -- -- -- -- -- -- -- -- --
--
--
--------------------
--
--
Note 1. Note 2.
This setting is only applicable in the 100- and 128-pin products. This setting is only applicable in the 64- and 80-pin products.
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CHAPTER 4 PORT FUNCTIONS
Pin Name PIOR POMxx
PMCAxx PMCEx CCDE CCSx PMxx
Pxx 30-pin 32-pin 36-pin 40-pin 44-pin 48-pin 52-pin 64-pin 80-pin 100-pin 128-pin
Table 4 - 8 Examples of Register and Output Latch Settings for Alternate Functions (Products with 192-Kbyte to 768Kbyte Flash Memory and 80-Pin and 100-Pin Products with 128-Kbyte Flash Memory) (3/21)
Function Used
Function Name
I/O
Alternate Function Output
SAU and UARTA (excluding clock output from the UARTA)
Other than SAU and UARTA (including clock output from the UARTA)
P10 P10 Input
--
× -- 0 ---- 1 ×
×
×
Output
--
N-ch open
--
drain output
0 -- 0 -- -- 0 0/1 SCK00/ SCL00 = 1
1 -- 0 -- -- 0 0/1
(TO07) = 0
EI10 Input
--
× -- 0 ---- 1 ×
×
×
EO10 Output
--
0/1 -- 1 -- -- 0 ×
×
×
SCK00 Input
PIOR1 = 0 × -- 0 -- -- 1 ×
×
×
Output
PIOR1 = 0 0/1 -- 0 -- -- 0 1
×
(TO07) = 0
SCL00 Output
PIOR1 = 0 0/1 -- 0 -- -- 0 1
×
(TO07) = 0
(TI07) Input
PIOR0 = 1 × -- 0 -- -- 1 ×
×
×
(TO07) Output
PIOR0 = 1 0 -- 0 -- -- 0 0
×
×
P11 P11
Input
--
× -- 0 ---- 1 ×
×
×
Output
--
0 -- 0 -- -- 0 0/1 SDA00 = 1 (TO06) = 0
N-ch open
--
drain output
1 -- 0 -- -- 0 0/1
EI11 Input
--
× -- 0 ---- 1 ×
×
×
EO11 Output
--
0/1 -- 1 -- -- 0 ×
×
×
SI00 Input
PIOR1 = 0 × -- 0 -- -- 1 ×
×
×
RxD0 Input
PIOR1 = 0 × -- 0 -- -- 1 ×
×
×
SDA00 I/O
PIOR1 = 0 1 -- 0 -- -- 0 1
×
(TO06) = 0
(TI06) Input
PIOR0 = 1 × -- 0 -- -- 1 ×
×
×
(TO06) Output
PIOR0 = 1 0 -- 0 -- -- 0 0
×
×
P12 P12 Input
--
× -- 0 ---- 1 ×
×
×
Output
--
N-ch open
--
drain output
0 -- 0 -- -- 0 0/1
SO00/
TxD0 = 1 1 -- 0 -- -- 0 0/1
(TO05) = 0
EI12 Input
--
× -- 0 ---- 1 ×
×
×
EO12 Output
--
0/1 -- 1 -- -- 0 ×
×
×
SO00 Output
PIOR1 = 0 0/1 -- 0 -- -- 0 1
×
(TO05) = 0
TxD0 Output
PIOR1 = 0 0/1 -- 0 -- -- 0 1
×
(TO05) = 0
(INTP5) Input
PIOR4 = 1 × -- 0 -- -- 1 ×
×
×
--------------
(TI05) Input
PIOR0 = 1 × -- 0 -- -- 1 ×
×
×
(TO05) Output
PIOR0 = 1 0 -- 0 -- -- 0 0
×
×
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CHAPTER 4 PORT FUNCTIONS
Table 4 - 8 Examples of Register and Output Latch Settings for Alternate Functions (Products with 192-Kbyte to 768Kbyte Flash Memory and 80-Pin and 100-Pin Products with 128-Kbyte Flash Memory) (4/21)
Pin Name PIOR POMxx
PMCAxx PMCEx CCDE CCSx PMxx
Pxx 30-pin 32-pin 36-pin 40-pin 44-pin 48-pin 52-pin 64-pin 80-pin 100-pin 128-pin
Function Used
Function Name
I/O
Alternate Function Output
SAU and UARTA (excluding clock output from the UARTA)
Other than SAU and UARTA (including clock output from the UARTA)
P13 P13
Input
--
× 0 0 ---- 1 ×
×
×
Output
--
0 0 0 -- -- 0 0/1 TxD2/
(TO04) = 0
N-ch open
SO20 = 1 (SDAA0) = 0
--
1 0 0 -- -- 0 0/1
drain output
EO13
Output
--
0/1 0 1 -- -- 0 ×
×
×
TxD2
Output
PIOR1 = 0 0/1 0 0 -- -- 0 1
×
(TO04) = 0
(SDAA0) = 0
SO20
Output
PIOR1 = 0 0/1 0 0 -- -- 0 1
×
(TO04) = 0
(SDAA0) = 0
(SDAA0) I/O
PIOR2 = 1 1 0 0 -- -- 0 0
×
(TO04) = 0
(TI04)
Input
PIOR0 = 1 × 0 0 -- -- 1 ×
×
×
(TO04) Output
PIOR0 = 1 0 0 0 -- -- 0 0
×
(SDAA0) = 0
IVREF0 Analog input
--
× 1 0 ---- 1 ×
×
×
P14 P14
Input
--
× -- 0 ---- 1 ×
×
×
Output
--
0 -- 0 -- -- 0 0/1 SDA20 = 1 VCOUT1 = 0
N-ch open
--
1 -- 0 -- -- 0 0/1
drain output
(TO03) = 0 (SCLA0) = 0
EO14
Output
--
0/1 -- 1 -- -- 0 ×
×
×
VCOUT1 Output
--
0 -- 0 ---- 0 0
×
(TO03) = 0
(SCLA0) = 0
RxD2
Input
PIOR1 = 0 × -- 0 -- -- 1 ×
×
×
SI20
Input
PIOR1 = 0 × -- 0 -- -- 1 ×
×
×
SDA20 I/O
PIOR1 = 0 1 -- 0 -- -- 0 1
×
VCOUT1 = 0
(TO03) = 0
(SCLA0) = 0
(SCLA0) I/O
PIOR2 = 1 1 -- 0 -- -- 0 0
×
VCOUT1 = 0
(TO03) = 0
(TI03)
Input
PIOR0 = 1 × -- 0 -- -- 1 ×
×
×
(TO03) Output
PIOR0 = 1 0 -- 0 -- -- 0 0
×
VCOUT1 = 0
(SCLA0) = 0
P15 P15
Input
--
× -- 0 ---- 1 ×
×
×
Output
--
0 -- 0 -- -- 0 0/1 SCK20/ PCLBUZ1 = 0
SCL20 = 1
Note
N-ch open
--
1 -- 0 -- -- 0 0/1
(TO02) = 0
drain output
EO15
Output
--
0/1 -- 1 -- -- 0 ×
×
×
PCLBUZ1 Output
--
0 -- 0 ---- 0 0
×
(TO02) = 0 -- -- -- --
SCK20 Input
PIOR1 = 0 × -- 0 -- -- 1 ×
×
×
Output
PIOR1 = 0 0/1 -- 0 -- -- 0 1
×
PCLBUZ1 = 0
Note
(TO02) = 0
SCL20 Output
PIOR1 = 0 0/1 -- 0 -- -- 0 1
×
PCLBUZ1 = 0
Note
(TO02) = 0
(TI02)
Input
PIOR0 = 1 × -- 0 -- -- 1 ×
×
×
(TO02) Output
PIOR0 = 1 0 -- 0 -- -- 0 0
×
PCLBUZ1 = 0
Note
Note
This setting is only applicable in the 30- to 52-pin products.
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CHAPTER 4 PORT FUNCTIONS
Pin Name PIOR POMxx
PMCAxx PMCEx CCDE CCSx PMxx
Pxx 30-pin 32-pin 36-pin 40-pin 44-pin 48-pin 52-pin 64-pin 80-pin 100-pin 128-pin
<R>
Table 4 - 8 Examples of Register and Output Latch Settings for Alternate Functions (Products with 192-Kbyte to 768Kbyte Flash Memory and 80-Pin and 100-Pin Products with 128-Kbyte Flash Memory) (5/21)
Function Used
Function Name
I/O
P16 P16 Input Output
CCD00 Output EO16 Output TI01 Input TO01 Output INTP5 Input
Alternate Function Output
Other SAU and than SAU UARTA and (excluding UARTA
clock (including output clock from the output UARTA) from the
UARTA)
-- -- -- 0 CCDE00 CCS0x 1 ×
--
= 0
= xxx
×
-- -- -- 0 CCDE00 CCS0x 0 0/1
= 0
= xxx
-- TO01 = 0
-- -- -- 0 CCDE00 CCS0x 0 0 = 1 = 001 to 011
-- TO01 = 0
-- -- -- 1 CCDE00 CCS0x 0 ×
--
= 0
= xxx
×
-- -- -- 0 CCDE00 CCS0x 1 ×
--
= 0
= xxx
×
-- -- -- 0 CCDE00 CCS0x 0 0
--
= 0
= xxx
×
PIOR4 -- -- 0 CCDE00 CCS0x 1 ×
--
= 0
= 0
= xxx
Note
×
(SI00) Input (RxD0) Input P17 P17 Input
PIOR1 -- -- = 1
PIOR1 -- -- = 1
-- ×--
Output
-- 0--
N-ch open
--
drain output
1--
CCD01 Output
-- 0/1 --
EO17 Output
-- 0/1 --
TI02 Input TO02 Output (TxD0) Output (SO00) Output
PIOR0 × -- = 0
PIOR0 0 -- = 0
PIOR1 0/1 -- = 1
PIOR1 0/1 -- = 1
0 CCDE00 CCS0x 1
= 0
= xxx
0 CCDE00 CCS0x 1
= 0
= xxx
0 CCDE01 CCS0x 1
= 0
= xxx
0 CCDE01 CCS0x 0
= 0
= xxx
0 CCDE01 CCS0x 0
= 0
= xxx
0 CCDE01 CCS0x 0 = 1 = 001 to 011
1 CCDE01 CCS0x 0
= 0
= xxx
0 CCDE01 CCS0x 1
= 0
= xxx
0 CCDE01 CCS0x 0
= 0
= xxx
0 CCDE01 CCS0x 0
= 0
= xxx
0 CCDE01 CCS0x 0
= 0
= xxx
×
--
×
--------------
×
--
×
×
×
×
0/1 (TxD0) = 1 TO02 = 0
(SO00) = 1
Note
0/1
0
×
TO02 = 0
×
×
×
×
×
×
0
×
×
1
×
TO02 = 0
1
×
TO02 = 0 -- -- -- -- -- -- --
Note
This setting is only applicable in the 64- to 128-pin products.
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CHAPTER 4 PORT FUNCTIONS
Table 4 - 8 Examples of Register and Output Latch Settings for Alternate Functions (Products with 192-Kbyte to 768Kbyte Flash Memory and 80-Pin and 100-Pin Products with 128-Kbyte Flash Memory) (6/21)
Pin Name
Function Used
Function Name
I/O
PMCAxx PMCTxx PMxx
Pxx
30- 32- 36- 40- 44- 48- 52- 64- 80- 100- 128pin pin pin pin pin pin pin pin pin pin pin
P20 P20
Input
0
--
1
×
Output
0
--
0
0/1
ANI0
Analog input
1
--
1
×
AVREFP Reference voltage
1
--
1
×
EI20
Input
0
--
1
×
P21 P21
Input
0
--
1
×
Output
0
--
0
0/1
ANI1
Analog input
1
--
1
×
AVREFM Reference voltage
1
--
1
×
EI21
Input
0
--
1
×
P22 P22
Input
0
0
1
×
Output
0
0
0
0/1
ANI2
Analog input
1
0
1
×
ANO0
Analog output
1
0
1
×
TS20
I/O
0
1
1
×
EI22
Input
0
0
1
×
P23 P23
Input
0
0
1
×
Output
0
0
0
0/1
ANI3
Analog input
1
0
1
×
ANO1
Analog output
1
0
1
×
IVREF0
Analog input
1
0
1
×
TS21
I/O
0
1
1
×
EI23
Input
0
0
1
×
P24 P24
Input
0
0
1
×
----
Output
0
0
0
0/1
ANI4
Analog input
1
0
1
×
----
TS22
I/O
0
1
1
×
----
P25 P25
Input
0
0
1
×
----
Output
0
0
0
0/1
ANI5
Analog input
1
0
1
×
----
TS23
I/O
0
1
1
×
----
P26 P26
Input
0
0
1
×
------
Output
0
0
0
0/1
ANI6
Analog input
1
0
1
×
------
TS24
I/O
0
1
1
×
------
P27 P27
Input
0
0
1
×
--------
Output
0
0
0
0/1
ANI7
Analog input
1
0
1
×
--------
TS25
I/O
0
1
1
×
--------
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RL78/G23
CHAPTER 4 PORT FUNCTIONS
Table 4 - 8 Examples of Register and Output Latch Settings for Alternate Functions (Products with 192-Kbyte to 768Kbyte Flash Memory and 80-Pin and 100-Pin Products with 128-Kbyte Flash Memory) (7/21)
Pin Name PIOR POMxx
PMCAxx PMCTxx
PMxx Pxx 30-pin 32-pin 36-pin 40-pin 44-pin 48-pin 52-pin 64-pin 80-pin 100-pin 128-pin
Function Used
Function Name
I/O
P30 P30
Input Output
Alternate Function Output
SAU and UARTA (excluding clock output from the UARTA)
Other than SAU and UARTA
(including clock output from the
UARTA)
--
---- 0 1 ×
×
×
--
-- -- 0 0 0/1 SCK11/
VCOUT0 = 0
SCL11 = 1 RTC1HZ = 0
Note 1
TSCAP
I/O
--
---- 1 1 ×
×
EI30
Input
--
---- 0 1 ×
×
VCOUT0
Output
--
---- 0 0 0
×
INTP3
Input
PIOR5 = 0 -- -- 0 1 ×
×
Note 2
× × RTC1HZ = 0 ×
RTC1HZ SCK11
SCL11 P31 P31
Output Input Output
Output
Input Output
TS01 EI31 TI03 TO03
INTP4
I/O Input Input Output
Input
--
---- 0 0 0
--
---- 0 1 ×
--
---- 0 0 1
--
---- 0 0 1
--
---- 0 1 ×
--
-- -- 0 0 0/1
--
---- 1 1 ×
--
---- 0 1 ×
PIOR0 = 0 -- -- 0 1 ×
PIOR0 = 0 -- -- 0 0 0
PIOR5 = 0 -- -- 0 1 ×
Note 2
×
VCOUT0 = 0
×
×
--
×
VCOUT0 = 0 --
RTC1HZ = 0
×
VCOUT0 = 0 --
RTC1HZ = 0
--
×
--
TO03 = 0
PLCBUZ0 = 0Note 3
(PCLBUZ0) = 0Note 4
×
×
--
×
--
×
--
PLCBUZ0 = 0Note 3
(PCLBUZ0) = 0Note 4
--
×
PCLBUZ0 Output
--
---- 0 0 0
--
(PCLBUZ0) Output
PIOR3 = 1 -- -- 0 0 0
--
P32 P32
Input
--
------ 1 ×
--
Output
--
-- -- -- 0 0/1
--
CLKA1
Output
--
------ 0 0
--
P33 P33
Input
--
------ 1 ×
--
Output
--
-- -- -- 0 0/1
--
RxDA1
Input
--
------ 1 ×
--
P34 P34
Input
--
× ---- 1 ×
×
Output
--
0 -- -- 0 0/1 TxDA1 = 1
N-ch open drain output
--
1 -- -- 0 0/1
TxDA1
Output
--
0/1 -- -- 0 1
×
P35 P35 to P37 Input
--
--0--1--
--
to P37
Output
--
-- 0 -- 0 0/1
--
ANI23 to
Analog input
--
--1--1 ×
--
ANI21
TO03 = 0 TO03 = 0
× CLKA1 = 0
× -- -- -- -- --
------------ ---------- --------------------
-------------------- --------------------
-------------------- --------------------
--
--------------------
--
--------------------
--
--
--------------------
Note 1. Note 2. Note 3. Note 4.
This setting is only applicable in the 30- to 100-pin products. This setting is only applicable in the 128-pin products. This setting is only applicable in the 30- to 44-pin products. This setting is only applicable in the 48- to 128-pin products.
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RL78/G23
CHAPTER 4 PORT FUNCTIONS
Table 4 - 8 Examples of Register and Output Latch Settings for Alternate Functions (Products with 192-Kbyte to 768Kbyte Flash Memory and 80-Pin and 100-Pin Products with 128-Kbyte Flash Memory) (8/21)
Pin Name PIOR POMxx PMxx Pxx 30-pin 32-pin 36-pin 40-pin 44-pin 48-pin 52-pin 64-pin 80-pin 100-pin 128-pin
Function Used
Function Name
I/O
Alternate Function Output
SAU and UARTA (excluding clock output from the
UARTA)
Other than SAU and UARTA
(including clock output from the
UARTA)
P40 P40
Input
--
--
1
×
--
--
Output
--
--
0
0/1
--
--
P41 P41
Input
--
--
1
×
--
×
--------
Output
--
--
0
0/1
--
TO07 = 0Note 1
RxDA1 Input
--
--
1
×
--
×
-------- --
TI07 Input
PIOR0 = 0 --
1
×
--
×
-------- ----
TO07 Output
PIOR0 = 0 --
0
0
--
×
-------- ----
P42 P42
Input
--
×
1
×
--
×
--------------
Output
--
0
0
0/1 TxDA1 = 1Note 3
TO04 = 0
N-ch open
--
1
0 0/1
drain output
TxDA1 Output
--
0/1 0
1
×
TO04 = 0
-------------- --
TI04 Input
PIOR0 = 0 ×
1
×
--
×
--------------
TO04 Output
PIOR0 = 0 0
0
0
×
×
--------------
P43 P43
Input
--
×
1
×
×
×
--------------
Output N-ch open
--
0
0 0/1
SCK01/
CLKA1 = 0Note 3
SCL01 = 1Note 2
--
1
0 0/1
drain output
SCK01 Input
--
×
1
×
×
×
----------------
Output
--
0/1 0
1
×
CLKA1 = 0Note 4 -- -- -- -- -- -- -- --
SCL01 Output
--
0/1 0
1
×
CLKA1 = 0Note 4 -- -- -- -- -- -- -- --
CLKA1 Output
--
0
0
0
×
×
-------------- --
P44 P44
Input
--
×
1
×
×
--
----------------
Output
--
0
0 0/1
SDA01 = 1
--
N-ch open
--
1
0 0/1
drain output
SI01 Input
--
×
1
×
×
--
----------------
SDA01 I/O
--
1
0
1
×
--
----------------
P45 P45
Input
--
×
1
×
×
--
----------------
Output
--
0
0 0/1
SO01 = 1
--
N-ch open
--
1
0 0/1
drain output
SO01 Output
--
0/1 0
1
×
--
----------------
P46 P46
Input
--
--
1
×
--
×
------------------
Output
--
--
0
0/1
--
TO05 = 0
INTP1 Input
PIOR5 = 0 --
1
×
--
×
------------------
TI05 Input
PIOR0 = 0 --
1
×
--
×
------------------
TO05 Output
PIOR0 = 0 --
0
0
--
×
------------------
P47 P47
Input
--
--
1
×
--
--
------------------
Output
--
--
0
0/1
--
--
INTP2 Input
--
--
1
×
--
--
------------------
Note 1. Note 2. Note 3. Note 4.
This setting is only applicable in the 44- to 80-pin products. This setting is only applicable in the 80- to 128-pin products. This setting is only applicable in the 64- to 100-pin products. This setting is only applicable in the 80- to 100-pin products.
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RL78/G23
CHAPTER 4 PORT FUNCTIONS
<R>
Table 4 - 8 Examples of Register and Output Latch Settings for Alternate Functions (Products with 192-Kbyte to 768Kbyte Flash Memory and 80-Pin and 100-Pin Products with 128-Kbyte Flash Memory) (9/21)
Pin Name PIOR POMxx
PMCTxx PMCEx CCDE CCSx PMxx
Pxx 30-pin 32-pin 36-pin 40-pin 44-pin 48-pin 52-pin 64-pin 80-pin 100-pin 128-pin
Function Used
Function Name
I/O
Alternate Function Output
SAU and UARTA (excluding clock output from the UARTA)
Other than SAU and UARTA (including
clock output from the UARTA)
P50 P50
Input
-- × 0 0 CCDE03 CCS0x 1 ×
×
= 0
= xxx
--
Output
-- 0 0 0 CCDE03 CCS0x 0 0/1 SDA11 = 1
--
= 0
= xxx
Note 1
N-ch open -- 1 0 0 CCDE03 CCS0x 0 0/1
drain output
= 0
= xxx
TS00 I/O
-- × 1 0 CCDE03 CCS0x 1 ×
×
= 0
= xxx
--
EI50
Input
-- × 0 0 CCDE03 CCS0x 1 ×
×
= 0
= xxx
--
EO50 Output
-- 0/1 0 1 CCDE03 CCS0x 0 ×
×
= 0
= xxx
--
CCD03 Output
-- 0/1 0 0 CCDE03 CCS0x 0 0
×
= 1 = 001 to
011
--
INTP1 Input
-- × 0 0 CCDE03 CCS0x 1 ×
×
= 0
= xxx
--
----
SI11
Input
-- × 0 0 CCDE03 CCS0x 1 ×
×
= 0
= xxx
--
--
SDA11 I/O
-- 1 0 0 CCDE03 CCS0x 0 1
×
= 0
= xxx
--
--
P51 P51
Input
-- -- -- 0 CCDE02 CCS0x 1 ×
×
= 0
= xxx
--
Output
-- -- -- 0 CCDE02 CCS0x 0 0/1 SO11 = 1
--
= 0
= xxx
Note 1
EI51
Input
-- -- -- 0 CCDE02 CCS0x 1 ×
×
= 0
= xxx
EO51 Output
-- -- -- 1 CCDE02 CCS0x 0 ×
×
= 0
= xxx
CCD02 Output
-- -- -- 0 CCDE02 CCS0x 0 0
×
= 1 = 001 to
011
INTP2 Input
-- -- -- 0 CCDE02 CCS0x 1 ×
×
= 0
= xxx
SO11 Output
-- -- -- 0 CCDE02 CCS0x 0 1
×
= 0
= xxx
P52 P52
Input
-- × ---- --
--
1×
×
Output
-- 0 ----
--
N-ch open -- 1 -- -- -- drain output
--
0 0/1 SO31 = 1
Note 2
--
0 0/1
SO31 Output
-- 0/1 -- -- --
--
01
×
(INTP10) Input
PIOR1 × -- -- --
--
1×
×
= 1
--
--
--
--
----
--
--
--
--------------
--
--
--
----------------
--
-------------- ------
Note 1. Note 2.
This setting is only applicable in the 30- to 100-pin products. This setting is only applicable in the 80- to 128-pin products.
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RL78/G23
CHAPTER 4 PORT FUNCTIONS
Table 4 - 8 Examples of Register and Output Latch Settings for Alternate Functions (Products with 192-Kbyte to 768Kbyte Flash Memory and 80-Pin and 100-Pin Products with 128-Kbyte Flash Memory) (10/21)
Pin Name PIOR POMxx
PMCTxx PMCEx CCDE CCSx PMxx
Pxx 30-pin 32-pin 36-pin 40-pin 44-pin 48-pin 52-pin 64-pin 80-pin 100-pin 128-pin
Function Used
Function Name
I/O
Alternate Function Output
SAU and UARTA (excluding clock output from the UARTA)
Other than SAU and UARTA (including
clock output from the UARTA)
P53 P53
Input
--
× -------- 1 ×
×
--
--------------
Output
--
0 -- -- -- -- 0 0/1 SDA31 = 1
--
Note
N-ch open
--
1 -- -- -- -- 0 0/1
--
drain output
SI31
Input
--
× -------- 1 ×
×
--
----------------
SDA31
I/O
--
1 -------- 0 1
×
--
----------------
(INTP11) Input
PIOR1 = 1 × -- -- -- -- 1 ×
×
--
-------------- ------
P54 P54
Input
--
× -------- 1 ×
×
--
--------------
Output
--
0 -- -- -- -- 0 0/1 SCK31/
--
SCL1 = 1
N-ch open
--
1 -- -- -- -- 0 0/1
Note
--
drain output
SCK31
Input
--
× -------- 1 ×
×
--
----------------
Output
--
0/1 -- -- -- -- 0 1
×
--
----------------
SCL31
Output
--
0/1 -- -- -- -- 0 1
×
--
----------------
P55 P55
Input
--
× -------- 1 ×
×
×
--------------
Output
--
N-ch open
--
drain output
0 -- -- -- -- 0 0/1 (SCK00) = 1 (PCLBUZ1) = 0
1 -- -- -- -- 0 0/1
(PCLBUZ1) Output
PIOR4 = 1 0 -- -- -- -- 0 0
×
×
--------------
(SCK00) Input
PIOR1 = 1 × -- -- -- -- 1 ×
×
×
--------------
Output
PIOR1 = 1 0/1 -- -- -- -- 0 1
×
(PCLBUZ1) -- -- -- -- -- -- --
= 0
P56 P56
Input
--
---------- 1 ×
--
--
------------------
Output
--
-- -- -- -- -- 0 0/1
--
--
(INTP1)
Input
PIOR5 = 1 -- -- -- -- -- 1 ×
--
--
------------------
P57 P57
Input
--
---------- 1 ×
--
--
------------------
Output
--
-- -- -- -- -- 0 0/1
--
--
(INTP3)
Input
PIOR5 = 1 -- -- -- -- -- 1 ×
--
--
------------------
Note
This setting is only applicable in the 80- to 128-pin products.
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RL78/G23
CHAPTER 4 PORT FUNCTIONS
Pin Name PIOR
PMCTxx PMCEx CCDE CCSx PMxx
Pxx 30-pin 32-pin 36-pin 40-pin 44-pin 48-pin 52-pin 64-pin 80-pin 100-pin 128-pin
Table 4 - 8 Examples of Register and Output Latch Settings for Alternate Functions (Products with 192-Kbyte to 768Kbyte Flash Memory and 80-Pin and 100-Pin Products with 128-Kbyte Flash Memory) (11/21)
Function Used
Function Name
I/O
P60 P60 Input
--
N-ch open
--
drain output
(6-V tolerance)
EO60 Output
--
--
CCD04 Output
--
--
SCLA0 I/O
PIOR2 = 0 --
P61 P61 Input
--
N-ch open
--
drain output
(6-V tolerance)
EO61 Output
--
--
CCD05 Output
--
--
SDAA0 I/O
PIOR2 = 0 --
P62 P62 Input
--
--
N-ch open
--
--
drain output
(6-V tolerance)
CCD06 Output
--
--
SCLA1 I/O
--
--
P63 P63 Input
--
--
N-ch open
--
--
drain output
(6-V tolerance)
CCD07 Output
--
--
SDAA1 I/O P64 P64 Input
Output TS12 I/O TI10 Input TO10 Output P65 P65 Input
Output TS13 I/O TI11 Input TO11 Output P66 P66 Input
Output TS14 I/O TI12 Input TO12 Output P67 P67 Input
Output TS15 I/O TI13 Input TO13 Output
--
--
--
0
--
0
--
1
--
0
--
0
--
0
--
0
--
1
--
0
--
0
--
0
--
0
--
1
--
0
--
0
--
0
--
0
--
1
--
0
--
0
0 CCDE04 = 0 CCS4x = 000 1 0 CCDE04 = 0 CCS4x = 000 0
1 CCDE04 = 0 CCS4x = 000 0
0 CCDE04 = 1 CCS4x
0
= 001 to 100
0 CCDE04 = 0 CCS4x = 000 0
0 CCDE05 = 0 CCS5x = 000 1
0 CCDE05 = 0 CCS5x = 000 0
1 CCDE05 = 0 CCS5x = 000 0
0 CCDE05 = 1 CCS5x
0
= 001 to 100
0 CCDE05 = 0 CCS5x = 000 0
-- CCDE06 = 0 CCS6x = 000 1
-- CCDE06 = 0 CCS6x = 000 0
-- CCDE06 = 1 CCS6x
0
= 001 to 100
-- CCDE06 = 0 CCS6x = 000 0
-- CCDE07 = 0 CCS7x = 000 1
-- CCDE07 = 0 CCS7x = 000 0
-- CCDE07 = 1 CCS7x
0
= 001 to 100
-- CCDE07 = 0 CCS7x = 000 0
--
--
--
1
--
--
--
0
--
--
--
1
--
--
--
1
--
--
--
0
--
--
--
1
--
--
--
0
--
--
--
1
--
--
--
1
--
--
--
0
--
--
--
1
--
--
--
0
--
--
--
1
--
--
--
1
--
--
--
0
--
--
--
1
--
--
--
0
--
--
--
1
--
--
--
1
--
--
--
0
Alternate Function Output
SAU and UARTA (excluding clock output from the UARTA)
Other than SAU and UARTA (including clock output from the UARTA)
×
--
×
0/1
--
SCLA0 = 0
×
--
×
0
--
SCLA0 = 0
0
--
×
×
--
×
0/1
--
SDAA0 = 0
×
--
×
0
--
SDAA0 = 0
0
--
×
×
--
×
--
0/1
--
SCLA1 = 0Note
0
--
SCLA1 = 0Note --
0
--
×
--------
×
--
×
--------
0/1
--
SDAA1 = 0
0
--
SDAA1 = 0 -- -- -- --
0
--
×
--
0/1
--
×
--
×
--
0
--
×
--
0/1
--
×
--
×
--
0
--
×
--
0/1
--
×
--
×
--
0
--
×
--
0/1
--
×
--
×
--
0
--
×
--------
×
----------------
TO10 = 0
×
----------------
×
----------------
×
----------------
×
----------------
TO11 = 0
×
----------------
×
----------------
×
----------------
×
----------------
TO12 = 0
×
----------------
×
----------------
×
----------------
×
----------------
TO13 = 0
×
----------------
×
----------------
×
----------------
Note
This setting is only applicable in the 44- to 128-pin products.
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 238 of 1478
RL78/G23
CHAPTER 4 PORT FUNCTIONS
Table 4 - 8 Examples of Register and Output Latch Settings for Alternate Functions (Products with 192-Kbyte to 768Kbyte Flash Memory and 80-Pin and 100-Pin Products with 128-Kbyte Flash Memory) (12/21)
Pin Name PIOR POMxx
PMCTxx PMxx Pxx 30-pin 32-pin 36-pin 40-pin 44-pin 48-pin 52-pin 64-pin 80-pin 100-pin 128-pin
Function Used
Function Name
I/O
P70 P70
Input Output
--
--
0
--
--
0
Alternate Function Output
SAU and UARTA (excluding clock output from the
UARTA)
Other than SAU and UARTA
(including clock output from the
UARTA)
1
×
×
--
--
0
0/1 SCK21/SCL21 = 1
--
Note 1
TS02 I/O
--
--
1
RIN0 Input
--
--
0
KR0
Input
--
--
0
SCK21 Input
--
--
0
Output
--
--
0
SCL21 Output
--
--
0
P71 P71
Input
--
×
0
Output
--
0
0
N-ch open
--
1
0
drain output
TS03 I/O
--
×
1
KR1
Input
--
×
0
SI21
Input
--
×
0
SDA21 I/O
--
1
0
RxDA0 Input
--
×
0
P72 P72
Input
--
×
0
Output
--
0
0
N-ch open
--
1
0
drain output
TS04 I/O
--
×
1
KR2
Input
--
×
0
SO21 Output
-- 0/1
0
TxDA0 Output
-- 0/1
0
P73 P73
Input
--
--
0
Output
--
--
0
TS05 I/O
--
--
1
KR3
Input
--
--
0
SO01 Output
--
--
0
1
×
1
×
1
×
1
×
0
1
0
1
1
×
0
0/1
0
0/1
× × × × × × × SDA21 = 1
1
×
1
×
1
×
0
1
1
×
1
×
0
0/1
0
0/1
× × × × × × SO21 = 1 TxDA0 = 1
1
×
×
1
×
×
0
1
TxDA0 = 1
0
1
SO21 = 1
1
×
×
0
0/1
SO01 = 1Note 2
1
×
×
1
×
×
0
1
×
--
--
--
--
--
------
--
----
--
----
--
----
--
----
--
--
----
--
------
--
----
--
----
--
---- ----
--
----
--
--
----
--
------
--
----
--
---- ----
--
------
--
--
------
--
------
--
---------- ------
Note 1. Note 2.
This setting is only applicable in the 36- to 128-pin products. This setting is only applicable in the 48- to 64-pin products.
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Page 239 of 1478
RL78/G23
CHAPTER 4 PORT FUNCTIONS
Table 4 - 8 Examples of Register and Output Latch Settings for Alternate Functions (Products with 192-Kbyte to 768Kbyte Flash Memory and 80-Pin and 100-Pin Products with 128-Kbyte Flash Memory) (13/21)
Pin Name PIOR POMxx
PMCTxx PMxx Pxx 30-pin 32-pin 36-pin 40-pin 44-pin 48-pin 52-pin 64-pin 80-pin 100-pin 128-pin
Function Used
Function Name
I/O
Alternate Function Output
SAU and UARTA (excluding clock output from the
UARTA)
Other than SAU and UARTA
(including clock output from the
UARTA)
P74 P74
Input
--
×
0
1
×
×
--
----------
Output
--
0
0
0
0/1 SDA01 = 1Note 1
--
N-ch open
--
drain output
1
0
0 0/1
TS06
I/O
--
×
1
1
×
×
--
----------
KR4
Input
--
×
0
1
×
×
--
----------
INTP8 Input
PIOR5 = 0 ×
0
1
×
×
Note 2
--
----------
SI01 SDA01 P75 P75
Input I/O Input Output
--
×
0
1
×
×
--
--
1
0
0
1
×
--
--
--
0
1
×
×
--
--
--
0
0 0/1 SCK01/SCL01 = 1
--
Note 1
---------- ------ ---------- ------ ----------
TS07
I/O
--
--
1
1
×
×
KR5
Input
--
--
0
1
×
×
INTP9 Input
PIOR5 = 0 --
0
1
×
×
Note 2
--
----------
--
----------
--
----------
SCK01
SCL01 P76 P76
TS08 KR6 INTP10 (RxD2) P77 P77
TS09 KR7 INTP11 (TxD2)
Input Output Output Input Output I/O Input Input Input Input Output I/O Input Input Output
--
--
0
--
--
0
--
--
0
--
--
0
--
--
0
--
--
1
--
--
0
PIOR1 = 0 --
0
PIOR1 = 1 --
0
--
--
0
--
--
0
--
--
1
--
--
0
PIOR1 = 0 --
0
PIOR1 = 1 --
0
1
×
0
1
0
1
1
×
0 0/1
1
×
1
×
1
×
1
×
1
×
0 0/1
1
×
1
×
1
×
0
1
× × × -- -- -- -- -- -- × (TxD2) = 1 × × × ×
--
---------- ------
--
---------- ------
--
---------- ------
--
------------
--
--
------------
--
------------
--
------------
--
------------
--
------------
--
--
------------
--
------------
--
------------
--
------------
Note 1. Note 2.
This setting is only applicable in the 48- to 64-pin products. This setting is only applicable in the 100- and 128-pin products.
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 240 of 1478
RL78/G23
CHAPTER 4 PORT FUNCTIONS
Pin Name PIOR POMxx PMxx Pxx 30-pin 32-pin 36-pin 40-pin 44-pin 48-pin 52-pin 64-pin 80-pin 100-pin 128-pin
Table 4 - 8 Examples of Register and Output Latch Settings for Alternate Functions (Products with 192-Kbyte to 768Kbyte Flash Memory and 80-Pin and 100-Pin Products with 128-Kbyte Flash Memory) (14/21)
Function Used
Function Name
I/O
Alternate Function Output
SAU and UARTA (excluding clock output from the UARTA)
Other than SAU and UARTA (including clock output from the UARTA)
P80 P80
Input
--
×
1
×
×
--
------------------
Output
--
N-ch open
--
drain output
0
0 0/1 (SCK10)/
--
(SCL10) = 1
1
0 0/1
(SCK10) Input
PIOR5 = 1 ×
1
×
×
--
------------------
Output
PIOR5 = 1 0/1 0
1
×
--
------------------
(SCL10) Output
PIOR5 = 1 0/1 0
1
×
--
------------------
P81 P81
Input
--
×
1
×
×
--
------------------
Output
--
0
0 0/1 (SDA10) = 1
--
N-ch open
--
drain output
1
0 0/1
(SI10) Input
PIOR5 = 1 ×
1
×
×
--
------------------
(RxD1) Input
PIOR5 = 1 ×
1
×
×
--
------------------
(SDA10) I/O
PIOR5 = 1 1
0
1
×
--
------------------
P82 P82
Input
--
×
1
×
×
--
------------------
Output
--
0
0 0/1
(SO10)/
--
N-ch open
(TxD1) = 1
--
1
0 0/1
drain output
(SO10) Output
PIOR5 = 1 0/1 0
1
×
--
------------------
(TxD1) Output
PIOR5 = 1 0/1 0
1
×
--
------------------
P83 P83
Input
--
×
1
×
×
--
------------------
Output
--
0
0 0/1 TxDA0 = 1
--
N-ch open
--
drain output
1
0 0/1
TxDA0 Output
--
0/1 0
1
×
--
------------------
P84 P84
Input
--
--
1
×
--
--
------------------
Output
--
--
0 0/1
--
--
RxDA0 Input
--
--
1
×
--
--
------------------
(INTP6) Input
PIOR5 = 1 --
1
×
--
--
------------------
P85 P85
Input
--
--
1
×
--
×
------------------
Output
--
--
0 0/1
--
CLKA0 = 0
CLKA0 Output
--
--
0
0
--
×
------------------
(INTP7) Input
PIOR5 = 1 --
1
×
--
×
------------------
P86 P86
Input
--
--
1
×
--
--
------------------
Output
--
--
0 0/1
--
--
(INTP8) Input
PIOR5 = 1 --
1
×
--
--
------------------
P87 P87
Input
--
--
1
×
--
--
------------------
Output
--
--
0 0/1
--
--
(INTP9) Input
PIOR5 = 1 --
1
×
--
--
------------------
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 241 of 1478
RL78/G23
CHAPTER 4 PORT FUNCTIONS
Pin Name PIOR POMxx PMxx Pxx 30-pin 32-pin 36-pin 40-pin 44-pin 48-pin 52-pin 64-pin 80-pin 100-pin 128-pin
Table 4 - 8 Examples of Register and Output Latch Settings for Alternate Functions (Products with 192-Kbyte to 768Kbyte Flash Memory and 80-Pin and 100-Pin Products with 128-Kbyte Flash Memory) (15/21)
Function Used
Function Name
I/O
P90 to P90 to Input
--
P94 P94
Output
--
P95 P95
Input
--
Output
--
SCK11 Input
--
Output
--
SCL11 Output
--
P96 P96
Input
--
Output
--
N-ch open
--
drain output
Alternate Function Output
SAU and UARTA (excluding clock output from the UARTA)
Other than SAU and UARTA (including clock output from the UARTA)
--1
×
--
--
--------------------
-- 0 0/1
--
--
--1
×
×
--
--------------------
-- 0 0/1 SCK11/
--
SCL11 = 1
--1
×
×
--
--------------------
--0
1
×
--
--------------------
--0
1
×
--
--------------------
×
1
×
×
--
--------------------
0
0 0/1 SDA11 = 1
--
1
0 0/1
SI11 SDA11 P97 P97
SO11
Input I/O Input Output Output
--
×
1
×
×
--
--------------------
--
1
0
1
×
--
--------------------
--
--1
×
×
--
--------------------
--
-- 0 0/1 SO11 = 1
--
--
--0
1
×
--
--------------------
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 242 of 1478
RL78/G23
CHAPTER 4 PORT FUNCTIONS
Pin Name PIOR
PMCAxx PMxx Pxx 30-pin 32-pin 36-pin 40-pin 44-pin 48-pin 52-pin 64-pin 80-pin 100-pin 128-pin
Table 4 - 8 Examples of Register and Output Latch Settings for Alternate Functions (Products with 192-Kbyte to 768Kbyte Flash Memory and 80-Pin and 100-Pin Products with 128-Kbyte Flash Memory) (16/21)
Function Used
Function Name
I/O
P100 P100
ANI20 P101 P101
P102 P102
TI06 TO06 P103 P103
TI14 TO14 P104 P104
TI15 TO15 P105 P105
TI16 TO16 P106 P106
TI17 TO17
Input
--
0
Output
--
0
Analog input
--
1
Input
--
--
Output
--
--
Input
--
--
Output
--
--
Input
PIOR0 = 0 --
Output
PIOR0 = 0 --
Input
--
--
Output
--
--
Input
--
--
Output
--
--
Input
--
--
Output
--
--
Input
--
--
Output
--
--
Input
--
--
Output
--
--
Input
--
--
Output
--
--
Input
--
--
Output
--
--
Input
--
--
Output
--
--
Alternate Function Output
SAU and Other than SAU
UARTA
and UARTA
(excluding clock (including clock
output from the output from the
UARTA)
UARTA)
1
×
--
--
----------------
0
0/1
--
--
1
×
--
--
----------------
1
×
--
--
------------------
0
0/1
--
--
1
×
--
×
------------------
0
0/1
--
TO06 = 0
1
×
--
×
------------------
0
0
--
×
------------------
1
×
--
×
--------------------
0
0/1
--
TO14 = 0
1
×
--
×
--------------------
0
0
--
×
--------------------
1
×
--
×
--------------------
0
0/1
--
TO15 = 0
1
×
--
×
--------------------
0
0
--
×
--------------------
1
×
--
×
--------------------
0
0/1
--
TO16 = 0
1
×
--
×
--------------------
0
0
--
×
--------------------
1
×
--
×
--------------------
0
0/1
--
TO17 = 0
1
×
--
×
--------------------
0
0
--
×
--------------------
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 243 of 1478
RL78/G23
CHAPTER 4 PORT FUNCTIONS
Table 4 - 8 Examples of Register and Output Latch Settings for Alternate Functions (Products with 192-Kbyte to 768Kbyte Flash Memory and 80-Pin and 100-Pin Products with 128-Kbyte Flash Memory) (17/21)
Pin Name PIOR POMxx
PMCAxx PMxx Pxx 30-pin 32-pin 36-pin 40-pin 44-pin 48-pin 52-pin 64-pin 80-pin 100-pin 128-pin
Function Used
Function Name
I/O
Alternate Function Output
SAU and Other than SAU
UARTA
and UARTA
(excluding clock (including clock
output from the output from the
UARTA)
UARTA)
P110 P110 Input
--
--
--
1
×
--
--
----------------
Output
--
--
--
0
0/1
--
--
(INTP10) Input
PIOR1 = 1 --
--
1
×
--
--
----------------
P111 P111 Input
--
--
--
1
×
--
--
----------------
Output
--
--
--
0
0/1
--
--
(INTP11) Input
PIOR1 = 1 --
--
1
×
--
--
----------------
P112 to P112 to Input
P114 P114
Output
--
--
--
1
×
--
--
--
--
0
0/1
--
--
------------------ --
--
P115 to P115 to Input
P117 P117
Output
--
--
0
1
×
--
--
--
0
0
0/1
--
--
------------------ --
--
ANI24 to Analog input
--
--
1
1
×
--
ANI26
--
------------------ --
P120 P120 Input
--
×
0
1
×
×
--
Output
--
0
0
0
0/1 TxDA1 = 1Note
--
N-ch open
--
drain output
1
0
0
0/1
ANI19 Analog input
--
×
1
1
×
×
IVCMP1 Analog input
--
×
1
1
×
×
EI120 Input
--
×
0
1
×
×
TxDA1 Output
--
0/1
0
0
1
×
--
--
--
--
-------- ---- -- --
Note
This setting is only applicable in the 44- to 52-pin products.
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CHAPTER 4 PORT FUNCTIONS
Table 4 - 8 Examples of Register and Output Latch Settings for Alternate Functions (Products with 192-Kbyte to 768Kbyte Flash Memory and 80-Pin and 100-Pin Products with 128-Kbyte Flash Memory) (18/21)
Pin Name
Function Used
Function Name
I/O
CMC
EXCLK, OSCSEL, EXCLKS, OSCSELS
PMxx XTSEL
Pxx
30- 32- 36- 40- 44- 48- 52- 64- 80- 100- 128pin pin pin pin pin pin pin pin pin pin pin
P121 P121
Input
00 xx / 10 xx / 11 xx xx 00 / xx 10 / xx 11
0
1
1Note
×
Output
00 xx / 10 xx / 11 xx xx 00 / xx 10 / xx 11
0
0
0/1
1Note
EI121
Input
00 xx / 10 xx / 11 xx xx 00 / xx 10 / xx 11
0
1
1Note
×
VBAT
Input
00 xx / 10 xx / 11 xx
0
0
1 ------
X1
--
01 xx
0
1
×
XT1
--
xx 01
1
1
×
----------------
P122 P122
Input
00 xx / 10 xx xx 00 / xx 10
0
1
1Note
×
Output
00 xx / 10 xx xx 00 / xx 10
0
0
0/1
1Note
EI122
Input
00 xx / 10 xx xx 00 / xx 10
0
1
1Note
×
X2
--
01 xx
0
1
×
XT2
--
xx 01
1
1
×
----------------
EXCLK Input
11 xx
0
1
×
EXCLKS Input
xx 11
1
1
×
----------------
P123 P123
Input
xx 00 / xx 10 / xx11
0
--
× ------
XT1
--
xx 01
0
--
× ------
P124 P124
Input
xx 00 / xx 10
0
--
× ------
XT2
--
xx 01
0
--
× ------
EXCLKS Input
xx 11
0
--
× ------
Note
This setting is only applicable in the 30- to 36-pin products.
Table 4 - 8 Examples of Register and Output Latch Settings for Alternate Functions (Products with 192-Kbyte to 768Kbyte Flash Memory and 80-Pin and 100-Pin Products with 128-Kbyte Flash Memory) (19/21)
Pin Name
Function Used
Function Name
I/O
PMxx
Pxx
30- 32- 36- 40- 44- 48- 52- 64- 80- 100- 128pin pin pin pin pin pin pin pin pin pin pin
P125 to P127
P125 to Input
P127
Output
1
×
--------------------
0
0/1
P130 P130 Output
--
0/1
----------
P137 P137 Input
--
×
EI137 Input
--
×
INTP0 Input
--
×
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CHAPTER 4 PORT FUNCTIONS
Pin Name PIOR POMxx
PMCAxx PMxx Pxx 30-pin 32-pin 36-pin 40-pin 44-pin 48-pin 52-pin 64-pin 80-pin 100-pin 128-pin
Table 4 - 8 Examples of Register and Output Latch Settings for Alternate Functions (Products with 192-Kbyte to 768Kbyte Flash Memory and 80-Pin and 100-Pin Products with 128-Kbyte Flash Memory) (20/21)
Function Used
Function Name
I/O
P140
P140
Input
Output
PCLBUZ0 Output
INTP6
Input
--
----
--
----
PIOR3 = 0 -- --
PIOR5 = 0 -- --
Note
Alternate Function Output
SAU and UARTA (excluding clock output from the UARTA)
Other than SAU and UARTA
(including clock output from the
UARTA)
1
×
--
×
----------
0 0/1
--
PCLBUZ0 = 0
0
0
--
×
----------
1
×
--
×
----------
P141
P141
Input
Output
PCLBUZ1 Output
INTP7
Input
--
----
1
×
--
----
0 0/1
PIOR4 = 0 -- --
0
0
PIOR5 = 0 -- --
1
×
Note
--
×
--------------
--
PCLBUZ1 = 0
--
×
--------------
--
×
--------------
P142 P142
Input
--
×
--
1
×
×
Output
--
N-ch open
--
drain output
0
--
0 0/1
SCK30/
SCL30 = 1
1
--
0 0/1
SCK30 Input
--
×
--
1
×
×
Output
--
0/1 --
0
1
×
SCL30
Output
--
0/1 --
0
1
×
P143 P143
Input
--
×
--
1
×
×
Output
--
0
--
0 0/1 SDA30 = 1
N-ch open
--
drain output
1
--
0 0/1
SI30
Input
--
×
--
1
×
×
RxD3
Input
--
×
--
1
×
×
SDA30 I/O
--
1
--
0
1
×
P144 P144
Input
--
×
--
1
×
×
Output
--
N-ch open
--
drain output
0
--
0 0/1
SO30/
TxD3 = 1
1
--
0 0/1
SO30
Output
--
0/1 --
0
1
×
TxD3
Output
--
0/1 --
0
1
×
P145 P145
Input
--
----
1
×
--
Output
--
----
0 0/1
--
TI07
Input
PIOR0 = 0 -- --
1
×
--
TO07
Output
PIOR0 = 0 -- --
0
0
--
P146 P146
Input
--
----
1
×
--
Output
--
----
0 0/1
--
(INTP4) Input
PIOR5 = 1 -- --
1
×
--
P147 P147
Input
--
--
0
1
×
--
Output
--
--
0
0 0/1
--
ANI18
Analog input
--
--
1
1
×
--
IVCMP0 Analog input
--
--
1
1
×
--
EI147
Input
--
--
0
1
×
--
--
----------------
--
--
----------------
--
----------------
--
----------------
--
----------------
--
--
----------------
--
----------------
--
----------------
--
----------------
--
-- -- × TO07 = 0 × × -- -- -- -- -- -- -- --
---------------- ---------------- ------------------
------------------ ------------------ --------
------------------
Note
This setting is only applicable in the 100- and 128-pin products.
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CHAPTER 4 PORT FUNCTIONS
Table 4 - 8 Examples of Register and Output Latch Settings for Alternate Functions (Products with 192-Kbyte to 768Kbyte Flash Memory and 80-Pin and 100-Pin Products with 128-Kbyte Flash Memory) (21/21)
Pin Name
Function Used
Function Name
I/O
PMCAxx PMCTxx PMxx
Pxx
30- 32- 36- 40- 44- 48- 52- 64- 80- 100- 128pin pin pin pin pin pin pin pin pin pin pin
P150 P150 Input
0
0
1
×
----------------
Output
0
0
0
0/1
ANI8
Analog input
1
0
1
×
----------------
TS30 I/O
0
1
1
×
----------------
P151 P151 Input
0
0
1
×
----------------
Output
0
0
0
0/1
ANI9
Analog input
1
0
1
×
----------------
TS31 I/O
0
1
1
×
----------------
P152 P152 Input
0
0
1
×
----------------
Output
0
0
0
0/1
ANI10 Analog input
1
0
1
×
----------------
TS32 I/O
0
1
1
×
----------------
P153 P153 Input
0
0
1
×
----------------
Output
0
0
0
0/1
ANI11 Analog input
1
0
1
×
----------------
TS33 I/O
0
1
1
×
----------------
P154 P154 Input
0
0
1
×
------------------
Output
0
0
0
0/1
ANI12 Analog input
1
0
1
×
------------------
TS34 I/O
0
1
1
×
------------------
P155 P155 Input
0
0
1
×
------------------
Output
0
0
0
0/1
ANI13 Analog input
1
0
1
×
------------------
TS35 I/O
0
1
1
×
------------------
P156 P156 Input
0
0
1
×
------------------
Output
0
0
0
0/1
ANI14 Analog input
1
0
1
×
------------------
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4.6
Cautions When Using Port Function
CHAPTER 4 PORT FUNCTIONS
4.6.1 Cautions on 1-bit manipulation instruction for port register n (Pn)
When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit. Therefore, it is recommended to rewrite the output latch before switching a port from input mode to output mode.
<Example> Explanation:
When P10 is an output port, P11 to P17 are input ports (all pins are at the high level), and the output latch value of port 1 is 00H, if the output of output port P10 is changed from low level to high level via a 1-bit manipulation instruction, the output latch value of port 1 becomes FFH. The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the output latch and pin state, respectively. A 1-bit manipulation instruction is executed in the following order in the RL78/G23.
<1> The Pn register is read in 8-bit units. <2> The targeted one bit is manipulated. <3> The Pn register is written in 8-bit units.
In step <1>, the output latch value (0) of P10, which is an output port, is read, while the states of P11 to P17, which are input ports, are read. If the states of P11 to P17 are high level at this time, the read value is FEH. The value is changed to FFH by the manipulation in <2>. FFH is written to the output latch by the manipulation in <3>.
Figure 4 - 18 One-Bit Manipulation Instruction (P10)
P10 P11 to P17 Port 1 output latch
00 00
Low-level output Pin state: High level 0 000
1-bit manipulation instruction (set1 P1.0)
P10
is executed for P10 bit.
P11 to P17
Port 1 output latch 1 111
High-level output Pin state: High level 11 11
1-bit manipulation instruction for P10 bit
<1> Port register 1 (P1) is read in 8-bit units. · In the case of P10, an output port, the value of the port output latch (0) is read. · In the case of P11 to P17, input ports, the pin state (1) is read.
<2> Set the P10 bit to 1. <3> Write the results of <2> to the output latch of port register 1 (P1) in 8-bit units.
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4.6.2 Notes on specifying the pin settings
For an output pin to which multiple functions are assigned, the output of the unused alternate functions must be set to the initial state of the pin so as to prevent conflicting outputs. This also applies to the functions assigned by using the peripheral I/O redirection register (PIOR). For details about the alternate function output, see 4.5 Register Settings When Using Alternate Function. No specific setting is required for input pins because the output of their alternate functions is disabled (the buffer output is Hi-Z).
Disabling the unused functions, including blocks that are only used for input or do not have I/O, is recommended for lower power consumption.
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CHAPTER 5 OPERATION STATE CONTROL
CHAPTER 5 OPERATION STATE CONTROL
The operating voltage, operating timing, and operating current of the internal circuit are optimized using flash operation modes. Select an appropriate flash operation mode in accord with the operating voltage range and clock frequencies of the MCU. The flash operation mode set by the option byte is selected for operation immediately after a reset is released. The mode can be changed by setting of the respective register.
5.1
Configuration of Operation State Control
Operation state control is supported by the following hardware blocks.
Table 5 - 1 Configuration of Operation State Control
Item
Configuration
Option byte
· Address of the user option byte: 000C2H
Control registers
· Flash operating mode select register (FLMODE) · Flash operating mode protect register (FLMWRP)
Figure 5 - 1 Block Diagram of Operation State Control
FLMWRP register
FLMODE register
FLMWEN
Enable/disable
MODE1
FLMODE setting
Set flash
operation mode
MODE0
Code flash memory Data flash memory
RAM
CPU Peripheral functions
Option byte (000C2H) CMODE1 CMODE0
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There are the following four flash operation modes. · HS (high-speed main) mode · LS (low-speed main) mode · LV (low-voltage main) mode · LP (low-power main) mode
The MCU can be operated efficiently by setting these flash operation modes according to MCU operating conditions. Table 5 - 2 lists the Features of Each Flash Operation Mode.
Table 5 - 2 Features of Each Flash Operation Mode
Flash Operation Mode
Recommended Operating Range
Description
HS (high-speed main) mode
1.6 V to 1.8 V 1 MHz to 4 MHz
High-speed CPU operation (at 24 MHz (max.)) is
(Rewriting of the flash memory is possible in this mode.
not possible.)
Suitable when CPU processing capacity is required.
1.6 V to 1.8 V 1 MHz to 2 MHz
1.8 V to 5.5 V 1 MHz to 32 MHz
LS (low-speed main) mode 1.6 V to 1.8 V 1 MHz to 4 MHz
The operating current and CPU operation processing
(Rewriting of the flash memory is (at 24 MHz (max.)) are wellbalanced in this mode.
not possible.)
1.6 V to 1.8 V 1 MHz to 2 MHz
1.8 V to 5.5 V 1 MHz to 24 MHz
LP (low-power main) mode 1.6 V to 5.5 V 1 MHz to 2 MHz
The CPU operates at 1 MHz to 2 MHz in this mode.
(Rewriting of the flash memory is Low operating current is realized at 1 MHz to 2 MHz.
not possible.)
SUB mode
1.6 V to 5.5 V
32.768 kHz (Rewriting of the flash memory is not possible.)
CPU operation is driven by the sub-system clock.Note Setting the system clock control register (CKC) to 1 places the CPU in this mode.
Note
The sub-system clock can be derived from the subsystem clock X (fSX) or the low-speed on-chip oscillator (fIL).
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CHAPTER 5 OPERATION STATE CONTROL
5.2
Registers to Control the Operation State Control
The following registers are used to control the operation state control.
· Flash operating mode select register (FLMODE) · Flash operating mode protect register (FLMWRP)
5.2.1 Flash operating mode select register (FLMODE)
The FLMODE is an 8-bit register used to control flash operation modes. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Note that the value of this register cannot be changed when FLMWEN in the flash operation mode protect register (FLMWRP) is 0. The settings of the MODE1 and MODE0 bits are updated to those of CMODE1 and CMODE0 in the option byte at address 000C2H following a reset.
Figure 5 - 2 Format of Flash operating mode select register (FLMODE)
Address: After reset: R/W:
F00AAH 40H/80H/C0HNote R/W
Symbol <7>
<6>
5
4
3
2
1
0
FLMODE MODE1 MODE0
0
0
0
0
0
0
MODE1 MODE0
Selection of flash operation mode
0
0
Setting prohibited
0
1
LP (low-power main) mode
(Selectable when 1 MHz fCLK 2 MHz in LS mode)
1
0
LS (low-speed main) mode
(Selectable when 1 MHz fCLK 24 MHz or in LP mode)
1
1
HS (high-speed main) mode
(Selectable when in LS mode)
Note
The initial value of the FLMODE register is set to the value of the MODE1 and MODE0 bits updated with the set value of the CMODE1 and CMODE0 bits in the option byte (address: 000C2H).
Caution 1.
Caution 2.
Caution 3. Caution 4.
The value of the FLMODE register can be changed when the FLMWEN bit in the flash operation mode protect register (FLMWRP) is 1. After the value of the FLMODE register is changed, set the FLMWEN bit to 0. Operation is in SUB mode when the setting of the CSS bit in the system clock control register (CKC) is 1 (operation of the CPU and peripheral functions is driven by the subsystem clock) regardless of the setting of the MODE1 and MODE0 bits. Do not change the value of the MODE1 and MODE0 bits using the DTC or SMS. When changing the flash operation mode, make sure that operation is possible within the voltage range and operating frequency range in the changed flash operation mode before changing the mode.
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CHAPTER 5 OPERATION STATE CONTROL
Caution 5. When the flash operation mode is changed by the MODE1 and MODE0 bits, the CPU enters a wait state for the following time until the mode changes. Interrupt requests are held pending during this wait period.
Flash Operation Mode Change LS (low-speed main) mode HS (high-speed main) mode LP (low-power main) mode LS (low-speed main) mode LS (low-speed main) mode LP (low-power main) mode HS (high-speed main) mode LS (low-speed main) mode
Change Time 225 cyclesNote 10 cyclesNote 10 cyclesNote 30 cyclesNote
Note
The cycle of the CPU/peripheral hardware clock (fCLK)
Caution 6. When rewriting the FLMODE register, insert one or more clock cycles after rewriting the FLMODE register and before writing to this register. Do not write to the FLMODE register successively.
Caution 7. Do not change the FLMODE register when rewriting the flash memory. Caution 8. Writing new values to the FLMODE register should be done while the snooze mode sequencer is
stopped, that is, while the setting of the SMSSTART bit is 0, or the settings of the SMSSTAT bit and the SMSTRGWAIT bit are 0 and 1, respectively. Caution 9. Before changing the flash operating mode, set the DFLEN bit in the data flash control register (DFLCTL) to 1 to enable access to the data flash memory. Caution 10. Before rewriting the contents of the code flash memory or data flash memory area by selfprogramming, be sure to place the MCU in HS (high-speed main) or LS (low-speed main) mode.
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CHAPTER 5 OPERATION STATE CONTROL
5.2.2 Flash operating mode protect register (FLMWRP)
The FLMWRP is an 8-bit register used to control access to the flash operation mode select register. This register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 5 - 3 Format of Flash operating mode protect register (FLMWRP)
Address: After reset: R/W:
F00ABH 00H R/W
Symbol
7
6
5
4
3
2
1
<0>
FLMWRP
0
0
0
0
0
0
0
FLMWEN
FLMWEN
Control of flash operation mode select register (FLMODE)
0
Rewriting the FLMODE register is disabled.
1
Rewriting the FLMODE register is enabled.
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CHAPTER 5 OPERATION STATE CONTROL
5.3
Initial Setting of Flash Operation Modes
The option byte (000C2H) is used to set the initial state of flash operation mode and the high-speed on-chip oscillator after a reset is released. Set an appropriate flash operation mode according to the VDD voltage and the high-speed on-chip oscillator frequency at a reset release. When a reset is released, the value of CMODE1 and CMODE0 is updated in MODE1 and MODE0 in the flash operation mode select register (FLMODE) and the value of FRQSEL3 to FRQSEL0 is updated in the high-speed onchip oscillator frequency select register (HOCODIV). For details on the option byte (000C2H), see CHAPTER 32 OPTION BYTES.
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5.4
Transitions between Flash Operation Modes
Setting of CMODE1 and CMODE0 in the option byte (000C2H) determines the initial flash operation mode immediately after a reset is released. The initial state can be selected from among the HS (high-speed main) mode, LS (low-speed main) mode, or LP (low-power main) mode. The value of CMODE1 and CMODE0 is updated in the MODE1 and MODE0 bits in the flash operation mode select register (FLMODE). After that, the flash operation mode can be changed by changing the value of the FLMODE register during CPU operation. Setting the CSS bit in the CKC register enables automatically placing the MCU in SUB mode.
Figure 5 - 4 State Transitions between Flash Operation Modes
HS (high-speed main) mode
FLMODE register MODE1 = 1, MODE0 = 1
Operating conditions: fCLK = 1 MHz to 2 MHz
VDD = 1.6 V to 5.5 V fCLK = 1 MHz to 4 MHz VDD = 1.6 V to 5.5 VNote fCLK = 1 MHz to 32 MHz VDD = 1.8 V to 5.5 V
Option byte (000C2H) CMODE1 = 1, CMODE0 = 1
MODE0 = 0
MODE0 = 1
Release of a reset
Option byte (000C2H) CMODE1 = 1, CMODE0 = 0
LS (low-speed main) mode
FLMODE register MODE1 = 1, MODE0 = 0
Operating conditions: fCLK = 1 MHz to 2 MHz
VDD = 1.6 V to 5.5 V fCLK = 1 MHz to 4 MHz VDD = 1.6 V to 5.5 VNote fCLK = 1 MHz to 24 MHz VDD = 1.8 V to 5.5 V
Option byte (000C2H) CMODE1 = 0, CMODE0 = 1
MODE1 = 0 MODE0 = 1
MODE1 = 1 MODE0 = 0
LP (low-power main) mode
CSS = 0 CSS = 1
CSS = 0 CSS = 1
SUB mode
FLMODE register MODE1 = x, MODE0 = x
Operating conditions: fCLK = 32.768 kHz
VDD = 1.6 V to 5.5 VNote
CSS = 0 CSS = 1
FLMODE register MODE1 = 0, MODE0 = 1
Operating conditions: fCLK = 1 MHz to 2 MHz
VDD = 1.6 V to 5.5 VNote
Note
Rewriting of the flash memory is not possible.
Caution
When a reset is applied while the MCU operates, operation always starts in the flash operation mode set by the option byte after a reset release. Therefore, make sure that operation does not start outside the operating voltage range when a reset is released by setting the LVD detection voltage to at least the operating voltage range of the flash operation mode set in the option byte.
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CHAPTER 5 OPERATION STATE CONTROL
5.5
Details of Flash Operation Modes
5.5.1 Details of HS (high-speed main) mode
HS (high-speed main) mode is suitable for applications that require CPU high-speed processing. HS mode can be operated immediately after a reset release. Also, this mode can be entered from LS (low-speed main) mode. The suitable operating range in HS mode is when the supply voltage is 1.8 V VDD 5.5 V and the operating frequency is 24 MHz < fCLK 32 MHz. When 24 MHz or lower is used for operation, another mode can be used as the suitable flash operation mode.
Figure 5 - 5 Operating Range in HS Mode
32 MHz
24 MHz
CPU/peripheral hardware clock (fCLK)
4 MHz
2 MHz
1 MHz 0.5 MHz
1.6 V
1.8 V Supply voltage (VDD)
5.5 V
: Operating range where HS mode is suitable : Operating range where another mode is suitable : Operating range over which rewriting of the flash memory is not possible
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CHAPTER 5 OPERATION STATE CONTROL
5.5.2 Details of LS (low-speed main) mode
LS (low-speed main) mode supports both CPU processing capacity and operating voltage performance, suitable for applications that require low-power consumption at 2 to 24 MHz. LS mode can be operated immediately after a reset release. Also, this mode can be entered from HS (high-speed main) mode, or LP (low-power main) mode. When entering from HS mode to LS mode, make sure that the operating frequency is 1 MHz fCLK 24 MHz. The suitable operating range in LS mode is when the supply voltage is 1.8 V VDD 5.5 V and the operating frequency is 2 MHz < fCLK 24 MHz, and when the supply voltage is 1.6 V VDD < 1.8 V and the operating frequency is 2 MHz < fCLK 4 MHzNote.
Note
When rewriting of flash memory is required, the operating frequency should be in the range of 1 MHz fCLK 2 MHz.
Figure 5 - 6 Operating Range in LS Mode
32 MHz
24 MHz
CPU/peripheral hardware clock (fCLK)
4 MHz
2 MHz
1 MHz 0.5 MHz
1.6 V
1.8 V Supply voltage (VDD)
5.5 V
: Operating range where LS mode is suitable : Operating range where another mode is suitable : Operating range over which rewriting of the flash memory is not possible
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CHAPTER 5 OPERATION STATE CONTROL
5.5.3 Details of LP (low-power main) mode
In LP (low-power main) mode, the CPU operates with a low voltage and at a frequency from 1 MHz to 2 MHz. LP mode can be entered from LS (low-speed main) mode. When entering from LS mode to LP mode, make sure the operating frequency is in the range of 1 MHz fCLK 2 MHz. The suitable operating range in LP mode is when the supply voltage is 1.6 V VDD 5.5 V and the operating frequency is 1 MHz fCLK 2 MHz. When rewriting of flash memory is required, place the CPU in LS (low-speed main) mode.
Figure 5 - 7 Operating Range in LP Mode
32 MHz
24 MHz
CPU/peripheral hardware clock (fCLK)
4 MHz
2 MHz
1 MHz 0.5 MHz
1.6 V
1.8 V Supply voltage (VDD)
5.5 V
: Operating range where LP mode is suitable : Operating range where another mode is suitable : Operating range over which rewriting of the flash memory is not possible
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5.5.4 Details on SUB mode
In SUB mode, the CPU operates at a frequency of 32.768 kHz. Transition to SUB mode is possible from HS (high-speed main) mode, LS (low-speed main) mode, or LP (low-power main) mode. Setting the CSS bit in the system clock control register (CKC) places the CPU in SUB mode. Rewriting of the flash memory is not possible in SUB mode. When rewriting of flash memory is required, place the CPU in HS (high-speed main) mode or LS (low-speed main) mode.
Figure 5 - 8 Operating Range in SUB Mode
32 MHz
24 MHz
CPU/peripheral hardware clock (fCLK)
1 MHz
0.5 MHz 32.768kHz
1.6 V
1.8 V Supply voltage (VDD)
5.5 V
: Operating range where SUB mode is suitable : Operating range where another mode is suitable : Operating range over which rewriting of the flash memory is not possible
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CHAPTER 6 CLOCK GENERATOR
CHAPTER 6 CLOCK GENERATOR
6.1
Functions of Clock Generator
The clock generator generates clocks to be supplied to the CPU and peripheral hardware. The following kinds of system clocks and clock oscillators are selectable.
(1) Main system clock <1> X1 oscillator
This circuit oscillates a clock of fX = 1 to 20 MHz by connecting a resonator to the X1 pin and X2 pin. Oscillation can be stopped by executing a STOP instruction or setting of the MSTOP bit (bit 7 of the clock operation status control register (CSC)). <2> High-speed on-chip oscillator The frequency of oscillation can be selected from among fIH = 32, 24, 16, 12, 8, 6, 4, 3, 2, or 1 MHz (typ.) by using an option byte (000C2H). After release from the reset state, the CPU always starts operating with this high-speed on-chip oscillator clock. Oscillation can be stopped by executing a STOP instruction or setting of the HIOSTOP bit (bit 0 of the CSC register). The frequency specified by using the option byte can be changed by using the high-speed on-chip oscillator frequency select register (HOCODIV). For details about the frequency, see Figure 6 - 11 Format of High-Speed On-Chip Oscillator Frequency Select Register (HOCODIV). The frequencies that can be specified for the high-speed on-chip oscillator by using the option byte and the highspeed on-chip oscillator frequency select register (HOCODIV) are shown below.
Oscillation Frequency (MHz)
Power Supply Voltage
1
2
3
4
6
8
12
16
24
32
1.8 V VDD 5.5 V
1.6 V VDD 5.5 V
--
--
--
--
--
--
--
--
<3> Middle-speed on-chip oscillator The frequency of oscillation can be selected from among fIM = 4, 2, or 1 MHz (typ.) by using the MOCODIV bits
(bits 0, 1 of the MOCODIV register). Oscillation can be stopped by executing a STOP instruction or clearing of the
MIOEN bit (bit 1 of the CSC register).
An external main system clock (fEX = 1 to 20 MHz) can also be supplied from the EXCLK/X2/P122 pin. External main system clock input can be disabled by executing a STOP instruction or setting of the MSTOP bit.
As the main system clock, a high-speed system clock (X1 clock or external main system clock) or a main on-chip oscillator clock (high-speed on-chip oscillator clock or middle-speed on-chip oscillator clock) can be selected by setting of the MCM0 and MCM1 bits (bits 4 and 0 of the system clock control register (CKC)).
Note that the usable frequency range of the CPU/peripheral hardware clock depends on the flash operation mode and VDD power supply voltage settings.
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When the main system clock is to be used as the CPU/peripheral hardware clock, select the frequency of the main system clock to suit the flash operation mode specified in the CMODE0 and CMODE1 bits of an option byte (000C2H) (see CHAPTER 32 OPTION BYTES) or the flash operating mode select register (FLMODE).
(2) Subsystem clock <1> XT1 oscillator
This circuit oscillates a clock of fXT = 32.768 kHz by connecting a 32.768-kHz resonator to XT1 pin and XT2 pin. Oscillation can be stopped by setting the XTSTOP bit (bit 6 of the clock operation status control register (CSC)).
An external subsystem clock (fEXS = 32.768 kHz) can also be supplied from the EXCLKS/XT2/P124 pin. External subsystem clock input can be disabled by the setting of the XTSTOP bit.
<2> Low-speed on-chip oscillator This circuit oscillates a clock of fIL = 32.768 kHz (typ.).
The low-speed on-chip oscillator operates when either of the following conditions is met. The value of one or more of the following bits is 1: bit 4 (WDTON) of an option byte (000C0H), bit 4 (WUTMMCK0)
of the subsystem clock supply mode control register (OSMC), and bit 0 (SELLOSC) of the subsystem clock select register (CKSEL) fIL is selected as the source clock for use in waiting by the SNOOZE mode sequencer. However, if a HALT or STOP instruction is executed when WDTON = 1, WUTMMCK0 = 0, SELLOSC = 0 and bit 0 (WDSTBYON) of the option byte (000C0H) is 0, this oscillator stops oscillating.
Remark
fX: fIH: fIM: fEX: fXT: fEXS: fIL:
X1 clock oscillation frequency High-speed on-chip oscillator clock frequency (32 MHz max.) Middle-speed on-chip oscillator clock frequency (4 MHz max.) External main system clock frequency XT1 clock oscillation frequency External subsystem clock frequency Low-speed on-chip oscillator clock frequency
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6.2
Configuration of Clock Generator
The clock generator includes the following hardware.
Table 6 - 1 Configuration of Clock Generator
Item
Configuration
Control registers
Clock operation mode control register (CMC) System clock control register (CKC) Clock operation status control register (CSC) Oscillation stabilization time counter status register (OSTC) Oscillation stabilization time select register (OSTS) Peripheral enable registers 0, 1 (PER0, PER1) Subsystem clock supply mode control register (OSMC) Subsystem clock select register (CKSEL) High-speed on-chip oscillator frequency select register (HOCODIV) Middle-speed on-chip oscillator frequency select register (MOCODIV) High-speed system clock division register (MOSCDIV) High-speed on-chip oscillator trimming register (HIOTRM) Middle-speed on-chip oscillator trimming register (MIOTRM) Low-speed on-chip oscillator trimming register (LIOTRM) Standby mode release setting register (WKUPMD)
Oscillators
X1 oscillator XT1 oscillator High-speed on-chip oscillator Middle-speed on-chip oscillator Low-speed on-chip oscillator
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CHAPTER 6 CLOCK GENERATOR
<R>
Internal bus
Option byte (000C2H) FRQSEL0 to FRQSEL3
Clock operation mode control register (CMC)
High-speed system clock division register (MOSCDIV)
System clock control register (CKC)
High-speed on-chip oscillator fIHP
(32 MHz (typ.)) (24 MHz (typ.))
(16 MHz (typ.)) (12 MHz (typ.))
(8 MHz (typ.)) (6 MHz (typ.)) fIH
(4 MHz (typ.)) (3 MHz (typ.))
(2 MHz (typ.)) (1 MHz (typ.))
X1/P121
X2/EXCLK/ P122
Middle-speed on-chip oscillator fIM
(4 MHz (typ.)) (2 MHz (typ.))
fIMP
(1 MHz (typ.))
X1 oscillator
Crystal/ceramic oscillation
External input clock
fX fMX fEX fMXP
fMX/24 fMX/23 fMX/22 fMX/2 fMX
Prescaler Selector
Selector Selector
Main system clock source selection
fOCO
fMAIN
CPU clock and peripheral fCLK
hardware clock source
selection
32-bit interval timer Serial interfaces UARTA0 and UARTA1
CPU and each peripheral function 32-bit interval timer Serial interfaces UARTA0 and UARTA1
Clock output/buzzer output controller
32-bit interval timer Serial interfaces UARTA0 and UARTA1
Low-speed on-chip oscillator
(32.768 kHz fIL (typ.))
Subsystem clock source selection
fSUB WUTMMCK0
Watchdog timer
Selector Selector
Selector
XT1/P123
XT2/EXCLKS/ P124
XT1 oscillator
fSX
Crystal oscillation
External input clock
fXT fSXR
fEXS
High-speed on-chip oscillator trimming register
(HIOTRM)
fSXP
Subsystem clock select register (CKSEL)
Frequency division
fRTCCK
Clock output/buzzer output controller 32-bit interval timer Serial interfaces UARTA0 and UARTA1 Remote control signal receiver
Realtime clock
Clock operation mode control register (CMC)
Low-speed on-chip oscillator trimming register (LIOTRM)
High-speed on-chip oscillator frequency select
register (HOCODIV)
Middle-speed on-chip Middle-speed on-chip
oscillator trimming oscillator frequency select
register (MIOTRM)
register (MOCODIV)
RTC128EN
Subsystem clock supply mode control register (OSMC)
Internal bus
<R>
Remark
fX:
X1 clock oscillation frequency
fEX: External main system clock frequency
fIH:
High-speed on-chip oscillator clock frequency (32 MHz max.)
fIHP: High-speed on-chip oscillator peripheral clock frequency
(32 MHz when FRQSEL3 = 1, 24 MHz when FRQSEL3 = 0)
fIM: Middle-speed on-chip oscillator clock frequency (4 MHz max.)
fIMP: Middle-speed on-chip oscillator peripheral clock frequency (4 MHz)
fMX: High-speed system clock frequency
fMXP: High-speed peripheral clock frequency
fMAIN: Main system clock frequency
fXT: XT1 clock oscillation frequency
fEXS: External subsystem clock frequency
fSX: Subsystem clock X frequency
fSXR: Subsystem clock XR frequency
fRTCCK: Operating clock for the realtime clock controller
fSXP: Low-speed peripheral clock frequency
fSUB: Subsystem clock frequency
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fCLK: fIL: fOCO:
CPU/peripheral hardware clock frequency Low-speed on-chip oscillator clock frequency Main on-chip oscillator clock frequency (fIH or fIM)
CHAPTER 6 CLOCK GENERATOR
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6.3
Registers to Control the Clock Generator
The following registers are used to control the clock generator.
· Clock operation mode control register (CMC) · System clock control register (CKC) · Clock operation status control register (CSC) · Oscillation stabilization time counter status register (OSTC) · Oscillation stabilization time select register (OSTS) · Peripheral enable registers 0, 1 (PER0, PER1) · Subsystem clock supply mode control register (OSMC) · Subsystem clock select register (CKSEL) · High-speed on-chip oscillator frequency select register (HOCODIV) · Middle-speed on-chip oscillator frequency select register (MOCODIV) · High-speed system clock division register (MOSCDIV) · High-speed on-chip oscillator trimming register (HIOTRM) · Middle-speed on-chip oscillator trimming register (MIOTRM) · Low-speed on-chip oscillator trimming register (LIOTRM) · Standby mode release setting register (WKUPMD)
Caution
Which registers and bits are included depends on the product. Be sure to set bits that are not mounted in a product to their initial values.
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6.3.1 Clock operation mode control register (CMC)
This register is used to set the operation mode of the X1/P121, X2/EXCLK/P122, XT1/P123, and XT2/EXCLKS/P124 pins, and to select the gain of the oscillator. The CMC register can be written only once by an 8-bit memory manipulation instruction after release from the reset state. This register can be read by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 6 - 2 Format of Clock Operation Mode Control Register (CMC)
Address: After reset: R/W:
FFFA0H 00H R/W
Symbol CMC
7
EXCLK
6 OSCSEL
5
EXCLKS
Note 1
4
OSCSELS
Note 1
3
XTSEL
Notes 1, 2
2
AMPHS1
Note 1
1
AMPHS0
Note 1
0 AMPH
Products with 30 to 36 pins
XTSEL
Note 1
EXCLK
OSCSEL
EXCLKS
Note 1
OSCSELS
Note 1
System clock pin operation mode
X1/P121/ XT1 pin
X2/EXCLK/ P122/XT2/ EXCLKS pin
0
0
0
0
0
Port mode
Port
Port
0
0
1
0
0
X1 oscillation
Crystal/ceramic resonator
mode
connection
0
1
0
0
0
Port mode
Port
Port
0
1
1
0
0
External clock
Port
input mode
External clock EXCLK input
1
0
0
0
0
Port mode
Port
Port
1
0
0
0
1
XT1 oscillation Crystal resonator connection
mode
1
0
0
1
0
Port mode
Port
Port
1
0
0
1
1
External clock
Port
input mode
External clock EXCLKS input
Other than above
Setting prohibited
Products with 40 to 128 pins
EXCLK
OSCSEL
High-speed system clock pin operation mode
0
0
Port mode
0
1
X1 oscillation mode
1
0
Port mode
1
1
External clock input mode
X1/P121 pin
X2/EXCLK/P122 pin
Port
Port
Crystal/ceramic resonator connection
Port
Port
Port
External clock input
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EXCLKS
Note 1
0 0 1 1
OSCSELS
Note 1
Subsystem clock pin operation mode
0
Input port mode
1
XT1 oscillation mode
0
Input port mode
1
External clock input mode
XT1/P123 pin
XT2/EXCLKS/P124 pin
Input port
Input port
Crystal resonator connection
Input port
Input port
Input port
External clock input
AMPHS1
Note 1
0 0 1 1
AMPHS0
Note 1
0 1 0 1
Selection of the oscillation mode of the XT1 oscillator
Low power consumption oscillation 1 (default)Note 3 Normal oscillation Low power consumption oscillation 2Note 3 Low power consumption oscillation 3Note 3
AMPH
Control of the X1 clock oscillation frequency
0
1 MHz fX 10 MHz
1
10 MHz < fX 20 MHz
Note 1. Note 2. Note 3.
The EXCLKS, OSCSELS, XTSEL, AMPHS1, and AMPHS0 bits are reset only by a power-on reset; they retain the values when a reset caused by another source occurs. The XTSEL bit can be written only in the products with 30 to 36 pins. Be sure to set this bit to 0 in the products with 40 to 128 pins. The gain and operating current of the XT1 clock oscillator decrease in the following order: low power consumption oscillation 1 > low power consumption oscillation 2 > low power consumption oscillation 3.
Caution 1. The CMC register can be written only once by an 8-bit memory manipulation instruction after release from the reset state. Even if you intend to use the CMC register with its initial value (00H), be sure to write 00H to the register after release from the reset state as a precaution against malfunctions (since returning the value to 00H after erroneously having written a value other than 00H to it is not possible).
Caution 2. After release from the reset state, set the CMC register before X1 or XT1 oscillation is started by setting the clock operation status control register (CSC).
Caution 3. Be sure to set the AMPH bit to 1 if the X1 clock oscillation frequency exceeds 10 MHz. Caution 4. Make the settings of the AMPH, AMPHS1, and AMPHS0 bits while fIH is selected as fCLK after release
from the reset state (before fCLK is switched to fMX or fSUB). Caution 5. Count the oscillation stabilization time of fXT by software. Caution 6. The XT1 oscillator is a circuit with low amplification in order to achieve low power consumption. Note
the following points when designing the circuit. · Pins and circuit boards include parasitic capacitance. Therefore, perform oscillation evaluation using
a circuit board to be actually used and confirm that there are no problems.
· When using low power consumption oscillation 2 (AMPHS1, AMPHS0 = 1, 0) or low power
consumption oscillation 3 (AMPHS1, AMPHS0 = 1, 1) as the XT1 oscillator mode, sufficiently evaluate
the resonator as described in 6.7 Resonator and Oscillator Constants, before using it in either of
these modes.
· Make the wiring runs between the XT1 and XT2 pins and the resonator as short as possible to
minimize the parasitic capacitance and wiring resistance. Take care with this particularly when low
power consumption oscillation 2 (AMPHS1, AMPHS0 = 1, 0) or low power consumption oscillation 3
(AMPHS1, AMPHS0 = 1, 1) is selected.
· Configure the circuit of the circuit board, using material with little parasitic capacitance and wiring
resistance.
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· Place a ground pattern that has the same potential as VSS as much as possible near the XT1 oscillator.
· Be sure that the signal lines between the XT1 and XT2 pins and the resonator do not cross the other signal lines. Do not route the wiring near a signal line through which a strong fluctuating current flows.
· The impedance between the XT1 and XT2 pins may drop and oscillation may be disturbed due to moisture absorption of the circuit board in a high-humidity environment or dew condensation on the board. When using the circuit board in such an environment, take measures to damp-proof the circuit board, such as by coating.
· When coating the circuit board, use material that does not cause capacitance or leakage between the XT1 and XT2 pins.
Caution 7. When selecting the XT1 oscillation mode for the P121/X1/XT1 and P122/X2/EXCLK/XT2/EXCLKS pins while the value of the XTSEL bit is 1 in a product with 30 to 36 pins, make sure that VDD is no less than 2.4 V.
Remark fX: X1 clock oscillation frequency
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6.3.2 System clock control register (CKC)
This register is used to select a CPU/peripheral hardware clock and a main system clock. The CKC register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 6 - 3 Format of System Clock Control Register (CKC)
Address: After reset: R/W:
FFFA4H 00H R/WNote 1
Symbol
<7>
<6>
<5>
<4>
3
CKC CLS
CSS
MCS
MCM0
0
2
<1>
<0>
0
MCS1
MCM1
CLS
0 1
State of the CPU/peripheral hardware clock (fCLK) Main system clock (fMAIN) Subsystem clock (fSUB)
CSSNote 2
Selection of the CPU/peripheral hardware clock (fCLK)
0
Main system clock (fMAIN)
1
Subsystem clock (fSUB)
MCS 0 1
State of the main system clock (fMAIN) Main on-chip oscillator clock (fOCO) High-speed system clock (fMX)
MCM0
Note 2
0 1
Main system clock (fMAIN) operation control
Selects the main on-chip oscillator clock (fOCO) as the main system clock (fMAIN) Selects the high-speed system clock (fMX) as the main system clock (fMAIN)
MCS1 0 1
State of the main on-chip oscillator clock (fOCO) High-speed on-chip oscillator clock Middle-speed on-chip oscillator clock
MCM1
Note 2
Main on-chip oscillator clock (fOCO) operation control
0
High-speed on-chip oscillator clock
1
Middle-speed on-chip oscillator clock
Note 1. Note 2.
Bits 7, 5, and 1 are read-only. Changing the value of the MCM0 and MCM1 bits is prohibited while the CSS bit is set to 1.
Remark
fIH: High-speed on-chip oscillator clock frequency (32 MHz max.) fMX: High-speed system clock frequency fMAIN: Main system clock frequency fSUB: Subsystem clock frequency fOCO: Main on-chip oscillator clock frequency (fIH or fIM)
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Caution 1. Be sure to set bits 3 and 2 of the CKC register to 0. Caution 2. The clock set by the CSS bit is supplied to the CPU and peripheral hardware. If the CPU clock is
changed, therefore, the clock supplied to peripheral hardware (except the realtime clock, clock output/buzzer output, 32-bit interval timer, and watchdog timer) is also changed at the same time. Consequently, stop each peripheral function when changing the CPU/peripheral hardware clock. Caution 3. If the subsystem clock is used as the peripheral hardware clock, the operations of the A/D converter and serial interface IICA are not guaranteed. For the operating characteristics of the peripheral hardware, refer to the chapters describing each item of peripheral hardware as well as CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
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6.3.3 Clock operation status control register (CSC)
This register is used to control the operations of the high-speed system clock, high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock, and subsystem clock (except the low-speed on-chip oscillator clock). The CSC register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is C0H following a reset.
Figure 6 - 4 Format of Clock Operation Status Control Register (CSC)
Address: After reset: R/W:
FFFA1H C0H R/W
Symbol
<7>
<6>
5
4
3
2
<1>
<0>
CSC MSTOP XTSTOPNote
0
0
0
0
MIOEN HIOSTOP
MSTOP 0 1
High-speed system clock operation control
X1 oscillation mode
External clock input mode
Port mode
The X1 oscillator runs.
An external clock signal on I/O port
the EXCLK pin is effective.
The X1 oscillator is stopped. An external clock signal on
the EXCLK pin is ineffective.
XTSTOP
Note
XT1 oscillation mode
Subsystem clock operation control External clock input mode
Port mode
0
The XT1 oscillator runs.
An external clock signal on Input port
the EXCLKS pin is effective.
1
The XT1 oscillator is stopped. An external clock signal on
the EXCLKS pin is ineffective.
MIOEN 0 1
Middle-speed on-chip oscillator clock operation control The middle-speed on-chip oscillator is stopped. The middle-speed on-chip oscillator runs.
HIOSTOP
High-speed on-chip oscillator clock operation control
0
The high-speed on-chip oscillator runs.
1
The high-speed on-chip oscillator is stopped.
Note
The XTSTOP bit is only initialized after a reset by a power-on reset; it retains its value when a reset caused by another source occurs.
Caution 1. After release from the reset state, set the clock operation mode control register (CMC) before setting the CSC register.
Caution 2. Set the oscillation stabilization time select register (OSTS) before setting the MSTOP bit to 0 after release from the reset state. Note that if the OSTS register is being used with its default settings, the OSTS register is not required to be set here.
Caution 3. When starting X1 oscillation by using the MSTOP bit, check the oscillation stabilization time of the X1 clock by using the oscillation stabilization time counter status register (OSTC).
Caution 4. When starting XT1 oscillation by using the XTSTOP bit, include code to wait for oscillation of the subsystem clock to become stable.
Caution 5. Do not stop the clock selected for the CPU/peripheral hardware clock (fCLK) with the CSC register.
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Caution 6. When stopping the clock, confirm the conditions before clock oscillation is stopped. For details on how to stop the clock, see Table 6 - 8 Conditions Before the Clock Oscillation is Stopped and Flag Settings.
6.3.4 Oscillation stabilization time counter status register (OSTC)
This register indicates the counter value by the X1 clock oscillation stabilization time counter. The X1 clock oscillation stabilization time can be checked in the following cases:
· If the X1 clock starts oscillation while the main on-chip oscillator clock or subsystem clock is in use as the CPU clock. · If entry to and then release from the STOP mode proceed while the main on-chip oscillator clock is in use as the CPU
clock and the X1 clock is oscillating.
The OSTC register can be read by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset, STOP instruction, or the MSTOP bit (bit 7 of the clock operation status control register (CSC)) being set to 1.
Remark
The oscillation stabilization time counter starts counting in the following cases. · When oscillation of the X1 clock starts (EXCLK, OSCSEL = 0, 1 MSTOP = 0) · When the STOP mode is released
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Figure 6 - 5 Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: After reset: R/W:
FFFA2H 00H R
Symbol
7
OSTC MOST8
6 MOST9
5 MOST10
4 MOST11
3 MOST13
2 MOST15
1 MOST17
0 MOST18
MOS MOS MOS MOS MOS MOS MOS MOS T8 T9 T10 T11 T13 T15 T17 T18
State of the oscillation stabilization time fX = 10 MHz fX = 20 MHz
0
0
0
0
0
0
0
0 Less than Less than
28/fX
25.6 µs
Less than 12.8 µs
1
0
0
0
0
0
0
0 28/fX min. 25.6 µs min. 12.8 µs min.
1
1
0
0
0
0
0
0 29/fX min. 51.2 µs min. 25.6 µs min.
1
1
1
0
0
0
0
0 210/fX min. 102 µs min. 51.2 µs min.
1
1
1
1
0
0
0
0 211/fX min. 204 µs min. 102 µs min.
1
1
1
1
1
0
0
0 213/fX min. 819 µs min. 409 µs min.
1
1
1
1
1
1
0
0 215/fX min. 3.27 ms min. 1.63 ms min.
1
1
1
1
1
1
1
0 217/fX min. 13.1 ms min. 6.55 ms min.
1
1
1
1
1
1
1
1 218/fX min. 26.2 ms min. 13.1 ms min.
Caution 1. After the above time has elapsed, the bits are set to 1 in order from the MOST8 bit and remain 1. Caution 2. The value counted by the OSTC register will only have reached the oscillation stabilization time setting
in the oscillation stabilization time select register (OSTS). In the following cases, set the oscillation stabilization time of the OSTS register to the value greater than the counter value which is to be checked by using the OSTC register. · If the X1 clock starts oscillation while the main on-chip oscillator clock or subsystem clock is in use
as the CPU clock.
· If entry to and then release from the STOP mode proceed while the main on-chip oscillator clock is in
use as the CPU clock and the X1 clock is oscillating
Therefore, note that the value counted by the OSTC register will only have reached the oscillation
stabilization time setting in the OSTS register after release from the STOP mode.
Caution 3. The X1 clock oscillation stabilization time does not include the time until clock oscillation starts ("a" below).
Release from the STOP mode
Voltage waveform on the X1 pin a
Remark fX: X1 clock oscillation frequency
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6.3.5 Oscillation stabilization time select register (OSTS)
This register is used to select the X1 clock oscillation stabilization time. When the X1 clock is made to oscillate by clearing the MSTOP bit to start operation of the X1 oscillator, actual operation is automatically delayed for the time set in the OSTS register. Use the oscillation stabilization time counter status register (OSTC) to confirm that the specified oscillation stabilization time has elapsed when the CPU clock is switched from the main on-chip oscillator clock or the subsystem clock to the X1 clock or entry to and then release from the STOP mode proceed while the main on-chip oscillator clock is in use as the CPU clock and the X1 clock is oscillating. The OSTC register can be used to check the counter value when counting has reached the time set beforehand in the OSTS register. The OSTS register can be set by an 8-bit memory manipulation instruction. The value of this register is 07H following a reset.
Figure 6 - 6 Format of Oscillation Stabilization Time Select Register (OSTS)
Address: After reset: R/W:
FFFA3H 07H R/W
Symbol
7
6
5
4
3
2
1
0
OSTS
0
0
0
0
0
OSTS2
OSTS1
OSTS0
OSTS2
OSTS1
OSTS0
Selection of the oscillation stabilization time
fX = 10 MHz
fX = 20 MHz
0
0
0
28/fX
25.6 µs
12.8 µs
0
0
1
29/fX
51.2 µs
25.6 µs
0
1
0
210/fX
102 µs
51.2 µs
0
1
1
211/fX
204 µs
102 µs
1
0
0
213/fX
819 µs
409 µs
1
0
1
215/fX
3.27 ms
1.63 ms
1
1
0
217/fX
13.1 ms
6.55 ms
1
1
1
218/fX
26.2 ms
13.1 ms
Caution 1. Change the setting of the OSTS register before setting the MSTOP bit of the clock operation status control register (CSC) to 0.
Caution 2. The value counted by the OSTC register will only have reached the oscillation stabilization time setting in the OSTS register. In the following cases, set the oscillation stabilization time of the OSTS register to the value greater than the counter value which is to be checked by using the OSTC register after the oscillation starts. · If the X1 clock starts oscillation while the main on-chip oscillator clock or subsystem clock is in use
as the CPU clock.
· If entry to and then release from the STOP mode proceed while the main on-chip oscillator clock is in
use as the CPU clock and the X1 clock is oscillating.
Therefore, note that the value counted by the OSTC register will only have reached the oscillation
stabilization time setting in the OSTS register after release from the STOP mode.
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Caution 3. The X1 clock oscillation stabilization time does not include the time until clock oscillation starts ("a" below).
Release from the STOP mode
Voltage waveform on the X1 pin a
Remark fX: X1 clock oscillation frequency
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6.3.6 Peripheral enable registers 0, 1 (PER0, PER1)
These registers are used to enable or disable the supply of a clock signal to various on-chip peripheral modules. Clock supply to an on-chip peripheral module that is not to be used can be stopped to decrease power consumption and noise. To use any of the on-chip peripheral modules listed below, the clock supplies to which are controlled by these registers, set the corresponding bit to 1 before making the initial settings of the on-chip peripheral module.
· Realtime clock · Serial interface IICAn · A/D converter · Serial array unit n · Timer array unit n · D/A converter · SNOOZE mode sequencer · Comparator · 32-bit interval timer · DTC · Serial interface UARTAn · Remote control signal receiver · Capacitive sensing unit
Remark n = 0, 1
The PER0 and PER1 registers can be set by a 1-bit or 8-bit memory manipulation instruction. The value of each of these registers is 00H following a reset.
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Figure 6 - 7 Format of Peripheral Enable Register 0 (PER0)
Address: After reset: R/W:
F00F0H 00H R/W
Symbol
<7>
PER0 RTCWEN
<6> IICA1EN
<5> ADCEN
<4> IICA0EN
<3> SAU1EN
<2> SAU0EN
<1> TAU1EN
<0> TAU0EN
RTCWEN
Control of access to the realtime clock
0
The SFRs used by the realtime clock cannot be written.
1
The SFRs used by the realtime clock can be read and written.
IICA1EN
Control of supply of an input clock to the IICA1 serial interface
0
Stops supply of an input clock.
· The SFRs used by the IICA1 serial interface cannot be written.
· When an SFR used by the IICA1 serial interface is read, the value returned is 00H or 0000H.
1
Enables supply of an input clock.
· The SFRs used by the IICA1 serial interface can be read and written.
ADCEN 0
1
Control of supply of an input clock to the A/D converter Stops supply of an input clock. · The SFRs used by the A/D converter cannot be written. · When an SFR used by the A/D converter is read, the value returned is 00H or 0000H. Enables supply of an input clock. · The SFRs used by the A/D converter can be read and written.
IICA0EN
Control of supply of an input clock to the IICA0 serial interface
0
Stops supply of an input clock.
· The SFRs used by the IICA0 serial interface cannot be written.
· When an SFR used by the IICA0 serial interface is read, the value returned is 00H or 0000H.
1
Enables supply of an input clock.
· The SFRs used by the IICA0 serial interface can be read and written.
SAU1EN
Control of supply of an input clock to serial array unit 1
0
Stops supply of an input clock.
· The SFRs used by serial array unit 1 cannot be written.
· When an SFR used by serial array unit 1 is read, the value returned is 00H or 0000H.
1
Enables supply of an input clock.
· The SFRs used by serial array unit 1 can be read and written.
SAU0EN
Control of supply of an input clock to serial array unit 0
0
Stops supply of an input clock.
· The SFRs used by serial array unit 0 cannot be written.
· When an SFR used by serial array unit 0 is read, the value returned is 00H or 0000H.
1
Enables supply of an input clock.
· The SFRs used by serial array unit 0 can be read and written.
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TAU1EN 0
1
Control of supply of an input clock to timer array unit 1 Stops supply of an input clock. · The SFRs used by timer array unit 1 cannot be written. · When an SFR used by timer array unit 1 is read, the value returned is 00H or 0000H. Enables supply of an input clock. · The SFRs used by timer array unit 1 can be read and written.
TAU0EN
Control of supply of an input clock to timer array unit 0
0
Stops supply of an input clock.
· The SFRs used by timer array unit 0 cannot be written.
· When an SFR used by timer array unit 0 is read, the value returned is 00H or 0000H.
1
Enables supply of an input clock.
· The SFRs used by timer array unit 0 can be read and written.
Caution 1. Be sure to clear the following bits to 0. 30-, 32-, 36-, and 40-pin products: Bits 6 and 1 44-, 48-, 52-, 64-pin products: Bit 1
Caution 2. Do not change the value of a bit of the PER0 register while operation of the corresponding on-chip peripheral module is enabled. Only change a value while the corresponding on-chip peripheral module is stopped.
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Figure 6 - 8 Format of Peripheral Enable Register 1 (PER1)
Address: After reset: R/W:
F00FAH 00H R/W
Symbol
<7>
PER1 DACEN
<6> SMSEN
<5> CMPEN
<4> TML32EN
<3> DTCEN
<2> UTAEN
<1> REMCEN
<0> CTSUEN
DACEN 0
1
Control of supply of an input clock to the D/A converter Stops supply of an input clock. · The SFRs used by the D/A converter cannot be written. · When an SFR used by the D/A converter is read, the value returned is 00H or 0000H. Enables supply of an input clock. · The SFRs used by the D/A converter can be read and written.
SMSEN 0
1
Control of supply of an input clock to the SNOOZE mode sequencer Stops supply of an input clock. · The SFRs used by the SNOOZE mode sequencer cannot be written. · When an SFR used by the SNOOZE mode sequencer is read, the value returned is 00H or
0000H. Enables supply of an input clock. · The SFRs used by the SNOOZE mode sequencer can be read and written.
CMPEN 0
1
Control of supply of an input clock to the comparator Stops supply of an input clock. · The SFRs used by the comparator cannot be written. · When an SFR used by the comparator is read, the value returned is 00H or 0000H. Enables supply of an input clock. · The SFRs used by the comparator can be read and written.
TML32EN
Control of supply of an input clock to the 32-bit interval timer
0
Stops supply of an input clock.
· The SFRs used by the 32-bit interval timer cannot be written.
· When an SFR used by the 32-bit interval timer is read, the value returned is 00H or 0000H.
1
Enables supply of an input clock.
· The SFRs used by the 32-bit interval timer can be read and written.
DTCEN 0
1
Control of supply of an input clock to the DTC Stops supply of an input clock. · The DTC cannot operate. Enables supply of an input clock. · The DTC can operate.
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UTAEN 0
1
Control of supply of an input clock to the UARTAn serial interface (n = 0, 1) Stops supply of an input clock. · The SFRs used by the UARTAn serial interface cannot be written. · When an SFR used by the UARTAn serial interface is read, the value returned is 00H or
0000H. Enables supply of an input clock. · The SFRs used by the UARTAn serial interface can be read and written.
REMCEN
Control of supply of an input clock to the remote control signal receiver
0
Stops supply of an input clock.
· The SFRs used by the remote control signal receiver cannot be written.
· When an SFR used by the remote control signal receiver is read, the value returned is 00H
or 0000H.
1
Enables supply of an input clock.
· The SFRs used by the remote control signal receiver can be read and written.
CTSUEN
Control of supply of an input clock to the capacitive sensing unit
0
Stops supply of an input clock.
· The SFRs used by the capacitive sensing unit cannot be written.
· When an SFR used by the capacitive touch sensing unit is read, the value returned is 00H or
0000H.
1
Enables supply of an input clock.
· The SFRs used by the capacitive sensing unit can be read and written.
Caution 1. Be sure to clear the following bits to 0. 30-pin products: Bits 2 and 1 32-pin products: Bit 2
Caution 2. Do not change the value of a bit of the PER1 register while operation of the corresponding on-chip peripheral module is enabled. Only change a value while the corresponding on-chip peripheral module is stopped.
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6.3.7 Subsystem clock supply mode control register (OSMC)
This register is used to reduce power consumption by stopping unnecessary clock functions. If the RTCLPC bit is set to 1, power consumption can be reduced, because clock supply to the peripheral functions except the realtime clock is stopped in STOP mode or in HALT mode while the CPU is operating with the subsystem clock. In addition, the OSMC register can be used to select the operating clock for the realtime clock, clock output/buzzer output controller, 32-bit interval timer, serial interfaces UARTA0 and UARTA1, and remote control signal receiver. The OSMC register can be set by an 8-bit memory manipulation instruction. The value of this register is undefined following a reset.
Figure 6 - 9 Format of Subsystem Clock Supply Mode Control Register (OSMC)
Address: After reset: R/W:
F00F3H Undefined R/WNote 1
Symbol
<7>
6
5
<4>
3
2
1
<0>
OSMC RTCLPC
0
0
WUTMMCK 0
x
x
0
HIPREC
RTCLPC
Note 4
Setting in STOP mode or in HALT mode while the CPU is operating with the subsystem clock.
0
Enables supply of the subsystem clock to peripheral functions
(See Table 23 - 1 to Table 23 - 4 for peripheral functions whose operations are enabled.)
1
Stops supply of the subsystem clock to peripheral functions other than the realtime clock.
WUTMMC K0
Selection of the operating clock for the realtime clock, 32-bit interval timer, serial interfaces UARTA0 and UARTA1, remote control signal receiver, and clock output/buzzer output controller
0
Subsystem clock X
1
Low-speed on-chip oscillator clockNotes 2, 3
HIPREC
State of the high-speed on-chip oscillator clockNotes 5, 6
0
The high-speed on-chip oscillator clock is being started at high speed and waiting for the
precision of its oscillation to become stable is in progress.Note 7
1
The high-speed on-chip oscillator clock is operating with high precision.
Note 1. Note 2. Note 3.
Note 4.
Note 5. Note 6.
Be sure to set bits 6, 5, and 1 to 0. Bits 3, 2, and 0 are read-only. Writing to these bits is ignored. Do not set the WUTMMCK0 bit to 1 while the subsystem clock X is oscillating. Switching between the subsystem clock X and the low-speed on-chip oscillator clock can be enabled by the WUTMMCK0 bit only when all of the realtime clock, 32-bit interval timer, serial interfaces UARTA0 and UARTA1, remote control signal receiver, and clock output/buzzer output function are stopped. When the subsystem clock X is selected (SELLOSC = 0) by bit 0 (SELLOSC) of the CKSEL register and RTCLPC is set to 1, the subsystem clock (fSUB) is stopped. However, when the low-speed on-chip oscillator clock is selected (SELLOSC = 1) and RTCLPC is set to 1, the subsystem clock (fSUB) is not stopped. Undefined while the high-speed on-chip oscillator is stopped. For frequency accuracy of the high-speed on-chip oscillator clock, see CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
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Note 7.
When the RL78/G23 is released from the STOP mode while the setting for starting the high-speed on-chip oscillator at high speed is in place (WKUPMD.FWKUP = 1), the high-speed on-chip oscillator clock runs at low precision while it is starting up. After the oscillation accuracy stabilization time, the value of the HIPREC bit changes automatically to 1. The table below shows the frequency of the high-speed on-chip oscillator when FRQSEL3 = 0 and HIPREC = 0.
Setting of FRQSEL2 or Setting of FRQSEL1 or Setting of FRQSEL0 or Frequency of the High-Speed
HOCODIV2
HOCODIV1
HOCODIV0
On-Chip Oscillator
0
0
0
16 MHz
0
0
1
8 MHz
0
1
0
4 MHz
0
1
1
2 MHz
1
0
0
Setting prohibited
1
0
1
Setting prohibited
Caution Do not execute a STOP instruction when HIPREC = 0. Remark x: Undefined
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6.3.8 Subsystem clock select register (CKSEL)
The CKSEL register is used to select the subsystem clock X or low-speed on-chip oscillator clock as the subsystem clock. The CKSEL register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 6 - 10 Format of Subsystem Clock Select Register (CKSEL)
Address: After reset: R/W:
FFFA7H 00H R/W
Symbol
7
6
5
4
3
2
1
<0>
CKSEL
0
0
0
0
0
0
0
SELLOSC
SELLOSC
Selection of the subsystem clock X or low-speed on-chip oscillator clock
0
Subsystem clock X
1
Low-speed on-chip oscillator clockNote
Note
Do not set SELLOSC to 1 when the subsystem clock X (fSX) or XR (fSXR) is operating.
Caution When changing the value of the SELLOSC bit, be sure to set the CSS bit to 0 (selecting fMAIN) and confirm that the value of the CLS bit is 0 before doing so.
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6.3.9 High-speed on-chip oscillator frequency select register (HOCODIV)
The HOCODIV register is used to change the frequency of the high-speed on-chip oscillator set in an option byte (000C2H). Note that the selectable frequencies depend on the value of the FRQSEL3 bit of the option byte (000C2H). The HOCODIV register can be set by an 8-bit memory manipulation instruction. The value of this register is that set in FRQSEL2 to FRQSEL0 of the option byte (000C2H) following a reset.
Figure 6 - 11 Format of High-Speed On-Chip Oscillator Frequency Select Register (HOCODIV)
Address: After reset: R/W:
F00A8H The value set in FRQSEL2 to FRQSEL0 of an option byte (000C2H) R/W
Symbol
7
6
5
4
3
2
1
0
HOCODIV
0
0
0
0
0
HOCODIV2 HOCODIV1 HOCODIV0
HOCODIV2 HOCODIV1 HOCODIV0
Selection of the high-speed on-chip oscillator clock frequency
FRQSEL3 = 0
FRQSEL3 = 1
0
0
0
fIH = 24 MHz
0
0
1
fIH = 12 MHz
0
1
0
fIH = 6 MHz
0
1
1
fIH = 3 MHz
1
0
0
Setting prohibited
fIH = 32 MHz fIH = 16 MHz fIH = 8 MHz fIH = 4 MHz fIH = 2 MHz
1
0
1
Setting prohibited
fIH = 1 MHz
Other than above
Setting prohibited
Caution 1. Set the HOCODIV register while ensuring that the voltage is within the usable range for the flash operation mode set in the flash operating mode select register (FLMODE) both before and after the frequency change. For details about the FLMODE register, see 5.2.1 Flash operating mode select register (FLMODE).
Caution 2. Set the HOCODIV register with the high-speed on-chip oscillator clock (fIH) selected as the CPU/peripheral hardware clock (fCLK).
Caution 3. After use of the HOCODIV register to change the frequency, actually switching of the frequency only proceeds after the following transition times have elapsed.
· The CPU/peripheral hardware clock continues to operate at the frequency before the change for up to three cycles.
· Up to three cycles of waiting are required for the CPU/peripheral hardware clock to be at the postchange frequency.
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6.3.10 Middle-speed on-chip oscillator frequency select register (MOCODIV)
The MOCODIV register is used to select the frequency of the middle-speed on-chip oscillator. The MOCODIV register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 6 - 12 Format of Middle-Speed On-Chip Oscillator Frequency Select Register (MOCODIV)
Address: After reset: R/W:
F00F2H 00H R/W
Symbol
7
6
5
4
3
2
1
0
MOCODIV
0
0
0
0
0
0
MOCODIV1 MOCODIV0
MOCODIV MOCODIV
1
0
Selection of the middle-speed on-chip oscillator clock frequency
0
0
4 MHz
0
1
2 MHz
1
0
1 MHz
Other than above Setting prohibited
Caution
Set the MOCODIV register while ensuring that the voltage is within the usable range for the flash operation mode set in the flash operating mode select register (FLMODE) both before and after the frequency change.
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6.3.11 High-speed system clock division register (MOSCDIV)
This register is used to select the division ratio of the high-speed system clock. The MOSCDIV register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 6 - 13 Format of High-Speed System Clock Division Register (MOSCDIV)
Address: After reset: R/W:
F0214H 00H R/W
Symbol
7
6
5
4
3
2
1
0
MOSCDIV
0
0
0
0
0
MOSCDIV2 MOSCDIV1 MOSCDIV0
Selected division ratio for the MOSCDIV2 MOSCDIV1 MOSCDIV0
high-speed system clock
fMX = 20 MHz
0
0
0
fMX
20 MHz
0
0
1
fMX/2
10 MHz
0
1
0
0
1
1
1
0
0
Other than above
fMX/4 fMX/8 fMX/16
5 MHz 2.5 MHz 1.25 MHz Setting prohibited
Caution
Set the MOSCDIV register while ensuring that the voltage is within the usable range for the flash operation mode set in the flash operating mode select register (FLMODE) both before and after the frequency change.
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6.3.12 High-speed on-chip oscillator trimming register (HIOTRM)
This register is used to adjust the accuracy of the high-speed on-chip oscillator. The accuracy of the high-speed on-chip oscillator frequency can be adjusted through self-measurement of the frequency by using a timer with high accuracy (timer array unit or 32-bit interval timer) for external clock input or in other ways. The HIOTRM register can be set by an 8-bit memory manipulation instruction.
Caution
The frequency will vary if the temperature and VDD pin voltage change after accuracy adjustment. When the temperature and VDD voltage change, accuracy adjustment must be executed regularly or before the frequency accuracy is required.
Figure 6 - 14 Format of High-Speed On-Chip Oscillator Trimming Register (HIOTRM)
Address: After reset: R/W:
F00A0H Note R/W
Symbol
7
HIOTRM
0
6
5
4
3
2
1
0
0
HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRM0
HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRM0
High-speed on-chip oscillator
0
0
0
0
0
0
Minimum speed
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
1
0
0
· · ·
1
1
1
1
1
0
1
1
1
1
1
1
Maximum speed
Note
The value of this register is that adjusted at shipment following a reset.
Remark 1. The HIOTRM register holds a six-bit value used to adjust the high-speed on-chip oscillator with an increment of 1 corresponding to an increase of frequency by about 0.05%.
Remark 2. For the usage example of the HIOTRM register, see the Application Note for RL78 MCU Series High-speed On-chip Oscillator (HOCO) Clock Frequency Correction (R01AN2833).
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6.3.13 Middle-speed on-chip oscillator trimming register (MIOTRM)
This register is used to adjust the accuracy of the middle-speed on-chip oscillator. The accuracy of the middle-speed on-chip oscillator frequency can be adjusted through self-measurement of the frequency by using a timer with high accuracy (timer array unit or 32-bit interval timer) for external clock input or in other ways. The MIOTRM register can be set by an 8-bit memory manipulation instruction. The value of this register is 90H following a reset.
Caution
The frequency will vary if the temperature and VDD pin voltage change after accuracy adjustment. When the temperature and VDD voltage change, accuracy adjustment must be executed regularly or before the frequency accuracy is required.
Figure 6 - 15 Format of Middle-Speed On-Chip Oscillator Trimming Register (MIOTRM)
Address: After reset: R/W:
F0212H 90H R/W
Symbol
7
6
5
4
3
2
1
0
MIOTRM MIOTRM7 MIOTRM6 MIOTRM5 MIOTRM4 MIOTRM3 MIOTRM2 MIOTRM1 MIOTRM0
MIOTRM MIOTRM MIOTRM MIOTRM MIOTRM MIOTRM MIOTRM MIOTRM Middle-speed on-
7
6
5
4
3
2
1
0
chip oscillator
0
0
0
0
0
0
0
0
Minimum speed
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
1
0
0
1
0
0
0
0
Initial value
1
0
0
1
0
0
0
1
1 1 Remark
1
1
1
1
1
1
0
1
1
1
1
1
1
1
Maximum speed
For details about the accuracy adjustment resolution of the middle-speed on-chip oscillator clock, see CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
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6.3.14 Low-speed on-chip oscillator trimming register (LIOTRM)
This register is used to adjust the accuracy of the low-speed on-chip oscillator. The accuracy of the low-speed on-chip oscillator frequency can be adjusted through self-measurement of the frequency by using a timer with high accuracy (timer array unit or 32-bit interval timer) for external clock input or in other ways. The LIOTRM register can be set by an 8-bit memory manipulation instruction. The value of this register is 80H following a reset.
Caution
The frequency will vary if the temperature and VDD pin voltage change after accuracy adjustment. When the temperature and VDD voltage change, accuracy adjustment must be executed regularly or before the frequency accuracy is required.
Figure 6 - 16 Format of Low-Speed On-Chip Oscillator Trimming Register (LIOTRM)
Address: After reset: R/W:
F0213H 80H R/W
Symbol
7
LIOTRM LIOTRM7
6 LIOTRM6
5 LIOTRM5
4 LIOTRM4
3 LIOTRM3
2 LIOTRM2
1 LIOTRM1
0 LIOTRM0
Low-speed onLIOTRM7 LIOTRM6 LIOTRM5 LIOTRM4 LIOTRM3 LIOTRM2 LIOTRM1 LIOTRM0
chip oscillator
0
0
0
0
0
0
0
0
Minimum speed
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
Initial value
1
0
0
0
0
0
0
1
1 1 Remark
1
1
1
1
1
1
0
1
1
1
1
1
1
1
Maximum speed
For details about the accuracy adjustment resolution of the low-speed on-chip oscillator clock, see CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
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6.3.15 Standby mode release setting register (WKUPMD)
This register is used to set the operation when the standby mode is released. The WKUPMD register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 6 - 17 Format of Standby Mode Release Setting Register (WKUPMD)
Address: After reset: R/W:
F0215H 00H R/W
Symbol
7
6
5
4
3
2
1
<0>
WKUPMD
0
0
0
0
0
0
0
FWKUP
FWKUP
0 1
Setting for starting the high-speed on-chip oscillator at the times of release from STOP mode and of transitions to SNOOZE modeNotes 1, 2
Starting of the high-speed on-chip oscillator is at normal speed.Note 3 Starting of the high-speed on-chip oscillator is at high speed.Note 3
Note 1. Note 2.
Note 3.
This setting is only available when the high-speed on-chip oscillator is selected for the CPU clock. This register is initialized when the RL78/G23 is released from STOP mode in response to the generation of a reset signal, so starting of the high-speed on-chip oscillator is at normal speed. For the activation time, see CHAPTER 23 STANDBY FUNCTION. The accuracy of the high-speed on-chip oscillator frequency depends on whether starting of the high-speed on-chip oscillator is at normal speed or at high speed. See CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
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6.4
System Clock Oscillator
6.4.1 X1 oscillator
The X1 oscillator oscillates with a crystal resonator or ceramic resonator (1 to 20 MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input the clock signal to the EXCLK pin. To use the X1 oscillator, set bits 7 and 6 (EXCLK, OSCSEL) of the clock operation mode control register (CMC) as follows. · Crystal or ceramic oscillation: EXCLK, OSCSEL = 0, 1 · External clock input: EXCLK, OSCSEL = 1, 1 When the X1 oscillator is not used, set the port mode (EXCLK, OSCSEL = 0, 0). When the pins are not used as port pins, either, see Table 2 - 3 Connections of Unused Pins. Figure 6 - 18 shows Examples of External Circuits for the X1 Oscillator.
Figure 6 - 18 Examples of External Circuits for the X1 Oscillator
(a) Crystal or ceramic oscillation
VSS X1
(b) External clock
X2
Crystal resonator or ceramic resonator
External clock
EXCLK
(Caution is listed on the next page.)
6.4.2 XT1 oscillator
The XT1 oscillator oscillates with a crystal resonator (32.768 kHz (typ.)) connected to the XT1 and XT2 pins.
To use the XT1 oscillator, set bit 4 (OSCSELS) of the clock operation mode control register (CMC) to 1.
An external clock can also be input. In this case, input the clock signal to the EXCLKS pin. To use the XT1 oscillator, set
bits 5 and 4 (EXCLKS, OSCSELS) of the clock operation mode control register (CMC) as follows.
· Crystal oscillation:
EXCLKS, OSCSELS = 0, 1
· External clock input:
EXCLKS, OSCSELS = 1, 1
When the XT1 oscillator is not used, set the input port mode (EXCLKS, OSCSELS = 0, 0). When XT1 oscillator is not used, and the pins are not used as input port pins, either, see Table 2 - 3 Connections of Unused Pins.
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Figure 6 - 19 shows Examples of External Circuits for the XT1 Oscillator. Figure 6 - 19 Examples of External Circuits for the XT1 Oscillator
(a) Crystal oscillation
(b) External clock
VSS XT1 32.768 kHz
XT2
External clock
EXCLKS
Caution When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed in broken lines in the Figure
6 - 18 and Figure 6 - 19 to avoid an adverse effect from wiring capacitance.
· Keep the wiring length as short as possible. · Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a
strong fluctuating current flows. · Always apply the same potential to the ground point for capacitors in the oscillator as that on VSS. Do not ground
the capacitors to a ground pattern through which a strong current flows. · Do not bring a signal line out from the oscillator.
The XT1 oscillator is a circuit with low amplification in order to achieve low power consumption. Note the following points when designing the circuit. · Pins and circuit boards include parasitic capacitance. Therefore, perform oscillation evaluation using a circuit board to be actually used and confirm that there are no problems. · When using low power consumption oscillation 2 (AMPHS1, AMPHS0 = 1, 0) or low power consumption oscillation 3 (AMPHS1, AMPHS0 = 1, 1) as the XT1 oscillator mode, sufficiently evaluate the resonator as described in 6.7 Resonator and Oscillator Constants, before using it in either of these modes. · Make the wiring runs between the XT1 and XT2 pins and the resonator as short as possible to minimize the parasitic capacitance and wiring resistance. Take care with this particularly when low power consumption oscillation 2 (AMPHS1, AMPHS0 = 1, 0) or low power consumption oscillation 3 (AMPHS1, AMPHS0 = 1, 1) is selected. · Configure the circuit of the circuit board, using material with little parasitic capacitance and wiring resistance. · Place a ground pattern that has the same potential as VSS as much as possible near the XT1 oscillator. · Be sure that the signal lines between the XT1 and XT2 pins and the resonator do not cross the other signal lines. Do not route the wiring near a signal line through which a strong fluctuating current flows. · The impedance between the XT1 and XT2 pins may drop and oscillation may be disturbed due to moisture absorption of the circuit board in a high-humidity environment or dew condensation on the board. When using the circuit board in such an environment, take measures to damp-proof the circuit board, such as by coating. · When coating the circuit board, use material that does not cause capacitance or leakage between the XT1 and XT2 pins.
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Figure 6 - 20 shows examples of incorrect resonator connection. Figure 6 - 20 Examples of Incorrect Resonator Connection (1/2)
(a) The wiring runs of the oscillator are too long.
(b) The wiring runs of the oscillator cross signal lines.
VSS
X1
X2
PORT
VSS
X1
X2
NG
NG
NG
(c) The wiring runs for the X1 and X2 signals cross each other.
(d) The power supply or GND pattern is under the wiring runs for the X1 and X2 signals.
VSS
X1
X2
VSS X1
X2
Note Power supply or GND pattern
Note
Do not place a power supply or GND pattern under the wiring section (section enclosed in broken lines in the figure) of the X1 and X2 pins and the resonator in a multi-layer board or double-sided board. Do not configure a layout that will cause capacitance elements and affect the oscillation characteristics.
Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert a resistor in series on the XT2 side.
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Figure 6 - 20 Examples of Incorrect Resonator Connection (2/2)
(e) A signal line for the oscillator and a signal line through which a strong fluctuating current flows are close to each other.
(f) Current flows through the ground line of the oscillator (making the potential at points A, B, and C fluctuate).
VDD
VSS
X1
X2
VSS
X1
Pmn X2
Strong current
A
B
C
Strong current
(g) A signal line is brought out.
V SS
X1
X2
Caution When the wiring runs for the X2 and X1 signals are in parallel, crosstalk noise from the X2 signal line may be imposed on the X1 signal, resulting in malfunctions.
Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert a resistor in series on the XT2 side.
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6.4.3 High-speed on-chip oscillator
The high-speed on-chip oscillator is incorporated in the RL78/G23. The frequency can be selected from among 32, 24, 16, 12, 8, 6, 4, 3, 2, or 1 MHz by using an option byte (000C2H). Oscillation can be controlled by bit 0 (HIOSTOP) of the clock operation status control register (CSC). The high-speed on-chip oscillator automatically starts oscillating after release from the reset state.
6.4.4 Middle-speed on-chip oscillator
The middle-speed on-chip oscillator is incorporated in the RL78/G23. Oscillation can be controlled by bit 1 (MIOEN) of the clock operation status control register (CSC).
6.4.5 Low-speed on-chip oscillator
The low-speed on-chip oscillator is incorporated in the RL78/G23. The low-speed on-chip oscillator operates when any of the following conditions is met.
The watchdog timer is operating. The value of one or both of bit 4 (WUTMMCK0) of the subsystem clock supply mode control register (OSMC) and
bit 0 (SELLOSC) of the subsystem clock select register (CKSEL) is 1. fIL is selected as the source clock for use in waiting by the SNOOZE mode sequencer. The low-speed on-chip oscillator is stopped when the watchdog timer is stopped and both WUTMMCK0 and SELLOSC are set to 0.
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6.5
Operations of the Clock Generator
The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode (see Figure 6 - 1).
· Main system clocks (fMAIN) High-speed system clocks (fMX) X1 clock (fX) External main system clock (fEX) High-speed on-chip oscillator clock (fIH) Middle-speed on-chip oscillator clock (fIM)
· Subsystem clocks (fSUB) XT1 clock (fXT) External subsystem clock (fEXS) Low-speed on-chip oscillator clock (fIL)
· CPU/peripheral hardware clock (fCLK)
· Subsystem clock X (fSX)
· Peripheral clocks High-speed on-chip oscillator peripheral clock (fIHP) Middle-speed on-chip oscillator peripheral clock (fIMP) High-speed peripheral clock (fMXP) Low-speed peripheral clock (fSXP) Subsystem clock XR (fSXR)
The CPU starts operation when the high-speed on-chip oscillator starts outputting after release from the reset state in the RL78/G23. Clock Generator Operation When Power Supply Voltage is Turned On is shown in Figure 6 - 21.
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Figure 6 - 21 Clock Generator Operation When Power Supply Voltage is Turned On
10 µs or more
Lower limit of the operating voltage range
Power supply voltage (VDD)
VPOR
0 V
<1>
Power-on-reset signal
RESET pin
CPU clock
High-speed on-chip oscillator clock (fIH) High-speed system clock
(fMX) (when X1 oscillation
selected) Subsystem clock (fSUB)
(when XT1 oscillation selected)
Reset processing
timeNote 3
<3>
High-speed on-chip
oscillator clock
<2>
Note 1 <4>
X1 clock oscillation
stabilization timeNote 2
Starting X1 oscillation
<4>
is specified by software.
Switched by software
<5> High-speed system clock
<5> Subsystem clock
Starting XT1 oscillation is specified by software.
<1> When the power is turned on, an internal reset signal is generated by the power-on-reset (POR) circuit. Note that the reset state is maintained after a reset by the voltage detection circuit or an external reset until the voltage reaches the range of operating voltage described in 37.4 AC Characteristics (the above figure is an example when the external reset is in use).
<2> When the reset is released, the high-speed on-chip oscillator automatically starts oscillation. <3> The CPU starts operation with the high-speed on-chip oscillator clock after waiting for the voltage to become stable
and a reset processing have been performed after release from the reset state. <4> Set the start of oscillation of the X1 or XT1 clock via software (see 6.6.2 Example of setting the X1 oscillator
clock and 6.6.3 Example of setting the XT1 oscillator clock). <5> When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to become stable, and then
make the setting for switching via software (see 6.6.2 Example of setting the X1 oscillator clock and 6.6.3 Example of setting the XT1 oscillator clock).
Note 1. Note 2. Note 3.
The internal reset processing time includes the oscillation accuracy stabilization time of the high-speed on-chip oscillator clock. When releasing a reset, confirm the oscillation stabilization time for the X1 clock using the oscillation stabilization time counter status register (OSTC). For the reset processing time, see CHAPTER 25 POWER-ON-RESET CIRCUIT (POR).
Caution Waiting for the oscillation stabilization time is not required when external clock input through the EXCLK pin is used.
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6.6
Controlling Clocks
6.6.1 Example of setting the high-speed on-chip oscillator
After release from the reset state, the CPU/peripheral hardware clock (fCLK) always starts operating with the high-speed on-chip oscillator clock as the source. The frequency of the high-speed on-chip oscillator can be selected from among 32, 24, 16, 12, 8, 6, 4, 3, 2, or 1 MHz by using FRQSEL0 to FRQSEL3 of an option byte (000C2H). In addition, the frequency can be changed by the high-speed on-chip oscillator frequency select register (HOCODIV).
[Option byte setting]
Address: 000C2H
Option byte
7
6
5
(000C2H)
CMODE1 CMODE0
0/1
0/1
1
4
3
2
1
0
FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0
0
0/1
0/1
0/1
0/1
FRQSEL3 1 0 1 0 1 0 1 0 1 1
FRQSEL2 FRQSEL1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
Other than above
FRQSEL0 Frequency of the high-speed on-chip oscillator
0
32 MHz
0
24 MHz
1
16 MHz
1
12 MHz
0
8 MHz
0
6 MHz
1
4 MHz
1
3 MHz
0
2 MHz
1
1 MHz
Setting prohibited
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[High-speed on-chip oscillator frequency select register (HOCODIV) setting]
Address: F00A8H
Symbol
7
6
5
4
3
2
1
0
HOCODIV
0
0
0
0
0
HOCODIV2 HOCODIV1 HOCODIV0
HOCODIV2 HOCODIV1 HOCODIV0
Selection of the high-speed on-chip oscillator clock frequency
FRQSEL3 = 0
FRQSEL3 = 1
0
0
0
fIH = 24 MHz
fIH = 32 MHz
0
0
1
fIH = 12 MHz
fIH = 16 MHz
0
1
0
fIH = 6 MHz
fIH = 8 MHz
0
1
1
fIH = 3 MHz
fIH = 4 MHz
1
0
0
Setting prohibited
fIH = 2 MHz
1
0
1
Setting prohibited
fIH = 1 MHz
Other than above
Setting prohibited
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6.6.2 Example of setting the X1 oscillator clock
After release from the reset state, the CPU/peripheral hardware clock (fCLK) always starts operating with the high-speed on-chip oscillator clock as the source. To subsequently change the source clock to the X1 oscillator clock, set and start the oscillator by using the oscillation stabilization time select register (OSTS), clock operation mode control register (CMC), and clock operation status control register (CSC), and wait for the oscillation to become stable by using the oscillation stabilization time counter status register (OSTC). After the oscillation becomes stable, set the X1 oscillator clock as the source of fCLK by using the system clock control register (CKC).
[Register settings] Set the registers in the order of <1> to <5> below. <1> Set the OSCSEL bit of the CMC register to 1 to make the X1 oscillator operate. Also set the AMPH bit to 1 if fX is
more than 10 MHz.
CMC
7
EXCLK 0
6
OSCSEL 1
5
EXCLKS 0
4
OSCSELS 0
3
XTSEL 0
2
AMPHS1 0
1
AMPHS0 0
0
AMPH 0/1
<2> Use the OSTS register to select the oscillation stabilization time for the X1 oscillator after release from the STOP mode. Example: Set the register as shown below if waiting is to be for at least 102 µs with a 10-MHz resonator.
7
6
5
4
3
2
1
0
OSTS
OSTS2
OSTS1
OSTS0
0
0
0
0
0
0
1
0
<3> Clear the MSTOP bit of the CSC register to 0 to start X1 oscillation.
7
6
5
4
3
2
1
0
CSC MSTOP
XTSTOP
MIOEN
HIOSTOP
0
1
0
0
0
0
0
0
<4> Use the OSTC register to wait for oscillation of the X1 oscillator to become stable. Example: Wait until counting has reached the following value if waiting is to be for at least 102 µs with a 10-MHz resonator.
OSTC
7
MOST8 1
6
MOST9 1
5
MOST10 1
4
MOST11 0
3
MOST13 0
2
MOST15 0
1
MOST17 0
0
MOST18 0
<5> Use the MCM0 bit of the CKC register to specify the X1 oscillator clock as the source of the CPU/peripheral hardware clock.
7
6
5
4
3
2
1
0
CKC
CLS 0
Caution
CSS
MCS
MCM0
0
0
1
0
MCS1
MCM1
0
0
0
Set the HOCODIV register while ensuring that the voltage is within the usable range for the flash operation mode set in the flash operating mode select register (FLMODE) both before and after the frequency change. For details about the FLMODE register, see 5.2.1 Flash operating mode select register (FLMODE).
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6.6.3 Example of setting the XT1 oscillator clock
After release from the reset state, the CPU/peripheral hardware clock (fCLK) always starts operating with the high-speed on-chip oscillator clock as the source. To subsequently change the source clock to the XT1 oscillator clock, set and start the oscillator by using the subsystem clock supply mode control register (OSMC), clock operation mode control register (CMC), and clock operation status control register (CSC), and set the XT1 oscillator clock as the source of fCLK by using the system clock control register (CKC).
[Register settings] Set the registers in the order of <1> to <5> below. <1> To select only running the realtime clock by the subsystem clock (for ultra-low current) in STOP mode or in HALT
mode while the CPU is also operating with the subsystem clock, set the RTCLPC bit to 1.
7
6
5
4
3
2
1
0
OSMC RTCLPC
WUTMMCK0
HIPREC
0/1
0
0
0
x
x
0
0
<2> Set the OSCSELS bit of the CMC register to 1 to make the XT1 oscillator operate. Also set the XTSEL bit to 1 in a product with 30 to 36 pins.
CMC
7
6
5
4
3
2
1
0
EXCLK 0
OSCSEL 0
EXCLKS 0
OSCSELS 1
XTSEL 0/1
AMPHS1 0/1
AMPHS0 0/1
AMPH 0
AMPHS0 and AMPHS1 bits: These bits are used to specify the oscillation mode of the XT1 oscillator.
<3> Clear the XTSTOP bit of the CSC register to 0 to start XT1 oscillation.
7
6
5
4
3
2
CSC MSTOP
XTSTOP
1
0
0
0
0
0
1
MIOEN 0
0
HIOSTOP 0
<4> Include code to wait for oscillation of the subsystem clock to become stable by using a timer or in other ways.
<5> Use the CSS bit of the CKC register to specify the XT1 oscillator clock as the source of the CPU/peripheral hardware clock.
7
6
5
4
3
CKC
CLS
CSS
MCS
MCM0
0
1
0
0
0
2
1
0
MCS1
MCM1
0
0
0
Remark x: Undefined
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6.6.4 State transitions of the CPU clock
Figure 6 - 22 shows the state transitions of the CPU clock in this product. Figure 6 - 22 State Transitions of the CPU Clock
Turning power on
CHAPTER 6 CLOCK GENERATOR
VDD Lower limit of the operating voltage range
(A)
(release from the reset state triggered by the LVD0 circuit or an external reset)
Release from the reset state
(O)
CPU: XT1/EXCLKS input;
at a HALT
(E)
CPU: XT1/EXCLKS input;
operating
(M)
CPU: X1/EXCLK input;
at a HALT
(N)
CPU: X1/EXCLK input;
at a STOP
(B)
CPU: High-speed on-chip oscillator; operating
(D)
CPU: X1/EXCLK input;
operating
(C)
CPU: Middle-speed on-chip oscillator; operating
(L)
(G)
CPU: High-speed on-chip oscillator; at a HALT
(H)
CPU: High-speed on-chip oscillator; at a STOP
(F) CPU: Low-speed on-chip oscillator; operating
(I)
CPU: High-speed on-chip oscillator; at a SNOOZE
(P) CPU: Low-speed on-chip oscillator; at a HALT
(J)
CPU: Middle-speed on-chip oscillator; at a HALT
CPU: Middle-speed on-chip oscillator; at a SNOOZE
(K)
CPU: Middle-speed on-chip oscillator; at a STOP
: State transitions of the CPU clock : Transitions of the CPU operating mode
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Table 6 - 2 (1/4) to Table 6 - 2 (4/4) show examples of transitions of the CPU clock and SFR settings.
Table 6 - 2 Examples of Transitions of the CPU Clock and SFR Settings (1/4)
(1) Transition to state (B) where the CPU is operating with the high-speed on-chip oscillator clock after release from the reset state (A) Scope of state transitions: (A) (B)
Clock after Transition High-speed on-chip oscillator
SFR Setting SFR setting not required (default state after release from the reset state)
(2) Transitions to state (B) where the CPU is operating with the high-speed on-chip oscillator clock Scope of state transitions: (C) (B), (D) (B), (E) (B), (F) (B)
(Sequence of setting the SFRs)
SFR Bit to be Set CSC Register
Clock after Transition
HIOSTOP
High-speed on-chip oscillator
0
Waiting for Oscillation Stabilization
5 µs
CSS 0
CKC Register MCM0 0
MCM1 0
Unnecessary if the high-speed on-chip oscillator clock is already
running
(3) Transitions to state (C) where the CPU is operating with the middle-speed on-chip oscillator clock Scope of state transitions: (B) (C), (D) (C), (E) (C), (F) (C)
(Sequence of setting the SFRs)
SFR Bit to be Set CSC Register
Clock after Transition
MIOEN
Middle-speed on-chip oscillator
1
Waiting for Oscillation Stabilization
1 µs
CSS 0
CKC Register MCM0 0
MCM1 1
Unnecessary if the middle-speed on-chip oscillator clock is already
running
Remark (A) to (P) in Table 6 - 2 correspond to (A) to (P) in Figure 6 - 22.
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Table 6 - 2 Examples of Transitions of the CPU Clock and SFR Settings (2/4)
(4) Transitions to state (D) where the CPU is operating with the high-speed system clock Scope of state transitions: (B) (D), (C) (D), (E) (D)Note 1, (F) (D)
(Sequence of setting the SFRs) SFR Bit to be Set
CMC RegisterNote 2
Clock after Transition X1 clock: 1 MHz fX 10 MHz
EXCLK OSCSEL AMPH
0
1
0
OSTS Register
Note 3
X1 clock: 10 MHz < fX 20 MHz
0
1
1
Note 3
External main clock
1
1
×
Note 3
CSC Register
MSTOP
OSTC Register
0
Must be
checked
0
Must be
checked
0
Need not
be
checked
CKC Register
CSS MCM0
0
1
0
1
0
1
Note 1. Note 2.
Note 3.
Unnecessary if these bits are already set
Unnecessary if the high-speed system clock is already running
Products with 30 to 36 pins do not support this transition. The clock operation mode control register (CMC) can be changed only once after release from the reset state. This register setting is not necessary if it has already been set. In the products with 30 to 36 pins, set XTSEL to 0. Set the oscillation stabilization time as follows. · Desired oscillation stabilization time counted by the oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time set by the oscillation stabilization time select register (OSTS)
Caution Set a clock after the supply voltage has reached the operating voltage range for the clock to be set (see CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C).
Remark (A) to (P) in Table 6 - 2 correspond to (A) to (P) in Figure 6 - 22.
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Table 6 - 2 Examples of Transitions of the CPU Clock and SFR Settings (3/4)
(5) Transitions to state (E) where the CPU is operating with the subsystem clock Scope of state transitions: (B) (E), (C) (E), (D) (E)Note 1
(Sequence of setting the SFRs) SFR Bit to be Set
CMC RegisterNote 2
CSC Register
Clock after Transition XT1 clock External subsystem clock
EXCLKS OSCSELS AMPHS1 AMPHS0
0
1
0/1
0/1
1
1
×
×
XTSTOP 0 ×
Waiting for Oscillation Stabilization
Necessary
Necessary
CKC Register
CSS
1 1
Note 1. Note 2.
Unnecessary if these bits are already set
Unnecessary if the subsystem clock is already running
Products with 30 to 36 pins do not support this transition. The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation instruction after release from the reset state. In the products with 30 to 36 pins, set XTSEL to 1.
(6) Transitions to state (F) where the CPU is operating with the low-speed on-chip oscillator clock Scope of state transitions: (B) (F), (C) (F), (D) (F)
(Sequence of setting the SFRs) SFR Bit to be Set
Clock after Transition Low-speed on-chip oscillator
CKSEL SELLOSC
1
Oscillation accuracy stabilization time
80 µs
Unnecessary if the lowspeed on-chip oscillator clock is already running
Remark 1. ×: Don't care. Remark 2. (A) to (P) in Table 6 - 2 correspond to (A) to (P) in Figure 6 - 22.
CKC Register CSS 1
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Table 6 - 2 Examples of Transitions of the CPU Clock and SFR Settings (4/4)
(7) Transitions from the CPU operating mode (B), (C), (D), (E), or (F) to the HALT mode (G), (J), (M), (O), or (P) Scope of state transitions: (B) (G), (C) (J), (D) (M), (E) (O), (F) (P)
Mode after Transition HALT mode
Executing a HALT instruction
Description
(8) Transitions from the CPU operating mode (B), (C), or (D) to the STOP mode (H), (K), or (N) Scope of state transitions: (B) (H), (C) (K), (D) (N)
(Setting sequence)
Mode after Transition
Description
STOP mode
Stopping peripheral functions that cannot operate in STOP mode
Setting the OSTS register
Confirming the value of the HIPREC bit is 1.
Executing a STOP instruction
When STOP or SNOOZE mode is released · FWKUP = 0 if the high-speed on-chip
oscillator is started at normal speed. · FWKUP = 1 if the high-speed on-chip
oscillator is started at high speed.
Only necessary if the CPU is shifting from the state of operating with the high-speed on-chip oscillator to the STOP mode
Only necessary if the CPU is shifting
from the state of operating
with the highspeed system clock to the STOP mode
Only necessary if the high-speed on-
chip oscillator is started at high
speed
(9) Transitions between a STOP mode (H) or (K) and SNOOZE mode (I) or (L) For details about the setting for switching from the STOP mode to the SNOOZE mode, see CHAPTER 23 STANDBY FUNCTION and descriptions of the SNOOZE mode functions of the on-chip peripheral modules.
Remark (A) to (P) in Table 6 - 2 correspond to (A) to (P) in Figure 6 - 22.
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6.6.5
Conditions before changing the CPU clock and processing after changing the CPU clock
The conditions before changing the CPU clock and processing after changing the CPU clock are shown below.
Table 6 - 3 Changing the CPU Clock (1/6)
CPU Clock
Before Change
After Change
Conditions before Change
Processing after Change
High-speed on-chip Middle-speed on-chip
oscillator clock
oscillator clock
X1 clock
The middle-speed on-chip oscillator is operating. Operating current can be reduced by
· MIOEN = 1
stopping the high-speed on-chip
X1 oscillation has become stable. · OSCSEL = 1, EXCLK = 0, MSTOP = 0,
XTSEL = 0Note 1
oscillator (HIOSTOP = 1) after checking that the CPU clock is changed.
· The oscillation stabilization time has elapsed.
External main system clock
External clock input from the EXCLK pin is enabled. · OSCSEL = 1, EXCLK = 1, MSTOP = 0,
XTSEL = 0Note 1
XT1 clock
XT1 oscillation has become stable. · OSCSELS = 1, EXCLKS = 0, XTSTOP = 0,
XTSEL = 1Note 1 · The oscillation stabilization time has elapsed.
External subsystem clock
External clock input from the EXCLKS pin is enabled. · OSCSELS = 1, EXCLKS = 1, XTSTOP = 0,
XTSEL = 1Note 1
Low-speed on-chip oscillator clock
The low-speed on-chip oscillator is selected. · SELLOSC = 1
Table 6 - 3 Changing the CPU Clock (2/6)
CPU Clock
Before Change
After Change
Middle-speed on- High-speed on-chip chip oscillator clock oscillator clock
X1 clock
External main system clock
XT1 clock
External subsystem clock
Low-speed on-chip oscillator clock
Conditions before Change
The high-speed on-chip oscillator is operating. · HIOSTOP = 0
X1 oscillation has become stable. · OSCSEL = 1, EXCLK = 0, MSTOP = 0,
XTSEL = 0Note 1 · The oscillation stabilization time has elapsed.
External clock input from the EXCLK pin is enabled. · OSCSEL = 1, EXCLK = 1, MSTOP = 0,
XTSEL = 0Note 1
XT1 oscillation has become stable. · OSCSELS = 1, EXCLKS = 0, XTSTOP = 0,
XTSEL = 1Note 1 · The oscillation stabilization time has elapsed.
External clock input from the EXCLKS pin is enabled. · OSCSELS = 1, EXCLKS = 1, XTSTOP = 0,
XTSEL = 1Note 1
The low-speed on-chip oscillator is selected. · SELLOSC = 1
Processing after Change
Operating current can be reduced by stopping the middle-speed on-chip oscillator (MIOEN = 0) after checking that the CPU clock is changed.
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Table 6 - 3 Changing the CPU Clock (3/6)
CPU Clock
Before Change
After Change
X1 clock
High-speed on-chip oscillator clock
Middle-speed on-chip oscillator clock
External main system clock
XT1 clockNote 2
External main system clock
External subsystem clockNote 2
Low-speed on-chip oscillator clock
High-speed on-chip oscillator clock
Middle-speed on-chip oscillator clock X1 clock XT1 clockNote 2
External subsystem clockNote 2
Low-speed on-chip oscillator clock
Conditions before Change
Processing after Change
The high-speed on-chip oscillator is enabled. · HIOSTOP = 0 · The oscillation stabilization time has elapsed.
X1 oscillation can be stopped (MSTOP = 1) after checking that the CPU clock is changed.
The middle-speed on-chip oscillator is operating. · MIOEN = 1
Transition is not possible.
--
XT1 oscillation has become stable. · OSCSELS = 1, EXCLKS = 0, XTSTOP = 0 · The oscillation stabilization time has elapsed.
X1 oscillation can be stopped (MSTOP = 1) after checking that the CPU clock is changed.
External clock input from the EXCLKS pin is enabled. · OSCSELS = 1, EXCLKS = 1, XTSTOP = 0
The XT1 oscillator is stopped. The low-speed on-chip oscillator is selected. · SELLOSC = 1
The high-speed on-chip oscillator is enabled. External main system clock input
· HIOSTOP = 0
can be disabled (MSTOP = 1) after
· The oscillation stabilization time has elapsed. checking that the CPU clock is
changed. The middle-speed on-chip oscillator is operating.
· MIOEN = 1
Transition is not possible.
--
XT1 oscillation has become stable. · OSCSELS = 1, EXCLKS = 0, XTSTOP = 0 · The oscillation stabilization time has elapsed.
External clock input from the EXCLKS pin is enabled. · OSCSELS = 1, EXCLKS = 1, XTSTOP = 0
External main system clock input can be disabled (MSTOP = 1) after checking that the CPU clock is changed.
The XT1 oscillator is stopped. The low-speed on-chip oscillator is selected. SELLOSC = 1
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Table 6 - 3 Changing the CPU Clock (4/6)
CPU Clock
Before Change
After Change
XT1 clock
High-speed on-chip oscillator clock
Middle-speed on-chip oscillator clock
X1 clockNote 2
External main system clockNote 2
External subsystem clock Low-speed on-chip oscillator clock
Conditions before Change
Processing after Change
The high-speed on-chip oscillator is operating and the high-speed on-chip oscillator clock is selected as the main system clock. · HIOSTOP = 0, MCS = 0, MCS1 = 0
XT1 oscillation can be stopped (XTSTOP = 1) after checking that the CPU clock is changed.
The middle-speed on-chip oscillator is operating and the middle-speed on-chip oscillator clock is selected as the main system clock. · MIOEN = 1, MCS = 0, MCS1 = 1
X1 oscillation has become stable and the highspeed system clock is selected as the main system clock. · OSCSEL = 1, EXCLK = 0, MSTOP = 0 · The oscillation stabilization time has elapsed. · MCS = 1
External clock input from the EXCLK pin is enabled and the high-speed system clock is selected as the main system clock. · OSCSEL = 1, EXCLK = 1, MSTOP = 0 · MCS = 1
Transition is not possible.
--
Transition is not possible.
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Table 6 - 3 Changing the CPU Clock (5/6)
CPU Clock
Before Change
After Change
External subsystem High-speed on-chip
clock
oscillator clock
Middle-speed on-chip oscillator clock
X1 clockNote 2
External main system clockNote 2
XT1 clock Low-speed on-chip oscillator clock
Conditions before Change
Processing after Change
The high-speed on-chip oscillator is operating and the high-speed on-chip oscillator clock is selected as the main system clock. · HIOSTOP = 0, MCS = 0, MCS1 = 0
External subsystem clock input can be disabled (XTSTOP = 1) after checking that the CPU clock is changed.
The middle-speed on-chip oscillator is operating and the middle-speed on-chip oscillator clock is selected as the main system clock. · MIOEN = 1, MCS = 0, MCS1 = 1
X1 oscillation has become stable and the highspeed system clock is selected as the main system clock. · OSCSEL = 1, EXCLK = 0, MSTOP = 0 · The oscillation stabilization time has elapsed. · MCS = 1
External clock input from the EXCLK pin is enabled and the high-speed system clock is selected as the main system clock. · OSCSEL = 1, EXCLK = 1, MSTOP = 0 · MCS = 1
Transition is not possible.
--
Transition is not possible.
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Table 6 - 3 Changing the CPU Clock (6/6)
CPU Clock
Before Change
After Change
Conditions before Change
Low-speed on-chip High-speed on-chip
oscillator clock
oscillator clock
The high-speed on-chip oscillator is operating and the high-speed on-chip oscillator clock is selected as the main system clock. · HIOSTOP = 0, MCS = 0, MCS1 = 0
Middle-speed on-chip oscillator clock
The middle-speed on-chip oscillator is operating and the middle-speed on-chip oscillator clock is selected as the main system clock. · MIOEN = 1, MCS = 0, MCS1 = 1
X1 clock
X1 oscillation has become stable and the highspeed system clock is selected as the main system clock. · OSCSEL = 1, EXCLK = 0, MSTOP = 0,
XTSEL = 0Note 1 · The oscillation stabilization time has elapsed. · MCS = 1
External main system clock
External clock input from the EXCLK pin is enabled and the high-speed system clock is selected as the main system clock. · OSCSEL = 1, EXCLK = 1, MSTOP = 0,
XTSEL = 0Note 1 · MCS = 1
XT1 clock
Transition is not possible.
Note 1. Note 2.
External subsystem clock
Transition is not possible.
Writing to the XTSEL bit is only possible in the products with 30 to 36 pins. Switching to this clock is only possible in the products with 40 to 128 pins.
Processing after Change --
--
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6.6.6 Time required for switchover of the CPU clock and main system clock
By setting bits 6, 4, 0 (CSS, MCM0, MCM1) of the system clock control register (CKC), the CPU clock can be switched between the main system clock and subsystem clock, the main system clock can be switched between the on-chip oscillator clock and high-speed system clock, and the on-chip oscillator clock can be switched between the high-speed on-chip oscillator clock and middle-speed on-chip oscillator clock. In actual operation, the clock is not switched immediately after writing to the CKC register; the CPU continues to operate with the prior clock for several clock cycles after writing proceeds (see Table 6 - 4 to Table 6 - 7). Whether the source of the CPU clock is the main system clock or subsystem clock can be ascertained from bit 7 (CLS) of the CKC register. Whether the source of the main system clock is the high-speed system clock or main on-chip oscillator clock can be ascertained from bit 5 (MCS) of the CKC register. Whether the source of the main on-chip oscillator clock is the high-speed on-chip oscillator clock or middle-speed on-chip oscillator clock can be ascertained from bit 1 (MCS1) of the CKC register. When the CPU clock is switched, the peripheral hardware clock is also switched.
Table 6 - 4 Maximum Time Required for Main System Clock Switchover
Clock A
Switching directions
Clock B
fOCO
fMX
fIH
fIM
fMAIN
fSUB
Remark See Table 6 - 5. See Table 6 - 6. See Table 6 - 7.
Table 6 - 5 Maximum Number of Clock Cycles Required for fOCO fMX
Set Value before Switchover MCM0
Set Value after Switchover
MCM0
0 (fMAIN = fOCO)
1 (fMAIN = fMX)
0 (fMAIN = fOCO)
fMX fOCO fMX < fOCO
2 cycles 2 fOCO/fMX cycles
1 (fMAIN = fMX)
fMX fOCO fMX < fOCO
2 fMX/fOCO cycles 2 cycles
Table 6 - 6 Maximum Number of Clock Cycles Required for fIH fIM
Set Value before Switchover MCM1
Set Value after Switchover
MCM1
0 (fOCO = fIH)
1 (fOCO = fIM)
0 (fOCO = fIH)
fIM fIH fIM < fIH
2 cycles 2 fIH/fIM cycles
1 (fOCO = fIM)
fIM fIH fIM < fIH
2 fIM/fIH cycles 2 cycles
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Table 6 - 7 Maximum Number of Clock Cycles Required for fMAIN fSUB
Set Value before Switchover CSS
Set Value after Switchover
CSS
0 (fCLK = fMAIN)
1 (fCLK = fSUB)
0 (fCLK = fMAIN)
1 + 2 fMAIN/fSUB cycles
1 (fCLK = fSUB)
3 cycles
Remark 1. The number of clock cycles listed in Table 6 - 5, Table 6 - 6, and Table 6 - 7 is the number of cycles of the CPU clock before switchover.
Remark 2. Calculate the number of clock cycles in Table 6 - 5, Table 6 - 6, and Table 6 - 7 by rounding up the number after the decimal position.
Example: When switching the main system clock from the high-speed on-chip oscillator clock (8 MHz selected) to the high-speed system clock (in this case, fIH = 8 MHz, fMX = 10 MHz) 1 + fIH/fMX = 1 + 8/10 = 1 + 0.8 = 1.8 2 cycles
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6.6.7 Conditions before clock oscillation is stopped
The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and conditions before the clock oscillation is stopped. When stopping the clock, confirm the conditions before clock oscillation is stopped.
Table 6 - 8 Conditions Before the Clock Oscillation is Stopped and Flag Settings
Clock
Conditions Before Clock Oscillation is Stopped (External Clock Input is Disabled)
Flag Settings of the SFRs
High-speed on-chip oscillator clock MCS1 = 1, MCS = 1 or CLS = 1 (The CPU is operating with a clock other than the highspeed on-chip oscillator clock.)
HIOSTOP = 1
Middle-speed on-chip oscillator clock
MCS1 = 0, MCS = 1 or CLS = 1 (The CPU is operating with a clock other than the middlespeed on-chip oscillator clock.)
MIOEN = 0
X1 clock External main system clock
MCS = 0 or CLS = 1 (The CPU is operating with a clock other than the highspeed system clock.)
MSTOP = 1
XT1 clock External subsystem clock
CLS = 0
XTSTOP = 1
(The CPU is operating with a clock other than the subsystem
clock.)
Low-speed on-chip oscillator clockNote
CLS = 0
SELLOSC = 0
(The CPU is operating with a clock other than the low-speed WUTMMCK0 = 0
on-chip oscillator clock.)
Note
The low-speed on-chip oscillator clock is not stopped while the WDT is operating or when fIL is selected as the source clock for use in waiting by the SNOOZE mode sequencer.
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6.7
Resonator and Oscillator Constants
For the resonators for which operation has been verified and their oscillator constants (reference values), see the target product page on the Renesas Web site.
Caution 1. The constants for these oscillator circuits are reference values based on specific environments set up for evaluation by the manufacturers. For actual applications, request evaluation by the manufacturer of the oscillator circuit mounted on a board. Furthermore, if you are switching from a different product to this microcontroller, and whenever you change the board, again request evaluation by the manufacturer of the oscillator circuit mounted on the new board.
Caution 2. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the RL78 microcontroller so that the internal operation conditions are within the specifications of the DC and AC characteristics.
Figure 6 - 23 Examples of External Circuits
(a) X1 oscillation
VSS X1
X2 Rd
C1 C2
(b) XT1 oscillation
VSS XT2 Rd
XT1
C4 C3
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
CHAPTER 7 TIMER ARRAY UNIT (TAU)
The number of units or channels of the timer array unit differs, depending on the product.
Units
Channels
30-, 32-, 36-, 40-, 44-, 48-, 52-, and 64-pin
80- and 100-pin
128-pin
Unit 0
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Unit 1
Channel 0
--
Channel 1
--
Channel 2
--
Channel 3
--
Channel 4
--
--
Channel 5
--
--
Channel 6
--
--
Channel 7
--
--
Caution 1. The presence or absence of timer I/O pins depends on the product. See Table 7 - 2 Timer I/O Pins Provided in Each Product for details.
Caution 2. Most of the following descriptions in this chapter use the 128-pin products as an example.
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The timer array unit has eight 16-bit timers. Each 16-bit timer is called a channel and can be used as an independent timer. In addition, two or more channels can be used to create a high-accuracy timer.
TIMER ARRAY UNIT
channel 0 channel 1
16-bit timers
channel 2
channel 6 channel 7
For details about each function, see the table below.
Independent channel operation function
· Interval timer ( refer to 7.8.1) · Square wave output ( refer to 7.8.1) · External event counter ( refer to 7.8.2) · DividerNote ( refer to 7.8.3) · Input pulse interval measurement ( refer to 7.8.4)
· Measurement of high-/low-level width of input signal ( refer to 7.8.5)
· Delay counter ( refer to 7.8.6)
Note
Only channel 0 of unit 0 supports this.
Simultaneous channel operation function
· One-shot pulse output ( refer to 7.9.1) · PWM output ( refer to 7.9.2) · Multiple PWM output ( refer to 7.9.3)
It is possible to use the 16-bit timer of channels 1 and 3 of the units 0 and 1 as two 8-bit timers (higher and lower). The functions that can use channels 1 and 3 as 8-bit timers are as follows: · Interval timer (upper or lower 8-bit timer)/square wave output (lower 8-bit timer only) · External event counter (lower 8-bit timer only) · Delay counter (lower 8-bit timer only)
Channel 7 of unit 0 can be used to realize LIN-bus communication operating in combination with UART2 of the serial array unit.
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7.1
Functions of Timer Array Unit
Timer array unit has the following functions.
7.1.1 Independent channel operation function
By operating a channel independently, it can be used for the following purposes without being affected by the operation mode of other channels.
(1) Interval timer Each timer of a unit can be used as a reference timer that generates an interrupt (INTTMmn) at fixed intervals.
Operation clock
Compare operation Channel n
Interrupt signal (INTTMmn)
(2) Square wave output A toggle operation is performed each time INTTMmn interrupt is generated and a square wave with a duty factor of 50% is output from a timer output pin (TOmn).
Operation clock
Compare operation Channel n
Timer output (TOmn)
(3) External event counter Each timer of a unit can be used as an event counter that generates an interrupt when the number of the valid edges of a signal input to the timer input pin (TImn) has reached a specific value.
Timer input (TImn)
Edge detection
Compare operation Channel n
Interrupt signal (INTTMmn)
(4) Divider function (only channel 0 of unit 0) A clock input from a timer input pin (TI00) is divided and output from an output pin (TO00).
Timer input (TI00)
Compare operation Channel 0
Timer output (TO00)
(5) Input pulse interval measurement Counting is started by the valid edge of a pulse signal input to a timer input pin (TImn). The count value of the timer is captured at the valid edge of the next pulse. In this way, the interval of the input pulse can be measured.
Timer input
(TImn) Edge detection
Capture operation Channel n
00H xxH Start Capture
(Remarks are listed on the next page.)
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(6) Measurement of high-/low-level width of input signal Counting is started by a single edge of the signal input to the timer input pin (TImn), and the count value is captured at the other edge. In this way, the high-level or low-level width of the input signal can be measured.
Timer input (TImn)
Edge detection
Capture operation Channel n
00H xxH Start Capture
(7) Delay counter Counting is started at the valid edge of the signal input to the timer input pin (TImn), and an interrupt is generated after any delay period.
Timer input
(TImn) Edge detection
Compare operation Channel n
Interrupt signal (INTTMmn)
Start
Remark 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) Remark 2. The presence or absence of timer I/O pins of channel 0 to 7 depends on the product. See Table 7 - 2 Timer
I/O Pins Provided in Each Product for details.
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7.1.2 Simultaneous channel operation function
By using the combination of a master channel (a reference timer mainly controlling the cycle) and slave channels (timers operating according to the master channel), channels can be used for the following purposes.
(1) One-shot pulse output Two channels are used as a set to generate a one-shot pulse with a specified output timing and a specified pulse width.
Timer input (TImn)
Edge detection
Compare operation Channel n (master)
Compare operation Channel p (slave)
Interrupt signal (INTTMmn)
Output timing
Pulse width
Timer output (TOmp)
Set (Master)
Start (Master)
Reset (Slave)
(2) PWM (Pulse Width Modulation) output Two channels are used as a set to generate a pulse with a specified period and a specified duty factor.
Operation clock
Compare operation Channel n (master)
Interrupt signal (INTTMmn)
Compare operation Channel p (slave)
Timer output (TOmp)
Duty Period
(3) Multiple PWM (Pulse Width Modulation) output By extending the PWM function and using one master channel and two or more slave channels, up to seven types of PWM signals that have a specific period and a specified duty factor can be generated.
Operation clock
Compare operation Channel n (master)
Interrupt signal (INTTMmn)
Compare operation Channel p (slave)
Timer output (TOmp)
Duty Period
Compare operation Channel q (slave)
Timer output (TOmq)
Duty Period
Caution
For details about the rules of simultaneous channel operation function, see 7.4.1 Basic rules of simultaneous channel operation function.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7), p, q: Slave channel number (n < p < q 7)
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7.1.3 8-bit timer operation function (channels 1 and 3 only)
The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8bit timer channels. This function can only be used for channels 1 and 3.
Caution
There are several rules for using 8-bit timer operation function. For details, see 7.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only).
7.1.4 LIN-bus supporting function (channel 7 of unit 0 only)
Timer array unit is used to check whether signals received in LIN-bus communication match the LIN-bus communication format.
(1) Detection of wakeup signal The timer starts counting at the falling edge of a signal input to the serial data input pin (RxD2) of UART2 and the count value of the timer is captured at the rising edge. In this way, a low-level width can be measured. If the lowlevel width is greater than a specific value, it is recognized as a wakeup signal.
(2) Detection of break field The timer starts counting at the falling edge of a signal input to the serial data input pin (RxD2) of UART2 after a wakeup signal is detected, and the count value of the timer is captured at the rising edge. In this way, a low-level width is measured. If the low-level width is greater than a specific value, it is recognized as a break field.
(3) Measurement of pulse width of sync field After a break field is detected, the low-level width and high-level width of the signal input to the serial data input pin (RxD2) of UART2 are measured. From the bit interval of the sync field measured in this way, a baud rate is calculated.
Remark
For details about setting up the operations used to implement the LIN-bus, see 7.3.15 Input switch control register (ISC) and 7.8.5 Operation for input signal high-/low-level width measurement.
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7.2
Configuration of Timer Array Unit
Timer array unit includes the following hardware.
Table 7 - 1 Configuration of Timer Array Unit
Item
Configuration
Timer/counter
Timer counter register mn (TCRmn)
Register
Timer data register mn (TDRmn)
Timer input
TI00 to TI07, TI10 to TI17Note 1, RxD2 pin (for LIN-bus)
Timer output
TO00 to TO07, TO10 to TO17 pinsNote 1, output controller
Control registers
<Registers of unit setting block> · Peripheral enable register 0 (PER0) · Peripheral reset control register 0 (PRR0) · Timer clock select register m (TPSm) · Timer channel enable status register m (TEm) · Timer channel start register m (TSm) · Timer channel stop register m (TTm) · Timer input select register 0 (TIS0) · Timer input select register 1 (TIS1) · Timer output enable register m (TOEm) · Timer output register m (TOm) · Timer output level register m (TOLm) · Timer output mode register m (TOMm)
<Registers of each channel>
· Timer mode register mn (TMRmn)
· Timer status register mn (TSRmn) · Input switch control register (ISC)
· Noise filter enable registers 1, 2 (NFEN1, NFEN2) · Port function output enable registers (PFOEx)Note 2 · Port mode control A registers (PMCAxx)Note 2 · Port mode control T registers (PMCTxx)Note 2 · Port mode control E registers (PMCEx)Note 2 · Port mode registers (PMxx)Note 2 · Port registers (Pxx)Note 2
Note 1. Note 2.
The presence or absence of timer I/O pins of channel 0 to 7 depends on the product. See Table 7 - 2 Timer I/O Pins Provided in Each Product for details. The port mode control A registers (PMCAxx), port mode control T registers (PMCTxx), port mode control E registers (PMCEx), port function output enable register 0 (PFOE0), port mode registers (PMxx), and port registers (Pxx) to be set differ depending on the product. For details, see 4.5.4 Examples of register settings for port and alternate functions.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
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The presence or absence of timer I/O pins in each timer array unit channel depends on the product.
Table 7 - 2 Timer I/O Pins Provided in Each Product
Timer array unit channels
128-pin
100-pin
80-pin
I/O Pins of Each Product
64-pin
52-pin
44- and 48-pin
40-pin
30-, 32-, and 36-pin
Channel 0
TI00, TO00
Channel 1
TI01/TO01
Channel 2
TI02/TO02
Unit 0
Channel 3
TI03/TO03
Channel 4
TI04/TO04
(TI04/TO04)
Channel 5
TI05/TO05
TI05/TO05
(TI05/TO05)
Channel 6
TI06/TO06
TI06/TO06
(TI06/TO06)
Channel 7
TI07/TO07
TI07/TO07
(TI07/TO07)
Channel 0
TI10/TO10
×
×
×
×
×
Channel 1
TI11/TO11
×
×
×
×
×
Channel 2
TI12/TO12
×
×
×
×
×
Unit 1
Channel 3
TI13/TO13
×
×
×
×
×
Channel 4
TI14/TO14
×
×
×
×
×
×
×
Channel 5
TI15/TO15
×
×
×
×
×
×
×
Channel 6
TI16/TO16
×
×
×
×
×
×
×
Channel 7
TI17/TO17
×
×
×
×
×
×
×
Remark 1. When timer input and timer output are shared by the same pin, either only timer input or only timer output can be used. Remark 2. ×: The channel is not available. Remark 3. Pins in the parentheses indicate an alternate port when the bit 0 of the peripheral I/O redirection register (PIOR) is set to 1.
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Figure 7 - 1 shows the block diagram of the timer array unit. Figure 7 - 1 Entire Configuration of Timer Array Unit 0 (Example: 64-Pin Products)
Timer clock select register 0 (TPS0)
PRS031 PRS030 PRS021 PRS020 PRS013 PRS012 PRS011 PRS010 PRS003 PRS002 PRS001 PRS000
2
2
4
4
fCLK
Peripheral enable register 0 TAU0EN (PER0)
Timer input select register 1 (TIS1)
TIS10
Selector
TI00
Event input from ELCL
Timer input select register 1 (TIS1)
TIS11
Selector
TI01 Event input from ELCL
Timer input select register 0 (TIS0) TIS02 TIS01 TIS00
TI02 TI03
Prescaler
fCLK/21, fCLK/22, fCLK/28, fCLK/210, fCLK/24, fCLK/26 fCLK/212, fCLK/214
Selector
fCLK/20 to fCLK/215 Selector
Selector CK03
CK02
Selector CK01 CK00
Channel 0 Channel 1 Channel 2 Channel 3
fSUB fIL fIMP
TI05 Event input from ELCL
Input switch control register (ISC)
ISC1
Selector
TI04 TI06
Selector
TI07
RxD2 (Serial input pin)
Channel 4 Channel 5 Channel 6 Channel 7 (LIN-bus supported)
PFOE00
TO00 Event signal INTTM00 output to ELCL (Timer interrupt)
PFOE01
TO01 Event signal INTTM01 output to ELCL INTTM01H PFOE02
TO02 Event signal INTTM02 output to ELCL
PFOE03
TO03 Event signal INTTM03 output to ELCL INTTM03H
PFOE04
TO04 Event signal INTTM04 output to ELCL
PFOE05
TO05 Event signal INTTM05 output to ELCL
PFOE06
TO06 Event signal INTTM06 output to ELCL
PFOE07
TO07 Event signal INTTM07 output to ELCL
Remark
fSUB:Subsystem clock frequency fIL:Low-speed on-chip oscillator clock frequency fIMP:Middle-speed on-chip oscillator peripheral clock frequency
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RL78/G23 Figure 7 - 2 Internal Block Diagram of Channel 0 of Timer Array Unit 0
CHAPTER 7 TIMER ARRAY UNIT (TAU)
Selector Operating
clock selection
CK00
CK01
Timer input select register 1 (TIS1)
TIS10
TI00 Event input from ELCL
fMCK
Edge detection
Trigger selection
Count clock selection
fTCLK Timer controller
Mode selection
Output controller
Interrupt controller
Output latch
PFOE00
(Pxx)
PMxx
TO00
Event signal output to ELCL
INTTM0n (Timer interrupt)
Timer counter register 0n (TCR0n) Timer data register 0n (TDR0n)
Timer status register 0n (TSR0n)
OVF Overflow 0n
Channel 0
CKS0n1 CKS0n0 CCS0n STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3 MD0n2 MD0n1 MD0n0 Timer mode register 0n (TMR0n)
Interrupt signal to the slave channel
Figure 7 - 3 Internal Block Diagram of Channel 1 of Timer Array Unit 0
Selector Operating
clock selection
Timer input select register 1 (TIS1)
TIS11
CK00 CK01 CK02 CK03
TI01
Event input from ELCL
Interrupt signal from the master channel
Count clock selection
fMCK
Edge detection
fTCLK Timer controller
Mode selection
Output controller
Interrupt controller
Output latch
PFOE01
(Pxx)
PMxx
TO01
Event signal output to ELCL
INTTM0n (Timer interrupt)
Trigger selection
Timer counter register 0n (TCR0n) Timer data register 0n (TDR0n)
Timer status register 0n (TSR0n)
OVF Overflow 0n
8-bit timer controller
Mode selection
Interrupt controller
INTTM0nH (Timer interrupt)
Channel 1
CKS0n1 CKS0n0
CCS0n
SPLIT 0n
STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3
MD0n2 MD0n1 MD0n0
Timer mode register 0n (TMR0n)
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Figure 7 - 4 Internal Block Diagram of Channels 2, 4, and 6 of Timer Array Unit 0
TI0n
CK00 CK01
Operating clock selection
Interrupt signal from the master channel
Count clock selection
fMCK
Edge detection
fTCLK Timer controller
Mode selection
Output controller
Interrupt controller
Output latch
PFOE0n
(Pxx)
PMxx
TO0n
Event signal output to ELCL
INTTM0n (Timer interrupt)
Trigger selection
Slave/master controller
Timer counter register 0n (TCR0n) Timer data register 0n (TDR0n)
Timer status register 0n (TSR0n)
OVF Overflow 0n
Channel n
CKS0n1CKS0n0 CCS0n
MAS TER0n
STS0n2
STS0n1
STS0n0
CIS0n1
CIS0n0
MD0n3
MD0n2
MD0n1
MD0n0
Timer mode register 0n (TMR0n)
Interrupt signal to the slave channel
Remark n = 2, 4, 6
Figure 7 - 5 Internal Block Diagram of Channel 3 of Timer Array Unit 0
TI0n
CK00 CK01 CK02 CK03
Operating clock selection
Interrupt signal from the master channel
Count clock selection
fMCK
Edge detection
fTCLK Timer controller
Mode selection
Output controller
Interrupt controller
Output latch
PFOE03
(Pxx)
PMxx
TO03
Event signal output to ELCL
INTTM0n (Timer interrupt)
Trigger selection
Timer counter register 0n (TCR0n) Timer data register 0n (TDR0n)
Timer status register 0n (TSR0n)
OVF Overflow 0n
8-bit timer controller
Mode selection
Interrupt controller
INTTM0nH (Timer interrupt)
Channel 3
CKS0n1 CKS0n0
CCS0n
SPLIT 0n
STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3
MD0n2 MD0n1 MD0n0
Timer mode register 0n (TMR0n)
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RL78/G23 Figure 7 - 6 Internal Block Diagram of Channel 5 of Timer Array Unit 0
CHAPTER 7 TIMER ARRAY UNIT (TAU)
Selector Operating
clock selection
CK00
CK01
Timer input select register 0 (TIS0) TIS02 TIS01 TIS00
fSUB fIL
fIMP TI05 Event input from ELCL
Interrupt signal from the master channel
Count clock selection
fMCK
Edge detection
Trigger selection
fTCLK Timer controller
Mode selection
Output controller
Interrupt controller
Timer counter register 05 (TCR05) Timer data register 05 (TDR05)
Timer status register 05 (TSR05)
OVF Overflow 05
Output latch
PFOE05
(Pxx)
PMxx
TO05
Event signal output to ELCL
INTTM05 (Timer interrupt)
Channel 5
CKS051CKS050 CCS05 STS052 STS051 STS050 CIS051 CIS050 MD053 MD052 MD051 MD050 Timer mode register 05 (TMR05)
Figure 7 - 7 Internal Block Diagram of Channel 7 of Timer Array Unit 0
Interrupt signal from the master channel
CK00
CK01
fMCK
Count clock selection
Selector Operating
clock selection
Trigger selection
TI07 RxD2
ISC1 Input switch control register (ISC)
Edge detection
fTCLK Timer controller
Mode selection
Output controller
Interrupt controller
Output latch
PFOE07
(Pxx)
PMxx
TO07
Event signal output to ELCL
INTTM07 (Timer interrupt)
Timer counter register 07 (TCR07) Timer data register 07 (TDR07)
Timer status register 07 (TSR07)
OVF Overflow 07
Channel 7
CKS071 CKS070 CCS07 STS072 STS071 STS070 CIS071 CIS070 MD073 MD072 MD071 MD070 Timer mode register 07 (TMR07)
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
7.2.1 Timer counter register mn (TCRmn)
The TCRmn register is a 16-bit read-only register used to count clocks. The value of this counter is incremented or decremented in synchronization with the rising edge of a count clock. Whether the counter is incremented or decremented depends on the operation mode that is selected by the MDmn3 to MDmn0 bits of timer mode register mn (TMRmn) (refer to 7.3.4 Timer mode register mn (TMRmn)).
Figure 7 - 8 Format of Timer Counter Register mn (TCRmn)
Address: After reset: R/W:
F0180H, F0181H (TCR00) to F018EH, F018FH (TCR07), F01C0H, F01C1H (TCR10) to F01CEH, F01CFH (TCR17) FFFFH R
F0181H (TCR00)
F0180H (TCR00)
Symbol 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
TCRmn
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
The count value can be read by reading timer counter register mn (TCRmn). The count value is set to FFFFH in the following cases. · When the reset signal is generated · When the TAUmRES bit of peripheral reset control register 0 (PRR0) is cleared · When counting of the slave channel has been completed in the PWM output mode · When counting of the slave channel has been completed in the delay count mode · When counting of the master/slave channel has been completed in the one-shot pulse output mode · When counting of the slave channel has been completed in the multiple PWM output mode The count value is cleared to 0000H in the following cases. · When the start trigger is input in the capture mode · When capturing has been completed in the capture mode
Caution
The count value is not captured to timer data register mn (TDRmn) even when the TCRmn register is read.
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The value read from the TCRmn register varies depending on the change to the operation mode and operating state as shown in the table below.
Table 7 - 3 Timer Counter Register mn (TCRmn) Read Value in Various Operation Modes
Operation Mode
Count Mode
Value Read from the Timer Counter Register mn (TCRmn)Note
Value when the operation mode is
changed after releasing reset
Value when count operation is
temporarily stopped (TTmn = 1)
Value when the operation mode is changed after count
operation was temporarily stopped
(TTmn = 1)
Value when waiting for a start trigger after
one count
Interval timer mode Countdown
FFFFH
Value when counting
Undefined
--
is stopped
Capture mode
Count-up
0000H
Value when counting
Undefined
--
is stopped
Event counter mode Countdown
FFFFH
Value when counting
Undefined
--
is stopped
One-count mode Countdown
FFFFH
Value when counting is stopped
Undefined
FFFFH
Capture & one-count Count-up mode
0000H
Value when counting is stopped
Undefined
Captured value of TDRmn register + 1
Note
This indicates the value read from the TCRmn register when channel n has stopped operating as a timer (TEmn = 0) and has been enabled to operate as a counter (TSmn = 1). The read value is held in the TCRmn register until the count operation starts.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
7.2.2 Timer data register mn (TDRmn)
This is a 16-bit register from which a capture function and a compare function can be selected. The capture or compare function can be switched by selecting an operation mode by using the MDmn3 to MDmn0 bits of timer mode register mn (TMRmn). The value of the TDRmn register can be changed at any time. This register can be read or written in 16-bit units. In addition, for the TDRm1 and TDRm3 registers, while in the 8-bit timer mode (when the SPLITm1, SPLITm3 bits of timer mode registers m1 and m3 (TMRm1, TMRm3) are 1), it is possible to read and write the data in 8-bit units, with TDRm1H and TDRm3H used as the higher 8 bits, and TDRm1L and TDRm3L used as the lower 8 bits. The value of this register is 0000H following a reset.
Figure 7 - 9 Format of Timer Data Register mn (TDRmn) (n = 0, 2, 4 to 7)
Address:
After reset: R/W:
FFF18H, FFF19H (TDR00), FFF64H, FFF65H (TDR02), FFF68H, FFF69H (TDR04) to FFF6EH, FFF6FH (TDR07), FFF70H, FFF71H (TDR10), FFF74H, FFF75H (TDR12), FFF78H, FFF79H (TDR14) to FFF7EH, FFF7FH (TDR17) 0000H R/W
FFF19H (TDR00)
FFF18H (TDR00)
Symbol 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
TDRmn
Figure 7 - 10 Format of Timer Data Register mn (TDRmn) (n = 1, 3)
Address: After reset: R/W:
FFF1AH, FFF1BH (TDR01), FFF66H, FFF67H (TDR03), FFF72H, FFF73H (TDR11), FFF76H, FFF77H (TDR13) 0000H R/W
FFF1BH (TDR01H)
FFF1AH (TDR01L)
Symbol 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
TDRmn
(i) When timer data register mn (TDRmn) is used as compare register Counting down is started from the value set to the TDRmn register. When the count value reaches 0000H, an interrupt signal (INTTMmn) is generated. The TDRmn register holds its value until it is rewritten.
Caution The TDRmn register does not perform a capture operation even if a capture trigger is input, when it is set to the compare function.
(ii) When timer data register mn (TDRmn) is used as capture register The count value of timer counter register mn (TCRmn) is captured to the TDRmn register when the capture trigger is input. A valid edge of the TImn pin can be selected as the capture trigger. This selection is made by timer mode register mn (TMRmn).
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
7.3
Registers to Control the Timer Array Unit
The following registers are used to control the timer array unit.
· Peripheral enable register 0 (PER0) · Peripheral reset control register 0 (PRR0) · Timer clock select register m (TPSm) · Timer mode register mn (TMRmn) · Timer status register mn (TSRmn) · Timer channel enable status register m (TEm) · Timer channel start register m (TSm) · Timer channel stop register m (TTm) · Timer input select register 0 (TIS0) · Timer input select register 1 (TIS1) · Timer output enable register m (TOEm) · Timer output register m (TOm) · Timer output level register m (TOLm) · Timer output mode register m (TOMm) · Input switch control register (ISC) · Noise filter enable registers 1, 2 (NFEN1, NFEN2) · Port mode control A registers (PMCAxx) · Port mode control T registers (PMCTxx) · Port mode control E registers (PMCEx) · Port mode registers (PMxx) · Port registers (Pxx) · Port function output enable registers (PFOEx)
Caution
Which registers and bits are included depends on the product. Be sure to set bits that are not mounted to their initial values.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
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7.3.1 Peripheral enable register 0 (PER0)
The PER0 register is used to enable or disable the supply of a clock signal to various on-chip peripheral modules. Clock supply to an on-chip peripheral module that is not to be used can be stopped to decrease power consumption and noise. If timer array unit 0 is to be used, be sure to set bit 0 (TAU0EN) of this register to 1. If timer array unit 1 is to be used, be sure to set bit 1 (TAU1EN) of this register to 1. The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 7 - 11 Format of Peripheral Enable Register 0 (PER0)
Address: After reset: R/W:
F00F0H 00H R/W
Symbol
<7>
PER0 RTCWEN
<6> IICA1EN
<5> ADCEN
<4> IICA0EN
<3> SAU1EN
<2> SAU0EN
<1> TAU1EN
<0> TAU0EN
TAU1EN
Control of supply of an input clock to timer array unit 1
0
Stops supply of an input clock.
· The SFRs used by timer array unit 1 cannot be written.
· When an SFR used by timer array unit 1 is read, the value returned is 00H or 0000H.
1
Enables supply of an input clock.
· The SFRs used by timer array unit 1 can be read and written.
TAU0EN
Control of supply of an input clock to timer array unit 0
0
Stops supply of an input clock.
· The SFRs used by timer array unit 0 cannot be written.
· When an SFR used by timer array unit 0 is read, the value returned is 00H or 0000H.
1
Enables supply of an input clock.
· The SFRs used by timer array unit 0 can be read and written.
Caution 1. When setting a timer array unit, make sure that the setting of the TAUmEN bit is 1 before setting the following registers. If TAUmEN = 0, the values of the registers which control the timer array unit are cleared to 00H and writing to them is ignored (except for timer input select registers 0, 1 (TIS0, TIS1), input switch control register (ISC), noise filter enable registers 1, 2 (NFEN1, NFEN2), port mode control A registers 0, 1 (PMCA0, PMCA1), port mode control T registers 0, 3, 6 (PMCT0, PMCT3, PMCT6), port mode control E registers 0, 1 (PMCE0, PMCE1), port mode registers 0, 1, 3, 4, 6, 10, 14 (PM0, PM1, PM3, PM4, PM6, PM10, PM14), port registers 0, 1, 3, 4, 6, 10, 14 (P0, P1, P3, P4, P6, P10, P14), and port function output enable register 0 (PFOE0)). · Timer clock select register m (TPSm) · Timer mode register mn (TMRmn) · Timer status register mn (TSRmn) · Timer channel enable status register m (TEm) · Timer channel start register m (TSm) · Timer channel stop register m (TTm) · Timer output enable register m (TOEm) · Timer output register m (TOm) · Timer output level register m (TOLm) · Timer output mode register m (TOMm)
Caution 2. The functions that are mounted depend on the product. For details on the PER0 register, see the description in CHAPTER 6 CLOCK GENERATOR.
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
7.3.2 Peripheral reset control register 0 (PRR0)
The PRR0 register is used to control resetting of the on-chip peripheral modules. Each bit in this register controls resetting and release from the reset state of the corresponding on-chip peripheral module. To place timer array unit 0 in the reset state, be sure to set bit 0 (TAU0RES) of this register to 1. To place timer array unit 1 in the reset state, be sure to set bit 1 (TAU1RES) of this register to 1. The PRR0 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 7 - 12 Format of Peripheral Reset Control Register 0 (PRR0)
Address: After reset: R/W:
F00F1H 00H R/W
Symbol
7
PRR0
0
<6>
<5>
<4>
<3>
<2>
<1>
<0>
IICA1RES ADCRES IICA0RES SAU1RES SAU0RES TAU1RES TAU0RES
TAU1RES
Control resetting of timer array unit 1
0
Timer array unit 1 is released from the reset state.
1
Timer array unit 1 is in the reset state.
· The SFRs for use with timer array unit 1 are initialized.
TAU0RES
Control resetting of timer array unit 0
0
Timer array unit 0 is released from the reset state.
1
Timer array unit 0 is in the reset state.
· The SFRs for use with timer array unit 0 are initialized.
Caution The functions that are mounted depend on the product. For details on the PRR0 register, see the description in CHAPTER 24 RESET FUNCTION.
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
7.3.3 Timer clock select register m (TPSm)
The TPSm register is a 16-bit register used to select two types or four types of operation clocks (CKm0, CKm1, CKm2, CKm3) that are commonly supplied to each channel. CKm0 is selected by using bits 3 to 0 of the TPSm register, and CKm1 is selected by using bits 7 to 4 of the TPSm register. In addition, only for channels 1 and 3, CKm2 and CKm3 can be also selected. CKm2 is selected by using bits 9 and 8 of the TPSm register, and CKm3 is selected by using bits 13 and 12 of the TPSm register. Rewriting of the TPSm register during timer operation is possible only in the following cases.
If the PRSm00 to PRSm03 bits can be rewritten (n = 0 to 7): All channels for which CKm0 is selected as the operation clock (CKSmn1, CKSmn0 = 0, 0) are stopped (TEmn = 0).
If the PRSm10 to PRSm13 bits can be rewritten (n = 0 to 7): All channels for which CKm1 is selected as the operation clock (CKSmn1, CKSmn0 = 0, 1) are stopped (TEmn = 0).
If the PRSm20 and PRSm21 bits can be rewritten (n = 1, 3): All channels for which CKm2 is selected as the operation clock (CKSmn1, CKSmn0 = 1, 0) are stopped (TEmn = 0).
If the PRSm30 and PRSm31 bits can be rewritten (n = 1, 3): All channels for which CKm3 is selected as the operation clock (CKSmn1, CKSmn0 = 1, 1) are stopped (TEmn = 0).
The TPSm register can be set by a 16-bit memory manipulation instruction. The value of this register is 0000H following a reset.
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Figure 7 - 13 Format of Timer Clock Select Register m (TPSm) (1/2)
Address: After reset: R/W:
F01B6H, F01B7H (TPS0), F01F6H, F01F7H (TPS1) 0000H R/W
Symbol
15
TPSm
0
14
13
12
11
0
PRSm31 PRSm30
0
10
9
8
0
PRSm21 PRSm20
7 PRSm13
6 PRSm12
5 PRSm11
4 PRSm10
3 PRSm03
2 PRSm02
1 PRSm01
0 PRSm00
PRS PRS PRS PRS mk3 mk2 mk1 mk0
0
0
0
0 fCLK
0
0
0
1 fCLK/2
0
0
1
0 fCLK/22
0
0
1
1 fCLK/23
0
1
0
0 fCLK/24
0
1
0
1 fCLK/25
0
1
1
0 fCLK/26
0
1
1
1 fCLK/27
1
0
0
0 fCLK/28
1
0
0
1 fCLK/29
1
0
1
0 fCLK/210
1
0
1
1 fCLK/211
1
1
0
0 fCLK/212
1
1
0
1 fCLK/213
1
1
1
0 fCLK/214
1
1
1
1 fCLK/215
Selection of operation clock (CKmk)Note (k = 0, 1)
fCLK = 2 MHz 2 MHz
fCLK = 5 MHz 5 MHz
fCLK = 10 MHz 10 MHz
fCLK = 20 MHz 20 MHz
fCLK = 32 MHz 32 MHz
1 MHz
2.5 MHz 5 MHz
10 MHz
16 MHz
500 kHz 1.25 MHz 2.5 MHz 5 MHz
8 MHz
250 kHz 625 kHz 1.25 MHz 2.5 MHz 4 MHz
125 kHz 313 kHz 625 kHz 1.25 MHz 2 MHz
62.5 kHz 156 kHz 313 kHz 625 kHz 1 MHz
31.3 kHz 78.1 kHz 156 kHz 313 kHz 500 kHz
15.6 kHz 39.1 kHz 78.1 kHz 156 kHz 250 kHz
7.81 kHz 19.5 kHz 39.1 kHz 78.1 kHz 125 kHz
3.91 kHz 9.77 kHz 19.5 kHz 39.1 kHz 62.5 kHz
1.95 kHz 4.88 kHz 9.77 kHz 19.5 kHz 31.3 kHz
977 Hz
2.44 kHz 4.88 kHz 9.77 kHz 15.6 kHz
488 Hz
1.22 kHz 2.44 kHz 4.88 kHz 7.81 kHz
244 Hz
610 Hz
1.22 kHz 2.44 kHz 3.91 kHz
122 Hz
305 Hz
610 Hz
1.22 kHz 1.95 kHz
61.0 Hz
153 Hz
305 Hz
610 Hz
977 Hz
Note
When changing the clock selected for fCLK (by changing the system clock control register (CKC) value), stop timer array unit (TTm = 00FFH).
Caution 1. Be sure to clear bits 15, 14, 11, 10 to 0. Caution 2. If fCLK (undivided) is selected as the operation clock (CKmk) and TDRnm is set to 0000H (n = 0, 1, m = 0
to 7), interrupt requests output from timer array units cannot be used.
Remark 1. fCLK: CPU/peripheral hardware clock frequency
Remark 2. Waveform of the clock to be selected in the TPSm register which becomes high level for one period of fCLK
from its rising edge (m = 1 to 15). For details, see 7.5.1 Count clock (fTCLK).
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Figure 7 - 13 Format of Timer Clock Select Register m (TPSm) (2/2)
Address: After reset: R/W:
F01B6H, F01B7H (TPS0), F01F6H, F01F7H (TPS1) 0000H R/W
Symbol
15
TPSm
0
14
13
12
11
0
PRSm31 PRSm30
0
10
9
8
0
PRSm21 PRSm20
7 PRSm13
6 PRSm12
5 PRSm11
4 PRSm10
3 PRSm03
2 PRSm02
1 PRSm01
0 PRSm00
PRS PRS m21 m20
0
0 fCLK/2
0
1 fCLK/22
1
0 fCLK/24
1
1 fCLK/26
Selection of operation clock (CKm2)Note
fCLK = 2 MHz 1 MHz
fCLK = 5 MHz 2.5 MHz
fCLK = 10 MHz 5 MHz
fCLK = 20 MHz 10 MHz
500 kHz 1.25 MHz 2.5 MHz 5 MHz
125 kHz 313 kHz 625 kHz 1.25 MHz
31.3 kHz 78.1 kHz 156 kHz 313 kHz
fCLK = 32 MHz 16 MHz 8 MHz 2 MHz 500 kHz
PRS PRS m31 m30
0
0 fCLK/28
0
1 fCLK/210
1
0 fCLK/212
1
1 fCLK/214
Selection of operation clock (CKm3)Note
fCLK = 2 MHz 7.81 kHz
fCLK = 5 MHz 19.5 kHz
fCLK = 10 MHz 39.1 kHz
fCLK = 20 MHz 78.1 kHz
1.95 kHz 4.88 kHz 9.77 kHz 19.5 kHz
488 Hz
1.22 kHz 2.44 kHz 4.88 kHz
122 Hz
305 Hz
610 Hz
1.22 kHz
fCLK = 32 MHz 125 kHz 31.3 kHz 7.81 kHz 1.95 kHz
Note
When changing the clock selected for fCLK (by changing the system clock control register (CKC) value), stop timer array unit (TTm = 00FFH). The timer array unit must also be stopped if the operating clock (fMCK) or the valid edge of the signal input from the TImn pin is selected.
Caution Be sure to clear bits 15, 14, 11, 10 to 0.
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By using channels 1 and 3 in the 8-bit timer mode and specifying CKm2 or CKm3 as the operation clock, the interval times shown in Table 7 - 4 can be achieved by using the interval timer function.
Table 7 - 4 Interval Times Available for Operation Clock CKSm2 or CKSm3
Clock
10 µs
Interval timeNote (fCLK = 32 MHz)
100 µs
1 ms
CKm2
fCLK/2
--
--
fCLK/22
--
--
fCLK/24
--
fCLK/26
--
CKm3
fCLK/28
--
fCLK/210
--
fCLK/212
--
--
fCLK/214
--
--
Note
The margin is within 5%.
10 ms -- -- -- -- -- --
Remark 1. fCLK: CPU/peripheral hardware clock frequency Remark 2. For details of a signal of fCLK/2j selected with the TPSm register, see 7.5.1 Count clock (fTCLK).
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7.3.4 Timer mode register mn (TMRmn)
The TMRmn register sets an operation mode of channel n. This register is used to select the operation clock (fMCK), select the count clock, select the master/slave, select the 16 or 8-bit timer (only for channels 1 and 3), specify the start trigger and capture trigger, select the valid edge of the timer input, and specify the operation mode (interval, capture, event counter, one-count, or capture and one-count). Rewriting the TMRmn register is prohibited when the register is in operation (when TEmn = 1). However, bits 7 and 6 (CISmn1, CISmn0) can be rewritten even while the register is operating with some functions (when TEmn = 1). For details, see 7.8 Independent Channel Operation Function of Timer Array Unit and 7.9 Simultaneous Channel Operation Function of Timer Array Unit. The TMRmn register can be set by a 16-bit memory manipulation instruction. The value of this register is 0000H following a reset.
Caution
The bit function assigned to bit 11 of the TMRmn register depends on the channel. TMRm2, TMRm4, TMRm6: MASTERmn bit (n = 2, 4, 6) TMRm1, TMRm3: SPLITmn bit (n = 1, 3) TMRm0, TMRm5, TMRm7: Fixed to 0
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Figure 7 - 14 Format of Timer Mode Register mn (TMRmn) (1/4)
Address:
After reset: R/W:
F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07), F01D0H, F01D1H (TMR10) to F01DEH, F01DFH (TMR17) 0000H R/W
Symbol
15
14
13
TMRmn (n = 2, 4, 6)
CKSmn1
CKSmn0
0
12
11
10
CCSmn MASTERmn STSmn2
9 STSmn1
8 STSmn0
7
6
5
CISmn1 CISmn0
0
4
3
2
1
0
0
MDmn3 MDmn2 MDmn1 MDmn0
Symbol
15
14
13
TMRmn (n = 1, 3)
CKSmn1
CKSmn0
0
7
6
5
CISmn1 CISmn0
0
12 CCSmn
11 SPLITmn
10 STSmn2
9 STSmn1
8 STSmn0
4
3
2
1
0
0
MDmn3 MDmn2 MDmn1 MDmn0
Symbol
15
14
13
TMRmn (n = 0, 5, 7)
CKSmn1
CKSmn0
0
12 CCSmn
11 0Note
10 STSmn2
9 STSmn1
8 STSmn0
7
6
5
CISmn1 CISmn0
0
4
3
2
1
0
0
MDmn3 MDmn2 MDmn1 MDmn0
CKS CKS mn1 mn0
Selection of operation clock (fMCK) of channel n
0 0 Operation clock CKm0 set by timer clock select register m (TPSm)
0 1 Operation clock CKm2 set by timer clock select register m (TPSm)
1 0 Operation clock CKm1 set by timer clock select register m (TPSm)
1 1 Operation clock CKm3 set by timer clock select register m (TPSm)
Operation clock (fMCK) is used by the edge detector. A count clock (fTCLK) and a sampling clock are generated depending on the setting of the CCSmn bit. The operation clocks CKm2 and CKm3 can only be selected for channels 1 and 3.
CCS mn
Selection of count clock (fTCLK) of channel n
0 Operation clock (fMCK) specified by the CKSmn0 and CKSmn1 bits
1 Valid edge of input signal input from the TImn pin
· In the case of unit 0:
In channels 0 to 4, valid edge of input signal selected by TIS1n In channel 5, valid edge of input signal selected by TIS0 In channel 7, valid edge of input signal selected by ISC
Count clock (fTCLK) is used for the counter, output controller, and interrupt controller.
(Note, Cautions, and Remark are listed on the next page.)
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Note
Bit 11 is a read-only bit and fixed to 0. Writing to this bit is ignored.
Caution 1. Be sure to clear bits 13, 5, and 4 to 0. Caution 2. The timer array unit must be stopped (TTm = 00FFH) if the clock selected for fCLK is changed (by
changing the value of the system clock control register (CKC)), even if the operating clock specified by using the CKSmn0 and CKSmn1 bits (fMCK) or the valid edge of the signal input from the TImn pin is selected as the count clock (fTCLK).
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
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Figure 7 - 14 Format of Timer Mode Register mn (TMRmn) (2/4)
Address:
After reset: R/W:
F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07), F01D0H, F01D1H (TMR10) to F01DEH, F01DFH (TMR17) 0000H R/W
Symbol
15
14
13
TMRmn (n = 2, 4, 6)
CKSmn1
CKSmn0
0
12
11
10
CCSmn MASTERmn STSmn2
9 STSmn1
8 STSmn0
7
6
5
CISmn1 CISmn0
0
4
3
2
1
0
0
MDmn3 MDmn2 MDmn1 MDmn0
Symbol
15
14
13
TMRmn (n = 1, 3)
CKSmn1
CKSmn0
0
7
6
5
CISmn1 CISmn0
0
12 CCSmn
11 SPLITmn
10 STSmn2
9 STSmn1
8 STSmn0
4
3
2
1
0
0
MDmn3 MDmn2 MDmn1 MDmn0
Symbol
15
14
13
TMRmn (n = 0, 5, 7)
CKSmn1
CKSmn0
0
7
6
5
CISmn1 CISmn0
0
12 CCSmn
11 0Note
10 STSmn2
9 STSmn1
8 STSmn0
4
3
2
1
0
0
MDmn3 MDmn2 MDmn1 MDmn0
(Bit 11 of TMRmn (n = 2, 4, 6))
MAS TER mn
Selection between using channel n independently or simultaneously with another channel (as a slave or master)
0 Operates in independent channel operation function or as slave channel in simultaneous channel operation function.
1 Operates as master channel in simultaneous channel operation function.
Only the channel 2, 4, 6 can be set as a master channel (MASTERmn = 1). Be sure to use channel 0, 5, 7 are fixed to 0 (Regardless of the bit setting, channel 0 operates as master, because it is the highest channel). Clear the MASTERmn bit to 0 for a channel that is used with the independent channel operation function.
(Note and Remark are listed on the next page.)
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(Bit 11 of TMRmn (n = 1, 3))
SPLI Tmn
Selection of 8 or 16-bit timer operation for channels 1 and 3
0 Operates as 16-bit timer. (Operates in independent channel operation function or as slave channel in simultaneous channel operation function.)
1 Operates as 8-bit timer.
STS STS STS mn2 mn1 mn0
Setting of start trigger or capture trigger of channel n
0 0 0 Only software trigger start is valid (other trigger sources are unselected).
0 0 1 Valid edge of the TImn pin input is used as both the start trigger and capture trigger.
0 1 0 Both the edges of the TImn pin input are used as a start trigger and a capture trigger.
1 0 0 Interrupt signal of the master channel is used (when the channel is used as a slave
channel with the simultaneous channel operation function).
Other than above Setting prohibited
Note
Bit 11 is a read-only bit and fixed to 0. Writing to this bit is ignored.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
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Figure 7 - 14 Format of Timer Mode Register mn (TMRmn) (3/4)
Address:
After reset: R/W:
F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07), F01D0H, F01D1H (TMR10) to F01DEH, F01DFH (TMR17) 0000H R/W
Symbol
15
14
13
TMRmn (n = 2, 4, 6)
CKSmn1
CKSmn0
0
12
11
10
CCSmn MASTERmn STSmn2
9 STSmn1
8 STSmn0
7
6
5
CISmn1 CISmn0
0
4
3
2
1
0
0
MDmn3 MDmn2 MDmn1 MDmn0
Symbol
15
14
13
TMRmn (n = 1, 3)
CKSmn1
CKSmn0
0
7
6
5
CISmn1 CISmn0
0
12 CCSmn
11 SPLITmn
10 STSmn2
9 STSmn1
8 STSmn0
4
3
2
1
0
0
MDmn3 MDmn2 MDmn1 MDmn0
Symbol
15
14
13
TMRmn (n = 0, 5, 7)
CKSmn1
CKSmn0
0
7
6
5
CISmn1 CISmn0
0
12 CCSmn
11 0Note
10 STSmn2
9 STSmn1
8 STSmn0
4
3
2
1
0
0
MDmn3 MDmn2 MDmn1 MDmn0
CIS CIS mn1 mn0
Selection of TImn pin input valid edge
0 0 Falling edge
0 1 Rising edge
1 0 Both edges (when low-level width is measured) Start trigger: Falling edge, Capture trigger: Rising edge
1 1 Both edges (when high-level width is measured) Start trigger: Rising edge, Capture trigger: Falling edge
If both the edges are specified when the value of the STSmn2 to STSmn0 bits is other than 010B, set the CISmn1 to CISmn0 bits to 10B.
Note
Bit 11 is a read-only bit and fixed to 0. Writing to this bit is ignored.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
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Figure 7 - 14 Format of Timer Mode Register mn (TMRmn) (4/4)
Address:
After reset: R/W:
F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07), F01D0H, F01D1H (TMR10) to F01DEH, F01DFH (TMR17) 0000H R/W
Symbol
15
14
13
TMRmn (n = 2, 4, 6)
CKSmn1
CKSmn0
0
12
11
10
CCSmn MASTERmn STSmn2
9 STSmn1
8 STSmn0
7
6
5
CISmn1 CISmn0
0
4
3
2
1
0
0
MDmn3 MDmn2 MDmn1 MDmn0
Symbol
15
14
13
TMRmn (n = 1, 3)
CKSmn1
CKSmn0
0
7
6
5
CISmn1 CISmn0
0
12 CCSmn
11 SPLITmn
10 STSmn2
9 STSmn1
8 STSmn0
4
3
2
1
0
0
MDmn3 MDmn2 MDmn1 MDmn0
Symbol
15
14
13
TMRmn (n = 0, 5, 7)
CKSmn1
CKSmn0
0
7
6
5
CISmn1 CISmn0
0
12 CCSmn
11 0Note 1
10 STSmn2
9 STSmn1
8 STSmn0
4
3
2
1
0
0
MDmn3 MDmn2 MDmn1 MDmn0
MD MD MD Operation mode of channel n
mn3 mn2 mn1
Corresponding function
Count operation of TCR
0 0 0 Interval timer mode
Interval timer/Square wave Counting down
output/Divider function/PWM
output (master)
0 1 0 Capture mode
Input pulse interval
Counting up
measurement
0 1 1 Event counter mode
External event counter
Counting down
1 0 0 One-count mode
Delay counter/One-shot pulse Counting down
output/PWM output (slave)
1 1 0 Capture & one-count mode
Measurement of high-/low- Counting up
level width of input signal
Other than above Setting prohibited
The operation in each mode varies depending on MDmn0 bit (see the table on the next page).
(Notes and Remark are listed on the next page.)
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Operation mode MD
(Value set by the MDmn3 to MDmn1 bits mn0
(see the table on the previous page))
Setting of starting counting and interrupt
· Interval timer mode (0, 0, 0)
· Capture mode (0, 1, 0)
0 Timer interrupt is not generated when counting is started (timer output does not change, either).
1 Timer interrupt is generated when counting is started (timer output also changes).
· Event counter mode (0, 1, 1)
0 Timer interrupt is not generated when counting is started (timer output does not change, either).
· One-count modeNote 2 (1, 0, 0)
0 Start trigger is invalid during counting operation. At that time, interrupt is not generated.
1 Start trigger is valid during counting operationNote 3. At that time, interrupt is not generated.
· Capture & one-count mode
0 Timer interrupt is not generated when counting is
(1, 1, 0)
started (timer output does not change, either).
Start trigger is invalid during counting operation.
At that time interrupt is not generated.
Other than above
Setting prohibited
Note 1. Note 2.
Note 3.
Bit 11 is a read-only bit and fixed to 0. Writing to this bit is ignored. In one-count mode, interrupt output (INTTMmn) when starting a count operation and TOmn output are not controlled. If the start trigger (TSmn = 1) is issued during operation, the counter is initialized, and recounting is started (does not occur the interrupt request).
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
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7.3.5 Timer status register mn (TSRmn)
The TSRmn register indicates the overflow state of the counter of channel n. The TSRmn register is valid only in the capture mode (MDmn3 to MDmn1 = 010B) and capture & one-count mode (MDmn3 to MDmn1 = 110B). See Table 7 - 5 for the operation of the OVF bit in each operation mode and set/clear conditions. The TSRmn register can be read by a 16-bit memory manipulation instruction. The 8 lower-order bits of a TSRmn register can be handled as TSRmnL, which can be read by an 8-bit memory manipulation instruction. The value of this register is 0000H following a reset.
Figure 7 - 15 Format of Timer Status Register mn (TSRmn)
Address:
After reset: R/W:
F01A0H, F01A1H (TSR00) to F01AEH, F01AFH (TSR07), F01E0H, F01E1H (TSR10) to F01EEH, F01EFH (TSR17) 0000H R
Symbol
15
14
13
12
11
10
9
8
TSRmn
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
OVF
OVF
Counter overflow state of channel n
0
Overflow does not occur.
1
Overflow occurs.
When OVF = 1, this flag is cleared (OVF = 0) when the next value is captured without overflow.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
Table 7 - 5 OVF Bit Operation and Set/Clear Conditions in Each Operation Mode
Timer operation mode
OVF bit
Set/clear conditions
· Capture mode · Capture & one-count mode
clear set
When no overflow has occurred upon capturing When an overflow has occurred upon capturing
· Interval timer mode · Event counter mode · One-count mode
clear set
-- (Use prohibited)
Remark The OVF bit does not change immediately after the counter has overflowed, but changes upon the subsequent capture.
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7.3.6 Timer channel enable status register m (TEm)
The TEm register is used to enable or stop the timer operation of each channel. Each bit of the TEm register corresponds to each bit of the timer channel start register m (TSm) and the timer channel stop register m (TTm). When a bit of the TSm register is set to 1, the corresponding bit of this register is set to 1. When a bit of the TTm register is set to 1, the corresponding bit of this register is cleared to 0. The TEm register can be read by a 16-bit memory manipulation instruction. The lower 8 bits of the TEm register can be set with a 1-bit or 8-bit memory manipulation instruction with TEmL. The value of this register is 0000H following a reset.
Figure 7 - 16 Format of Timer Channel Enable Status Register m (TEm)
Address: After reset: R/W:
F01B0H, F01B1H (TE0), F01F0H, F01F1H (TE1) 0000H R
Symbol
15
14
13
12
11
10
9
8
TEm
0
0
0
0
TEHm3
0
TEHm1
0
7 TEm7
6 TEm6
5 TEm5
4 TEm4
3 TEm3
2 TEm2
1 TEm1
0 TEm0
TEHm3
0 1
Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 3 is in the 8-bit timer mode
Operation is stopped. Operation is enabled.
TEHm1
0 1
Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 1 is in the 8-bit timer mode
Operation is stopped. Operation is enabled.
TEmn
Indication of operation enabled or stopped state of channel n
0
Operation is stopped.
1
Operation is enabled.
This bit displays whether operation of the lower 8-bit timer for TEm1 and TEm3 is enabled or stopped when
channel 1 or 3 is in the 8-bit timer mode.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
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7.3.7 Timer channel start register m (TSm)
The TSm register is a trigger register that is used to initialize timer counter register mn (TCRmn) and start the counting operation of each channel. When a bit of this register is set to 1, the corresponding bit of timer channel enable status register m (TEm) is set to 1. The TSmn, TSHm1, TSHm3 bits are immediately cleared when operation is enabled (TEmn, TEHm1, TEHm3 = 1), because they are trigger bits. The TSm register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the TSm register can be set with a 1-bit or 8-bit memory manipulation instruction with TSmL. The value of this register is 0000H following a reset.
Figure 7 - 17 Format of Timer Channel Start Register m (TSm)
Address: After reset: R/W:
F01B2H, F01B3H (TS0), F01F2H, F01F3H (TS1) 0000H R/W
Symbol
15
14
13
12
11
10
9
8
TSm
0
0
0
0
TSHm3
0
TSHm1
0
7 TSm7
6 TSm6
5 TSm5
4 TSm4
3 TSm3
2 TSm2
1 TSm1
0 TSm0
TSHm3
0 1
Trigger to enable operation (start operation) of the higher 8-bit timer when channel 3 is in the 8-bit timer mode
No trigger operation The TEHm3 bit is set to 1 and the count operation becomes enabled. The TCRm3 register count operation start in the interval timer mode in the count operation enabled state (see Table 7 - 6 in 7.5.2 Timing of the start of counting).
TSHm1
0 1
Trigger to enable operation (start operation) of the higher 8-bit timer when channel 1 is in the 8-bit timer mode
No trigger operation The TEHm1 bit is set to 1 and the count operation becomes enabled. The TCRm1 register count operation start in the interval timer mode in the count operation enabled state (see Table 7 - 6 in 7.5.2 Timing of the start of counting).
TSmn
Operation enable (start) trigger of channel n
0
No trigger operation
1
The TEmn bit is set to 1 and the count operation becomes enabled.
The TCRmn register count operation start in the count operation enabled state varies depending on each operation mode (see Table 7 - 6 in 7.5.2 Timing of the start of counting).
This bit is the trigger to enable operation (start operation) of the lower 8-bit timer for TSm1 and
TSm3 when channel 1 or 3 is in the 8-bit timer mode.
(Cautions and Remarks are listed on the next page.)
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Caution 1. Be sure to clear bits 15 to 12, 10, and 8 to 0. Caution 2. When switching from a function that does not use TImn pin input to one that does, the following wait
period is required from when timer mode register mn (TMRmn) is set until the TSmn (TSHm1, TSHm3) bit is set to 1. When the TImn pin noise filter is enabled (TNFENnm = 1): Four cycles of the operation clock (fMCK) When the TImn pin noise filter is disabled (TNFENnm = 0): Two cycles of the operation clock (fMCK)
Remark 1. When the TSm register is read, 0 is always read. Remark 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
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7.3.8 Timer channel stop register m (TTm)
The TTm register is a trigger register that is used to stop the counting operation of each channel. When a bit of this register is set to 1, the corresponding bit of timer channel enable status register m (TEm) is cleared to 0. The TTmn, TTHm1, TTHm3 bits are immediately cleared when operation is stopped (TEmn, TEHm1, TEHm3 = 0), because they are trigger bits. The TTm register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the TTm register can be set with a 1-bit or 8-bit memory manipulation instruction with TTmL. The value of this register is 0000H following a reset.
Figure 7 - 18 Format of Timer Channel Stop Register m (TTm)
Address: After reset: R/W:
F01B4H, F01B5H (TT0), F01F4H, F01F5H (TT1) 0000H R/W
Symbol
15
14
13
12
11
10
9
8
TTm
0
0
0
0
TTHm3
0
TTHm1
0
7 TTm7
6 TTm6
5 TTm5
4 TTm4
3 TTm3
2 TTm2
1 TTm1
0 TTm0
TTHm3 0 1
Trigger to stop operation of the higher 8-bit timer when channel 3 is in the 8-bit timer mode No trigger operation TEHm3 bit is cleared to 0 and the count operation is stopped.
TTHm1 0 1
Trigger to stop operation of the higher 8-bit timer when channel 1 is in the 8-bit timer mode No trigger operation TEHm1 bit is cleared to 0 and the count operation is stopped.
TTmn
Operation stop trigger of channel n
0
No trigger operation
1
TEmn bit is cleared to 0 and the count operation is stopped.
This bit is the trigger to stop operation of the lower 8-bit timer for TTm1 and TTm3 when
channel 1 or 3 is in the 8-bit timer mode.
Caution Be sure to clear bits 15 to 12, 10, and 8 of the TTm register to 0.
Remark 1. When the TTm register is read, 0 is always read. Remark 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
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7.3.9 Timer input select register 0 (TIS0)
The TIS0 register is used to select the channel 5 of unit 0 timer input. The TIS0 register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 7 - 19 Format of Timer Input Select Register 0 (TIS0)
Address: After reset: R/W:
F0074H 00H R/W
Symbol
7
6
5
4
3
2
1
0
TIS0
0
0
0
0
0
TIS02
TIS01
TIS00
TIS02
TIS01
TIS00
Selection of timer input used with channel 5
0
0
0
Input signal of timer input pin (TI05)
0
0
1
Event input signal from ELCL
0
1
1
Middle-speed on-chip oscillator peripheral clock (fIMP)
1
0
0
Low-speed on-chip oscillator clock (fIL)
1
0
1
Subsystem clock (fSUB)
Other than above
Setting prohibited
Caution
Make sure that both the high-level and low-level widths of timer input to be selected are no less than 1/fMCK + 10 ns. Therefore, when selecting fSUB as fCLK (the CSS bit of the CKC register = 1), the TIS02 bit cannot be set to 1.
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7.3.10 Timer input select register 1 (TIS1)
The TIS1 register is used to select channels 0 and 1 of unit 0 timer input. The TIS1 register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 7 - 20 Format of Timer Input Select Register 1 (TIS1)
Address: After reset: R/W:
F0075H 00H R/W
Symbol
7
6
5
4
3
2
1
TIS1
0
0
0
0
0
0
TIS11
TIS1n
Selection of timer input used with channel n
0
Timer input pin (TI0n)
1
Event input signal from ELCL
Remark n = 0, 1
0 T1S10
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7.3.11 Timer output enable register m (TOEm)
The TOEm register is used to enable or disable timer output of each channel. Channel n for which timer output has been enabled becomes unable to rewrite the value of the TOmn bit of timer output register m (TOm) described later by software, and the value reflecting the setting of the timer output function through the count operation is output from the timer output pin (TOmn). The TOEm register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the TOEm register can be set with a 1-bit or 8-bit memory manipulation instruction with TOEmL. The value of this register is 0000H following a reset.
Figure 7 - 21 Format of Timer Output Enable Register m (TOEm)
Address: After reset: R/W:
F01BAH, F01BBH (TOE0), F01FAH, F01FBH (TOE1) 0000H R/W
Symbol
15
14
13
12
11
10
9
8
TOEm
0
0
0
0
0
0
0
0
7 TOEm7
6 TOEm6
5 TOEm5
4 TOEm4
3 TOEm3
2 TOEm2
1 TOEm1
0 TOEm0
TOEmn
Enabling/disabling timer output for channel n
0
Disables timer output.
The corresponding TOmn bit does not reflect timer operation with this setting, so the output
level of a TOmn bit is fixed to the level written to the TOm register.
Writing to the TOmn bit is enabled and the level set in the TOmn bit is output from the TOmn
pin.
1
Enables timer output.
The corresponding TOmn bit reflects timer operation with this setting, so the output waveform
is generated.
Writing to the TOmn bit is ignored.
Caution Be sure to clear bits 15 to 8 to 0.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
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7.3.12 Timer output register m (TOm)
The TOm register is a buffer register of timer output of each channel. The value of each bit in this register is output from the timer output pin (TOmn) of each channel. The TOmn bit on this register can be rewritten by software only when timer output is disabled (TOEmn = 0). When timer output is enabled (TOEmn = 1), rewriting this register by software is ignored, and the value is changed only by the timer operation. To use the P00/TI00, P01/TO00, P16/TI01/TO01, P17/TI02/TO02, P31/TI03/TO03, P42/TI04/TO04, P46/TI05/TO05, P102/TI06/TO06, P145/TI07/TO07, P64/TI10/TO10, P65/TI11/TO11, P66/TI12/TO12, P67/TI13/TO13, P103/TI14/TO14, P104/TI15/TO15, P105/TI16/TO16, or P106/TI17/TO17 pin as a port function pin, set the corresponding TOmn bit to 0. The TOm register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the TOm register can be set with an 8-bit memory manipulation instruction with TOmL. The value of this register is 0000H following a reset.
Figure 7 - 22 Format of Timer Output Register m (TOm)
Address: After reset: R/W:
F01B8H, F01B9H (TO0), F01F8H, F01F9H (TO1) 0000H R/W
Symbol
15
14
13
12
11
10
9
8
TOm
0
0
0
0
0
0
0
0
7 TOm7
6 TOm6
5 TOm5
4 TOm4
3 TOm3
2 TOm2
1 TOm1
0 TOm0
TOmn
Timer output of channel n
0
Timer output value is 0.
1
Timer output value is 1.
Caution Be sure to clear bits 15 to 8 to 0.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
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7.3.13 Timer output level register m (TOLm)
The TOLm register controls the timer output level of each channel. The setting of the inverted output of channel n by this register is reflected at the timing of set or reset of the timer output signal while the timer output is enabled (TOEmn = 1) in the Slave channel output mode (TOMmn = 1). In the master channel output mode (TOMmn = 0), this register setting is invalid. The TOLm register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the TOLm register can be set with an 8-bit memory manipulation instruction with TOLmL. The value of this register is 0000H following a reset.
Figure 7 - 23 Format of Timer Output Level Register m (TOLm)
Address: After reset: R/W:
F01BCH, F01BDH (TOL0), F01FCH, F01FDH (TOL1) 0000H R/W
Symbol
15
14
13
12
11
10
9
8
TOLm
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
TOLm7
TOLm6
TOLm5
TOLm4
TOLm3
TOLm2
TOLm1
0
TOLmn
Control of timer output level of channel n
0
Positive logic output (active-high)
1
Negative logic output (active-low)
Caution Be sure to clear bits 15 to 8, and 0 to 0.
Remark 1. If the value of this register is rewritten during timer operation, the timer output logic is inverted when the timer output signal changes next, instead of immediately after the register value is rewritten.
Remark 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
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7.3.14 Timer output mode register m (TOMm)
The TOMm register is used to control the timer output mode of each channel. When a channel is used for the independent channel operation function, set the corresponding bit of the channel to be used to 0. When a channel is used for the simultaneous channel operation function (PWM output, one-shot pulse output, or multiple PWM output), set the corresponding bit of the master channel to 0 and the corresponding bit of the slave channel to 1. The setting of each channel n by this register is reflected at the timing when the timer output signal is set or reset while the timer output is enabled (TOEmn = 1). The TOMm register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the TOMm register can be set with an 8-bit memory manipulation instruction with TOMmL. The value of this register is 0000H following a reset.
Figure 7 - 24 Format of Timer Output Mode Register m (TOMm)
Address: After reset: R/W:
F01BEH, F01BFH (TOM0), F01FEH, F01FFH (TOM1) 0000H R/W
Symbol
15
14
13
12
11
10
9
8
TOMm
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
TOMm7 TOMm6 TOMm5 TOMm4 TOMm3 TOMm2 TOMm1
0
TOMmn
Control of timer output mode of channel n
0
Master channel output mode (to produce toggled output by timer interrupt request signal
(INTTMmn))
1
Slave channel output mode (output is set by the timer interrupt request signal (INTTMmn) of
the master channel, and reset by the timer interrupt request signal (INTTM0p) of the slave
channel)
Caution Be sure to clear bits 15 to 8, and 0 to 0.
Remark
m: Unit number (m = 0, 1) n: Channel number n = 0 to 7 (n = 0, 2, 4, 6 for master channel) p: Slave channel number n < p 7
(For details of the relation between the master channel and slave channel, refer to 7.4.1 Basic rules of
simultaneous channel operation function.)
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7.3.15 Input switch control register (ISC)
The ISC1 and ISC0 bits of the ISC register are used to implement LIN-bus communication operation by using channel 7 in association with the serial array unit. When the ISC1 bit is set to 1, the input signal of the serial data input pin (RxD2) is selected as a timer input signal. The ISC register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 7 - 25 Format of Input Switch Control Register (ISC)
Address: After reset: R/W:
F0073H 00H R/W
Symbol ISC
7 ISC7
6 ISC6
5 ISC5
4 ISC4
3 ISC3
2 ISC2
1 ISC1
0 ISC0
ISC1 0 1
Switching channel 7 input of timer array unit Uses the input signal of the TI07 pin as a timer input (normal operation). Input signal of the RXD2 pin is used as timer input (detects the wakeup signal and measures the low width of the break field and the pulse width of the sync field).
ISC0
Switching external interrupt (INTP0) input
0
Uses the input signal of the INTP0 pin as an external interrupt (normal operation).
1
Uses the input signal of the RXD2 pin as an external interrupt (wakeup signal detection).
Remark When the LIN-bus communication function is used, select the input signal of the RxD2 pin by setting ISC1 to 1.
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7.3.16 Noise filter enable registers 1, 2 (NFEN1, NFEN2)
The NFEN1 and NFEN2 registers are used to set whether the noise filter can be used for the timer input signal to each channel. Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal. When the noise filter is enabled, after synchronization with the operating clock (fMCK) for the target channel, whether the signal keeps the same value for two clock cycles is detected. When the noise filter is disabled, the input signal is only synchronized with the operating clock (fMCK) for the target channelNote. The NFEN1 and NFEN2 registers can be set by a 1-bit or 8-bit memory manipulation instruction. The value of each of these registers is 00H following a reset.
Note
For details, see 7.5.1 (2)When valid edge of input signal via the TImn pin is selected (CCSmn = 1), 7.5.2 Timing of the start of counting, and 7.7 Timer Input (TImn) Control.
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Figure 7 - 26 Format of Noise Filter Enable Registers 1, 2 (NFEN1, NFEN2) (1/2)
Address: After reset: R/W:
F0071H 00H R/W
Symbol
7
6
5
4
3
2
1
0
NFEN1 TNFEN07 TNFEN06 TNFEN05 TNFEN04 TNFEN03 TNFEN02 TNFEN01 TNFEN00
Address: After reset: R/W:
F0072H 00H R/W
Symbol
7
6
5
4
3
2
1
0
NFEN2 TNFEN17 TNFEN16 TNFEN15 TNFEN14 TNFEN13 TNFEN12 TNFEN11 TNFEN10
TNFEN07
Enabling/disabling use of the noise filter for the TI07 pinNote
0
Turns the noise filter off.
1
Turns the noise filter on.
TNFEN06
Enabling/disabling use of the noise filter for the TI06 pin
0
Turns the noise filter off.
1
Turns the noise filter on.
TNFEN05
Enabling/disabling use of the noise filter for the TI05 pin
0
Turns the noise filter off.
1
Turns the noise filter on.
TNFEN04
Enabling/disabling use of the noise filter for the TI04 pin
0
Turns the noise filter off.
1
Turns the noise filter on.
TNFEN03
Enabling/disabling use of the noise filter for the TI03 pin
0
Turns the noise filter off.
1
Turns the noise filter on.
TNFEN02
Enabling/disabling use of the noise filter for the TI02 pin
0
Turns the noise filter off.
1
Turns the noise filter on.
TNFEN01
Enabling/disabling use of the noise filter for the TI01 pin
0
Turns the noise filter off.
1
Turns the noise filter on.
TNFEN00
Enabling/disabling use of the noise filter for the TI00 pin
0
Turns the noise filter off.
1
Turns the noise filter on.
(Note and Remark are listed on the next page.)
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Note
The applicable pin can be switched by setting the ISC1 bit of the ISC register. ISC1 = 0: Whether or not to use the noise filter of the TI07 pin can be selected. ISC1 = 1: Whether or not to use the noise filter of the RxD2 pin can be selected.
Remark The presence or absence of timer I/O pins of channel 0 to 7 depends on the product. See Table 7 - 2 Timer I/O Pins Provided in Each Product for details.
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Figure 7 - 26 Format of Noise Filter Enable Registers 1, 2 (NFEN1, NFEN2) (2/2)
Address: After reset: R/W:
F0071H 00H R/W
Symbol
7
6
5
4
3
2
1
0
NFEN1 TNFEN07 TNFEN06 TNFEN05 TNFEN04 TNFEN03 TNFEN02 TNFEN01 TNFEN00
Address: After reset: R/W:
F0072H 00H R/W
Symbol
7
6
5
4
3
2
1
0
NFEN2 TNFEN17 TNFEN16 TNFEN15 TNFEN14 TNFEN13 TNFEN12 TNFEN11 TNFEN10
TNFEN17
Enabling/disabling use of the noise filter for the TI17 pin
0
Turns the noise filter off.
1
Turns the noise filter on.
TNFEN16
Enabling/disabling use of the noise filter for the TI16 pin
0
Turns the noise filter off.
1
Turns the noise filter on.
TNFEN15
Enabling/disabling use of the noise filter for the TI15 pin
0
Turns the noise filter off.
1
Turns the noise filter on.
TNFEN14
Enabling/disabling use of the noise filter for the TI14 pin
0
Turns the noise filter off.
1
Turns the noise filter on.
TNFEN13
Enabling/disabling use of the noise filter for the TI13 pin
0
Turns the noise filter off.
1
Turns the noise filter on.
TNFEN12
Enabling/disabling use of the noise filter for the TI12 pin
0
Turns the noise filter off.
1
Turns the noise filter on.
TNFEN11
Enabling/disabling use of the noise filter for the TI11 pin
0
Turns the noise filter off.
1
Turns the noise filter on.
TNFEN10
Enabling/disabling use of the noise filter for the TI10 pin
0
Turns the noise filter off.
1
Turns the noise filter on.
Remark The presence or absence of timer I/O pins of channel 0 to 7 depends on the product. See Table 7 - 2 Timer I/O Pins Provided in Each Product for details.
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7.3.17 Registers controlling port functions of pins to be used for timer I/O
Using port pins for the timer array unit functions requires setting of the registers that control the port functions multiplexed on the target pins (port mode register (PMxx), port register (Pxx), port mode control A register (PMCAxx), port mode control T register (PMCTxx), port mode control E register (PMCEx), and port function output enable register 0 (PFOE0)). For details, see 4.3.1 Port mode registers (PMxx), 4.3.2 Port registers (Pxx), 4.3.7 Port mode control A registers (PMCAxx), 4.3.8 Port mode control T registers (PMCTxx), 4.3.9 Port mode control E registers (PMCEx), and 4.3.15 Port function output enable registers (PFOEx). The port mode register (PMxx), port register (Pxx), port mode control A register (PMCAxx), port mode control T register (PMCTxx), port mode control E register (PMCEx), and port function output enable register 0 (PFOE0) to be set depend on the product. For details, see 4.5.4 Examples of register settings for port and alternate functions.
When using the ports (such as P00/TI00 and P01/TO00) to be shared with the timer output pin for timer output, set the corresponding bits in the port mode control A register (PMCAxx), port mode control T register (PMCTxx), port mode control E register (PMCEx), port mode register (PMxx), and port register (Pxx) to 0. Set the corresponding bit in port function output enable register 0 (PFOE0) to 1.
Example: When using P01/TO00 for timer output Set the PMCT01 bit of port mode control T register 0 to 0. Set the PMCE01 bit of port mode control E register 0 to 0. Set the PFOE01 bit of port function output enable register 0 to 1. Set the PM01 bit of port mode register 0 to 0. Set the P01 bit of port register 0 to 0.
Remark
The above statements apply to products with 192 to 768 Kbytes of flash memory, 40- to 64-pin products with 96 and 128 Kbytes of flash memory, and 80- and 100-pin products with 128 Kbytes of flash memory.
When using the ports (such as P00/TI00) to be shared with the timer input pin for timer input, set the corresponding bit in the port mode register (PMxx) to 1. And set the corresponding bits in the port mode control A register (PMCAxx), port mode control T register (PMCTxx), and port mode control E register (PMCEx) to 0. At this time, the bit in the port register (Pxx) may be 0 or 1.
Example: When using P00/TI00 for timer input Set the PMCT01 bit of port mode control T register 0 to 0. Set the PMCE01 bit of port mode control E register 0 to 0. Set the PM00 bit of port mode register 0 to 1. Set the P00 bit of port register 0 to 0 or 1.
Remark
The above statements apply to products with 192 to 768 Kbytes of flash memory, 40- to 64-pin products with 96 and 128 Kbytes of flash memory, and 80- and 100-pin products with 128 Kbytes of flash memory.
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7.4
Basic Rules of Timer Array Unit
7.4.1 Basic rules of simultaneous channel operation function
When simultaneously using multiple channels, namely, a combination of a master channel (a reference timer mainly counting the cycle) and slave channels (timers operating according to the master channel), the following rules apply.
(1) Only an even channel (channels 0, 2, 4, etc.) can be set as a master channel. (2) Any channel, except channel 0, can be set as a slave channel. (3) The slave channel must be lower than the master channel.
Example: If channel 2 is set as a master channel, channel 3 or those that follow (channels 3, 4, 5, etc.) can be set as a slave channel.
(4) Two or more slave channels can be set for one master channel. (5) When two or more master channels are to be used, slave channels with a master channel between them may not
be set. Example: If channels 0 and 4 are set as master channels, channels 1 to 3 can be set as the slave channels of
master channel 0. Channels 5 to 7 cannot be set as the slave channels of master channel 0.
(6) The operating clock for a slave channel in combination with a master channel must be the same as that of the master channel. The CKSmn0, CKSmn1 bits (bit 15, 14 of timer mode register mn (TMRmn)) of the slave channel that operates in combination with the master channel must be the same value as that of the master channel.
(7) A master channel can transmit INTTMmn (interrupt), start software trigger, and count clock to the lower channels. (8) A slave channel can use INTTMmn (interrupt), a start software trigger, or the count clock of the master channel as
a source clock, but cannot transmit its own INTTMmn (interrupt), start software trigger, or count clock to channels with lower channel numbers. (9) A master channel cannot use INTTMmn (interrupt), a start software trigger, or the count clock from the other higher master channel as a source clock. (10) To simultaneously start channels that operate in combination, the channel start trigger bit (TSmn) of the channels in combination must be set at the same time. (11) During the counting operation, a TSmn bit of a master channel or TSmn bits of all channels which are operating simultaneously can be set. It cannot be applied to TSmn bits of slave channels alone. (12) To stop the channels in combination simultaneously, the channel stop trigger bit (TTmn) of the channels in combination must be set at the same time. (13) CKm2/CKm3 cannot be selected while channels are operating simultaneously, because the operating clocks of master channels and slave channels have to be synchronized. (14) Timer mode register m0 (TMRm0) has no master bit (it is fixed to 0). However, as channel 0 is the highest channel, it can be used as a master channel during simultaneous operation.
The rules of the simultaneous channel operation function are applied in a channel group (a master channel and slave channels forming one simultaneous channel operation function). If two or more channel groups that do not operate in combination are specified, the basic rules of the simultaneous channel operation function in 7.4.1 Basic rules of simultaneous channel operation function do not apply to the channel groups.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
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TAU0 CK00
CK01 CK00
Channel 0: Master
Channel 1: Slave
Channel 2: Slave
Channel 3: Independent channel operation function
Channel 4: Master Channel 5: Independent channel
operation function Channel 6: Slave
Channel 7: Independent channel operation function
CHAPTER 7 TIMER ARRAY UNIT (TAU)
Channel group 1 (Simultaneous channel operation function)
Channel group 2 (Simultaneous channel operation function)
* The operating clock of channel group 1 may be different from that of channel group 2.
* A channel that operates independent channel operation function may be between channel group 1 and channel group 2.
* A channel that operates independent channel operation function may be between a master and a slave of channel group 2. Furthermore, the operating clock may be set separately.
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7.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only)
The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8bit timer channels. This function can only be used for channels 1 and 3, and there are several rules for using it. The basic rules for this function are as follows:
(1) The 8-bit timer operation function applies only to channels 1 and 3. (2) When using 8-bit timers, set the SPLITmn bit of timer mode register mn (TMRmn) to 1. (3) The higher 8 bits can be operated as the interval timer function. (4) At the start of operation, the higher 8 bits output INTTMm1H/INTTMm3H (an interrupt) (which is the same
operation performed when MDmn0 is set to 1). (5) The operation clock of the higher 8 bits is selected according to the CKSmn1 and CKSmn0 bits of the lower-bit
TMRmn register. (6) For the higher 8 bits, the TSHm1/TSHm3 bit is manipulated to start channel operation and the TTHm1/TTHm3 bit is
manipulated to stop channel operation. The channel state can be checked using the TEHm1/TEHm3 bit. (7) The lower 8 bits operate according to the TMRmn register settings. The following three functions support operation
of the lower 8 bits: · Interval timer function/square wave output function · External event counter function · Delay count function
(8) For the lower 8 bits, the TSm1/TSm3 bit is manipulated to start channel operation and the TTm1/TTm3 bit is manipulated to stop channel operation. The channel state can be checked using the TEm1/TEm3 bit.
(9) During 16-bit operation, manipulating the TSHm1, TSHm3, TTHm1, and TTHm3 bits is invalid. The TSm1, TSm3, TTm1, and TTm3 bits are manipulated to operate channels 1 and 3. The TEHm3 and TEHm1 bits are not changed.
(10) For the 8-bit timer function, the simultaneous operation functions (one-shot pulse, PWM, and multiple PWM) cannot be used.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 1, 3)
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7.5
Operations of Counters
7.5.1
Count clock (fTCLK)
The count clock (fTCLK) of the timer array unit can be selected between following by CCSmn bit of timer mode register mn (TMRmn).
· Operation clock (fMCK) specified by the CKSmn0 and CKSmn1 bits · Valid edge of input signal input from the TImn pin
Because the timer array unit is designed to operate in synchronization with fCLK, the timings of the count clock (fTCLK) are shown below.
(1) When operation clock (fMCK) specified by the CKSmn0 and CKSmn1 bits is selected (CCSmn = 0) The count clock (fTCLK) is between fCLK to fCLK/215 by setting of timer clock select register m (TPSm). When a divided fCLK is selected, however, the clock selected in TPSmn register, but a signal which becomes high level for one period of fCLK from its rising edge. When a fCLK is selected, fixed to high level Counting of timer counter register mn (TCRmn) delayed by one period of fCLK from rising edge of the count clock, because of synchronization with fCLK. But, this is described as "counting at rising edge of the count clock", as a matter of convenience.
Figure 7 - 27 Timing of fCLK and Count Clock (fTCLK) (When CCSmn = 0)
fCLK
f CLK/2
fTC LK ( = f MCK
= CKmn)
f CLK/4 f CLK/8 f CLK/16
Remark 1. : Rising edge of the count clock : Synchronization, increment/decrement of counter
Remark 2. fCLK: CPU/peripheral hardware clock
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(2) When valid edge of input signal via the TImn pin is selected (CCSmn = 1) The count clock (fTCLK) becomes the signal that detects valid edge of input signal via the TImn pin and synchronizes next rising fMCK. The count clock (fTCLK) is delayed for 1 to 2 period of fMCK from the input signal via the TImn pin (when a noise filter is used, the delay becomes 3 to 4 clock). Counting of timer counter register mn (TCRmn) delayed by one period of fCLK from rising edge of the count clock, because of synchronization with fCLK. But, this is described as "counting at valid edge of input signal via the TImn pin", as a matter of convenience.
Figure 7 - 28 Timing of fCLK and Count Clock (fTCLK) (When CCSmn = 1, Noise Filter Unused)
fCLK fMCK
TSmn (Write) < 1>
TEmn TImn input
Sampling wave
Rising edge detection signal ( fTCLK)
< 2> Edge detection <3>
Edge detection
<1> Setting TSmn bit to 1 enables the timer to be started and to become wait state for valid edge of input signal via the TImn pin.
<2> The rise of input signal via the TImn pin is sampled by fMCK. <3> The edge is detected by the rising of the sampled signal and the detection signal (count clock) is output.
Remark 1. : Rising edge of the count clock : Synchronization, increment/decrement of counter
Remark 2. fCLK: CPU/peripheral hardware clock fMCK: Operation clock of channel n
Remark 3. The waveform of the input signal via TImn pin of the input pulse interval measurement, the measurement of high/low width of input signal, and the delay counter, the one-shot pulse output are the same.
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
7.5.2 Timing of the start of counting
Timer counter register mn (TCRmn) becomes enabled to operation by setting of TSmn bit of timer channel start register m (TSm). Operations from count operation enabled state to timer counter register mn (TCRmn) count start is shown in Table 7 - 6.
Table 7 - 6 Operations from the Count Operation Enabled State to the Start of Counting by a Timer Counter Register mn (TCRmn)
Timer operation mode
Operation when TSmn = 1 is set
· Interval timer mode
No operation is carried out from start trigger detection (TSmn=1) until count clock
generation.
The first count clock loads the value of the TDRmn register to the TCRmn register and the subsequent count clock performs count down operation (see 7.5.3 (1) Operation in interval timer mode).
· Event counter mode
Writing 1 to the TSmn bit loads the value of the TDRmn register to the TCRmn register.
If detect edge of TImn input. The subsequent count clock performs count down operation (see 7.5.3 (2) Operation in event counter mode).
· Capture mode
No operation is carried out from start trigger detection (TSmn = 1) until count clock
generation.
The first count clock loads 0000H to the TCRmn register and the subsequent count clock performs count up operation (see 7.5.3 (3) Operation in capture mode (input pulse interval measurement)).
· One-count mode
The waiting-for-start-trigger state is entered by writing 1 to the TSmn bit while the timer
is stopped (TEmn = 0).
No operation is carried out from start trigger detection until count clock generation. The first count clock loads the value of the TDRmn register to the TCRmn register and the subsequent count clock performs count down operation (see 7.5.3 (4) Operation in one-count mode).
· Capture & one-count mode
The waiting-for-start-trigger state is entered by writing 1 to the TSmn bit while the timer is stopped (TEmn = 0).
No operation is carried out from start trigger detection until count clock generation.
The first count clock loads 0000H to the TCRmn register and the subsequent count clock performs count up operation (see 7.5.3 (5) Operation in capture & one-count mode (high-level width measurement)).
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
7.5.3 Operations of Counters
Here, the counter operation in each mode is explained.
(1) Operation in interval timer mode
<1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. Timer counter register mn (TCRmn) holds the initial value until count clock generation.
<2> A start trigger is generated at the first count clock after operation is enabled. <3> When the MDmn0 bit is set to 1, INTTMmn is generated by the start trigger. <4> By the first count clock after the operation enable, the value of timer data register mn (TDRmn) is loaded to the
TCRmn register and counting starts in the interval timer mode. <5> When the TCRmn register counts down and its count value is 0000H, INTTMmn is generated and the value of
timer data register mn (TDRmn) is loaded to the TCRmn register and counting keeps on.
Figure 7 - 29 Timing during Operation in Interval Timer Mode
fMC K (fTCLK)
TSmn(Write)
<1 >
TEmn
<2 >
Start trigger detection signal
TCRmn
TDRmn
Initial value
<3>
m <4>
m - 1
INTTMmn
When MDmn0 = 1 setting
0001
0000
m
m <5>
Caution
In the first cycle operation of count clock after writing the TSmn bit, an error at a maximum of one clock is generated since count start delays until count clock has been generated. When the information on count start timing is necessary, an interrupt can be generated at count start by setting MDmn0 = 1.
Remark fMCK, the start trigger detection signal, and INTTMmn become active between one clock in synchronization with fCLK.
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
(2) Operation in event counter mode
<1> Timer counter register mn (TCRmn) holds its initial value while operation is stopped (TEmn = 0). <2> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. <3> As soon as 1 has been written to the TSmn bit and 1 has been set to the TEmn bit, the value of timer data register
mn (TDRmn) is loaded to the TCRmn register to start counting. <4> After that, the TCRmn register value is counted down according to the count clock of the valid edge of the TImn
input.
Figure 7 - 30 Timing during Operation in Event Counter Mode
fMCK
TSmn ( Write) < 1>
TEmn <2 >
TImn input
Count clock
Edge detection
Edge detection
Start trigger detection signal
TCRmn
<1>
Initial value
<3> <3>
< 4> m
m-1
m-2
TDRmn
m
Remark
Figure 7 - 30 shows the timing when the noise filter is not used. By making the noise filter on-state, the edge detection
becomes 2 fMCK cycles (it sums up to 3 to 4 cycles) later than the normal cycle of TImn input. The error per one period occurs be the asynchronous between the period of the TImn input and that of the count clock (fMCK).
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(3) Operation in capture mode (input pulse interval measurement)
<1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. <2> Timer counter register mn (TCRmn) holds the initial value until count clock generation. <3> A start trigger is generated at the first count clock after operation is enabled. And the value of 0000H is loaded to
the TCRmn register and counting starts in the capture mode. (When the MDmn0 bit is set to 1, INTTMmn is generated by the start trigger.) <4> On detection of the valid edge of the TImn input, the value of the TCRmn register is captured to timer data register mn (TDRmn) and INTTMmn is generated. However, this captured value is meaningless. The TCRmn register keeps on counting from 0000H. <5> On next detection of the valid edge of the TImn input, the value of the TCRmn register is captured to timer data register mn (TDRmn) and INTTMmn is generated.
Figure 7 - 31 Timing during Operation in Capture Mode (Input Pulse Interval Measurement)
fMCK
TSmn (Write) TEmn
TImn input Rising edge
<1> <3>
Note
Edge detection
Start trigger detection signal
TCRmn
<2>
Initial value
<3>
0000
<4>
0001
0000
Edge detection <5>
m- 1
m
0000
TDRmn
0001Note
m
Note
INTTMmn
When MDmn0 = 1
If a clock has been input to TImn (the trigger exists) when capturing starts, counting starts when a trigger is detected, even if no edge is detected. Therefore, the first captured value (<4>) does not determine a pulse interval (in the above figure, 0001 just indicates two clock cycles but does not determine the pulse interval) and so the user can ignore it.
Caution
In the first cycle operation of count clock after writing the TSmn bit, an error at a maximum of one clock is generated since count start delays until count clock has been generated. When the information on count start timing is necessary, an interrupt can be generated at count start by setting MDmn0 = 1.
Remark
Figure 7 - 31 shows the timing when the noise filter is not used. By making the noise filter on-state, the edge detection
becomes 2 fMCK cycles (it sums up to 3 to 4 cycles) later than the normal cycle of TImn input. The error per one period occurs be the asynchronous between the period of the TImn input and that of the count clock (fMCK).
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(4) Operation in one-count mode
<1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. <2> Timer counter register mn (TCRmn) holds the initial value until start trigger generation. <3> Rising edge of the TImn input is detected. <4> On start trigger detection, the value of timer data register mn (TDRmn) is loaded to the TCRmn register and count
starts. <5> When the TCRmn register counts down and its count value is 0000H, INTTMmn is generated and the value of the
TCRmn register becomes FFFFH and counting stops.
Figure 7 - 32 Timing during Operation in One-Count Mode
fMCK (fTCLK) TSmn (Write)
TEmn TImn input
Rising edge Start trigger detection signal
TCRmn
<1>
<3> Edge detection
<4>
<2>
Initial value
m
INTTMmn
Start trigger input wait state
<5>
1
0
FFFF
Remark
Figure 7 - 32 shows the timing when the noise filter is not used. By making the noise filter on-state, the edge detection
becomes 2 fMCK cycles (it sums up to 3 to 4 cycles) later than the normal cycle of TImn input. The error per one period occurs be the asynchronous between the period of the TImn input and that of the count clock (fMCK).
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(5) Operation in capture & one-count mode (high-level width measurement)
<1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit of timer channel start register m (TSm). <2> Timer counter register mn (TCRmn) holds the initial value until start trigger generation. <3> Rising edge of the TImn input is detected. <4> On start trigger detection, the value of 0000H is loaded to the TCRmn register and count starts. <5> On detection of the falling edge of the TImn input, the value of the TCRmn register is captured to timer data register
mn (TDRmn) and INTTMmn is generated.
Figure 7 - 33 Timing during Operation in Capture & One-Count Mode (High-Level Width Measurement)
f MCK (fTCLK)
TSmn (Write) < 1>
TEmn
TImn input Rising edge Falling edge
< 3> Edge detection
<4>
Edge detection <5>
Start trigger detection signal
< 2>
TCRmn
Initial value
0000
m-1
m
m+1
TDRmn
0000
m
INTTMmn
Remark
Figure 7 - 33 shows the timing when the noise filter is not used. By making the noise filter on-state, the edge detection
becomes 2 fMCK cycles (it sums up to 3 to 4 cycles) later than the normal cycle of TImn input. The error per one period occurs be the asynchronous between the period of the TImn input and that of the count clock (fMCK).
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7.6
Channel Output (TOmn Pin) Control
7.6.1 TOmn pin output circuit configuration
Figure 7 - 34 Output Circuit Configuration
CHAPTER 7 TIMER ARRAY UNIT (TAU)
Interrupt signal of the master channel (INTTMmn)
Interrupt signal of the slave channel (INTTMmp)
Controller
<1>
<2>
<3>
TOLmn TOMmn
TOEmn
<5> TOmn register Set Reset/toggle
<4>
Enabling output (PFOE0n)Note
TOmn pin
Note The PFOE0n bits are only for unit 0.
Internal bus
TOmn write signal
The following describes the TOmn pin output circuit.
<1> When TOMmn = 0 (master channel output mode), the set value of timer output level register m (TOLm) is ignored and only INTTM0p (slave channel timer interrupt) is transmitted to timer output register m (TOm).
<2> When TOMmn = 1 (slave channel output mode), both INTTMmn (master channel timer interrupt) and INTTM0p (slave channel timer interrupt) are transmitted to the TOm register. At this time, the TOLm register becomes valid and the signals are controlled as follows:
When TOLmn = 0: Positive logic output (INTTMmn set, INTTM0p reset) When TOLmn = 1: Negative logic output (INTTMmn reset, INTTM0p set)
When INTTMmn and INTTM0p are simultaneously generated, (0% output of PWM), INTTM0p (reset signal) takes priority, and INTTMmn (set signal) is masked. <3> While timer output is enabled (TOEmn = 1), INTTMmn (master channel timer interrupt) and INTTM0p (slave channel timer interrupt) are transmitted to the TOm register. Writing to the TOm register (TOmn write signal) becomes invalid. When TOEmn = 1, the TOmn pin output never changes with signals other than interrupt signals. To initialize the TOmn pin output level, it is necessary to set timer operation is stopped (TOEmn = 0) and to write a value to the TOm register. <4> While timer output is disabled (TOEmn = 0), writing to the TOmn bit to the target channel (TOmn write signal) becomes valid. When timer output is disabled (TOEmn = 0), neither INTTMmn (master channel timer interrupt) nor INTTM0p (slave channel timer interrupt) is transmitted to the TOm register. <5> The TOm register can always be read, and the TOmn pin output level can be checked.
Remark
m: Unit number (m = 0, 1) n: Channel number n = 0 to 7 (n = 0, 2, 4, 6 for master channel) p: Slave channel number n < p 7
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7.6.2 TOmn pin output setting
The following figure shows the procedure and state transitions from the initial settings of a TOmn output pin to the start of timer operation.
Figure 7 - 35 State Transitions from the settings for timer output to the start of timer operation.
TCRmn (Counter)
Timer alternate-function pin
Undefined value (FFFFH after reset) Hi-Z
Timer output signal TOmn
TOEmn
Write operation enabled period to TOmn
Write operation disabled period to TOmn
<1> Set TOMmn <2> Set TOmn <3> Set TOEmn <4><5>
Set TOLmn
Set the port to
output mode
<6> Timer operation start
<1> The operation mode of timer output is set.
· TOMmn bit (0: Master channel output mode, 1: Slave channel output mode) · TOLmn bit (0: Positive logic output, 1: Negative logic output)
<2> The timer output signal is set to the initial state by setting timer output register m (TOm). <3> The timer output operation is enabled by writing 1 to the TOEmn bit (writing to the TOm register is disabled). <4> The port is set to digital I/O by the port mode control A register (PMCAxx), port mode control T register (PMCTxx),
port mode control E register (PMCEx), and port function output enable register (PFOEx) (see 7.3.17 Registers controlling port functions of pins to be used for timer I/O). <5> The port I/O setting is set to output (see 7.3.17 Registers controlling port functions of pins to be used for timer I/O). <6> The timer operation is enabled (TSmn = 1).
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
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7.6.3 Cautions on channel output operation
CHAPTER 7 TIMER ARRAY UNIT (TAU)
(1) Changing values set in the registers TOm, TOEm, and TOLm during timer operation Since the timer operations (operations of timer counter register mn (TCRmn) and timer data register mn (TDRmn)) are independent of the TOmn output circuit and changing the values set in timer output register m (TOm), timer output enable register m (TOEm), and timer output level register m (TOLm) does not affect the timer operation, the values can be changed during timer operation. To output an expected waveform from the TOmn pin by timer operation, however, set the TOm, TOEm, TOLm, and TOMm registers to the values stated in the register setting example of each operation shown in 7.7 and 7.8. When the values set to the TOEm, and TOMm registers (but not the TOm register) are changed close to the occurrence of the timer interrupt (INTTMmn) of each channel, the waveform output to the TOmn pin might differ, depending on whether the values are changed immediately before or immediately after the timer interrupt (INTTMmn) occurs.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
(2) Default level of TOmn pin and output level after timer operation start The change in the output level of the TOmn pin when timer output register m (TOm) is written while timer output is disabled (TOEmn = 0), the initial level is changed, and then timer output is enabled (TOEmn = 1) before port output is enabled, is shown below.
(a) When operation starts with master channel output mode (TOMmn = 0) setting The setting of timer output level register m (TOLm) is invalid when master channel output mode (TOMmn = 0). When the timer operation starts after setting the default level, the toggle signal is generated and the output level of the TOmn pin is inverted.
Figure 7 - 36 TOmn Pin Output States with Toggled Output (TOMmn = 0)
TOEmn Hi-Z Default state
TOmn (output)
Port output is enabled Toggle
Toggle
Toggle
Toggle
TOmn bit = 0 (Default state: Low)
TOmn bit = 1 (Default state: High)
TOmn bit = 0 (Default state: Low)
TOmn bit = 1 (Default state: High)
TOLmn bit = 0 (Active high)
TOLmn bit = 1 (Active low)
Toggle
Bold: Active level
Remark 1. Toggle: Toggle signal to invert the output on the TOmn pin Remark 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
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(b) When operation starts with slave channel output mode (TOMmp = 1) setting (PWM output) When slave channel output mode (TOMmp = 1), the active level is determined by timer output level register m (TOLm) setting.
Figure 7 - 37 TOmp Pin Output States with PWM Output (TOMmp = 1)
TOEmp Hi-Z Default state
Active
TOmp (output)
Port output is enabled
Active
Active TOmp bit = 0 (Default state: Low)
TOmp bit = 1 (Default state: High)
TOLmp bit = 0 (Active high)
TOmp bit = 0 (Default state: Low)
TOmp bit = 1 (Default state: High)
TOLmp bit = 1 (Active low)
Reset
Reset
Set
Set
Set
Remark 1. Set: The output signal of the TOmp pin changes from inactive level to active level.
Reset: The output signal of the TOmp pin changes from active level to inactive level.
Remark 2. m: Unit number (m = 0, 1), p: Channel number (p = 1 to 7)
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(3) Operation of TOmn pin in slave channel output mode (TOMmn = 1)
(a) When the relevant bit of timer output level register m (TOLm) is changed during timer operation When the TOLm register setting has been changed during timer operation, the setting becomes valid at the generation timing of the TOmn pin change condition. Rewriting the TOLm register does not change the output level of the TOmn pin. The operation when TOMmn is set to 1 and the value of the TOLm register is changed while the timer is operating (TEmn = 1) is shown below.
Figure 7 - 38 Operation When the Relevant Bit of the TOLm Register is Changed during Timer Operation
TOLm
TOmn (output )
Active
Active
Active
Active
Reset
Reset
Reset
Reset
Set
Set
Set
Set
Remark 1. Set: The output signal of the TOmn pin changes from inactive level to active level. Reset: The output signal of the TOmn pin changes from active level to inactive level.
Remark 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
(b) Set/reset timing To realize 0%/100% output at PWM output, the TOmn pin/TOmn bit set timing at master channel timer interrupt (INTTMmn) generation is delayed by 1 count clock by the slave channel. If the set condition and reset condition are generated at the same time, a higher priority is given to the latter. Figure 7 - 39 shows the states of operation following set and reset signals when the master and slave channels are set as follows.
Master channel: TOEmn = 1, TOMmn = 0, TOLmn = 0 Slave channel: TOEmp = 1, TOMmp = 1, TOLmp = 0
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RL78/G23 Figure 7 - 39 States of Operation following Set and Reset Signals (1) Basic timing during operation
fTCLK
INTTMmn
Master channel
Internal reset signal
TOmn pin/TOmn Toggle
Slave channel
Internal reset signal 1 clock delay
INTTMmp
Internal reset signal
TOmp pin/TOmp Set
Reset
(2) Timing during operation with the duty cycle set to 0%
fTCLK
INTTMmn
Master channel
Internal reset signal
TOmn pin/TOmn
Toggle
Internal reset signal
1 clock delay
TCRmp
0000 0001
Slave channel
INTTMmp
Internal reset signal
Reset
Set
TOmp pin/TOmp
Reset has priority .
(Remarks are listed on the next page.)
CHAPTER 7 TIMER ARRAY UNIT (TAU)
Toggle Set
Toggle
0000
0001
Set Reset
Reset has priority .
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Remark 1. Internal reset signal: TOmn pin reset/toggle signal Internal set signal: TOmn pin set signal
Remark 2. m: Unit number (m = 0, 1) n: Channel number n = 0 to 7 (n = 0, 2, 4, 6 for master channel) p: Slave channel number n < p 7
CHAPTER 7 TIMER ARRAY UNIT (TAU)
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
7.6.4 Collective manipulation of TOmn bit
In timer output register m (TOm), the setting bits for all the channels are located in one register in the same way as timer channel start register m (TSm). Therefore, the TOmn bit of all the channels can be manipulated collectively. Only the desired bits can also be manipulated by enabling writing only to the TOmn bits (TOEmn = 0) that correspond to the relevant bits of the channel used to perform output (TOmn).
Figure 7 - 40 Example of TO0n Bit Collective Manipulation
Before writing
TO0
0
0
0
0
0
0
0
0 TO07 TO06 TO05 TO04 TO03 TO02 TO01 TO00
0
0
1
0
0
0
1
0
TOE0 0
0
0
0
0
0
0
0 TOE07 TOE06 TOE05 TOE04 TOE03 TOE02 TOE01 TOE00
0
0
1
0
1
1
1
1
Data to be written
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
After writing
TO0
0
0
0
0
0
0
0
0 TO07 TO06 TO05 TO04 TO03 TO02 TO01 TO00
1
1
1
0
0
0
1
0
Writing is done only to the TOmn bit with TOEmn = 0, and writing to the TOmn bit with TOEmn = 1 is ignored. TOmn (channel output) to which TOEmn = 1 is set is not affected by the write operation. Even if the write operation is done to the TOmn bit, it is ignored and the output change by timer operation is normally done.
Figure 7 - 41 TO0n Pin States by Collective Manipulation of TO0n Bits
TO07 TO06 TO05 TO04 TO03 TO02 TO01 TO00
Remark
Before writing Writing to the TO0n bit
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
The levels of two or more TO0n outputs can be changed simultaneously.
The output level does not change unless the value of TO0n is changed.
Writing to the TO0n bit is ignored when TOE0n = 1.
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
7.6.5 Timer interrupts and TOmn outputs when counting is started
In the interval timer mode or capture mode, the MDmn0 bit in timer mode register mn (TMRmn) sets whether or not to generate a timer interrupt at count start. When MDmn0 is set to 1, the count operation start timing can be known by the timer interrupt (INTTMmn) generation. In the other modes, neither timer interrupt at count operation start nor TOmn output is controlled. Figure 7 - 42 shows operation examples when the interval timer mode (TOEmn = 1, TOMmn = 0) is set.
Figure 7 - 42 Examples of the Operation of Timer Interrupts and TOmn Outputs When Counting is Started
(a) When MDmn0 is set to 1
TCRmn TEmn
INTTMmn TOmn
(b) When MDmn0 is set to 0
Count operation start
TCRmn TEmn
INTTMmn TOmn
Count operation start
When MDmn0 is set to 1, a timer interrupt (INTTMmn) is output at count operation start, and TOmn performs a toggle operation. When MDmn0 is set to 0, a timer interrupt (INTTMmn) is not output at count operation start, and TOmn does not change either. After counting one cycle, INTTMmn is output and TOmn performs a toggle operation.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
7.7
Timer Input (TImn) Control
7.7.1 TImn input circuit configuration
A signal is input from a timer input pin, goes through a noise filter and an edge detector, and is sent to a timer controller. Enable the noise filter for the pin in need of noise removal. The following shows the configuration of the input circuit.
Figure 7 - 43 Input Circuit Configuration
Interrupt signal from master channel fMCK
TImn pin
Noise filter
Edge detection
Count clock sele ction
CCSmn
f TCLK Timer
controller
Trigg er selectio n
TNFENmn
CISmn1, CISmn0
STSmn2 to STSmn0
7.7.2 Noise filter
When the noise filter is disabled, the input signal is only synchronized with the operating clock (fMCK) for channel n. When the noise filter is enabled, after synchronization with the operating clock (fMCK) for channel n, whether the signal keeps the same value for two clock cycles is detected. The following shows differences in waveforms output from the noise filter between when the noise filter is enabled and disabled.
Figure 7 - 44 Sampling Waveforms through TImn Input Pin with Noise Filter Enabled and Disabled
TImn pin Noise filter disabled Noise filter enabled
Operating clock (fMCK)
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7.7.3 Cautions on channel input operation
When a timer input pin is set as unused, the operating clock is not supplied to the noise filter. Therefore, after settings are made to use the timer input pin, the following wait time is necessary before a trigger is specified to enable operation of the channel corresponding to the timer input pin.
(1) Noise filter is disabled When bits 12 (CCSmn), 9 (STSmn1), and 8 (STSmn0) in the timer mode register mn (TMRmn) are 0 and then one of them is set to 1, wait for at least two cycles of the operating clock (fMCK), and then set the operation enable trigger bit in the timer channel start register (TSm).
(2) Noise filter is enabled When bits 12 (CCSmn), 9 (STSmn1), and 8 (STSmn0) in the timer mode register mn (TMRmn) are all 0 and then one of them is set to 1, wait for at least four cycles of the operating clock (fMCK), and then set the operation enable trigger bit in the timer channel start register (TSm).
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
7.8
Independent Channel Operation Function of Timer Array Unit
7.8.1 Operation as an interval timer or for square wave output
(1) Interval timer The timer array unit can be used as a reference timer that generates INTTMmn (timer interrupt) at fixed intervals. The interrupt generation period can be calculated by the following expression.
Generation period of INTTMmn (timer interrupt) = Period of count clock × (Set value of TDRmn + 1)
(2) Operation for square wave output TOmn performs a toggle operation as soon as INTTMmn has been generated, and outputs a square wave with a duty factor of 50%. The period and frequency for outputting a square wave from TOmn can be calculated by the following expressions.
· Period of square wave output from TOmn = Period of count clock × (Set value of TDRmn + 1) × 2
· Frequency of square wave output from TOmn = Frequency of count clock/{(Set value of TDRmn + 1) × 2}
Timer counter register mn (TCRmn) operates as a down counter in the interval timer mode. The TCRmn register loads the value of timer data register mn (TDRmn) at the first count clock after the channel start trigger bit (TSmn, TSHm1, TSHm3) of timer channel start register m (TSm) is set to 1. If the MDmn0 bit of timer mode register mn (TMRmn) is 0 at this time, INTTMmn is not output and the output on TOmn is not toggled. If the MDmn0 bit of the TMRmn register is 1, INTTMmn is output and the output on TOmn is toggled. After that, the TCRmn register count down in synchronization with the count clock. When TCRmn = 0000H, INTTMmn is output and the output on TOmn is toggled at the next count clock. At the same time, the TCRmn register loads the value of the TDRmn register again. After that, the same operation is repeated. The TDRmn register can be rewritten at any time. The new value of the TDRmn register becomes valid from the next period.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
Figure 7 - 45 Block Diagram for Operation as an Interval Timer or for Square Wave Output
Clock selection
CKm1 Operation clockNote
CKm0 TSmn
Timer counter register mn (TCRmn)
Timer data register mn (TDRmn)
Output controller
TOmn pin
Interrupt controller
Interrupt signal (INTTMmn)
Trigger selection
Note
For channels 1 and 3, the clock can be selected as CKm0, CKm1, CKm2, or CKm3.
Figure 7 - 46 Example of Basic Timing during Operation as an Interval Timer or for Square Wave Output (MDmn0 = 1)
TSmn TEmn
TCRmn 0000H
TDRmn
a
b
TOmn
INTTMmn
a+1 a+1 a+1 b+1 b+1 b+1
Remark 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) Remark 2. TSmn: Bit n of timer channel start register m (TSm)
TEmn: Bit n of timer channel enable status register m (TEm) TCRmn: Timer counter register mn (TCRmn) TDRmn: Timer data register mn (TDRmn) TOmn: TOmn pin output signal
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Figure 7 - 47 Example of Register Settings for Operation as an Interval Timer or for Square Wave Output
(a) Timer mode register mn (TMRmn)
Symbol 15 14 13 12 11 10
9
8
7
6
5
TMRmn CKSmn1 CKSmn0 1/0 1/0
0
CCSmn M/SNote STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
0 0/1 0
0
0
0
0
0
4
3
2
1
0
0
MDmn3 MDmn2 MDmn1 MDmn0
0
0
0 1/0
Operation mode of channel n 000B: Interval timer
Setting of operation when counting is started 0: Neither generates INTTMmn nor inverts timer output when counting is started. 1: Generates INTTMmn and inverts timer output when counting is started.
Selection of TImn pin input edge 00B: Set to 00B because the TImn input pin is
not to be used.
Start trigger selection 000B: Selects only software start.
Setting of MASTERmn bit (channels 2, 4, 6) 0: Independent channel operation function.
Setting of SPLITmn bit (channels 1, 3) 0: 16-bit timer mode 1: 8-bit timer mode
Count clock selection
0: Selects operation clock (fMCK). Selection of the operating clock (fMCK)
00B: Selects CKm0 as the operating clock for channel n. 10B: Selects CKm1 as the operating clock for channel n. 01B: Selects CKm2 as the operating clock (this can only be selected for channels 1 and 3). 11B: Selects CKm3 as the operating clock (this can only be selected for channels 1 and 3).
(b) Timer output register m (TOm)
TOm
Bit n
TOmn 1/0
0: Outputs 0 from TOmn. 1: Outputs 1 from TOmn.
(c) Timer output enable register m (TOEm)
Bit n
TOEm TOEmn 1/0
0: Stops the TOmn output operation by counting operation. 1: Enables the TOmn output operation by counting operation.
(d) Timer output level register m (TOLm)
Bit n
TOLm TOLmn 0
0: Set this bit to 0 when TOMmn = 0 (master channel output mode)
(e) Timer output mode register m (TOMm)
Bit n
TOMm TOMmn 0
0: Sets master channel output mode.
Note
TMRm2, TMRm4, TMRm6: TMRm1, TMRm3: TMRm0, TMRm5, TMRm7:
MASTERmn bit SPLITmn bit Fixed to 0
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
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Figure 7 - 48 Procedure for Operations When the Interval Timer or Square Wave Output Function is to be Used
Software Operation
Hardware State
TAU default setting
Power-off state (Clock supply is stopped and writing to each register is disabled.)
Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1.
Power-on state. Each channel stops operating. (Clock supply is started and writing to each register is enabled.)
Sets timer clock select register m (TPSm). Determines clock frequencies of CKm0 to CKm3.
Channel default setting
Sets timer mode register mn (TMRmn) (determines operation mode of channel). Sets interval (period) value to timer data register mn (TDRmn).
Channel stops operating. (Clock is supplied and some power is consumed.)
To use the TOmn output Clears the TOMmn bit of timer output mode register m (TOMm) to 0 (master channel output mode). Clears the TOLmn bit to 0. Sets the TOmn bit and determines default level of the TOmn output.
Sets the TOEmn bit to 1 and enables operation of TOmn.
Clears the port register and port mode register to 0.
The TOmn pin goes into Hi-Z output state.
The TOmn default setting level is output when the port mode register is in the output mode and the port register is 0. TOmn does not change because channel stops operating. The TOmn pin outputs the TOmn set level.
Operation start
(Sets the TOEmn bit to 1 only if using TOmn output and resuming operation.). Sets the TSmn (TSHm1, TSHm3) bit to 1.
The TSmn (TSHm1, TSHm3) bit automatically returns to 0 because it is a trigger bit.
TEmn (TEHm1, TEHm3) = 1, and count operation starts. Value of the TDRmn register is loaded to timer counter register mn (TCRmn). INTTMmn is generated and TOmn performs toggle operation if the MDmn0 bit of the TMRmn register is 1.
During operation
Set values of the TMRmn register, TOMmn, and TOLmn bits cannot be changed. Set value of the TDRmn register can be changed. The TCRmn register can always be read. The TSRmn register is not used. Set values of the TOm and TOEm registers can be changed.
Counter (TCRmn) counts down. When count value reaches 0000H, the value of the TDRmn register is loaded to the TCRmn register again and the count operation is continued. By detecting TCRmn = 0000H, INTTMmn is generated and TOmn performs toggle operation. After that, the above operation is repeated.
Operation The TTmn (TTHm1, TTHm3) bit is set to 1.
stop
The TTmn (TTHm1, TTHm3) bit automatically returns
to 0 because it is a trigger bit.
TEmn (TEHm1, TEHm3) = 0, and count operation stops. The TCRmn register holds count value and stops. The TOmn output is not initialized and retains its current state.
The TOEmn bit is cleared to 0 and value is set to the TOmn bit.
The TOmn pin outputs the TOmn bit set level.
TAU stop
To hold the TOmn pin output level Clears the TOmn bit to 0 after the value to be held is set to the port register.
When holding the TOmn pin output level is not necessary Setting not required.
The TOmn pin output level is held by port function.
The TAUmEN bit of the PER0 register is cleared to 0. Set the TAUmRES bit of the PRR0 register to 1 to initialize all circuits of the timer array unit.
This stops supply of the input clock to timer array unit m.
All circuits are initialized and SFR of each channel is also initialized. (The TOmn bit is cleared to 0 and the TOmn pin is set to port mode.)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
Operation is resumed.
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7.8.2 Operation as an external event counter
The timer array unit can be used as an external event counter that counts the number of times the valid input edge (external event) is detected in the TImn pin. When a specified count value is reached, the event counter generates an interrupt. The specified number of counts can be calculated by the following expression.
Specified number of counts = Set value of TDRmn + 1
Timer counter register mn (TCRmn) operates as a down counter in the event counter mode. The TCRmn register loads the value of timer data register mn (TDRmn) by setting any channel start trigger bit (TSmn) of timer channel start register m (TSm) to 1. The TCRmn register counts down each time the valid input edge of the TImn pin has been detected. When TCRmn = 0000H, the TCRmn register loads the value of the TDRmn register again, and outputs INTTMmn. After that, the above operation is repeated. An irregular waveform that depends on external events is output from the TOmn pin. Stop the output by setting the TOEmn bit of timer output enable register m (TOEm) to 0. The TDRmn register can be rewritten at any time. The new value of the TDRmn register becomes valid during the next count period.
Figure 7 - 49 Block Diagram for Operation as an External Event Counter
TImn pin
TNFENmn
Noise filter
Edge detection
Timer counter register mn (TCRmn)
Trigger selection Clock selection
TSmn
Timer data register mn (TDRmn)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
Interrupt controller
Interrupt signal (INTTMmn)
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Figure 7 - 50 Example of Basic Timing during Operation as an External Event Counter
TSmn TEmn
TImn
TCRmn
3
0000H
2
3
10
2
TDRmn
0003H
2
1
1
0
0
0002H
21
INTTMmn
4 events
4 events
3 events
Remark 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) Remark 2. TSmn: Bit n of timer channel start register m (TSm)
TEmn: Bit n of timer channel enable status register m (TEm) TImn: TImn pin input signal TCRmn: Timer counter register mn (TCRmn) TDRmn: Timer data register mn (TDRmn)
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Figure 7 - 51 Example of Register Settings in External Event Counter Mode
(a) Timer mode register mn (TMRmn)
Symbol 15 14 13 12 11 10
9
8
7
6
5
TMRmn CKSmn1 CKSmn0 1/0 1/0
0
CCSmn M/SNote STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
0 0/1 0
0
0 1/0 1/0
0
4
3
2
1
0
0
MDmn3 MDmn2 MDmn1 MDmn0
0
1
1
0
Operation mode of channel n 011B: Event count mode
Setting of operation when counting is started 0: Neither generates INTTMmn nor inverts timer output when counting is started.
Selection of TImn pin input edge 00B: Detects falling edge. 01B: Detects rising edge. 10B: Detects both edges. 11B: Setting prohibited
Start trigger selection 000B: Selects only software start.
Setting of MASTERmn bit (channels 2, 4, 6) 0: Independent channel operation function.
Setting of SPLITmn bit (channels 1, 3) 0: 16-bit timer mode 1: 8-bit timer mode
Count clock selection 1: Selects the TImn pin input valid edge.
Selection of the operating clock (fMCK)
00B: Selects CKm0 as the operating clock for channel n. 10B: Selects CKm1 as the operating clock for channel n. 01B: Selects CKm2 as the operating clock (this can only be selected for channels 1 and 3). 11B: Selects CKm3 as the operating clock (this can only be selected for channels 1 and 3).
(b) Timer output register m (TOm)
TOm
Bit n
TOmn 0
0: Outputs 0 from TOmn.
(c) Timer output enable register m (TOEm)
Bit n
TOEm TOEmn 0
0: Stops the TOmn output operation by counting operation.
(d) Timer output level register m (TOLm)
Bit n
TOLm TOLmn 0
0: Set this bit to 0 when TOMmn = 0 (master channel output mode).
(e) Timer output mode register m (TOMm)
Bit n
TOMm TOMmn 0
0: Sets master channel output mode.
Note Remark
TMRm2, TMRm4, TMRm6: MASTERmn bit
TMRm1, TMRm3:
SPLITmn bit
TMRm0, TMRm5, TMRm7: Fixed to 0
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
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Figure 7 - 52 Procedure for Operations When the External Event Counter Function is to be Used
Software Operation
Hardware State
TAU default setting
Power-off state (Clock supply is stopped and writing to each register is disabled.)
Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1.
Power-on state. Each channel stops operating. (Clock supply is started and writing to each register is enabled.)
Sets timer clock select register m (TPSm). Determines clock frequencies of CKm0 to CKm3.
Channel default setting
Sets the corresponding bit of the noise filter enable registers 1, 2 (NFEN1, NFEN2) to 0 (off) or 1 (on). Sets timer mode register mn (TMRmn) (determines operation mode of channel). Sets number of counts to timer data register mn (TDRmn). Clears the TOEmn bit of timer output enable register m (TOEm) to 0.
Channel stops operating. (Clock is supplied and some power is consumed.)
Operation start
Sets the TSmn bit to 1. The TSmn bit automatically returns to 0 because it is a trigger bit.
TEmn = 1, and count operation starts. Value of the TDRmn register is loaded to timer counter register mn (TCRmn) and detection of the TImn pin input edge is awaited.
During operation
Set value of the TDRmn register can be changed. The TCRmn register can always be read. The TSRmn register is not used. Set values of the TMRmn register, TOMmn, TOLmn, TOmn, and TOEmn bits cannot be changed.
Counter (TCRmn) counts down each time input edge of the TImn pin has been detected. When count value reaches 0000H, the value of the TDRmn register is loaded to the TCRmn register again, and the count operation is continued. By detecting TCRmn = 0000H, the INTTMmn output is generated. After that, the above operation is repeated.
Operation The TTmn bit is set to 1.
TEmn = 0, and count operation stops.
stop
The TTmn bit automatically returns to 0 because it is a The TCRmn register holds count value and stops.
trigger bit.
TAU stop
The TAUmEN bit of the PER0 register is cleared to 0. Set the TAUmRES bit of the PRR0 register to 1 to initialize all circuits of the timer array unit.
This stops supply of the input clock to timer array unit m.
All circuits are initialized and SFR of each channel is also initialized.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
Operation is resumed
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7.8.3 Operation as a frequency divider (channel 0 of unit 0 only)
The timer array unit can be used as a frequency divider that divides a clock input to the TI00 pin and outputs the result from the TO00 pin. The divided clock frequency output from TO00 can be calculated by the following expression.
· When rising edge/falling edge is selected: Divided clock frequency = Input clock frequency/{(Set value of TDR00 + 1) × 2}
· When both edges are selected: Divided clock frequency Input clock frequency/(Set value of TDR00 + 1)
Timer counter register 00 (TCR00) operates as a down counter in the interval timer mode. After the channel start trigger bit (TS00) of timer channel start register 0 (TS0) is set to 1, the TCR00 register loads the value of timer data register 00 (TDR00) when the TI00 valid edge is detected. If the MD000 bit of timer mode register 00 (TMR00) is 0 at this time, INTTM00 is not output and the output on TO00 is not toggled. If the MD000 bit of timer mode register 00 (TMR00) is 1, INTTM00 is output and the output on TO00 is toggled. After that, the TCR00 register counts down at the valid edge of the TI00 pin. When TCR00 = 0000H, it toggles the output on TO00. At the same time, the TCR00 register loads the value of the TDR00 register again, and continues counting. If detection of both the edges of the TI00 pin is selected, the duty factor error of the input clock affects the divided clock period of the TO00 output. The period of the TO00 output clock includes a sampling error of one period of the operation clock.
Clock period of TO00 output = Ideal TO00 output clock period ± Operation clock period (error)
The TDR00 register can be rewritten at any time. The new value of the TDR00 register becomes valid during the next count period.
Figure 7 - 53 Block Diagram for Operation as a Frequency Divider
TI00 pin
TNFEN00
Noise filter
Edge detection
Timer counter register 00 (TCR00)
Output controller
TO00 pin
Clock selection
TS00
Timer data register 00 (TDR00)
Trigger selection
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Figure 7 - 54 Example of Basic Timing during Operation as a Frequency Divider (MD000 = 1)
TS00 TE00
TI00
TCR00
2
2
2
1
1
11 1 1 1
0000H
0
0
00000
TDR00
0002H
0001H
TO00
INTTM00
Divided by 6
Remark
TS00: Bit 0 of timer channel start register 0 (TS0) TE00: Bit 0 of timer channel enable status register 0 (TE0) TI00: TI00 pin input signal TCR00: Timer counter register 00 (TCR00) TDR00: Timer data register 00 (TDR00) TO00: TO00 pin output signal
Divided by 4
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Figure 7 - 55 Example of Register Settings for Operation as a Frequency Divider
(a) Timer mode register 00 (TMR00)
Symbol 15 14 13 12 11 10
9
8
7
6
5
TMR00 CKS001 CKS000 1/0 0
0
CCS00
1
0
STS002 STS001 STS000 CIS001 CIS000
0
0
0 1/0 1/0
0
4
3
2
1
0
0
MD003 MD002 MD001 MD000
0
0
0 1/0
Operation mode of channel 0 000B: Interval timer
Setting of operation when counting is started 0: Neither generates INTTM00 nor inverts timer output when counting is started. 1: Generates INTTM00 and inverts timer output when counting is started.
Selection of TI00 pin input edge 00B: Detects falling edge. 01B: Detects rising edge. 10B: Detects both edges. 11B: Setting prohibited
Start trigger selection 000B: Selects only software start.
Count clock selection 1: Selects the TI00 pin input valid edge.
Operation clock (fMCK) selection
00B: Selects CK00 as operation clock of channel 0. 10B: Selects CK01 as operation clock of channel 0.
(b) Timer output register 0 (TO0)
Bit 0
TO0 TO00 1/0
0: Outputs 0 from TO00. 1: Outputs 1 from TO00.
(c) Timer output enable register 0 (TOE0)
Bit 0
TOE0 TOE00 1/0
0: Stops the TO00 output operation by counting operation. 1: Enables the TO00 output operation by counting operation.
(d) Timer output level register 0 (TOL0)
Bit 0
TOL0 TOL00 0
0: Set this bit to 0 when master channel output mode (TOM00 = 0)
(e) Timer output mode register 0 (TOM0)
Bit 0
TOM0 TOM00 0
0: Sets master channel output mode.
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Figure 7 - 56 Procedure for Operations When the Frequency Divider Function is to be Used (1/2)
TAU default setting
Software Operation
Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1.
Channel default setting
Sets timer clock select register 0 (TPS0). Determines clock frequencies of CK00 to CK03.
Sets the corresponding bit of the noise filter enable registers 1, 2 (NFEN1, NFEN2) to 0 (off) or 1 (on). Sets timer mode register 0n (TMR0n) (determines operation mode of channel and selects the detection edge). Sets interval (period) value to timer data register 00 (TDR00).
Clears the TOM00 bit of timer output mode register 0 (TOM0) to 0 (master channel output mode). Clears the TOL00 bit to 0. Sets the TO00 bit and determines default level of the TO00 output.
Sets the TOE00 bit to 1 and enables operation of TO00.
Clears the port register and port mode register to 0.
Hardware State Power-off state
(Clock supply is stopped and writing to each register is disabled.)
Power-on state. Each channel stops operating. (Clock supply is started and writing to each register is enabled.)
Channel stops operating. (Clock is supplied and some power is consumed.)
The TO00 pin goes into Hi-Z output state.
The TO00 default setting level is output when the port mode register is in output mode and the port register is 0. TO00 does not change because channel stops operating. The TO00 pin outputs the TO00 set level.
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Figure 7 - 56 Procedure for Operations When the Frequency Divider Function is to be Used (2/2)
Operation is resumed
Software Operation
Hardware State
Operation start
Sets the TOE00 bit to 1 (only when operation is resumed). Sets the TS00 bit to 1.
The TS00 bit automatically returns to 0 because it is a trigger bit.
TE00 = 1, and count operation starts. Value of the TDR00 register is loaded to timer counter register 00 (TCR00). INTTM00 is generated and TO00 performs toggle operation if the MD000 bit of the TMR00 register is 1.
During operation
Set value of the TDR00 register can be changed. The TCR00 register can always be read. The TSR00 register is not used. Set values of the TO0 and TOE0 registers can be changed. Set values of the TMR00 register, TOM00, and TOL00 bits cannot be changed.
Counter (TCR00) counts down. When count value reaches 0000H, the value of the TDR00 register is loaded to the TCR00 register again, and the count operation is continued. By detecting TCR00 = 0000H, INTTM00 is generated and TO00 performs toggle operation. After that, the above operation is repeated.
Operation stop
The TT00 bit is set to 1. The TT00 bit automatically returns to 0 because it is a trigger bit.
TE00 = 0, and count operation stops. The TCR00 register holds count value and stops. The TO00 output is not initialized and retains its current state.
The TOE00 bit is cleared to 0 and value is set to the TO00 bit.
The TO00 pin outputs the TO00 set level.
TAU stop
To hold the TO00 pin output level Clears the TO00 bit to 0 after the value to be held is set to the port register.
When holding the TO00 pin output level is not necessary Setting not required.
The TO00 pin output level is held by port function.
The TAU0EN bit of the PER0 register is cleared to 0. Set the TAUmRES bit of the PRR0 register to 1 to initialize all circuits of the timer array unit.
This stops supply of the input clock to timer array unit m.
All circuits are initialized and SFR of each channel is also initialized. (The TO00 bit is cleared to 0 and the TO00 pin is set to port mode).
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7.8.4 Operation for input pulse interval measurement
The count value can be captured at the TImn valid edge and the interval of the pulse input to TImn can be measured. In addition, the count value can be captured by using software operation (TSmn = 1) as a capture trigger while the TEmn bit is set to 1. The pulse interval can be calculated by the following expression.
TImn input pulse interval = Period of count clock × ((10000H × TSRmn: OVF) + (Captured value of TDRmn + 1))
Caution
The TImn pin input is sampled using the operating clock selected with the CKSmn bit of timer mode register mn (TMRmn), so an error of up to one operating clock cycle occurs.
Timer counter register mn (TCRmn) operates as an up counter in the capture mode. When the channel start trigger bit (TSmn) of timer channel start register m (TSm) is set to 1, the TCRmn register counts up from 0000H in synchronization with the count clock. When the TImn pin input valid edge is detected, the count value of the TCRmn register is transferred (captured) to timer data register mn (TDRmn) and, at the same time, the TCRmn register is cleared to 0000H, and the INTTMmn is output. If the counter overflows at this time, the OVF bit of timer status register mn (TSRmn) is set to 1. If the counter does not overflow, the OVF bit is cleared. After that, the above operation is repeated. As soon as the count value has been captured to the TDRmn register, the OVF bit of the TSRmn register is updated depending on whether the counter overflows during the measurement period. Therefore, the overflow state of the captured value can be checked. If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF bit of the TSRmn register is set to 1. However, a normal interval value cannot be measured for the OVF bit, if two or more overflows occur. Set the STSmn2 to STSmn0 bits of the TMRmn register to 001B to use the valid edges of TImn as a start trigger and a capture trigger.
Figure 7 - 57 Block Diagram for Operation for Input Pulse Interval Measurement
Clock selection
Operation clockNote TNFENmn
CKm1 CKm0
TImn pin
Noise filter
Edge detection
TSmn
Timer counter register mn (TCRmn)
Timer data register mn (TDRmn)
Interrupt controller
Trigger selection
Note
For channels 1 and 3, the clock can be selected as CKm0, CKm1, CKm2, or CKm3.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
Interrupt signal (INTTMmn)
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Figure 7 - 58 Example of Basic Timing during Operation for Input Pulse Interval Measurement (MDmn0 = 0)
TSmn TEmn
TImn
FFFFH
b
TCRmn
a
0000H
TDRmn 0000H
a
b
INTTMmn
OVF
Remark 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) Remark 2. TSmn: Bit n of timer channel start register m (TSm)
TEmn: Bit n of timer channel enable status register m (TEm) TImn: TImn pin input signal TCRmn: Timer counter register mn (TCRmn) TDRmn: Timer data register mn (TDRmn) OVF: Bit 0 of timer status register mn (TSRmn)
c
d
c
d
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Figure 7 - 59 Example of Register Settings for Operation for Input Pulse Interval Measurement
(a) Timer mode register mn (TMRmn)
Symbol 15 14 13 12 11 10
9
8
7
6
5
TMRmn CKSmn1 CKSmn0 1/0 0
0
CCSmn M/SNote STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
0
0
0
0
1 1/0 1/0
0
4
3
2
1
0
0
MDmn3 MDmn2 MDmn1 MDmn0
0
1
0 1/0
Operation mode of channel n 010B: Capture mode
Setting of operation when counting is started 0: Does not generate INTTMmn when counting is started. 1: Generates INTTMmn when counting is started.
Selection of TImn pin input edge 00B: Detects falling edge. 01B: Detects rising edge. 10B: Detects both edges. 11B: Setting prohibited
Capture trigger selection 001B: Selects the TImn pin input valid edge.
Setting of MASTERmn bit (channels 2, 4, 6) 0: Independent channel operation
Setting of SPLITmn bit (channels 1, 3) 0: 16-bit timer mode.
Count clock selection
0: Selects operation clock (fMCK).
Selection of the operating clock (fMCK)
00B: Selects CKm0 as the operating clock for channel n. 10B: Selects CKm1 as the operating clock for channel n. 01B: Selects CKm2 as the operating clock (this can only be selected for channels 1 and 3). 11B: Selects CKm3 as the operating clock (this can only be selected for channels 1 and 3).
(b) Timer output register m (TOm)
TOm
Bit n
TOmn 0
0: Outputs 0 from TOmn.
(c) Timer output enable register m (TOEm)
Bit n
TOEm TOEmn 0
0: Stops TOmn output operation by counting operation.
(d) Timer output level register m (TOLm)
Bit n
TOLm TOLmn 0
0: Set this bit to 0 when TOMmn = 0 (master channel output mode).
(e) Timer output mode register m (TOMm)
Bit n
TOMm TOMmn 0
0: Sets master channel output mode.
(Note and Remark are listed on the next page.)
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
Note
TMRm2, TMRm4, TMRm6: TMRm1, TMRm3: TMRm0, TMRm5, TMRm7:
MASTERmn bit SPLITmn bit Fixed to 0
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
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Figure 7 - 60 Procedure for Operations When the Input Pulse Interval Measurement Function is to be Used
Software Operation
Hardware State
TAU default setting
Power-off state (Clock supply is stopped and writing to each register is disabled.)
Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1.
Power-on state. Each channel stops operating. (Clock supply is started and writing to each register is enabled.)
Sets timer clock select register m (TPSm). Determines clock frequencies of CKm0 to CKm3.
Channel default setting
Sets the corresponding bit of the noise filter enable registers 1, 2 (NFEN1, NFEN2) to 0 (off) or 1 (on). Sets timer mode register mn (TMRmn) (determines operation mode of channel).
Channel stops operating. (Clock is supplied and some power is consumed.)
Operation start
Sets TSmn bit to 1. The TSmn bit automatically returns to 0 because it is a trigger bit.
TEmn = 1, and count operation starts. Timer counter register mn (TCRmn) is cleared to 0000H. When the MDmn0 bit of the TMRmn register is 1, INTTMmn is generated.
During operation
Set values of only the CISmn1 and CISmn0 bits of the TMRmn register can be changed. The TDRmn register can always be read. The TCRmn register can always be read. The TSRmn register can always be read. Set values of the TOMmn, TOLmn, TOmn, and TOEmn bits cannot be changed.
Counter (TCRmn) counts up from 0000H. When the valid edge of the TImn pin input is detected or the TSmn bit is set to 1, the count value is transferred (captured) to timer data register mn (TDRmn). At the same time, the TCRmn register is cleared to 0000H, and the INTTMmn signal is generated. If an overflow occurs at this time, the OVF bit of timer status register mn (TSRmn) is set; if an overflow does not occur, the OVF bit is cleared. After that, the above operation is repeated.
Operation The TTmn bit is set to 1.
TEmn = 0, and count operation stops.
stop
The TTmn bit automatically returns to 0 because it is a The TCRmn register holds count value and stops.
trigger bit.
The OVF bit of the TSRmn register is also held.
TAU stop
The TAUmEN bit of the PER0 register is cleared to 0. Set the TAUmRES bit of the PRR0 register to 1 to initialize all circuits of the timer array unit.
This stops supply of the input clock to timer array unit m.
All circuits are initialized and SFR of each channel is also initialized.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
Operation is resumed.
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7.8.5 Operation for input signal high-/low-level width measurement
Caution
When using a channel to implement the LIN-bus, set bit 1 (ISC1) of the input switch control register (ISC) to 1. In the following descriptions, read TImn as RxD2.
By starting counting at one edge of the TImn pin input and capturing the number of counts at another edge, the signal width (high-level width/low-level width) of TImn can be measured. The signal width of TImn can be calculated by the following expression.
Signal width of TImn input = Period of count clock × ((10000H × TSRmn: OVF) + (Captured value of TDRmn + 1))
Caution
The TImn pin input is sampled using the operating clock selected with the CKSmn bit of timer mode register mn (TMRmn), so an error equivalent to one operation clock occurs.
Timer counter register mn (TCRmn) operates as an up counter in the capture & one-count mode. When the channel start trigger bit (TSmn) of timer channel start register m (TSm) is set to 1, the TEmn bit is set to 1 and the TImn pin start edge detection wait state is set. When the TImn pin input start edge (rising edge of the TImn pin input when the high-level width is to be measured) is detected, the counter counts up from 0000H in synchronization with the count clock. When the valid capture edge (falling edge of the TImn pin input when the high-level width is to be measured) is detected later, the count value is transferred to timer data register mn (TDRmn) and, at the same time, INTTMmn is output. If the counter overflows at this time, the OVF bit of timer status register mn (TSRmn) is set to 1. If the counter does not overflow, the OVF bit is cleared. The TCRmn register stops at the value "value transferred to the TDRmn register + 1", and the TImn pin start edge detection wait state is set. After that, the above operation is repeated. As soon as the count value has been captured to the TDRmn register, the OVF bit of the TSRmn register is updated depending on whether the counter overflows during the measurement period. Therefore, the overflow state of the captured value can be checked. If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF bit of the TSRmn register is set to 1. However, a normal interval value cannot be measured for the OVF bit, if two or more overflows occur. Whether the high-level width or low-level width of the TImn pin is to be measured can be selected by using the CISmn1 and CISmn0 bits of the TMRmn register. Because this function is used to measure the signal width of the TImn pin input, the TSmn bit cannot be set to 1 while the TEmn bit is 1.
CISmn1, CISmn0 of TMRmn register = 10B: Low-level width is measured. CISmn1, CISmn0 of TMRmn register = 11B: High-level width is measured.
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
Figure 7 - 61 Block Diagram for Operation for Input Signal High-/Low-Level Width Measurement
Clock selection
Operation clockNote CKm1 CKm0
TImn pin
TNFENmn
Noise filter
Edge detection
Timer counter register mn (TCRmn)
Timer data register mn (TDRmn)
Interrupt controller
Interrupt signal (INTTMmn)
Trigger selection
Note
For channels 1 and 3, the clock can be selected as CKm0, CKm1, CKm2, or CKm3.
Figure 7 - 62 Example of Basic Timing during Operation for Input Signal High-/Low-Level Width Measurement
TSmn TEmn
TImn
FFFFH
a
TCRmn
0000H
TDRmn
0000H
INTTMmn
b
c
a
b
c
OVF
Remark 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) Remark 2. TSmn: Bit n of timer channel start register m (TSm)
TEmn: Bit n of timer channel enable status register m (TEm) TImn: TImn pin input signal TCRmn: Timer counter register mn (TCRmn) TDRmn: Timer data register mn (TDRmn) OVF: Bit 0 of timer status register mn (TSRmn)
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Figure 7 - 63 Example of Register Settings for Operation for Input Signal High-/Low-Level Width Measurement
(a) Timer mode register mn (TMRmn)
Symbol 15 14 13 12 11 10
9
8
7
6
5
TMRmn CKSmn1 CKSmn0 1/0 0
0
CCSn0 M/SNote STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
0
0
0
1
0
1 1/0
0
4
3
2
1
0
0
MDmn3 MDmn2 MDmn1 MDmn0
1
1
0
0
Operation mode of channel n 110B: Capture & one-count
Setting of operation when counting is started 0: Does not generate INTTMmn when counting is started.
Selection of TImn pin input edge 10B: Both edges (to measure low-level width) 11B: Both edges (to measure high-level width)
Start trigger selection 010B: Selects the TImn pin input valid edge.
Setting of MASTERmn bit (channels 2, 4, 6) 0: Independent channel operation function.
Setting of SPLITmn bit (channels 1, 3) 0: 16-bit timer mode.
Count clock selection
0: Selects operation clock (fMCK).
Selection of the operating clock (fMCK)
00B: Selects CKm0 as the operating clock for channel n. 10B: Selects CKm1 as the operating clock for channel n. 01B: Selects CKm2 as the operating clock (this can only be selected for channels 1 and 3). 11B: Selects CKm3 as the operating clock (this can only be selected for channels 1 and 3).
(b) Timer output register m (TOm)
Bit n
TOm TOmn 0
0: Outputs 0 from TOmn.
(c) Timer output enable register m (TOEm)
Bit n
TOEm TOEmn 0
0: Stops the TOmn output operation by counting operation.
(d) Timer output level register m (TOLm)
Bit n
TOLm TOLmn 0
0: Set this bit to 0 when TOMmn = 0 (master channel output mode).
(e) Timer output mode register m (TOMm)
Bit n
TOMm TOMmn 0
0: Sets master channel output mode.
Note Remark
TMRm2, TMRm4, TMRm6: MASTERmn bit
TMRm1, TMRm3:
SPLITmn bit
TMRm0, TMRm5, TMRm7: Fixed to 0
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
Figure 7 - 64 Procedure for Operations When the Input Signal High-/Low-Level Width Measurement Function is to be Used
Software Operation
Hardware State
TAU default setting
Power-off state (Clock supply is stopped and writing to each register is disabled.)
Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1.
Power-on state. Each channel stops operating. (Clock supply is started and writing to each register is enabled.)
Sets timer clock select register m (TPSm). Determines clock frequencies of CKm0 to CKm3.
Channel default setting
Sets the corresponding bit of the noise filter enable registers 1, 2 (NFEN1, NFEN2) to 0 (off) or 1 (on). Sets timer mode register mn (TMRmn) (determines operation mode of channel). Clears the TOEmn bit to 0 and stops operation of TOmn.
Channel stops operating. (Clock is supplied and some power is consumed.)
Operation Sets the TSmn bit to 1.
TEmn = 1, and the TImn pin start edge detection wait
start
The TSmn bit automatically returns to 0 because it is a state is set.
trigger bit.
Detects the TImn pin input count start valid edge.
Clears timer counter register mn (TCRmn) to 0000H and starts counting up.
During operation
Set value of the TDRmn register can always be read. The TCRmn register can always be read. The TSRmn register can always be read. Set values of the TMRmn register, TOMmn, TOLmn, TOmn, and TOEmn bits cannot be changed.
When the TImn pin start edge is detected, the counter (TCRmn) counts up from 0000H. If a capture edge of the TImn pin is detected, the count value is transferred to timer data register mn (TDRmn) and INTTMmn is generated. If an overflow occurs at this time, the OVF bit of timer status register mn (TSRmn) is set; if an overflow does not occur, the OVF bit is cleared. The TCRmn register stops the count operation until the next TImn pin start edge is detected.
Operation The TTmn bit is set to 1.
TEmn = 0, and count operation stops.
stop
The TTmn bit automatically returns to 0 because it is a The TCRmn register holds count value and stops.
trigger bit.
The OVF bit of the TSRmn register is also held.
TAU stop
The TAUmEN bit of the PER0 register is cleared to 0. Set the TAUmRES bit of the PRR0 register to 1 to initialize all circuits of the timer array unit.
This stops supply of the input clock to timer array unit m.
All circuits are initialized and SFR of each channel is also initialized.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
Operation is resumed.
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7.8.6 Operation as a delay counter
It is possible to start counting down when the valid edge of the TImn pin input is detected (an external event), and then generate INTTMmn (a timer interrupt) after any specified interval. It is also possible to start counting down and generate INTTMmn (timer interrupt) at any interval by setting TSmn to 1 by software while TEmn = 1. The interrupt generation period can be calculated by the following expression.
Generation period of INTTMmn (timer interrupt) = Period of count clock × (Set value of TDRmn + 1)
Timer counter register mn (TCRmn) operates as a down counter in the one-count mode. When the channel start trigger bit (TSmn, TSHm1, TSHm3) of timer channel start register m (TSm) is set to 1, the TEmn, TEHm1, TEHm3 bits are set to 1 and the TImn pin input valid edge detection wait state is set. Timer counter register mn (TCRmn) starts operating upon TImn pin input valid edge detection and loads the value of timer data register mn (TDRmn). The TCRmn register counts down from the value of the TDRmn register it has loaded, in synchronization with the count clock. When TCRmn = 0000H, it outputs INTTMmn and stops counting until the next TImn pin input valid edge is detected. The TDRmn register can be rewritten at any time. The new value of the TDRmn register becomes valid from the next period.
Figure 7 - 65 Block Diagram for Operation as a Delay Counter
Trigger selection Clock selection
CKm1 Operation clockNote
CKm0
TImn pin
TSmn TNFENmn
Noise filter
Edge detection
Timer counter register mn (TCRmn)
Timer data register mn (TDRmn)
Interrupt controller
Interrupt signal (INTTMmn)
Note
For channels 1 and 3, the clock can be selected as CKm0, CKm1, CKm2, or CKm3.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
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Figure 7 - 66 Example of Basic Timing during Operation as a Delay Counter
TSmn
TEmn
TImn
FFFFH
TCRmn
0000H
TDRmn
a
b
INTTMmn
a+1
b+1
Remark 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) Remark 2. TSmn: Bit n of timer channel start register m (TSm)
TEmn: Bit n of timer channel enable status register m (TEm) TImn: TImn pin input signal TCRmn: Timer counter register mn (TCRmn) TDRmn: Timer data register mn (TDRmn)
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
Figure 7 - 67 Example of Register Settings for Operation as a Delay Counter
(a) Timer mode register mn (TMRmn)
Symbol 15 14 13 12 11 10
9
8
7
6
5
TMRmn CKSmn1 CKSmn0 1/0 1/0
0
CCSmn M/SNote STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
0 0/1 0
0
1 1/0 1/0
0
4
3
2
1
0
0
MDmn3 MDmn2 MDmn1 MDmn0
1
0
0 1/0
Operation mode of channel n 100B: One-count mode
Start trigger during operation 0: Trigger input is invalid. 1: Trigger input is valid.
Selection of TImn pin input edge 00B: Detects falling edge. 01B: Detects rising edge. 10B: Detects both edges. 11B: Setting prohibited
Start trigger selection 001B: Selects the TImn pin input valid edge.
Setting of MASTERmn bit (channels 2, 4, 6) 0: Independent channel operation function.
Setting of SPLITmn bit (channels 1, 3) 0: 16-bit timer mode 1: 8-bit timer mode
Count clock selection
0: Selects operation clock (fMCK).
Selection of the operating clock (fMCK)
00B: Selects CKm0 as the operating clock for channel n. 10B: Selects CKm1 as the operating clock for channel n. 01B: Selects CKm2 as the operating clock (this can only be selected for channels 1 and 3). 11B: Selects CKm3 as the operating clock (this can only be selected for channels 1 and 3).
(b) Timer output register m (TOm)
TOm
Bit n
TOmn 0
0: Outputs 0 from TOmn.
(c) Timer output enable register m (TOEm)
Bit n
TOEm TOEmn 0
0: Stops the TOmn output operation by counting operation.
(d) Timer output level register m (TOLm)
Bit n
TOLm TOLmn 0
0: Set this bit to 0 when TOMmn = 0 (master channel output mode).
(e) Timer output mode register m (TOMm)
Bit n
TOMm TOMmn 0
0: Sets master channel output mode.
Note Remark
TMRm2, TMRm4, TMRm6: MASTERmn bit
TMRm1, TMRm3:
SPLITmn bit
TMRm0, TMRm5, TMRm7: Fixed to 0
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
Figure 7 - 68 Procedure for Operations When the Delay Counter Function is to be Used
Software Operation
Hardware State
TAU default setting
Power-off state (Clock supply is stopped and writing to each register is disabled.)
Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1.
Power-on state. Each channel stops operating. (Clock supply is started and writing to each register is enabled.)
Sets timer clock select register m (TPSm). Determines clock frequencies of CKm0 to CKm3.
Channel default setting
Sets the corresponding bit of the noise filter enable registers 1, 2 (NFEN1, NFEN2) to 0 (off) or 1 (on). Sets timer mode register mn (TMRmn) (determines operation mode of channel). INTTMmn output delay is set to timer data register mn (TDRmn). Clears the TOEmn bit to 0 and stops operation of TOmn.
Channel stops operating. (Clock is supplied and some power is consumed.)
Operation Sets the TSmn bit to 1.
TEmn = 1, and the start trigger detection (the valid edge
start
The TSmn bit automatically returns to 0 because it is a of the TImn pin input is detected or the TSmn bit is set to
trigger bit.
1) wait state is set.
The counter starts counting down by the next start trigger detection. · Detects the TImn pin input valid edge. · Sets the TSmn bit to 1 by the software.
Value of the TDRmn register is loaded to the timer counter register mn (TCRmn).
During operation
Set value of the TDRmn register can be changed. The TCRmn register can always be read. The TSRmn register is not used.
The counter (TCRmn) counts down. When the count value of TCRmn reaches 0000H, the INTTMmn output is generated, and the count operation stops until the next start trigger detection (the valid edge of the TImn pin input is detected or the TSmn bit is set to 1).
Operation The TTmn bit is set to 1.
TEmn = 0, and count operation stops.
stop
The TTmn bit automatically returns to 0 because it is a The TCRmn register holds count value and stops.
trigger bit.
TAU stop
The TAUmEN bit of the PER0 register is cleared to 0. Set the TAUmRES bit of the PRR0 register to 1 to initialize all circuits of the timer array unit.
This stops supply of the input clock to timer array unit m.
All circuits are initialized and SFR of each channel is also initialized.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
Operation is resumed.
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7.9
Simultaneous Channel Operation Function of Timer Array Unit
7.9.1 Operation for the one-shot pulse output function
By using two channels as a set, a one-shot pulse having any delay pulse width can be generated from the signal input to the TImn pin. The delay time and pulse width can be calculated by the following expressions.
Delay time = {Set value of TDRmn (master) + 2} × Count clock period Pulse width = {Set value of TDRmp (slave)} × Count clock period
The master channel operates in the one-count mode and counts the delays. Timer counter register mn (TCRmn) of the master channel starts operating upon start trigger detection and loads the value of timer data register mn (TDRmn). The TCRmn register counts down from the value of the TDRmn register it has loaded, in synchronization with the count clock. When TCRmn = 0000H, it outputs INTTMmn and stops counting until the next start trigger is detected. The slave channel operates in the one-count mode and counts the pulse width. The TCRmp register of the slave channel starts operation using INTTMmn of the master channel as a start trigger, and loads the value of the TDRmp register. The TCRmp register counts down from the value of The TDRmp register it has loaded, in synchronization with the count value. When count value = 0000H, it outputs INTTMmp and stops counting until the next start trigger (INTTMmn of the master channel) is detected. The output level of TOmp becomes active one count clock after generation of INTTMmn from the master channel, and inactive when TCRmp = 0000H. Instead of using the TImn pin input, a one-shot pulse can also be output using the software operation (TSmn = 1) as a start trigger.
Caution
The timing of loading of timer data register mn (TDRmn) of the master channel is different from that of the TDRmp register of the slave channel. If the TDRmn and TDRmp registers are rewritten during operation, therefore, an illegal waveform is output. Rewrite the TDRmn register after INTTMmn is generated and the TDRmp register after INTTMmp is generated.
Remark
m: Unit number (m = 0, 1), n: Master channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p 7)
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Figure 7 - 69 Block Diagram for Operation for the One-Shot Pulse Output Function
Master channel (one-count mode)
CKm1 Operation clock
CKm0
TImn pin
TNFENmn TSmn
Noise filter
Edge detection
Slave channel (one-count mode)
CKm1 Operation clock
CKm0
Trigger selection Clock selection
Timer counter register mn (TCRmn)
Timer data register mn (TDRmn)
Interrupt controller
Interrupt signal (INTTMmn)
Timer counter register mp (TCRmp)
Output controller
TOmp pin
Clock selection
Timer data register mp (TDRmp)
Interrupt controller
Interrupt signal (INTTMmp)
Trigger selection
Remark m: Unit number (m = 0, 1), n: Master channel number (n = 0, 2, 4, 6)
p: Slave channel number (n < p 7)
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Figure 7 - 70 Example of Basic Timing during Operation for the One-Shot Pulse Output Function
TSmn
TEmn
Master channel
TImn
TCRmn
FFFFH 0000H
TDRmn
a
TOmn
INTTMmn
TSmp
TEmp
FFFFH
Slave channel
TCRmp
0000H
TDRmp
b
TOmp
INTTMmp
a+2
b
a+2
b
Remark 1. m: Unit number (m = 0, 1), n: Master channel number (n = 0, 2, 4, 6)
p: Slave channel number (n < p 7)
Remark 2. TSmn, TSmp: Bits n and p of timer channel start register m (TSm)
TEmn, TEmp: Bits n and p of timer channel enable status register m (TEm)
TImn, TImp:
Signals on the TImn and TImp input pins
TCRmn, TCRmp: Timer counter registers mn, mp (TCRmn, TCRmp)
TDRmn, TDRmp: Timer data registers mn, mp (TDRmn, TDRmp)
TOmn, TOmp: Signals on the TOmn and TOmp output pins
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Figure 7 - 71 Example of Register Settings for the Master Channel When the One-Shot Pulse Output Function is to be Used
(a) Timer mode register mn (TMRmn)
Symbol 15 14 13 12 11 10
9
8
7
6
5
TMRmn CKSmn1 CKSmn0 1/0 0
0
MASTER
CCSmn
0
mnNote
1
STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
0
0
1 1/0 1/0
0
4
3
2
1
0
0
MDmn3 MDmn2 MDmn1 MDmn0
1
0
0
0
Operation mode of channel n 100B: One-count mode
Start trigger during operation 0: Trigger input is invalid.
Selection of TImn pin input edge 00B: Detects falling edge. 01B: Detects rising edge. 10B: Detects both edges. 11B: Setting prohibited
Start trigger selection 001B: Selects the TImn pin input valid edge.
Setting of MASTERmn bit (channels 2, 4, 6) 1: Master channel.
Count clock selection
0: Selects operation clock (fMCK).
Operation clock (fMCK) selection
00B: Selects CKm0 as operation clock of channels n. 10B: Selects CKm1 as operation clock of channels n.
(b) Timer output register m (TOm)
TOm
Bit n
TOmn 0
0: Outputs 0 from TOmn.
(c) Timer output enable register m (TOEm)
Bit n
TOEm TOEmn 0
0: Stops the TOmn output operation by counting operation.
(d) Timer output level register m (TOLm)
Bit n
TOLm TOLmn 0
0: Set this bit to 0 when TOMmn = 0 (master channel output mode).
(e) Timer output mode register m (TOMm)
Bit n
TOMm TOMmn 0
0: Sets master channel output mode.
Note
TMRm2, TMRm4, TMRm6: MASTERmn = 1
TMRm0:
Fixed to 0
Remark m: Unit number (m = 0, 1), n: Master channel number (n = 0, 2, 4, 6)
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Figure 7 - 72 Example of Register Settings for the Slave Channel When the One-Shot Pulse Output Function is to be Used
(a) Timer mode register mp (TMRmp)
Symbol 15 14 13 12 11 10
9
8
7
6
5
TMRmp CKSmp1 CKSmp0 1/0 0
0
CCSmp M/SNote STSmp2 STSmp1 STSmp0 CISmp1 CISmp0
0
0
1
0
0
0
0
0
4
3
2
1
0
0
MDmp3 MDmp2 MDmp1 MDmp0
1
0
0
0
Operation mode of channel p 100B: One-count mode
Start trigger during operation 0: Trigger input is invalid.
Selection of TImp pin input edge 00B: Set to 00B because the TImp input pin is not to be used.
Start trigger selection 100B: Selects INTTMmn of master channel.
Setting of MASTERmn bit (channels 2, 4, 6) 0: Independent channel operation function.
Setting of SPLITmn bit (channels 1, 3) 0: 16-bit timer mode.
Count clock selection
0: Selects operation clock (fMCK).
Operation clock (fMCK) selection
00B: Selects CKm0 as operation clock of channel p. 10B: Selects CKm1 as operation clock of channel p. * Make the same setting as master channel.
(b) Timer output register m (TOm)
TOm
Bit p
TOmp 1/0
0: Outputs 0 from TOmp. 1: Outputs 1 from TOmp.
(c) Timer output enable register m (TOEm)
Bit p
TOEm TOEmp 1/0
0: Stops the TOmp output operation by counting operation. 1: Enables the TOmp output operation by counting operation.
(d) Timer output level register m (TOLm)
Bit p
TOLm TOLmp 1/0
0: Positive logic output (active-high) 1: Negative logic output (active-low)
(e) Timer output mode register m (TOMm)
Bit p
TOMm TOMmp 1
1: Sets the slave channel output mode.
Note Remark
TMRm2, TMRm4, TMRm6: MASTERmn bit
TMRm1, TMRm3:
SPLITmp bit
TMRm5, TMRm7:
Fixed to 0
m: Unit number (m = 0, 1), n: Master channel number (n = 0, 2, 4, 6)
p: Slave channel number (n < p 7)
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
Figure 7 - 73 Procedure for Operations When the One-Shot Pulse Output Function is to be Used (1/2)
Software Operation
Hardware State
TAU default setting
Power-off state (Clock supply is stopped and writing to each register is disabled.)
Sets the TAUmEN bit of peripheral enable registers 0 (PER0) to 1.
Power-on state. Each channel stops operating. (Clock supply is started and writing to each register is enabled.)
Sets timer clock select register m (TPSm). Determines clock frequencies of CKm0 and CKm1.
Channel default setting
Sets the corresponding bit of the noise filter enable registers 1, 2 (NFEN1, NFEN2) to 1. Sets timer mode register mn, mp (TMRmn, TMRmp) of two channels to be used (determines operation mode of channels). An output delay is set to timer data register mn (TDRmn) of the master channel, and a pulse width is set to the TDRmp register of the slave channel.
Channel stops operating. (Clock is supplied and some power is consumed.)
Sets slave channel. The TOMmp bit of timer output mode register m (TOMm) is set to 1 (slave channel output mode). Sets the TOLmp bit. Sets the TOmp bit and determines default level of the TOmp output. Sets the TOEmp bit to 1 and enables operation of TOmp.
Clears the port register and port mode register to 0.
The TOmp pin goes into Hi-Z output state.
The TOmp default setting level is output when the port mode register is in output mode and the port register is 0. TOmp does not change because channel stops operating. The TOmp pin outputs the TOmp set level.
(Note and Remark are listed on the next page.)
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
Figure 7 - 73 Procedure for Operations When the One-Shot Pulse Output Function is to be Used (2/2)
Operation is resumed.
Software Operation
Hardware State
Operation start
Sets the TOEmp bit (slave) to 1 (only when operation is resumed). The TSmn (master) and TSmp (slave) bits of timer channel start register m (TSm) are set to 1 at the same time.
The TSmn and TSmp bits automatically return to 0 because they are trigger bits.
The TEmn and TEmp bits are set to 1 and the master channel enters the start trigger detection (the valid edge of the TImn pin input is detected or the TSmn bit of the master channel is set to 1) wait state. Counter stops operating.
Count operation of the master channel is started by start trigger detection of the master channel. · Detects the TImn pin input valid edge. · Sets the TSmn bit of the master channel to 1 by
softwareNote.
Master channel starts counting.
During operation
Set values of only the CISmn1 and CISmn0 bits of the TMRmn register can be changed. Set values of the TMRmp, TDRmn, TDRmp registers, TOMmn, TOMmp, TOLmn, and TOLmp bits cannot be changed. The TCRmn and TCRmp registers can always be read. The TSRmn and TSRmp registers are not used. Set values of the TOm and TOEm registers by slave channel can be changed.
Master channel loads the value of the TDRmn register to timer counter register mn (TCRmn) by the start trigger detection (the valid edge of the TImn pin input is detected or the TSmn bit of the master channel is set to 1), and the counter starts counting down. When the count value reaches TCRmn = 0000H, the INTTMmn output is generated, and the counter stops until the next start trigger detection. The slave channel, triggered by INTTMmn of the master channel, loads the value of the TDRmp register to the TCRmp register, and the counter starts counting down. The output level of TOmp becomes active one count clock after generation of INTTMmn from the master channel. It becomes inactive when TCRmp = 0000H, and the counting operation is stopped. After that, the above operation is repeated.
Operation stop
The TTmn (master) and TTmp (slave) bits are set to 1 at the same time.
The TTmn and TTmp bits automatically return to 0 because they are trigger bits.
TEmn, TEmp = 0, and count operation stops. The TCRmn and TCRmp registers hold count value and stop. The TOmp output is not initialized and retains its current state.
The TOEmp bit of slave channel is cleared to 0 and value
is set to the TOmp bit.
The TOmp pin outputs the TOmp set level.
TAU stop
To hold the TOmp pin output level Clears the TOmp bit to 0 after the value to be held is set to the port register.
When holding the TOmp pin output level is not necessary
Setting not required.
The TOmp pin output level is held by port function.
The TAUmEN bit of the PER0 register is cleared to 0. Set the TAUmRES bit of the PRR0 register to 1 to initialize all circuits of the timer array unit.
This stops supply of the input clock to timer array unit m.
All circuits are initialized and SFR of each channel is also initialized. (The TOmp bit is cleared to 0 and the TOmp pin is set to port mode.)
Note
Do not set the TSmn bit of the slave channel to 1.
Remark m: Unit number (m = 0, 1), n: Master channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p 7)
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
7.9.2 Operation for the PWM function
Two channels can be used as a set to generate a pulse of any period and duty factor. The period and duty factor of the output pulse can be calculated by the following expressions.
Pulse period = {Set value of TDRmn (master) + 1} × Count clock period Duty factor [%] = {Set value of TDRmp (slave)}/{Set value of TDRmn (master) + 1} × 100 0% output: Set value of TDRmp (slave) = 0000H 100% output: Set value of TDRmp (slave) {Set value of TDRmn (master) + 1}
Remark The duty factor exceeds 100% if the set value of TDRmp (slave) > (set value of TDRmn (master) + 1), it summarizes to 100% output.
The master channel operates in the interval timer mode. If the channel start trigger bit (TSmn) of timer channel start register m (TSm) is set to 1, an interrupt (INTTMmn) is output, the value set to timer data register mn (TDRmn) is loaded to timer counter register mn (TCRmn), and the counter counts down in synchronization with the count clock. When the counter reaches 0000H, INTTMmn is output, the value of the TDRmn register is loaded again to the TCRmn register, and the counter counts down. This operation is repeated until the channel stop trigger bit (TTmn) of timer channel stop register m (TTm) is set to 1. If two channels are used to output a PWM waveform, the period until the master channel counts down to 0000H is the PWM output (TOmp) cycle. The slave channel operates in one-count mode. By using INTTMmn from the master channel as a start trigger, the TCRmp register loads the value of the TDRmp register and the counter counts down to 0000H. When the counter reaches 0000H, it outputs INTTMmp and waits until the next start trigger (INTTMmn from the master channel) is generated. If two channels are used to output a PWM waveform, the period until the slave channel counts down to 0000H is the PWM output (TOmp) duty. PWM output (TOmp) goes to the active level one clock after the master channel generates INTTMmn and goes to the inactive level when the TCRmp register of the slave channel becomes 0000H.
Caution
To rewrite both timer data register mn (TDRmn) of the master channel and the TDRmp register of the slave channel, a write access is necessary two times. The timing at which the values of the TDRmn and TDRmp registers are loaded to the TCRmn and TCRmp registers is upon occurrence of INTTMmn of the master channel. Thus, when rewriting is performed split before and after occurrence of INTTMmn of the master channel, the TOmp pin cannot output the expected waveform. To rewrite both the TDRmn register of the master and the TDRmp register of the slave, therefore, be sure to rewrite both the registers immediately after INTTMmn is generated from the master channel.
Remark
m: Unit number (m = 0, 1), n: Master channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p 7)
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RL78/G23 Figure 7 - 74 Block Diagram for Operation for the PWM Function
Master channel (interval timer mode)
CKm1 Operation clock
CKm0
Timer counter register mn (TCRmn)
CHAPTER 7 TIMER ARRAY UNIT (TAU)
Clock selection
Trigger selection
TSmn
Slave channel (one-count mode)
CKm1 Operation clock
CKm0
Timer data register mn (TDRmn)
Interrupt controller
Interrupt signal (INTTMmn)
Timer counter register mp (TCRmp)
Output controller
TOmp pin
Clock selection
Trigger selection
Timer data register mp (TDRmp)
Interrupt controller
Interrupt signal (INTTMmp)
Remark m: Unit number (m = 0, 1), n: Master channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p 7)
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
Figure 7 - 75 Example of Basic Timing during Operation for the PWM Function
TSmn
TEmn
Master channel
TCRmn
FFFFH 0000H
TDRmn
a
b
TOmn
INTTMmn
TSmp
TEmp
FFFFH
Slave channel
TCRmp
0000H
TDRmp
c
d
TOmp
INTTMmp
a+1 c
a+1 c
b+1 d
Remark 1. m: Unit number (m = 0, 1), n: Master channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p 7)
Remark 2. TSmn, TSmp: Bits n and p of timer channel start register m (TSm) TEmn, TEmp: Bits n and p of timer channel enable status register m (TEm) TCRmn, TCRmp: Timer counter registers mn, mp (TCRmn, TCRmp) TDRmn, TDRmp: Timer data registers mn, mp (TDRmn, TDRmp) TOmn, TOmp: Signals on the TOmn and TOmp output pins
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
Figure 7 - 76 Example of Register Settings for the Master Channel When the PWM Function is to be Used
(a) Timer mode register mn (TMRmn)
Symbol 15 14 13 12 11 10
9
8
7
6
5
TMRmn CKSmn1 CKSmn0 1/0 0
0
MASTER
CCSmn
0
mnNote
1
STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
0
0
0
0
0
0
4
3
2
1
0
0
MDmn3 MDmn2 MDmn1 MDmn0
0
0
0
1
Operation mode of channel n 000B: Interval timer
Setting of operation when counting is started
1: Generates INTTMmn when counting is started.
Selection of TImn pin input edge 00B: Set to 00B because the TImn input pin is not to be used.
Start trigger selection 000B: Selects only software start.
Setting of the MASTERmn bit (channels 2, 4, 6) 1: Master channel.
Count clock selection
0: Selects operation clock (fMCK).
Operation clock (fMCK) selection
00B: Selects CKm0 as operation clock of channel n. 10B: Selects CKm1 as operation clock of channel n.
(b) Timer output register m (TOm)
TOm
Bit n
TOmn 0
0: Outputs 0 from TOmn.
(c) Timer output enable register m (TOEm)
Bit n
TOEm TOEmn 0
0: Stops the TOmn output operation by counting operation.
(d) Timer output level register m (TOLm)
Bit n
TOLm TOLmn 0
0: Set this bit to 0 when TOMmn = 0 (master channel output mode).
(e) Timer output mode register m (TOMm)
Bit n
TOMm TOMmn 0
0: Sets master channel output mode.
Note
TMRm2, TMRm4, TMRm6: MASTERmn = 1
TMRm0:
Fixed to 0
Remark m: Unit number (m = 0, 1), n: Master channel number (n = 0, 2, 4, 6)
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
Figure 7 - 77 Example of Register Settings for the Slave Channel When the PWM Function is to be Used
(a) Timer mode register mp (TMRmp)
Symbol 15 14 13 12 11 10
9
8
7
6
5
TMRmp CKSmp1 CKSmp0 1/0 0
0
CCSmp M/SNote STSmp2 STSmp1 STSmp0 CISmp1 CISmp0
0
0
1
0
0
0
0
0
4
3
2
1
0
0
MDmp3 MDmp2 MDmp1 MDmp0
1
0
0
1
Operation mode of channel p 100B: One-count mode
Start trigger during operation 1: Trigger input is valid.
Selection of TImp pin input edge 00B: Set to 00B because the TImp input pin is not to be used.
Start trigger selection 100B: Selects INTTMmn of master channel.
Setting of MASTERmn bit (channels 2, 4, 6) 0: Slave channel
Setting of SPLITmp bit (channels 1, 3) 0: 16-bit timer mode
Count clock selection
0: Selects operation clock (fMCK).
Operation clock (fMCK) selection
00B: Selects CKm0 as operation clock of channel p. 10B: Selects CKm1 as operation clock of channel p.
* Make the same setting as master channel.
(b) Timer output register m (TOm)
TOm
Bit p
TOmp 1/0
0: Outputs 0 from TOmp. 1: Outputs 1 from TOmp.
(c) Timer output enable register m (TOEm)
Bit p
TOEm TOEmp 1/0
0: Stops the TOmp output operation by counting operation. 1: Enables the TOmp output operation by counting operation.
(d) Timer output level register m (TOLm)
Bit p
TOLm TOLmp 1/0
0: Positive logic output (active-high) 1: Negative logic output (active-low)
(e) Timer output mode register m (TOMm)
Bit p
TOMm TOMmp 1
1: Sets the slave channel output mode.
Note
TMRm2, TMRm4, TMRm6: TMRm1, TMRm3: TMRm5, TMRm7:
MASTERmn bit SPLITmp bit Fixed to 0
Remark m: Unit number (m = 0, 1), n: Master channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p 7)
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
Figure 7 - 78 Procedure for Operations When the PWM Function is to be Used (1/2)
TAU default setting
Channel default setting
Software Operation
Hardware State
Power-off state (Clock supply is stopped and writing to each register is disabled.)
Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1.
Power-on state. Each channel stops operating. (Clock supply is started and writing to each register is enabled.)
Sets timer clock select register m (TPSm). Determines clock frequencies of CKm0 and CKm1.
Sets timer mode registers mn, mp (TMRmn, TMRmp) of two channels to be used (determines operation mode of channels). An interval (period) value is set to timer data register mn (TDRmn) of the master channel, and a duty factor is set to the TDRmp register of the slave channel.
Channel stops operating. (Clock is supplied and some power is consumed.)
Sets slave channel. The TOMmp bit of timer output mode register m (TOMm) is set to 1 (slave channel output mode). Sets the TOLmp bit. Sets the TOmp bit and determines default level of the TOmp output.
Sets the TOEmp bit to 1 and enables operation of TOmp.
Clears the port register and port mode register to 0.
The TOmp pin goes into Hi-Z output state.
The TOmp default setting level is output when the port mode register is in output mode and the port register is 0. TOmp does not change because channel stops operating. The TOmp pin outputs the TOmp set level.
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
Figure 7 - 78 Procedure for Operations When the PWM Function is to be Used (2/2)
Operation is resumed.
Software Operation
Hardware State
Operation start
Sets the TOEmp bit (slave) to 1 (only when operation is resumed). The TSmn (master) and TSmp (slave) bits of timer channel start register m (TSm) are set to 1 at the same time.
The TSmn and TSmp bits automatically return to 0 because they are trigger bits.
TEmn = 1, TEmp = 1 When the master channel starts counting, INTTMmn is generated. Triggered by this interrupt, the slave channel also starts counting.
During operation
Set values of the TMRmn and TMRmp registers, TOMmn, TOMmp, TOLmn, and TOLmp bits cannot be changed. Set values of the TDRmn and TDRmp registers can be changed after INTTMmn of the master channel is generated. The TCRmn and TCRmp registers can always be read. The TSRmn and TSRmp registers are not used.
The counter of the master channel loads the TDRmn register value to timer counter register mn (TCRmn), and counts down. When the count value reaches TCRmn = 0000H, INTTMmn output is generated. At the same time, the value of the TDRmn register is loaded to the TCRmn register, and the counter starts counting down again. At the slave channel, the value of the TDRmp register is loaded to the TCRmp register, triggered by INTTMmn of the master channel, and the counter starts counting down. The output level of TOmp becomes active one count clock after generation of the INTTMmn output from the master channel. It becomes inactive when TCRmp = 0000H, and the counting operation is stopped. After that, the above operation is repeated.
Operation stop
The TTmn (master) and TTmp (slave) bits are set to 1 at the same time.
The TTmn and TTmp bits automatically return to 0 because they are trigger bits.
TEmn, TEmp = 0, and count operation stops. The TCRmn and TCRmp registers hold count value and stop. The TOmp output is not initialized and retains its current state.
The TOEmp bit of slave channel is cleared to 0 and value
is set to the TOmp bit.
The TOmp pin outputs the TOmp set level.
TAU stop
To hold the TOmp pin output level
Clears the TOmp bit to 0 after the value to be held is set
to the port register.
The TOmp pin output level is held by port function.
When holding the TOmp pin output level is not necessary
Setting not required.
The TAUmEN bit of the PER0 register is cleared to 0. Set the TAUmRES bit of the PRR0 register to 1 to initialize all circuits of the timer array unit.
This stops supply of the input clock to timer array unit m.
All circuits are initialized and SFR of each channel is also initialized. (The TOmp bit is cleared to 0 and the TOmp pin is set to port mode.)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p 7)
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
7.9.3 Operation for the multiple PWM output function
By extending the PWM function and using multiple slave channels, many PWM waveforms with different duty values can be output. For example, when using two slave channels, the period and duty factor of an output pulse can be calculated by the following expressions.
Pulse period = {Set value of TDRmn (master) + 1} × Count clock period Duty factor 1 [%] = {Set value of TDRmp (slave 1)}/{Set value of TDRmn (master) + 1} × 100 Duty factor 2 [%] = {Set value of TDRmq (slave 2)}/{Set value of TDRmn (master) + 1} × 100
Remark Although the duty factor exceeds 100% if the set value of TDRmp (slave 1) > {set value of TDRmn (master) + 1} or if the {set value of TDRmq (slave 2)} > {set value of TDRmn (master) + 1}, it is summarized into 100% output.
Timer counter register mn (TCRmn) of the master channel operates in the interval timer mode and counts the periods. The TCRmp register of the slave channel 1 operates in one-count mode, counts the duty factor, and outputs a PWM waveform from the TOmp pin. The TCRmp register loads the value of timer data register mp (TDRmp), using INTTMmn of the master channel as a start trigger, and starts counting down. When TCRmp = 0000H, TCRmp outputs INTTMmp and stops counting until the next start trigger (INTTMmn of the master channel) has been input. The output level of TOmp becomes active one count clock after generation of INTTMmn from the master channel, and inactive when TCRmp = 0000H. In the same way as the TCRmp register of the slave channel 1, the TCRmq register of the slave channel 2 operates in one-count mode, counts the duty factor, and outputs a PWM waveform from the TOmq pin. The TCRmq register loads the value of the TDRmq register, using INTTMmn of the master channel as a start trigger, and starts counting down. When TCRmq = 0000H, the TCRmq register outputs INTTMmq and stops counting until the next start trigger (INTTMmn of the master channel) has been input. The output level of TOmq becomes active one count clock after generation of INTTMmn from the master channel, and inactive when TCRmq = 0000H. When channel 0 is used as the master channel as above, up to seven types of PWM signals can be output at the same time.
Caution
To rewrite both timer data register mn (TDRmn) of the master channel and the TDRmp register of the slave channel 1, write access is necessary at least twice. Since the values of the TDRmn and TDRmp registers are loaded to the TCRmn and TCRmp registers after INTTMmn is generated from the master channel, if rewriting is performed separately before and after generation of INTTMmn from the master channel, the TOmp pin cannot output the expected waveform. To rewrite both the TDRmn register of the master and the TDRmp register of the slave, be sure to rewrite both the registers immediately after INTTMmn is generated from the master channel (This applies also to the TDRmq register of the slave channel 2).
Remark
m: Unit number (m = 0, 1), n: Master channel number (n = 0, 2, 4) p: Slave channel number, q: Slave channel number n < p < q 7 (Where p and q are integers greater than n)
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
Figure 7 - 79 Block Diagram for Operation for the Multiple PWM Output Function (for Two Types of PWM Output)
Master channel (interval timer mode)
CKm1 Operation clock
CKm0
Timer counter register mn (TCRmn)
Clock selection
Trigger selection
TSmn
Slave channel 1 (one-count mode)
CKm1 Operation clock
CKm0
Timer data register mn (TDRmn)
Interrupt controller
Interrupt signal (INTTMmn)
Timer counter register mp (TCRmp)
Output controller
TOmp pin
Clock selection
Trigger selection
Slave channel 2 (one-count mode)
CKm1 Operation clock
CKm0
Timer data register mp (TDRmp)
Interrupt controller
Interrupt signal (INTTMmp)
Timer counter register mq (TCRmq)
Output controller
TOmq pin
Clock selection
Trigger selection
Timer data register mq (TDRmq)
Remark
m: Unit number (m = 0, 1), n: Master channel number (n = 0, 2, 4) p: Slave channel number, q: Slave channel number n < p < q 7 (Where p and q are integers greater than n)
Interrupt controller
Interrupt signal (INTTMmq)
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
Figure 7 - 80 Example of Basic Timing during Operation for the Multiple PWM Output Function (for Two Types of PWM Output)
TSmn
TEmn
Master channel
TCRmn
FFFFH 0000H
TDRmn
a
b
TOmn
INTTMmn
TSmp
TEmp
Slave channel 1
TCRmp
FFFFH 0000H
TDRmp
c
TOmp
INTTMmp TSmq
a+1 c
d
a+1 c
b+1
d
d
TEmq
FFFFH
Slave channel 2
TCRmq
0000H
TDRmq
e
f
TOmq
INTTMmq
a+1 e
a+1 e
b+1
f
f
Remark 1. m: Unit number (m = 0, 1), n: Master channel number (n = 0, 2, 4)
p: Slave channel number, q: Slave channel number
n < p < q 7 (Where p and q are integers greater than n)
Remark 2. TSmn, TSmp, TSmq:
Bits n, p, and q of timer channel start register m (TSm)
TEmn, TEmp, TEmq:
Bits n, p, and q of timer channel enable status register m (TEm)
TCRmn, TCRmp, TCRmq: Timer counter registers mn, mp, mq (TCRmn, TCRmp, TCRmq)
TDRmn, TDRmp, TDRmq: Timer data registers mn, mp, mq (TDRmn, TDRmp, TDRmq)
TOmn, TOmp, TOmq: Signals on the TOmn, TOmp, and TOmq output pins
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
Figure 7 - 81 Example of Register Settings for the Master Channel When the Multiple PWM Output Function is to be Used
(a) Timer mode register mn (TMRmn)
Symbol 15 14 13 12 11 10
9
8
7
6
5
TMRmn CKSmn1 CKSmn0 1/0 0
0
MASTER
CCSmn
0
mnNote
1
STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
0
0
0
0
0
0
4
3
2
1
0
0
MDmn3 MDmn2 MDmn1 MDmn0
0
0
0
1
Operation mode of channel n 000B: Interval timer
Setting of operation when counting is started 1: Generates INTTMmn when counting is started.
Selection of TImn pin input edge 00B: Set to 00B because the TImn input pin is not to be used.
Start trigger selection 000B: Selects only software start.
Setting of MASTERmn bit (channels 2, 4, 6) 1: Master channel.
Count clock selection
0: Selects operation clock (fMCK).
Operation clock (fMCK) selection
00B: Selects CKm0 as operation clock of channel n. 10B: Selects CKm1 as operation clock of channel n.
(b) Timer output register m (TOm)
TOm
Bit n
TOmn 0
0: Outputs 0 from TOmn.
(c) Timer output enable register m (TOEm)
Bit n
TOEm TOEmn 0
0: Stops the TOmn output operation by counting operation.
(d) Timer output level register m (TOLm)
Bit n
TOLm TOLmn 0
0: Set this bit to 0 when TOMmn = 0 (master channel output mode).
(e) Timer output mode register m (TOMm)
Bit n
TOMm TOMmn 0
0: Sets master channel output mode.
Note
TMRm2, TMRm4, TMRm6: MASTERmn = 1
TMRm0:
Fixed to 0
Remark m: Unit number (m = 0, 1), n: Master channel number (n = 0, 2, 4)
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
Figure 7 - 82 Example of Register Settings for the Slave Channel When the Multiple PWM Output Function is to be Used (for Two Types of PWM Output)
(a) Timer mode registers mp and mq (TMRmp and TMRmq)
Symbol 15 14 13 12 11 10
9
8
7
6
5
TMRmp CKSmp CKSmp
1
0
1/0 0
0
CCSmp
0
M/SNote
0
STSmp 2
1
STSmp 1
0
STSmp 0
0
CISmp1 CISmp0
0
0
0
Symbol 15 14 13 12 11 10
9
8
7
6
5
TMRmq CKSmq CKSmq
1
0
1/0 0
0
CCSmq
0
M/SNote
0
STSmq 2
1
STSmq 1
0
STSmq 0
0
CISmq1 CISmq0
0
0
0
4
3
2
1
0
0
MDmp3 MDmp2 MDmp1 MDmp0
1
0
0
1
4
3
2
1
0
0
MDmq3 MDmq2 MDmq1 MDmq0
1
0
0
1
Operation mode of channels p and q 100B: One-count mode
Start trigger during operation 1: Trigger input is valid.
Selection of TImp and TImq pin input edges 00B: Set to 00B because the TImp and TImq input pins are not to be used.
Start trigger selection 100B: Selects INTTMmn of master channel.
Setting of MASTERmp and MASTERmq bits (channels 2, 4, 6) 0: Independent channel operation function.
Setting of SPLITmp and SPLITmq bits (channels 1, 3) 0: 16-bit timer mode.
Count clock selection
0: Selects operation clock (fMCK).
Selection of the operating clock (fMCK)
00B: Selects CKm0 as the operating clock for channels p and q. 10B: Selects CKm1 as the operating clock for channels p and q. * Make the same setting as that for the master channel.
(b) Timer output register m (TOm)
TOm
Bit q
TOmq 1/0
Bit p
TOmp 1/0
0: Outputs 0 from TOmp or TOmq. 1: Outputs 1 from TOmp or TOmq.
(c) Timer output enable register m (TOEm)
Bit q Bit p
TOEm TOEmq TOEmp
1/0
1/0
0: Stops the TOmp or TOmq output operation by counting operation. 1: Enables the TOmp or TOmq output operation by counting operation.
(d) Timer output level register m (TOLm)
Bit q Bit p
TOLm TOLmq TOLmp
1/0
1/0
0: Positive logic output (active-high) 1: Negative logic output (active-low)
(e) Timer output mode register m (TOMm)
Bit q Bit p
TOMm TOMmq TOMmp
1
1
1: Sets the slave channel output mode.
(Note and Remark are listed on the next page.)
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
Note
TMRm2, TMRm4, TMRm6: TMRm1, TMRm3: TMRm5, TMRm7:
MASTERmp and MASTERmq bits SPLITmp and SPLITmq bits Fixed to 0
Remark
m: Unit number (m = 0, 1), n: Master channel number (n = 0, 2, 4) p: Slave channel number, q: Slave channel number n < p < q 7 (Where p and q are integers greater than n)
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
Figure 7 - 83 Procedure for Operations When the Multiple PWM Output Function is to be Used (for Two Types of PWM Output) (1/2)
Software Operation
Hardware State
TAU default setting
Power-off state (Clock supply is stopped and writing to each register is disabled.)
Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1.
Power-on state. Each channel stops operating. (Clock supply is started and writing to each register is enabled.)
Sets timer clock select register m (TPSm). Determines clock frequencies of CKm0 and CKm1.
Channel default setting
Sets timer mode registers mn, mp, 0q (TMRmn, TMRmp, TMRmq) of each channel to be used (determines operation mode of channels). An interval (period) value is set to timer data register mn (TDRmn) of the master channel, and a duty factor is set to the TDRmp and TDRmq registers of the slave channels.
Channel stops operating. (Clock is supplied and some power is consumed.)
Sets slave channels. The TOMmp and TOMmq bits of timer output mode register m (TOMm) are set to 1 (slave channel output mode). Sets the TOLmp and TOLmq bits. Sets the TOmp and TOmq bits and determines default level of the TOmp and TOmq outputs.
Sets the TOEmp and TOEmq bits to 1 and enables operation of TOmp and TOmq.
Clears the port register and port mode register to 0.
The TOmp and TOmq pins go into Hi-Z output state.
The TOmp and TOmq default setting levels are output when the port mode register is in output mode and the port register is 0. TOmp and TOmq do not change because channels stop operating. The TOmp and TOmq pins output the TOmp and TOmq set levels.
(Remark is listed on the next page.)
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
Figure 7 - 83 Procedure for Operations When the Multiple PWM Output Function is to be Used (for Two Types of PWM Output) (2/2)
Operation is resumed.
Software Operation
Hardware State
Operation start
(Sets the TOEmp and TOEmq (slave) bits to 1 only when resuming operation.) The TSmn bit (master), and TSmp and TSmq (slave) bits of timer channel start register m (TSm) are set to 1 at the same time. The TSmn, TSmp, and TSmq bits automatically return to 0 because they are trigger bits.
TEmn = 1, TEmp, TEmq = 1 When the master channel starts counting, INTTMmn is generated. Triggered by this interrupt, the slave channel also starts counting.
During operation
Set values of the TMRmn, TMRmp, TMRmq registers, The counter of the master channel loads the TDRmn
TOMmn, TOMmp, TOMmq, TOLmn, TOLmp, and
register value to timer counter register mn (TCRmn) and
TOLmq bits cannot be changed.
counts down. When the count value reaches TCRmn =
Set values of the TDRmn, TDRmp, and TDRmq registers 0000H, INTTMmn output is generated. At the same
can be changed after INTTMmn of the master channel is time, the value of the TDRmn register is loaded to the
generated.
TCRmn register, and the counter starts counting down
The TCRmn, TCRmp, and TCRmq registers can always again.
be read.
At the slave channel 1, the values of the TDRmp register
The TSRmn, TSRmp, and TSR0q registers are not used. are transferred to the TCRmp register, triggered by
INTTMmn of the master channel, and the counter starts
counting down. The output levels of TOmp become
active one count clock after generation of the INTTMmn
output from the master channel. It becomes inactive
when TCRmp = 0000H, and the counting operation is
stopped.
At the slave channel 2, the values of the TDRmq register
are transferred to TCRmq register, triggered by
INTTMmn of the master channel, and the counter starts
counting down. The output levels of TOmq become
active one count clock after generation of the INTTMmn
output from the master channel. It becomes inactive
when TCRmq = 0000H, and the counting operation is
stopped.
After that, the above operation is repeated.
Operation stop
The TTmn bit (master), TTmp, and TTmq (slave) bits are set to 1 at the same time.
The TTmn, TTmp, and TTmq bits automatically return to 0 because they are trigger bits.
TEmn, TEmp, TEmq = 0, and count operation stops. The TCRmn, TCRmp, and TCRmq registers hold count value and stop. The TOmp and TOmq outputs are not initialized and retain their current states.
The TOEmp and TOEmq bits of slave channels are cleared to 0 and value is set to the TOmp and TOmq bits.
The TOmp and TOmq pins output the TOmp and TOmq set levels.
TAU stop
To hold the TOmp and TOmq pin output levels Clears the TOmp and TOmq bits to 0 after the value to be held is set to the port register.
When holding the TOmp and TOmq pin output levels are not necessary
Setting not required
The TOmp and TOmq pin output levels are held by port function.
The TAUmEN bit of the PER0 register is cleared to 0. Set the TAUmRES bit of the PRR0 register to 1 to initialize all circuits of the timer array unit.
This stops supply of the input clock to timer array unit m.
All circuits are initialized and SFR of each channel is also initialized. (The TOmp and TOmq bits are cleared to 0 and the TOmp and TOmq pins are set to port mode.)
Remark m: Unit number (m = 0, 1), n: Master channel number (n = 0, 2, 4)
p: Slave channel number, q: Slave channel number
n < p < q 7 (Where p and q are consecutive integers greater than n)
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CHAPTER 7 TIMER ARRAY UNIT (TAU)
7.10
Cautions When Using Timer Array Unit
7.10.1 Cautions when using timer output
Pins may be assigned multiplexed timer output and other alternate functions. The assignment depends on the product. If you intend to use a timer output, set the outputs from all other multiplexed pin functions to their initial values. For details, see 4.5 Register Settings When Using Alternate Function.
7.10.2
Point for caution when a timer output is to be used as an event input for the ELCL
The timer outputs (TO00 to TO07) of channels 0 to 7 of timer array unit 0 can be used as event inputs for the logic and event link controller (ELCL). When the timer output signal is to be used for event input to the ELCL but not for output to the TO0m pin, set the corresponding bit in port function output enable register 0 (PFOE0) to 0. For details, see 4.3.15 Port function output enable registers (PFOEx).
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CHAPTER 8 REALTIME CLOCK (RTC)
CHAPTER 8 REALTIME CLOCK (RTC)
8.1
Functions of Realtime Clock
The realtime clock has the following features. · Capable of counting years, months, days of the week, dates, hours, minutes, and seconds, for up to 99 years · Fixed-cycle interrupt (with period selectable from among 0.5 of a second, 1 second, 1 minute, 1 hour, 1 day, or 1
month) · Alarm interrupt (alarm set by day of week, hour, and minute) · Pin output function of 1 Hz
The realtime clock interrupt signal (INTRTC) can be used to wake up the MCU from the STOP mode, or to trigger transitions of the A/D converter to the SNOOZE mode.
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CHAPTER 8 REALTIME CLOCK (RTC)
8.2
Configuration of the Realtime Clock
The realtime clock includes the following hardware blocks.
Table 8 - 1 Configuration of the Realtime Clock
Item
Configuration
Counter
Internal counter (16 bits)
Control registers
Peripheral enable register 0 (PER0)
Subsystem clock supply mode control register (OSMC)
Realtime clock control register 0 (RTCC0)
Realtime clock control register 1 (RTCC1)
Second count register (SEC)
Minute count register (MIN)
Hour count register (HOUR)
Day count register (DAY)
Day-of-week count register (WEEK)
Month count register (MONTH)
Year count register (YEAR)
Time error correction register (SUBCUD)
Alarm minute register (ALARMWM)
Alarm hour register (ALARMWH)
Alarm day-of-week register (ALARMWW)
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CHAPTER 8 REALTIME CLOCK (RTC)
Figure 8 - 1 Block Diagram of the Realtime Clock
Realtime clock control register 1 WALE WALIE WAFG RIFG RWST RWAIT
Realtime clock control register 0
RTCE
RCLOE1
RTC128 EN
AMPM
CT2
CT1
CT0
WUTMM Subsystem clock supply mode CK0 control register (OSMC)
RTC1HZ
Alarm day-ofweek register (ALARMWW)
(7-bit)
Matched
Alarm hour register
(ALARMWH) (6-bit)
Alarm minute register
(ALARMWM) (7-bit)
INTRTC CT0 to CT2
Selector
RIFG
1 year
Year count register (YEAR) (8-bit)
1 month
Month count register (MONTH) (5-bit)
Day-of-week count register
(WEEK) (3-bit)
Buffer
Buffer
Buffer
AMPM
1 day
Day count register (DAY) (6-bit)
1 hour
1 minute
Hour count register (HOUR) (6-bit)
Minute count register (MIN) (7-bit)
Buffer
Buffer
Buffer
RWST RWAIT
1 second
Second count register (SEC) (7-bit)
Wait control
Buffer
Internal counter (8-bit)
Internal counter (8-bit)
Count enable/ disable circuit
Time error correction
register
(SUBCUD)
RTCE
(8-bit)
RTC128EN
Selector Selector Selector
fRTCCK
fRTCCLK
fSXR
Division
fIL
fRTC128HZ
WUTMMCK0 RTC128EN
Internal bus
Caution
The count of years, months, weeks, days, hours, minutes, and seconds can only proceed when a subsystem clock (fSXR = 32.768 kHz) is selected as the operating clock of the realtime clock. When the low-speed on-chip oscillator clock (fIL = 32.768 kHz) is selected, only the fixed-cycle interrupt is available.
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CHAPTER 8 REALTIME CLOCK (RTC)
8.3
Registers to Control the Realtime Clock
The following registers are used to control the realtime clock.
· Peripheral enable register 0 (PER0) · Subsystem clock supply mode control register (OSMC) · Realtime clock control register 0 (RTCC0) · Realtime clock control register 1 (RTCC1) · Second count register (SEC) · Minute count register (MIN) · Hour count register (HOUR) · Day count register (DAY) · Day-of-week count register (WEEK) · Month count register (MONTH) · Year count register (YEAR) · Time error correction register (SUBCUD) · Alarm minute register (ALARMWM) · Alarm hour register (ALARMWH) · Alarm day-of-week register (ALARMWW) · Port mode register 3 (PM3) · Port register 3 (P3)
The following shows the register states depending on reset sources.
Reset Source
System-related registersNote 1
Calendar-related registersNote 2
POR
Reset
Not reset
External reset
Retained
Retained
WDT
Retained
Retained
TRAP
Retained
Retained
LVD
Retained
Retained
Other internal reset sources
Retained
Retained
Note 1. Note 2.
RTCC0, RTCC1, and SUBCUD SEC, MIN, HOUR, DAY, WEEK, MONTH, YEAR, ALARMWM, ALARMWH, and ALARMWW
Assertion of the reset signal does not reset the SEC, MIN, HOUR, DAY, WEEK, MONTH, YEAR, ALARMWM, ALARMWH, or ALARMWW register. Initialize all the registers after power on.
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CHAPTER 8 REALTIME CLOCK (RTC)
8.3.1 Peripheral enable register 0 (PER0)
This register is used to enable or disable the supply of a clock signal to various on-chip peripheral modules. Clock supply to an on-chip peripheral module that is not to be used can be stopped to decrease power consumption and noise. When the realtime clock is used, be sure to set bit 7 (RTCWEN) of this register to 1. The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 8 - 2 Format of Peripheral Enable Register 0 (PER0)
Address: After reset: R/W:
F00F0H 00H R/W
Symbol
<7>
PER0 RTCWEN
<6>
IICA1EN
Note 1
<5> ADCEN
<4> IICA0EN
<3> SAU1EN
<2> SAU0EN
<1>
TAU1EN
Note 2
<0> TAU0EN
RTCWEN
Control of access to the realtime clock (RTC)
0
· SFR used by the realtime clock (RTC) cannot be written.
· Operation of the realtime clock (RTC) can be enabled.
1
· SFR used by the realtime clock (RTC) can be read and written.
· Operation of the realtime clock (RTC) can be enabled.
Note 1. Note 2.
This bit is only present in the 44- to 128-pin products. This bit is only present in the 80-, 100-, and 128-pin products.
Caution 1. When the realtime clock is to be used, start by setting the RTCWEN bit to 1 and then set the following registers once oscillation of the counter clock (fRTCCK) has become stable. If RTCWEN is 0, attempted writing to the control registers of the realtime clock is ignored, and 00H is read (except for the subsystem clock supply mode control register (OSMC), port mode register 3 (PM3), and port register 3 (P3)). · Realtime clock control register 0 (RTCC0) · Realtime clock control register 1 (RTCC1) · Second count register (SEC) · Minute count register (MIN) · Hour count register (HOUR) · Day count register (DAY) · Day-of-week count register (WEEK) · Month count register (MONTH) · Year count register (YEAR) · Time error correction register (SUBCUD) · Alarm minute register (ALARMWM) · Alarm hour register (ALARMWH) · Alarm day-of-week register (ALARMWW)
Caution 2. The subsystem clock supply to peripheral functions other than the realtime clock can be stopped in STOP mode or HALT mode when the subsystem clock is in use, by setting the RTCLPC bit of the subsystem clock supply mode control register (OSMC) to 1.
Caution 3. Be sure to clear the following bits to 0. Bits 6 and 1 in the 30-, 32-, 36-, 40-, 44-, 48-, 52-, and 64-pin products
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CHAPTER 8 REALTIME CLOCK (RTC)
8.3.2 Subsystem clock supply mode control register (OSMC)
The WUTMMCK0 bit can be used to select the control clock (fRTCCK) for the realtime clock. The RTCLPC bit of this register can be used to reduce the power consumption by disabling supply of the clock signal to peripheral functions that are not in use. For details about setting the RTCLPC bit, see CHAPTER 6 CLOCK GENERATOR. The OSMC register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 8 - 3 Format of Subsystem Clock Supply Mode Control Register (OSMC)
Address: After reset: R/W:
F00F3H Undefined R/W
Symbol
<7>
6
5
<4>
3
2
1
<0>
OSMC RTCLPC
0
0
WUTMMCK0
×
×
0
HIPREC
WUTMMCK0
Selection of the operating clock (fRTCCK) for the control block of the realtime clock
0
Subsystem clock XR (fSXR) or fRTC128HZ
(fRTC128HZ is selected when the setting of the RTC128EN bit is 1.)
1
Low-speed on-chip oscillator clock (fIL)Notes 1, 2
Note 1. Note 2.
Setting the WUTMMCK0 bit to 1 is prohibited when the subsystem clock X is selected as the operating clock for the control block of the realtime clock. Switching between the subsystem clock and the low-speed on-chip oscillator clock by using the WUTMMCK0 bit is only possible while operations of the realtime clock, 32-bit interval timer interfaces UARTA0 and UARTA1, remote control signal receiver, and clock output/buzzer output controller are all stopped.
Caution
Counting of years, months, weeks, days, hours, minutes, and seconds can only proceed when the subsystem clock XR (fSXR = 32.768 kHz) or fRTC128HZ is selected as the operating clock for the control block of the realtime clock. When the low-speed on-chip oscillator clock (fIL = 32.768 kHz) is selected, only the fixed-cycle interrupt is available.
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CHAPTER 8 REALTIME CLOCK (RTC)
8.3.3 Realtime clock control register 0 (RTCC0)
The RTCC0 is an 8-bit register that is used to start or stop the realtime clock operation, control the RTC1HZ pin, and set a 12- or 24-hour system and the fixed-cycle interrupt. The RTCC0 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following an internal reset by the power-on reset circuit.
Figure 8 - 4 Format of Realtime Clock Control Register 0 (RTCC0)
Address: After reset: R/W:
F022BH 00H R/W
Symbol RTCC0
<7> RTCE
6
<5>
<4>
3
2
1
0
0
RCLOE1 RTC128EN AMPM
CT2
CT1
CT0
RTCENote
0
Stops counter operation.
1
Starts counter operation.
Realtime clock operation control
RCLOE1
RTC1HZ pin output control
0
Disables output of the RTC1HZ pin (1 Hz).
1
Enables output of the RTC1HZ pin (1 Hz).
RTC128EN
Selection of the operating clock for the realtime clock (fRTCCLK)
0
32.768 kHz
1
128 Hz
· Setting this bit to 1 enables the realtime clock to operate with the 128-Hz clock for lower-power operation. · Time error correction cannot be used when the setting of this bit is 1. · The WUTMMCK bit in the OSMC register should be set to 0 when setting this bit to 1.
AMPM
Selection of 12-/24-hour system
0
12-hour system (a.m. and p.m. are displayed.)
1
24-hour system
· Rewrite the AMPM bit value after setting the RWAIT bit (bit 0 of the realtime clock control register 1
(RTCC1)) to 1. If the AMPM bit value is changed, the values of the hour count register (HOUR) change
according to the specified time system. · Table 8 - 2 shows the time (hour) digits indicated according to the setting of this bit.
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CHAPTER 8 REALTIME CLOCK (RTC)
CT2
CT1
CT0
Fixed-cycle interrupt (INTRTC) selection
0
0
0
Does not use fixed-cycle interrupt.
0
0
1
Once per 0.5 s (synchronized with second count up)
0
1
0
Once per 1 s (same time as second count up)
0
1
1
Once per 1 m (second 00 of every minute)
1
0
0
Once per 1 hour (minute 00 and second 00 of every hour)
1
0
1
Once per 1 day (hour 00, minute 00, and second 00 of every day)
1
1
×
Once per 1 month (Day 1, hour 00 a.m., minute 00, and second 00
of every month)
To change the values of the CT2 to CT0 bits while counting is in progress (RTCE = 1), rewrite the values of
the CT2 to CT0 bits after disabling interrupt processing of INTRTC by using the interrupt mask flag register.
Furthermore, after rewriting the values of the CT2 to CT0 bits, enable interrupt processing after clearing the
RIFG and RTCIF flags.
Note
To shift to the STOP mode immediately after setting the RTCE bit to 1, follow the procedure in Figure 8 - 20 Procedure for Shifting to HALT or STOP Mode after Setting RTCE Bit to 1.
Caution 1. Do not change the value of the RCLOE1 bit when RTCE is 1. Caution 2. 1 Hz is not output even if RCLOE1 is set to 1 when RTCE is 0. Caution 3. Be sure to set bit 6 to 0.
Remark ×: don't care
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CHAPTER 8 REALTIME CLOCK (RTC)
8.3.4 Realtime clock control register 1 (RTCC1)
The RTCC1 is an 8-bit register that is used to control the alarm interrupt and the wait time of the counter. The RTCC1 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following an internal reset by the power-on reset circuit.
Figure 8 - 5 Format of Realtime Clock Control Register 1 (RTCC1) (1/2)
Address: After reset: R/W:
F022CH 00H R/W
Symbol
<7>
<6>
5
<4>
<3>
RTCC1 WALE
WALIE
0
WAFG
RIFG
2
<1>
<0>
0
RWST
RWAIT
WALE
Alarm operation control
0
Match operation is invalid.
1
Match operation is valid.
When setting a value to the WALE bit while counting is in progress (RTCE = 1) and WALIE is 1, rewrite the
WALE bit after disabling interrupt processing of INTRTC by using the interrupt mask flag register.
Furthermore, clear the WAFG and RTCIF flags after rewriting the WALE bit. When setting any of the alarm-
related registers (WALIE flag of realtime clock control register 1 (RTCC1), the alarm minute register
(ALARMWM), the alarm hour register (ALARMWH), and the alarm day-of-week register (ALARMWW)), set
the WALE bit to 0 to disable matching.
WALIE 0 1
Control of alarm interrupt (INTRTC) Does not generate interrupt on matching of alarm. Generates interrupt on matching of alarm.
WAFG
Alarm detection status flag
0
Alarm mismatch
1
Detection of matching of alarm
This is a status flag that indicates detection of matching with the alarm. It is only valid when WALE is 1 and
is set to 1 one cycle of fRTCCK after matching of the alarm is detected. This flag is cleared when 0 is written to it. Writing 1 to it is invalid.
RIFG
Fixed-cycle interrupt status flag
0
Fixed-cycle interrupt is not generated.
1
Fixed-cycle interrupt is generated.
This flag indicates the status of generation of the fixed-cycle interrupt. When the fixed-cycle interrupt is
generated, it is set to 1. This flag is cleared when 0 is written to it. Writing 1 to it is invalid.
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CHAPTER 8 REALTIME CLOCK (RTC)
Figure 8 - 5 Format of Realtime Clock Control Register 1 (RTCC1) (2/2)
RWST
Wait status flag of realtime clockNote 3
0
Counting is in progress.
1
Counter values are readable and writable.
This status flag indicates whether the setting of the RWAIT bit is valid.
Before reading or writing the counter value, confirm that the value of this flag is 1.
RWAIT
Wait control of realtime clock
0
Counting proceeds.
1
Stops the SEC to YEAR counters. Counter values are readable and writable.
This bit controls the operation of the counter. Be sure to write 1 to this bit to read or write the counter value. So that the 16-bit internal counter continues to run, return the value of this bit to 0 on completion of reading or writing within one second. After setting this bit to 1, it takes up to one cycle of fRTTCK until the counter value can be actually read or written (RWST = 1).Notes 1, 2 When the internal counter (16 bits) overflows while the setting of this bit is 1, an indicator of the counter having overflowed is retained after RWAIT has become 0, after which counting up continues. Note that, when the second count register has been written to, the overflow is not retained.
Note 1. Note 2.
Note 3.
When the RWAIT bit is set to 1 within one cycle of fRTCCK clock after setting the RTCE bit to 1, the setting of the RWST bit actually becoming 1 may take up to two cycles of the operating clock (fRTCCK). When the RWAIT bit is set to 1 within one cycle of fRTCCK clock after release from the standby mode (HALT mode, STOP mode, or SNOOZE mode), the setting of the RWST bit actually becoming 1 may take up to two cycles of the operating clock (fRTCCK). Bit 1 is read-only.
Caution
Note that using a bit manipulation instruction for writing to the RTCC1 register may lead to clearing of the RIFG and WAFG flags. Therefore, when writing to the RTCC1 register, be sure to use an 8-bit manipulation instruction. To prevent the RIFG and WAFG flags from being cleared during writing, disable writing by setting 1 to the corresponding bit. However, if the RIFG and WAFG flags are not in use and a change to the value does not matter, using a bit manipulation instruction for writing to the RTCC1 register does not create a problem.
Remark 1. Fixed-cycle interrupts and alarm match interrupts use the same interrupt source (INTRTC). When using these two types of interrupts at the same time, which interrupt occurred can be judged by checking the fixed-cycle interrupt status flag (RIFG) and the alarm detection status flag (WAFG) upon INTRTC occurrence.
Remark 2. The internal counter (16 bits) is cleared when the second count register (SEC) is written.
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CHAPTER 8 REALTIME CLOCK (RTC)
8.3.5 Second count register (SEC)
The SEC is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of seconds. This counter is incremented each time the internal counter (16-bit) overflows. When data is written to this register, it is written to a buffer and then to the counter up to two cycles of fRTCCK later. Set a decimal value of 00 to 59 to this register in BCD code. The SEC register can be set by an 8-bit memory manipulation instruction. This register is not initialized by a reset signal.
Figure 8 - 6 Format of Second Count Register (SEC)
Address: After reset: R/W:
F0220H Undefined R/W
Symbol
7
SEC
0
Caution
6 SEC40
5 SEC20
4 SEC10
3 SEC8
2 SEC4
1 SEC2
0 SEC1
When reading from or writing to this register while the counter is in operation (RTCE = 1), follow the procedures described in 8.4.3 Reading from and writing to the counters of the realtime clock.
Remark The internal counter (16 bits) is cleared when the second count register (SEC) is written.
8.3.6 Minute count register (MIN)
The MIN is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of minutes. This counter is incremented each time the second counter overflows. When data is written to this register, it is written to a buffer and then to the counter up to two cycles of fRTCCK later. Even if the second count register overflows while this register is being written, this register ignores the overflow and is set to the value written. Set a decimal value of 00 to 59 to this register in BCD code. The MIN register can be set by an 8-bit memory manipulation instruction. This register is not initialized by a reset signal.
Figure 8 - 7 Format of Minute Count Register (MIN)
Address: After reset: R/W:
F0221H Undefined R/W
Symbol
7
MIN
0
Caution
6 MIN40
5 MIN20
4 MIN10
3 MIN8
2 MIN4
1 MIN2
0 MIN1
When reading from or writing to this register while the counter is in operation (RTCE = 1), follow the procedures described in 8.4.3 Reading from and writing to the counters of the realtime clock.
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CHAPTER 8 REALTIME CLOCK (RTC)
8.3.7 Hour count register (HOUR)
The HOUR is an 8-bit register that takes a value of 00 to 23 or 01 to 12 and 21 to 32 (decimal) and indicates the count value of hours. This counter is incremented each time the minute counter overflows. When data is written to this register, it is written to a buffer and then to the counter up to two cycles of fRTCCK later. Even if the minute count register overflows while this register is being written, this register ignores the overflow and is set to the value written. Specify a decimal value of 00 to 23, 01 to 12, or 21 to 32 by using BCD code according to the time system specified using bit 3 (AMPM) of the realtime clock control register 0 (RTCC0). If the AMPM bit value is changed, the values of the HOUR register change according to the specified time system. The HOUR register can be set by an 8-bit memory manipulation instruction. This register is not initialized by a reset signal.
Figure 8 - 8 Format of Hour Count Register (HOUR)
Address: After reset: R/W:
F0222H Undefined R/W
Symbol
7
HOUR
0
6
5
4
3
2
1
0
0
HOUR20 HOUR10 HOUR8 HOUR4 HOUR2 HOUR1
Caution 1. Bit 5 (HOUR20) of the HOUR register indicates AM(0)/PM(1) if AMPM = 0 (if the 12-hour system is selected).
Caution 2. When reading from or writing to this register while the counter is in operation (RTCE = 1), follow the procedures described in 8.4.3 Reading from and writing to the counters of the realtime clock.
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CHAPTER 8 REALTIME CLOCK (RTC)
Table 8 - 2 shows the relationship between the setting value of the AMPM bit, the hour count register (HOUR) value, and time.
Table 8 - 2 Displayed Time Digits
24-Hour Display (AMPM = 1)
Time
HOUR Register
0
00H
1
01H
2
02H
3
03H
4
04H
5
05H
6
06H
7
07H
8
08H
9
09H
10
10H
11
11H
12
12H
13
13H
14
14H
15
15H
16
16H
17
17H
18
18H
19
19H
20
20H
21
21H
22
22H
23
23H
12 a.m. 1 a.m. 2 a.m. 3 a.m. 4 a.m. 5 a.m. 6 a.m. 7 a.m. 8 a.m. 9 a.m. 10 a.m. 11 a.m. 12 p.m. 1 p.m. 2 p.m. 3 p.m. 4 p.m. 5 p.m. 6 p.m. 7 p.m. 8 p.m. 9 p.m. 10 p.m. 11 p.m.
12-Hour Display (AMPM = 0)
Time
HOUR Register
12H
01H
02H
03H
04H
05H
06H
07H
08H
09H
10H
11H
32H
21H
22H
23H
24H
25H
26H
27H
28H
29H
30H
31H
The HOUR register value is set to 12-hour display when the AMPM bit is 0 and to 24-hour display when the AMPM bit is 1. In 12-hour display, the fifth bit of the HOUR register displays 0 for AM and 1 for PM.
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CHAPTER 8 REALTIME CLOCK (RTC)
8.3.8 Day count register (DAY)
The DAY is an 8-bit register that takes a value of 1 to 31 (decimal) and indicates the count value of days. This counter is incremented each time the hour counter overflows. Counting by the date counter proceeds as shown below.
· 01 to 31 (January, March, May, July, August, October, December) · 01 to 30 (April, June, September, November) · 01 to 29 (February, leap year) · 01 to 28 (February, normal year)
When data is written to this register, it is written to a buffer and then to the counter up to two cycles of fRTCCK later. Even if the hour count register overflows while this register is being written, this register ignores the overflow and is set to the value written. Set a decimal value of 01 to 31 to this register in BCD code. The DAY register can be set by an 8-bit memory manipulation instruction. This register is not initialized by a reset signal.
Figure 8 - 9 Format of Day Count Register (DAY)
Address: After reset: R/W:
F0224H Undefined R/W
Symbol
7
DAY
0
Caution
6
5
4
3
2
1
0
0
DAY20
DAY10
DAY8
DAY4
DAY2
DAY1
When reading from or writing to this register while the counter is in operation (RTCE = 1), follow the procedures described in 8.4.3 Reading from and writing to the counters of the realtime clock.
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8.3.9 Day-of-week count register (WEEK)
The WEEK is an 8-bit register that takes a value of 0 to 6 (decimal) and indicates the count value of days of the week. This counter is incremented in synchronization with the date counter. When data is written to this register, it is written to a buffer and then to the counter up to two cycles of fRTCCK later. Set a decimal value of 00 to 06 to this register in BCD code. The WEEK register can be set by an 8-bit memory manipulation instruction. This register is not initialized by a reset signal.
Figure 8 - 10 Format of Day-of-Week Count Register (WEEK)
Address: After reset: R/W:
F0223H Undefined R/W
Symbol
7
6
5
4
3
2
1
0
WEEK
0
0
0
0
0
WEEK4 WEEK2 WEEK1
Caution 1. The value corresponding to the month count register (MONTH) or the day count register (DAY) is not stored in the day-of-week count register (WEEK) automatically. After reset release, set the day-of-week count register as follow.
Day
WEEK
Sunday
00H
Monday
01H
Tuesday
02H
Wednesday
03H
Thursday
04H
Friday
05H
Saturday
06H
Caution 2. When reading from or writing to this register while the counter is in operation (RTCE = 1), follow the procedures described in 8.4.3 Reading from and writing to the counters of the realtime clock.
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CHAPTER 8 REALTIME CLOCK (RTC)
8.3.10 Month count register (MONTH)
The MONTH is an 8-bit register that takes a value of 1 to 12 (decimal) and indicates the count value of months. This counter is incremented each time the day counter overflows. When data is written to this register, it is written to a buffer and then to the counter up to two cycles of fRTCCK later. Even if the day count register overflows while this register is being written, this register ignores the overflow and is set to the value written. Set a decimal value of 01 to 12 to this register in BCD code. The MONTH register can be set by an 8-bit memory manipulation instruction. This register is not initialized by a reset signal.
Figure 8 - 11 Format of Month Count Register (MONTH)
Address: After reset: R/W:
F0225H Undefined R/W
Symbol
7
MONTH
0
Caution
6
5
4
3
2
1
0
0
0
MONTH10 MONTH8 MONTH4 MONTH2 MONTH1
When reading from or writing to this register while the counter is in operation (RTCE = 1), follow the procedures described in 8.4.3 Reading from and writing to the counters of the realtime clock.
8.3.11 Year count register (YEAR)
The YEAR is an 8-bit register that takes a value of 0 to 99 (decimal) and indicates the value of the counter of years. This counter is incremented each time the month count register (MONTH) overflows. Values 00, 04, 08, ..., 92, and 96 indicate a leap year. When data is written to this register, it is written to a buffer and then to the counter up to two cycles of fRTCCK later. Even if the MONTH register overflows while this register is being written, this register ignores the overflow and is set to the value written. Set a decimal value of 00 to 99 to this register in BCD code. The YEAR register can be set by an 8-bit memory manipulation instruction. This register is not initialized by a reset signal.
Figure 8 - 12 Format of Year Count Register (YEAR)
Address: After reset: R/W:
F0226H Undefined R/W
Symbol
7
YEAR YEAR80
6 YEAR40
5 YEAR20
4 YEAR10
3 YEAR8
2 YEAR4
1 YEAR2
0 YEAR1
Caution When reading from or writing to this register while the counter is in operation (RTCE = 1), follow the procedures described in 8.4.3 Reading from and writing to the counters of the realtime clock.
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CHAPTER 8 REALTIME CLOCK (RTC)
8.3.12 Time error correction register (SUBCUD)
This register is used to correct the time with high accuracy when it is running slow or fast by adjusting the value that is considered an overflow from the internal counter (16 bits) to the second count register (SEC) (reference value: 7FFFH). The SUBCUD register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following an internal reset by the power-on reset circuit.
Figure 8 - 13 Format of Time Error Correction Register (SUBCUD)
Address: After reset: R/W:
F0227H 00H R/W
Symbol
7
6
5
4
3
2
1
0
SUBCUD DEV
F6
F5
F4
F3
F2
F1
F0
DEV
Setting of time error correction timing
0
Corrects time error when the second digits are at 00, 20, or 40 (every 20 seconds).
1
Corrects time error only when the second digits are at 00 (every 60 seconds).
Writing to the SUBCUD register at the following timing is prohibited.
· When DEV = 0 is set: For a period of SEC = 00H, 20H, 40H
· When DEV = 1 is set: For a period of SEC = 00H
F6
Setting of time error correction value
0
Increases by {(F5, F4, F3, F2, F1, F0) 1} × 2.
1
Decreases by {(/F5, /F4, /F3, /F2, /F1, /F0) + 1} × 2.
When (F6, F5, F4, F3, F2, F1, F0) = (*, 0, 0, 0, 0, 0, *), the time error is not corrected. * is 0 or 1.
/F5 to /F0 are the inverted values of the corresponding bits (000011 when 111100). Range of correction value: (when F6 = 0) 2, 4, 6, 8, ... , 120, 122, 124
(when F6 = 1) 2, 4, 6, 8, ... , 120, 122, 124
The range of value that can be corrected by using the time error correction register (SUBCUD) is shown below.
DEV = 0 (correction every 20 seconds) DEV = 1 (correction every 60 seconds)
Correctable range
189.2 ppm to 189.2 ppm
63.1 ppm to 63.1 ppm
Maximum excludes quantization error
±1.53 ppm
±0.51 ppm
Minimum resolution ±3.05 ppm
±1.02 ppm
Caution Time error correction cannot be used in the 128-Hz operating mode (RTC128EN = 1); it can only proceed if the setting of RTC128EN is 0.
Remark If a correctable range is 63.1 ppm or lower and 63.1 ppm or higher, set DEV to 0.
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CHAPTER 8 REALTIME CLOCK (RTC)
8.3.13 Alarm minute register (ALARMWM)
This register is used to set minutes of alarm. The ALARMWM register can be set by an 8-bit memory manipulation instruction. This register is not initialized by a reset signal.
Caution
Set a decimal value of 00 to 59 to this register in BCD code. If a value outside the range is set, the alarm is not detected.
Figure 8 - 14 Format of Alarm Minute Register (ALARMWM)
Address: After reset: R/W:
F0228H Undefined R/W
Symbol
7
ALARMWM
0
6 WM40
5 WM20
4 WM10
3 WM8
2 WM4
1 WM2
0 WM1
8.3.14 Alarm hour register (ALARMWH)
This register is used to set hours of alarm. The ALARMWH register can be set by an 8-bit memory manipulation instruction. This register is not initialized by a reset signal.
Caution
Set a decimal value of 00 to 23, 01 to 12, or 21 to 32 to this register in BCD code. If a value outside the range is set, the alarm is not detected.
Figure 8 - 15 Format of Alarm Hour Register (ALARMWH)
Address: After reset: R/W:
F0229H Undefined R/W
Symbol
7
ALARMWH
0
Caution
6
5
4
3
2
1
0
0
WH20
WH10
WH8
WH4
WH2
WH1
Bit 5 (WH20) of the ALARMWH register indicates AM(0)/PM(1) if AMPM = 0 (if the 12-hour system is selected).
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CHAPTER 8 REALTIME CLOCK (RTC)
8.3.15 Alarm day-of-week register (ALARMWW)
This register is used to set days of the week of alarm. The ALARMWW register can be set by an 8-bit memory manipulation instruction. This register is not initialized by a reset signal.
Figure 8 - 16 Format of Alarm Day-of-Week Register (ALARMWW)
Address: After reset: R/W:
F022AH Undefined R/W
Symbol
7
ALARMWW
0
6 WW6
5 WW5
4 WW4
3 WW3
2 WW2
1 WW1
0 WW0
Here is an example of setting the alarm.
Time of Alarm
Day of week
12-Hour Display
24-Hour Display
Sunday
W W 0
Monday
W W 1
Tuesday Wednesday Thursday
WW W
WW W
2
3
4
Friday
W W 5
Saturday
W W 6
Hour 10
Hour Minute Minute Hour 1 10 1 10
Hour Minute Minute 1 10 1
Every day, 0:00 a.m.
1
1
1
1
1
1
1
1
2
0
0
0
0
0
0
Every day, 1:30 a.m.
1
1
1
1
1
1
1
0
1
3
0
0
1
3
0
Every day, 11:59 a.m.
1
1
1
1
1
1
1
1
1
5
9
1
1
5
9
Monday through Friday, 0:00 p.m. 0
1
1
1
1
1
0
3
2
0
0
1
2
0
0
Sunday, 1:30 p.m.
1
0
0
0
0
0
0
2
1
3
0
1
3
3
0
Monday, Wednesday, Friday, 11:59 p.m.
0
1
0
1
0
1
0
3
1
5
9
2
3
5
9
8.3.16 Port mode register 3 (PM3)
The PM3 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is FFH following a reset. When using the port 3 as the RTC1HZ pin for output of 1 Hz, set the PM30 bit to 0.
Figure 8 - 17 Format of Port Mode Register 3 (PM3)
Address: After reset: R/W:
FFF23H FFH R/W
Symbol PM3
7 PM37
6 PM36
5 PM35
4 PM34
3 PM33
2 PM32
1 PM31
0 PM30
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8.3.17 Port register 3 (P3)
The P3 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset. When using the port 3 as 1-Hz output to the RTC1Hz pin, set the P30 bit to 0.
Figure 8 - 18 Format of Port Register 3 (P3)
Address: After reset: R/W:
FFF03H 00H R/W
Symbol
7
6
5
4
3
2
1
0
P3 P37
P36
P35
P34
P33
P32
P31
P30
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CHAPTER 8 REALTIME CLOCK (RTC)
8.4
Operations of the Realtime Clock
8.4.1 Starting the Realtime Clock Operation
Figure 8 - 19 Procedure for Starting the Realtime Clock Operation
<R>
Start RTCWEN = 1Note 1
RTCE = 0 Setting WUTMMCK0 Setting RTC128ENNote 1 Setting AMPM, CT2 to CT0
Supplies input clock. Stops counter operation. Sets fRTCCK. Sets fRTCCLK. Selects 12-/24-hour system and interrupt (INTRTC).
Setting SEC
Sets second count register.
Setting MIN
Sets minute count register.
Setting HOUR
Sets hour count register.
Setting WEEK
Sets day-of-week count register.
Setting DAY
Sets day count register.
Setting MONTH
Sets month count register.
Setting YEAR
Sets year count register.
Setting SUBCUDNote 2
Sets time error correction register.
Clearing IF flags of interrupt
Clears interrupt request flags (RTCIF).
Clearing MK flags of interrupt RTCE = 1Note 3
Clears interrupt mask flags (RTCMK). Starts counter operation.
No INTRTC = 1? Yes End
Note 1. Note 2.
Note 3.
First set the RTCWEN bit to 1 and set the RTC128EN bit as desired, while oscillation of the count clock (fRTCCK) is stable. Set up the SUBCUD register only if the time error must be corrected. For details about how to calculate the correction value, see 8.4.6 Example of time error correction by the realtime clock. Time error correction cannot be used while the setting of the RTC128EN bit is 1. Confirm the procedure described in 8.4.2 Shifting to HALT or STOP mode after starting operation when shifting to HALT or STOP mode without waiting for INTRTC = 1 after RTCE = 1.
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CHAPTER 8 REALTIME CLOCK (RTC)
8.4.2 Shifting to HALT or STOP mode after starting operation
Take either of the steps listed below when shifting to HALT or STOP mode immediately after setting the RTCE bit to 1. Note that any of these steps is not required when shifting to the HALT or STOP mode after the INTRTC interrupt has occurred.
· Make a transition to HAL or STOP mode when at least two counter clock cycles (fRTCCK) have elapsed after setting the RTCE bit to 1 (see Figure 8 - 20, Example 1).
· After setting the RTCE bit to 1 and then setting the RWAIT bit to 1, poll the RWST bit to check if it has become 1 yet. After setting the RWAIT bit to 0 and polling the RWST bit to check if it has become 0 yet, a transition to HALT/STOP mode will proceed (see Figure 8 - 20, Example 2).
Figure 8 - 20 Procedure for Shifting to HALT or STOP Mode after Setting RTCE Bit to 1
Example 1
Example 2
RTCE = 1
Sets to counter operation start
Waiting for at least for 2 cycles of fRTCCK
HALT or STOP instruction execution
The MCU is placed in HALT or STOP mode.
No
RTCE = 1 RWAIT = 1
RWST = 1 ? Yes
RWAIT = 0
Sets to counter operation start
Sets to stop the SEC to YEAR counters, reads the counter value, write mode
Checks the counter wait status
Sets the counter operation
RWST = 0 ? No
Yes
HALT or STOP instruction execution
The MCU is placed in HALT or STOP mode.
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CHAPTER 8 REALTIME CLOCK (RTC)
8.4.3 Reading from and writing to the counters of the realtime clock
Read or write the counter after setting 1 to RWAIT first. Set RWAIT to 0 after completion of reading or writing the counter.
Figure 8 - 21 Procedure for Reading Realtime Clock
Start RWAIT = 1
Stops SEC to YEAR counters. Mode to read and write count values
No
RWST = 1?
Yes
Reading SEC
Reading MIN
Reading HOUR
Checks wait status of counter.
Reads second count register. Reads minute count register. Reads hour count register.
Reading WEEK
Reads day-of-week count register.
Reading DAY
Reads day count register.
Reading MONTH
Reads month count register.
Reading YEAR
Reads year count register.
RWAIT = 0
Sets counter operation.
Note
No
RWST = 0?Note
Yes End
Be sure to confirm that RWST = 0 before setting STOP mode.
Caution Complete the series of process of setting the RWAIT bit to 1 to clearing the RWAIT bit to 0 within 1 second.
Remark
The second count register (SEC), minute count register (MIN), hour count register (HOUR), day-of-week count register (WEEK), day count register (DAY), month count register (MONTH), and year count register (YEAR) may be read in any sequence. All the registers do not have to read and only some registers may be read.
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RL78/G23 Figure 8 - 22 Procedure for Writing Realtime Clock
CHAPTER 8 REALTIME CLOCK (RTC)
Start RWAIT = 1
No
RWST = 1?
Yes
Writing SEC
Writing MIN
Writing HOUR
Stops SEC to YEAR counters. Mode to read and write count values
Checks wait status of counter.
Writes second count register. Writes minute count register.
Writes hour count register.
Writing WEEK
Writes day-of-week count register.
Writing DAY
Writes day count register.
Writing MONTH
Writes month count register.
Writing YEAR RWAIT = 0
Writes year count register.
Sets counter operation.
Note
No
RWST = 0?Note
Yes End
Be sure to confirm that RWST = 0 before setting STOP mode.
Caution 1. Complete the series of operations of setting the RWAIT bit to 1 to clearing the RWAIT bit to 0 within 1 second. Caution 2. When changing the values of the SEC, MIN, HOUR, WEEK, DAY, MONTH, and YEAR register while the counting is
in progress (RTCE = 1), rewrite the values of the MIN register after disabling interrupt processing of INTRTC by using the interrupt mask flag register. Furthermore, clear the WAFG, RIFG and RTCIF flags after rewriting the MIN register.
Remark
The second count register (SEC), minute count register (MIN), hour count register (HOUR), day-of-week count register (WEEK), day count register (DAY), month count register (MONTH), and year count register (YEAR) may be written in any sequence. All the registers do not have to be set and only some registers may be written.
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8.4.4 Setting alarm by the realtime clock
Set time of alarm after setting 0 to WALE (alarm operation invalid.) first. Figure 8 - 23 Alarm Processing Procedure
CHAPTER 8 REALTIME CLOCK (RTC)
Start WALE = 0
Match operation of alarm is invalid.
WALIE = 1
alarm match interrupts is valid.
Setting ALARMWM
Sets alarm minute register.
Setting ALARMWH
Sets alarm hour register.
Setting ALARMWW
Sets alarm day-of-week register.
WALE = 1
Match operation of alarm is valid.
No
INTRTC = 1?
Yes
WAFG = 1?
No
Match detection of alarm Yes
Alarm interrupt processing
Fixed-cycle interrupt processing
Remark 1. The alarm minute register (ALARMWM), alarm hour register (ALARMWH), and alarm day-of-week register (ALARMWW) may be written in any sequence.
Remark 2. Fixed-cycle interrupts and alarm match interrupts use the same interrupt source (INTRTC). To use these two types of interrupts at the same time, the source of the interrupt can be identified by checking the fixed-cycle interrupt status flag (RIFG) and the alarm detection status flag (WAFG) when an INTRTC is generated.
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8.4.5 1 Hz output by the realtime clock
Figure 8 - 24 1 Hz Output Setting Procedure
CHAPTER 8 REALTIME CLOCK (RTC)
Start
RTCE = 0
Stops counter operation.
Setting port
Sets P30 = 0 and PM30 = 0
RCLOE1 = 1
Enables output of the RTC1HZ pin (1 Hz).
RTCE = 1
Starts counter operation.
Output start from RTC1HZ pin
Caution First set the RTCWEN bit to 1, while oscillation of the count clock (fRTCCK) is stable.
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CHAPTER 8 REALTIME CLOCK (RTC)
8.4.6 Example of time error correction by the realtime clock
Time can be corrected with high accuracy when it is slow or fast, by setting a value to the time error correction register.
Example of calculating the correction value The correction value used when correcting the count value of the internal counter (16 bits) is calculated by using the following expression. Set the DEV bit to 0 when the correction range is 63.1 ppm or less, or 63.1 ppm or more.
(When DEV = 0) Correction valueNote =
Number of correction counts in 1 minute ÷ 3 = (Oscillation frequency ÷ Target frequency 1) × 32768 × 60 ÷ 3
(When DEV = 1) Correction valueNote =
Number of correction counts in 1 minute = (Oscillation frequency ÷ Target frequency 1) × 32768 × 60
Note
The correction value is the time error correction value calculated by using bits 6 to 0 of the time error correction register (SUBCUD). (When F6 = 0) Correction value = {(F5, F4, F3, F2, F1, F0) 1} × 2 (When F6 = 1) Correction value = {(/F5, /F4, /F3, /F2, /F1, /F0) + 1} × 2 When (F6, F5, F4, F3, F2, F1, F0) is (*, 0, 0, 0, 0, 0, *), time error correction is not performed. "*" is 0 or 1. /F5 to /F0 are bit-inverted values (000011 when 111100).
Remark 1. The correction value is 2, 4, 6, 8, ... 120, 122, 124 or 2, 4, 6, 8, ... 120, 122, 124. Remark 2. The oscillation frequency is a value of the count clock (fRTCCK).
It can be calculated from the output frequency of the RTC1HZ pin × 32768 when the time error correction register is set to its initial value (00H). Remark 3. The target frequency is the frequency resulting after correction performed by using the time error correction register.
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CHAPTER 8 REALTIME CLOCK (RTC)
Correction example 1 Example of correcting from 32772.3 Hz to 32768 Hz (32772.3 Hz 131.2 ppm)
[Measuring the oscillation frequency] To measure the oscillation frequencyNote of each product, a signal at about 32.768 kHz can be output from the PCLBUZ0 pin when the clock error correction register (SUBCUD) is set to its initial value (00H).
Note
See 8.4.5 1 Hz output by the realtime clock for the setting procedure of the RTC1Hz output, and see 10.4 Operations of the Clock Output/Buzzer Output Controller for the setting procedure for output of about 32 kHz from the PCLBUZ0 pin.
[Calculating the correction value] When the output frequency from the PCLBUZ0 pin is 32772.3 Hz: Given that the target frequency is 32768 Hz (32772.3 Hz -131.2 ppm) and the extent of correction is -131.2 ppm (not in the range below -63.1 ppm), set DEV to 0. Accordingly, the expression for calculating the correction value when DEV is 0 is applicable.
Correction value = Error for correction of counting of 1 minute ÷ 3 = (Oscillation frequency ÷ target frequency 1) × 32768 × 60 ÷ 3 = (32772.3 ÷ 32768 1) × 32768 × 60 ÷ 3 = 86
[Calculating the values to be set to (F6 to F0)] When the correction value is 86: If the correction value is 0 or larger (the clock is running slow), set F6 to 0. Calculate (F5, F4, F3, F2, F1, F0) from the correction value.
{ (F5, F4, F3, F2, F1, F0) 1} × 2 (F5, F4, F3, F2, F1, F0) (F5, F4, F3, F2, F1, F0)
= 86 = 44 = (1, 0, 1, 1, 0, 0)
Consequently, when correcting from 32772.3 Hz to 32768 Hz (32772.3 Hz 131.2 ppm), setting the correction register such that DEV is 0 and the correction value is 86 (bits 6 to 0 of the SUBCUD register: 0101100) results in the desired frequency of 32768 Hz (error of 0 ppm).
Figure 8 - 25 shows the operation for correction when the value of (DEV, F6, F5, F4, F3, F2, F1, F0) is (0, 0, 1, 0, 1, 1, 0, 0).
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Figure 8 - 25 Operation for Correction when the Value of (DEV, F6, F5, F4, F3, F2, F1, F0) = (0, 0, 1, 0, 1, 1, 0, 0)
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7FFFH + 56H (86) Count start
7FFFH + 56H (86)
7FFFH + 56H (86)
7FFFH + 56H (86)
RSUBC counter value
0000H
8054H 8055H 0000H 0001H
7FFFH
0000H 0001H
7FFFH 0000H
8054H 8055H
0000H 0001H
7FFFH 0000H
8054H 8055H
0000H 0001H
7FFFH 0000H
8054H 8055H
SEC
00
01
19
20
39
40
59
00
CHAPTER 8 REALTIME CLOCK (RTC)
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CHAPTER 8 REALTIME CLOCK (RTC)
Correction example 2 Example of correcting from 32767.4 Hz to 32768 Hz (32767.4 Hz + 18.3 ppm)
[Measuring the oscillation frequency] To measure the oscillation frequencyNote of each product, a signal at about 1 Hz can be output from the RTC1HZ pin when the clock error correction register (SUBCUD) is set to its initial value (00H).
Note
See 8.4.5 1 Hz output by the realtime clock for the setting procedure for output of about 1 Hz from the RTC1HZ pin.
[Calculating the correction value] When the output frequency from the RTC1HZ pin is 0.9999817 Hz: Oscillation frequency = 32768 × 0.9999817 32767.4 Hz Given that the target frequency is 32768 Hz (32767.4 Hz + 18.3 ppm), set DEV to 0. Accordingly, the expression for calculating the correction value when DEV is 1 is applicable.
Correction value = Error for correction of counting of 1 minute = (Oscillation frequency ÷ Target frequency 1) × 32768 × 60 = (32767.4 ÷ 32768 1) × 32768 × 60 = 36
[Calculating the values to be set to (F6 to F0)] When the correction value is 36: If the correction value is 0 or less (the clock is running fast), set F6 to 0. Calculate (F5, F4, F3, F2, F1, F0) from the correction value.
{(/F5, /F4, /F3, /F2, /F1, /F0) + 1} × 2 (/F5, /F4, /F3, /F2, /F1, /F0) (/F5, /F4, /F3, /F2, /F1, /F0) (F5, F4, F3, F2, F1, F0)
= 36 = 17 = (0, 1, 0, 0, 0, 1) = (1, 0, 1, 1, 1, 0)
Consequently, when correcting from 32767.4 Hz to 32768 Hz (32767.4 Hz + 18.3 ppm), setting the correction register such that DEV is 1 and the correction value is 36 (bits 6 to 0 of the SUBCUD register: 1101110) results in the desired frequency of 32768 Hz (error of 0 ppm).
Figure 8 - 26 shows the operation for correction when the value of (DEV, F6, F5, F4, F3, F2, F1, F0) is (1, 1, 1, 0, 1, 1, 1, 0).
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Figure 8 - 26 Operation for Correction when the Value of (DEV, F6, F5, F4, F3, F2, F1, F0) = (1, 1, 1, 0, 1, 1, 1, 0)
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Count start
7FFFH-24H (36)
7FFFH-24H (36)
Counter (16-bit) 0000H counter value
7FDAH 7FDBH 0000H 0001H
7FFFH
0000H 0001H
7FFFH 0000H 0001H
7FFFH
0000H 0001H
7FFFH 0000H 0001H
7FFFH
0000H 0001H
7FFFH 0000H
7FDAH 7FDBH
SEC
00
01
19
20
39
40
59
00
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CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
The 32-bit interval timer is made up of four 8-bit interval timers (referred to as channels 0 to 3). Each is capable of operating independently and in that case they all have the same functions. Two 8-bit interval timer channels can be connected to operate as a 16-bit interval timer. Four 8-bit interval timer channels can be connected to operate as a 32bit interval timer.
9.1
Overview
The 32-bit interval timer operates with the fMXP, fSXP, fIHP, or fIMP clock or the event input from the ELCL, which is asynchronous with the CPU operation. Table 9 - 1 lists the specifications of the 32-bit interval timer operations and Figure 9 - 1 shows a block diagram of the 32-bit interval timer.
Table 9 - 1 Specifications of 32-Bit Interval Timer Operations
Item
Description
Count source (operating clock)
· fMXP · fSXP · fIHP · fIMP · Event input from the ELCL
Capture clock
· fMXP · fSXP · fIHP · fIMP · Event input from the ELCL
Frequency division ratio · 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128
Operating mode
· 8-bit counter mode Channels 0 to 3 independently operate as 8-bit counters.
· 16-bit counter mode The combinations of channels 0 and 1 and channels 2 and 3 are cascade-connectable to operate as two 16-bit counters.
· 32-bit counter mode Channels 0 to 3 are connected to operate as a 32-bit counter.
· 16-bit capture mode Channels 0 and 1 are connected to operate as a 16-bit counter using the count source, channels 2 and 3 are connected to operate as a 16-bit counter using the capture clock, and the connected counters are used for capture operation.
Interrupt
· Five interrupt sources are integrated into one interrupt signal and output as the INTITL signal. - Output when the counter value in any of channels 0 to 3 matches the compare value. - Output when the capturing of the counter value is completed in capture mode.
Remark
fMXP: High-speed peripheral clock frequency fSXP: Low-speed peripheral clock frequency fIHP: High-speed on-chip oscillator peripheral clock frequency fIMP: Middle-speed on-chip oscillator peripheral clock frequency (4 MHz)
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RL78/G23 Figure 9 - 1 Block Diagram of 32-Bit Interval Timer
CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
CAPEN0
01
fSXP
10
fITL2
Edge detection
Event input from ELCL 11
CAPR0 00
FDIV00m
CTRS0n
1/128 1/64 1/32
111 110 101
ISEL00m
Event input
from ELCL 101
fSXP 100 fMXP 011
fITL0
Divider
1/16 100
1/8 011
1/4 1/2
010 001
1/1 000
fIMP fIHP
010 001
1/1, 1/2, 1/4, 1/8,
FDIV01m
1/16, 1/32, 1/64, 1/128 1/128
CSEL01m
Event input from ELCL 101
1/64 1/32
1/16 1/8 1/4 1/2
111 110 101 100 011 010 001
1/1 000
fSXP 100 fMXP 011
fITL1
fIMP 010 fIHP 001
FDIV02m
1/128 111 1/64 110 1/32 101 1/16 100 1/8 011 1/4 010 1/2 001 1/1 000
FDIV03m
1/128
1/64 1/32
111 110 101
1/16 1/8 1/4 1/2
100 011 010 001
1/1 000
Data bus
INTITLC
MKF0C
Channel 0
ITLEN00
ITLCMP000 (8 bits)
Count operation controller
Clear ITL000 (8 bits)
ITLCAP00 (8 lower-order bits)
INTITL0
ITF0C ITF03 ITF02 ITF01 ITF00
8-bit counter mode
MKF00
ITLMD01, ITLMD00
10 01 00
Data bus
ITLEN01
ITLCMP001 (8 bits)
Count operation controller
Clear ITL001 (8 bits)
Channel 1
ITLCAP00 (8 higher-order bits)
ITLMD01, ITLMD00, CAPEN0
Data bus
100 010 000 xx1
Channel 2
ITLEN02
ITLCMP012 (8 bits)
Count operation controller
Clear ITL012 (8 bits)
ITLMD01, ITLMD00, CAPEN0
Data bus
100 010 000 xx1
Channel 3
ITLEN03
ITLCMP013 (8 bits)
Count operation controller
Clear ITL013 (8 bits)
INTITL1
16-bit counter mode 32-bit counter mode 8-bit counter mode
MKF01
MKF03 MKF02
INTITL2
8-bit counter mode 16-bit counter mode 8-bit counter mode
INTITL3 ITLMKF0
ISEL00m CSEL01m
FDIV0im
CTRS0n
ITLMD0n, ITLEN0i
ITLCSEL0 ITLFDIV00, ITLFDIV01
ITLCC0 ITLCTL0
INTITL
ITL000, ITL001, ITL012, ITL013: 8-bit counters
Note
In 16-bit counter mode, the counters in channels 0 and 1 are connected (ITL000 + ITL001) and the counters in channels 2
and 3 are connected (ITL012 + ITL013).
In 32-bit counter mode, the counters in channels 0 to 3 are connected (ITL000 + ITL001 + ITL012 + ITL013).
ISEL00m, CSEL01m: Bits in the interval timer clock select register (ITLCSEL0) FDIV0im: Bits in the interval timer frequency division register (ITLFDIV0n) CTRS0n: Bits in the interval timer capture control register (ITLCC0) ITLMD0n, ITLEN0i: Bits in the interval timer control register (ITLCTL0)
Remark n = 0, 1 m = 0, 1, 2 i = 0, 1, 2, 3
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CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
9.2
Registers to Control the 32-bit Interval Timer
The following registers are used to control the 32-bit interval timer.
· Peripheral enable register 1 (PER1) · Peripheral reset control register 1 (PRR1) · Interval timer compare registers 0mn (ITLCMP0mn) (mn = 00, 01, 12, 13) · Interval timer compare registers 0n (ITLCMP0n) (n = 0, 1)Note · Interval timer capture register 00 (ITLCAP00)Note · Interval timer control register (ITLCTL0) · Interval timer clock select register 0 (ITLCSEL0) · Interval timer frequency division register 0 (ITLFDIV00) · Interval timer frequency division register 1 (ITLFDIV01) · Interval timer capture control register 0 (ITLCC0) · Interval timer status register (ITLS0) · Interval timer match detection mask register (ITLMKF0)
Note
This register is only accessible in 16 bits.
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CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
9.2.1 Peripheral enable register 1 (PER1)
This register is used to enable or disable the supply of a clock signal to various on-chip peripheral modules. Clock supply to an on-chip peripheral module that is not to be used can be stopped to decrease power consumption and noise. If the 32-bit interval timer is to be used, be sure to set bit 4 (TML32EN) of this register to 1. The PER1 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 9 - 2 Format of Peripheral Enable Register 1 (PER1)
Address: After reset: R/W:
F00FAH 00H R/W
Symbol
<7>
PER1 DACEN
<6> SMSEN
<5> CMPEN
<4> TML32EN
<3> DTCEN
<2> UTAEN
<1> REMCEN
<0> CTSUEN
TML32EN
Control of supply of an input clock to the 32-bit interval timer
0
Stops supply of an input clock.
· The SFRs used by the 32-bit interval timer cannot be written.
· When an SFR used by the 32-bit interval timer is read, the value returned is 00H or 0000H.
1
Enables supply of an input clock.
· The SFRs used by the 32-bit interval timer can be read and written.
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CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
9.2.2 Peripheral reset control register 1 (PRR1)
The PRR1 register is used to control resetting of the on-chip peripheral modules. Each bit in this register controls resetting and release from the reset state of the corresponding on-chip peripheral module. To place the 32-bit interval timer in the reset state, be sure to set bit 4 (TML32RES) of this register to 1. The PRR1 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 9 - 3 Format of Peripheral Reset Control Register 1 (PRR1)
Address: After reset: R/W:
F00FBH 00H R/W
Symbol
<7>
<6>
<5>
<4>
3
PRR1 DACRES SMSRES CMPRES TML32RES
0
2
<1>
<0>
0
REMCRES CTSURES
TML32RES
Control resetting of the 32-bit interval timer
0
The 32-bit interval timer is released from the reset state.
1
The 32-bit interval timer is in the reset state.
· The SFRs for use with the 32-bit interval timer are initialized.
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CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
9.2.3 Interval timer compare registers 0mn (ITLCMP0mn) (mn = 00, 01, 12, 13)
These are compare value registers used in 8-bit counter mode. These registers can be set by an 8-bit memory manipulation instruction. The value of each ITLCMP0mn register is FFH following a reset. A value from 01H to FFH can be specified. Setting these registers to 00H is prohibited. These registers hold values to be compared with the ITL000 to ITL013 counter values.
Figure 9 - 4 Format of Interval Timer Compare Registers 0mn (ITLCMP0mn)
Address: After reset: R/W:
F0360H (ITLCMP000), F0361H (ITLCMP001), F0362H (ITLCMP012), F0363H (ITLCMP013) FFH R/WNote
Symbol
7
6
5
4
3
2
1
0
ITLCMP0mn
Note
Write to ITLCMP000 while the ITLEN00 bit is 0. Write to ITLCMP001 while the ITLEN01 bit is 0. Write to ITLCMP012 while the ITLEN02 bit is 0. Write to ITLCMP013 while the ITLEN03 bit is 0.
9.2.4 Interval timer compare registers 0n (ITLCMP0n) (n = 0, 1)
These are compare value registers used in 16-bit or 32-bit counter mode. These registers can be set by a 16-bit memory manipulation instruction. The value of each ITLCMP0n register is FFFFH following a reset. A value from 0001H to FFFFH can be specified. Setting these registers to 0000H is prohibited. These registers hold values to be compared with the ITL0n counter values. When the ITLMD01 and ITLMD00 bits are set to 1 and 0, respectively, these registers are used as compare registers in 32-bit counter mode; specify the upper 16-bit compare value in ITLCMP01 and the lower 16-bit compare value in ITLCMP00.
Figure 9 - 5 Format of Interval Timer Compare Registers 0n (ITLCMP0n)
Address: After reset: R/W:
F0360H, F0361H (ITLCMP00), F0362H, F0363H (ITLCMP01) FFFFH R/WNote
Symbol 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ITLCMP0n
Note
Write to ITLCMP00 while the ITLEN00 bit is 0. Write to ITLCMP01 while the ITLEN02 bit is 0 in 16-bit counter mode or while the ITLEN00 bit is 0 in 32-bit counter mode.
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CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
9.2.5 Interval timer capture register 00 (ITLCAP00)
This register holds 16-bit captured values when the interval timers are operating in 16-bit counter mode. The values of the 16-bit counters (ITL000 + ITL001) are stored in the capture register (ITLCAP00) in response to the capture trigger selected in interval timer capture control register 0 (ITLCC0) when the CAPEN0 bit in the ITLCC0 register is 1. When an interrupt on compare match with ITLCMP01 is to be used, select the counter clock in interval timer clock select register 0 (ITLCSEL0) and set the comparison value in interval timer compare register 01 (ITLCMP01).
Figure 9 - 6 Format of Interval Timer Capture Register 00 (ITLCAP00)
Address: After reset: R/W:
F0364H, F0365H 0000H R
Symbol 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ITLCAP00
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CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
9.2.6 Interval timer control register (ITLCTL0)
This register is used to start or stop counting by the interval timer and to select 8-bit, 16-bit, or 32-bit counter mode. This register can be set by a 1-bit or 8-bit manipulation instruction. The value of this register is 00H following a reset.
Figure 9 - 7 Format of Interval Timer Control Register (ITLCTL0)
Address: After reset: R/W:
F0366H 00H R/W
Symbol
7
6
5
ITLCTL0 ITLMD01 ITLMD00
0
4
<3>
<2>
<1>
<0>
0
ITLEN03 ITLEN02 ITLEN01 ITLEN00
ITLMD01 0 0
1
1
ITLMD00
Selection of 8-bit, 16-bit, or 32-bit counter modeNote 1
0
The interval timer operates in 8-bit counter mode.
1
The interval timer operates in 16-bit counter mode (channel 0 is connected with
channel 1 and channel 2 is connected with channel 3).
0
The interval timer operates in 32-bit counter mode (channels 0 to 3 are
connected).
1
Setting prohibited.
ITLEN03
8-bit counter mode: ITL013 count enableNote 2
0
Counting stops.
1
Counting begins.
In 8-bit counter mode, writing 1 to this bit starts up-counting in the ITL013 counter and writing 0 stops it.
In 16-bit counter mode, this bit is not used; write 0 to it.
In 32-bit counter mode, this bit is not used; write 0 to it.
ITLEN02
8-bit counter mode: ITL012 count enableNote 2 16-bit counter mode: ITL012 + ITL013 count enableNote 2
0
Counting stops.
1
Counting begins.
In 8-bit counter mode, writing 1 to this bit starts up-counting in the ITL012 counter and writing 0 stops it. In 16-bit counter mode, writing 1 to this bit starts up-counting in the ITL012 + ITL013 counter and writing 0
stops it.
In 32-bit counter mode, this bit is not used; write 0 to it.
ITLEN01
8-bit counter mode: ITL001 count enableNote 2
0
Counting stops.
1
Counting begins.
In 8-bit counter mode, writing 1 to this bit starts up-counting in the ITL001 counter and writing 0 stops it.
In 16-bit counter mode, this bit is not used; write 0 to it.
In 32-bit counter mode, this bit is not used; write 0 to it.
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CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
ITLEN00
8-bit counter mode: ITL000 count enableNote 2 16-bit counter mode: ITL000 + ITL001 count enableNote 2 32-bit counter mode: ITL000 + ITL001 + ITL012 + ITL013 count enableNote 2
0
Counting stops.
1
Counting begins.
In 8-bit counter mode, writing 1 to this bit starts up-counting in the ITL000 counter and writing 0 stops it.
In 16-bit counter mode, writing 1 to this bit starts up-counting in the ITL000 + ITL001 counter and writing 0
stops it.
In 32-bit counter mode, writing 1 to this bit starts up-counting in the ITL000 + ITL001 + ITL012 + ITL013
counter and writing 0 stops it.
Note 1. To change the timer mode, be sure to write to the ITLMD00 and ITLMD01 bits only while the ITLEN00,
Note 2.
ITLEN01, ITLEN02, and ITLEN03 bits are all 0. When one of the ITLEN03 to ITLEN00 bits is cleared to 0, the corresponding counter is cleared to 0 without
synchronization with the counter clock.
Mode
ITLMD01 ITLMD00 ITLEN03 ITLEN02 ITLEN01 ITLEN00
Target Counter
8-bit mode
0
0
ITL000
ITL001
ITL012
ITL013
16-bit mode
0
1
Always set
to 0.
Always set to 0.
ITL000+ITL001
Always set
Always set
to 0.
to 0.
ITL012+ITL013
32-bit mode
1
0
Always set Always set Always set
ITL000+ITL001+ITL012+ITL013
to 0.
to 0.
to 0.
Note Note Note
: Enables counting in the target counter. In 8-bit counter mode, two or more bits of ITLEN03 to ITLEN00 can be set to 1 or 0 at the same time. In 16-bit counter mode, the ITLEN02 and ITLEN00 bits can be set to 1 or 0 at the same time.
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CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
9.2.7 Interval timer clock select register 0 (ITLCSEL0)
This register is used to select the count source for the interval timer. This register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 9 - 8 Format of Interval Timer Clock Select Register 0 (ITLCSEL0)
Address: After reset: R/W:
F0367H 00H R/W
Symbol
7
6
5
4
3
ITLCSEL0
0
CSEL012 CSEL011 CSEL010
0
2 ISEL002
1 ISEL001
0 ISEL000
CSEL012 0 0 0 0 1 1
CSEL011 0 0 1 1 0 0
Others
CSEL010
Selection of interval timer count clock for capturing (fITL1)Note
0
Counting stops.
1
fIHP
0
fIMP
1
fMXP
0
fSXP
1
Event input from the ELCL
Setting prohibited.
ISEL002 ISEL001 ISEL000
Selection of interval timer count clock (fITL0)Note
0
0
0
Counting stops.
0
0
1
fIHP
0
1
0
fIMP
0
1
1
fMXP
1
0
0
fSXP
1
0
1
Event input from the ELCL
Others
Setting prohibited.
Note
Be sure to write to the CSEL012 to CSEL010 bits and ISEL002 to ISEL000 bits only while the ITLEN03 to ITLEN00 bits are all 0.
Remark
fMXP: fSXP: fIHP: fIMP:
High-speed peripheral clock frequency Low-speed peripheral clock frequency High-speed on-chip oscillator peripheral clock frequency Middle-speed on-chip oscillator peripheral clock frequency (4 MHz)
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CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
9.2.8 Interval timer frequency division register 0 (ITLFDIV00)
This register is used to select the counter clock for the interval timer. This register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 9 - 9 Format of Interval Timer Frequency Division Register 0 (ITLFDIV00)
Address: After reset: R/W:
F0368H 00H R/W
Symbol
7
6
5
4
3
2
1
0
ITLFDIV00
0
FDIV012 FDIV011 FDIV010
0
FDIV002 FDIV001 FDIV000
FDIV012 FDIV011 FDIV010
8-bit counter mode: Counter clock for ITL001Note 1
0
0
0
fITL0
0
0
1
fITL0/2
0
1
0
fITL0/4
0
1
1
fITL0/8
1
0
0
fITL0/16
1
0
1
fITL0/32
1
1
0
fITL0/64
1
1
1
fITL0/128
In 8-bit counter mode, ITL001 counts cycles of the counter clock specified in the FDIV010 to FDIV012 bits. In 16-bit counter mode, these bits are not used; write 000B to them. In 32-bit counter mode, these bits are not used; write 000B to them.
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CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
FDIV002
FDIV001
FDIV000
8-bit counter mode: Counter clock for ITL000Note 2 16-bit counter mode: Counter clock for ITL000 + ITL001Note 2 32-bit counter mode: Counter clock for ITL000 + ITL001 + ITL012 +
ITL013Note 2
0
0
0
fITL0
0
0
1
fITL0/2
0
1
0
fITL0/4
0
1
1
fITL0/8
1
0
0
fITL0/16
1
0
1
fITL0/32
1
1
0
fITL0/64
1
1
1
fITL0/128
In 8-bit counter mode, ITL000 counts cycles of the counter clock specified in the FDIV000 to FDIV002 bits. In 16-bit counter mode, ITL000 + ITL001 counts cycles of the counter clock specified in the FDIV000 to FDIV002 bits. In 32-bit counter mode, ITL000 +ITL001 + ITL012 + ITL013 counts cycles of the counter clock specified in the FDIV000 to FDIV002 bits.
Note 1. Note 2.
In 8-bit counter mode, be sure to write to the FDIV012 to FDIV010 bits only while the ITLEN01 bit is 0. Be sure to write to the FDIV002 to FDIV000 bits only while the ITLEN00 bit is 0.
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CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
9.2.9 Interval timer frequency division register 1 (ITLFDIV01)
This register is used to select the counter clock for the interval timer. This register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 9 - 10 Format of Interval Timer Frequency Division Register 1 (ITLFDIV01)
Address: After reset: R/W:
F0369H 00H R/W
Symbol
7
6
5
4
3
2
1
0
ITLFDIV01
0
FDIV032 FDIV031 FDIV030
0
FDIV022 FDIV021 FDIV020
FDIV032 FDIV031 FDIV030
8-bit counter mode: Counter clock for ITL013Note 1
0
0
0
fITL0
0
0
1
fITL0/2
0
1
0
fITL0/4
0
1
1
fITL0/8
1
0
0
fITL0/16
1
0
1
fITL0/32
1
1
0
fITL0/64
1
1
1
fITL0/128
In 8-bit counter mode, ITL013 counts cycles of the counter clock specified in the FDIV030 to FDVI032 bits. In 16-bit counter mode, these bits are not used; write 000B to them. In 32-bit counter mode, these bits are not used; write 000B to them.
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CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
FDIV022
FDIV021
FDIV020
8-bit counter mode: Counter clock for ITL012Note 2 16-bit counter mode: Counter clock for ITL012 and ITL013Note 2
0
0
0
fITL0
0
0
1
fITL0/2
0
1
0
fITL0/4
0
1
1
fITL0/8
1
0
0
fITL0/16
1
0
1
fITL0/32
1
1
0
fITL0/64
1
1
1
fITL0/128
In 8-bit counter mode, ITL012 counts cycles of the counter clock specified in the FDIV020 to FDIV022 bits. In 16-bit counter mode, ITL012 + ITL013 counts cycles of the counter clock specified in the FDIV020 to FDIV022 bits. In 32-bit counter mode, these bits are not used; write 000B to them.
Note 1. Note 2.
In 8-bit counter mode, be sure to write to the FDIV032 to FDIV030 bits only while the ITLEN03 bit is 0. In 8-bit or 16-bit counter mode, be sure to write to the FDIV022 to FDIV020 bits only while the ITLEN02 bit is 0.
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CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
9.2.10 Interval timer capture control register 0 (ITLCC0)
This register is used to enable or disable the capture function of the interval timer, specify whether to hold or clear the capture completion flag, set up the software trigger, and select the capture trigger. This register can be set by a 1-bit or 8-bit manipulation instruction. The value of this register is 00H following a reset.
Figure 9 - 11 Format of Interval Timer Capture Control Register 0 (ITLCC0)
Address: After reset: R/W:
F036AH 00H R/W
Symbol
7
<6>
5
<4>
3
2
ITLCC0 CAPEN0 CAPF0CR CAPF0
CAPR0 CAPC0CR
0
1 CTRS01
0 CTRS00
CAPEN0
0
Capturing is disabled.
1
Capturing is enabled.
Capture enableNote 1
CAPF0CR
Capture completion flag clearNote 2
0
The value of the capture completion flag CAPF0 is held.
1
The value of the capture completion flag CAPF0 is cleared.
CAPF0 0 1
Capture completion flagNote 3 Capturing has not been completed. Capturing has been completed. This flag is set to 1 after a capture trigger selected in the CTRS01 and CTRS00 bits is generated and the captured data is stored in ITLCAP00. Writing 1 to the CAPF0CR bit clears this flag to 0.
CAPR0 0 1
Software capture triggerNotes 4, 7 A software trigger for capturing is not generated. A software trigger for capturing is generated.
CAPC0CR
Selection of capture counter clearing after capturingNote 5
0
The capture counter value is held after the completion of capturing.
1
The capture counter value is cleared after the completion of capturing.
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CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
CTRS01 CTRS00
Selection of capture triggerNotes 6, 7
0
0
Software trigger
0
1
Interrupt on compare match with ITLCMP01
1
0
fSXP (rising edge)
1
1
Event input from ELCL (rising edge)
Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Note 7.
Be sure to write to the CAPEN0 bit only while the ITLEN03 to ITLEN00 bits are all 0. The CAPF0CR bit is always read as 0. Bit 5 is read-only. The CAPR0 bit is always read as 0. Be sure to write to the CAPC0CR bit only while the ITLEN03 to ITLEN00 bits are all 0. Be sure to write to the CTRS01 and CTRS00 bits only while the ITLEN03 to ITLEN00 bits are all 0. In the capture operation, the interval at which the capture trigger is generated should be two or more cycles of the counter clock.
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CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
9.2.11 Interval timer status register (ITLS0)
This is a status register for the interval timer. This register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset. When the value of the ITL0mn counter (mn = 00, 01, 12, 13) matches the value specified in the compare registers ITLCMP0mn, ITLCMP00, and ITLCMP01, the status flag for the corresponding channel is set. When a capture trigger is generated while the CAPEN0 bit in the ITLCC0 register is 1, the capture completion status flag is set after the value of the ITL0n counter is stored in the ITLCAP00 register. The values of the ITF0C and ITF03 to ITF00 bits in this register are ORed and output as the INTITL interrupt signal. Table 9 - 2 shows the conditions for setting the interrupt status flags in each timer mode selected by the ITLMD01 and ITLMD00 bits.
Figure 9 - 12 Format of Interval Timer Status Register (ITLS0)
Address: After reset: R/W:
F036BH 00H R/WNote
Symbol
7
6
5
4
3
2
1
0
ITLS0
0
0
0
ITF0C
ITF03
ITF02
ITF01
ITF00
ITF0C 0 1
Capture detection flag Completion of capturing has not been detected. Completion of capturing has been detected.
ITF03 0 1
Compare match detection flag for channel 3 A compare match signal has not been detected in channel 3. A compare match signal has been detected in channel 3.
ITF02 0 1
Compare match detection flag for channel 2 A compare match signal has not been detected in channel 2. A compare match signal has been detected in channel 2.
ITF01 0 1
Compare match detection flag for channel 1 A compare match signal has not been detected in channel 1. A compare match signal has been detected in channel 1.
ITF00
Compare match detection flag for channel 0
0
A compare match signal has not been detected in channel 0.
1
A compare match signal has been detected in channel 0.
Note
Writing 1 to each bit is ignored. To clear the ITF0C or ITF0i bit, write 0 to the desired bit and 1 to the other bits by using an 8-bit memory manipulation instruction.
Caution
If the value of the ITLS0 register is other than 00H, the interrupt request flag (ITLIF bit) is not set even when a compare match for the channel currently having that event or completion of capture is detected. That is, an interrupt is not generated in such cases. For this reason, when clearing the detection flags, check all channels that are in use and set the ITLS0 register to 00H.
Remark n = 0, 1, 2, 3, C
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CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
Table 9 - 2 Conditions for Setting the Interrupt Status Flags in Each Timer Mode
Mode 8-bit mode
16-bit mode 32-bit mode
ITLMD01 0
0 1
ITLMD00 0
1 0
CAPEN0 x x x x x x 1
Status Flag ITF00 ITF01 ITF02 ITF03 ITF00 ITF02 ITF0C ITF00
Conditions for Setting Status Flag
The ITL000 value matches the ITLCMP000 value.
The ITL001 value matches the ITLCMP001 value.
The ITL012 value matches the ITLCMP012 value.
The ITL013 value matches the ITLCMP013 value.
The ITL000 + ITL001 value matches the ITLCMP00 value.
The ITL012 + ITL013 value matches the ITLCMP00 value.
The ITL000 + ITL001 value is stored in ITLCAP00 after a capture trigger is generated.
The ITL000 + ITL001 + ITL012 + ITL013 value matches the ITLCMP00 + ITLCMP01 value.
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CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
9.2.12 Interval timer match detection mask register (ITLMKF0)
This is a match detection mask register for the interval timer. This register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset. Interrupt status flags ITLF0C and ITLF0i (i = 0 to 3), that is, those of the set of generating sources for INTITL, are masked by setting the MKF0C and MKF0i (i = 0 to 3) bits to 1.
Figure 9 - 13 Format of Interval Timer Match Detection Mask Register (ITLMKF0)
Address: After reset: R/W:
F036CH 00H R/W
Symbol
7
6
5
4
3
2
1
0
ITLMKF0
0
0
0
MKF0C
MKF03
MKF02
MKF01
MKF00
MKF0C 0 1
ITF0C is not masked. ITF0C is masked.
Mask for capture detection status flagNote
MKF03 0 1
Mask for compare match status flag for channel 3Note ITF03 is not masked. ITF03 is masked.
MKF02 0 1
Mask for compare match status flag for channel 2Note ITF02 is not masked. ITF02 is masked.
MKF01 0 1
Mask for compare match status flag for channel 1Note ITF01 is not masked. ITF01 is masked.
MKF00
Mask for compare match status flag for channel 0Note
0
ITF00 is not masked.
1
ITF00 is masked.
Note
When a bit is set to 1 to mask a desired interrupt, the corresponding flag bit in the ITLS0 register is not set. Therefore, the polling processing using the flag bit cannot be done in this case. When specifying the compare match operation in one of channels 0 to 3, do not mask the status flag for the channel. To poll the capture completion state, the CAPF0 bit in the ITLCC0 register can be used instead of the status flag in the ITLS0 register.
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CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
9.3
Operation
9.3.1 Counter mode settings
The interval timer has three modes: 8-bit counter mode, 16-bit counter mode, and 32-bit counter mode. Table 9 - 3 to Table 9 - 5 show the registers and settings used in 8-bit counter mode, 16-bit counter mode, and 32-bit counter mode.
Table 9 - 3 Registers and Settings Used in 8-Bit Counter Mode
Register Name (Symbol)
Bit
Function
Interval timer compare registers 0mn (ITLCMP0mn)
Bits 7 to 0
Specify 8-bit compare values for channels 0 to 3.
Interval timer control register 0 (ITLCTL0)
ITLEN00
Specify whether to start or stop counting in channel 0.
ITLEN01
Specify whether to start or stop counting in channel 1.
ITLEN02
Specify whether to start or stop counting in channel 2.
ITLEN03
Specify whether to start or stop counting in channel 3.
ITLMD00
Set to 0.
ITLMD01
Set to 0.
Interval timer frequency division registers n (ITLFDIV0n)
FDIV000 to FDIV002
Select the count clock for channel 0.
FDIV010 to FDIV012
Select the count clock for channel 1.
FDIV020 to FDIV022
Select the count clock for channel 2.
FDIV030 to FDIV032
Select the count clock for channel 3.
Interval timer clock select register 0 (ITLCSEL0)
ISEL000 to ISEL002 Select the count clock for the interval timer.
CSEL010 to CSEL012
Set to 000B.
Interval timer capture control register 0 (ITLCC0)
Bits 7 to 0
Set to 0.
Remark mn = 00, 01, 12, 13
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CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
Table 9 - 4 Registers and Settings Used in 16-Bit Counter Mode
Register Name (Symbol)
Bit
Function
Interval timer compare registers 0n (ITLCMP0n)
Bits 15 to 0
Specify 16-bit compare values for channels 0 and 1, and channels 2 and 3.
Interval timer control register 0 (ITLCTL0)
ITLEN00
Specify whether to start or stop counting in channels 0 and 1.
ITLEN01
Set to 0.
ITLEN02
Specify whether to start or stop counting in channels 2 and 3.
ITLEN03
Set to 0.
ITLMD00
Set to 1.
ITLMD01
Set to 0.
Interval timer frequency division registers n (ITLFDIV0n)
FDIV000 to FDIV002
Select the count clock for channels 0 and 1.
FDIV010 to FDIV012
Set to 000B.
FDIV020 to FDIV022
Select the count clock for channels 2 and 3.
FDIV030 to FDIV032
Set to 000B.
Interval timer clock select register 0 (ITLCSEL0)
ISEL000 to ISEL002 Select the count clock for the interval timer.
CSEL010 to CSEL012
Set to 000B.
Interval timer capture control register 0 (ITLCC0)
Bits 7 to 0
Set to 0.
Remark n = 0, 1
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CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
Table 9 - 5 Registers and Settings Used in 32-Bit Counter Mode
Register Name (Symbol)
Bit
Function
Interval timer compare registers 0n (ITLCMP0n)
Bits 15 to 0
Specify a compare value in 32-bit counter mode. Specify the lower 16 bits of the compare value (16-bit value for channels 0 and 1) in ITLCMP00 and the upper 16 bits of the compare value (16-bit value for channels 2 and 3) in ITLCMP01.
Interval timer control register 0 (ITLCTL0)
ITLEN00
Specify whether to start or stop counting in channels 0 to 3.
ITLEN01
Set to 0.
ITLEN02
Set to 0.
ITLEN03
Set to 0.
ITLMD00
Set to 0.
ITLMD01
Set to 1.
Interval timer frequency division registers n (ITLFDIV0n)
FDIV000 to FDIV002
Select the count clock for channels 0 to 3.
FDIV010 to FDIV012
Set to 000B.
FDIV020 to FDIV022
Set to 000B.
FDIV030 to FDIV032
Set to 000B.
Interval timer clock select register 0 (ITLCSEL0)
ISEL000 to ISEL002 Select the count clock for the interval timer.
CSEL010 to CSEL012
Set to 000B.
Interval timer capture control register 0 (ITLCC0)
Bits 7 to 0
Set to 0.
Remark n = 0, 1
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CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
9.3.2 Capture mode settings
The interval timer provides 16-bit capture mode. Table 9 - 6 shows the registers and settings used in 16-bit capture mode.
Table 9 - 6 Registers and Settings Used in 16-Bit Capture Mode
Register Name (Symbol)
Bit
Function
Interval timer compare register 00 (ITLCMP00)
Bits 15 to 0
16-bit compare value for channels 0 and 1. Set to FFFFH.
Interval timer compare register 01 (ITLCMP01)
Bits 15 to 0
16-bit compare value for channels 2 and 3. Specify a compare value.
Interval timer control register 0 (ITLCTL0)
ITLEN00
Specify whether to start or stop counting in channels 0 and 1.
ITLEN01
Set to 0.
ITLEN02
Specify whether to start or stop counting in channels 2 and 3.
ITLEN03
Set to 0.
ITLMD00
Set to 1.
ITLMD01
Set to 0.
Interval timer frequency division registers FDIV000 to FDIV002 Select the count clock for channel 0.
n (ITLFDIV0n)
FDIV010 to FDIV012 Set to 000B.
FDIV020 to FDIV022 Set to 000B.
FDIV030 to FDIV032 Set to 000B.
Interval timer clock select register 0 (ITLCSEL0)
ISEL000 to ISEL002 Select the count clock for the interval timer in channels 0 and 1.
CSEL010 to CSEL012
Select the count clock for the interval timer for capturing in channels 2 and 3.
Interval timer capture control register 0 (ITLCC0)
CAPEN0 CAPC0CR
Set to 1.
Specify whether to clear or hold the counter value in channels 0 and 1 after the completion of capturing.
CTRS00 and CTRS01
Select a capture trigger.
Caution Channels 2 and 3 can only be used in 16-bit counter mode when an interrupt on compare match with ITLCMP01 is not to be used as a capture trigger.
Remark n = 0, 1
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CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
9.3.3 Timer operation
The ITL0mn counter counts up cycles of the counting clock specified in the interval timer frequency division registers (ITLFDIV00 and ITLFDIV01). An interrupt request signal (INTITL) is generated on the counting of the next clock cycle after the value of the counter matches the comparison value. The interrupt request signal (INTITL) remains high until the value of the ITLS0 register becomes 00H. While the interrupt request signal (INTITL) is high, neither the generation of a further interrupt request (INTITL) nor setting of the interrupt request flag (ITLIF) proceeds even if a compare match or capture completion is detected for an operating channel. Clearing the ITLEN00 to ITLEN03 bits to 0 clears the counter value.
Figure 9 - 14 Example of Timer Operation
Count clock ITLmn counter value FFFFH
Counter channel i 00H
ITLEN 0i bit in ITLCTL0 register
INTITL
Compare register
Writing 0 to ITF 0i clears the interrupt .
FFFFH
Remark mn = 00, 01, 12, 13 i = 0, 1, 2, 3
Modifying ITLEN0i from 1 to 0 clears the counter without synchronization with the count clock .
Time
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CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
9.3.4 Capture operation
When the setting of the CAPEN0 bit in the ITLCC0 register is 1, the values in the 16-bit counters (ITL000 and ITL001) are stored in interval timer capture register 00 (ITLCAP00) in response to the capture trigger. The capture trigger is selectable from among the interrupt on compare match with the ITLCMP01 register, fSXP, an event signal input from the ELCL, and a software trigger (setting the CAPR0 bit to 1). To use the interrupt on compare match with the ITLCMP01 register as the capture trigger, set interval timer clock select register 0 (ITLCSEL0) to select the clock for counting, and set interval timer compare register 01 (ITLCMP01) to specify the comparison value. When using fSXP, an event signal input from the ELCL, or a software trigger (setting the CAPR0 bit to 1) as a capture trigger, channels 2 and 3 can be used in 16-bit counter mode. After a capture trigger is input and the counter value is stored in the interval timer capture register, the interrupt request signal (INTITL) is output, the capture completion flag (CAPF0) and capture detection flag (ITF0C) are set to 1, and the flag values are retained until they are explicitly cleared. The CAPF0 flag can be cleared by setting the CAPF0CR bit to 1. The ITF0C flag in the ITLS0 register can be cleared by writing 0 to it. Since capture operations operate with the counter clock, the interval at which the capture trigger is generated should be two or more cycles of the counter clock. If a capture trigger is generated again within two cycles of the counter clock after an earlier capture trigger was generated, the CAPF0 bit may not be set. Note that, when the setting of any of the bits in the ITLS0 register is 1, neither the generation of a further interrupt request (INTITL) nor setting of the interrupt request flag (ITLIF) proceeds, even if the capture detection flag (ITL0C) is set.
Figure 9 - 15 Example of Capture Operation
Count clock ITLEN0i
ITLmn counter value
Capture trigger input (internal signal)
0000H
0001H 0002H
0FFFH 1000H 0000H
X-1
X
X+1
0FFFH 1000H 0000H
The counter value is cleared to0 when a capture interrupt occurs when CAPC0CR = 1. (It is not cleared when CAPC0CR = 0.)
ITLCAP 00 INTITL
0000H Completion of capturing is detected.
1000H
1000H
ITF0C CAPF0
Completion of capturing is detected.
0 is written to the capture detection flag.
CAPF0CR
1 is written to clear the capture completion flag.
Remark mn = 00, 01, 12, 13 i = 0, 1, 2, 3
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CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
After the counter value matches the compare value, the counter value is cleared on the counting of the next clock cycle when the CAPC0CR bit in the ITLCC0 register is 1. It is not cleared when the CAPC0CR bit is 0. Table 9 - 7 shows the interrupt sources in 8-bit, 16-bit, and 32-bit counter modes. The ITF00 to ITF03 and ITF0C bits are interrupt status flags in the ITLS0 register. When any of the interrupt status flag is set, an interrupt request is output as the INTITL signal. When multiple interrupt flags are simultaneously set to 1, clear each flag in the ITLS0 register by writing 0 to them in a bit-by-bit manner to ensure that all interrupt sources are checked without omission.
Table 9 - 7
Interrupt Source ITF00
ITF01 ITF02
ITF03 ITF0C
Interrupt Sources in 8-Bit, 16-Bit, and 32-Bit Counter Modes
Interrupt Condition in 8-Bit Counter Mode
Interrupt Condition in 16-Bit Counter Interrupt Condition in 32-Bit Counter
Mode
Mode
Next rising edge of the counter clock after a compare match in channel 0
Next rising edge of the counter clock after a compare match in channels 0 and 1
Next rising edge of the counter clock after a compare match
Next rising edge of the counter clock Not generated after a compare match in channel 1
Not generated
Next rising edge of the counter clock after a compare match in channel 2
Next rising edge of the counter clock after a compare match in channels 2 and 3
Not generated
Next rising edge of the counter clock Not generated after a compare match in channel 3
Not generated
Not generated; this is the case when the setting of ITLCC0 is 00H.
Timing of storing the counter value in the capture register after a capture trigger is input
Not generated; this is the case when the setting of ITLCC0 is 00H.
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CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
9.3.5 Interval timer setting procedures
The following shows the procedures for setting up the 32-bit interval timer.
Figure 9 - 16 Procedure for Starting the 32-Bit Interval Timer
Procedure for starting the 32-bit interval timer
Start operation.
TML32RES = 0
Release the 32-bit interval timer from the reset state.
TML32EN = 1
Set up the ITLMD00 and ITLMD01 bits.
Set up the ISEL000 to ISEL002 bits. Set up the ITLFDIV0n register. Set up the ITLCMP0n register.
Enable the clock supply to the 32-bit interval timer.
Select 8-bit, 16-bit, or 32-bit counter mode.
Select the count clock for the interval timer. Select the frequency division ratio for the count source. Specify a compare value.
Set the CAPEN0 bit. Clear the CAPF0CR bit. Set up the CSEL010 to CSEL012 bits. Clear the CAPC0CR bit. Set up the CTRS00 and CTRS01 bits.
When using the capture function Enable capturing. Clear the capture completion flag. Select the count clock for the capture timer. Specify the clearing of the counter values in channels 0 and 1 after completion of capturing. Select the capture trigger.
Clear the ITF0i bits. Set up the MKF0i bits.
ITLEN0i = 1
When using an interrupt Clear the ITF0i interrupt status flags. Set up masks for the ITF0i status flags. Note: When using this timer as an interval timer, do not mask the interrupts.
When selecting a compare match in channels 2 and 3 as the capture trigger in 16-bit counter mode, set the MFK02 bit to 1 to specify a mask.
Start the 32-bit interval timer.
CAPR0 = 1 Wait for an interrupt.
Set the CAPR0 bit to 1 when using the capture function and software capture trigger.
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RL78/G23 Figure 9 - 17 Procedure for Stopping the 32-Bit Interval Timer
CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
Procedure for stopping the 32-bit interval timer Starting to stop the counter
Set the MKF0i bits. Clear the ITF0i bits.
Set the MKF0C bit. Clear the ITF0C bit.
ITLEN0i = 0
Stop
Set up masks for the ITF0i status flags. Clear the ITF0i interrupt status flags.
When the capture function is in use Set up a mask for the ITF0C status flag. Clear the ITF0C interrupt status flag.
Stop the 32-bit interval timer. Counting stops after one cycle of the source clock.
Figure 9 - 18 Procedure for Changing the Operating Mode of the 32-Bit Interval Timer
Procedure for changing the operating mode of the 32-bit interval timer Starting to change the operating mode
Set the MKF0i bits. Clear the ITF0i bits.
Set the MKF0C bit. Clear the ITF0C bit.
ITLEN00 to ITLEN03 = 0
Set up masks for the ITF0i status flags. Clear the ITF0i interrupt status flags.
When the capture function is in use Set up a mask for the ITF0C status flag. Clear the ITF0C interrupt status flag.
Disable all counters in the 32-bit interval timer.
Wait for stopping.
Wait for at least one cycle of the count source until the timer is stopped.
Make the setting to change the operating mode.
Change the operating mode of the 32-bit interval timer (see Figure 9 - 16).
Completion of changing the operating mode
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RL78/G23 Figure 9 - 19 Procedure for Resetting the 32-Bit Interval Timer
CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
Procedure for resetting the 32-bit interval timer
Start of the procedure for resetting
Set the MKF0i bits. Clear the ITF0i bits.
Set the MKF0C bit. Clear the ITF0C bit.
TML32RES = 1
Set up masks for the ITF0i status flags. Clear the ITF0i interrupt status flags.
When the capture function is in use Set up a mask for the ITF0C status flag. Clear the ITF0C interrupt status flag.
Reset the 32-bit interval timer.
Wait for stopping.
Wait for at least one cycle of the count source until the timer is stopped.
TML32RES = 0
Release the 32-bit interval timer from the reset state.
Completion of the procedure for resetting
Change the operating mode of the 32-bit interval timer when operation resumes (see Figure 9 - 16).
Figure 9 - 20 Procedure for Starting Event Input from the ELCL
Procedure for starting event input from the ELCL
Start of the procedure for starting event input from the ELCL.
Select the 32- bit interval timer as the destination of output in ELOSELn .
Use the ELCL output signal select register n(ELOSELn ) to select the 32-bit interval timer as the destination of the output from the ELCL.
Set up ELOENCTL to enable the output.
Specify the operating mode of the event generation source .
Specify the operating mode of the 32- bit interval timer.
Start the operation of the event generation source .
Set the ELOENCTLn bit in the ELCL output signal enable register (ELOENCTL) to 1 (output is enabled).
See Figure 9 - 16. Use the CSEL012 to CSEL010 or ISEL 002 to ISEL000 bits in the ITLCSEL0 register or the CTRS01 and CTRS00 bits in the ITLCC0 register to select the event input from the ELCL for the count source or capture trigger as desired.
Completion of the procedure for starting event input from the ELCL
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CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
Figure 9 - 21 Procedure for Stopping Event Input from the ELCL
Procedure for stopping event input from the ELCL
Start of the procedure for stopping event input from the ELCL
Stop the operation of the event generation source .
Stop the 32 -bit interval timer.
See Figure 9 - 17.
Set up ELOENCTL to disable the output.
Clear the ELOENCTLn bit in the ELCL output signal enable register (ELOENCTL) to 0 (output is disabled).
Completion of the procedure for stopping event input from the ELCL
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CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
9.3.6 Points for caution when the 32-bit interval timer is to be used
(1) Clearing of the detection flags in the interval timer status register (ITLS0) Writing to the ITLS0 register is only possible by using an 8-bit memory manipulation instruction and writing 1 to individual bits is prohibited. To clear the detection flags (ITF0C, ITF03, ITF02, ITF01, and ITF00), use the 8-bit memory manipulation instruction to write 0 to the target bit and 1 to other bits. For example, write 00011101B to clear the ITF01 bit.
(2) Using multiple channels in 8-bit counter mode or 16-bit counter mode While the setting of any of the bits in the ITLS0 register is 1, the interrupt request signal (INTITL) remains high. Accordingly, neither the generation of a further interrupt request (INTITL) nor setting of the interrupt request flag (ITLIF) proceeds even if a compare match or capture completion is detected for an operating channel. To clear the detection flags (ITF0C, ITF03, ITF02, ITF01, and ITF00), clear the ITLS0 register for all channels to 00H. For clearing of the detection flags, see Figure 9 - 22.
The following describes the operation shown in Figure 9 - 22. When a compare match signal is detected in channel 1 while the setting of the ITLS0 register is 00H, the ITF01 flag is set and the interval detection interrupt signal (INTITL) is driven high. While the interval detection interrupt signal (INTITL) is being driven high, neither the generation of a further interrupt request (INTITL) nor setting of the interrupt request flag (ITLIF) proceeds even if a compare match or capture completion is detected for an operating channel. Accordingly, processing of the interval detection interrupt in response to the given detection flag proceeds until the ITLS0 register is cleared to 00H.
<1> Within the interval detection interrupt processing, check which detection flag in the ITLS0 register is set. The ITF01 flag is set in the figure.
<2> Clear the ITF01 flag that had been set in step 1. <3> Check whether the setting of the ITLS0 register is 00H. If not, check which flag in the ITLS0 register is set.
The ITF00 flag is set in the figure. <4> Execute the processing in response to the ITF01 flag being set. <5> Since the setting of the ITLS0 register was not 00H in step 3, the interval detection interrupt processing continues.
Clear the ITF00 flag that had been set in step 3. <6> Check whether the setting of the ITLS0 register is 00H. If it is 00H, a further interrupt request signal (INTITL) can be
generated and the interrupt request flag can be set. <7> Execute the interrupt processing in response to the ITF00 flag having been set. <8> Since the setting of the ITLS0 register is now 00H, processing for the interval detection interrupts ends.
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RL78/G23 Figure 9 - 22 Example of Clearing the Detection Flags
CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
ITF01 flag
ITF00 flag
Interval detection interrupt request signal (INTITL)
Processing in response to the interval detection interrupt
<1> Checking of ITLS0 <3> Checking of ITLS0
(ITF01 being set is
(ITF00 being set is
detected)
detected)
<2> Clearing of ITF01
<4> Processing in response to ITF01 being set
<6> Checking of ITLS0 (ITLS0 is 00H)
<5> Clearing of ITF00
<7> Processing in response to ITF00 being set
<8> End of processing for the interval detection interrupt
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CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER (PCLBUZ)
CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER (PCLBUZ)
Caution Most of the following descriptions in this chapter use the 64-pin products as an example.
10.1
Functions of Clock Output/Buzzer Output Controller
In clock output, the controller outputs a clock signal for supply to peripheral ICs. In buzzer output, the controller outputs a square wave at the buzzer frequency. This module has two output channels (PCLBUZn) and each of them can be specified to output a clock or buzzer signal. Switching of the output is handled by the clock output select registers n (CKSn: n = 0, 1). Figure 10 - 1 shows the block diagram of clock output/buzzer output controller.
Caution
Output of the low-speed peripheral clock (fSXP) from the PCLBUZn pin is not possible when the following conditions are both satisfied: - The setting of the RTCLPC bit in the subsystem clock supply mode control register (OSMC) is 1. - Operation is in the HALT mode with the subsystem clock (fSUB) selected as the CPU clock.
Remark n = 0, 1
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CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER (PCLBUZ)
Figure 10 - 1 Block Diagram of Clock Output/Buzzer Output Controller
PCLOE1 0
Internal bus
Clock output select register 1 (CKS1)
0
0 CSEL1 CCS12 CCS11 CCS10
fMAIN fSXP
Prescaler
5
3 fMAIN/211 to fMAIN/213
fMAIN to fMAIN/24 fSXP to fSXP/27
fMAIN/211 to fMAIN/213
88 Prescaler
fMAIN to fMAIN/24 fSXP to fSXP/27
Selector
Selector
PCLOE1
Clock/buzzer controller
PCLBUZ1Note/INTP7/P141
Output latch (P141)
PM141
Clock/buzzer controller
PCLBUZ0Note/INTP6/P140
PCLOE0
Output latch (P140)
PM140
Note
PCLOE0 0
0
0 CSEL0 CCS02 CCS01 CCS00
Clock output select register 0 (CKS0)
Internal bus
For output frequencies available from PCLBUZ0 and PCLBUZ1, refer to 37.4 AC Characteristics.
Remark The clock output/buzzer output pins in above diagram show the information of 64- to 128-pin products with PIOR3 = 0 and PIOR4 = 0.
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CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER (PCLBUZ)
10.2
Configuration of Clock Output/Buzzer Output Controller
The clock output/buzzer output controller includes the following hardware.
Table 10 - 1 Configuration of Clock Output/Buzzer Output Controller
Item
Configuration
Control registers
Clock output select registers n (CKSn) Port mode registers 1, 3, 5, 14 (PM1, PM3, PM5, PM14) Port registers 1, 3, 5, 14 (P1, P3, P5, P14) Port mode control T register 3 (PMCT3) Port mode control E register 1 (PMCE1)
10.3
Registers to Control the Clock Output/Buzzer Output Controller
The following registers are used to control the clock output/buzzer output controller.
· Clock output select registers n (CKSn) · Port mode registers (PMxx) · Port registers (Pxx) · Port mode control T registers (PMCTxx) · Port mode control E registers (PMCEx)
10.3.1 Clock output select registers n (CKSn)
These registers enable or disable the output from the clock or buzzer frequency output pin (PCLBUZn), and set the output clock. Use the CKSn register to select the clock to be output from the PCLBUZn pin. The CKSn registers are set by a 1-bit or 8-bit memory manipulation instruction. The value of each CKSn register is 00H following a reset.
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CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER (PCLBUZ)
Figure 10 - 2 Format of Clock Output Select Register n (CKSn)
Address: After reset: R/W:
FFFA5H (CKS0), FFFA6H(CKS1) 00H R/W
Symbol
<7>
6
5
4
3
2
1
0
CKSn PCLOEn
0
0
0
CSELn
CCSn2
CCSn1
CCSn0
PCLOEn 0 1
PCLBUZn pin output enable/disable specification Output disabled (default) Output enabled
CSELn CCSn2 CCSn1 CCSn0
PCLBUZn pin output clock selection
fMAIN = 5 MHz
fMAIN = 10 MHz
fMAIN = 20 MHz
fMAIN = 32 MHz
0
0
0
0
fMAIN
5 MHzNote 10 MHzNote Setting
Setting
prohibited prohibited
0
0
0
1
fMAIN/2
2.5 MHz 5 MHzNote 10 MHzNote 16 MHzNote
0
0
1
0
fMAIN/22 1.25 MHz 2.5 MHz 5 MHzNote 8 MHzNote
0
0
1
1
fMAIN/23
625 kHz 1.25 MHz 2.5 MHz
4 MHz
0
1
0
0
fMAIN/24 312.5 kHz 625 kHz 1.25 MHz
2 MHz
0
1
0
1
fMAIN/211 2.44 kHz 4.88 kHz 9.77 kHz 15.63 kHz
0
1
1
0
fMAIN/212 1.22 kHz 2.44 kHz 4.88 kHz 7.81 kHz
0
1
1
1
fMAIN/213
610 Hz
1.22 kHz 2.44 kHz 3.91 kHz
1
0
0
0
fSXP
32.768 kHz
1
0
0
1
fSXP/2
16.384 kHz
1
0
1
0
fSXP/22
8.192 kHz
1
0
1
1
fSXP/23
4.096 kHz
1
1
0
0
fSXP/24
2.048 kHz
1
1
0
1
fSXP/25
1.024 kHz
1
1
1
0
fSXP/26
512 Hz
1
1
1
1
fSXP/27
256 Hz
Note
The selectable output clock frequency depends on the power supply voltage (VDD). See 37.4 AC
Characteristics for details.
Caution 1. Change the output clock after disabling clock output (PCLOEn = 0).
Caution 2. To shift to STOP mode when the main system clock is selected (CSELn = 0), set PCLOEn = 0 before
executing the STOP instruction. When the subsystem clock is selected (CSELn = 1), PCLOEn = 1 can
be set because the clock can be output while the RTCLPC bit of the subsystem clock supply mode
control (OSMC) register is set to 0 and moreover while STOP mode is set.
Caution 3. It is not possible to output the low-speed peripheral clock (fSXP) from the PCLBUZn pin while the
RTCLPC bit of the subsystem clock supply mode control register (OSMC) is set to 1 and moreover
while HALT mode is set with the subsystem clock (fSUB) selected as CPU clock.
Remark 1. n = 0, 1
Remark 2. fMAIN: Main system clock frequency
fSUB: Subsystem clock frequency
fSXP: Low-speed peripheral clock frequency
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CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER (PCLBUZ)
10.3.2 Registers controlling port functions of pins to be used for clock or buzzer output
Using a port pin for clock or buzzer output requires setting of the following registers that control the port functions multiplexed on the target pin. - Port mode registers (PMxx) - Port registers (Pxx) - Port mode control T registers (PMCTxx) - Port mode control E registers (PMCEx) For details, see 4.3.1 Port mode registers (PMxx), 4.3.2 Port registers (Pxx), 4.3.8 Port mode control T registers (PMCTxx), and 4.3.9 Port mode control E registers (PMCEx).
Specifically, using a port pin with a multiplexed clock or buzzer output function (e.g. P140/INTP6/PCLBUZ0, P141/INTP7/PCLBUZ1) for clock or buzzer output, requires setting the corresponding bits in the port mode register (PMxx), port register (Pxx), port mode control T register (PMCTxx), and port mode control E register (PMCEx) to 0.
Example:
When P140/INTP6/PCLBUZ0 is to be used for clock or buzzer output Set the PM140 bit of port mode register 14 to 0. Set the P140 bit of port register 14 to 0.
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CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER (PCLBUZ)
10.4
Operations of the Clock Output/Buzzer Output Controller
This module has two output channels (PCLBUZn) and each of them can be specified to output a clock or buzzer signal. The PCLBUZ0 and PCLBUZ1 pins respectively output the clock specified by the clock output select registers 0 and 1 (CKS0 and CKS1).
10.4.1 Operation of Output Pins
Follow the steps below to enable output from a PCLBUZn pin.
1. Set the corresponding bits of the following registers to 0 to select the port pin for use as a PCLBUZn pin. - Port mode register (PMxx) - Port register (Pxx) - Port mode control T register (PMCTxx) - Port mode control E register (PMCEx)
2. Select the output frequency with bits 0 to 3 (CCSn0 to CCSn2, CSELn) of the clock output select register (CKSn) for a PCLBUZn pin (output is still disabled).
3. Set bit 7 (PCLOEn) of the CKSn register to 1 to enable clock/buzzer output.
Remark 1. The controller used for the clock output starts or stops output one clock cycle after that in which the PCLOEn bit was set to enable or disable the output, respectively. Pulses that are narrower than the specified width are not output at those times. Figure 10 - 3 shows the relationship between the setting of the PCLOEn bit and the timing of clock output.
Remark 2. n = 0, 1
Figure 10 - 3 Timing of the Clock Output from a PCLBUZn Pin
PCLOEn
One clock cycle elapses.
Clock output
N. arrower than specified pulses are not output.
10.5
Point for Caution when the Clock Output/Buzzer Output Controller is to be Used
When the main system clock is selected for the PCLBUZn output (CSELn = 0), if STOP mode is entered within 1.5 clock cycles of output from a PCLBUZn pin having been disabled (PCLOEn = 0), the width of a PCLBUZn pulse being output at that time becomes shorter.
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CHAPTER 11 WATCHDOG TIMER (WDT)
CHAPTER 11 WATCHDOG TIMER (WDT)
11.1
Functions of Watchdog Timer
The counting operation of the watchdog timer is set by the option byte (000C0H). The watchdog timer operates with the low-speed on-chip oscillator clock (fIL) divided by 2 (1/2 fIL). The watchdog timer is used to detect program malfunctions. If a malfunction is detected, an internal reset signal is generated. Any among the following cases is considered a program malfunction.
· The watchdog timer counter overflows · A 1-bit manipulation instruction is used to write to the watchdog timer enable register (WDTE). · A value other than ACH is written to the WDTE register. · Writing to the WDTE register proceeds while the window is closed.
When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1. For details of the RESF register, see CHAPTER 24 RESET FUNCTION. When 75% of the overflow time + 1/4 fIL is reached, an interval interrupt can be generated.
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CHAPTER 11 WATCHDOG TIMER (WDT)
11.2
Configuration of Watchdog Timer
The watchdog timer includes the following hardware.
Table 11 - 1 Configuration of Watchdog Timer
Item
Configuration
Counter
Internal counter (17 bits)
Control register
Watchdog timer enable register (WDTE)
How the counter operation is controlled, overflow time, window open period, and interval interrupt are set by the option byte.
Table 11 - 2 Setting of Option Bytes and Watchdog Timer
Setting of Watchdog Timer Watchdog timer interval interrupt Window open period Controlling counter operation of watchdog timer Overflow time of watchdog timer Controlling counter operation of watchdog timer (in HALT/STOP mode)
Remark For the option byte, see CHAPTER 32 OPTION BYTES.
Option Byte (000C0H) Bit 7 (WDTINT) Bits 6 and 5 (WINDOW1, WINDOW0) Bit 4 (WDTON) Bits 3 to 1 (WDCS2 to WDCS0) Bit 0 (WDSTBYON)
Figure 11 - 1 Block Diagram of Watchdog Timer
WDTINT of option byte (000C0H)
WDCS2 to WDCS0 of option byte (000C0H)
Interval time controller (Count value overflow time
× 3/4 + 1/4 fIL)
Interval time interrupt
Clock 1/2 fIL Internal fIL/27 to fIL/217
Overflow signal
fIL
input
counter
Selector
controller
(17 bits)
WINDOW1 and WINDOW0 of option
byte (000C0H)
WDTON of option byte (000C0H)
Count clear signal
Window size check
Window size decision signal
Detection of writing ACH to WDTE
Watchdog timer enable register (WDTE)
Write detector to WDTE except ACH
Reset Output controller
Internal reset signal
Remark fIL: Low-speed on-chip oscillator clock
Internal bus
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CHAPTER 11 WATCHDOG TIMER (WDT)
11.3
Register to Control the Watchdog Timer
The following register is used to control the watchdog timer.
· Watchdog timer enable register (WDTE)
11.3.1 Watchdog timer enable register (WDTE)
Writing ACH to the WDTE register clears the watchdog timer counter and starts counting again. This register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 9AH or 1AHNote.
Figure 11 - 2 Format of Watchdog Timer Enable Register (WDTE)
Address: After reset: R/W:
FFFABH 9AH/1AHNote R/W
Symbol
7
WDTE
Note
6
5
4
3
2
1
0
The WDTE register reset value differs depending on the WDTON bit setting value of the option byte (000C0H). To operate watchdog timer, set the WDTON bit to 1.
WDTON Bit Setting Value 0 (Watchdog timer counting disabled) 1 (Watchdog timer counting enabled)
WDTE Register Reset Value 1AH 9AH
Caution 1. If a value other than ACH is written to the WDTE register, an internal reset signal is generated. Caution 2. If a 1-bit memory manipulation instruction is executed for the WDTE register, an internal reset signal is
generated. Caution 3. The value read from the WDTE register is 9AH/1AH (this differs from the written value (ACH)).
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11.4
Operation of Watchdog Timer
CHAPTER 11 WATCHDOG TIMER (WDT)
11.4.1 Controlling operation of watchdog timer
1. When the watchdog timer is used, its operation is specified by the option byte (000C0H).
· Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (000C0H) to 1 (the counter starts operating after a reset release) (for details, see CHAPTER 32 OPTION BYTES).
WDTON
Watchdog Timer Counter
0
Counter operation disabled (counting stopped after reset)
1
Counter operation enabled (counting started after reset)
· Set the time at which the counter is to overflow by using bits 3 to 1 (WDCS2 to WDCS0) of an option byte (000C0H). For details, see 11.4.2 and CHAPTER 32 OPTION BYTES.
· Set a window open period by using bits 6 and 5 (WINDOW1 and WINDOW0) of the option byte (000C0H) (for details, see 11.4.3 and CHAPTER 32 OPTION BYTES).
2. After a reset release, the watchdog timer starts counting. 3. By writing ACH to the watchdog timer enable register (WDTE) after the watchdog timer starts counting and before
the overflow time set by the option byte, the watchdog timer is cleared and starts counting again. 4. After that, writing to the WDTE register the second and subsequent times must proceed while the window is open.
If the WDTE register is written during a window close period, an internal reset signal is generated. If the time at which an overflow is to occur elapses without ACH having been written to the WDTE register, an internal reset signal is generated. 5. An internal reset signal is also generated in the following cases.
· If a 1-bit manipulation instruction is executed on the WDTE register · If data other than ACH is written to the WDTE register
Caution 1.
Caution 2. Caution 3. Caution 4.
When data is written to the watchdog timer enable register (WDTE) for the first time after reset release, the watchdog timer is cleared in any timing regardless of the window open time, as long as the register is written before the overflow time, and the watchdog timer starts counting again. After ACH is written to the WDTE register, an error of up to 4 cycles of the clock at fIL may occur before the watchdog timer is cleared. The watchdog timer can be cleared immediately before the counter value overflows. The operation of the watchdog timer in the HALT, STOP, and SNOOZE modes differs as follows depending on the set value of bit 0 (WDSTBYON) of the option byte (000C0H).
WDSTBYON = 0
WDSTBYON = 1
In HALT mode
Watchdog timer operation stops.
Watchdog timer operation continues.
In STOP mode
In SNOOZE mode
If WDSTBYON = 0, the watchdog timer resumes counting after the HALT or STOP mode is released. At this time, the counter is cleared to 0 and counting starts. When operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts operating after the oscillation stabilization time has elapsed. Therefore, if the period between the STOP mode release and the watchdog timer overflow is short, an overflow occurs during the oscillation stabilization time, causing a reset. Consequently, set the overflow time in consideration of the oscillation stabilization time when operating with the X1 oscillation clock and when the watchdog timer is to be cleared after the STOP mode release by an interval interrupt.
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CHAPTER 11 WATCHDOG TIMER (WDT)
11.4.2 Setting overflow time of watchdog timer
Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H). If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer starts counting again by writing ACH to the watchdog timer enable register (WDTE) during the window open period before the overflow time. The following overflow times can be set.
Table 11 - 3 Setting of Overflow Time of Watchdog Timer
WDCS2
WDCS1
WDCS0
Overflow Time of Watchdog Timer (fIL = 37.683 kHz (max.))
0
0
0
27/fIL (3.39 ms)
0
0
1
28/fIL (6.79 ms)
0
1
0
29/fIL (13.58 ms)
0
1
1
210/fIL (27.17 ms)
1
0
0
212/fIL (108.69 ms)
1
0
1
214/fIL (434.78 ms)Note
1
1
0
215/fIL (869.56 ms)Note
1
1
1
217/fIL (3478.26 ms)Note
Note
Using the watchdog timer under the following conditions may lead to the generation of an interval interrupt (INTWDTI) after one cycle of the watchdog timer clock once the watchdog timer counter has been cleared. Usage conditions that may lead to the generation of an interval interrupt: · the watchdog timer interval interrupt is in use, and · ACH is written to the WDTE register (FFFABH) when the watchdog timer counter has reached or exceeded 75% of the
overflow time.
This interrupt can be masked by clearing the watchdog timer counter through steps 1 to 5 below. 1. Set the WDTIMK bit of the interrupt mask flag register 0 (MK0L) to 1 before clearing the watchdog timer counter. 2. Clear the watchdog timer counter. 3. Wait for at least 80 µs. 4. Clear the WDTIIF bit of the interrupt request flag register 0 (IF0L) to 0. 5. Clear the WDTIMK bit of the interrupt mask flag register 0 (MK0L) to 0.
Remark fIL: Low-speed on-chip oscillator clock frequency
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CHAPTER 11 WATCHDOG TIMER (WDT)
11.4.3 Setting window open period of watchdog timer
Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte (000C0H). The outline of the window is as follows.
· If ACH is written to the watchdog timer enable register (WDTE) during the window open period, the watchdog timer is cleared and starts counting again.
· Even if ACH is written to the WDTE register during the window close period, an abnormality is detected and an internal reset signal is generated.
Example: If the window open period is 50%
Counting starts
Window close period (50%)
Overflow time
Window open period (50%)
Internal reset signal is generated if ACH is written to WDTE.
Counting starts again when ACH is written to WDTE.
Caution
When data is written to the WDTE register for the first time after reset release, the watchdog timer is cleared in any timing regardless of the window open time, as long as the register is written before the overflow time, and the watchdog timer starts counting again.
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CHAPTER 11 WATCHDOG TIMER (WDT)
The window open period can be set is as follows.
Table 11 - 4 Setting Window Open Period of Watchdog Timer
WINDOW1
WINDOW0
Window Open Period of Watchdog Timer
0
1
50%
1
1
100%
Others
Setting prohibited
Remark
If the overflow time is set to 210/fIL, the times over which the window is open and closed are as follows.
Setting of Window Open Period
50%
100%
Window close time
0 to 18.38 ms
None
Window open time
18.38 to 27.17 ms
0 to 27.17 ms
<When window open period is 50%>
· Overflow time: 210/fIL (max.) = 29/18.842 kHz = 27.17 ms
· Window close time: 0 to 210/fIL (min.) × (1 - 0.5) = 0 to 210/13.926 kHz × 0.5 = 0 to 18.38 ms
· Window open time: 210/fIL (min.) × (1 - 0.5) to 210/fIL (max.) = 29/13.926 kHz × 0.5 to 29/18.842 kHz = 18.38 to 27.17 ms
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CHAPTER 11 WATCHDOG TIMER (WDT)
11.4.4 Setting watchdog timer interval interrupt
Depending on the setting of bit 7 (WDTINT) of an option byte (000C0H), an interval interrupt (INTWDTI) can be generated when 75% of the overflow time + 1/4 fIL is reached.
Table 11 - 5 Setting of Watchdog Timer Interval Interrupt
WDTINT
Use of Watchdog Timer Interval Interrupt
0
Interval interrupt is not used.
1
Interval interrupt is generated when 75% of the overflow time + 1/4 fIL is reached.
Caution
When operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts operating after the oscillation stabilization time has elapsed. Therefore, if the period between the STOP mode release and the watchdog timer overflow is short, an overflow occurs during the oscillation stabilization time, causing a reset. Consequently, set the overflow time in consideration of the oscillation stabilization time when operating with the X1 oscillation clock and when the watchdog timer is to be cleared after the STOP mode release by an interval interrupt.
Remark
The watchdog timer continues counting even after INTWDTI is generated (until ACH is written to the watchdog timer enable register (WDTE)). If ACH is not written to the WDTE register before the overflow time, an internal reset signal is generated.
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CHAPTER 12 A/D CONVERTER (ADC)
CHAPTER 12 A/D CONVERTER (ADC)
The number of analog input channels of the A/D converter differs, depending on the product.
30- and 32-pin
36-pin
40-pin
44- and 48-pin
52- and 64-pin
80-pin
100-pin
128-pin
Number of the analog input channels
8 (ANI0 to ANI3, ANI16 to ANI19)
8 (ANI0 to ANI5, ANI18, ANI19)
9 (ANI0 to ANI6, ANI18, ANI19)
10 (ANI0 to ANI7, ANI18, ANI19)
12 (ANI0 to ANI7, ANI16 to ANI19)
17 (ANI0 to ANI11, ANI16 to ANI20)
20 (ANI0 to ANI14, ANI16 to ANI20)
26 (ANI0 to ANI14, ANI16 to ANI26)
12.1
Function of A/D Converter
The A/D converter is used to convert analog input signals into digital values, and is configured to control up to 26 channels of A/D converter analog inputs (ANI0 to ANI14 and ANI16 to ANI26). 12-bit, 10-bit, or 8-bit resolution can be selected by the ADTYP1 and ADTYP0 bits of the A/D converter mode register 2 (ADM2). The A/D converter has the following function.
· 12-bit/10-bit/8-bit resolution A/D conversion 12-bit, 10-bit, or 8-bit resolution A/D conversion is carried out repeatedly for one analog input channel selected from ANI0 to ANI14 and ANI16 to ANI26. Each time an A/D conversion operation ends, an interrupt request signal (INTAD) is generated (when in the select mode).
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CHAPTER 12 A/D CONVERTER (ADC)
Various A/D conversion modes can be specified by using the mode combinations below.
Trigger mode
Software trigger no-wait mode
Conversion is started by setting the ADCE bit to 1 by software, and then setting ADCS to 1 after the A/D power supply stabilization wait time has passed.
Software trigger wait mode
The power is turned on by setting the ADCS bit to 1 by software while A/D conversion is stopped and conversion is then started automatically after the A/D power supply stabilization wait time has passed.
Hardware trigger no-wait Conversion is started by detecting a hardware trigger. mode
Hardware trigger wait mode
The power to the A/D converter is turned on by detecting a hardware trigger while the A/D converter is off and in the conversion standby state, and conversion is then started automatically after the stabilization wait time passes. When using the SNOOZE mode function, specify the hardware trigger wait mode.
Channel selection mode
Select mode
A/D conversion is performed on the analog input of one selected channel.
Scan mode
A/D conversion is performed on the analog input of four channels in order. Four consecutive channels can be selected from ANI0 to ANI14 as analog input channels.
Conversion operation mode One-shot conversion mode
A/D conversion is performed on the selected channel once.
Sequential conversion mode
A/D conversion is sequentially performed on the selected channels until it is stopped by software.
Operation voltage modeNote Sampling clock cycles
Normal 1 Normal 2 Low voltage 1
43 fAD 160 fAD 53 fAD
Set the number of sampling clock cycles so that the sampling capacitor is sufficiently charged according to the output impedance of the analog input source.
Low voltage 2
80 fAD
Note
The operation mode that can be selected differs depending on the analog input channel, VDD voltage, AVREFP voltage, trigger mode, and fCLK. See Table 12 - 3 A/D Conversion Time Selection (1/8) for details.
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RL78/G23 Figure 12 - 1 Block Diagram of A/D Converter
Note
For details about the internal reference voltage, see CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
Remark 1. Analog input pins in this figure are for a 128-pin product. Remark 2. n = 0 to 3
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Internal bus
Port mode control register
PMCAxx PMCTxx PMCEx
A/D test register (ADTES)
ADTES1 ADTES0 2
Conversion result comparison upper limit setting register (ADUL)
Conversion result comparison lower limit setting register (ADLL)
ANI0/AVREFP/P20 ANI1/AVREFM/P21 ANI2/P22/ANO0/TS20 ANI3/P23/ANO1/IVREF0/TS21
ANI4/P24/TS22 ANI5/P25/TS23 ANI6/P26/TS24 ANI7/P27/TS25 ANI8/P150/TS30 ANI9/P151/TS31 ANI10/P152/TS32 ANI11/P153/TS33 ANI12/P154/TS34 ANI13/P155/TS35
ANI14/P156
PMCAxx PMCTxx PMCEx
ANI16/P03/TS29/SI10/RxD1/SDA10 ANI17/P02/TS28/SO10/TxD1 ANI18/P147/IVCMP0 ANI19/P120/IVCMP1 ANI20/P100 ANI21/P37 ANI22/P36 ANI23/P35 ANI24/P117 ANI25/P116 ANI26/P115
Temperature sensor
Internal reference voltage Note
6
Digital port control
Digital port control
Selector
2
Sample & hold circuit
A/D voltage comparator
VSS
Successive approximation register
(SAR)
Controller
4 ADREFP1ADREFP0ADREFM ADRCK AWC ADTYP1 ADTYP0
7
ADREFP1 and ADREFP0 bits
Selector
ADCS bit
AVREFP/ANI0/P20 Internal reference voltage Note
VDD
Comparison Voltage generator
ADREFM bit
Selector
AVREFM/ANI1/P21
VSS
Timer trigger signal (INTRTC) Timer trigger signal (INTIT) Timer trigger signal (INTTM01) Event input from ELCL
A/D conversion result upper
limit/lower limit comparator
INTAD
6
CHAPTER 12 A/D CONVERTER (ADC)
ADISS ADS4 ADS3 ADS2 ADS1 ADS0
Analog input channel specification register (ADS)
ADTMD1 ADTMD0 ADSCM ADLSP ADTRS2 ADTRS1 ADTRS0 ADCS ADMD FR2 FR1 FR0 LV1 LV0 ADCE
A/D conversion result
registers (ADCRn, ADCRnH)
A/D converter mode register 2 (ADM2)
A/D converter mode register 1 (ADM1)
A/D converter mode register 0 (ADM0)
Internal bus
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CHAPTER 12 A/D CONVERTER (ADC)
12.2
Configuration of A/D Converter
The A/D converter includes the following hardware.
(1) ANI0 to ANI14 and ANI16 to ANI26 pins These are the analog input pins of the 26 channels of the A/D converter. They input analog signals to be converted into digital signals. Pins other than the one selected as the analog input pin can be used as I/O port pins.
(2) Sample & hold circuit The sample & hold circuit samples each of the analog input voltages sequentially sent from the input circuit, and sends them to the A/D voltage comparator. This circuit also holds the sampled analog input voltage during A/D conversion.
(3) A/D voltage comparator This A/D voltage comparator compares the voltage generated from the voltage tap of the comparison voltage generator with the analog input voltage. If the analog input voltage is found to be greater than the reference voltage (1/2 AVREF) as a result of the comparison, the most significant bit (MSB) of the successive approximation register (SAR) is set. If the analog input voltage is less than the reference voltage (1/2 AVREF), the MSB of the SAR is reset. After that, bit 10 of the SAR register is automatically set, and the next comparison is made. The voltage tap of the comparison voltage generator is selected by the value of bit 11, to which the result has already been set.
Bit 11 = 0: (1/4 AVREF) Bit 11 = 1: (3/4 AVREF)
The voltage tap of the comparison voltage generator and the analog input voltage are compared and bit 10 of the SAR register is manipulated according to the result of the comparison.
Analog input voltage Voltage tap of comparison voltage generator: Bit 10 = 1 Analog input voltage Voltage tap of comparison voltage generator: Bit 10 = 0
Comparison is continued like this to bit 0 of the SAR register.
Remark
AVREF: The + side reference voltage of the A/D converter. This can be selected from AVREFP, the internal reference voltageNote, and VDD.
(4) Comparison voltage generator The comparison voltage generator generates the voltage to be compared with the input from an analog input pin.
Note
For details about the internal reference voltage, see CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
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(5) Successive approximation register (SAR) The SAR is used to set voltage tap data whose values from the comparison voltage generator match the voltage values of the analog input pins, one bit at a time starting from the most significant bit (MSB). If data is set in the SAR register all the way to the least significant bit (LSB) (end of A/D conversion), the contents of the SAR register (conversion results) are held in the A/D conversion result register (ADCRn). When all the specified A/D conversion operations have ended, an A/D conversion end interrupt request signal (INTAD) is generated.
(6) 12-bit/10-bit A/D conversion result register (ADCRn) Each time A/D conversion ends, the conversion result is loaded from the successive approximation register, and then operation is performed as follows: When this register is used to specify 12-bit resolution, it holds the A/D conversion result in its lower 12 bits (the higher 4 bits are fixed to 0). When this register is used to specify 10-bit resolution, it holds the A/D conversion result in its higher 10 bits (the lower 6 bits are fixed to 0).
(7) 8-bit A/D conversion result register (ADCRnH) The A/D conversion result is loaded from the successive approximation register to this register each time A/D conversion is completed, and the ADCRnH register holds the higher 8 bits of the A/D conversion result.
(8) Controller This circuit controls the conversion time of an analog input signal that is to be converted into a digital signal, as well as starting and stopping of the conversion operation. When A/D conversion has been completed, this controller generates INTAD through the A/D conversion result upper limit/lower limit comparator.
(9) AVREFP pin This pin inputs an external reference voltage (AVREFP). If using AVREFP as the + side reference voltage of the A/D converter, set the ADREFP1 and ADREFP0 bits of A/D converter mode register 2 (ADM2) to 0 and 1, respectively. The analog signals input to ANI2 to ANI14 and ANI16 to ANI26 are converted to digital signals based on the voltage applied between AVREFP and the side reference voltage (AVREFM/VSS). In addition to AVREFP, it is possible to select VDD or the internal reference voltage as the + side reference voltage of the A/D converter.
Caution
For details about the internal reference voltage, see CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
(10) AVREFM pin This pin inputs an external reference voltage (AVREFM). To use AVREFM as the side reference voltage of the A/D converter, set the ADREFM bit of the ADM2 register to 1. In addition to AVREFM, it is possible to select VSS as the side reference voltage of the A/D converter.
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12.3
Registers to Control the A/D Converter
The following registers are used to control the A/D converter.
· Peripheral enable register 0 (PER0) · Peripheral reset control register 0 (PRR0) · A/D converter mode register 0 (ADM0) · A/D converter mode register 1 (ADM1) · A/D converter mode register 2 (ADM2) · 12-bit/10-bit A/D conversion result register (ADCRn) · 8-bit A/D conversion result register (ADCRnH) · Analog input channel specification register (ADS) · Conversion result comparison upper limit setting register (ADUL) · Conversion result comparison lower limit setting register (ADLL) · A/D test register (ADTES) · Port mode control A registers (PMCAxx) · Port mode control T registers (PMCTxx) · Port mode control E registers (PMCEx) · Port mode registers (PMxx)
CHAPTER 12 A/D CONVERTER (ADC)
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CHAPTER 12 A/D CONVERTER (ADC)
12.3.1 Peripheral enable register 0 (PER0)
The PER0 register is used to enable or disable the supply of a clock signal to various on-chip peripheral modules. Clock supply to an on-chip peripheral module that is not to be used can be stopped to decrease power consumption and noise. If the A/D converter is to be used, be sure to set bit 5 (ADCEN) of this register to 1. The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 12 - 2 Format of Peripheral Enable Register 0 (PER0)
Address: After reset: R/W:
F00F0H 00H R/W
Symbol
<7>
PER0 RTCWEN
<6>
IICA1EN
Note 1
<5> ADCEN
<4> IICA0EN
<3> SAU1EN
<2> SAU0EN
<1>
TAU1EN
Note 2
<0> TAU0EN
ADCEN
Control of supply of an input clock to the A/D converter
0
Stops supply of an input clock.
· The SFRs used by the A/D converter cannot be written.
· When an SFR used by the A/D converter is read, the value returned is 00H or 0000H.
1
Enables supply of an input clock.
· The SFRs used by the A/D converter can be read and written.
Note 1. Note 2.
This bit is only present in the 44- to 128-pin products. This bit is only present in the 80- to 128-pin products.
Caution 1. When setting the A/D converter, make sure that the setting of the ADCEN bit is 1 before setting the following registers. If ADCEN = 0, the value of each register which controls the A/D converter is 00H and writing to any of those registers is ignored (except for port mode registers 0, 2, 3, 10, 11, 12, 14, and 15 (PM0, PM2, PM3, PM10, PM11, PM12, PM14, and PM15), port mode control A registers 0, 2, 3, 10, 11, 12, 14, and 15 (PMCA0, PMCA2, PMCA3, PMCA10, PMCA11, PMCA12, PMCA14, and PMCA15), port mode control T registers 0, 2, and 15 (PMCT0, PMCT2, and PMCT15), and port mode control E register 0 (PMCE0)). · A/D converter mode register 0 (ADM0) · A/D converter mode register 1 (ADM1) · A/D converter mode register 2 (ADM2) · 12-bit/10-bit A/D conversion result register (ADCRn) · 8-bit A/D conversion result register (ADCRnH) · Analog input channel specification register (ADS) · Conversion result comparison upper limit setting register (ADUL) · Conversion result comparison lower limit setting register (ADLL) · A/D test register (ADTES).
Caution 2. Be sure to clear the following bits to 0. For the presence of bits for each product, see CHAPTER 6 CLOCK GENERATOR. Bits 1 and 6 in the 30-, 32-, 36-, and 40-pin products Bit 1 in the 44-, 48-, 52-, and 64-pin products
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CHAPTER 12 A/D CONVERTER (ADC)
12.3.2 Peripheral reset control register 0 (PRR0)
The PRR0 register is used to control resetting of the on-chip peripheral modules. Each bit in this register controls resetting and release from the reset state of the corresponding on-chip peripheral module. To place the A/D converter in the reset state, be sure to set bit 5 (ADCRES) of this register to 1. The PRR0 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 12 - 3 Format of Peripheral Reset Control Register 0 (PRR0)
Address: After reset: R/W:
F00F1H 00H R/W
Symbol
7
PRR0
0
<6>
<5>
<4>
<3>
<2>
<1>
<0>
IICA1RES ADCRES IICA0RES SAU1RES SAU0RES TAU1RES TAU0RES
ADCRES
Control resetting of the A/D converter
0
The A/D converter is released from the reset state.
1
The A/D converter is in the reset state.
· The SFRs for use with the A/D converter are initialized.
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CHAPTER 12 A/D CONVERTER (ADC)
12.3.3 A/D converter mode register 0 (ADM0)
This register sets the time for converting analog input to digital data, and starts and stops conversion. The ADM0 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 12 - 4 Format of A/D Converter Mode Register 0 (ADM0)
Address: After reset: R/W:
FFF30H 00H R/W
Symbol ADM0
<7> ADCS
6 ADMD
5 FR2Note 1
4 FR1Note 1
3 FR0Note 1
2 LV1Note 1
1 LV0Note 1
<0> ADCE
ADCS 0
1
A/D conversion operation control
Stops conversion operation
[When read]
Conversion is stopped or in standby.
Enables conversion operation
[When read]
While in the software trigger no wait mode: Conversion is enabled. While in the software trigger wait mode: A/D power supply stabilization wait time +
conversion While in the hardware trigger no wait mode: Conversion is enabled. While in the hardware trigger wait mode: A/D power supply stabilization wait time +
conversion
ADMD 0 1
Select mode Scan mode
Specification of the A/D conversion channel selection mode
ADCE
A/D voltage comparator operation controlNote 2
0
Stops A/D voltage comparator operation
1
Enables A/D voltage comparator operation
Note 1. Note 2.
For details of the FR2 to FR0, LV1, LV0 bits, and A/D conversion, see Table 12 - 3 A/D Conversion Time Selection (1/8). While in the software trigger no-wait mode or hardware trigger no-wait mode, the operation of the A/D voltage comparator is controlled by the ADCS and ADCE bits, and it takes 1 µs + 2 cycles of the conversion clock (fAD) from the start of operation for the operation to stabilize. Therefore, immediately after the ADCS bit is set to 1 after at least 1 µs + 2 cycles of the conversion clock (fAD) have elapsed from the time ADCE bit is set to 1, the conversion result becomes valid. When ADCS is set to 1 while ADCE = 0, A/D conversion starts after the stabilization wait time has passed. If ADCS is set before at least 1 µs + 2 cycles of the conversion clock (fAD) have elapsed, ignore data of the first conversion.
Caution 1. Change the ADMD, FR2 to FR0, LV1, and LV0 bits while conversion is stopped (ADCS = 0, ADCE = 0). Caution 2. Setting change from ADCS = 1 and ADCE = 1 to ADCS = 1 and ADCE = 0 is prohibited. Caution 3. Do not change the ADCS and ADCE bits from 0 to 1 at the same time by using an 8-bit manipulation
instruction. Be sure to follow the procedure described in 12.7 A/D Converter Setup Flowchart.
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CHAPTER 12 A/D CONVERTER (ADC)
Table 12 - 1 Settings of ADCS and ADCE Bits
ADCS
ADCE
A/D Conversion Operation
0
0
Conversion stopped state
0
1
Conversion standby state
1
0
Conversion operation state (software trigger wait mode) or conversion stopped state
1
1
Conversion operation state (other than software trigger wait mode)
Table 12 - 2 Conditions for Setting and Clearing the ADCS Bit
A/D Conversion Mode
Set Conditions
Clear Conditions
Software trigger no-wait mode
Select mode Sequential conversion When 1 is written When 0 is written to ADCS
mode
to ADCS
One-shot conversion mode
· When 0 is written to ADCS · The bit is automatically cleared to 0 when A/D
conversion ends.
Scan mode
Sequential conversion mode
When 0 is written to ADCS
One-shot conversion mode
· When 0 is written to ADCS · The bit is automatically cleared to 0 when
conversion ends on the specified four channels
Software trigger wait mode
Select mode Sequential conversion mode
When 0 is written to ADCS
One-shot conversion mode
· When 0 is written to ADCS · The bit is automatically cleared to 0 when A/D
conversion ends.
Scan mode
Sequential conversion mode
When 0 is written to ADCS
One-shot conversion mode
· When 0 is written to ADCS · The bit is automatically cleared to 0 when
conversion ends on the specified four channels.
Hardware trigger Select mode Sequential conversion
no-wait mode
mode
When 0 is written to ADCS
One-shot conversion mode
When 0 is written to ADCS
Scan mode
Sequential conversion mode
When 0 is written to ADCS
One-shot conversion mode
When 0 is written to ADCS
Hardware trigger Select mode Sequential conversion When a hardware When 0 is written to ADCS
wait mode
mode
trigger is input
One-shot conversion mode
· When 0 is written to ADCS · The bit is automatically cleared to 0 when A/D
conversion ends.
Scan mode
Sequential conversion mode
When 0 is written to ADCS
One-shot conversion mode
· When 0 is written to ADCS · The bit is automatically cleared to 0 when
conversion ends on the specified four channels
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RL78/G23 Figure 12 - 5 Timing Chart When A/D Voltage Comparator Is Used
CHAPTER 12 A/D CONVERTER (ADC)
ADCE
A/D voltage comparator: enables operation
A/D voltage comparator
Software trigger no-wait mode
ADCS
Conversion standby
Note 1
Conversion start timeNote 2
Conversion
Conversion
operation
standby
Conversion stopped
ADCE
Software trigger wait mode
ADCS
Hardware trigger no-wait mode ADCS
Hardware trigger wait mode ADCS
ADCE = 0
Conversion stopped
Set by writing 1 to the
ADCS bit.
Cleared by writing 0 to the ADCS bit or automatically upon completion of A/D conversion.
Conversion start timeNote 2
A/D power supply stabilization wait time
Conversion operation
Conversion stopped
Set by writing 1 to the ADCS bit.
Cleared by writing 0 to the ADCS bit or automatically upon completion of A/D conversion.
Conversion Trigger standby standby
Conversion start timeNote 2
Conversion
Conversion
operation
standby
Note 1
Hardware
trigger detection
Set by writing 1 to the
Cleared by writing 0 to the ADCS bit.
ADCS bit.
Conversion start timeNote 2
A/D power supply stabilization wait time
Conversion standby
Conversion operation
Conversion standby
Conversion stopped
Conversion stopped
Hardware trigger detection
Cleared by writing 0 to the ADCS bit or automatically upon completion of A/D conversion.
Note 1. Note 2.
While in the software trigger no-wait mode or hardware trigger no-wait mode, the time from the rising of the ADCE bit to the rising of the ADCS bit must be 1 µs + 2 cycles of the conversion clock (fAD) or longer to stabilize the internal circuit. The following shows the maximum time to start conversion.
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ADM1 ADLSP
0 0 0 0 0
ADM0 FR2 FR1 FR0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
Conversion Clock (fAD)
Conversion Start Time (Number of fCLK Clock)
Software Trigger No-wait Mode/Hardware Trigger No-wait Mode
Software trigger wait mode/ Hardware trigger wait mode
fCLK/32
31
1
fCLK/16
15
1
fCLK/8
7
1
fCLK/4
3
1
fCLK/2
1
1
0
1
0
1
fCLK
1
1
1
0
1
1
fCLK/4
3
1
1
1
0
0
fCLK/2
1
1
1
1
0
1
fCLK
1
1
However, for the second and subsequent conversion in sequential conversion mode and for conversion of the channels specified for scan 1, 2, and 3 in scan mode, the conversion start time and stabilization wait time for A/D power supply do not occur after a hardware trigger is detected.
Caution 1. If using the hardware trigger wait mode, setting the ADCS bit to 1 is prohibited (but the bit is automatically switched to 1 when the hardware trigger signal is detected). However, it is possible to clear the ADCS bit to 0 to specify the A/D conversion standby state.
Caution 2. While in the one-shot conversion mode of the hardware trigger no-wait mode, the ADCS bit is not automatically cleared to 0 when A/D conversion ends. Instead, 1 is retained.
Caution 3. Only rewrite the value of the ADCE bit when ADCS = 0 (while in the conversion stopped/conversion standby state). Caution 4. To complete A/D conversion, specify at least the following time as the hardware trigger interval:
Hardware trigger no wait mode: 2 fCLK clock cycles + conversion start time + A/D conversion time Hardware trigger wait mode: 2 fCLK clock cycles + conversion start time + A/D power supply stabilization wait time + A/D conversion time
Remark fCLK: CPU/peripheral hardware clock frequency
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CHAPTER 12 A/D CONVERTER (ADC)
Table 12 - 3 A/D Conversion Time Selection (1/8)
(1) When there is no A/D power supply stabilization wait time Normal mode 1 and 2 (for software trigger no-wait select mode and hardware trigger no-wait select mode)
A/D Converter Mode Register 0 A/D Converter Mode Register 1
(AD M1)
(ADM0)
ADL SP
FR2
FR1
FR0
LV1
LV0
Mode
Conversion Clock (fAD)
Number of Clock
Cycles for Conversion Start Delay
Number of Clock
Cycles for Conversion
Number of Clock
Cycles for Interrupt Output
Delay
A/D Conversion Time (Conversion Start Delay Time + Conversion Time + Interrupt Output Delay Time)
2.4 V AVREFP VDD 5.5 V
fCLK = 1 MHz
fCLK = 4 MHz
fCLK = 8 MHz
fCLK = 16 MHz
fCLK = 32 MHz
0 0 0 0 0 0 Normal fCLK/32 1
1 fAD
64 fAD
1 fAD
2112/fCLK Setting Setting Setting Setting 66 µs prohibited prohibited prohibited prohibited
0001
fCLK/16
1 fAD
64 fAD
1 fAD
1056/fCLK Setting Setting Setting 66 µs prohibited prohibited prohibited
33 µs
0010
fCLK/8
1 fAD
64 fAD
1 fAD
528/fCLK Setting Setting 66 µs prohibited prohibited
33 µs 16.5 µs
0011
fCLK/4
1 fAD
64 fAD
1 fAD
264/fCLK Setting Setting 33 µs prohibited prohibited
16.5 µs 8.25 µs
0100
fCLK/2
1 fAD
64 fAD
1 fAD
132/fCLK Setting Setting 16.5 µs 8.25 µs 4.125 µs prohibited prohibited
0101
fCLK
1 fAD
64 fAD
1 fAD
66/fCLK Setting Setting 8.25 µs 4.125 µs 2.0625 µs
prohibited prohibited
1011
fCLK/4
1 fAD
64 fAD
1 fAD
264/fCLK Setting 66 µs Setting Setting Setting
prohibited
prohibited prohibited prohibited
1100
fCLK/2
1 fAD
64 fAD
1 fAD
132/fCLK Setting 33 µs Setting Setting Setting
prohibited
prohibited prohibited prohibited
1101
fCLK
1 fAD
64 fAD
1 fAD
66/fCLK
66 µs 16.5 µs Setting Setting Setting
prohibited prohibited prohibited
Other than the above
Setting prohibited
0 0 0 0 0 1 Normal fCLK/32 2
1 fAD
181 fAD
1 fAD
5856/fCLK Setting Setting Setting Setting 183 µs prohibited prohibited prohibited prohibited
0001
fCLK/16
1 fAD
181 fAD
1 fAD
2928/fCLK Setting Setting Setting 183 µs prohibited prohibited prohibited
91.5 µs
0010
fCLK/8
1 fAD
181 fAD
1 fAD
1464/fCLK Setting Setting 183 µs 91.5 µs 45.75 µs prohibited prohibited
0011
fCLK/4
1 fAD
181 fAD
1 fAD
732/fCLK Setting Setting 91.5 µs 45.75 µs 22.875 µs prohibited prohibited
0100
fCLK/2
1 fAD
181 fAD
1 fAD
366/fCLK Setting Setting 45.75 µs 22.875 µs 11.4375 µs prohibited prohibited
0101
fCLK
1 fAD
181 fAD
1 fAD
183/fCLK Setting Setting 22.875 µs 11.4375 µs 5.71875
prohibited prohibited
µs
1011
fCLK/4
1 fAD
181 fAD
1 fAD
732/fCLK Setting 183 µs Setting Setting Setting
prohibited
prohibited prohibited prohibited
1100
fCLK/2
1 fAD
181 fAD
1 fAD
366/fCLK Setting 91.5 µs Setting Setting Setting
prohibited
prohibited prohibited prohibited
1101
fCLK
1 fAD
181 fAD
1 fAD
183/fCLK 183 µs 45.75 µs Setting Setting Setting
prohibited prohibited prohibited
Other than the above
Setting prohibited
Caution 1. The A/D conversion time must also be within the relevant range of conversion times (tCONV) described in 37.6.1 A/D converter characteristics.
Caution 2. Rewrite the FR2 to FR0, LV1, and LV0 bits to different values while conversion is stopped (ADCS = 0, ADCE = 0). Caution 3. The above conversion times do not include the conversion start time. Add the conversion start time to obtain the
time for the first conversion. Additionally, the conversion times do not include clock frequency errors. Consider clock frequency errors when selecting the conversion time. Caution 4. Use normal mode 2 when the internal reference voltage or temperature sensor output voltage is selected as the target for A/D conversion. Caution 5. When the internal reference voltage is selected as the positive reference voltage, normal modes 1 and 2 cannot be used. Use low-voltage mode 1 or 2.
Remark fCLK: CPU/peripheral hardware clock frequency
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CHAPTER 12 A/D CONVERTER (ADC)
Table 12 - 3 A/D Conversion Time Selection (2/8)
(2) When there is no A/D power supply stabilization wait time Low-voltage mode 1 and 2 (for software trigger no-wait select mode and hardware trigger no-wait select mode)
A/D Converter Mode Register 0 A/D Converter Mode Register 1
(AD M1)
(ADM0)
ADL SP
FR2
FR1
FR0
LV1
LV0
Mode
Conversion Clock (fAD)
Number of Clock
Cycles for Conversion Start Delay
Number of Clock
Cycles for Conversion
Number of Clock
Cycles for Interrupt Output
Delay
A/D Conversion Time (Conversion Start Delay Time + Conversion Time + Interrupt Output Delay Time)
1.6 V 1.6 V 1.8 V 2.4 V 2.7 V AVREFP AVREFP AVREFP AVREFP AVREFP
VDD VDD VDD VDD VDD 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V
fCLK = 1 MHz
fCLK = 4 MHz
fCLK = fCLK = fCLK = 8 MHz 16 MHz 32 MHz
000010
Low
fCLK/32
voltage 1
1 fAD
80 fAD
1 fAD
2624/fCLK Setting Setting Setting Setting 82 µs prohibited prohibited prohibited prohibited
0001
fCLK/16
1 fAD
80 fAD
1 fAD
1312/fCLK Setting Setting Setting 82 µs prohibited prohibited prohibited
41 µs
0010
fCLK/8
1 fAD
80 fAD
1 fAD
656/fCLK Setting Setting 82 µs prohibited prohibited
41 µs 20.5 µs
0011
fCLK/4
1 fAD
80 fAD
1 fAD
328/fCLK Setting Setting 41 µs prohibited prohibited
20.5 µs 10.25 µs
0100
fCLK/2
1 fAD
80 fAD
1 fAD
164/fCLK Setting Setting 20.5 µs 10.25 µs 5.125 µs prohibited prohibited
0101
fCLK
1 fAD
80 fAD
1 fAD
82/fCLK Setting Setting 10.25 µs 5.125 µs Setting
prohibited prohibited
prohibited
1011
fCLK/4
1 fAD
80 fAD
1 fAD
328/fCLK Setting 82 µs Setting Setting Setting
prohibited
prohibited prohibited prohibited
1100
fCLK/2
1 fAD
80 fAD
1 fAD
164/fCLK Setting 41 µs Setting Setting Setting
prohibited
prohibited prohibited prohibited
1101
fCLK
1 fAD
80 fAD
1 fAD
82/fCLK
82 µs 20.5 µs Setting Setting Setting
prohibited prohibited prohibited
Other than the above
Setting prohibited
000011
Low
fCLK/32
voltage 2
1 fAD
107 fAD
1 fAD
3488/fCLK Setting Setting Setting Setting 109 µs prohibited prohibited prohibited prohibited
0001
fCLK/16
1 fAD
107 fAD
1 fAD
1744/fCLK Setting Setting Setting 109 µs 54.5 µs prohibited prohibited prohibited
0010
fCLK/8
1 fAD
107 fAD
1 fAD
872/fCLK Setting Setting 109 µs 54.5 µs 27.25 µs prohibited prohibited
0011
fCLK/4
1 fAD
107 fAD
1 fAD
436/fCLK Setting Setting 54.5 µs 27.25 µs 13.625 µs prohibited prohibited
0100
fCLK/2
1 fAD
107 fAD
1 fAD
218/fCLK Setting Setting 27.25 µs 13.625 µs 6.8125 µs prohibited prohibited
0101
fCLK
1 fAD
107 fAD
1 fAD
109/fCLK Setting Setting 13.625 µs 6.8125 µs Setting
prohibited prohibited
prohibited
1011
fCLK/4
1 fAD
107 fAD
1 fAD
436/fCLK Setting 109 µs Setting Setting Setting
prohibited
prohibited prohibited prohibited
1100
fCLK/2
1 fAD
107 fAD
1 fAD
218/fCLK Setting 54.5 µs Setting Setting Setting
prohibited
prohibited prohibited prohibited
1101
fCLK
1 fAD
107 fAD
1 fAD
109/fCLK 109 µs 27.25 µs Setting Setting Setting
prohibited prohibited prohibited
Other than the above
Setting prohibited
Caution 1. The A/D conversion time must also be within the relevant range of conversion times (tCONV) described in 37.6.1 A/D converter characteristics.
Caution 2. Rewrite the FR2 to FR0, LV1, and LV0 bits to different values while conversion is stopped (ADCS = 0, ADCE = 0). Caution 3. The above conversion times do not include the conversion start time. Add the conversion start time to obtain the
time for the first conversion. Additionally, the conversion times do not include clock frequency errors. Consider clock frequency errors when selecting the conversion time. Caution 4. When the internal reference voltage or temperature sensor output voltage is selected as the target for A/D conversion, use low-voltage mode 2 and use a conversion clock (fAD) with a frequency no greater than 16 MHz. Caution 5. When the internal reference voltage is selected as the positive reference voltage, the conversion clock (fAD) must be in the range from 1 to 2 MHz. Remark fCLK: CPU/peripheral hardware clock frequency
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CHAPTER 12 A/D CONVERTER (ADC)
Table 12 - 3 A/D Conversion Time Selection (3/8)
(3) When there is A/D power supply stabilization wait time Normal mode 1 and 2 (for software trigger wait select mode and hardware trigger wait select modeNote 1)
A/D Converter Mode Register 0 A/D Converter Mode Register 1
(AD M1)
(ADM0)
ADL SP
FR2
FR1
FR0
LV1
LV0
Mode
Number of
Clock
Conversion Clock (fAD)
Cycles for A/D Power
Supply
Stabilization
Wait
Number of Clock
Cycles for Conversion
Number of Clock
Cycles for Interrupt Output
Delay
Note 2
A/D Conversion Time (A/D Power Supply Stabilization Wait Time + Conversion Time + Interrupt Output Delay Time)
2.4 V AVREFP VDD 5.5 V
fCLK = 1 MHz
fCLK = 4 MHz
fCLK = 8 MHz
fCLK = 16 MHz
fCLK = 32 MHz
0 0 0 0 0 0 Normal fCLK/32 1
4 fAD
64 fAD
4 fAD
2304/fCLK Setting Setting Setting Setting prohibited prohibited prohibited prohibited
72 µs
0001
fCLK/16
4 fAD
64 fAD
4 fAD
1152/fCLK Setting Setting Setting prohibited prohibited prohibited
72 µs
36 µs
0010
fCLK/8
6 fAD
64 fAD
4 fAD
592/fCLK Setting Setting prohibited prohibited
74 µs
37 µs 18.5 µs
0011
fCLK/4
10 fAD
64 fAD
4 fAD
312/fCLK Setting Setting prohibited prohibited
39 µs
19.5 µs 9.75 µs
0100
fCLK/2
18 fAD
64 fAD
4 fAD
172/fCLK Setting Setting 21.5 µs 10.75 µs 5.375 µs prohibited prohibited
0101
fCLK
34 fAD
64 fAD
4 fAD 102/fCLK Setting Setting 12.75 µs 6.375 µs 3.1875 µs
prohibited prohibited
1011
fCLK/4
4 fAD
64 fAD
4 fAD 288/fCLK 288 µs
72 µs
Setting Setting Setting prohibited prohibited prohibited
1100
fCLK/2
4 fAD
64 fAD
4 fAD 144/fCLK 144 µs
36 µs
Setting Setting Setting prohibited prohibited prohibited
1101
fCLK
6 fAD
64 fAD
4 fAD
74/fCLK
74 µs
18.5 µs Setting Setting Setting
prohibited prohibited prohibited
Other than the above
Setting prohibited
0 0 0 0 0 1 Normal fCLK/32 2
4 fAD
181 fAD
4 fAD
6048/fCLK Setting Setting Setting Setting 189 µs prohibited prohibited prohibited prohibited
0001
fCLK/16
4 fAD
181 fAD
4 fAD
3024/fCLK Setting Setting Setting 189 µs prohibited prohibited prohibited
94.5 µs
0010
fCLK/8
6 fAD
181 fAD
4 fAD
1528/fCLK Setting Setting 191 µs prohibited prohibited
95.5 µs 47.75 µs
0011
fCLK/4
10 fAD 181 fAD
4 fAD
780/fCLK Setting Setting 97.5 µs 48.75 µs 24.375 µs prohibited prohibited
0100
fCLK/2
18 fAD 181 fAD
4 fAD
406/fCLK Setting Setting 50.75 µs 25.375 µs 12.6875 µs prohibited prohibited
0101
fCLK
34 fAD 181 fAD
4 fAD 219/fCLK Setting Setting 27.375 µs 13.6875 µs 6.84375 µs
prohibited prohibited
1011
fCLK/4
4 fAD
181 fAD
4 fAD
756/fCLK Setting 189 µs Setting Setting Setting
prohibited
prohibited prohibited prohibited
1100
fCLK/2
4 fAD
181 fAD
4 fAD
378/fCLK Setting 94.5 µs Setting Setting Setting
prohibited
prohibited prohibited prohibited
1101
fCLK
6 fAD
181 fAD
4 fAD 191/fCLK 191 µs 47.75 µs Setting Setting Setting
prohibited prohibited prohibited
Other than the above
Setting prohibited
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CHAPTER 12 A/D CONVERTER (ADC)
Note 1. Note 2.
For the second and subsequent conversion in sequential conversion mode and for conversion of the channels specified for scan 1, 2, and 3 in scan mode, the conversion start time and A/D power supply stabilization wait time do not occur after a hardware trigger is detected (see Table 12 - 3 A/D Conversion Time Selection (1/8)). The value in this column is applicable when the one-shot conversion mode is selected. When the sequential conversion mode is selected, the number of clock cycles is shortened by 3 cycles of the conversion clock (fAD).
Caution 1. The A/D conversion time must also be within the relevant range of conversion times (tCONV) described in 37.6.1 A/D converter characteristics.
Caution 2. Rewrite the FR2 to FR0, LV1, and LV0 bits to different values while conversion is stopped (ADCS = 0, ADCE = 0). Caution 3. The above conversion times do not include the conversion start time. Add the conversion start time to obtain the
time for the first conversion. Additionally, the conversion times do not include clock frequency errors. Consider clock frequency errors when selecting the conversion time. Caution 4. The conversion times in hardware trigger wait mode include the A/D power supply stabilization wait time from the time the hardware trigger is detected. The conversion times in software trigger wait mode include the A/D power supply stabilization wait time from the time the ADCS bit is set to 1. Caution 5. Use normal mode 2 when the internal reference voltage or temperature sensor output voltage is selected as the target for A/D conversion. Caution 6. When the internal reference voltage is selected as the positive reference voltage, normal modes 1 and 2 cannot be used. Use low-voltage mode 1 or 2.
Remark fCLK: CPU/peripheral hardware clock frequency
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CHAPTER 12 A/D CONVERTER (ADC)
Table 12 - 3 A/D Conversion Time Selection (4/8)
(4) When there is A/D power supply stabilization wait time Low-voltage mode 1 and 2 (for software trigger wait select mode and hardware trigger wait select modeNote 1)
A/D Converter Mode Register 0 A/D Converter Mode Register 1
(AD M1)
(ADM0)
ADL SP
FR2
FR1
FR0
LV1
LV0
Mode
Number of
Conversion Clock (fAD)
Clock Cycles for A/D Power
Supply Stabilization
Number of Clock
Cycles for Conversion
Wait
Number of Clock
Cycles for Interrupt Output
Delay
Note 2
A/D Conversion Time (A/D Power Supply Stabilization Wait Time + Conversion Time + Interrupt Output Delay Time)
1.6 V AVREFP
VDD 5.5 V
1.6 V AVREFP
VDD 5.5 V
1.8 V AVREFP
VDD 5.5 V
2.4 V AVREFP
VDD 5.5 V
2.7 V AVREFP
VDD 5.5 V
fCLK = 1 MHz
fCLK = 4 MHz
fCLK = 8 MHz
fCLK = 16 MHz
fCLK = 32 MHz
0 0 0 0 1 0 Low fCLK/32 voltage 1
4 fAD
80 fAD
4 fAD
2816/fCLK Setting Setting Setting Setting 88 µs prohibited prohibited prohibited prohibited
0001
fCLK/16
4 fAD
80 fAD
4 fAD
1408/fCLK Setting Setting Setting 88 µs prohibited prohibited prohibited
44 µs
0010
fCLK/8
6 fAD
80 fAD
4 fAD
720/fCLK Setting Setting 90 µs prohibited prohibited
45 µs 22.5 µs
0011
fCLK/4
10 fAD
80 fAD
4 fAD
376/fCLK Setting Setting 47 µs prohibited prohibited
23.5 µs 11.75 µs
0100
fCLK/2
18 fAD
80 fAD
4 fAD
204/fCLK Setting Setting 25.5 µs 12.75 µs 6.375 µs prohibited prohibited
0101
fCLK
34 fAD
80 fAD
4 fAD 118/fCLK Setting Setting 14.75 µs 7.375 µs Setting
prohibited prohibited
prohibited
1011
fCLK/4
4 fAD
80 fAD
4 fAD
352/fCLK Setting 88 µs Setting Setting Setting
prohibited
prohibited prohibited prohibited
1100
fCLK/2
4 fAD
80 fAD
4 fAD
176/fCLK Setting 44 µs Setting Setting Setting
prohibited
prohibited prohibited prohibited
1101
fCLK
6 fAD
80 fAD
4 fAD
90/fCLK
90 µs 22.5 µs Setting Setting Setting
prohibited prohibited prohibited
Other than the above
Setting prohibited
0 0 0 0 1 1 Low fCLK/32 voltage 2
4 fAD
107 fAD
4 fAD
3680/fCLK Setting Setting Setting Setting 115 µs prohibited prohibited prohibited prohibited
0001
fCLK/16
4 fAD
107 fAD
4 fAD
1840/fCLK Setting Setting Setting 115 µs prohibited prohibited prohibited
57.5 µs
0010
fCLK/8
6 fAD
107 fAD
4 fAD
936/fCLK Setting Setting 117 µs prohibited prohibited
58.5 µs 29.25 µs
0011
fCLK/4
10 fAD 107 fAD
4 fAD
484/fCLK Setting Setting 60.5 µs 30.25 µs 15.125 µs prohibited prohibited
0100
fCLK/2
18 fAD 107 fAD
4 fAD
258/fCLK Setting Setting 32.25 µs 16.125 µs 8.0625 µs prohibited prohibited
0101
fCLK
34 fAD 107 fAD
4 fAD 145/fCLK Setting Setting 18.125 µs 9.0625 µs Setting
prohibited prohibited
prohibited
1011
fCLK/4
4 fAD
107 fAD
4 fAD
460/fCLK Setting 115 µs Setting Setting Setting
prohibited
prohibited prohibited prohibited
1100
fCLK/2
4 fAD
107 fAD
4 fAD
230/fCLK Setting 57.5 µs Setting Setting Setting
prohibited
prohibited prohibited prohibited
1101
fCLK
6 fAD
107 fAD
4 fAD 117/fCLK 117 µs 29.25 µs Setting Setting Setting
prohibited prohibited prohibited
Other than the above
Setting prohibited
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CHAPTER 12 A/D CONVERTER (ADC)
Note 1. Note 2.
For the second and subsequent conversion in sequential conversion mode and for conversion of the channels specified for scan 1, 2, and 3 in scan mode, the conversion start time and A/D power supply stabilization wait time do not occur after a hardware trigger is detected (see Table 12 - 3 A/D Conversion Time Selection (2/8)). The value in this column is applicable when the one-shot conversion mode is selected. When the sequential conversion mode is selected, the number of clock cycles is shortened by 3 cycles of the conversion clock (fAD).
Caution 1. The A/D conversion time must also be within the relevant range of conversion times (tCONV) described in 37.6.1 A/D converter characteristics.
Caution 2. Rewrite the FR2 to FR0, LV1, and LV0 bits to different values while conversion is stopped (ADCS = 0, ADCE = 0). Caution 3. The above conversion times do not include the conversion start time. Add the conversion start time to obtain the
time for the first conversion. Additionally, the conversion times do not include clock frequency errors. Consider clock frequency errors when selecting the conversion time. Caution 4. The conversion times in hardware trigger wait mode include the A/D power supply stabilization wait time from the time the hardware trigger is detected. The conversion times in software trigger wait mode include the A/D power supply stabilization wait time from the time the ADCS bit is set to 1. Caution 5. When the internal reference voltage or temperature sensor output voltage is selected as the target for A/D conversion, use low-voltage mode 2 and use a conversion clock (fAD) with a frequency no greater than 16 MHz. Caution 6. When the internal reference voltage is selected as the positive reference voltage, the conversion clock (fAD) must be in the range from 1 to 2 MHz.
Remark fCLK: CPU/peripheral hardware clock frequency
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CHAPTER 12 A/D CONVERTER (ADC)
Table 12 - 4 A/D Conversion Time Selection (5/8)
(5) When there is no A/D power supply stabilization wait time
Normal mode 1 and 2 (for software trigger no-wait scan mode and hardware trigger no-wait scan mode)
A/D Converter Mode Register 0 A/D Converter Mode Register 1
(AD M1)
(ADM0)
ADL SP
FR2
FR1
FR0
LV1
LV0
Mode
Conversion Clock (fAD)
Number of Clock
Cycles for Conversion Start Delay
Number of Clock
Cycles for Conversion
Number of Clock
Cycles for Interrupt Output
Delay
A/D Conversion Time (Conversion Start Delay Time + Conversion Time × 4 + Interrupt Output Delay Time)
2.4 V AVREFP VDD 5.5 V
fCLK = 1 MHz
fCLK = 4 MHz
fCLK = 8 MHz
fCLK = 16 MHz
fCLK = 32 MHz
0 0 0 0 0 0 Normal fCLK/32 1
1 fAD
64 fAD
1 fAD
8256/fCLK Setting Setting Setting Setting 258 µs prohibited prohibited prohibited prohibited
0001
fCLK/16
1 fAD
64 fAD
1 fAD
4128/fCLK Setting Setting Setting 258 µs prohibited prohibited prohibited
129 µs
0010
fCLK/8
1 fAD
64 fAD
1 fAD
2064/fCLK Setting Setting 258 µs prohibited prohibited
129 µs
64.5 µs
0011
fCLK/4
1 fAD
64 fAD
1 fAD
1032/fCLK Setting Setting 129 µs 64.5 µs 32.25 µs prohibited prohibited
0100
fCLK/2
1 fAD
64 fAD
1 fAD
516/fCLK Setting Setting 64.5 µs 32.25 µs 16.125 µs prohibited prohibited
0101
fCLK
1 fAD
64 fAD
1 fAD
258/fCLK Setting Setting 32.25 µs 16.125 µs 8.0625 µs
prohibited prohibited
1011
fCLK/4
1 fAD
64 fAD
1 fAD
1032/fCLK Setting 258 µs Setting Setting Setting
prohibited
prohibited prohibited prohibited
1100
fCLK/2
1 fAD
64 fAD
1 fAD
516/fCLK Setting 129 µs Setting Setting Setting
prohibited
prohibited prohibited prohibited
1101
fCLK
1 fAD
64 fAD
1 fAD
258/fCLK 258 µs 64.5 µs Setting Setting Setting
prohibited prohibited prohibited
Other than the above
Setting prohibited
0 0 0 0 0 1 Normal fCLK/32 2
1 fAD
181 fAD
1 fAD
23232/fCLK Setting Setting Setting Setting 726 µs prohibited prohibited prohibited prohibited
0001
fCLK/16
1 fAD
181 fAD
1 fAD
11616/fCLK Setting Setting Setting 726 µs prohibited prohibited prohibited
363 µs
0010
fCLK/8
1 fAD
181 fAD
1 fAD
5808/fCLK Setting Setting 726 µs prohibited prohibited
363 µs
181.5 µs
0011
fCLK/4
1 fAD
181 fAD
1 fAD
2904/fCLK Setting Setting 363 µs 181.5 µs 90.75 µs prohibited prohibited
0100
fCLK/2
1 fAD
181 fAD
1 fAD
1452/fCLK Setting Setting 181.5 µs 90.75 µs 45.375 µs prohibited prohibited
0101
fCLK
1 fAD
181 fAD
1 fAD
726/fCLK Setting Setting 90.75 µs 45.375 µs 22.6875
prohibited prohibited
µs
1011
fCLK/4
1 fAD
181 fAD
1 fAD
2904/fCLK Setting 726 µs Setting Setting Setting
prohibited
prohibited prohibited prohibited
1100
fCLK/2
1 fAD
181 fAD
1 fAD
1452/fCLK Setting 363 µs Setting Setting Setting
prohibited
prohibited prohibited prohibited
1101
fCLK
1 fAD
181 fAD
1 fAD
726/fCLK 726 µs 181.5 µs Setting Setting Setting
prohibited prohibited prohibited
Other than the above
Setting prohibited
Caution 1. The A/D conversion time must also be within the relevant range of conversion times (tCONV) described in 37.6.1 A/D converter characteristics.
Caution 2. Rewrite the FR2 to FR0, LV1, and LV0 bits to different values while conversion is stopped (ADCS = 0, ADCE = 0). Caution 3. The above conversion times do not include the conversion start time. Add the conversion start time to obtain the
time for the first conversion. Additionally, the conversion times do not include clock frequency errors. Consider clock frequency errors when selecting the conversion time. Caution 4. Use normal mode 2 when the internal reference voltage or temperature sensor output voltage is selected as the target for A/D conversion. Caution 5. When the internal reference voltage is selected as the positive reference voltage, normal modes 1 and 2 cannot be used. Use low-voltage mode 1 or 2.
Remark fCLK: CPU/peripheral hardware clock frequency
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CHAPTER 12 A/D CONVERTER (ADC)
Table 12 - 3 A/D Conversion Time Selection (6/8)
(6) When there is no A/D power supply stabilization wait time
Low-voltage mode 1 and 2 (for software trigger no-wait scan mode and hardware trigger no-wait scan mode)
A/D Converter Mode Register 0 A/D Converter Mode Register 1
(AD M1)
(ADM0)
ADL SP
FR2
FR1
FR0
LV1
LV0
Mode
Conversion Clock (fAD)
Number of Clock
Cycles for Conversion Start Delay
Number of Clock
Cycles for Conversion
Number of Clock
Cycles for Interrupt Output
Delay
A/D Conversion Time (Conversion Start Delay Time + Conversion Time × 4 + Interrupt Output Delay Time)
1.6 V 1.6 V 1.8 V 2.4 V 2.7 V AVREFP AVREFP AVREFP AVREFP AVREFP
VDD VDD VDD VDD VDD 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V
fCLK = 1 MHz
fCLK = 4 MHz
fCLK = fCLK = fCLK = 8 MHz 16 MHz 32 MHz
00
00
10
Low
fCLK/32
voltage 1
1 fAD
80 fAD
1 fAD
10304/fCLK Setting Setting Setting Setting 322 µs prohibited prohibited prohibited prohibited
0001
fCLK/16
1 fAD
80 fAD
1 fAD
5152/fCLK Setting Setting Setting 322 µs 161 µs prohibited prohibited prohibited
0010
fCLK/8
1 fAD
80 fAD
1 fAD
2576/fCLK Setting Setting 322 µs 161 µs 80.5 µs prohibited prohibited
0011
fCLK/4
1 fAD
80 fAD
1 fAD
1288/fCLK Setting Setting 161 µs 80.5 µs 40.25 µs prohibited prohibited
0100
fCLK/2
1 fAD
80 fAD
1 fAD
644/fCLK Setting Setting 80.5 µs 40.25 µs 20.125 µs prohibited prohibited
0101
fCLK
1 fAD
80 fAD
1 fAD
322/fCLK Setting Setting 40.25 µs 20.125 µs Setting
prohibited prohibited
prohibited
1011
fCLK/4
1 fAD
80 fAD
1 fAD
1288/fCLK Setting 322 µs Setting Setting Setting
prohibited
prohibited prohibited prohibited
1100
fCLK/2
1 fAD
80 fAD
1 fAD
644/fCLK Setting 161 µs Setting Setting Setting
prohibited
prohibited prohibited prohibited
1101
fCLK
1 fAD
80 fAD
1 fAD
322/fCLK 322 µs 80.5 µs Setting Setting Setting
prohibited prohibited prohibited
Other than the above
Setting prohibited
00
00
11
Low
fCLK/32
voltage 2
1 fAD
107 fAD
1 fAD
13760/fCLK Setting Setting Setting Setting 430 µs prohibited prohibited prohibited prohibited
0001
fCLK/16
1 fAD
107 fAD
1 fAD
6880/fCLK Setting Setting Setting 430 µs 215 µs prohibited prohibited prohibited
0010
fCLK/8
1 fAD
107 fAD
1 fAD
3440/fCLK Setting Setting 430 µs 215 µs 107.5 µs prohibited prohibited
0011
fCLK/4
1 fAD
107 fAD
1 fAD
1720/fCLK Setting Setting 215 µs 107.5 µs 53.75 µs prohibited prohibited
0100
fCLK/2
1 fAD
107 fAD
1 fAD
860/fCLK Setting Setting 107.5 µs 53.75 µs 26.875 µs prohibited prohibited
0101
fCLK
1 fAD
107 fAD
1 fAD
430/fCLK Setting Setting 53.75 µs 26.875 µs Setting
prohibited prohibited
prohibited
1011
fCLK/4
1 fAD
107 fAD
1 fAD
1720/fCLK Setting 430 µs Setting Setting Setting
prohibited
prohibited prohibited prohibited
1100
fCLK/2
1 fAD
107 fAD
1 fAD
860/fCLK Setting 215 µs Setting Setting Setting
prohibited
prohibited prohibited prohibited
1101
fCLK
1 fAD
107 fAD
1 fAD
430/fCLK 430 µs 107.5 µs Setting Setting Setting
prohibited prohibited prohibited
Other than the above
Setting prohibited
Caution 1. The A/D conversion time must also be within the relevant range of conversion times (tCONV) described in 37.6.1 A/D converter characteristics.
Caution 2. Rewrite the FR2 to FR0, LV1, and LV0 bits to different values while conversion is stopped (ADCS = 0, ADCE = 0). Caution 3. The above conversion times do not include the conversion start time. Add the conversion start time to obtain the
time for the first conversion. Additionally, the conversion times do not include clock frequency errors. Consider clock frequency errors when selecting the conversion time. Caution 4. When the internal reference voltage or temperature sensor output voltage is selected as the target for A/D conversion, use low-voltage mode 2 and use a conversion clock (fAD) with a frequency no greater than 16 MHz. Caution 5. When the internal reference voltage is selected as the positive reference voltage, the conversion clock (fAD) must be in the range from 1 to 2 MHz. Remark fCLK: CPU/peripheral hardware clock frequency
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
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RL78/G23
CHAPTER 12 A/D CONVERTER (ADC)
Table 12 - 3 A/D Conversion Time Selection (7/8)
(7) When there is A/D power supply stabilization wait time Normal mode 1 and 2 (for software trigger wait scan mode and hardware trigger wait scan modeNote 1)
A/D Converter Mode Register 0 A/D Converter Mode Register 1
(AD M1)
(ADM0)
ADL SP
FR2
FR1
FR0
LV1
LV0
Mode
Number of
Clock
Conversion Clock (fAD)
Cycles for A/D Power
Supply
Stabilization
Wait
Number of Clock
Cycles for Conversion
Number of Clock
Cycles for Interrupt Output
Delay
Note 2
A/D Conversion Time (A/D Power Supply Stabilization Wait Time + Conversion Time × 4 + Interrupt Output Delay Time)
2.4 V AVREFP VDD 5.5 V
fCLK = 1 MHz
fCLK = 4 MHz
fCLK = 8 MHz
fCLK = 16 MHz
fCLK = 32 MHz
0 0 0 0 0 0 Normal fCLK/32 1
4 fAD
64 fAD
4 fAD
8448/fCLK Setting Setting Setting Setting 264 µs prohibited prohibited prohibited prohibited
0001
fCLK/16
4 fAD
64 fAD
4 fAD
4224/fCLK Setting Setting Setting 264 µs prohibited prohibited prohibited
132 µs
0010
fCLK/8
6 fAD
64 fAD
4 fAD
2128/fCLK Setting Setting 266 µs prohibited prohibited
133 µs
66.5 µs
0011
fCLK/4
10 fAD
64 fAD
4 fAD
1080/fCLK Setting Setting 135 µs prohibited prohibited
67.5 µs 33.75 µs
0100
fCLK/2
18 fAD
64 fAD
4 fAD
556/fCLK Setting Setting 69.5 µs 34.75 µs 17.375 µs prohibited prohibited
0101
fCLK
34 fAD
64 fAD
4 fAD 294/fCLK Setting Setting 36.75 µs 18.375 µs 9.1875 µs
prohibited prohibited
1011
fCLK/4
4 fAD
64 fAD
4 fAD
1056/fCLK 1056 µs
264 µs Setting Setting Setting prohibited prohibited prohibited
1100
fCLK/2
4 fAD
64 fAD
4 fAD
528/fCLK 528 µs
132 µs Setting Setting Setting prohibited prohibited prohibited
1101
fCLK
6 fAD
64 fAD
4 fAD 266/fCLK 266 µs 66.5 µs Setting Setting Setting
prohibited prohibited prohibited
Other than the above
Setting prohibited
0 0 0 0 0 1 Normal fCLK/32 2
4 fAD
181 fAD
4 fAD 23424/fCLK Setting Setting Setting Setting 732 µs prohibited prohibited prohibited prohibited
0001
fCLK/16
4 fAD
181 fAD
4 fAD 11712/fCLK Setting Setting Setting 732 µs prohibited prohibited prohibited
366 µs
0010
fCLK/8
6 fAD
181 fAD
4 fAD
5872/fCLK Setting Setting 734 µs prohibited prohibited
367 µs 183.5 µs
0011
fCLK/4
10 fAD 181 fAD
4 fAD
2952/fCLK Setting Setting 369 µs prohibited prohibited
184.5 µs 92.25 µs
0100
fCLK/2
18 fAD 181 fAD
4 fAD
1492/fCLK Setting Setting 186.5 µs 93.25 µs 46.625 µs prohibited prohibited
0101
fCLK
34 fAD 181 fAD
4 fAD 762/fCLK Setting Setting 95.25 µs 47.625 µs 23.8125 µs
prohibited prohibited
1011
fCLK/4
4 fAD
181 fAD
4 fAD
2928/fCLK Setting 732 µs Setting Setting Setting
prohibited
prohibited prohibited prohibited
1100
fCLK/2
4 fAD
181 fAD
4 fAD
1464/fCLK Setting 366 µs Setting Setting Setting
prohibited
prohibited prohibited prohibited
1101
fCLK
6 fAD
181 fAD
4 fAD 734/fCLK 734 µs 183.5 µs Setting Setting Setting
prohibited prohibited prohibited
Other than the above
Setting prohibited
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CHAPTER 12 A/D CONVERTER (ADC)
Note 1. Note 2.
For the second and subsequent conversion in sequential conversion mode and for conversion of the channels specified for scan 1, 2, and 3 in scan mode, the conversion start time and A/D power supply stabilization wait time do not occur after a hardware trigger is detected (see Table 12 - 3 A/D Conversion Time Selection (1/8)). The value in this column is applicable when the one-shot conversion mode is selected. When the sequential conversion mode is selected, the number of clock cycles is shortened by 3 cycles of the conversion clock (fAD).
Caution 1. The A/D conversion time must also be within the relevant range of conversion times (tCONV) described in 37.6.1 A/D converter characteristics.
Caution 2. Rewrite the FR2 to FR0, LV1, and LV0 bits to different values while conversion is stopped (ADCS = 0, ADCE = 0). Caution 3. The above conversion times do not include the conversion start time. Add the conversion start time to obtain the
time for the first conversion. Additionally, the conversion times do not include clock frequency errors. Consider clock frequency errors when selecting the conversion time. Caution 4. The conversion times in hardware trigger wait mode include the A/D power supply stabilization wait time from the time the hardware trigger is detected. The conversion times in software trigger wait mode include the A/D power supply stabilization wait time from the time the ADCS bit is set to 1. Caution 5. Use normal mode 2 when the internal reference voltage or temperature sensor output voltage is selected as the target for A/D conversion. Caution 6. When the internal reference voltage is selected as the positive reference voltage, normal modes 1 and 2 cannot be used. Use low-voltage mode 1 or 2.
Remark fCLK: CPU/peripheral hardware clock frequency
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CHAPTER 12 A/D CONVERTER (ADC)
Table 12 - 3 A/D Conversion Time Selection (8/8)
(8) When there is A/D power supply stabilization wait time Low-voltage mode 1 and 2 (for software trigger wait scan mode and hardware trigger wait scan modeNote 1)
A/D Converter Mode Register 0 A/D Converter Mode Register 1
(AD M1)
(ADM0)
ADL SP
FR2
FR1
FR0
LV1
LV0
Mode
Number of
Conversion Clock (fAD)
Clock Cycles for A/D Power
Supply Stabilization
Number of Clock
Cycles for Conversion
Wait
Number of Clock
Cycles for Interrupt Output
Delay
Note 2
A/D Conversion Time (A/D Power Supply Stabilization Wait Time + Conversion Time × 4 + Interrupt Output Delay Time)
1.6 V AVREFP
VDD 5.5 V
1.6 V AVREFP
VDD 5.5 V
1.8 V AVREFP
VDD 5.5 V
2.4 V AVREFP
VDD 5.5 V
2.7 V AVREFP
VDD 5.5 V
fCLK = 1 MHz
fCLK = 4 MHz
fCLK = 8 MHz
fCLK = 16 MHz
fCLK = 32 MHz
0 0 0 0 1 0 Low fCLK/32 voltage 1
4 fAD
80 fAD
4 fAD 10496/fCLK Setting Setting Setting Setting 328 µs prohibited prohibited prohibited prohibited
0001
fCLK/16
4 fAD
80 fAD
4 fAD
5248/fCLK Setting Setting Setting 328 µs prohibited prohibited prohibited
164 µs
0010
fCLK/8
6 fAD
80 fAD
4 fAD
2640/fCLK Setting Setting 330 µs prohibited prohibited
165 µs
82.5 µs
0011
fCLK/4
10 fAD
80 fAD
4 fAD
1336/fCLK Setting Setting 167 µs prohibited prohibited
83.5 µs 41.75 µs
0100
fCLK/2
18 fAD
80 fAD
4 fAD
684/fCLK Setting Setting 85.5 µs 42.75 µs 21.375 µs prohibited prohibited
0101
fCLK
34 fAD
80 fAD
4 fAD 358/fCLK Setting Setting 44.75 µs 22.375 µs Setting
prohibited prohibited
prohibited
1011
fCLK/4
4 fAD
80 fAD
4 fAD
1312/fCLK Setting 328 µs Setting Setting Setting
prohibited
prohibited prohibited prohibited
1100
fCLK/2
4 fAD
80 fAD
4 fAD
656/fCLK Setting 164 µs Setting Setting Setting
prohibited
prohibited prohibited prohibited
1101
fCLK
6 fAD
80 fAD
4 fAD 330/fCLK 330 µs 82.5 µs Setting Setting Setting
prohibited prohibited prohibited
Other than the above
Setting prohibited
0 0 0 0 1 1 Low fCLK/32 voltage 2
4 fAD
107 fAD
4 fAD 13952/fCLK Setting Setting Setting Setting 436 µs prohibited prohibited prohibited prohibited
0001
fCLK/16
4 fAD
107 fAD
4 fAD
6976/fCLK Setting Setting Setting 436 µs prohibited prohibited prohibited
218 µs
0010
fCLK/8
6 fAD
107 fAD
4 fAD
3504/fCLK Setting Setting 438 µs prohibited prohibited
219 µs 109.5 µs
0011
fCLK/4
10 fAD 107 fAD
4 fAD
1768/fCLK Setting Setting 221 µs 110.5 µs 55.25 µs prohibited prohibited
0100
fCLK/2
18 fAD 107 fAD
4 fAD
900/fCLK Setting Setting 112.5 µs 56.25 µs 28.125 µs prohibited prohibited
0101
fCLK
34 fAD 107 fAD
4 fAD 466/fCLK Setting Setting 58.25 µs 29.125 µs Setting
prohibited prohibited
prohibited
1011
fCLK/4
4 fAD
107 fAD
4 fAD
1744/fCLK Setting 436 µs Setting Setting Setting
prohibited
prohibited prohibited prohibited
1100
fCLK/2
4 fAD
107 fAD
4 fAD
872/fCLK Setting 218 µs Setting Setting Setting
prohibited
prohibited prohibited prohibited
1101
fCLK
6 fAD
107 fAD
4 fAD 438/fCLK 438 µs 109.5 µs Setting Setting Setting
prohibited prohibited prohibited
Other than the above
Setting prohibited
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CHAPTER 12 A/D CONVERTER (ADC)
Note 1. Note 2.
For the second and subsequent conversion in sequential conversion mode and for conversion of the channels specified for scan 1, 2, and 3 in scan mode, the conversion start time and A/D power supply stabilization wait time do not occur after a hardware trigger is detected (see Table 12 - 3 A/D Conversion Time Selection (2/8)). The value in this column is applicable when the one-shot conversion mode is selected. When the sequential conversion mode is selected, the number of clock cycles is shortened by 3 cycles of the conversion clock (fAD).
Caution 1. The A/D conversion time must also be within the relevant range of conversion times (tCONV) described in 37.6.1 A/D converter characteristics.
Caution 2. Rewrite the FR2 to FR0, LV1, and LV0 bits to different values while conversion is stopped (ADCS = 0, ADCE = 0). Caution 3. The above conversion times do not include the conversion start time. Add the conversion start time to obtain the
time for the first conversion. Additionally, the conversion times do not include clock frequency errors. Consider clock frequency errors when selecting the conversion time. Caution 4. The conversion times in hardware trigger wait mode include the A/D power supply stabilization wait time from the time the hardware trigger is detected. The conversion times in software trigger wait mode include the A/D power supply stabilization wait time from the time the ADCS bit is set to 1. Caution 5. When the internal reference voltage or temperature sensor output voltage is selected as the target for A/D conversion, use low-voltage mode 2 and use a conversion clock (fAD) with a frequency no greater than 16 MHz. Caution 6. When the internal reference voltage is selected as the positive reference voltage, the conversion clock (fAD) must be in the range from 1 to 2 MHz.
Remark fCLK: CPU/peripheral hardware clock frequency
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CHAPTER 12 A/D CONVERTER (ADC)
Figure 12 - 6 A/D Converter Sampling and A/D Conversion Timing (Example for Software Trigger No-wait Mode)
1 is written to ADCS or ADS is rewritten. ADCS
Sampling timing
INTAD
Conversion start
Sampling
Successive approximation
Sampling
Successive approximation
Conversion start time
A/D conversion time
A/D conversion time
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CHAPTER 12 A/D CONVERTER (ADC)
12.3.4 A/D converter mode register 1 (ADM1)
This register is used to specify the A/D conversion trigger, conversion mode, and hardware trigger signal. The ADM1 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 12 - 7 Format of A/D Converter Mode Register 1 (ADM1)
Address: After reset: R/W:
FFF32H 00H R/W
Symbol
7
6
5
4
3
2
1
0
ADM1 ADTMD1 ADTMD0 ADSCM
0
ADLSP ADTRS2 ADTRS1 ADTRS0
ADTMD1 0 1 1
ADTMD0
Selection of the A/D conversion trigger mode
×
Software trigger no-wait mode or software trigger wait mode
0
Hardware trigger no-wait mode
1
Hardware trigger wait mode
ADLSP 0 1
4 MHz < fCLK 32 MHz 1 MHz fCLK 4 MHz
fCLK input frequency setting
ADSCM 0 1
Specification of the A/D conversion mode Sequential conversion mode One-shot conversion mode
ADTRS2 ADTRS1 ADTRS0
Selection of the hardware trigger signal
0
0
0
Timer channel 01 count or capture end interrupt signal (INTTM01)
0
1
0
Realtime clock interrupt signal (INTRTC)
0
1
1
32-bit interval timer interrupt signal (INTITL)
1
0
0
Event input from ELCL
Setting values other than the above is prohibited.
Caution 1. Only rewrite the value of the ADM1 register while conversion operation is stopped (ADCS = 0, ADCE = 0).
Caution 2. To complete A/D conversion, specify at least the following time as the hardware trigger interval: Hardware trigger no wait mode: 2 fCLK clock cycles + conversion start time + A/D conversion time Hardware trigger wait mode: 2 fCLK clock cycles + conversion start time + A/D power supply stabilization wait time + A/D conversion time
Caution 3. In modes other than SNOOZE mode, input of the next INTRTC or INTITL will not be recognized as a valid hardware trigger for up to four fCLK cycles after the first INTRTC or INTITL is input.
Remark 1. ×: Don't care Remark 2. fCLK: CPU/peripheral hardware clock frequency
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CHAPTER 12 A/D CONVERTER (ADC)
12.3.5 A/D converter mode register 2 (ADM2)
This register is used to select the + side and - side reference voltages of the A/D converter, check the upper limit and lower limit A/D conversion result values, select the resolution, and specify whether to use the SNOOZE mode. The ADM2 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 12 - 8 Format of A/D Converter Mode Register 2 (ADM2) (1/2)
Address: After reset: R/W:
F0010H 00H R/W
Symbol
7
6
5
4
ADM2 ADREFP1 ADREFP0 ADREFM
0
<3> ADRCK
<2> AWC
<1> ADTYP1
<0> ADTYP0
ADREFP1 ADREFP0
Selection of the + side reference voltage source of the A/D converter
0
0
Supplied from VDD
0
1
Supplied from P20/AVREFP/ANI0
1
0
Supplied from the internal reference voltageNote
1
1
Discharged
· Use the following procedures to rewrite the ADREFP1 and ADREFP0 bits.
(1) Set ADCE = 0
(2) Set both ADREFP1 and ADREFP0 to 1.
This step is only necessary when the values of ADREFP1 and ADREFP0 are changed to 1 and 0,
respectively.
(3) Reference voltage discharge time: 1 µs
This step is only necessary when the values of ADREFP1 and ADREFP0 are changed to 1 and 0,
respectively.
(4) Change the values of ADREFP1 and ADREFP0
(5) Reference voltage stabilization wait time (A)
(6) Set ADCE = 1
(7) Reference voltage stabilization wait time (B)
When ADREFP1 and ADREFP0 are set to 1 and 0, A = 5 µs and B = 1 s + 2 cycles of the conversion
clock (fAD). When ADREFP1 and ADREFP0 are set to 0 and 0 or 0 and 1, A needs no wait and B = 1 s + 2 cycles
of the conversion clock (fAD).
After (7) stabilization time, start the A/D conversion.
· When ADREFP1 and ADREFP0 are set to 1 and 0, respectively, A/D conversion cannot be performed on the temperature sensor output voltage and internal reference voltageNote.
Be sure to perform A/D conversion while ADISS = 0.
ADREFM
Selection of the - side reference voltage of the A/D converter
0
Supplied from VSS
1
Supplied from P21/AVREFM/ANI1
(Note and Cautions are listed on the next page.)
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CHAPTER 12 A/D CONVERTER (ADC)
Note
For details about the internal reference voltage, see CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
Caution 1. Only rewrite the value of the ADM2 register while conversion operation is stopped (ADCS = 0, ADCE = 0).
Caution 2. Do not set the ADREFP1 bit to 1 when shifting to STOP mode, or to HALT mode while the CPU is operating on the subsystem clock. When the internal reference voltage is selected (ADREFP1, ADREFP0 = 1, 0), the A/D converter reference voltage current (IADREF) indicated in 37.3.2 Supply current characteristics will be added.
Caution 3. When using AVREFP and AVREFM, specify ANI0 and ANI1 as the analog input channels and specify input mode by using the port mode register.
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Figure 12 - 8 Format of A/D Converter Mode Register 2 (ADM2) (2/2)
Address: After reset: R/W:
F0010H 00H R/W
CHAPTER 12 A/D CONVERTER (ADC)
Symbol
7
6
5
4
ADM2 ADREFP1 ADREFP0 ADREFM
0
<3> ADRCK
<2> AWC
<1> ADTYP1
<0> ADTYP0
ADRCK
Checking the upper limit and lower limit conversion result values
0
The interrupt signal (INTAD) is output when the ADLL register the ADCRn register the
ADUL register (AREA 1).
1
The interrupt signal (INTAD) is output when the ADCRn register < the ADLL register (AREA 2)
or the ADUL register < the ADCRn register (AREA 3).
Figure 12 - 9 shows the generation range of the interrupt signal (INTAD) for AREA 1 to AREA 3.
AWC
Specification of the SNOOZE mode
0
Do not use the SNOOZE mode function.
1
Use the SNOOZE mode function.
When there is a hardware trigger signal in the STOP mode, the STOP mode is exited, and A/D conversion is
performed without operating the CPU (the SNOOZE mode).
· The SNOOZE mode function can only be specified when the high-speed on-chip oscillator clock or
medium-speed on-chip oscillator clock is selected for the CPU/peripheral hardware clock (fCLK). If any other clock is selected, specifying this mode is prohibited.
· When using the SNOOZE mode function, set AWC to 0 in software trigger wait mode, and set AWC to 1 in
hardware trigger wait mode.
· Using the SNOOZE mode function in the software trigger no-wait mode or hardware trigger no-wait mode
is prohibited.
· Using the SNOOZE mode function in hardware trigger no-wait mode in sequential conversion mode is
prohibited.
· When using the SNOOZE mode function, specify a hardware trigger interval of at least "shift time to SNOOZE modeNote + conversion start time + A/D power supply stabilization wait time + A/D conversion
time + 2 fCLK clock cycles".
· Even when using SNOOZE mode, be sure to set the AWC bit to 0 in normal operation and change it to 1
just before shifting to STOP mode.
Also, be sure to change the AWC bit to 0 after returning from STOP mode to normal operation.
If the AWC bit is left set to 1, A/D conversion will not start normally in spite of the subsequent SNOOZE
mode or normal operation.
ADTYP1 ADTYP0
Selection of the A/D conversion resolution
0
0
10-bit resolution
0
1
8-bit resolution
1
0
12-bit resolution
1
1
Setting prohibited
Note Caution
Refer to "Transition time from STOP mode to SNOOZE mode" in 23.3.3 SNOOZE mode. Only rewrite the value of the ADM2 register while conversion operation is stopped (ADCS = 0, ADCE = 0).
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RL78/G23 Figure 12 - 9 ADRCK Bit Interrupt Signal Generation Range
CHAPTER 12 A/D CONVERTER (ADC)
ADCR register value (A/D conversion result)
1111111111
AREA 3 (ADUL < ADCR)
AREA 1 (ADLL ADCR ADUL)
0000000000
AREA 2 (ADCR < ADLL)
INTAD is generated when ADRCK = 1.
ADUL register setting
INTAD is generated when ADRCK = 0.
INTAD is generated when ADRCK = 1.
ADLL register setting
Remark If INTAD does not occur, the A/D conversion result is not stored in the ADCRn or ADCRnH register.
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CHAPTER 12 A/D CONVERTER (ADC)
12.3.6 12-bit/10-bit A/D conversion result register (ADCRn)
ADCRn is a 16-bit register that holds the A/D conversion result. When A/D conversion with 12-bit resolution is selected, the higher 4 bits are fixed to 0. When A/D conversion with 10-bit resolution is selected, the lower 6 bits are fixed to 0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register (SAR). The ADCRn register can be read by a 16-bit memory manipulation instruction. The value of this register is 0000H following a reset. In select mode, the conversion results are stored in the ADCR and ADCR0 registersNote. In scan mode, the conversion results of scan 0 are stored in the ADCR and ADCR0 registers, and the conversion results of scan 1 to 3 are stored in the ADCR1 to ADCR3 registersNote.
Note
If the A/D conversion result is outside the range specified by using the A/D conversion comparison function (set up by the ADRCK bit of the ADM2 register and ADUL/ADLL registers; see Figure 12 - 9), the result is not stored.
Figure 12 - 10 Format of 12-bit/10-bit A/D Conversion Result Register (ADCRn)
Address:
After reset: R/W:
FFF1FH, FFF1EH (ADCR)Note, F0021H, F0020H (ADCR0)Note, F0023H, F0022H (ADCR1), F0025H, F0024H (ADCR2), F0027H, F0026H (ADCR3) 0000H R
When A/D conversion with 12-bit resolution is selected FFF1FH (for ADCR)
FFF1EH (for ADCR)
Symbol 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ADCRn (n = 0 to 3)
0
0
0
0
When A/D conversion with 10-bit resolution is selected FFF1FH (for ADCR)
FFF1EH (for ADCR)
Symbol 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ADCRn (n = 0 to 3)
0
0
0
0
0
0
Note
The contents of the ADCR register are stored in the ADCR0 register.
Caution 1. When 8-bit resolution A/D conversion is selected (when the ADTYP1 and ADTYP0 bits of A/D converter mode register 2 (ADM2) are respectively set to 01) and the ADCRn register is read, 0 is read from the bits other than the higher 8 bits.
Caution 2. When the ADCRn register is accessed in 16-bit units, and A/D conversion with 10-bit resolution is selected, the higher 10 bits of the conversion result are read in order starting at bit 15 of the ADCRn register. When A/D conversion with 12-bit resolution is selected, the higher 12 bits of the conversion result are read in order starting at bit 11 of the ADCRn register.
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CHAPTER 12 A/D CONVERTER (ADC)
12.3.7 8-bit A/D conversion result register (ADCRnH)
ADCRnH is an 8-bit register that holds the A/D conversion result. The higher 8 bits of 12-bit resolution are storedNote. The ADCRnH register can be read by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Note
If the A/D conversion result is outside the range specified by using the A/D conversion comparison function (set up by the ADRCK bit of the ADM2 register and ADUL/ADLL registers; see Figure 12 - 9), the result is not stored.
Figure 12 - 11 Format of 8-bit A/D Conversion Result Register (ADCRnH)
Address:
After reset: R/W:
FFF1FH (ADCRH)Note, F0021H (ADCR0H)Note, F0023H (ADCR1H), F0025H (ADCR2H), F0027H (ADCR3H) 00H R
Symbol
7
6
5
4
3
2
1
0
ADCRnH (n = 0 to 3)
Note
The contents of the ADCRH register are stored in the ADCR0H register.
Caution
When writing to any of the following registers, the contents of the ADCRnH register may become undefined: A/D converter mode register 0 (ADM0), analog input channel specification register (ADS), port mode control A registers 0, 2, 3, 10, 11, 12, 14, and 15 (PMCA0, PMCA2, PMCA3, PMCA10, PMCA11, PMCA12, PMCA14, and PMCA15), port mode control T registers 0, 2, and 15 (PMCT0, PMCT2, and PMCT15), and port mode control E register 0 (PMCE0) Read the conversion result following conversion completion before writing to the ADM0, ADS, PMCAxx, PMCTxx, or PMCEx register. Using timing other than the above may cause an incorrect conversion result to be read.
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CHAPTER 12 A/D CONVERTER (ADC)
12.3.8 Analog input channel specification register (ADS)
This register specifies the input channel of the analog voltage to be A/D converted. The ADS register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 12 - 12 Format of Analog Input Channel Specification Register (ADS)
Address: After reset: R/W:
FFF31H 00H R/W
Symbol
7
6
ADS ADISS
0
5
4
3
2
1
0
0
ADS4
ADS3
ADS2
ADS1
ADS0
<Select mode (ADMD = 0)> (1/2)
ADISS ADS4 ADS3 ADS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
ADS1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
Analog input ADS0
channel
Input source
0 ANI0
P20/ANI0/AVREFP pin
1 ANI1
P21/ANI1/AVREFM pin
0 ANI2
P22/ANI2 pin
1 ANI3
P23/ANI3 pin
0 ANI4
P24/ANI4 pin
1 ANI5
P25/ANI5 pin
0 ANI6
P26/ANI6 pin
1 ANI7
P27/ANI7 pin
0 ANI8
P150/ANI8 pin
1 ANI9
P151/ANI9 pin
0 ANI10
P152/ANI10 pin
1 ANI11
P153/ANI11 pin
0 ANI12
P154/ANI12 pin
1 ANI13
P155/ANI13 pin
0 ANI14
P156/ANI14 pin
1 Setting prohibited
0 ANI16
P03/ANI16 pinNote 1
1 ANI17
P02/ANI17 pinNote 2
0 ANI18
P147/ANI18 pin
1 ANI19
P120/ANI19 pin
0 ANI20
P100/ANI20 pin
1 ANI21
P37/ANI21 pin
0 ANI22
P36/ANI22 pin
1 ANI23
P35/ANI23 pin
0 ANI24
P117/ANI24 pin
1 ANI25
P116/ANI25 pin
0 ANI26
P115/ANI26 pin
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CHAPTER 12 A/D CONVERTER (ADC)
<Select mode (ADMD = 0)> (2/2)
ADISS ADS4
ADS3
ADS2
ADS1
ADS0
Analog input channel
Input source
0
1
1
0
1
1 Setting prohibited
1
0
0
0
0
0
1
0
0
0
0
1
--
Temperature sensor output
voltage
--
Internal reference voltageNote 3
Note 1. Note 2. Note 3.
Other than the above
Setting prohibited
30-, 32-pin products: P01/ANI16 pin 30-, 32-pin products: P00/ANI17 pin For details about the internal reference voltage, see CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
<Scan mode (ADMD = 1)>
ADISS ADS4 ADS3 ADS2 ADS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
0
1
Other than the above
ADS0
Scan 0
Analog input channel Scan 1 Scan 2
Scan 3
0 ANI0
ANI1
ANI2
ANI3
1 ANI1
ANI2
ANI3
ANI4
0 ANI2
ANI3
ANI4
ANI5
1 ANI3
ANI4
ANI5
ANI6
0 ANI4
ANI5
ANI6
ANI7
1 ANI5
ANI6
ANI7
ANI8
0 ANI6
ANI7
ANI8
ANI9
1 ANI7
ANI8
ANI9
ANI10
0 ANI8
ANI9
ANI10
ANI11
1 ANI9
ANI10
ANI11
ANI12
0 ANI10
ANI11
ANI12
ANI13
1 ANI11
ANI12
ANI13
ANI14
Setting prohibited
(Cautions are listed on the next page.)
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Caution 1. Be sure to clear bits 6 and 5 to 0. Caution 2. Set the channel that is specified as the analog input by a PMCAxx, PMCTxx, or PMCEx register to the
input mode by using port mode registers 0, 2, 3, 10 to 12, 14, or 15 (PM0, PM2, PM3, PM10 to PM12, PM14, PM15). Caution 3. When specifying an input channel by the ADS register, do not select the pin that is specified as digital I/O by port mode control A register 0, 2, 3, 10, 11, 12, 14, or 15 (PMCA0, PMCA2, PMCA3, PMCA10, PMCA11, PMCA12, PMCA14, or PMCA15), port mode control T register 0, 2, or 15 (PMCT0, PMCT2, or PMCT15), or port mode control E register 0 (PMCE0). Caution 4. Rewrite the value of the ADISS bit while conversion is stopped (ADCS = 0, ADCE = 0). Caution 5. If using AVREFP as the + side reference voltage of the A/D converter, do not select ANI0 as an A/D conversion channel. Caution 6. If using AVREFM as the side reference voltage of the A/D converter, do not select ANI1 as an A/D conversion channel. Caution 7. If the ADISS bit is set to 1, the internal reference voltage cannot be used for the + side reference voltage. After the ADISS bit is set to 1, the initial conversion result cannot be used. For the setting flow, see 12.7.5 Example of using the ADC when selecting the temperature sensor output voltage or internal reference voltage, and software trigger no-wait mode and one-shot conversion mode. For details about the internal reference voltage, see CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C. Caution 8. Do not set the ADISS bit to 1 when shifting to STOP mode, or to HALT mode while the CPU is operating on the subsystem clock. When the ADISS bit is set to 1, the A/D converter reference voltage current (IADREF) indicated in 37.3.2 Supply current characteristics will be added.
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12.3.9 Conversion result comparison upper limit setting register (ADUL)
This register is used to specify the setting for checking the upper limit of the A/D conversion results. The A/D conversion results and ADUL register value are compared, and interrupt signal (INTAD) generation is controlled in the range specified by the ADRCK bit of A/D converter mode register 2 (ADM2) (shown in Figure 12 - 9 ADRCK Bit Interrupt Signal Generation Range). The ADUL register can be set by an 8-bit memory manipulation instruction. The value of this register is FFH following a reset.
Figure 12 - 13 Format of Conversion Result Comparison Upper Limit Setting Register (ADUL)
Address: After reset: R/W:
F0011H FFH R/W
Symbol ADUL
7 ADUL7
6 ADUL6
5 ADUL5
4 ADUL4
3 ADUL3
2 ADUL2
1 ADUL1
0 ADUL0
12.3.10 Conversion result comparison lower limit setting register (ADLL)
This register is used to specify the setting for checking the lower limit of the A/D conversion results. The A/D conversion results and ADLL register value are compared, and interrupt signal (INTAD) generation is controlled in the range specified by the ADRCK bit of A/D converter mode register 2 (ADM2) (shown in Figure 12 - 9 ADRCK Bit Interrupt Signal Generation Range). The ADLL register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 12 - 14 Format of Conversion Result Comparison Lower Limit Setting Register (ADLL)
Address: After reset: R/W:
F0012H 00H R/W
Symbol ADLL
7 ADLL7
6 ADLL6
5 ADLL5
4 ADLL4
3 ADLL3
2 ADLL2
1 ADLL1
0 ADLL0
Caution 1. When A/D conversion with 10-bit resolution is selected, the A/D conversion result register ADCRn[15:8] value is compared with the values in the ADUL and ADLL registers. When A/D conversion with 12-bit resolution is selected, the A/D conversion result register ADCRn[11:4] value is compared with the values in the ADUL and ADLL registers.
Caution 2. Only write new values to the ADUL and ADLL registers while conversion is stopped (ADCS = 0, ADCE = 0).
Caution 3. The setting of the ADUL register must be greater than that of the ADLL register.
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12.3.11 A/D test register (ADTES)
This register is used to select the + side reference voltage or - side reference voltage for the converter, an analog input channel (ANIxx), the temperature sensor output voltage, or the internal reference voltageNote as the target for A/D conversion. When using this register to test the converter, set as follows. · For zero-scale measurement, select the - side reference voltage as the target for conversion. · For full-scale measurement, select the + side reference voltage as the target for conversion. The ADTES register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 12 - 15 Format of A/D Test Register (ADTES)
Address: After reset: R/W:
F0013H 00H R/W
Symbol
7
6
5
4
3
2
1
0
ADTES
0
0
0
0
0
0
ADTES1 ADTES0
ADTES1 ADTES0
A/D conversion target
0
0
ANIxx/temperature sensor output voltage/internal reference voltageNote
(Set by analog input channel specification register (ADS))
1
0
The - side reference voltage (selected by the ADREFM bit of the ADM2 register)
1
1
The + side reference voltage (selected by the ADREFP1 and ADREFP0 bits of
the ADM2 register)
Other than the above Setting prohibited
Note
For details about the internal reference voltage, see CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
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12.3.12 Registers controlling port function of analog input pins
Set up the registers for controlling the functions of the ports shared with the analog input pins of the A/D converter (port mode registers (PMxx), port mode control A registers (PMCAxx), port mode control T registers (PMCTxx), and port mode control E register (PMCEx)). For details see 4.3.1 Port mode registers (PMxx), 4.3.7 Port mode control A registers (PMCAxx), 4.3.8 Port mode control T registers (PMCTxx), and 4.3.9 Port mode control E registers (PMCEx).
When using the ANI0 to ANI14 and ANI16 to ANI26 pins for analog input of the A/D converter, set the port mode register (PMxx) bit and port mode control A register (PMCAxx) bit corresponding to each port to 1.
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CHAPTER 12 A/D CONVERTER (ADC)
12.4
A/D Converter Operations
The A/D converter conversion operations are described below.
<1> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <2> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the
sampled voltage is held until the A/D conversion operation has ended. <3> Bit 11 of the successive approximation register (SAR) is set to 1. The series resistor string voltage tap is set to 1/2
AVREF by the tap selector. <4> The voltage difference between the series resistor string voltage tap and sampled voltage is compared by the
voltage comparator. If the analog input is greater than 1/2 AVREF, the MSB of the SAR register remains set to 1. If the analog input is smaller than 1/2 AVREF, the MSB is reset to 0. <5> Next, bit 10 of the SAR register is automatically set to 1, and the operation proceeds to the next comparison. The series resistor string voltage tap is selected according to the preset value of bit 11, as described below. · Bit 11 = 1: (3/4) AVREF · Bit 11 = 0: (1/4) AVREF The voltage tap and sampled voltage are compared and bit 10 of the SAR register is manipulated as follows.
· Sampled voltage Voltage tap: Bit 10 = 1 · Sampled voltage < Voltage tap: Bit 10 = 0 <6> Comparison is continued in this way up to bit 0 of the SAR register. <7> Upon completion of the comparison of 12 bits, an effective digital result value remains in the SAR register, and the result value is transferred to the A/D conversion result register (ADCRn, ADCRnH) and then latchedNote 1. At the same time, the A/D conversion end interrupt request signal (INTAD) can also be generatedNote 1. <8> Repeat steps <1> to <7>, until the ADCS bit is cleared to 0Note 2. To stop the A/D converter, clear the ADCS bit to 0.
Note 1. Note 2.
If the A/D conversion result is outside the A/D conversion result range specified by the ADRCK bit and the ADUL and ADLL registers (see Figure 12 - 9 ADRCK Bit Interrupt Signal Generation Range), the A/D conversion end interrupt request signal is not generated and no A/D conversion results are stored in the ADCRn and ADCRnH registers. While in the sequential conversion mode, the ADCS flag is not automatically cleared to 0. This flag is not automatically cleared to 0 while in the one-shot conversion mode of the hardware trigger no-wait mode, either. Instead, 1 is retained.
Remark 1. Two types of the A/D conversion result registers are available. · ADCRn register (16 bits): Store 12-bit/10-bit A/D conversion value · ADCRnH register (8 bits): Store 8-bit A/D conversion value
Remark 2. AVREF: The + side reference voltage of the A/D converter. This can be selected from AVREFP, the internal reference voltage, and VDD. For details about the internal reference voltage, see CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
Remark 3. n = 0 to 3
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Figure 12 - 16 Conversion Operation of A/D Converter (Software Trigger No-wait Mode)
1 is written to ADCS
ADCS
Conversion Sampling
start time
time
A/D converter Conversion Conversion Sampling
operation standby
start
SAR
Undefined
ADCRn
INTAD
Conversion time A/D conversion
Conversion standby
Conversion result
Conversion result
In one-shot conversion mode, the ADCS bit is automatically cleared to 0 after completion of A/D conversion. In sequential conversion mode, A/D conversion operations proceed continuously until the software clears bit 7 (ADCS) of the A/D converter mode register 0 (ADM0) to 0. Writing to the analog input channel specification register (ADS) during A/D conversion interrupts the current conversion after which A/D conversion of the analog input specified by the ADS register proceeds. Data from the A/D conversion that was in progress are discarded. The value of the A/D conversion result register (ADCRn, ADCRnH) is 00H or 0000H following a reset.
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12.5
Input Voltage and Conversion Results
The relationship between the analog voltage input to the analog input pins (ANI0 to ANI14, ANI16 to ANI26) and the theoretical A/D conversion result (stored in the 12-bit/10-bit A/D conversion result register (ADCRn)) is shown by the following expression.
VAIN
ADCRn = INT (
× 4096 + 0.5)
AVREF
or
AVREF
AVREF
(ADCRn - 0.5) ×
VAIN < (ADCRn + 0.5) ×
4096
4096
where, INT( ): Function which returns integer part of value in parentheses VAIN: Analog input voltage AVREF: AVREF pin voltage ADCRn: 12-bit/10-bit A/D conversion result register (ADCRn) value
Figure 12 - 17 shows Relationship Between Analog Input Voltage and A/D Conversion Result.
Figure 12 - 17 Relationship Between Analog Input Voltage and A/D Conversion Result
SAR
ADCRn
4095
0FFFH
4094
0FFEH
A/D conversion result
4093 3
0FFDH 0003H
2
0002H
1
0001H
0
1 1325 3 8192 4096 8192 4096 8192 4096
0000H 8187 4094 8189 4095 8191 1 8192 4096 8192 4096 8192
Input voltage/AVREF
Remark
AVREF: The + side reference voltage of the A/D converter. This can be selected from AVREFP, the internal reference voltageNote, and VDD.
Note
For details about the internal reference voltage, see CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
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CHAPTER 12 A/D CONVERTER (ADC)
12.6
A/D Converter Operation Modes
The operation of each A/D converter mode is described below. In addition, the procedure for specifying each mode is described in 12.7 A/D Converter Setup Flowchart.
12.6.1 Software trigger no-wait mode (select mode, sequential conversion mode)
<1> In the stop state, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the A/D converter enters the standby state.
<2> After the software counts up to the stabilization wait time (1 µs + 2 cycles of the conversion clock (fAD)), the ADCS bit of the ADM0 register is set to 1 to perform the A/D conversion of the analog input specified by the analog input channel specification register (ADS).
<3> When A/D conversion ends, the conversion result is stored in the A/D conversion result registers (ADCR, ADCRH, ADCR0, and ADCR0H), and the A/D conversion end interrupt request signal (INTAD) is generated. After A/D conversion ends, the next A/D conversion immediately starts.
<4> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded.
<5> When the value of the ADS register is written during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register. The partially converted data is discarded.
<6> Even if a hardware trigger is input during conversion operation, A/D conversion does not start. <7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the A/D
converter enters the standby state. <8> When ADCE is cleared to 0 while in the A/D conversion standby state, the A/D converter enters the stop state.
Figure 12 - 18 Example of Software Trigger No-Wait Mode (Select Mode, Sequential Conversion Mode) Operation Timing
<1> ADCE is set to 1.
ADCE is cleared to 0. <8>
ADCE
The trigger is not
ADCS acknowledged.
<2> ADCS is set to 1 while in the conversion standby state.
<4>
ADCS is overwritten with 1 during A/D
conversion operation.
<6>
A is
hardware trigger generated
(and ignored).
ADCS
is cleared to 0 during A/D
<7>
conversion operation.
ADS is rewritten during <5> A/D conversion operation
(from ANI0 to ANI1).
The trigger is not acknowledged.
ADS
A/D conversion
state
Stop Conversion state standby
Data 0 (ANI0)
<3>Aen/Ddscoannvderthsieonnex<t 3> conversion starts.
Data 0 (ANI0)
Data 0 (ANI0)
Data 0 (ANI0)
Conversion is <3> interrupted and restarts.
Data 0 (ANI0)
Data 0 (ANI0)
Data 1 (ANI1)
<3>
<3>
Data 1 (ANI1)
Data 1 (ANI1)
Data 1 (ANI1)
Conversion is interrupted.
Conversion Stop standby state
ADCR0, ADCR0H
Data 0 (ANI0)
Data 0 (ANI0)
Data 0 (ANI0)
Data 1 (ANI1)
Data 1 (ANI1)
INTAD
Caution
When <4> or <5> is detected while conversion is in progress, conversion is automatically restarted from the rising edge of the next cycle of the conversion clock (fAD). The conversion time at the first conversion operation restarted is the same as that when there is A/D power supply stabilization wait time in software trigger wait mode or hardware trigger wait mode. (See Table 12 - 3 A/D Conversion Time Selection (3/8) and Table 12 - 3 A/D Conversion Time Selection (4/8).)
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12.6.2 Software trigger no-wait mode (select mode, one-shot conversion mode)
<1> In the stop state, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the A/D converter enters the standby state.
<2> After the software counts up to the stabilization wait time (1 µs + 2 cycles of the conversion clock (fAD)), the ADCS bit of the ADM0 register is set to 1 to perform the A/D conversion of the analog input specified by the analog input channel specification register (ADS).
<3> When A/D conversion ends, the conversion result is stored in the A/D conversion result registers (ADCR, ADCRH, ADCR0, and ADCR0H), and the A/D conversion end interrupt request signal (INTAD) is generated.
<4> After A/D conversion ends, the ADCS bit is automatically cleared to 0, and the A/D converter enters the standby state.
<5> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded.
<6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register. The partially converted data is discarded.
<7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the A/D converter enters the standby state.
<8> When ADCE is cleared to 0 while in the A/D conversion standby state, the A/D converter enters the stop state. In addition, A/D conversion does not start even if a hardware trigger is input while in the A/D conversion standby state.
Figure 12 - 19 Example of Software Select No-Wait Mode (Select Mode, One-Shot Conversion Mode) Operation Timing
<1> ADCE is set to 1.
ADCE is cleared to 0.<8>
ADCE
The trigger is not
acknowledged. ADCS
ADCS is set to <2> 1 while in the
conversion standby state.
ADCS is <4> automatically <2>
cleared to 0 after conversion ends.
<5>
ADCS is overwritten with 1 during A/D
<4>
conversion operation.
<2>
<4>
<6> ADS is rewritten during A/D conversion operation
(from ANI0 to ANI1).
<2>
<7> ADCS is cleared to 0 during A/D conversion operation.
The trigger is not acknowledged.
ADS
A/D conversion
state
Stop Conversion state standby
Data 0 (ANI0)
Data 0 (ANI0)
A/D <3>conversion
ends.
Conversion standby
Data 0 (ANI0)
Conversion is interrupted and restarts.
Data 0 (ANI0)
<3>
Conversion standby
Data 0 (ANI0)
Data 1 (ANI1)
Data 1 (ANI1)
Conversion is
<3>
interrupted.
Conversion Data 1 standby (ANI1)
Conversion Stop standby state
ADCR0, ADCR0H
INTAD
Data 0 (ANI0)
Data 0 (ANI0)
Data 1 (ANI1)
Caution
When <4>, <5>, or <6> is detected while conversion is in progress, conversion is automatically restarted from the rising edge of the next cycle of the conversion clock (fAD). The conversion time at the first conversion operation restarted is the same as that when there is A/D power supply stabilization wait time in software trigger wait mode or hardware trigger wait mode. (See Table 12 - 3 A/D Conversion Time Selection (3/8) and Table 12 - 3 A/D Conversion Time Selection (4/8).)
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12.6.3 Software trigger no-wait mode (scan mode, sequential conversion mode)
<1> In the stop state, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the A/D converter enters the standby state.
<2> After the software counts up to the stabilization wait time (1 µs + 2 cycles of the conversion clock (fAD)), the ADCS bit of the ADM0 register is set to 1 to perform A/D conversion on the four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel specification register (ADS). A/D conversion is performed on the analog input channels in order, starting with that specified by scan 0.
<3> A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in the A/D conversion result register (ADCRn, ADCRnH) each time conversion ends, and the A/D conversion end interrupt request signal (INTAD) is generated immediately after A/D conversion of the four channels ends. After A/D conversion of the four channels ends, the next A/D conversion of the specified channels automatically starts (until all four channels are finished).
<4> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts at the first channel. The partially converted data is discarded.
<5> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register. The partially converted data is discarded.
<6> Even if a hardware trigger is input during conversion operation, A/D conversion does not start. <7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the A/D
converter enters the standby state. <8> When ADCE is cleared to 0 while in the A/D conversion standby state, the A/D converter enters the stop state.
Figure 12 - 20 Example of Software Trigger No-Wait Mode (Scan Mode, Sequential Conversion Mode) Operation Timing
<1> ADCE is set to 1.
ADCE is cleared to 0.<8>
ADCE
The trigger is not
acknowledged.
ADCS
<2> ADCS is set to 1 while in the conversion standby state.
<4>
ADCS is overwritten with 1 during A/D
conversion operation.
A hardware generated (and
trigger is ignored).
<6> ADCS is cleared to 0 during A/D
conversion operation.
<7>
The trigger is not
acknowledged.
<5> ADS is rewritten during A/D conversion operation.
ADS
A/D conversion
state
ANI0 to ANI3
ANI4 to ANI7
A/D conversion ends and the <3> next conversion starts.
Conversion is
<3>
interrupted and restarts.
Conversion is
<3>
interrupted and restarts.
Conversion is interrupted.
Stop Conversion Data 0 Data 1 Data 2 Data 3 Data 0 Data 1 Data 0 Data 1 Data 2 Data 3 Data 0 Data 1 Data 4 Data 5 Data 6 Data 7 Data 4 Data 5 Conversion Stop state standby (ANI0) (ANI1) (ANI2) (ANI3) (ANI0) (ANI1) (ANI0) (ANI1) (ANI2) (ANI3) (ANI0) (ANI1) (ANI4) (ANI5) (ANI6) (ANI7) (ANI4) (ANI5) standby state
ADCR0 ADCR0H
Data 0 (ANI0)
Data 0 (ANI0)
Data 0 (ANI0)
Data 0 (ANI0)
Data 4 (ANI4)
Data 4 (ANI4)
ADCR1 ADCR1H
Data 1 (ANI1)
Data 1 (ANI1)
Data 5 (ANI5)
ADCR2 ADCR2H
Data 2 (ANI2)
Data 2 (ANI2)
Data 6 (ANI6)
ADCR3 ADCR3H
INTAD
Data 3 (ANI3)
Data 3 (ANI3)
Data 7 (ANI7)
An interrupt request signal is generated immediately after the fourth A/D conversion ends.
An interrupt request signal is generated immediately after the fourth A/D conversion ends.
An interrupt request signal is generated immediately after the fourth A/D conversion ends.
Caution
When <4> or <5> is detected while conversion is in progress, conversion is automatically restarted from the rising edge of the next cycle of the conversion clock (fAD). The conversion time at the first conversion operation restarted is the same as that when there is A/D power supply stabilization wait time in software trigger wait mode or hardware trigger wait mode. (See Table 12 - 3 A/D Conversion Time Selection (3/8) and Table 12 - 3 A/D Conversion Time Selection (4/8).)
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12.6.4 Software trigger no-wait mode (scan mode, one-shot conversion mode)
<1> In the stop state, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the A/D converter enters the standby state.
<2> After the software counts up to the stabilization wait time (1 µs + 2 cycles of the conversion clock (fAD)), the ADCS bit of the ADM0 register is set to 1 to perform A/D conversion on the four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel specification register (ADS). A/D conversion is performed on the analog input channels in order, starting with that specified by scan 0.
<3> A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in the A/D conversion result register (ADCRn, ADCRnH) each time conversion ends, and the A/D conversion end interrupt request signal (INTAD) is generated immediately after A/D conversion of the four channels ends.
<4> After A/D conversion of the four channels ends, the ADCS bit is automatically cleared to 0, and the A/D converter enters the standby state.
<5> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts at the first channel. The partially converted data is discarded.
<6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register. The partially converted data is discarded.
<7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the A/D converter enters the standby state.
<8> When ADCE is cleared to 0 while in the A/D conversion standby state, the A/D converter enters the stop state. In addition, A/D conversion does not start even if a hardware trigger is input while in the A/D conversion standby state.
Figure 12 - 21 Example of Software Trigger No-Wait Mode (Scan Mode, One-Shot Conversion Mode) Operation Timing
<1> ADCE is set to 1.
ADCE is cleared to 0. <8>
ADCE
The trigger is not
acknowledged. ADCS
<2>ADCS is set to 1 while in the conversion standby state.
<4> ADCS is automatically <2> cleared to
0 after conversion ends.
<5>
ADCS is overwritten with 1 during A/D
<4>
<2>
conversion operation.
ADCS is cleared to 0 during A/D
<7>
conversion operation.
The trigger is not acknowledged.
<6> ADS is rewritten during A/D conversion operation.
ADS
A/D conversion
state
ANI0 to ANI3
Stop Conversion Data 0 Data 1 state standby (ANI0) (ANI1)
Data 2 (ANI2)
ANI4 to ANI7
<3> A/D conversion ends.
Conversion is interrupted and
restarts.<3>
Conversion is interrupted and restarts.
Conversion is interrupted.
Data 3 Conversion Data 0 Data 1 Data 0 Data 1 Data 2 Data 3 Conversion Data 0 Data 1 Data 4 Data 5 (ANI3) standby (ANI0) (ANI1) (ANI0) (ANI1) (ANI2) (ANI3) standby (ANI0) (ANI1) (ANI4) (ANI5)
Data 6 (ANI6)
Data 7 Conversion Stop (ANI7) standby state
ADCR0 ADCR0H
Data 0 (ANI0)
Data 0 (ANI0) Data 0 (ANI0)
Data 0 (ANI0)
Data 4 (ANI4)
ADCR1 ADCR1H
Data 1 (ANI1)
Data 1 (ANI1)
Data 5 (ANI5)
ADCR2 ADCR2H
ADCR3 ADCR3H
INTAD
Data 2 (ANI2)
Data 3 (ANI3) An interrupt request signal is generated immediately after the fourth A/D conversion ends.
Data 2 (ANI2)
Data 3 (ANI3) An interrupt request signal is generated immediately after the fourth A/D conversion ends.
Data 6 (ANI6)
Caution
When <4>, <5>, or <6> is detected while conversion is in progress, conversion is automatically restarted from the rising edge of the next cycle of the conversion clock (fAD). The conversion time at the first conversion operation restarted is the same as that when there is A/D power supply stabilization wait time in software trigger wait mode or hardware trigger wait mode. (See Table 12 - 3 A/D Conversion Time Selection (3/8) and Table 12 - 3 A/D Conversion Time Selection (4/8).)
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12.6.5 Software trigger wait mode (select mode, sequential conversion mode)
<1> To shift to software trigger wait mode, the ADCE bit of A/D converter mode register 0 (ADM0) must be set to 0 (stop state).
<2> If ADCS is set to 1 in the stop state, A/D conversion is performed on the analog input specified by the analog input channel specification register (ADS) (software trigger wait mode).
<3> When A/D conversion ends, the conversion result is stored in the A/D conversion result registers (ADCR, ADCRH, ADCR0, and ADCR0H), and the A/D conversion end interrupt request signal (INTAD) is generated. After A/D conversion ends, the next A/D conversion immediately starts.
<4> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded.
<5> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register. The partially converted data is discarded.
<6> Even if a hardware trigger is input during conversion operation, A/D conversion does not start. <7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the A/D
converter enters the stop state.
Figure 12 - 22 Example of Software Trigger Wait Mode (Select Mode, Sequential Conversion Mode) Operation Timing
ADCE
ADCS
ADS
A/D conversion
state ADCR0, ADCR0H
INTAD
<1> ADCE = 0
<2> ADCS is set to 1 while in the conversion standby state.
<4> ADCS is overwritten with 1 during A/D conversion operation.
<6> A hardware trigger is generated (and ignored).
<7> ADCS is cleared to 0 during A/D conversion operation.
Stop state
Data 0 (ANI0)
<3>A/D conversion <3> ends and the next
conversion starts.
Data 0 (ANI0)
Data 0 (ANI0)
Data 0 (ANI0)
<5> ADS is rewritten (from ANI0 to ANI1) during A/D conversion operation.
Conversion is <3> interrupted and
restarts.
Data 0 (ANI0)
Data 0 (ANI0)
Data 1 (ANI1)
<3>
<3>
Data 1 (ANI1)
Data 1 (ANI1)
Data 1 (ANI1)
Conversion is interrupted.
Stop state
Data 0 (ANI0)
Data 0 (ANI0)
Data 0 (ANI0)
Data 1 (ANI1)
Data 1 (ANI1)
Caution
When <4> or <5> is detected during conversion operation, conversion is restarted automatically after the stabilization wait time has passed since the rising edge of the next conversion clock (fAD). The conversion time at the first conversion operation restarted is the same as that when there is A/D power supply stabilization wait time in software trigger wait mode or hardware trigger wait mode. (See Table 12 - 3 A/D Conversion Time Selection (3/8) and Table 12 - 3 A/D Conversion Time Selection (4/8).)
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12.6.6 Software trigger wait mode (select mode, one-shot conversion mode)
<1> To shift to software trigger wait mode, the ADCE bit of A/D converter mode register 0 (ADM0) must be set to 0 (stop state).
<2> If ADCS is set to 1 in the stop state, A/D conversion is performed on the analog input specified by the analog input channel specification register (ADS) (software trigger wait mode).
<3> When A/D conversion ends, the conversion result is stored in the A/D conversion result registers (ADCR, ADCRH, ADCR0, and ADCR0H), and the A/D conversion end interrupt request signal (INTAD) is generated.
<4> After A/D conversion ends, the ADCS bit is automatically cleared to 0, and the A/D converter enters the stop state. <5> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is initialized. <6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register. The partially converted data is discarded. <7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the A/D converter enters the stop state. <8> When a hardware trigger is input during conversion operation, the trigger is not accepted.
Figure 12 - 23 Example of Software Trigger Wait Mode (Select Mode, One-Shot Conversion Mode) Operation Timing
ADCE
ADCS
ADS
A/D conversion
state ADCR0, ADCR0H
INTAD
<1> ADCE = 0
<2>
ADCS is set while in the
to
1
conversion
standby state.
<3>ADCS is
<2>
automatically
cleared to 0 after
conversion ends.
<5> ADCS is overwritten <4> with 1 during A/D conversion operation.
<2>
<8>
A hardware trigger is generated (and
<4>
ignored).
<2>
<7> ADCS is cleared to 0 during A/D conversion operation.
<6>ADS is rewritten (from ANI0 to ANI1) during A/D conversion operation.
Data 0 (ANI0)
Data 1 (ANI1)
Stop state
Data 0 (ANI0)
<3>Aen/Ddsc.onversion
Stop state
Data 0 (ANI0)
Conversion is interrupted and restarts.
Data 0 (ANI0)
<3> Stop state
Data 0 (ANI0)
Data 1 (ANI1)
<3>
Stop state
Data 1 (ANI1)
Conversion is interrupted.
Stop state
Data 0 (ANI0)
Data 0 (ANI0)
Data 1 (ANI1)
Caution
When <4>, <5>, or <6> is detected during conversion operation, conversion is restarted automatically after the stabilization wait time has passed since the rising edge of the next conversion clock (fAD). The conversion time at the first conversion operation restarted is the same as that when there is A/D power supply stabilization wait time in software trigger wait mode or hardware trigger wait mode. (See Table 12 - 3 A/D Conversion Time Selection (3/8) and Table 12 - 3 A/D Conversion Time Selection (4/8).)
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12.6.7 Software trigger wait mode (scan mode, sequential conversion mode)
<1> To shift to software trigger wait mode, the ADCE bit of A/D converter mode register 0 (ADM0) must be set to 0 (stop state).
<2> If ADCS is set to 1 in the stop state, A/D conversion is performed on the four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel specification register (ADS) (software trigger wait mode). A/D conversion is performed on the analog input channels in order, starting with that specified by scan 0.
<3> A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in the A/D conversion result register (ADCRn, ADCRnH) each time conversion ends, and the A/D conversion end interrupt request signal (INTAD) is generated immediately after A/D conversion of the four channels ends. After A/D conversion of the four channels ends, the next A/D conversion of the specified channels automatically starts.
<4> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded.
<5> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register. The partially converted data is discarded.
<6> When a hardware trigger is input during conversion operation, the trigger is not accepted. <7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the A/D
converter enters the stop state.
Figure 12 - 24 Example of Software Trigger Wait Mode (Scan Mode, Sequential Conversion Mode) Operation Timing
ADCE
ADCS
ADS
A/D conversion
state ADCR0 ADCR0H ADCR1 ADCR1H ADCR2 ADCR2H ADCR3 ADCR3H
INTAD
<1> ADCE = 0
<2> ADCS is set to 1 while in the conversion standby state.
<4> ADCS is overwritten with 1 during A/D conversion operation.
<6> A hardware trigger is <7> ADCS is cleared to 0 generated (and ignored). during A/D conversion operation.
<5> ADS is rewritten during A/D conversion operation.
ANI0 to ANI3
ANI4 to ANI7
A/D conversion ends and <3> the next conversion starts.
Conversion is interrupted and restarts.
<3>
Conversion is interrupted and restarts.
<3>
Stop state
Data 0 Data 1 (ANI0) (ANI1)
Data 2 (ANI2)
Data 3 Data 0 Data 1 Data 0 Data 1 Data 2 Data 3 Data 0 Data 1 Data 4 Data 5 Data 6 Data 7 Data 4 Data 5 (ANI3) (ANI0) (ANI1) (ANI0) (ANI1) (ANI2) (ANI3) (ANI0) (ANI1) (ANI4) (ANI5) (ANI6) (ANI7) (ANI4) (ANI5)
Conversion is interrupted.
Stop state
Data 0 (ANI0)
Data 0 (ANI0)
Data 0 (ANI0)
Data 0 (ANI0)
Data 4 (ANI4)
Data 4 (ANI4)
Data 1 (ANI1)
Data 1 (ANI1)
Data 5 (ANI5)
Data 2 (ANI2)
Data 2 (ANI2)
Data 6 (ANI6)
Data 3 (ANI3)
An interrupt request signal is generated immediately after the fourth A/D conversion ends.
Data 3 (ANI3)
An interrupt request signal is generated immediately after the fourth A/D conversion ends.
Data 7 (ANI7)
An interrupt request signal is generated immediately after the fourth A/D conversion ends.
Caution
When <4> or <5> is detected during conversion operation, conversion is restarted automatically after the stabilization wait time has passed since the rising edge of the next conversion clock (fAD). The conversion time at the first conversion operation restarted is the same as that when there is A/D power supply stabilization wait time in software trigger wait mode or hardware trigger wait mode. (See Table 12 - 3 A/D Conversion Time Selection (3/8) and Table 12 - 3 A/D Conversion Time Selection (4/8).)
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12.6.8 Software trigger wait mode (scan mode, one-shot conversion mode)
<1> To shift to software trigger wait mode, the ADCE bit of A/D converter mode register 0 (ADM0) must be set to 0 (stop state).
<2> If ADCS is set to 1 in the stop state, A/D conversion is performed on the four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel specification register (ADS) (software trigger wait mode). A/D conversion is performed on the analog input channels in order, starting with that specified by scan 0.
<3> A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in the A/D conversion result register (ADCRn, ADCRnH) each time conversion ends, and the A/D conversion end interrupt request signal (INTAD) is generated immediately after A/D conversion of the four channels ends.
<4> After A/D conversion ends, the ADCS bit is automatically cleared to 0, and the A/D converter enters the stop state. <5> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is discarded. <6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register. The partially converted data is discarded. <7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the A/D converter enters the stop state. <8> When a hardware trigger is input during conversion operation, the trigger is not accepted.
Figure 12 - 25 Example of Software Trigger Wait Mode (Scan Mode, One-Shot Conversion Mode) Operation Timing
ADCE
ADCS
ADS
A/D conversion
state ADCR0 ADCR0H ADCR1 ADCR1H ADCR2 ADCR2H ADCR3 ADCR3H
INTAD
<1> ADCE = 0
<2> ADCS is set to 1 while in the conversion
standby state.
<4>
ADCS is
<2>
automatically
cleared to 0 after
conversion ends.
<5> ADCS is overwritten with 1 during A/D conversion operation.
<4>
<2>
<8> A hardware trigger is generated (and ignored).
<7> ADCS is cleared to 0 during A/D conversion operation.
<6> ADS is rewritten during A/D conversion operation.
ANI0 to ANI3
ANI4 to ANI7
Stop state
Data 0 (ANI0)
Data 1 (ANI1)
Data 2 (ANI2)
<3> A/D conversion ends.
Data 3 (ANI3)
Stop state
Data 0 (ANI0)
Data 1 (ANI1)
Conversion is
<3>
interrupted and restarts.
Data 0 (ANI0)
Data 1 (ANI1)
Data 2 (ANI2)
Data 3 (ANI3)
Stop state
Data 0 Data 1 (ANI0) (ANI1)
Conversion is interrupted and restarts.
Data 4 (ANI4)
Data 5 (ANI5)
Data 6 (ANI6)
Data 7 (ANI7)
Conversion is interrupted.
Stop state
Data 0 (ANI0)
Data 0 (ANI0)
Data 0 (ANI0)
Data 0 (ANI0)
Data 4 (ANI4)
Data 1 (ANI1)
Data 1 (ANI1)
Data 5 (ANI5)
Data 2 (ANI2)
Data 2 (ANI2)
Data 6 (ANI6)
Data 3 (ANI3)
An interrupt request signal is generated immediately after the fourth A/D conversion ends.
Data 3 (ANI3)
An interrupt request signal is generated immediately after the fourth A/D conversion ends.
Caution
When <4>, <5>, or <6> is detected during conversion operation, conversion is restarted automatically after the stabilization wait time has passed since the rising edge of the next conversion clock (fAD). The conversion time at the first conversion operation restarted is the same as that when there is A/D power supply stabilization wait time in software trigger wait mode or hardware trigger wait mode. (See Table 12 - 3 A/D Conversion Time Selection (3/8) and Table 12 - 3 A/D Conversion Time Selection (4/8).)
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12.6.9 Hardware trigger no-wait mode (select mode, sequential conversion mode)
<1> In the stop state, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the A/D converter enters the standby state.
<2> After the software counts up to the stabilization wait time (1 µs + 2 cycles of the conversion clock (fAD)), the ADCS bit of the ADM0 register is set to 1 to place the A/D converter in the hardware trigger standby state (and conversion does not start at this stage). Note that, while in this state, A/D conversion does not start even if ADCS is set to 1.
<3> If a hardware trigger is input while ADCS = 1, A/D conversion is performed on the analog input specified by the analog input channel specification register (ADS).
<4> When A/D conversion ends, the conversion result is stored in the A/D conversion result registers (ADCR, ADCRH, ADCR0, and ADCR0H), and the A/D conversion end interrupt request signal (INTAD) is generated. After A/D conversion ends, the next A/D conversion immediately starts.
<5> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded.
<6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register. The partially converted data is discarded.
<7> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded.
<8> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the A/D converter enters the standby state. However, the A/D converter does not stop in this state.
<9> When ADCE is cleared to 0 while in the A/D conversion standby state, the A/D converter enters the stop state. When ADCS = 0, inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 12 - 26 Example of Hardware Trigger No-Wait Mode (Select Mode, Sequential Conversion Mode) Operation Timing
<1> ADCE is set to 1.
ADCE is cleared to 0. <9>
ADCE
<2> ADCS is set to 1.
<3> A hardware trigger is generated.
Hardware trigger Trigger The trigger is not standby acknowledged. state
<5> A hardware trigger is generated during A/D conversion operation.
The trigger is not acknowledged.
ADCS is with 1
overwritten during A/D
<7>
ADCS is cleared <8> to 0 during A/D
conversion operation.
conversion operation.
ADCS
<6> ADS is rewritten during A/D conversion operation (from ANI0 to ANI1).
ADS
Data 0 (ANI0)
Data 1 (ANI1)
A/D conversion
state
Stop Conversion state standby
<4> A/D conversion
ends and the next
conversion starts.
<4>
Data 0 (ANI0)
Data 0 (ANI0)
Data 0 (ANI0)
Conversion is
interrupted and restarts.
<4>
Data 0 (ANI0)
Data 0 (ANI0)
Conversion is
interrupted and restarts.
<4>
Data 1 (ANI1)
Data 1 (ANI1)
Conversion is
interrupted and restarts.
<4>
Conversion is interrupted.
Data 1 (ANI1)
Data 1 Conversion (ANI1) standby
Stop state
ADCR0, ADCR0H
Data 0 (ANI0)
Data 0 (ANI0)
Data 0 (ANI0)
Data 1 (ANI1)
Data 1 (ANI1)
INTAD
Caution
When <4>, <5>, or <6> is detected while conversion is in progress, conversion is automatically restarted from the rising edge of the next cycle of the conversion clock (fAD). The conversion time at the first conversion operation restarted is the same as that when there is A/D power supply stabilization wait time in software trigger wait mode or hardware trigger wait mode. (See Table 12 - 3 A/D Conversion Time Selection (3/8) and Table 12 - 3 A/D Conversion Time Selection (4/8).)
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12.6.10 Hardware trigger no-wait mode (select mode, one-shot conversion mode)
<1> In the stop state, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the A/D converter enters the standby state.
<2> After the software counts up to the stabilization wait time (1 µs + 2 cycles of the conversion clock (fAD)), the ADCS bit of the ADM0 register is set to 1 to place the A/D converter in the hardware trigger standby state (and conversion does not start at this stage). Note that, while in this state, A/D conversion does not start even if ADCS is set to 1.
<3> If a hardware trigger is input while ADCS = 1, A/D conversion is performed on the analog input specified by the analog input channel specification register (ADS).
<4> When A/D conversion ends, the conversion result is stored in the A/D conversion result registers (ADCR, ADCRH, ADCR0, and ADCR0H), and the A/D conversion end interrupt request signal (INTAD) is generated.
<5> After A/D conversion ends, the ADCS bit remains set to 1, and the A/D converter enters the standby state. <6> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and conversion
restarts. The partially converted data is discarded. <7> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register. The partially converted data is discarded. <8> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded. <9> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the A/D converter enters the standby state. However, the A/D converter does not stop in this state. <10>When ADCE is cleared to 0 while in the A/D conversion standby state, the A/D converter enters the stop state. When ADCS = 0, inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 12 - 27 Example of Hardware Trigger No-Wait Mode (Select Mode, One-Shot Conversion Mode) Operation Timing
<1> ADCE is set to 1.
ADCE is cleared to 0. <10>
ADCE
Hardware trigger
ADCS
ADS
A/D conversion
state
<2> ADCS is set to 1.
<3>A hardware trigger <3> is generated.
<6> A hardware trigger is generated during A/D
<3>
conversion operation.
<3>
<3>
The trigger is not
acknowledged.
The trigger is not acknowledged.
Trigger standby
state
ADCS retains <5> the value 1.
Data 0 (ANI0)
Stop state
Conversion standby
<4> A/D conversion ends.
Data 0 (ANI0)
Conversion Data 0 standby (ANI0)
Conversion is interrupted and restarts.
Data 0 (ANI0)
<5>
ADCS is overwritten with 1 during <8>
<5>
A/D conversion operation.
<7>ADS is rewritten during A/D conversion operation (from ANI0 to ANI1).
<5>
<9>ADCS is cleared to 0 during A/D conversion operation.
<4>
Data 1 (ANI1)
Conversion is
interrupted and restarts.
<4>
Conversion is interrupted and restarts.<4>
Conversion is interrupted.
Conversion Data 0 standby (ANI0)
Data 1 (ANI1)
Conversion Data 1 standby (ANI1)
Data 1 (ANI1)
Data 1 Conversion
Conversion
Stop
(ANI1) standby standby state
ADCR0, ADCR0H
INTAD
Data 0 (ANI0)
Data 0 (ANI0)
Data 1 (ANI1)
Data 1 (ANI1)
Caution
When <4>, <5>, or <6> is detected while conversion is in progress, conversion is automatically restarted from the rising edge of the next cycle of the conversion clock (fAD). The conversion time at the first conversion operation restarted is the same as that when there is A/D power supply stabilization wait time in software trigger wait mode or hardware trigger wait mode. (See Table 12 - 3 A/D Conversion Time Selection (3/8) and Table 12 - 3 A/D Conversion Time Selection (4/8).)
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12.6.11 Hardware trigger no-wait mode (scan mode, sequential conversion mode)
<1> In the stop state, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the A/D converter enters the standby state.
<2> After the software counts up to the stabilization wait time (1 µs + 2 cycles of the conversion clock (fAD)), the ADCS bit of the ADM0 register is set to 1 to place the A/D converter in the hardware trigger standby state (and conversion does not start at this stage). Note that, while in this state, A/D conversion does not start even if ADCS is set to 1.
<3> If a hardware trigger is input while ADCS = 1, A/D conversion is performed on the four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel specification register (ADS). A/D conversion is performed on the analog input channels in order, starting with that specified by scan 0.
<4> A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in the A/D conversion result register (ADCRn, ADCRnH) each time conversion ends, and the A/D conversion end interrupt request signal (INTAD) is generated immediately after A/D conversion of the four channels ends. After A/D conversion of the four channels ends, the next A/D conversion of the specified channels automatically starts.
<5> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and conversion restarts at the first channel. The partially converted data is discarded.
<6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register. The partially converted data is discarded.
<7> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded.
<8> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the A/D converter enters the standby state. However, the A/D converter does not stop in this state.
<9> When ADCE is cleared to 0 while in the A/D conversion standby state, the A/D converter enters the stop state. When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversion does not start.
Figure 12 - 28 Example of Hardware Trigger No-Wait Mode (Scan Mode, Sequential Conversion Mode) Operation Timing
<1> ADCE is set to 1.
ADCE is cleared to 0.<9>
ADCE
Hardware trigger
<2> ADCS is set to 1. <3> A hardware trigger is generated.
The trigger is not acknowledged.
Trigger standby
state
ADCS
<5> A hardware trigger is generated during A/D conversion operation.
ADCS is overwritten with 1 during A/D
<7>
conversion operation.
The trigger is not acknowledged.
ADCS is cleared to 0 <8> during A/D conversion
operation.
<6> ADS is rewritten during A/D conversion operation.
ADS
A/D conversion
state
Stop state
ANI0 to ANI3 Conversion Data 0
standby (ANI0)
A/D conversion <4> ends and the next conversion starts.
Conversion is interrupted and restarts.
Data 1 Data 2 Data 3 Data 0 Data 1 Data 0 Data 1 Data 2 (ANI1) (ANI2) (ANI3) (ANI0) (ANI1) (ANI0) (ANI1) (ANI2)
ANI4 to ANI7
<4>
Data 3 Data 0 Data 1 (ANI3) (ANI0) (ANI1)
Conversion is interrupted and restarts.
Data 4 Data 5 (ANI4) (ANI5)
Data 6 (ANI6)
<4>
Data 7 Data 4 (ANI7) (ANI4)
Data 5 (ANI5)
Data 6 (ANI6)
Conversion is interrupted and restarts.
Data 4 Data 5 Data 6 (ANI4) (ANI5) (ANI6)
<4>
Conversion is interrupted.
Data 7 Data 4 Conversion (ANI7) (ANI4) standby
Stop state
ADCR0 ADCR0H
Data 0 (ANI0)
Data 0 (ANI0)
Data 0 (ANI0)
Data 0 (ANI0)
Data 4 (ANI4)
Data 4 (ANI4)
Data 4 (ANI4)
ADCR1 ADCR1H
Data 1 (ANI1)
Data 1 (ANI1)
Data 5 (ANI5)
Data 5 (ANI5)
Data 5 (ANI5)
ADCR2 ADCR2H
Data 2 (ANI2)
Data 2 (ANI2)
Data 6 (ANI6)
Data 6 (ANI6)
ADCR3 ADCR3H
INTAD
Data 3 (ANI3)
An interrupt request signal is generated immediately after the fourth A/D conversion ends.
Data 3 (ANI3)
An interrupt request signal is generated immediately after the fourth A/D conversion ends.
Data 7 (ANI7)
An interrupt request signal is generated immediately after the fourth A/D conversion ends.
Data 7 (ANI7)
An interrupt request signal is generated immediately after the fourth A/D conversion ends.
Caution
When <4>, <5>, or <6> is detected while conversion is in progress, conversion is automatically restarted from the rising edge of the next cycle of the conversion clock (fAD). The conversion time at the first conversion operation restarted is the same as that when there is A/D power supply stabilization wait time in software trigger wait mode or hardware trigger wait mode. (See Table 12 - 3 A/D Conversion Time Selection (3/8) and Table 12 - 3 A/D Conversion Time Selection (4/8).)
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12.6.12 Hardware trigger no-wait mode (scan mode, one-shot conversion mode)
<1> In the stop state, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the A/D converter enters the standby state.
<2> After the software counts up to the stabilization wait time (1 µs + 2 cycles of the conversion clock (fAD)), the ADCS bit of the ADM0 register is set to 1 to place the A/D converter in the hardware trigger standby state (and conversion does not start at this stage). Note that, while in this state, A/D conversion does not start even if ADCS is set to 1.
<3> If a hardware trigger is input while ADCS = 1, A/D conversion is performed on the four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel specification register (ADS). A/D conversion is performed on the analog input channels in order, starting with that specified by scan 0.
<4> A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in the A/D conversion result register (ADCRn, ADCRnH) each time conversion ends, and the A/D conversion end interrupt request signal (INTAD) is generated immediately after A/D conversion of the four channels ends.
<5> After A/D conversion of the four channels ends, the ADCS bit remains set to 1, and the A/D converter enters the standby state.
<6> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and conversion restarts at the first channel. The partially converted data is discarded.
<7> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register. The partially converted data is discarded.
<8> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts at the first channel. The partially converted data is discarded.
<9> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the A/D converter enters the standby state. However, the A/D converter does not stop in this state.
<10>When ADCE is cleared to 0 while in the A/D conversion standby state, the A/D converter enters the stop state. When ADCS = 0, inputting a hardware trigger is ignored and A/D conversion does not start.
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Figure 12 - 29 Example of Hardware Trigger No-Wait Mode (Scan Mode, One-Shot Conversion Mode) Operation Timing
<1> ADCE is set to 1.
ADCE is cleared to 0. <10>
ADCE Hardware
<2> ADCS is set to 1.
<3> A hardware trigger is generated.
<3>
trigger
The trigger is not acknowledged.
Trigger standby
state
ADCS retains <5> the value 1.
ADCS
<6> A hardware trigger is
generated during A/D conversion operation.
<3>
<5>
<3>
<5>
<7>
ADS is rewritten during A/D
conversion operation.
The trigger is not acknowledged.
<8>ADCS is overwritten
with 1 during A/D conversion operation.
<9>ADCS is cleared
to 0 during A/D conversion
operation.
ADS
ANI0 to ANI3
ANI4 to ANI7
A/D conversion
state
Stop state
<4> A/D conversion ends.
Conversion is interrupted and restarts.
<4>
Conversion is interrupted and restarts.
<4>
Conversion is interrupted and restarts.
Conversion is interrupted.
Conversion Data 0 Data 1 Data 2 Data 3 Conversion Data 0 Data 1 Data 0 Data 1 Data 2 Data 3 Conversion Data 0 Data 1 Data 4 Data 5 Data 6 Data 7 Conversion Data 4 Data 5 Data 4 Data 5 Data 6 Conversion Stop
standby
(ANI0) (ANI1) (ANI2) (ANI3) standby (ANI0) (ANI1) (ANI0) (ANI1) (ANI2) (ANI3) standby (ANI0) (ANI1) (ANI4) (ANI5) (ANI6) (ANI7) standby (ANI4) (ANI5) (ANI4) (ANI5) (ANI6) standby state
ADCR0 ADCR0H
Data 0 (ANI0)
Data 0 (ANI0)
Data 0 (ANI0)
Data 0 (ANI0)
Data 4 (ANI4)
Data 4 (ANI4)
Data 4 (ANI4)
ADCR1 ADCR1H
Data 1 (ANI1)
Data 1 (ANI1)
Data 5 (ANI5)
Data 5 (ANI5)
ADCR2 ADCR2H
ADCR3 ADCR3H
INTAD
Data 2 (ANI2)
Data 3 (ANI3) An interrupt request signal is generated immediately after the fourth A/D conversion ends.
Data 2 (ANI2)
Data 3 (ANI3) An interrupt request signal is generated immediately after the fourth A/D conversion ends.
Data 6 (ANI6)
Data 7 (ANI7) An interrupt request signal is generated immediately after the fourth A/D conversion ends.
Caution
When <4>, <5>, or <6> is detected while conversion is in progress, conversion is automatically restarted from the rising edge of the next cycle of the conversion clock (fAD). The conversion time at the first conversion operation restarted is the same as that when there is A/D power supply stabilization wait time in software trigger wait mode or hardware trigger wait mode. (See Table 12 - 3 A/D Conversion Time Selection (3/8) and Table 12 - 3 A/D Conversion Time Selection (4/8).)
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12.6.13 Hardware trigger wait mode (select mode, sequential conversion mode)
<1> In the stop state, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the A/D converter enters the hardware trigger standby state.
<2> If a hardware trigger is input while in the hardware trigger standby state, A/D conversion is performed on the analog input specified by the analog input channel specification register (ADS). The ADCS bit of the ADM0 register is automatically set to 1 according to the hardware trigger input.
<3> When A/D conversion ends, the conversion result is stored in the A/D conversion result registers (ADCR, ADCRH, ADCR0, and ADCR0H), and the A/D conversion end interrupt request signal (INTAD) is generated. After A/D conversion ends, the next A/D conversion immediately starts. (At this time, no hardware trigger is necessary.)
<4> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded.
<5> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register. The partially converted data is discarded.
<6> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded.
<7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, the A/D converter enters the hardware trigger standby state, and the A/D converter enters the stop state. When ADCE = 0, inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 12 - 30 Example of Hardware Trigger Wait Mode (Select Mode, Sequential Conversion Mode) Operation Timing
<1> ADCE is set to 1.
ADCE
Hardware trigger
The trigger is not
acknowledged.
ADCS
<2> A hardware trigger is generated.
Trigger standby
state
<4> A hardware trigger is generated during A/D conversion operation.
Trigger standby
state
The trigger
is not acknowledged.
ADCS is overwritten <6>
ADCS is cleared <7>
with 1 during A/D
to 0 during A/D
conversion operation.
conversion operation.
<5> ADS is rewritten during A/D conversion operation (from ANI0 to ANI1).
ADS
Data 0 (ANI0)
Data 1 (ANI1)
A/D conversion
state
Stop state
<3>A/D conversion ends and the next conversion <3> starts.
Data 0 (ANI0)
Data 0 (ANI0)
Data 0 (ANI0)
Conversion is interrupted and restarts. <3>
Data 0 (ANI0)
Data 0 (ANI0)
Conversion is
interrupted and restarts.
<3>
Data 1 (ANI1)
Data 1 (ANI1)
Conversion is interrupted and restarts.
<3>
Conversion is interrupted.
Data 1 (ANI1)
Data 1 (ANI1)
Stop state
ADCR0, ADCR0H
Data 0 (ANI0)
Data 0 (ANI0)
Data 0 (ANI0)
Data 1 (ANI1)
Data 1 (ANI1)
INTAD
Caution
When <4>, <5>, or <6> is detected during conversion operation, conversion is restarted automatically after the stabilization wait time has passed since the rising edge of the next conversion clock (fAD). The conversion time at the first conversion operation restarted is the same as that when there is A/D power supply stabilization wait time in software trigger wait mode or hardware trigger wait mode. (See Table 12 - 3 A/D Conversion Time Selection (3/8) and Table 12 - 3 A/D Conversion Time Selection (4/8).)
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12.6.14 Hardware trigger wait mode (select mode, one-shot conversion mode)
<1> In the stop state, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the A/D converter enters the hardware trigger standby state.
<2> If a hardware trigger is input while in the hardware trigger standby state, A/D conversion is performed on the analog input specified by the analog input channel specification register (ADS). The ADCS bit of the ADM0 register is automatically set to 1 according to the hardware trigger input.
<3> When A/D conversion ends, the conversion result is stored in the A/D conversion result registers (ADCR, ADCRH, ADCR0, and ADCR0H), and the A/D conversion end interrupt request signal (INTAD) is generated.
<4> After A/D conversion ends, the ADCS bit is automatically cleared to 0, and the A/D converter enters the stop state. <5> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and conversion
restarts. The partially converted data is discarded. <6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register. The partially converted data is discarded. <7> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is initialized. <8> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, the A/D converter enters the hardware trigger standby state, and the A/D converter enters the stop state. When ADCE = 0, inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 12 - 31 Example of Hardware Trigger Wait Mode (Select Mode, One-Shot Conversion Mode) Operation Timing
<1> ADCE is set to 1.
ADCE
Hardware trigger
<2>A hardware trigger is generated.
<2>
<5> A hardware trigger is generated during A/D
<2>
conversion operation.
<2>
<2>
Trigger
standby state
The trigger is not acknowledged.
The trigger is not acknowledged.
Trigger standby
state
ADCS
ADCS is automatically <4> cleared to 0 after conversion ends.
<4>
<4>
<6>
ADS is rewritten during A/D conversion
operation (from ANI0
to ANI1).
<7>ADCS is overwritten <4>
with 1 during A/D conversion operation.
<8> ADCS is cleared to 0 during A/D conversion operation.
ADS
A/D conversion
state
Stop state
Data 0 (ANI0)
Data 0 (ANI0)
<3>A/D conversion ends. Stop Data 0 state (ANI0)
Conversion is
interrupted and restarts.
<3>
Data 0 (ANI0)
Stop state
Data 0 (ANI0)
Data 1 (ANI1)
Conversion is
interrupted and restarts.
<3>
Data 1 (ANI1)
Stop state
Data 1 (ANI1)
Conversion is
interrupted and restarts.
<3>
Data 1 (ANI1)
Stop state
Data 1 (ANI1)
Conversion is interrupted.
Stop state
ADCR0, ADCR0H
INTAD
Data 0 (ANI0)
Data 0 (ANI0)
Data 1 (ANI1)
Data 1 (ANI1)
Caution
When <4>, <5>, or <6> is detected during conversion operation, conversion is restarted automatically after the stabilization wait time has passed since the rising edge of the next conversion clock (fAD). The conversion time at the first conversion operation restarted is the same as that when there is A/D power supply stabilization wait time in software trigger wait mode or hardware trigger wait mode. (See Table 12 - 3 A/D Conversion Time Selection (3/8) and Table 12 - 3 A/D Conversion Time Selection (4/8).)
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12.6.15 Hardware trigger wait mode (scan mode, sequential conversion mode)
<1> In the stop state, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the A/D converter enters the standby state.
<2> If a hardware trigger is input while in the hardware trigger standby state, A/D conversion is performed on the four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel specification register (ADS). The ADCS bit of the ADM0 register is automatically set to 1 according to the hardware trigger input. A/D conversion is performed on the analog input channels in order, starting with that specified by scan 0.
<3> A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in the A/D conversion result register (ADCRn, ADCRnH) each time conversion ends, and the A/D conversion end interrupt request signal (INTAD) is generated immediately after A/D conversion of the four channels ends. After A/D conversion of the four channels ends, the next A/D conversion of the specified channels automatically starts.
<4> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and conversion restarts at the first channel. The partially converted data is discarded.
<5> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register. The partially converted data is discarded.
<6> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded.
<7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, the A/D converter enters the hardware trigger standby state, and the A/D converter enters the stop state. When ADCE = 0, inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 12 - 32 Example of Hardware Trigger Wait Mode (Scan Mode, Sequential Conversion Mode) Operation Timing
<1> ADCE is set to 1.
ADCE
Hardware trigger
<2> A hardware trigger is generated.
The trigger
Trigger
is not
standby
acknowledged. state
ADCS
<4> A hardware trigger is generated during A/D
conversion operation.
ADCS is overwritten with 1 during A/D
<6>
conversion operation.
Trigger standby
state
The trigger is not acknowledged.
ADCS is cleared <7> to 0 during A/D
conversion operation.
ADS
A/D conversion
state
<5> ADS is rewritten during A/D conversion operation.
ANI0 to ANI3
ANI4 to ANI7
Stop state
Data 0 (ANI0)
A/D conversion <3> ends and the next conversion starts.
Data 1 Data 2 Data 3 Data 0 (ANI1) (ANI2) (ANI3) (ANI0)
Data 1 (ANI1)
Conversion is
<3>
interrupted and restarts.
Data 0 Data 1 Data 2 Data 3 Data 0 (ANI0) (ANI1) (ANI2) (ANI3) (ANI0)
Data 1 (ANI1)
Conversion is
<3>
interrupted and restarts.
Data 4 Data 5 Data 6 Data 7 Data 4 (ANI4) (ANI5) (ANI6) (ANI7) (ANI4)
Conversion is
<3>
interrupted and restarts.
Data 5 Data 6 Data 4 Data 5 Data 6 Data 7 Data 4 (ANI5) (ANI6) (ANI4) (ANI5) (ANI6) (ANI7) (ANI4)
Conversion is interrupted.
Stop state
ADCR0 ADCR0H
Data 0 (ANI0)
Data 0 (ANI0)
Data 0 (ANI0)
Data 0 (ANI0)
Data 4 (ANI4)
Data 4 (ANI4)
Data 4 (ANI4)
ADCR1 ADCR1H
Data 1 (ANI1)
Data 1 (ANI1)
Data 5 (ANI5)
Data 5 (ANI5)
Data 5 (ANI5)
ADCR2 ADCR2H
Data 2 (ANI2)
Data 2 (ANI2)
Data 6 (ANI6)
Data 6 (ANI6)
ADCR3 ADCR3H
INTAD
Data 3 (ANI3)
An interrupt request signal is generated immediately after the fourth A/D conversion ends.
Data 3 (ANI3)
An interrupt request signal is generated immediately after the fourth A/D conversion ends.
Data 7 (ANI7)
An interrupt request signal is generated immediately after the fourth A/D conversion ends.
Data 7 (ANI7)
An interrupt request signal is generated immediately after the fourth A/D conversion ends.
Caution
When <4>, <5>, or <6> is detected during conversion operation, conversion is restarted automatically after the stabilization wait time has passed since the rising edge of the next conversion clock (fAD). The conversion time at the first conversion operation restarted is the same as that when there is A/D power supply stabilization wait time in software trigger wait mode or hardware trigger wait mode. (See Table 12 - 3 A/D Conversion Time Selection (3/8) and Table 12 - 3 A/D Conversion Time Selection (4/8).)
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12.6.16 Hardware trigger wait mode (scan mode, one-shot conversion mode)
<1> In the stop state, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the A/D converter enters the standby state.
<2> If a hardware trigger is input while in the hardware trigger standby state, A/D conversion is performed on the four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel specification register (ADS). The ADCS bit of the ADM0 register is automatically set to 1 according to the hardware trigger input. A/D conversion is performed on the analog input channels in order, starting with that specified by scan 0.
<3> A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in the A/D conversion result register (ADCRn, ADCRnH) each time conversion ends, and the A/D conversion end interrupt request signal (INTAD) is generated immediately after A/D conversion of the four channels ends.
<4> After A/D conversion ends, the ADCS bit is automatically cleared to 0, and the A/D converter enters the stop state. <5> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and conversion
restarts at the first channel. The partially converted data is discarded. <6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register. The partially converted data is discarded. <7> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded. <8> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, the A/D converter enters the hardware trigger standby state, and the A/D converter enters the stop state. When ADCE = 0, inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 12 - 33 Example of Hardware Trigger Wait Mode (Scan Mode, One-Shot Conversion Mode) Operation Timing
<1> ADCE is set to 1.
ADCE
Hardware trigger
<2> A hardware trigger
<2>
is generated.
The trigger is not
ADCS acknowledged.
Trigger
standby state
ADCS is automatically <4> cleared to 0 after conversion ends.
<5> A hardware trigger is
generated during A/D
<2>
conversion operation.
<4>
<2>
<4> ADS is rewritten <6> during A/D conversion operation.
Trigger standby The trigger is not
state acknowledged.
<7> ADCS is overwritten
with 1 during A/D
<8>
conversion operation.
ADCS is cleared to 0 during A/D conversion
operation.
ADS
A/D conversion
state
ANI0 to ANI3
ANI4 to ANI7
<3> A/D conversion ends.
Conversion is interrupted
and restarts.
<3>
Conversion is interrupted and restarts.
<3>
Conversion is interrupted and restarts.
Conversion is interrupted.
Stop state
Data 0 Data 1 Data 2 Data 3 Stop Data 0 Data 1 Data 0 Data 1 Data 2 Data 3 Stop Data 0 Data 1 Data 4 Data 5 Data 6 Data 7 Stop Data 4 Data 5 Data 4 Data 5 Data 6 (ANI0) (ANI1) (ANI2) (ANI3) state (ANI0) (ANI1) (ANI0) (ANI1) (ANI2) (ANI3) state (ANI0) (ANI1) (ANI4) (ANI5) (ANI6) (ANI7) state (ANI4) (ANI5) (ANI4) (ANI5) (ANI6)
Stop state
ADCR0 ADCR0H
Data 0 (ANI0)
Data 0 (ANI0)
Data 0 (ANI0)
Data 0 (ANI0)
Data 4 (ANI4)
Data 4 (ANI4)
Data 4 (ANI4)
ADCR1 ADCR1H
Data 1 (ANI1)
Data 1 (ANI1)
Data 5 (ANI5)
Data 5 (ANI5)
ADCR2 ADCR2H
Data 2 (ANI2)
Data 2 (ANI2)
Data 6 (ANI6)
ADCR3 ADCR3H
INTAD
Data 3 (ANI3)
An interrupt request signal is generated immediately after the fourth A/D conversion ends.
Data 3 (ANI3)
An interrupt request signal is generated immediately after the fourth A/D conversion ends.
Data 7 (ANI7)
An interrupt request signal is generated immediately after the fourth A/D conversion ends.
Caution
When <4>, <5>, or <6> is detected during conversion operation, conversion is restarted automatically after the stabilization wait time has passed since the rising edge of the next conversion clock (fAD). The conversion time at the first conversion operation restarted is the same as that when there is A/D power supply stabilization wait time in software trigger wait mode or hardware trigger wait mode. (See Table 12 - 3 A/D Conversion Time Selection (3/8) and Table 12 - 3 A/D Conversion Time Selection (4/8).)
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12.7
A/D Converter Setup Flowchart
The A/D converter setup flowchart in each operation mode is described below.
12.7.1 Setting up software trigger no-wait mode
Figure 12 - 34 Setting up Software Trigger No-Wait Mode
Start of setup
PER0 register setting
PMCAxx, PMCTxx, and PMCEx register settings
PM register setting
· ADM0 register setting · ADM1 register setting · ADM2 register setting · ADUL/ADLL register setting · ADS register setting
(The order of the settings is irrelevant.)
Yes
Supplied from the internal reference
voltage?
No
· Setting ADM2 register Setting ADREFP1, ADREFP0 to (1, 1)
· Reference voltage discharge time: 1 µs wait
The ADCEN bit of the PER0 register is set to 1, and supplying the clock starts.
The ports are set to analog input.
The ports are set to the input mode.
· ADM0 register FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time . ADMD bit: Select mode/scan mode
· ADM1 register ADTMD1 and ADTMD0 bits: These are used to specify the software trigger no-wait mode. ADSCM bit: Sequential conversion mode/one-shot conversion mode
· ADM2 register ADRCK bit: This is used to select the range for the A/D conversion result comparison value for generating the interrupt signal from AREA1, AREA3, and AREA 2. ADTYP1 and ADTYP0 bits: 8-bit/10-bit/12-bit resolution
· ADUL/ADLL register These are used to specify the upper limit and lower limit A/D conversion result comparison values.
· ADS register ADS4 to ADS0 bits: These are used to select the analog input channels.
· Setting ADM2 register Changing the values of ADREFP1 and ADREFP0
Reference voltage stabilization wait time count A
ADCE bit setting
· ADM2 register ADREFM bit: This is used to select the - side reference voltage source ADREFP1 and ADREFP0 bits: These are used to select the + side reference voltage source. Before the supply setting of the internal reference voltage (ADREFP1, ADREFP0 = 1, 0), the reference voltage discharge time (1 µs) is required.
The reference voltage stabilization wait time count indicated by A below may be required if the values of the ADREFP1 and ADREFP0 bits are changed. If the values of ADREFP1 and ADREFP0 are changed to 1 and 0, respectively: A = 5 µs A wait is not required if the values of ADREFP1 and ADREFP0 are changed to 0 and 0 or 0 and 1, respectively.
The ADCE bit of the ADM0 register is set to 1, and the A/D converter enters the standby state.
Reference voltage stabilization wait time count B
ADCS bit setting
Use software to control waiting until reference voltage stabilization wait time count B (1 µs + 2 cycles of the conversion clock (fAD)) elapses.
After reference voltage stabilization wait time count B elapses, the ADCS bit of the ADM0 register is set to 1, and A/D conversion starts.
Start of A/D conversion
The A/D conversion operations are performed.
End of A/D conversion
The A/D conversion end interrupt (INTAD) is generated.Note
Note
Storage of conversion results in the ADCRn or ADCRnH register
The conversion results are stored in the ADCRn or ADCRnH register.
Depending on the settings of the ADRCK bit and ADUL/ADLL register, there is a possibility of no interrupt signal being generated. In this case, the results are not stored in the ADCRn or ADCRnH register.
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12.7.2 Setting up software trigger wait mode
Figure 12 - 35 Setting up Software Trigger Wait Mode
Start of setup
PER0 register setting
PMCAxx, PMCTxx, and PMCEx register settings
· PM register setting
· ADM0 register setting · ADM1 register setting · ADM2 register setting · ADUL/ADLL register setting · ADS register setting (The order of the settings is irrelevant.)
Yes
Supplied from the internal reference
voltage?
No · Setting ADM2 register Setting ADREFP1, ADREFP0 to (1, 1) · Reference voltage discharge time: 1 µs wait
The ADCEN bit of the PER0 register is set to 1, and supplying the clock starts.
The ports are set to analog input.
The ports are set to the input mode.
· ADM0 register FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time. ADMD bit: Select mode/scan mode
· ADM1 register ADTMD1 and ADTMD0 bits: These are used to specify the software trigger wait mode. ADSCM bit: Sequential conversion mode/one-shot conversion mode.
· ADM2 register ADRCK bit: This is used to select the range for the A/D conversion result comparison value for generating the interrupt signal from AREA1, AREA3, and AREA2. ADTYP1 and ADTYP0 bits: 8-bit/10-bit/12-bit resolution
· ADUL/ADLL register These are used to specify the upper limit and lower limit A/D conversion result comparison values.
· ADS register ADS4 to ADS0 bits: These are used to select the analog input channels.
· Setting ADM2 register Changing the values of ADREFP1 and ADREFP0
Reference voltage stabilization wait time count A
ADCE bit setting
ADCS bit setting
· ADM2 register ADREFM bit: This is used to select the - side reference voltage source ADREFP1 and ADREFP0 bits: These are used to select the + side reference voltage source Before the supply setting of the internal reference voltage (ADREFP1, ADREFP0 = 1, 0), the reference voltage discharge time (1 µs) is required.
The reference voltage stabilization wait time count indicated by A below may be required if the values of the ADREFP1 and ADREFP0 bits are changed. If the values of ADREFP1 and ADREFP0 are changed to 1 and 0, respectively: A = 5 µs Before changing as above, perform reference supply discharge (1 µs) by setting ADREFP1, ADREFP0 = 1, 1. A wait is not required if the values of ADREFP1 and ADREFP0 are changed to 0 and 0 or 0 and 1, respectively.
Do not set the ADCE bit of the ADM0 register (0). The A/D converter must remain in the stopped state.
The ADCS bit of the ADM0 register is set to 1, and the A/D converter enters the standby state.
Stabilization wait time for A/D power supply
The A/D converter automatically counts up to the stabilization wait time for A/D power supply.
Start of A/D conversion
After counting up to the stabilization wait time for A/D power supply ends, A/D conversion starts.
The A/D conversion operations are performed.
End of A/D conversion
The A/D conversion end interrupt (INTAD) is generated.Note
Note
Storage of conversion results in the ADCRn or ADCRnH register
The conversion results are stored in the ADCRn or ADCRnH register.
Depending on the settings of the ADRCK bit and ADUL/ADLL register, there is a possibility of no interrupt signal being generated. In this case, the results are not stored in the ADCRn or ADCRnH register.
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12.7.3 Setting up hardware trigger no-wait mode
Figure 12 - 36 Setting up Hardware Trigger No-Wait Mode
Start of setup
PER0 register setting PMCAxx, PMCTxx, and PMCEx register settings
PM register setting
· ADM0 register setting · ADM1 register setting · ADM2 register setting · ADUL/ADLL register setting · ADS register setting
(The order of the settings is irrelevant.)
Yes
Supplied from the internal reference
voltage?
No
· Setting ADM2 register Setting ADREFP1, ADREFP0 to (1, 1) · Reference voltage discharge time
The ADCEN bit of the PER0 register is set to 1, and supplying the clock starts.
The ports are set to analog input.
The ports are set to the input mode.
· ADM0 register FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time. ADMD bit: Select mode/scan mode
· ADM1 register ADTMD1 and ADTMD0 bits: These are used to specify the hardware trigger no-wait mode. ADSCM bit: Sequential conversion mode/one-shot conversion mode
· ADM2 register ADRCK bit: This is used to select the range for the A/D conversion result comparison value for generating the interrupt signal from AREA1, AREA3, and AREA2. ADTYP1 and ADTYP0 bits: 8-bit/10-bit/12-bit resolution
· ADUL/ADLL register These are used to specify the upper limit and lower limit A/D conversion result comparison values.
· ADS register ADS4 to ADS0 bits: These are used to select the analog input channels.
· Setting ADM2 register Changing the values of ADREFP1 and ADREFP0
Reference voltage stabilization wait time count A
ADCE bit setting
· ADM2 register ADREFM bit: This is used to select the - side reference voltage source ADREFP1 and ADREFP0 bits: These are used to select the + side reference voltage source Before the supply setting of the internal reference voltage (ADREFP1, ADREFP0 = 1, 0), the reference voltage discharge time (1 µs) is required.
The reference voltage stabilization wait timecount indicated by A below may be required if the values of the ADREFP1 and ADREFP0 bits are changed. If the values of ADREFP1 and ADREFP0 are changed to 1 and 0, respectively: A = 5 µs A wait is not required if the values of ADREFP1 and ADREFP0 are changed to 0 and 0 or 0 and 1, respectively.
The ADCE bit of the ADM0 register is set to 1, and the A/D converter enters the standby state.
Reference voltage stabilization wait time count B
Use software to control waiting until reference voltage stabilization wait time count B (1 µs + 2 cycles of the conversion clock (fAD)) elapses.
ADCS bit setting
After reference voltage stabilization wait time count B elapses, the ADCS bit of the ADM0 register is set to 1, and the A/D converter enters the hardware trigger standby state.
Hardware trigger standby state
Start of A/D conversion by generating a hardware trigger
The A/D conversion operations are performed.
End of A/D conversion
The A/D conversion end interrupt (INTAD) is generated.Note
Storage of conversion results in the ADCRn or ADCRnH register
The conversion results are stored in the ADCRn or ADCRnH register.
Note
Depending on the settings of the ADRCK bit and ADUL/ADLL register, there is a possibility of no interrupt signal being generated. In this case, the results are not stored in the ADCRn or ADCRnH register.
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12.7.4 Setting up hardware trigger wait mode
Figure 12 - 37 Setting up Hardware Trigger Wait Mode
Start of setup
PER0 register setting PMCAxx, PMCTxx, and PMCEx register settings
PM register setting
· ADM0 register setting · ADM1 register setting · ADM2 register setting · ADUL/ADLL register setting · ADS register setting
(The order of the settings is irrelevant.)
Yes
Supplied from the internal reference
voltage?
No
· Setting ADM2 register Setting ADREFP1, ADREFP0 to (1, 1) · Reference voltage discharge time
The ADCEN bit of the PER0 register is set to 1, and supplying the clock starts.
The ports are set to analog input.
The ports are set to the input mode.
· ADM0 register FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time. ADMD bit: Select mode/scan mode
· ADM1 register ADTMD1 and ADTMD0 bits: These are used to specify the hardware trigger wait mode. ADSCM bit: Sequential conversion mode/one-shot conversion mode ADTRS1 and ADTRS0 bits: These are used to select the hardware trigger signal.
· ADM2 register ADRCK bit: This is used to select the range for the A/D conversion result comparison value for generating the interrupt signal from AREA1, AREA3, and AREA2. ADTYP1 and ADTYP0 bits: 8-bit/10-bit/12-bit resolution
· ADUL/ADLL register These are used to specify the upper limit and lower limit A/D conversion result comparison values.
· ADS register ADS4 to ADS0 bits: These are used to select the analog input channels.
· Setting ADM2 register Changing the values of ADREFP1 and ADREFP0
Reference voltage stabilization wait time count A
ADCE bit setting
· ADM2 register ADREFM bit: This is used to select the - side reference voltage source ADREFP1 and ADREFP0 bits: These are used to select the + side reference voltage source Before the supply setting of the internal reference voltage (ADREFP1, ADREFP0 = 1, 0), the reference voltage discharge time (1 µs) is required.
The reference voltage stabilization wait time count indicated by A below may be required if the values of the ADREFP1 and ADREFP0 bits are changed. If the values of ADREFP1 and ADREFP0 are changed to 1 and 0, respectively: A = 5 µs A wait is not required if the values of ADREFP1 and ADREFP0 are changed to 0 and 0 or 0 and 1, respectively.
The ADCE bit of the ADM0 register is set to 1, and the A/D converter enters the standby state.
Hardware trigger generation
Stabilization wait time for A/D power supply
The A/D converter automatically counts up to the stabilization wait time for A/D power supply.
Start of A/D conversion
After counting up to the stabilization wait time for A/D power supply ends, A/D conversion starts.
The A/D conversion operations are performed.
End of A/D conversion
The A/D conversion end interrupt (INTAD) is generated.Note
Note
Storage of conversion results in the ADCRn or ADCRnH register
The conversion results are stored in the ADCRn or ADCRnH register.
Depending on the settings of the ADRCK bit and ADUL/ADLL register, there is a possibility of no interrupt signal being generated. In this case, the results are not stored in the ADCRn or ADCRnH register.
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12.7.5
Example of using the ADC when selecting the temperature sensor output voltage or internal reference voltage, and software trigger no-wait mode and one-shot conversion mode
Figure 12 - 38 Setup When Temperature Sensor Output Voltage/Internal Reference Voltage Is Selected
Start of setup PER0 register setting
· ADM0 register setting · ADM1 register setting · ADM2 register setting · ADUL/ADLL register setting · ADS register setting
The ADCEN bit of the PER0 register is set to 1, and supplying the clock starts.
· ADM0 register FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time. ADMD bit: This is used to specify the select mode.
· ADM1 register ADTMD1 and ADTMD0 bits: These are used to specify the software trigger no-wait mode. ADSCM bit: One-shot conversion mode
· ADM2 register ADREFP1, ADREFP0, and ADREFM bits: These are used to select the reference voltage. ADRCK bit: This is used to select the range for the A/D conversion result comparison value for generating the interrupt signal from AREA1, AREA3, and AREA2. ADTYP1 and ADTYP0 bits: 8-bit/10-bit/12-bit resolution
· ADUL/ADLL register These are used to specify the upper limit and lower limit A /D conversion result comparison values.
· ADS register ADISS and ADS4 to ADS0 bits: These are used to select the temperature sensor output voltage or internal reference voltage.
Reference voltage stabilization wait time A
ADCE bit setting Reference voltage stabilization wait time count B
ADCS bit setting Start of A/D conversion End of A/D conversion
The reference voltage stabilization wait time count A may be required if the values of the ADREFP1 and ADREFP0 bits are changed. A wait is not required if the values of ADREFP1 and ADREFP0 are changed to 0 and 0 or 0 and 1, respectively. Setting the values of ADREFP1 and ADREFP0 to 1 and 0, respectively is prohibited.
The ADCE bit of the ADM0 register is set to 1, and the A/D converter enters the standby state.
Use software to control waiting until reference voltage stabilization wait time count B (1 µs + 2 cycles of the conversion clock (fAD)) elapses. After reference voltage stabilization wait time B elapses , the ADCS bit of the ADM0 register is set to 1, and A/D conversion starts.
The A/D conversion end interrupt (INTAD) will be generated. After ADISS is set to 1, the initial conversion result cannot be used.
ADCS bit setting
The ADCS bit of the ADM0 register is set to 1, and A/D conversion starts.
Start of A/D conversion End of A/D conversion
The A/D conversion end interrupt (INTAD) is generated. Note
Storage of conversion results in the ADCRn or ADCRnH register
The conversion results are stored in the ADCRn or ADCRnH register.
Note
Depending on the settings of the ADRCK bit and ADUL/ADLL register, there is a possibility of no interrupt signal being generated. In this case, the results are not stored in the ADCRn or ADCRnH register.
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12.7.6 Setting up test mode
Figure 12 - 39 Setting up Test Mode
CHAPTER 12 A/D CONVERTER (ADC)
Start of setup PER0 register setting
· ADM0 register setting · ADM1 register setting · ADM2 register setting · ADUL/ADLL register setting · ADS register setting · ADTES register setting
(The order of the settings is irrelevant.)
Yes
Supplied from the internal reference
voltage?
No
· Setting ADM2 register Setting ADREFP1, ADREFP0 to (1, 1) · Reference voltage discharge time: 1 µs wait
· Setting ADM2 register Changing the values of ADREFP1 and ADREFP0
Reference voltage stabilization wait time count A
ADCE bit setting
Reference voltage stabilization wait time count B
ADCS bit setting
Start of A/D conversion
End of A/D conversion
The ADCEN bit of the PER0 register is set to 1, and supplying the clock starts.
· ADM0 register FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time. ADMD bit: This is used to specify the select mode. · ADM1 register ADTMD1 and ADTMD0 bits: These are used to specify the software trigger no-wait mode. ADSCM bit: This is used to specify the one-shot conversion mode. · ADM2 register ADRCK bit: This is used to set the range for the A/D conversion result comparison value for
generating the interrupt signal to AREA2. ADTYP1 and ADTYP0 bits: 8-bit/10-bit/12-bit resolution. · ADUL/ADLL register These set ADUL to FFH and ADLL to 00H (initial values). · ADS register ADS4 to ADS0 bits: These are used to set to ANI0. · ADTES register ADTES1, ADTES0 bits: AVREFM/AVREFP
· ADM2 register ADREFM bit: This is used to select the - side reference voltage source ADREFP1 and ADREFP0 bits: These are used to select the + side reference voltage source
Before the supply setting of the internal reference voltage (ADREFP1, ADREFP0 = 1, 0), the reference voltage discharge time (1 µs) is required.
The reference voltage stabilization wait time count indicated by A below may be required if the values of the ADREFP1 and ADREFP0 bits are changed. If the values of ADREFP1 and ADREFP0 are changed to 1 and 0, respectively: A = 5 µs A wait is not required if the values of ADREFP1 and ADREFP0 are changed to 0 and 0 or 0 and 1, respectively.
The ADCE bit of the ADM0 register is set to 1, and the A/D converter enters the standby state.
Use software to control waiting until reference voltage stabilization wait time count B (1 µs + 2 cycles of the conversion clock (fAD)) elapses.
After reference voltage stabilization wait time count B elapses, the ADCS bit of the ADM0 register is set to 1, and A/D conversion starts.
The A/D conversion end interrupt (INTAD) is generated.Note
Storage of conversion results in the ADCRn or ADCRnH register
The conversion results are stored in the ADCRn or ADCRnH register.
Note
Depending on the settings of the ADRCK bit and ADUL/ADLL register, there is a possibility of no interrupt signal being
generated. In this case, the results are not stored in the ADCRn or ADCRnH register.
Caution For the procedure for testing the A/D converter, see 27.3.10 Testing of the A/D converter.
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12.8
SNOOZE Mode Function
In the SNOOZE mode, A/D conversion is triggered by inputting a software trigger or a hardware trigger in the STOP mode. Normally, A/D conversion is stopped while in the STOP mode, but, by using the SNOOZE mode function, A/D conversion can be performed without operating the CPU. This is effective for reducing the operating current.
12.8.1 A/D conversion by inputting a software trigger
In the SNOOZE mode, A/D conversion is triggered by inputting a software trigger. A software trigger generated by the SNOOZE mode sequencer (SMS) is used as an input trigger for AD conversion. When performing A/D conversion by inputting a software trigger in SNOOZE mode, only the following four conversion modes can be used. · Software trigger wait mode (select mode, one-shot conversion mode) · Software trigger wait mode (select mode, sequential conversion mode) · Software trigger wait mode (scan mode, one-shot conversion mode) · Software trigger wait mode (scan mode, sequential conversion mode)
Caution
The SNOOZE mode can only be specified when the high-speed on-chip oscillator clock or mediumspeed on-chip oscillator clock is selected for fCLK.
Figure 12 - 40 Block Diagram When Using SNOOZE Mode Function (in Software Trigger Wait Mode)
SNOOZE mode sequencer Software trigger
(SMS)
input
A/D conversion end interrupt request signal
(INTAD)Note
A/D converter
Clock request signal
High-speed on-chip oscillator clock
Clock generator
When using the SNOOZE mode function, the initial setting of each register is specified before switching to the STOP mode (for details about these settings, see 12.7.2 Setting up software trigger wait mode). If a software trigger (ADCS = 1) is input after switching to the STOP mode, the high-speed on-chip oscillator clock is supplied to the A/D converter. After supplying this clock, the A/D converter automatically counts up to the A/D power supply stabilization wait time, and then A/D conversion starts.
Note
Clear the setting of the A/D conversion result comparison function (ADRCK bit and ADUL/ADLL register) to the initial value, and specify settings so that an interrupt signal is generated each time conversion is completed.
· One-shot conversion mode (select/scan) When the STOP instruction is executed after the A/D conversion is completed and the interrupt request signal (INTAD) is generated, the supplied clock can be stopped.
· Sequential conversion mode (select/scan) When ADCS is written with 0 after the A/D conversion is completed and the interrupt request signal (INTAD) is generated, the sequential conversion mode is stopped. After that, when the STOP instruction is executed after 2 cycles of the conversion clock (fAD) have elapsed, the supplied clock can be stopped.
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Figure 12 - 41 Flowchart for Setting up SNOOZE Mode (Software Trigger)
Normal operation
Start of setup
PER0 register setting
PMCAxx, PMCTxx, and PMCEx register settings
The ADCEN bit of the PER0 register is set to 1, and supplying the clock starts. The ports are set to analog input.
PMx register setting
· ADM0 register setting · ADM1 register setting · ADM2 register setting · ADUL/ADLL register setting · ADS register setting (The order of the settings is irrelevant.)
Reference voltage stabilization wait time count A
The ports are set to the input mode.
· ADM0 register FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time. ADMD bit: Select mode/scan mode
· ADM1 register ADTMD1 and ADTMD0 bits: These are used to specify the software trigger wait mode. ADSCM bit: One-shot conversion mode
· ADM2 register ADREFP1, ADREFP0, and ADREFM bits: These are used to select the reference voltage. ADRCK bit: This is used to select the range for the A/D conversion result comparison value for generating the interrupt signal from AREA1, AREA3, and AREA2. ADTYP1 and ADTYP0 bits: 8-bit/10-bit/12-bit resolution
· ADUL/ADLL register These are used to specify the upper limit and lower limit A/D conversion result comparison values.
· ADS register ADS4 to ADS0 bits: These are used to select the analog input channels.
The reference voltage stabilization wait time count indicated by A below may be required if the values of the ADREFP1 and ADREFP0 bits are changed. If the values of ADREFP1 and ADREFP0 are changed to 1 and 0, respectively: A = 5 µs Before changing as above, perform reference supply discharge (1 µs) by setting ADREFP1, ADREFP0 = 1, 1. A wait is not required if the values of ADREFP1 and ADREFP0 are changed to 0 and 0 or 0 and 1, respectively.
STOP mode
SNOOZE mode
STOP mode
Enter the STOP mode
Leave the AWC and ADCE bits at the initial value "0". These bits are not re-set.
Software trigger generation
After software trigger (ADCS = 1) is generated, the A/D converter automatically counts up to the A/D power supply stabilization wait time and A/D conversion is started in SNOOZE mode.
The A/D conversion operations are performed.
End of A/D conversion
INTAD generationNote 1
The A/D conversion end interrupt (INTAD) is generated.Note 1
Storage of conversion results in the ADCRn or
ADCRnH register
The conversion results are stored in the ADCRn or ADCRnH register.
End processingNote 2
STOP instruction availableNote 3
Note 1. Note 2. Note 3.
Clear the ADRCK bit and ADUL/ADLL register to the initial value in the initial setting, and specify settings so that an interrupt request signal (INTAD) is generated each time A/D conversion is completed. Sequential conversion mode requires the end processing. Write 0 to ADCS after INTAD is generated. Then, after 2 cycles of the conversion clock (fAD) have elapsed, the STOP instruction can be executed. If a software trigger is input after the STOP instruction, A/D conversion operation is again performed in the SNOOZE mode.
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12.8.2 A/D conversion by inputting a hardware trigger
In the SNOOZE mode, A/D conversion is triggered by inputting a hardware trigger. When performing A/D conversion by inputting a hardware trigger in SNOOZE mode, only the following two conversion modes can be used. · Hardware trigger wait mode (select mode, one-shot conversion mode) · Hardware trigger wait mode (scan mode, one-shot conversion mode) If the A/D conversion result range is specified using the ADUL and ADLL registers, A/D conversion results can be judged at a certain interval of time. Using this function enables power supply voltage monitoring and input key judgment based on A/D inputs.
Caution
The SNOOZE mode can only be specified when the high-speed on-chip oscillator clock or mediumspeed on-chip oscillator clock is selected for fCLK.
Figure 12 - 42 Block Diagram When Using SNOOZE Mode Function (in Hardware Trigger Wait Mode)
Realtime clock (RTC), 12-bit interval timer, or event input from ELCL
Hardware trigger input
A/D conversion end interrupt request signalNote
(INTAD)
A/D converter
Clock request signal (internal signal)
High-speed on-chip oscillator clock
Clock generator
When using the SNOOZE mode function, the initial setting of each register is specified before switching to the STOP mode (for details about these settings, see Figure 12 - 45 Flowchart for Setting up SNOOZE Mode (Hardware Trigger)). Just before moving to STOP mode, set bit 2 (AWC) of A/D converter mode register 2 (ADM2) to 1. After the initial settings are specified, set bit 0 (ADCE) of A/D converter mode register 0 (ADM0) to 1. If a hardware trigger is input after switching to the STOP mode, the high-speed on-chip oscillator clock is supplied to the A/D converter. After supplying this clock, the A/D converter automatically counts up to the A/D power supply stabilization wait time, and then A/D conversion starts. The SNOOZE mode operation after A/D conversion ends differs depending on whether an interrupt signal is generatedNote.
Note
Depending on the setting of the A/D conversion result comparison function (ADRCK bit, ADUL/ADLL register), there is a possibility of no interrupt signal being generated.
Caution
Select the hardware trigger signal from among the realtime clock interrupt signal (INTRTC), 32-bit interval timer interrupt signal (INTITL), and event input from the ELCL.
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(1) If an interrupt is generated after A/D conversion ends If the A/D conversion result value is inside the range of values specified by the A/D conversion result comparison function (which is set up by using the ADRCK bit and ADUL/ADLL register), the A/D conversion end interrupt request signal (INTAD) is generated.
· While in the select mode When A/D conversion ends and an A/D conversion end interrupt request signal (INTAD) is generated, the A/D converter returns to normal operation mode from SNOOZE mode. At this time, be sure to clear bit 2 (AWC = 0: SNOOZE mode release) of the A/D converter mode register 2 (ADM2). If the AWC bit is left set to 1, A/D conversion will not start normally in the subsequent SNOOZE or normal operation mode.
· While in the scan mode If even one value of the A/D conversion results of the four channels falls within the range specified by the A/D conversion result comparison function, and A/D conversion end interrupt request signal (INTAD) is generated, the A/D converter switches from the SNOOZE mode to the normal operation mode. At this time, be sure to clear bit 2 (AWC = 0: SNOOZE mode release) of the A/D converter mode register 2 (ADM2). If the AWC bit is left set to 1, A/D conversion will not start normally in the subsequent SNOOZE or normal operation mode.
Figure 12 - 43 Operation Example When Interrupt Is Generated After A/D Conversion Ends (While in Scan Mode)
INTRTC
Clock request signal (internal signal)
ADCS
Conversion channels
Comparison result from the A/D conversion result comparison function (internal signal) Interrupt signal (INTAD)
Channel 1
Channel 2
Channel 3
Channel 4
If even one comparison result at any conversion end falls within the range specified by the A/D conversion result comparison function, an interrupt is generated after conversion ends on the four channels.
The clock request signal remains at the high level.
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(2) If no interrupt is generated after A/D conversion ends If the A/D conversion result value is outside the range of values specified by the A/D conversion result comparison function (which is set up by using the ADRCK bit and ADUL/ADLL register), the A/D conversion end interrupt request signal (INTAD) is not generated.
· While in the select mode If the A/D conversion end interrupt request signal (INTAD) is not generated after A/D conversion ends, the clock request signal (an internal signal) is automatically set to the low level, and supplying the high-speed on-chip oscillator clock stops. If a hardware trigger is input later, A/D conversion work is again performed in the SNOOZE mode.
· While in the scan mode If the A/D conversion result values of the four channels do not fall within the range specified by the A/D conversion result comparison function even once, and the A/D conversion end interrupt request signal (INTAD) is not generated, the clock request signal (an internal signal) is automatically set to the low level after A/D conversion of the four channels ends, and supplying the high-speed on-chip oscillator clock stops. If a hardware trigger is input later, A/D conversion work is again performed in the SNOOZE mode.
Figure 12 - 44 Operation Example When No Interrupt Is Generated After A/D Conversion Ends (While in Scan Mode)
INTRTC
Clock request signal (internal signal)
ADCS
Conversion channels
Comparison result from the A/D conversion result comparison function (internal signal)
Interrupt signal (INTAD)
Channel 1
Channel 2
Channel 3
Channel 4
If comparison results at conversion ends of any channels do not fall within the range specified by the A/D conversion result comparison function even once, an interrupt is not generated after conversion ends on the four channels.
The clock request signal is set to the low level.
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Figure 12 - 45 Flowchart for Setting up SNOOZE Mode (Hardware Trigger)
Start of setup PER0 register setting
The ADCEN bit of the PER0 register is set to 1, and supplying the clock starts.
Normal operation
STOP mode
SNOOZE mode
Normal operation
PMCAxx, PMCTxx, and PMCEx register settings
The ports are set to analog input.
PMx register setting
· ADM0 register setting · ADM1 register setting · ADM2 register setting · ADUL/ADLL register setting · ADS register setting
(The order of the settings is irrelevant.)
Reference voltage stabilization wait time count A
AWC = 1 ADCE bit setting
The ports are set to the input mode.
· ADM0 register FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time. ADMD bit: Select mode/scan mode
· ADM1 register ADTMD1 and ADTMD0 bits: These are used to specify the hardware trigger wait mode. ADSCM bit: One-shot conversion mode ADTRS1 and ADTRS0 bits: These are used to select the hardware trigger signal.
· ADM2 register ADREFP1, ADREFP0, and ADREFM bits: These are used to select the reference voltage. ADRCK bit: This is used to select the range for the A/D conversion result comparison value for generating the interrupt signal from AREA1, AREA3, and AREA2. ADTYP1 and ADTYP0 bits: 8-bit/10-bit/12-bit resolution
· ADUL/ADLL register These are used to specify the upper limit and lower limit A/D conversion result comparison values.
· ADS register ADS4 to ADS0 bits: These are used to select the analog input channels.
The reference voltage stabilization wait time count indicated by A below may be required if the values of the ADREFP1 and ADREFP0 bits are changed. If the values of ADREFP1 and ADREFP0 are changed to 1 and 0, respectively: A = 5 µs Before changing as above, perform reference supply discharge (1 µs) by setting ADREFP1, ADREFP0 = 1, 1. A wait is not required if the values of ADREFP1 and ADREFP0 are changed to 0 and 0 or 0 and 1, respectively.
Immediately before entering the STOP mode, enable the SNOOZE mode by setting the AWC bit of the ADM2 register to 1.
The ADCE bit of the ADM0 register is set to 1, and the A/D converter enters the standby state.
The clock request signal
(an internal signal) is
No
automatically set to the low
level in the SNOOZE mode.
Enter the STOP mode
Hardware trigger generation
After hardware trigger is generated, the A/D converter automatically counts up to the stabilization wait time for A/D power supply and A/D conversion is started in the SNOOZE mode.
The A/D conversion operations are performed.
End of A/D conversion
The A/D conversion end interrupt (INTAD) is generated. Note1
INTAD generation
Yes Storage of conversion results in the ADCRn or
ADCRnH register
AWC = 0
The conversion results are stored in the ADCRn or ADCRnH register.
Release the SNOOZE mode by clearing the AWC bit of the ADM2 register to 0.Note2
Normal operation
Note 1. Note 2.
If the A/D conversion end interrupt request signal (INTAD) is not generated depending on the settings of the ADRCK bit and ADUL and ADLL registers, the result is not stored in the ADCRn or ADCRnH register. The A/D converter enters the STOP mode again. If a hardware trigger is input later, A/D conversion operation is again performed in the SNOOZE mode. If the AWC bit is left set to 1, A/D conversion will not start normally in the subsequent SNOOZE or normal operation mode. Be sure to clear the AWC bit to 0.
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12.9
How to Read A/D Converter Characteristics Table
Here, special terms unique to the A/D converter are explained. (1) Resolution
This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is expressed by %FSR (Full Scale Range).
1LSB is as follows when the resolution is 12 bits.
1 LSB = 1/212 = 1/4096 0.024 %FSR
Accuracy has no relation to resolution, but is determined by overall error. (2) Overall error
This shows the maximum error value between the actual measured value and the theoretical value. Zero-scale error, full-scale error, integral linearity error, differential linearity errors, and combinations of these express the overall error. Note that the quantization error is not included in the overall error in the characteristics table. (3) Quantization error When analog values are converted to digital values, a ±1/2LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of ±1/2LSB is converted to the same digital code, so a quantization error cannot be avoided. Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table.
Figure 12 - 46 Overall Error
1......1 Ideal line
Overall error
Digital output
0......0 0
Analog input
AVREF
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1......1
CHAPTER 12 A/D CONVERTER (ADC)
Digital output
1/2LSB
Quantization error 1/2LSB
0......0 0
Analog input
AVREF
(4) Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2LSB) when the digital output changes from 0......000 to 0......001. If the actual measurement value is greater than the theoretical value, it shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 0......001 to 0......010.
(5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale 3/2LSB) when the digital output changes from 1......110 to 1......111.
(6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0.
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CHAPTER 12 A/D CONVERTER (ADC)
(7) Differential linearity error While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value and the ideal value of the width of output code.
Figure 12 - 48 Zero-Scale Error
Digital output (lower 3 bits)
111 Ideal line
011
010
001
000 0
Zero-scale error
12
3
Analog input (LSB)
AVREF
Figure 12 - 49 Full-Scale Error
Digital output (lower 3 bits)
Full-scale error 111
110
101
000 0
Ideal line
AVREF - 3 AVREF - 2 AVREF - 1 AVREF
Analog input (LSB)
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RL78/G23 Figure 12 - 50 Integral Linearity Error
1......1 Ideal line
CHAPTER 12 A/D CONVERTER (ADC)
Digital output
0......0 0
Integral linearity error
Analog input
AVREF
Figure 12 - 51 Differential Linearity Error
1......1
Ideal 1LSB width
Digital output
0......0 0
Differential linearity error
Analog input
AVREF
(8) Conversion time This expresses the time from the start of sampling to when the digital output is obtained. The sampling time is included in the conversion time in the characteristics table.
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CHAPTER 12 A/D CONVERTER (ADC)
(9) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit.
Sampling time
A/D conversion time
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CHAPTER 12 A/D CONVERTER (ADC)
12.10 Points for Caution when the A/D Converter is to be Used
(1) Operating current in STOP mode Shift to STOP mode after stopping the A/D converter (by setting bit 7 (ADCS) of A/D converter mode register 0 (ADM0) to 0). The operating current can be reduced by setting bit 0 (ADCE) of the ADM0 register to 0 at the same time. To restart from the standby state, clear bit 0 (ADIF) of interrupt request flag register 1H (IF1H) to 0 and start operation.
(2) Input range of ANI0 to ANI14 and ANI16 to ANI26 pins Observe the rated range of the ANI0 to ANI14 and ANI16 to ANI26 pins input voltage. If a voltage exceeding VDD and AVREFP or a voltage lower than VSS and AVREFM (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. In addition, the converted values of the other channels may also be affected. When internal reference voltage is selected as the reference voltage for the + side of the A/D converter, do not input a voltage equal to or higher than the internal reference voltage to a pin selected by the ADS register. However, it is no problem that a voltage equal to or higher than the internal reference voltage is input to a pin not selected by the ADS register.
Caution
For details about the internal reference voltage, see CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
(3) Conflicting operations <1> Conflict between the write access to the A/D conversion result register (ADCRn or ADCRnH) upon the end of
conversion and the read access to the ADCRn or ADCRnH register by instruction The ADCRn or ADCRnH register read has priority. After the read operation, the new conversion result is written to the ADCRn or ADCRnH registers. <2> Conflict between the write access to the ADCRn or ADCRnH register upon the end of conversion, the write access to the A/D converter mode register 0 (ADM0), and the write access to the analog input channel specification register (ADS) The ADM0 and ADS registers write has priority. The ADCRn and ADCRnH registers write is not performed, nor is the conversion end interrupt signal (INTAD) generated. (4) Noise countermeasures To maintain the 12-bit/10-bit resolution, attention must be paid to noise input to the AVREFP, VDD, ANI0 to ANI14, and ANI16 to ANI26 pins. <1> Connect a capacitor with a low equivalent resistance and a good frequency response (capacitance of about 0.1 µF) via the shortest possible run of relatively thick wiring to the VDD and AVREFP pins. <2> The higher the output impedance of the analog input source, the greater the influence. To reduce the noise, connecting an external capacitor as shown in Figure 12 - 52 is recommended. <3> Do not switch these pins with other pins during conversion. <4> The accuracy is improved if the HALT mode is set immediately after the start of conversion.
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CHAPTER 12 A/D CONVERTER (ADC)
Figure 12 - 52 Connections of VDD, AVREFP, and Analog Input Pins
Analog input
10 pF to 0.1 µF
0.1 µF
If there is a possibility that noise equal to or higher than AVREFP and VDD or equal to or lower than AVREFM and VSS may enter, clamp with a diode with a small VF value (0.3 V or lower).
VDD AVREFP
ANI0 to ANI14, ANI16 to ANI26
0.1 µF
VSS AVREFM
(5) Analog input (ANIxx) pins <1> The analog input pins (ANI0 to ANI14 and ANI16 to ANI26) are also used as input port pins (P02, P03, P20 to P27,
P35 to P37, P100, P115 to P117, P120, P147, and P150 to P156). When A/D conversion is performed with any of the ANI0 to ANI14 and ANI16 to ANI26 pins selected, do not change to output value P02, P03, P20 to P27, P35 to P37, P100, P115 to P117, P120, P147, and P150 to P156 while conversion is in progress; otherwise the conversion resolution may be degraded. <2> If a pin adjacent to a pin that is being A/D converted is used as a digital I/O port pin, the A/D conversion result might differ from the expected value due to a coupling noise. Be sure to avoid the input or output of digital signals and signals with similarly sharp transitions during conversion. (6) Input impedance of analog input (ANIxx) pins This A/D converter charges a sampling capacitor for sampling during sampling time. Therefore, only a leakage current flows when sampling is not in progress, and a current that charges the capacitor flows during sampling. Consequently, the input impedance fluctuates depending on whether sampling is in progress. To make sure that sampling is effective, however, we recommend using the converter with analog input sources that have output impedances no greater than 1 k. If a source has a higher output impedance, lengthen the sampling time or connect a larger capacitor (with a value of about 0.1 µF) to the pin from among ANI0 to ANI14 and ANI16 to ANI26 to which the source is connected (see Figure 12 - 52). The sampling capacitor may be being charged while the setting of the ADCS bit is 0 and immediately after sampling is restarted and so is not defined at these times. Accordingly, the state of conversion is undefined after charging starts in the next round of conversion after the value of the ADCS bit has been 1 or when conversion is repeated. Thus, to secure full charging regardless of the size of fluctuations in the analog signal, ensure that the output impedances of the sources of analog inputs are low or secure sufficient time for the completion of sampling. (7) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF flag for the pre-change analog input may have been set before the ADS register is rewritten. When reading the ADIF flag immediately after rewriting to the ADS register, note that the ADIF flag is set although A/D conversion for the postchange analog input has not ended. When A/D conversion is stopped and then resumed, clear ADIF flag before the A/D conversion operation is resumed.
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Figure 12 - 53 Timing of A/D Conversion End Interrupt Request Generation
ADS rewrite (start of ANIxx conversion)
ADS rewrite (start of ANIyy conversion)
ADIF is set but ANIyy conversion has not ended.
A/D conversion
ANIxx
ANIxx
ANIyy
ANIyy
ADCR
ANIxx
ANIxx
ANIyy
ANIyy
ADIF
(8) Conversion results just after A/D conversion start While in the software trigger no-wait mode or hardware trigger no-wait mode, the first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the ADCS bit is set to 1 within 1 µs + 2 cycles of the conversion clock (fAD) after the ADCE bit was set to 1. Take measures such as polling the A/D conversion end interrupt request signal (INTAD) and removing the first conversion result.
(9) A/D conversion result register (ADCRn, ADCRnH) read operation When a write operation is performed to A/D converter mode register 0 (ADM0), analog input channel specification register (ADS), or port mode control registers (PMCAxx, PMCTxx, PMCEx), the contents of the ADCRn and ADCRnH registers may become undefined. After the completion of conversion, read the conversion result before writing to the ADM0, ADS, PMCAxx, PMCTxx, or PMCEx register; otherwise, an incorrect conversion result may be read.
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(10) Internal equivalent circuit The equivalent circuit of the analog input block is shown below.
Figure 12 - 54 Internal Equivalent Circuit of ANIxx Pin
CHAPTER 12 A/D CONVERTER (ADC)
R1 ANIxx
C1
C2
<R>
Table 12 - 4 Resistance and Capacitance Values of Equivalent Circuit (Reference Values)
AVREFP, VDD
ANIxx pin
R1 [k]
C1 [pF]
2.4 V VDD 5.5 V
ANI0 to ANI14
11
8
ANI16 to ANI26
12
8
1.8 V VDD < 2.4 V
ANI0 to ANI14
55
8
ANI16 to ANI26
60
8
1.6 V VDD < 1.8 V
ANI0 to ANI14
110
8
ANI16 to ANI26
120
8
Remark The resistance and capacitance values shown in Table 12 - 4 are not guaranteed values.
(11) Starting the A/D converter Start the A/D converter after the AVREFP and VDD voltages stabilize.
C2 [pF] 9 10 9 10 9 10
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CHAPTER 13 D/A CONVERTER (DAC)
CHAPTER 13 D/A CONVERTER (DAC)
The number of channels of the D/A converter (DAC) depends on the product.
Table 13 - 1 Output Pins of D/A Converter
D/A Output Pins ANO0 ANO1
30-pin --
32- to 128-pin
13.1
Functions of D/A Converter
The D/A converter is an 8-bit resolution converter that converts digital inputs into analog signals. It is used to control analog outputs for two independent channels (ANO0, ANO1). The D/A converter has the following features.
· 8-bit resolution 2 channels · R-2R ladder method · Output analog voltage
· 8-bit resolution: VDD m8/256 (m8: Value set to DACSi register) · Operation mode
· Normal mode · Realtime output mode
Remark i = 0, 1
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13.2
Configuration of D/A Converter
Figure 13 - 1 shows the block diagram of D/A converter.
Figure 13 - 1 Block Diagram of D/A Converter
CHAPTER 13 D/A CONVERTER (DAC)
Write signal of DACS0 register DAMD0 (DAM)
Event signal from ELCL
VDD pin
VSS pin
Internal bus
D/A conversion value setting register 0 (DACS0)
DACE0 (DAM)
Selector
ANO0/P22 pin
Write signal of DACS1 register DAMD1(DAM)
DACE1 (DAM)
Event signal from ELCL
D/A converter mode register (DAM)
D/A conversion value setting register 1 (DACS1)
Internal bus
Selector
ANO1/P23 pin
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CHAPTER 13 D/A CONVERTER (DAC)
13.3
Registers to Control the D/A Converter
The following registers are used to control the D/A converter.
· Peripheral enable register 1 (PER1) · Peripheral reset control register 1 (PRR1) · D/A converter mode register (DAM) · D/A conversion value setting register i (DACSi) (i = 0, 1) · Output signal select registers n (ELOSELn) (n = 0 to 7) · Output signal enable register (ELOENCTL) · Port mode registers (PMxx) · Port mode control A registers (PMCAxx)
13.3.1 Peripheral enable register 1 (PER1)
The PER1 register is used to enable or disable the supply of a clock signal to various on-chip peripheral modules. Clock supply to an on-chip peripheral module that is not to be used can be stopped to decrease power consumption and noise. If the D/A converter is to be used, be sure to set bit 7 (DACEN) of this register to 1. The PER1 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 13 - 2 Format of Peripheral Enable Register 1 (PER1)
Address: After reset: R/W:
F00FAH 00H R/W
Symbol
<7>
PER1 DACEN
<6> SMSEN
<5> CMPEN
<4> TML32EN
<3> DTCEN
<2> UATEN
<1> REMCEN
<0> CTSUEN
DACEN
Control of supply of an input clock to the D/A converter
0
Stops supply of an input clock.
· The SFRs used by the D/A converter cannot be written.
· When an SFR used by the D/A converter is read, the value returned is 00H or 0000H.
1
Enables supply of an input clock.
· The SFRs used by the D/A converter can be read and written.
Caution 1. When setting the D/A converter, be sure to set DACEN to 1 first. If DACEN = 0, writing to the registers which control the D/A converter is ignored, and the value read is 00H (except for port mode register 2 (PM2) and port register 2 (P2)).
Caution 2. The functions mounted depend on the product. For details on the PER1 register, see CHAPTER 6 CLOCK GENERATOR.
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CHAPTER 13 D/A CONVERTER (DAC)
13.3.2 Peripheral reset control register 1 (PRR1)
The PRR1 register is used to control resetting of the on-chip peripheral modules. Each bit in this register controls resetting and release from the reset state of the corresponding on-chip peripheral module. To place the D/A converter in the reset state, be sure to set bit 7 (DACRES) of this register to 1. The PRR1 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 13 - 3 Format of Peripheral Reset Control Register 1 (PRR1)
Address: After reset: R/W:
F00FBH 00H R/W
Symbol
<7>
<6>
<5>
<4>
3
PRR1 DACRES SMSRES CMPRES TML32RES
0
2
<1>
<0>
0
REMCRES CTSURES
DACRES
Control resetting of the D/A converter
0
The D/A converter is released from the reset state.
1
The D/A converter is in the reset state.
· The SFRs for use with the D/A converter are initialized.
Caution 1. Be sure to clear bits 3 and 2 to 0. Caution 2. The functions mounted depend on the product. For details on the PRR1 register, see CHAPTER 24
RESET FUNCTION.
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CHAPTER 13 D/A CONVERTER (DAC)
13.3.3 D/A converter mode register (DAM)
This register controls the operation of the D/A converter. The DAM register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 13 - 4 Format of D/A Converter Mode Register (DAM)
Address: After reset: R/W:
F0332H 00H R/W
Symbol
7
6
<5>
<4>
3
2
DAM
0
0
DACE1
DACE0
0
0
DACEi 0 1
D/A conversion operation control Stops D/A conversion operation Enables D/A conversion operation
1 DAMD1
0 DAMD0
DAMDi 0 1
Normal mode Realtime output mode
Remark i = 0, 1
D/A converter operation mode selection
13.3.4 D/A conversion value setting register i (DACSi) (i = 0, 1)
This register is used to set the analog voltage value to be output to the ANO0 and ANO1 pins when the D/A converter is used. The DACSi register can be read by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 13 - 5 Format of D/A Conversion Value Setting Register i (DACSi) (i = 0, 1)
Address: After reset: R/W:
F0330H (DACS0), F0331H (DACS1) 00H R/W
Symbol
7
DACSi DACSi7
6 DACSi6
5 DACSi5
4 DACSi4
3 DACSi3
2 DACSi2
1 DACSi1
0 DACSi0
Remark The relation between the resolution and analog output voltage (VANOi) of the D/A converter are as follows. VANOi = VDD (DACSi)/256
When the D/A converter is not used, set the DACEi bit to 0 (output disable) and set the DACSi register to 00H to prevent current from flowing into the R-2R resistor ladder to reduce unnecessary current consumption.
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CHAPTER 13 D/A CONVERTER (DAC)
13.3.5 Registers controlling the event output from the logic and event link controller
When the realtime output mode of the D/A converter is used, D/A conversion is performed using an event signal from the logic and event link controller as an activation trigger. For details, see 20.3.23 Output signal select registers n (ELOSELn) (n = 0 to 7) and 20.3.24 Output signal enable register (ELOENCTL).
13.3.6 Registers controlling port functions of analog input pins
Set the registers (port mode register (PMxx) and port mode control A register (PMCAxx)) that control the port functions shared with the analog output of the D/A converter. For details, see 4.3.1 Port mode registers (PMxx) and 4.3.7 Port mode control A registers (PMCAxx). When using the ANO0 and ANO1 pins for analog output of the D/A converter, set the port mode register (PMxx) bit corresponding to each port to 1, and specify analog output using the port mode control A register (PMCAxx).
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CHAPTER 13 D/A CONVERTER (DAC)
13.4
Operations of D/A Converter
13.4.1 Operation in normal mode
D/A conversion is performed using write operation to the DACSi register as the trigger. The setting method is described below.
<1> Set the DACEN bit of the PER1 register (peripheral enable register 1) to 1 to start the supply of the input clock to the D/A converter.
<2> Use the PMCA register (port mode control A register) to set the ports to analog pins. <3> Set the DAMDi bit of the DAM register (D/A converter mode register) to 0 (normal mode). <4> Set the analog voltage value to be output to the ANOi pin to the DACSi register (D/A conversion value setting
register i).
Steps <1> and <4> above constitute the initial settings.
<5> Set the DACEi bit of the DAM register to 1 (D/A conversion enable). D/A conversion starts, and then, after the settling time elapses, the analog voltage set in step <4> is output to the ANOi pin.
<6> To perform subsequent D/A conversions, write to the DACSi register.
The previous D/A conversion result is held until the next D/A conversion is performed. When the DACEi bit of the DAM register is set to 0 (D/A conversion operation stop), D/A conversion stops.
Caution 1. Even if 1, 0, and then 1 is set to the DACEi bit, the analog voltage set by the DACSi register is output to the ANOi pin when a settling time has elapsed after 1 is set for the last time.
Caution 2. If the DACSi register is rewritten during the settling time, D/A conversion is aborted and reconversion by using the rewritten values starts.
Caution 3. Set the DACRES bit of the PRR1 register to 1 to initialize all circuits of the D/A converter.
Remark i = 0, 1
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13.4.2 Operation in realtime output mode
D/A conversion is performed on each channel using the event signals from the ELCL as triggers. The setting method is described below.
<1> Set the DACRES bit of the PRR1 register (peripheral reset control register 1) to 0 to release the D/A converter from the reset state.
<2> Set the DACEN bit of the PER1 register (peripheral enable register 1) to 1 to start the supply of the input clock to the D/A converter.
<3> Use the PMCA register (port mode control A register) to set the ports to analog pins. <4> Set the DAMDi bit of the DAM register (D/A converter mode register) to 0 (normal mode). <5> Set the analog voltage value to be output to the ANOi pin to the DACSi register (D/A conversion value setting
register i). <6> Set the DACEi bit of the DAM register to 1 (D/A conversion enable).
D/A conversion starts, and then, after the settling time elapses, the analog voltage set in step <3> is output to the ANOi pin. <7> Use the registers (ELOSELn and ELOENCTL) that control the event signal output from the logic and event link controller to set the trigger signal for use in realtime output mode. <8> Set the DAMDi bit of the DAM register to 1 (realtime output mode). <9> Start the operation of the event source.
Steps <1> to <9> above constitute the initial settings.
<10>Upon generation of the trigger signals used for realtime output mode, D/A conversion starts and the analog voltage set in step <5> will be output to the ANOi pin after a settling time has elapsed. Set the analog voltage value to be output to the ANOi pin, to the DACSi register before performing the next D/A conversion (trigger signal used for realtime output mode is generated).
Set the analog voltage value to be output to the ANOi pin, to the DACSi register before performing the next D/A conversion (trigger signal used for realtime output mode is generated). When the DACEi bit of the DAM register is set to 0 (D/A conversion operation stop), D/A conversion stops.
Caution 1. Caution 2. Caution 3. Caution 4.
Even if 1, 0, and then 1 is set to the DACEi bit, the analog voltage set by the DACSi register is output to the ANOi pin when a settling time has elapsed after 1 is set for the last time. Set the interval between each generation of the trigger signal used for realtime output mode of the same channel to longer than the settling time. If a trigger signal used for realtime output mode is generated during the settling time, D/A conversion is aborted and reconversion starts. Set the interval between each generation of the trigger signal used for realtime output mode of the same channel to longer than the three clocks of fCLK. When a trigger is generated consecutively at intervals of three or fewer fCLK clock cycles, D/A conversion is performed using only the first trigger. Set the DACRES bit of the PRR1 register to 1 to initialize all circuits of the D/A converter.
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CHAPTER 13 D/A CONVERTER (DAC)
13.4.3 Timing for outputting D/A conversion value
Figure 13 - 6 shows the timing for outputting D/A conversion value.
Figure 13 - 6 Timing for Outputting D/A Conversion Value
DAMDi bit
Operating clock
Write to DACSi register enabled Event signal i from ELCL D/A conversion enabled (internal signal) D/A conversion timing
DACSi register
ANOi (data latch)
Normal mode Realtime output mode (DACEi = 0)
Data 0 Data 0
Data 1
Remark i = 0, 1
Realtime output mode (DACEi = 1)
Data 1
Data 2
Data 2
· Normal mode and realtime output mode (when conversion operation is disabled) The value is written to the data latch after one cycle of the operating clock when the DACSi register is written.
· Realtime output mode (when conversion operation is enabled) The value is written to the data latch (output from the ANOi pin) after three cycles of the operating clock when the event signal from the ELCL is accepted.
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CHAPTER 13 D/A CONVERTER (DAC)
13.5
Points for Caution when the D/A Converter is to be Used
Observe the following cautions when using the D/A converter.
(1) The digital port I/O function, which is the alternate function of the ANO0 and ANO1 pins, does not operate if the ports are set to analog pins by using the PMCA (port mode control A register). When the P2 register is read while the ports are set to analog pins by using the PMCA register, 0 is read in the input mode and the set value of the P2 register is read in the output mode. If the digital output mode is set, no output data is output to pins.
(2) The operation of the D/A converter continues in the HALT and STOP modes. To lower the power consumption, therefore, clear the DACEi bit to 0, and execute the HALT or STOP instruction after stopping the operation of the D/A converter.
Remark i = 0, 1
(3) To stop the realtime output mode (including when changing to normal mode), one of the following procedures must be used:
· Wait for at least three clocks after stopping the trigger output source and then set bits DACEi and DAMDi to 0. · After setting bits DACEi and DAMDi, set the DACEN bit of the PER1 register to 0 (stopping supply of the input
clock to the DAC). Note that setting the DACEN bit to 0 does not initialize the D/A converter. Use bit 7 (DACRES) of PRR1 to initialize the D/A converter and its SFRs.
(4) When D/A conversion operation is enabled, do not perform A/D conversions from the analog input pins multiplexed with the ANO0 and ANO1 pins.
(5) In realtime output mode, set the value of the DACSi register before a trigger signal used for realtime output mode is generated. Do not change the set value of the DACSi register while the trigger signal is output.
(6) Since the output impedance of the D/A converter is high, no current can be taken out from the ANO0 or ANO1 pin. If the input impedance of the load is low, insert a follower amplifier between the load and the ANO0 and ANO1 pins before use. In addition, the wiring length between the follower amplifier and the load must be as short as possible due to the high output impedance. If the wiring length is long, take measures such as placing a ground pattern around the wiring area.
(7) When entering STOP mode while realtime output mode is enabled, disable linking of ELC events before entering STOP mode.
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CHAPTER 14 COMPARATOR (CMP)
CHAPTER 14 COMPARATOR (CMP)
14.1
Functions of Comparator
The comparator has the following functions.
· Comparator high-speed mode, or comparator low-speed mode can be selected. · The external reference voltage input and the internal reference voltage Note or D/A converter output Note are selectable
as the reference voltage. · The canceling width of the noise canceling digital filter can be selected. · An interrupt signal can be generated by detecting an active edge of the comparator output. · An event signal can be output to the logic and event link controller (ELCL) by detecting an active edge of the
comparator output.
Note
The internal reference voltage and D/A converter output 0 are selectable for comparators 0 and 1, respectively.
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14.2
Configuration of Comparator
Figure 14 - 1 shows the Comparator Block Diagram.
Figure 14 - 1 Comparator Block Diagram
CHAPTER 14 COMPARATOR (CMP)
Comparator mode setting register (COMPDR) C0MON C0VRF C0LVL C0ENB
Comparator filter control register (COMPFIR) C0EDG C0EPO C0FCK1 C0FCK0
IVCMP0 IVREF0
Internal reference voltage
Selector
Selector Selector
fCLK fCLK/8 fCLK/32
Sampling clock
Digital filter (match 3 times)
Selector Selector
Comparator 0
Both-edge detection
One-edge detection
COMP0 Event signal for the ELCL
INTCMP0 (Comparator detection 0 interrupt)
VCOUT0
I/O control
Selector
Comparator mode setting register (COMPDR) C1MON C1VRF C1LVL C1ENB
SPDMD C0OP C0OE C0IE Comparator output control register (COMPOCR)
Comparator filter control register (COMPFIR) C1EDG C1EPO C1FCK1 C1FCK0
IVCMP1 IVREF1
D/A converter output 0
Selector
Selector Selector
fCLK fCLK/8 fCLK/32
Sampling clock
Digital filter (match 3 times)
Selector Selector
Comparator1
Both-edge detection
One-edge detection
COMP1 Event signal for the ELCL
INTCMP1 (Comparator detection 1 interrupt)
VCOUT1
I/O control
Selector
SPDMD C1OP C1OE C1IE Comparator output control register (COMPOCR)
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14.3
Registers to Control the Comparator
The following registers are used to control the comparator.
· Peripheral enable register 1 (PER1) · Peripheral reset control register 1 (PRR1) · Comparator mode setting register (COMPMDR) · Comparator filter control register (COMPFIR) · Comparator output control register (COMPOCR) · Port mode control A registers (PMCAxx) · Port mode registers (PMxx) · Port registers (Pxx)
14.3.1 Peripheral enable register 1 (PER1)
The PER1 register is used to enable or disable the supply of a clock signal to various on-chip peripheral modules. Clock supply to an on-chip peripheral module that is not to be used can be stopped to decrease power consumption and noise. If the comparator is to be used, be sure to set bit 5 (CMPEN) of this register to 1. The PER1 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 14 - 2 Format of Peripheral Enable Register 1 (PER1)
Address: After reset: R/W:
F00FAH 00H R/W
Symbol
<7>
PER1 DACEN
<6> SMSEN
<5> CMPEN
<4> TML32EN
<3> DTCEN
<2> UTAEN
<1> REMCEN
<0> CTSUEN
CMPEN
Control of supply of an input clock to the comparator
0
Stops supply of an input clock.
· The SFRs used by the comparator cannot be written.
· When an SFR used by the comparator is read, the value returned is 00H or 0000H.
1
Enables supply of an input clock.
· The SFRs used by the comparator can be read and written.
Caution
When setting the comparator, be sure to set the CMPEN bit to 1 first. If CMPEN = 0, writing to the registers which control the comparator is ignored (except for port mode control A registers 1, 2, 12, 14 (PMCA1, PMCA2, PMCA12, PMCA14), port mode registers 1, 2, 3, 12, 14 (PM1, PM2, PM3, PM12, PM14), and port registers 1, 2, 3, 12, 14 (P1, P2, P3, P12, P14)).
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14.3.2 Peripheral reset control register 1 (PRR1)
The PRR1 register is used to control resetting of the on-chip peripheral modules. Each bit in this register controls resetting and release from the reset state of the corresponding on-chip peripheral module. To place the comparator in the reset state, be sure to set bit 5 (CMPRES) of this register to 1. The PRR1 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 14 - 3 Format of Peripheral Reset Control Register 1 (PRR1)
Address: After reset: R/W:
F00FBH 00H R/W
Symbol
<7>
<6>
<5>
<4>
3
PRR1 DACRES SMSRES CMPRES TML32RES
0
2
<1>
<0>
0
REMCRES CTSURES
CMPRES
Control resetting of the comparator
0
The comparator is released from the reset state.
1
The comparator is in the reset state.
· The SFRs for use with the comparator are initialized.
Caution 1. Be sure to set bits 2 and 3 to 0. Caution 2. The functions that are mounted depend on the product. For details on the PRR1 register, see the
description in CHAPTER 24 RESET FUNCTION.
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14.3.3 Comparator mode setting register (COMPMDR)
The COMPMDR register is used to make the various settings of comparators 0 and 1, such as selection of the reference voltage, starting or stopping comparing operation, and also indicates the results of comparison. The COMPMDR register can be set by a 1-bit or 8-bit memory manipulation instruction. Note that the CnMON bit is read-only. The value of this register is 00H following a reset.
Figure 14 - 4 Format of Comparator Mode Setting Register (COMPMDR)
Address: After reset: R/W:
F0340H 00H R/W
Symbol
7
COMPMDR C1MON
6 C1VRF
5 C1LVL
<4> C1ENB
3 C0MON
2 C0VRF
1 C0LVL
C1MON 0 1
Comparator 1 monitor flagNotes 1, 2 IVCMP1 < comparator 1 reference voltage (IVREF1 or D/A converter output 0) IVCMP1 > comparator 1 reference voltage (IVREF1 or D/A converter output 0)
<0> C0ENB
C1VRF 0 1
Selection of comparator 1 reference voltage Supply through the IVREF1 pin Supply through D/A converter output 0
C1LVL 0 1
0 to VDD - 1.4 V 1.4 V to VDD
Selection of comparator 1 reference voltage range
C1ENB 0 1
Comparator 1 operation enable Comparator 1 operation disabled Comparator 1 operation enabled
C0MON 0 1
Comparator 0 monitor flagNotes 1, 2 IVCMP0 < comparator 0 reference voltage (IVREF0 or internal reference voltage) IVCMP0 > comparator 0 reference voltage (IVREF0 or internal reference voltage)
C0VRF 0 1
Selection of comparator 0 reference voltageNote 3 Supply through the IVREF0 pin Supply through the internal reference voltage
C0LVL 0 1
0 to VDD - 1.4 V 1.4 V to VDD
Selection of comparator 0 reference voltage rangeNote 3
C0ENB 0 1
Comparator 0 operation enable Comparator 0 operation disabled Comparator 0 operation enabled
(Notes are listed on the next page.)
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Note 1.
Note 2. Note 3.
The initial value is 0 immediately after a reset is released. However, the value is undefined when C0ENB is set to 0 and C1ENB is set to 0 after operation of the comparator is enabled once. Bits 7 and 3 are read-only. The value written to these bits is ignored. When the internal reference voltage (C0VRF = 1) is to be used as the comparator 0 reference voltage, C0LVL = 0 and VDD (internal reference voltage (max.) + 1.4 V) must be satisfied.
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14.3.4 Comparator filter control register (COMPFIR)
The COMPFIR register is used to select the valid edge for use with the comparator interrupt signals and whether or not to use the digital filter. If rejecting noise is required, set the CnFCK1 and CnFCK0 bits to enable the digital filters. While a digital filter is enabled, the filter conveys the input level after detecting matches for three cycles of the sampling clock for use with the filter. The COMPFIR register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 14 - 5 Format of Comparator Filter Control Register (COMPFIR)
Address: After reset: R/W:
F0341H 00H R/W
Symbol
7
COMPFIR C1EDG
6 C1EPO
5 C1FCK1
4 C1FCK0
3 C0EDG
2 C0EPO
1 C0FCK1
0 C0FCK0
C1EDG 0 1
Comparator 1 edge detection selection Note 1 Interrupt request by comparator 1 one-edge detection Interrupt request by comparator 1 both-edge detection
C1EPO 0 1
Comparator 1 edge polarity switching Note 1 Interrupt request at comparator 1 rising edge Interrupt request at comparator 1 falling edge
C1FCK1 0 0 1 1
C1FCK0 0 1 0 1
Comparator 1 filter selection Notes 1, 3 No comparator 1 filter Comparator 1 filter enabled, sampling at fCLK Comparator 1 filter enabled, sampling at fCLK/8 Comparator 1 filter enabled, sampling at fCLK/32
C0EDG 0 1
Comparator 0 edge detection selection Note 2 Interrupt request by comparator 0 one-edge detection Interrupt request by comparator 0 both-edge detection
C0EPO 0 1
Comparator 0 edge polarity switching Note 2 Interrupt request at comparator 0 rising edge Interrupt request at comparator 0 falling edge
C0FCK1 0 0 1 1
C0FCK0 0 1 0 1
Comparator 0 filter selection Notes 2, 3 No comparator 0 filter Comparator 0 filter enabled, sampling at fCLK Comparator 0 filter enabled, sampling at fCLK/8 Comparator 0 filter enabled, sampling at fCLK/32
(Notes are listed on the next page.)
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Note 1. Note 2. Note 3.
Changing the C1FCK0 and C1FCK1 bit field or the C1EPO or C1EDG bit may lead to the generation of an event signal for the ELCL and a comparator 1 interrupt request. Only change these bits while the output from comparator 1 is not selected as an input signal to the ELCL and the comparator 1 interrupt is masked. After that, to use the comparator 1 interrupt, clear the CMPIF1 bit to 0 and then clear the CMPMK1 bit to 0 to enable the interrupt. If the C1FCK1 and C1FCK0 bits are changed from 00B (no comparator 1 filter) to a value other than 00B (comparator 1 filter enabled), allow the time for sampling four times to elapse until the filter output is updated, and then use the comparator 1 interrupt request or the event signal for the ELCL. Changing the C0FCK1 and C0FCK0 bit field or the C0EPO or C0EDG bit may lead to the generation of an event signal for the ELCL and a comparator 0 interrupt request. Only change these bits while the output from comparator 0 is not selected as an input signal to the ELCL and the comparator 0 interrupt is masked. After that, to use the comparator 0 interrupt, clear the CMPIF0 bit to 0 and then clear the CMPMK0 bit to 0 to enable the interrupt. If the C0FCK1 and C0FCK0 bits are changed from 00B (no comparator 0 filter) to a value other than 00B (comparator 0 filter enabled), allow the time for sampling four times to elapse until the filter output is updated, and then use the comparator 0 interrupt request or the event signal for the ELCL. When using the comparators in STOP mode, make the settings for non-use of the filters (C0FCK1 and C0FCK0 = 00B, C1FCK1 and C1FCK0 = 00B).
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14.3.5 Comparator output control register (COMPOCR)
The COMPOCR register is used to select items including the response speed of the comparators, control of the VCOUTn outputs, and enabling or disabling the interrupt request signals. The COMPOCR register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 14 - 6 Format of Comparator Output Control Register (COMPOCR)
Address: After reset: R/W:
F0342H 00H R/W
Symbol
7
COMPOCR SPDMD
6 C1OP
<5> C1OE
<4> C1IE
3
2
0
C0OP
SPDMD 0 1
Comparator speed selection Note 1 Comparator low-speed mode Comparator high-speed mode
<1> C0OE
<0> C0IE
C1OP 0 1
VCOUT1 output polarity selection Comparator 1 output is output to VCOUT1 Inverted comparator 1 output is output to VCOUT1
C1OE 0 1
VCOUT1 pin output enable Comparator 1 VCOUT1 pin output disabled Comparator 1 VCOUT1 pin output enabled
C1IE 0 1
Comparator 1 interrupt request enable Note 2 Comparator 1 interrupt request disabled Comparator 1 interrupt request enabled
C0OP 0 1
VCOUT0 output polarity selection Comparator 0 output is output to VCOUT0 Inverted comparator 0 output is output to VCOUT0
C0OE 0 1
VCOUT0 pin output enable Comparator 0 VCOUT0 pin output disabled Comparator 0 VCOUT0 pin output enabled
C0IE 0 1
Comparator 0 interrupt request enable Note 3 Comparator 0 interrupt request disabled Comparator 0 interrupt request enabled
Note 1. Note 2.
Note 3.
When rewriting the SPDMD bit, be sure to set the CiENB bit (i = 0, 1) in the COMPMDR register to 0 in advance. If the C1IE bit is changed from 0 (interrupt request disabled) to 1 (interrupt request enabled), since bit 0 (CMPIF1) in the interrupt request flag register 2H (IF2H) may be set to 1 (interrupt requested), clear bit 0 (CMPIF1) in the interrupt request flag register 2H (IF2H) to 0 before using an interrupt. If the C0IE bit is changed from 0 (interrupt request disabled) to 1 (interrupt request enabled), since bit 0 (CMPIF0) in the interrupt request flag register 2H (IF2H) may be set to 1 (interrupt requested), clear bit 0 (CMPIF0) in the interrupt request flag register 2H (IF2H) to 0 before using an interrupt.
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14.3.6 Registers controlling port functions of analog input pins
When using the IVCMP0, IVCMP1, IVREF0, and IVREF1 pins for analog input of the comparator, set the corresponding bits of the port mode register (PMxx) and port mode control A register (PMCAxx) to 1.
When using the VCOUT0 and VCOUT1 functions, set the registers (port mode register (PMxx) and port register (Pxx)) that control the port functions shared with comparators 0 and 1. For details, see 4.3.1 Port mode registers (PMxx) and 4.3.2 Port registers (Pxx).
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CHAPTER 14 COMPARATOR (CMP)
14.4
Operation
Comparator 0 and comparator 1 operate independently. Their setting methods and operations are the same. Table 14 1 lists the Procedure for Setting Comparator Associated Registers.
Table 14 - 1 Procedure for Setting Comparator Associated Registers
Step
Register
Bit
Setting Value
1 PRR1
CMPRES
0 (releasing comparator i from the reset state)
2 PER1
CMPEN
1 (enabling input clock supply)
3 PMCAxx
PMCA13, PMCA23, PMCA120, PMCA147
Select the function of pins IVCMPi and IVREFi. · Set the PMCA13, PMCA23, PMCA120, and PMCA147 bits to 1 (analog input). · Set the PM13, PM23, PM120, and PM147 bits to 1 (input mode).
PMxx
PM13, PM23, PM120, PM147
4 COMPOCR
SPDMD
Select the comparator response speed (0: Low-speed mode, 1: High-speed mode).
Note 1
5 COMPMDR
CiVRF
Select the reference voltage. (For i = 0, 0: Input to the IVREF0 pin, 1: Internal reference voltage (For i = 1, 0: Input to the IVREF1 pin, 1: D/A converter output 0)
CiLVL
Select the reference input voltage range. (0: 0 to VDD - 1.4 V, 1: 1.4 V to VDD)
6 COMPMDR
CiENB
1 (operation enabled)
7 Wait for comparator stabilization time tCMP.
8 COMPFIR 9
CiFCK1 and CiFCK0 Select whether the digital filter is used or not and the sampling clock.
CiEPO, CiEDG
Select the edge detection condition for an interrupt request (rising edge/falling edge/both edges).
10 COMPOCR
CiOP, CiOE
Set the VCOUTi output (select the polarity and set output enabled or disabled).
CiIE
Set the interrupt request output enabled or disabled.
11 Select the port logic output pin: VCOUTi. Refer to 14.4.4 Comparator i output (i = 0, 1).
12 PR02H
CMPPR0i, CMPPR1i When using an interrupt: Select the interrupt priority level.
13 MK2H
CMPMKi
When using an interrupt: Select the interrupt masking.
14 IF2H
CMPIFi
When using an interrupt: 0 (no interrupt requested: initialization) Note 2
Note 1. Note 2.
Comparator 0 and comparator 1 cannot be set independently. After the setting of the comparator, an unnecessary interrupt may occur until operation becomes stable, so initialize the interrupt flag.
Caution To initialize all circuits of comparator i, set the CMPRES bit in the PRR1 register to 1.
Remark i = 0, 1
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CHAPTER 14 COMPARATOR (CMP)
Figure 14 - 7 shows an operation example of comparator i (i = 0, 1). In both low-speed mode and high-speed mode, the CiMON bit in the COMPMDR register is set to 1 when the analog input voltage is higher than the reference input voltage, and the CiMON bit is set to 0 when the analog input voltage is lower than the reference input voltage. The input voltage to the IVREF0 pin is selected for use as the reference voltage.
Figure 14 - 7 Comparator i (i = 0, 1) Operation Example
Example
Analog input voltage (V)
Reference input voltage (external IVREF0)
1 CiMON bit in COMPMDR register 0
In low-speed mode, longer delay time until the determined-result output, but lower power consumption
CMPIFi bit in interrupt 1
In high-speed mode, shorter delay time until the determined-result output, but higher power consumption
control register
0
(A)
(B)
(A)
(B)
Set to 0 by a program
Caution
The above diagram applies when CiFCK1 and CiFCK0 in the COMPFIR register = 00B (no filter) and CiEDG = 1 (both edges). When CiEDG = 0 and CiEPO = 0 (rising edge), CMPIFi changes as shown by (A) only. When CiEDG = 0 and CiEPO = 1 (falling edge), CMPIFi changes as shown by (B) only.
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CHAPTER 14 COMPARATOR (CMP)
14.4.1 Comparator i digital filter (i = 0, 1)
Comparator i contains a digital filter. The sampling clock can be selected by bits CiFCK1 and CiFCK0 in the COMPFIR register. The comparator i output signal is sampled every sampling clock, and when the level matches three times, that value is determined as the digital filter output at the next sampling clock. Figure 14 - 8 shows the Comparator i (i = 0, 1) Digital Filter and Interrupt Operation Example.
Figure 14 - 8 Comparator i (i = 0, 1) Digital Filter and Interrupt Operation Example
CiMON
Sampling timing
CMPIFi bit in interrupt control register
If the level does not match three times,
it is assumed to be noise and the CMPIFi bit does not change
Since the level matched three times , it is
recognized as a signal change and the CMPIFi
bit is set to 1
Set to 0 by a program
Caution The above operation example applies when bits CiFCK1 and CiFCK0 in the COMPFIR register is 01B, 10B, or 11B (digital filter enabled).
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14.4.2 Comparator i (i = 0, 1) interrupts
The comparator generates interrupt requests from two sources, comparator 0 and comparator 1. The comparator i interrupt each uses a priority level specification flag, an interrupt mask flag, an interrupt request flag, and a single vector. When using the comparator i interrupt, set the CiIE bit in the COMPOCR register to 1 (interrupt request output enabled). The condition for interrupt request generation can be set by the COMPFIR register. The comparator outputs can also be passed through the digital filter. Three different sampling clocks can be selected for the digital filter. For details on the register setting and interrupt request generation, refer to 14.3.4 Comparator filter control register (COMPFIR) and 14.3.5 Comparator output control register (COMPOCR).
14.4.3 Event signal output for the logic and event link controller (ELCL)
An event signal for the ELCL is generated by detecting the edge for the digital filter output set by the COMPFIR register, which is the same as the condition for interrupt request generation. However, unlike interrupt requests, the event signal for the ELCL is always output regardless of the setting of the CilE bit in the COMPOCR register. Set the output signal select registers n (ELOSELn) and output signal enable register (ELOENCTL) of the ELCL to select the event output destination and to stop linking events.
Figure 14 - 9 Digital Filter and Interrupt Request/Event Signal Output for the ELCL
Digital filter input Sampling timing
Digital filter output
If the level does not match three times , it is assumed to be noise and the output does not change
When the level matches three times , it is recognized as a signal and applies to the output
If the level does not match three times, it is assumed to be noise
and the output does not change
When the level matches three times, it is recognized as a signal and applies to the output
(A)
(B)
(C) Interrupt request, ELCL event signal Note
(D)
When the digital filter input changes, a oneshot pulse is output
The digital filter input is output without modification
The inverted digital filter input is output
When the digital filter output changes, a one-shot pulse is output
(E)
The digital filter output is output without modification
(F)
The inverted digital filter output is output
Note
When the CiIE bit (i = 0, 1) is 1, the same waveform is generated for an interrupt request and an ELCL event signal. When the CiIE bit (i = 0, 1) is 0, the value is fixed at 0 for an interrupt request only.
The waveforms of (A), (B), and (C) are shown for an operation example when the CiFCK bits (i = 0, 1) in the COMPFIR register are 00B (no digital filter). The waveforms (D), (E), and (F) are shown for an operation example when the CiFCK bits (i = 0, 1) in the COMPFIR register are 01B, 10B, or 11B (digital filter enabled). (A) and (D) apply when the CiEDG bit is set to 1 (both edges), (B) and (E) when the CiEDG bit is 0 and the CiEPO bit is 0 (rising edge), and (C) and (F) when the CiEDG bit is 0 and the CiEPO bit is 1 (falling edge).
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14.4.4 Comparator i output (i = 0, 1)
The comparison result from the comparator can be output to external pins. Bits CiOP and CiOE in the COMPOCR register can be used to set the output polarity (non-inverted output or inverted output) and output enabled or disabled. For the correspondence between the register setting and the comparator output, refer to 14.3.5 Comparator output control register (COMPOCR). To output the comparator comparison result to the VCOUTi output pin, use the following procedure to set the ports. Note that the ports are set to input after reset.
<1> Set the mode for the comparator (steps 1 to 9 as listed in Table 14 - 1 Procedure for Setting Comparator Associated Registers).
<2> Select the polarity of the VCOUT0 or VCOUT1 output and enable the output (step 11 as listed in Table 14 - 1 Procedure for Setting Comparator Associated Registers).
<3> Set the corresponding port mode control register bit for the VCOUTi output pin to 0. <4> Set the corresponding port register bit for the VCOUTi output pin to 0. <5> Set the corresponding port mode register for the VCOUTi output pin to output (start outputting from the pin).
14.4.5 Stopping or supplying comparator clock
To stop the comparator clock by setting peripheral enable register 1 (PER1), use the following procedure:
<1> Set the CiIE bit (i = 0, 1) in the COMPOCR register to 0 (disable a comparator interrupt). <2> Set the CiENB bit in the COMPMDR register to 0 (stop the comparator). <3> Set the CMPIFi bit in the IF2H register to 0 (clear any unnecessary interrupt before stopping the comparator). <4> Set the CMPEN bit in the PER1 register to 0.
When the clock is stopped by setting PER1, all the internal registers in the comparator are not initialized. The values of these registers are retained.
Caution
When DTC activation is enabled under either of the following conditions, a DTC transfer is started and an interrupt is generated after completion of the transfer. Therefore, check the monitor flag (CnMON) of the comparator before enabling DTC activation as required (n = 0, 1). The comparator is set to an interrupt request on one-edge detection (CnEDG = 0), an interrupt
request at the rising edge for the comparator (CnEPO = 0), and IVCMP > comparator n reference voltage The comparator is set to an interrupt request on one-edge detection (CnEDG = 0), an interrupt request at the falling edge for the comparator (CnEPO = 1), and IVCMP < comparator n reference voltage
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
A single serial array unit has up to four serial channels. Each channel can achieve 3-wire serial (SPI or CSINote), UART, and simplified I2C communication. Function assignment of each channel supported by the RL78/G23 is as shown below.
<R> Note
Although the CSI function is generally called SPI, it is also called CSI in this product, so it is referred to as such in this manual.
<30- and 32-pin products>
Unit 0
1
Channel 0 1 2 3 0 1
Used as SPI (CSI) CSI00 -- -- CSI11 CSI20 --
Used as UART UART0
UART1
UART2 (supporting LIN-bus)
Used as Simplified I2C IIC00 -- -- IIC11 IIC20 --
<36-, 40-, and 44-pin products>
Unit 0
1
Channel 0 1 2 3 0 1
Used as SPI (CSI) CSI00 -- -- CSI11 CSI20 CSI21
Used as UART UART0
UART1
UART2 (supporting LIN-bus)
Used as Simplified I2C IIC00 -- -- IIC11 IIC20 IIC21
<48- and 52-pin products>
Unit 0
1
Channel 0 1 2 3 0 1
Used as SPI (CSI) CSI00 CSI01 -- CSI11 CSI20 CSI21
Used as UART UART0
UART1
UART2 (supporting LIN-bus)
Used as Simplified I2C IIC00 IIC01 -- IIC11 IIC20 IIC21
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<64-pin products>
Unit 0
1
Channel 0 1 2 3 0 1
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Used as SPI (CSI) CSI00 CSI01 CSI10 CSI11 CSI20 CSI21
Used as UART UART0
UART1
UART2 (supporting LIN-bus)
Used as Simplified I2C IIC00 IIC01 IIC10 IIC11 IIC20 IIC21
<80-, 100-, and 128-pin products>
Unit 0
1
Channel 0 1 2 3 0 1 2 3
Used as SPI (CSI) CSI00 CSI01 CSI10 CSI11 CSI20 CSI21 CSI30 CSI31
Used as UART UART0 UART1
UART2 (supporting LIN-bus) UART3
Used as Simplified I2C IIC00 IIC01 IIC10 IIC11 IIC20 IIC21 IIC30 IIC31
When "UART0" is used for channels 0 and 1 of the unit 0, CSI00 and CSI01 cannot be used, but CSI10, UART1, or IIC10 in channels 1 and 3 can be used.
Caution
Most of the following descriptions in this chapter use the units and channels of the 128-pin products as an example.
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15.1
Functions of Serial Array Unit
Each serial interface supported by the RL78/G23 has the following features.
15.1.1 3-wire Serial SPI (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31)
Data is transmitted or received in synchronization with the serial clock (SCK) output from the master. 3-wire serial communication is clocked communication performed by using three communication lines: one for the serial clock (SCK), one for transmitting serial data (SO), one for receiving serial data (SI). For details about the settings, see 15.5 Operation of 3-Wire Serial SPI (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) Communication.
[Data transmission/reception]
· Data length of 7 or 8 bits · Phase control of transmit/receive data · MSB/LSB first selectable [Clock control]
· Master/slave selection · Phase control of I/O clock · Setting of transfer period by prescaler and internal counter of each channel · Maximum transfer rateNote During master communication: Max. fCLK/2 (CSI00 only)
Max. fCLK/4 During slave communication: Max. fMCK/6 [Interrupt function]
· Transfer end interrupt/buffer empty interrupt [Error detection flag]
· Overrun error
In addition, SPIs (CSIs) of following channels support the SNOOZE mode. In the SNOOZE mode, data can be received without CPU processing upon detecting SCK input in the STOP mode. The SNOOZE mode is only available in the following SPIs (CSIs), which support asynchronous reception.
· 30- to 64-pin products: CSI00 · 80- to 128-pin products: CSI00 and CSI20
Note
Set up the transfer rate within a range satisfying the SCK cycle time (tKCY). For details, see CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.1.2 UART (UART0 to UART3)
This is a start-stop synchronization communication function using two lines: serial data transmission (TxD) and serial data reception (RxD) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party. Full-duplex UART communication can be performed by using a channel dedicated to transmission (even-numbered channel) and a channel dedicated to reception (odd-numbered channel). The LIN-bus can be implemented by using timer array unit with an external interrupt (INTP0). For details about the settings, see 15.6 Operation of UART (UART0 to UART3) Communication.
[Data transmission/reception] · Data length of 7, 8, or 9 bits Note · MSB/LSB first selectable · Level setting of transmit/receive data and select of reverse · Parity bit appending and parity check functions · Stop bit appending [Interrupt function]
· Transfer end interrupt/buffer empty interrupt · Error interrupt in case of framing error, parity error, or overrun error [Error detection flag]
· Framing error, parity error, or overrun error
In addition, UART reception of following channels supports the SNOOZE mode. In the SNOOZE mode, data can be received without CPU processing upon detecting RxD input in the STOP mode. The SNOOZE mode is only available in the following UARTs, which support the reception baud rate adjustment function. · 30- to 64-pin products: UART0 · 80- to 128-pin products: UART0 and UART2
The LIN-bus is accepted in UART2 (channels 0 and 1 of unit 1) (30-pin to 128-pin products only).
[LIN-bus functions]
· Wakeup signal detection · Break field (BF) detection · Sync field measurement, baud rate calculation
Using the external interrupt (INTP0) and timer array unit
Note
Only the following UARTs support the 9-bit data length. · 30- to 64-pin products: UART0 · 80- to 128-pin products: UART0 and UART2
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.1.3 Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31)
This is a clocked communication function to communicate with two or more devices by using two lines: serial clock (SCL) and serial data (SDA). This simplified I2C is designed for single communication with a device such as EEPROM, flash memory, or A/D converter, and therefore, it functions only as a master. Make sure by using software, as well as operating the control registers, that the AC specifications of the start and stop conditions are observed. For details about the settings, see 15.8 Operation of Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) Communication.
[Data transmission/reception]
· Master transmission, master reception (only master function with a single master) · ACK output function Note and ACK detection function · Data length of 8 bits
(When an address is transmitted, the address is specified by the higher 7 bits, and the least significant bit is used for R/W control.) · Manual generation of start condition and stop condition [Interrupt function]
· Transfer end interrupt [Error detection flag]
· ACK error, or overrun error
* [Functions not supported by simplified I2C]
· Slave transmission, slave reception · Arbitration loss detection function · Clock stretch detection
Note
When receiving the last data, ACK will not be output if 0 is written to the SOEmn bit (serial output enable register m (SOEm)) and serial communication data output is stopped. See 15.8.3 (2) Processing flow for details.
Remark 1. To use an I2C bus of full function, see CHAPTER 16 SERIAL INTERFACE IICA (IICA). Remark 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.2
Configuration of Serial Array Unit
The serial array unit includes the following registers, and input and output pins.
Table 15 - 1 Configuration of Serial Array Unit
Item
Configuration
Shift register
8 or 9 bitsNote 1
Buffer register
Lower 8 bits or 9 bits of serial data register mn (SDRmn)Notes 1, 2
Serial clock I/O
SCK00, SCK01, SCK10, SCK11, SCK20, SCK21, SCK30, SCK31 pins (for 3-wire serial SPI), SCL00, SCL01, SCL10, SCL11, SCL20, SCL21, SCL30, SCL31 pins (for simplified I2C)
Serial data input
SI00, SI01, SI10, SI11, SI20, SI21, SI30, SI31 pins (for 3-wire serial SPI), RxD0, RxD1, RxD3 pins (for UART), RxD2 pin (for UART supporting LIN-bus)
Serial data output
SO00, SO01, SO10, SO11, SO20, SO21, SO30, SO31 pins (for 3-wire serial SPI), TxD0, TxD1, TxD3 pins (for UART), TxD2 pin (for UART supporting LIN-bus)
Serial data I/O
SDA00, SDA01, SDA10, SDA11, SDA20, SDA21, SDA30, SDA31 pins (for simplified I2C)
Control registers
<Registers of unit setting block> · Peripheral enable register 0 (PER0) · Peripheral reset control register 0 (PRR0) · Serial clock select register m (SPSm) · Serial channel enable status register m (SEm) · Serial channel start register m (SSm) · Serial channel stop register m (STm) · Serial output enable register m (SOEm) · Serial output register m (SOm) · Serial output level register m (SOLm) · Serial standby control register m (SSCm) · Input switch control register (ISC) · Noise filter enable register 0 (NFEN0)
<Registers of each channel> · Serial data register mn (SDRmn) · Serial mode register mn (SMRmn) · Serial communication operation setting register mn (SCRmn) · Serial status register mn (SSRmn) · Serial flag clear trigger register mn (SIRmn)
· Port input mode registers 0, 1, 4, 5, 8, 14 (PIM0, PIM1, PIM4, PIM5, PIM8, PIM14) · Port output mode registers 0, 1, 4, 5, 7 to 9, 14 (POM0, POM1, POM4, POM5, POM7 to POM9, POM14) · Port mode control A, T, E registers (PMCAxx, PMCTxx, PMCEx) · Port mode registers 0, 1, 3 to 5, 7 to 9, 14 (PM0, PM1, PM3 to PM5, PM7 to PM9, PM14) · Port registers 0, 1, 3 to 5, 7 to 9, 14 (P0, P1, P3 to P5, P7 to P9, P14) · Port function output enable register (PFOE1) · UART loopback select register (ULBS)
Note 1. Note 2.
The number of bits used as the shift register and buffer register differs depending on the unit and channel. · 30- to 64-pin products and mn = 00, 01: lower 9 bits · 80- to 128-pin products and mn = 00, 01, 10, 11: lower 9 bits · Other than above: lower 8 bits The lower 8 bits of serial data register mn (SDRmn) can be read or written as the following SFR, depending on the communication mode. · CSIp communication ... SIOp (CSIp data register) · UARTq reception ... RxDq (UARTq receive data register) · UARTq transmission ... TxDq (UARTq transmit data register) · IICr communication ... SIOr (IICr data register)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31) q: UART number (q = 0 to 3), r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31)
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Figure 15 - 1 shows the block diagram of serial array unit 0.
Figure 15 - 1 Block Diagram of Serial Array Unit 0
<R>
Serial output register 0 (SO0)
0
0
0
0 CKO03 CKO02 CKO01 CKO00 0
0
0
Peripheral enable register 0 (PER0)
SAU0EN
Serial clock select register 0 (SPS0)
PRS PRS PRS PRS PRS PRS 013 012 011 010 003 002
PRS 001
PRS 000
4
4
fCLK
Prescaler
fCLK/20 to fCLK/215
fCLK/20 to fCLK/215
0 SO03 SO02 SO01 SO00
Serial channel SE03 SE02 SE01 SE00 enable status
register 0 (SE0)
Serial channel SS03 SS02 SS01 SS00 start register 0
(SS0)
Serial channel ST03 ST02 ST01 ST00 stop register 0
(ST0)
Serial output SOE03 SOE02 SOE01 SOE00 enable register 0
(SOE0)
0
SOL02
0
SOL00
Serial output level register 0 (SOL0)
Selector
Selector
Noise filter enable register 0 (NFEN0)
SNFEN SNFEN 10 00
Serial standby control register 0 (SSC0)
SSEC0 SWC0
Channel 0
CK01
CK00
Serial data register 00 (SDR00)
(Clock division setting block)
(Buffer register block)
Serial clock I/O pin (when CSI00: SCK00) (when IIC00: SCL00)
Selector
ELCL output TO01 output
ISC4, ISC3 bits
ELCL input
Synchronous circuit
PFOE12
Edge detection
fSCK
fMCK
Selector Selector Clock controller
fTCLK
Shift register
Communication controller
PM10
Serial data input pin (when CSI00: SI00) (when IIC00: SDA00) (when UART0: RxD0)
Output latch (P10)
Selector
ELCL output
ISC2 bit
Synchronous circuit
Noise elimination enabled/
disabled
Edge/ level detection
SNFEN00
CKS00 CCS00 STS00 SIS00 MD002 MD001 MD000
Mode selection CSI00 or IIC00
or UART0 (for transmission)
State of communications
Serial mode register 00 (SMR00)
Output controller
Output latch
PFOE10 bit
(P11 or P12)
PM11 or PM12
ELCL input
Serial data output pin (when CSI00: SO00) (when IIC00: SDA00)
(when UART0: TxD0)
Interrupt controller
Serial flag clear trigger register 00 (SIR00) PECT OVCT 00 00 Clear
Error controller
Error information
Serial transfer end interrupt (when CSI00: INTCSI00) (when IIC00: INTIIC00)
(when UART0: INTST0)
When UART0
TXE RXE DAP CKP EOC PTC PTC DIR SLC SLC DLS DLS 00 00 00 00 00 001 000 00 001 000 001 000
Serial communication operation setting register 00 (SCR00)
TSF BFF PEF OVF 00 00 00 00
Serial status register 00 (SSR00)
Selector
<R>
Serial clock I/O pin (when CSI01: SCK01) (when IIC01: SCL01)
ELCL output TO01 output
Selector
ISC7, ISC6 bits
ELCL input
Selector
Serial data input pin
PM
(when CSI01: SI01)
(when IIC01: SDA01)
ELCL output
ISC5 bit
PFOE13 Output latch
Serial clock I/O pin (when CSI10: SCK10) (when IIC10: SCL10)
Channel 1
Synchronous circuit
Channel 2
ULBS0 bit
CK01
CK00
CK01
CK00
Selector
Serial data input pin (when CSI10: SI10) (when IIC10: SDA10) (when UART1: RxD1)
Synchronous circuit
Noise elimination enabled/
disabled
SNFEN10
Edge/level detection
When UART1
Edge/level detection
Selector
Serial clock I/O pin (when CSI11: SCK11) (when IIC11: SCL11)
Serial data input pin (when CSI11: SI11) (when IIC11: SDA11)
ULBS1 bit
Channel 3
CK01
CK00
Synchronous circuit
Selector
Edge/level detection
Communication controller
Mode selection CSI01 or IIC01
or UART0 (for reception)
Error controller
Communication controller
Mode selection CSI10 or IIC10
or UART1 (for transmission)
Communication controller
Mode selection CSI11 or IIC11
or UART1 (for reception)
Error controller
PFOE11 bit Output latch
PM
ELCL input
Serial data output pin (when CSI01: SO01) (when IIC01: SDA01)
Serial transfer end interrupt (when CSI01: INTCSI01) (when IIC01: INTIIC01) (when UART0: INTSR0)
Serial transfer error interrupt (INTSRE0)
Serial data output pin (when CSI10: SO10) (when IIC10: SDA10) (when UART1: TxD1)
Serial transfer end interrupt (when CSI10: INTCSI10) (when IIC10: INTIIC10) (when UART1: INTST1)
Serial data output pin (when CSI11: SO11) (when IIC11: SDA11)
Serial transfer end interrupt (when CSI11: INTCSI11) (when IIC11: INTIIC11) (when UART1: INTSR1)
Serial transfer error interrupt (INTSRE1)
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RL78/G23 Figure 15 - 2 shows the block diagram of serial array unit 1.
Figure 15 - 2 Block Diagram of Serial Array Unit 1
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Serial output register 1 (SO1)
0
0
0
0 CKO13 CKO12 CKO11 CKO10 0
0
0
Peripheral enable register 0 (PER0)
SAU1EN
PRS 113
Serial clock select register 1 (SPS1)
PRS PRS PRS PRS PRS PRS 112 111 110 103 102 101
PRS 100
4
4
fCLK
Prescaler
fCLK/20 to fCLK/215
fCLK/20 to fCLK/215
Selector
Selector
0 SO13 SO12 SO11 SO10
SE13 SE12 SE11 SE10 SS13 SS12 SS11 SS10 ST13 ST12 ST11 ST10 SOE13 SOE12 SOE11 SOE10
0 SOL12 0 SOL10
Serial channel enable status register 1 (SE1)
Serial channel start register 1 (SS1)
Serial channel stop register 1 (ST1)
Serial output enable register 1 (SOE1)
Serial output level register 1 (SOL1)
Noise filter enable register 0 (NFEN0)
SNFEN SNFEN 30 20
Serial standby control register 1 (SSC1)
SSEC1 SWC1
Selector Selector Clock controller
Serial clock I/O pin (when CSI20: SCK20) (when IIC20: SCL20)
Channel 0
CK11
(LIN-bus supported)
CK10
Synchronous
Edge
fSCK
circuit
detection
Serial data register 10 (SDR10)
(Clock division setting block)
(Buffer register block)
fMCK
fTCLK Shift register
Output controller
Output latch (P14 or P13)
PM14 or PM13
Serial data output pin (when CSI20: SO20) (when IIC20: SDA20) (when UART2:TXD2)
Output latch PM15 (P15)
Serial data input pin (when CSI20: SI20) (when IIC20: SDA20) (when UART2: RxD2)
Synchronous circuit
Noise elimination enabled/
disabled
Edge/ level detection
SNFEN20
CKS10 CCS10 STS10 SIS10 MD102 MD101 MD100
Communication controller
Mode selection CSI20 or IIC20
or UART2 (for transmission)
Interrupt controller
Serial flag clear trigger register 10 (SIR10)
PECT OVCT 10 10 Clear
Error controller
State of communications
Serial mode register 10 (SMR10)
Error information
When UART2
TXE RXE DAP CKP EOC PTC PTC DIR SLC SLC DLS DLS 10 10 10 10 10 101 100 10 101 100 101 100
Serial communication operation setting register 10 (SCR10)
TSF BFF PEF OVF 10 10 10 10
Serial status register 10 (SSR10)
Serial transfer end interrupt (when CSI20: INTCSI20) (when IIC20: INTIIC20) (when UART2: INTST2)
Selector
Serial clock I/O pin (when CSI21: SCK21) (when IIC21: SCL21)
Serial data input pin (when CSI21: SI21) (when IIC21: SDA21)
Serial clock I/O pin (when CSI30: SCK30) (when IIC30: SCL30) Serial data input pin (when CSI30: SI30) (when IIC30: SDA30) (when UART3: RxD3)
ULBS2 bit
CK11
CK10
Channel 1 (LIN-bus supported)
Synchronous circuit
Channel 2
CK11
CK10
Synchronous circuit
Noise elimination enabled/
disabled
SNFEN30
Edge/level detection
Selector
Serial clock I/O pin (when CSI31: SCK31) (when IIC31: SCL31)
Serial data input pin (when CSI31: SI31) (when IIC31: SDA31)
When UART3
ULBS3 bit
Channel 3
CK11
CK10
Synchronous circuit
Selector
Edge/level detection
Selector
Edge/level detection
Communication controller
Mode selection CSI21 or IIC21
or UART2 (for reception)
Error controller
Communication controller
Mode selection CSI30 or IIC30
or UART3 (for transmission)
Communication controller
Mode selection CSI31 or IIC31
or UART3 (for reception)
Error controller
Serial data output pin (when CSI21: SO21) (when IIC21: SDA21) Serial transfer end interrupt (when CSI21: INTCSI21) (when IIC21: INTIIC21) (when UART2: INTSR2) Serial transfer error interrupt (INTSRE2)
Serial data output pin (when CSI30: SO30) (when IIC30: SDA30) (when UART3: TxD3) Serial transfer end interrupt (when CSI30: INTCSI30) (when IIC30: INTIIC30) (when UART3: INTST3)
Serial data output pin (when CSI31: SO31) (when IIC31: SDA31) Serial transfer end interrupt (when CSI31: INTCSI31) (when IIC31: INTIIC31) (when UART3: INTSR3) Serial transfer error interrupt (INTSRE3)
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.2.1 Shift Register
This is a 9-bit register that converts parallel data into serial data or vice versa. In case of the UART communication of nine bits of data, nine bits (bits 0 to 8) are used Note 1. During reception, it converts data input to the serial pin into parallel data. When data is transmitted, the value set to this register is output as serial data from the serial output pin. The shift register cannot be directly manipulated by program. To read or write the shift register, use the lower 8 or 9 bits of serial data register mn (SDRmn).
8
7
6
5
4
3
2
1
0
Shift register
15.2.2 Lower 8 or 9 bits of the serial data register mn (SDRmn)
The SDRmn is the transmit/receive data register (16 bits) of channel n. Bits 8 to 0 (lower 9 bits)Note 1 or bits 7 to 0 (lower 8 bits) function as a transmit/receive buffer register, and bits 15 to 9 are used as a register that sets the division ratio of the operation clock (fMCK). When data is received, parallel data converted by the shift register is stored in the lower 8 or 9 bits. When data is to be transmitted, set transmit data to be transferred to the shift register to the lower 8 or 9 bits. The data stored in the lower 8 or 9 bits of this register is as follows, depending on the setting of bits 0 and 1 (DLSmn0, DLSmn1) of serial communication operation setting register mn (SCRmn), regardless of the output sequence of the data. · 7-bit data length (stored in bits 0 to 6 of the SDRmn register) · 8-bit data length (stored in bits 0 to 7 of the SDRmn register) · 9-bit data length (stored in bits 0 to 8 of the SDRmn register)Note 1
The SDRmn register can be read or written in 16-bit units. The lower 8 or 9 bits of the SDRmn register can be read or writtenNote 2 as the following SFR, depending on the communication mode. · CSIp communication ... SIOp (CSIp data register) · UARTq reception ... RxDq (UARTq receive data register) · UARTq transmission ... TxDq (UARTq transmit data register) · IICr communication ... SIOr (IICr data register) The value of each SDRmn register is 0000H following a reset.
Note 1. Note 2.
Only the following UARTs support the 9-bit data length. · 30- to 64-pin products: UART0 · 80- to 128-pin products: UART0 and UART2 When operation is stopped (SEmn = 0), do not rewrite SDRmn[7:0] by an 8-bit memory manipulation
instruction (SDRmn[15:9] are all cleared to 0).
Remark 1. After data is received, "0" is stored in bits 0 to 8 in bit portions that exceed the data length. Remark 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31)
q: UART number (q = 0 to 3), r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31)
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Figure 15 - 3 Format of Serial Data Register mn (SDRmn) (mn = 00, 01, 10, 11)
Address:
After reset: R/W:
FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01) FFF48H, FFF49H (SDR10)Note, FFF4AH, FFF4BH (SDR11)Note 0000H R/W
FFF11H (SDR00)
FFF10H (SDR00)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SDRmn
Shift register
8
7
6
5
4
3
2
1
0
Note
80- to 128-pin products
Remark For the function of the higher 7 bits of the SDRmn register, see 15.3 Registers to Control the Serial Array Unit.
Figure 15 - 4 Format of Serial Data Register mn (SDRmn) (mn = 02, 03, 10, 11, 12, 13)
Address:
After reset: R/W:
FFF44H, FFF45H (SDR02), FFF46H, FFF47H (SDR03), FFF48H, FFF49H (SDR10)Note 1, FFF4AH, FFF4BH (SDR11)Note 1 FFF14H, FFF15H (SDR12)Note 2, FFF16H, FFF17H (SDR13)Note 2
0000H
R/W
FFF45H (SDR02)
FFF44H (SDR02)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SDRmn
0
Shift register
8
7
6
5
4
3
2
1
0
Note 1. Note 2.
30- to 64-pin products: 80- to 128-pin products
Caution Be sure to clear bit 8 to 0.
Remark For the function of the higher 7 bits of the SDRmn register, see 15.3 Registers to Control the Serial Array Unit.
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.3
Registers to Control the Serial Array Unit
The following registers are used to control the serial array unit.
· Peripheral enable register 0 (PER0) · Peripheral reset control register 0 (PRR0) · Serial clock select register m (SPSm) · Serial mode register mn (SMRmn) · Serial communication operation setting register mn (SCRmn) · Serial data register mn (SDRmn) · Serial flag clear trigger register mn (SIRmn) · Serial status register mn (SSRmn) · Serial channel start register m (SSm) · Serial channel stop register m (STm) · Serial channel enable status register m (SEm) · Serial output enable register m (SOEm) · Serial output register m (SOm) · Serial output level register m (SOLm) · Serial standby control register m (SSCm) · Input switch control register (ISC) · Noise filter enable register 0 (NFEN0) · Port input mode registers (PIMxx) · Port output mode registers (POMxx) · Port mode control A registers (PMCAxx) · Port mode control T registers (PMCTxx) · Port mode control E registers (PMCEx) · Port function output enable registers (PFOEx) · Port mode registers (PMxx) · Port registers (Pxx) · UART loopback select register (ULBS)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.3.1 Peripheral enable register 0 (PER0)
The PER0 register is used to enable or disable the supply of a clock signal to various on-chip peripheral modules. Clock supply to an on-chip peripheral module that is not to be used can be stopped to decrease power consumption and noise. If serial array unit 0 is to be used, be sure to set bit 2 (SAU0EN) of this register to 1. If serial array unit 1 is to be used, be sure to set bit 3 (SAU1EN) of this register to 1. The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of the PER0 register is 00H following a reset.
Figure 15 - 5 Format of Peripheral Enable Register 0 (PER0)
Address: After reset: R/W:
F00F0H 00H R/W
Symbol
<7>
PER0 RTCWEN
<6> IICA1EN
<5> ADCEN
<4> IICA0EN
<3> SAU1EN
<2> SAU0EN
<1>
TAU1EN
Note
<0> TAU0EN
SAUmEN
Control of supply of an input clock to serial array unit m
0
Stops supply of an input clock.
· The SFRs used by serial array unit m cannot be written.
· When an SFR used by serial array unit m is read, the value returned is 00H or 0000H.
1
Enables supply of an input clock.
· The SFRs used by serial array unit m can be read and written.
Note
This bit is only present in products with 80 to 128 pins.
Caution 1. When setting serial array unit m, make sure that the setting of the SAUmEN bit is 1 before setting the following registers. If SAUmEN = 0, writing to the registers which control serial array unit m is ignored (except for the input switch control register (ISC), noise filter enable register 0 (NFEN0), port input mode registers 0, 1, 4, 5, 8, 14 (PIM0, PIM1, PIM4, PIM5, PIM8, PIM14), port output mode registers 0, 1, 4, 5, 7 to 9, 14 (POM0, POM1, POM4, POM5, POM7 to POM9, POM14), port mode control A registers 0, 3, 14 (PMCA0, PMCA3, PMCA14), port mode control T registers 0, 3 (PMCT0, PMCT3), port mode control E register 0 (PMCE0), port mode registers 0, 1, 3 to 5, 7 to 9, 14 (PM0, PM1, PM3 to PM5, PM7 to PM9, PM14), and port registers 0, 1, 3 to 5, 7 to 9, 14 (P0, P1, P3 to P5, P7 to P9, P14)). · Port function output enable register 1 (PFOE1) · Serial clock select register m (SPSm) · Serial mode register mn (SMRmn) · Serial communication operation setting register mn (SCRmn) · Serial data register mn (SDRmn) · Serial flag clear trigger register mn (SIRmn) · Serial status register mn (SSRmn) · Serial channel start register m (SSm) · Serial channel stop register m (STm) · Serial channel enable status register m (SEm) · Serial output enable register m (SOEm) · Serial output level register m (SOLm) · Serial output register m (SOm) · Serial standby control register m (SSCm)
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Caution 2. Be sure to clear the following bits to 0. Bits 6 and 1 in the 30-, 32-, 36-, 40-, 44-, 48-, 52-, and 64-pin products
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.3.2 Peripheral reset control register 0 (PRR0)
The PRR0 register is used to control resetting of the on-chip peripheral modules. Each bit in this register controls resetting and release from the reset state of the corresponding on-chip peripheral module. To place serial array unit 0 in the reset state, be sure to set bit 2 (SAU0RES) of this register to 1. To place serial array unit 1 in the reset state, be sure to set bit 3 (SAU1RES) of this register to 1. The PRR0 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of the PRR0 register is 00H following a reset.
Figure 15 - 6 Format of Peripheral Reset Control Register 0 (PRR0)
Address: After reset: R/W:
F00F1H 00H R/W
Symbol
7
PRR0
0
<6>
<5>
<4>
<3>
<2>
<1>
<0>
IICA1RES ADCRES IICA0RES SAU1RES SAU0RES TAU1RES TAU0RES
SAUmRES
Control resetting of serial array unit m
0
Serial array unit m is released from the reset state.
1
Serial array unit m is in the reset state.
· The SFRs for use with serial array unit m are initialized.
Caution Be sure to set bit 7 to 0.
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15.3.3 Serial clock select register m (SPSm)
The SPSm is a 16-bit register that is used to select two types of operation clocks (CKm0, CKm1) that are commonly supplied to each channel. CKm1 is selected by bits 7 to 4 of the SPSm register, and CKm0 is selected by bits 3 to 0. Rewriting the SPSm register is prohibited when the register is in operation (when SEmn = 1). The SPSm register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the SPSm register can be set with an 8-bit memory manipulation instruction with SPSmL. The value of each SPSm register is 0000H following a reset.
Figure 15 - 7 Format of Serial Clock Select Register m (SPSm)
Address: After reset: R/W:
F0126H, F0127H (SPS0), F0166H, F0167H (SPS1)Note 0000H R/W
Symbol
15
14
13
12
11
10
9
8
SPSm
0
0
0
0
0
0
0
0
7 PRSm13
6 PRSm12
5 PRSm11
4 PRSm10
3 PRSm03
2 PRSm02
1 PRSm01
0 PRSm00
PRS PRS PRS PRS mk3 mk2 mk1 mk0
0
0
0
0 fCLK
0
0
0
1 fCLK/2
0
0
1
0 fCLK/22
0
0
1
1 fCLK/23
0
1
0
0 fCLK/24
0
1
0
1 fCLK/25
0
1
1
0 fCLK/26
0
1
1
1 fCLK/27
1
0
0
0 fCLK/28
1
0
0
1 fCLK/29
1
0
1
0 fCLK/210
1
0
1
1 fCLK/211
1
1
0
0 fCLK/212
1
1
0
1 fCLK/213
1
1
1
0 fCLK/214
1
1
1
1 fCLK/215
Selection of operation clock (CKmk)Note
fCLK = 2 MHz 2 MHz
fCLK = 5 MHz 5 MHz
fCLK = 10 MHz 10 MHz
fCLK = 20 MHz 20 MHz
1 MHz
2.5 MHz 5 MHz
10 MHz
500 kHz 1.25 MHz 2.5 MHz 5 MHz
250 kHz 625 kHz 1.25 MHz 2.5 MHz
125 kHz 313 kHz 625 kHz 1.25 MHz
62.5 kHz 156 kHz 313 kHz 625 kHz
31.3 kHz 78.1 kHz 156 kHz 313 kHz
15.6 kHz 39.1 kHz 78.1 kHz 156 kHz
7.81 kHz 19.5 kHz 39.1 kHz 78.1 kHz
3.91 kHz 9.77 kHz 19.5 kHz 39.1 kHz
1.95 kHz 4.88 kHz 9.77 kHz 19.5 kHz
977 Hz
2.44 kHz 4.88 kHz 9.77 kHz
488 Hz
1.22 kHz 2.44 kHz 4.88 kHz
244 Hz
610 Hz
1.22 kHz 2.44 kHz
122 Hz
305 Hz
610 Hz
1.22 kHz
61 Hz
153 Hz
305 Hz
610 Hz
fCLK = 32 MHz 32 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.3 kHz 15.6 kHz 7.81 kHz 3.91 kHz 1.95 kHz 977 Hz
Note
When changing the clock selected for fCLK (by changing the system clock control register (CKC) value), do so
after having stopped (serial channel stop register m (STm) = 000FH) the operation of the serial array unit
(SAU).
Caution Be sure to clear bits 15 to 8 to 0.
Remark 1. fCLK: CPU/peripheral hardware clock frequency
Remark 2. m: Unit number (m = 0, 1)
Remark 3. k = 0, 1
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15.3.4 Serial mode register mn (SMRmn)
The SMRmn register is used to set an operation mode of channel n. It is also used to select an operation clock (fMCK), specify whether the serial clock (fSCK) may be input or not, set a start trigger, the operating mode (as SPI or CSI, UART, or simplified I2C), and an interrupt source. This register is also used to invert the level of the receive data only in the UART mode. Rewriting the SMRmn register is prohibited when the register is in operation (when SEmn = 1). However, the MDmn0 bit can be rewritten during operation. The SMRmn register can be set by a 16-bit memory manipulation instruction. The value of each SMRmn register is 0020H following a reset.
Figure 15 - 8 Format of Serial Mode Register mn (SMRmn) (1/2)
Address:
After reset: R/W:
F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03), F0150H, F0151H (SMR10) to F0156H, F0157H (SMR13)Note 1
0020H
R/W
Symbol
15
14
13
12
11
10
SMRmn CKSmn
CCSmn
0
0
0
0
9
8
0
STSmnNote 2
7
6
5
4
3
2
1
0
0
SISmn0
Note 2
1
0
0
MDmn2 MDmn1 MDmn0
CKSmn
Selection of operation clock (fMCK) of channel n
0
Operation clock CKm0 set by the SPSm register
1
Operation clock CKm1 set by the SPSm register
Operation clock (fMCK) is used by the edge detector. In addition, depending on the setting of the CCSmn bit and the higher 7 bits of the SDRmn register, a transfer clock (fTCLK) is generated.
CCSmn
Selection of transfer clock (fTCLK) of channel n
0
Divided operation clock fMCK specified by the CKSmn bit
1
Clock input fSCK from the SCKp pin (slave transfer in SPI or CSI mode)
Transfer clock fTCLK is used for the shift register, communication controller, output controller, interrupt controller, and error controller. When CCSmn = 0, the division ratio of operation clock (fMCK) is set by the higher 7 bits of the SDRmn register.
STSmn
Note 2
Selection of start trigger source
0
Only software trigger is valid (selected for SPI or CSI, UART transmission, and simplified I2C).
1
Valid edge of the RxDq pin (selected for UART reception)
Transfer is started when the above source is satisfied after 1 is set to the SSm register.
Note 1. Note 2.
SMR00 to SMR03, SMR10, SMR11: All products SMR12, SMR13: 80- to 128-pin products The SMR01, SMR03, SMR11, and SMR13 registers only
Caution Be sure to clear bits 13 to 9, 7, 4, and 3 (or bits 13 to 6, 4, and 3 for the SMR00, SMR02, SMR10, or SMR12 register) to "0". Be sure to set bit 5 to 1.
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Figure 15 - 8 Format of Serial Mode Register mn (SMRmn) (2/2)
Address:
After reset: R/W:
F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03), F0150H, F0151H (SMR10) to F0156H, F0157H (SMR13)Note 1
0020H
R/W
Symbol
15
14
13
12
11
10
SMRmn CKSmn
CCSmn
0
0
0
0
9
8
0
STSmnNote 2
7
6
5
4
3
2
1
0
SISmn0
0
Note 2
1
0
0
MDmn2 MDmn1 MDmn0
SISmn0
Note 2
Controls inversion of level of receive data of channel n in UART mode
0
Falling edge is detected as the start bit.
The input communication data is captured as is.
1
Rising edge is detected as the start bit.
The input communication data is inverted and captured.
MDmn2 0 0 1 1
MDmn1 0 1 0 1
Setting of operation mode of channel n SPI (CSI) mode UART mode Simplified I2C mode Setting prohibited
MDmn0
Note 2
Selection of interrupt source of channel n
0
Transfer end interrupt
1
Buffer empty interrupt
(Occurs when data is transferred from the SDRmn register to the shift register.)
For continuous transmission, set this bit to 1 and write the next transmit data when SDRmn data has run out.
Note 1. Note 2.
SMR00 to SMR03, SMR10, SMR11: All products SMR12, SMR13: 80- to 128-pin products The SMR01, SMR03, SMR11, and SMR13 registers only.
Caution Be sure to clear bits 13 to 9, 7, 4, and 3 (or bits 13 to 6, 4, and 3 for the SMR00, SMR02, SMR10, or SMR12 register) to "0". Be sure to set bit 5 to 1.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), q: UART number (q = 0 to 3), r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31)
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15.3.5 Serial communication operation setting register mn (SCRmn)
The SCRmn is a communication operation setting register of channel n. It is used to set a data transmission/reception mode, phase of data and clock, whether an error signal is to be masked or not, parity bit, start bit, stop bit, and data length. Rewriting the SCRmn register is prohibited when the register is in operation (when SEmn = 1). The SCRmn register can be set by a 16-bit memory manipulation instruction. The value of each SCRmn register is 0087H following a reset.
Figure 15 - 9 Format of Serial Communication Operation Setting Register mn (SCRmn) (1/2)
Address:
After reset: R/W:
F0118H, F0119H (SCR00) to F011EH, F011FH (SCR03), F0158H, F0159H (SCR10) to F015EH, F015FH (SCR13)Note 1
0087H
R/W
Symbol
15
14
13
12
11
10
9
8
SCRmn TXEmn
RXEmn
DAPmn
CKPmn
0
EOCmn PTCmn1 PTCmn0
7 DIRmn
6
5
4
3
SLCmn1
0
Note 2
SLCmn0
0
2
1
0
DLSmn1
1
Note 3
DLSmn0
TXEmn 0 0 1 1
RXEmn 0 1 0 1
Setting of operation mode of channel n Disable communication. Reception only Transmission only Transmission/reception
DAPmn 0
CKPmn 0
Selection of data and clock phase in SPI (CSI) mode
SCKp SOp SIp input timing
D7 D6 D5 D4 D3 D2 D1 D0
0
1
SCKp SOp SIp input timing
D 7 D6 D5 D4 D3 D2 D1 D0
1
0
SCKp
SOp
D7 D6 D5 D4 D3 D2 D 1 D0
SIp input timing
1
1
SCKp
SOp
D7 D6 D5 D4 D3 D2 D1 D0
SIp input timing
Be sure to set DAPmn, CKPmn = 0, 0 in the UART mode and simplified I2C mode.
Type 1 2 3 4
EOCmn
Mask control of error interrupt signal (INTSREx (x = 0 to 3))
0
Disables generation of error interrupt INTSREx (INTSRx is generated).
1
Enables generation of error interrupt INTSREx (INTSRx is not generated if an error occurs).
Set EOCmn = 0 in the SPI (CSI) mode, simplified I2C mode, and during UART transmissionNote 4.
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Note 1.
Note 2. Note 3.
Note 4.
SCR00 to SCR03, SCR10, SCR11: All products SCR12, SCR13: 80- to 128-pin products The SCR00, SCR02, SCR10, and SCR12 registers only. Only provided for the SCR00 and SCR01 registers and the SCR10 and SCR11 registers of 80- to 128-pin products. This bit is fixed to 1 for the other registers. When using CSImn not with EOCmn = 0, error interrupt INTSREn may be generated.
Caution Be sure to clear bits 11, 6, and 3 to "0" (Also clear bit 5 of the SCR01, SCR03, SCR11, or SCR13 register to 0). Be sure to set bit 2 to 1.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31)
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Figure 15 - 9 Format of Serial Communication Operation Setting Register mn (SCRmn) (2/2)
Address:
After reset: R/W:
F0118H, F0119H (SCR00) to F011EH, F011FH (SCR03), F0158H, F0159H (SCR10) to F015EH, F015FH (SCR13)Note 1
0087H
R/W
Symbol
15
14
13
12
11
10
9
8
SCRmn TXEmn
RXEmn
DAPmn
CKPmn
0
EOCmn PTCmn1 PTCmn0
7 DIRmn
6
5
4
3
SLCmn1
0
Note 2
SLCmn0
0
2
1
0
DLSmn1
1
Note 3
DLSmn0
PTCmn1 PTCmn0
Setting of parity bit in UART mode
Transmission
Reception
0
0
Does not output the parity bit.
Receives without parity
0
1
Outputs 0 parityNote 4.
No parity judgment
1
0
Outputs even parity.
Judged as even parity.
1
1
Outputs odd parity.
Judges as odd parity.
Be sure to set PTCmn1, PTCmn0 = 0, 0 in the SPI (CSI) mode and simplified I2C mode.
DIRmn
Selection of data transfer sequence in SPI (CSI) and UART modes
0
Inputs/outputs data with MSB first.
1
Inputs/outputs data with LSB first.
Be sure to clear DIRmn = 0 in the simplified I2C mode.
SLCmn1
Note 2
SLCmn0
Setting of stop bit in UART mode
0
0
No stop bit
0
1
Stop bit length = 1 bit
1
0
Stop bit length = 2 bits (mn = 00, 02, 10, 12 only)
1
1
Setting prohibited
When the transfer end interrupt is selected, the interrupt is generated when all stop bits have been completely transferred.
Set 1 bit (SLCmn1, SLCmn0 = 0, 1) during UART reception and in the simplified I2C mode. Set no stop bit (SLCmn1, SLCmn0 = 0, 0) in the SPI (CSI) mode. Set 1 bit (SLCmn1, SLCmn0 = 0, 1) or 2 bits (SLCmn1, SLCmn0 = 1, 0) during UART transmission.
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
DLSmn1
Note 3
DLSmn0
Setting of data length in SPI (CSI) and UART modes
0
1
9-bit data length (stored in bits 0 to 8 of the SDRmn register)
(settable in UART mode only)
1
0
7-bit data length (stored in bits 0 to 6 of the SDRmn register)
1
1
8-bit data length (stored in bits 0 to 7 of the SDRmn register)
Other than above Setting prohibited
Be sure to set DLSmn1, DLSmn0 = 1, 1 in the simplified I2C mode.
Note 1.
Note 2. Note 3.
Note 4.
SCR00 to SCR03, SCR10, SCR11: All products SCR12, SCR13: 80- to 128-pin products The SCR00, SCR02, SCR10, and SCR12 registers only. Only provided for the SCR00 and SCR01 registers and the SCR10 and SCR11 registers of 80- to 128-pin products. This bit is fixed to 1 for the other registers. 0 is always added regardless of the data contents.
Caution Be sure to clear bits 11, 6, and 3 to "0" (Also clear bit 5 of the SCR01, SCR03, SCR11, or SCR13 register to 0). Be sure to set bit 2 to 1.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31)
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.3.6 Serial data register mn (SDRmn)
The SDRmn is the transmit/receive data register (16 bits) of channel n. Bits 8 to 0 (lower 9 bits) of SDR00, SDR01, SDR10Note 1, and SDR11Note 1 or bits 7 to 0 (lower 8 bits) of SDR02, SDR03, SDR10Note 2, SDR11Note 2, SDR12, and SDR13 function as a transmit/receive buffer register, and bits 15 to 9 (higher 7 bits) are used as a register that sets the division ratio of the operation clock (fMCK). If the CCSmn bit of serial mode register mn (SMRmn) is cleared to 0, the clock set by dividing the operation clock by bits 15 to 9 (higher 7 bits) of the SDRmn register is used as the transfer clock. If the CCSmn bit of serial mode register mn (SMRmn) is set to 1, set bits 15 to 9 (upper 7 bits) of SDR00, SDR01, SDR10Note 1, and SDR11Note 1 to 0000000B. The input clock fSCK (slave transfer in SPI or CSI mode) from the SCKp pin is used as the transfer clock. The lower 8 or 9 bits of the SDRmn register function as a transmit/receive buffer register. During reception, the parallel data converted by the shift register is stored in the lower 8 or 9 bits, and during transmission, the data to be transmitted to the shift register is set to the lower 8 or 9 bits. The SDRmn register can be read or written in 16-bit units. However, the higher 7 bits can only be written or read when the operation is stopped (SEmn = 0). During operation (SEmn = 1), a value is written only to the lower 8 or 9 bits of the SDRmn register. When the SDRmn register is read during operation, the higher 7 bits are always read as 0. The value of each SDRmn register is 0000H following a reset.
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Figure 15 - 10 Format of Serial Data Register mn (SDRmn)
Address:
After reset: R/W:
FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01) FFF48H, FFF49H (SDR10)Note 1, FFF4AH, FFF4BH (SDR11)Note 1 0000H R/W
FFF11H (SDR00)
FFF10H (SDR00)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SDRmn
Address:
After reset: R/W:
FFF44H, FFF45H (SDR02), FFF46H, FFF47H (SDR03) FFF48H, FFF49H (SDR10)Note 2, FFF4AH, FFF4BH (SDR11)Note 2 FFF14H, FFF15H (SDR12)Note 1, FFF16H, FFF17H (SDR13)Note 1
0000H
R/W
FFF45H (SDR02)
FFF44H (SDR02)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SDRmn
0
SDRmn[15:9]
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
1
1
Transfer clock setting by dividing the operation clock fMCK/2 fMCK/4 fMCK/6 fMCK/8
1
1
1
1
1
1
0
1
1
1
1
1
1
1
fMCK/254 fMCK/256
Note 1. Note 2.
80- to 128-pin products 30- to 64-pin products:
Caution 1. Be sure to clear bit 8 of the SDR02, SDR03, SDR12, SDR13, and SDR10 and SDR11 of 30- to 64-pin products to "0".
Caution 2. Setting SDRmn[15:9] to 0000000B or 0000001B is prohibited when UART is used. Caution 3. Setting SDRmn[15:9] to 0000000B is prohibited when simplified I2C is used. Set SDRmn[15:9] to
0000001B or greater. Caution 4. When operation is stopped (SEmn = 0), do not rewrite SDRmn[7:0] by an 8-bit memory manipulation
instruction (SDRmn[15:9] are all cleared to 0).
Remark 1. For the function of the lower 8 or 9 bits of the SDRmn register, see 15.2 Configuration of Serial Array Unit. Remark 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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15.3.7 Serial flag clear trigger register mn (SIRmn)
The SIRmn is a trigger register that is used to clear each error flag of channel n. When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn, PEFmn, OVFmn) of serial status register mn is cleared to 0. Because the SIRmn is a trigger register, it is cleared immediately when the corresponding bit of the SSRmn register is cleared. The SIRmn register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the SIRmn register can be set with an 8-bit memory manipulation instruction with SIRmnL. The value of each SIRmn register is 0000H following a reset.
Figure 15 - 11 Format of Serial Flag Clear Trigger Register mn (SIRmn)
Address:
After reset: R/W:
F0108H, F0109H (SIR00) to F010EH, F010FH (SIR03), F0148H, F0149H (SIR10) to F014EH, F014FH (SIR13)Note 1
0000H
R/W
Symbol
15
14
13
12
11
10
9
8
SIRmn
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
FECTmn
Note 2
PECTmn
OVCTmn
FECTmn
Clear trigger of framing error flag of channel n
0
Not cleared
1
Clears the FEFmn bit of the SSRmn register to 0.
PECTmn
Clear trigger of parity error flag of channel n
0
Not cleared
1
Clears the PEFmn bit of the SSRmn register to 0.
OVCTmn
Clear trigger of overrun error flag of channel n
0
Not cleared
1
Clears the OVFmn bit of the SSRmn register to 0.
Note 1. Note 2.
SIR00 to SIR03, SIR10, SIR11: All products SIR12, SIR13: 80- to 128-pin products The SIR01, SIR03, SIR11, and SIR13 registers only.
Caution Be sure to clear bits 15 to 3 (or bits 15 to 2 for the SIR00, SIR02, SIR10, or SIR12 register) to "0".
Remark 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3) Remark 2. When the SIRmn register is read, 0000H is always read.
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.3.8 Serial status register mn (SSRmn)
The SSRmn register indicates the state of communications and occurrence of errors for channel n. The errors indicated by this register are a framing error, parity error, and overrun error. The SSRmn register can be read by a 16-bit memory manipulation instruction. The lower 8 bits of the SSRmn register can be read with an 8-bit memory manipulation instruction with SSRmnL. The value of each SSRmn register is 0000H following a reset.
Figure 15 - 12 Format of Serial Status Register mn (SSRmn) (1/2)
Address:
After reset: R/W:
F0100H, F0101H (SSR00) to F0106H, F0107H (SSR03), F0140H, F0141H (SSR10) to F0146H, F0147H (SSR13)Note 1
0000H
R
Symbol
15
14
13
12
11
10
9
8
SSRmn
0
0
0
0
0
0
0
0
7
6
5
4
0
TSFmn
BFFmn
0
3
2
1
0
0
FEFmnNote 2 PEFmn
OVFmn
TSFmn
Flag indicating the state of communications for channel n
0
Communication is stopped or suspended.
1
Communication is in progress.
<Clear conditions>
· The STmn bit of the STm register is set to 1 (communication is stopped) or the SSmn bit of the SSm
register is set to 1 (communication is suspended).
· Communication ends.
<Set condition>
· Communication starts.
BFFmn
Flag indicating the state of the buffer register for channel n
0
Valid data is not stored in the SDRmn register.
1
Valid data is stored in the SDRmn register.
<Clear conditions> · Transferring transmit data from the SDRmn register to the shift register ends during transmission.
· Reading receive data from the SDRmn register ends during reception. · The STmn bit of the STm register is set to 1 (communication is stopped) or the SSmn bit of the SSm
register is set to 1 (communication is enabled). <Set condition>
· Transmit data is written to the SDRmn register while the TXEmn bit of the SCRmn register is set to 1 (transmission or transmission/reception mode in each communication mode).
· Receive data is stored in the SDRmn register while the RXEmn bit of the SCRmn register is set to 1
(reception or transmission/reception mode in each communication mode).
· A reception error occurs.
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Note 1. Note 2.
SSR00 to SSR03, SSR10, SSR11: All products SSR12, SSR13: 80- to 128-pin products The SSR01, SSR03, SSR11, and SSR13 registers only.
Caution When the SPI (CSI) is performing reception operations in the SNOOZE mode (SWCm = 1), the BFFmn flag will not change.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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Figure 15 - 12 Format of Serial Status Register mn (SSRmn) (2/2)
Address:
After reset: R/W:
F0100H, F0101H (SSR00) to F0106H, F0107H (SSR03), F0140H, F0141H (SSR10) to F0146H, F0147H (SSR13)Note 1
0000H
R
Symbol
15
14
13
12
11
10
9
8
SSRmn
0
0
0
0
0
0
0
0
7
6
5
4
0
TSFmn
BFFmn
0
3
2
1
0
0
FEFmnNote 2 PEFmn
OVFmn
FEFmn
Note 2
Framing error detection flag of channel n
0
No error occurs.
1
An error occurs (during UART reception).
<Clear conditions> · 1 is written to the FECTmn bit of the SIRmn register. <Set condition> · A stop bit is not detected when UART reception ends.
PEFmn
Parity/ACK error detection flag of channel n
0
No error occurs.
1
Parity error occurs (during UART reception) or ACK is not detected (during I2C transmission).
<Clear conditions> · 1 is written to the PECTmn bit of the SIRmn register. <Set condition> · The parity of the transmit data and the parity bit do not match when UART reception ends (parity error). · No ACK signal is returned from the slave at the ACK reception timing during I2C transmission (ACK is not
detected).
OVFmn
Overrun error detection flag of channel n
0
No error occurs.
1
An error occurs
<Clear conditions>
· 1 is written to the OVCTmn bit of the SIRmn register.
<Set condition>
· Even though receive data is stored in the SDRmn register, that data is not read and transmit data or the
next receive data is written while the RXEmn bit of the SCRmn register is set to 1 (reception or
transmission/reception mode in each communication mode).
· Transmit data is not ready for slave transmission or transmission/reception in SPI (CSI) mode.
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Note 1. Note 2.
SSR00 to SSR03, SSR10, SSR11: All products SSR12, SSR13: 80- to 128-pin products The SSR01, SSR03, SSR11, and SSR13 registers only.
Caution 1. If data is written to the SDRmn register when BFFmn = 1, the transmit/receive data stored in the register is discarded and an overrun error (OVFmn = 1) is detected.
Caution 2. When the SPI (CSI) is performing reception operations in the SNOOZE mode (SWCm = 1), the OVFmn flag will not change.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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15.3.9 Serial channel start register m (SSm)
The SSm is a trigger register that is used to enable starting communication/count by each channel. When 1 is written to a bit (SSmn) of this register, the corresponding bit (SEmn) of serial channel enable status register m (SEm) is set to 1 (operation is enabled). Because the SSmn bit is a trigger bit, it is cleared immediately when SEmn = 1. The SSm register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the SSm register can be set with an 1-bit or 8-bit memory manipulation instruction with SSmL. The value of each SSm register is 0000H following a reset.
Figure 15 - 13 Format of Serial Channel Start Register m (SSm)
Address: After reset: R/W:
F0122H, F0123H (SS0) 0000H R/W
Symbol
15
14
13
SS0
0
0
0
7
6
5
0
0
0
Address: After reset: R/W:
F0162H, F0163H (SS1)Note 0000H R/W
12
11
10
9
8
0
0
0
0
0
4
3
2
1
0
0
SS03
SS02
SS01
SS00
Symbol
15
14
13
12
11
10
9
8
SS1
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
SS13
SS12
SS11
SS10
SSmn
Operation start trigger of channel n
0
No trigger operation
1
Set the SEmn bit to 1 to place the channel in the communications waiting state.Note
Note
Setting an SSmn bit to 1 during communications stops communications through channel n and places the channel in the waiting state. At this time, the values of the control registers and shift register, the states of the SCKmn and SOmn pins, and the values of the FEFmn, PEFmn, and OVFmn flags are retained.
Caution 1. Be sure to clear bits 15 to 4 of the SS0 register, bits 15 to 2 of the SS1 register for 30- to 64-pin products and bits 15 to 4 of the SS1 register for 80- to 128-pin products to "0".
Caution 2. For the UART reception, set the RXEmn bit of SCRmn register to 1, and then be sure to set SSmn to 1 after at least 4 fMCK clock cycles have elapsed.
Remark 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3) Remark 2. When the SSm register is read, 0000H is always read.
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15.3.10 Serial channel stop register m (STm)
The STm is a trigger register that is used to enable stopping communication/count by each channel. When 1 is written to a bit (STmn) of this register, the corresponding bit (SEmn) of serial channel enable status register m (SEm) is cleared to 0 (operation is stopped). Because the STmn bit is a trigger bit, it is cleared immediately when SEmn = 0. The STm register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the STm register can be set with a 1-bit or 8-bit memory manipulation instruction with STmL. The value of each STm register is 0000H following a reset.
Figure 15 - 14 Format of Serial Channel Stop Register m (STm)
Address: After reset: R/W:
F0124H, F0125H (ST0) 0000H R/W
Symbol
15
14
13
12
11
10
9
8
ST0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
ST03
ST02
ST01
ST00
Address: After reset: R/W:
F0164H, F0165H (ST1)Note 0000H R/W
Symbol
15
14
13
12
11
10
9
8
ST1
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
ST13
ST12
ST11
ST10
STmn
Operation stop trigger of channel n
0
No trigger operation
1
Clears the SEmn bit to 0 and stops the communication operationNote.
Note
The values of the control registers and shift register, the states of the SCKmn and SOmn pins, and the values of the FEFmn, PEFmn, and OVFmn flags are retained.
Caution Be sure to clear bits 15 to 4 of the ST0 register, bits 15 to 2 of the ST1 register for 30- to 64-pin products and bits 15 to 4 of the ST1 register for 80- to 128-pin products to "0".
Remark 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3) Remark 2. When the STm register is read, 0000H is always read.
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15.3.11 Serial channel enable status register m (SEm)
The SEm register indicates whether data transmission/reception operation of each channel is enabled or stopped. When 1 is written to a bit of serial channel start register m (SSm), the corresponding bit of this register is set to 1. When 1 is written to a bit of serial channel stop register m (STm), the corresponding bit is cleared to 0. For channel n whose operation is enabled, the value of the CKOmn bit of serial output register m (SOm) to be described later cannot be rewritten by software, and a value reflected by a communication operation is output from the serial clock pin. For channel n whose operation is stopped, the value of the CKOmn bit of the SOm register can be set by software and is output from the serial clock pin. In this way, any waveform, such as that of a start condition/stop condition, can be created by software. The SEm register can be read by a 16-bit memory manipulation instruction. The lower 8 bits of the SEm register can be read with a 1-bit or 8-bit memory manipulation instruction with SEmL. The value of each SEm register is 0000H following a reset.
Figure 15 - 15 Format of Serial Channel Enable Status Register m (SEm)
Address: After reset: R/W:
F0120H, F0121H (SE0) 0000H R
Symbol
15
14
13
12
11
10
9
8
SE0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
SE03
SE02
SE01
SE00
Address: After reset: R/W:
F0160H, F0161H (SE1) 0000H R
Symbol
15
14
13
12
11
10
9
8
SE1
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
SE13
SE12
SE11
SE10
SEmn
Indication of whether operation of channel n is enabled or stopped.
0
Operation stops
1
Operation is enabled.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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15.3.12 Serial output enable register m (SOEm)
The SOEm register is used to enable or stop output of the serial communication operation of each channel. For channel n whose serial output is enabled, the value of the SOmn bit of serial output register m (SOm) to be described later cannot be rewritten by software, and a value reflected by a communication operation is output from the serial data output pin. For channel n, whose serial output is stopped, the SOmn bit value of the SOm register can be set by software, and that value can be output from the serial data output pin. In this way, any waveform, such as that of a start condition/stop condition, can be created by software. The SOEm register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the SOEm register can be set with a 1-bit or 8-bit memory manipulation instruction with SOEmL. The value of each SOEm register is 0000H following a reset.
Figure 15 - 16 Format of Serial Output Enable Register m (SOEm)
Address: After reset: R/W:
F012AH, F012BH (SOE0) 0000H R/W
Symbol
15
14
13
12
11
10
9
8
SOE0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
SOE03
SOE02
SOE01
SOE00
Address: After reset: R/W:
F016AH, F016BH (SOE1) 0000H R/W
Symbol
15
14
13
12
11
10
9
8
SOE1
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
SOE13
SOE12
SOE11
SOE10
SOEmn
Serial output enable/stop of channel n
0
Stops output by serial communication operation.
1
Enables output by serial communication operation.
Caution Be sure to clear bits 15 to 4 of the SOE0 register, bits 15 to 2 of the SOE1 register for 30- to 64-pin products and bits 15 to 4 of the SOE1 register for 80- to 128-pin products to "0".
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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15.3.13 Serial output register m (SOm)
The SOm is a buffer register for serial output of each channel. The value of the SOmn bit of this register is output from the serial data output pin of channel n. The value of the CKOmn bit of this register is output from the serial clock output pin of channel n. The SOmn bit of this register can be rewritten by software only when serial output is disabled (SOEmn = 0). When serial output is enabled (SOEmn = 1), rewriting by software is ignored, and the value of the register can be changed only by a serial communication operation. The CKOmn bit of this register can be rewritten by software only when the channel operation is stopped (SEmn = 0). While channel operation is enabled (SEmn = 1), rewriting by software is ignored, and the value of the CKOmn bit can be changed only by a serial communication operation. To use the pin for serial interface as a port function pin, set the corresponding CKOmn and SOmn bits to "1". The SOm register can be set by a 16-bit memory manipulation instruction. The value of each SOm register is 0F0FH following a reset.
Figure 15 - 17 Format of Serial Output Register m (SOm)
Address: After reset: R/W:
F0128H, F0129H (SO0) 0F0FH R/W
Symbol
15
14
13
12
11
10
9
8
SO0
0
0
0
0
CKO03
CKO02
CKO01
CKO00
7
6
5
4
3
2
1
0
0
0
0
0
SO03
SO02
SO01
SO00
Address: After reset: R/W:
F0168H, F0169H (SO1) 0F0FHNote R/W
Symbol
15
14
13
SO1
0
0
0
7
6
5
0
0
0
12
11
10
9
8
0
CKO13
CKO12
CKO11
CKO10
4
3
2
1
0
0
SO13
SO12
SO11
SO10
CKOmn 0 1
Serial clock output of channel n Serial clock output value is "0". Serial clock output value is "1".
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SOmn
Serial data output of channel n
0
Serial data output value is "0".
1
Serial data output value is "1".
Note
In the 30- to 64-pin products, the value of the SO1 register is 0303H following a reset.
Caution
Be sure to clear bits 15 to 12 and 7 to 4 of the SO0 register to "0". Be sure to clear bits 15 to 10 and 7 to 2 of the SO1 register for 30- to 64-pin products and bits 15 to 12 and 7 to 4 of the SO1 register for 80- to 128-pin products to "0".
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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15.3.14 Serial output level register m (SOLm)
The SOLm register is used to set inversion of the data output level of each channel. This register can be set only in the UART mode. Be sure to set 0 for the bit corresponding the channel used in the SPI (CSI) mode or simplified I2C mode. Inverting channel n by using this register is reflected on pin output only when serial output is enabled (SOEmn = 1). When serial output is disabled (SOEmn = 0), the value of the SOmn bit is output as is. Rewriting the SOLm register is prohibited when the register is in operation (when SEmn = 1). The SOLm register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the SOLm register can be set with an 8-bit memory manipulation instruction with SOLmL. The value of each SOLm register is 0000H following a reset.
Figure 15 - 18 Format of Serial Output Level Register m (SOLm)
Address: After reset: R/W:
F0134H, F0135H (SOL0) 0000H R/W
Symbol
15
14
13
12
11
10
9
8
SOL0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
SOL02
0
SOL00
Address: After reset: R/W:
F0174H, F0175H (SOL1) 0000H R/W
Symbol
15
14
13
12
11
10
9
8
SOL1
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
SOL12
0
SOL10
SOLmn
Selects inversion of the level of the transmit data of channel n in UART mode
0
Communication data is output as is.
1
Communication data is inverted and output.
Caution Be sure to clear bits 15 to 3, and 1 of the SOL0 register, bits 15 to 1 of the SOL1 register for 30- to 64pin products, and bits 15 to 3, and 1 of the SOL1 register for 80- to 128-pin products to "0".
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Figure 15 - 19 shows examples in which the level of transmit data is reversed during UART transmission. Figure 15 - 19 Examples of Reverse Transmit Data
(a) Non-reverse Output (SOLmn = 0)
SOLmn = 0 output TxDq
ST
Transmit data
PS
(b) Reverse Output (SOLmn = 1)
SOLmn = 1 output
TxDq
ST Transmit data (inverted)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
PS
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15.3.15 Serial standby control register m (SSCm)
The SSC0 register is used to control the startup of reception (the SNOOZE mode) while in the STOP mode when receiving CSI00 or UART0 serial data. The SSC1Note register is used to control the startup of reception (the SNOOZE mode) while in the STOP mode when receiving CSI20 or UART2 serial data. The SSCm register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the SSCm register can be set with an 8-bit memory manipulation instruction with SSCmL. The value of each SSCm register is 0000H following a reset.
Caution The maximum transfer rate in the SNOOZE mode is as follows.
· When using CSI00, CSI20: Up to 1 Mbps
<R>
· When using UART0, UART2: Up to 115.2 kbps (when setting FWKUP = 1, fCLK = fIH (32 MHz))
Figure 15 - 20 Format of Serial Standby Control Register m (SSCm)
Address: After reset: R/W:
F0138H, F0139H (SSC0), F0178H, F0179H (SSC1)Note 0000H R/W
Symbol
15
14
13
12
11
10
9
8
SSCm
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
SSECm
SWCm
SSECm
Selection of whether to enable or disable the generation of communication error interrupts in the SNOOZE mode
0
Enable the generation of error interrupts (INTSRE0/INTSRE2).
1
Disable the generation of error interrupts (INTSRE0/INTSRE2).
· The SSECm bit can be set to 1 or 0 only when both the SWCm and EOCmn bits are set to 1 during UART
reception in the SNOOZE mode. In other cases, clear the SSECm bit to 0.
· Setting SSECm, SWCm = 1, 0 is prohibited.
SWCm
Setting of the SNOOZE mode
0
Do not use the SNOOZE mode function.
1
Use the SNOOZE mode function.
· When there is a hardware trigger signal in the STOP mode, the STOP mode is exited, and SPI (CSI) or UART reception is performed without operating the CPU (the SNOOZE mode).
· The SNOOZE mode function can only be specified when the high-speed on-chip oscillator clock or medium-speed on-chip oscillator clock is selected for the CPU/peripheral hardware clock (fCLK). If any other clock is selected, specifying this mode is prohibited.
· Even when using SNOOZE mode, be sure to set the SWCm bit to 0 in normal operation mode and change it to 1 just before shifting to STOP mode. Also, be sure to change the SWCm bit to 0 after returning from STOP mode to normal operation mode.
Note
The SSC1 register is only present in products with 80 to 128 pins.
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Figure 15 - 21 Interrupt in UART Reception Operation in SNOOZE Mode
EOCmn Bit 0 0 1 1
SSECm Bit 0 1 0 1
Reception Ended Successfully INTSRx is generated. INTSRx is generated. INTSRx is generated. INTSRx is generated.
Reception Ended in an Error INTSRx is generated. INTSRx is generated. INTSREx is generated.
No interrupt is generated.
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15.3.16 Input switch control register (ISC)
The ISC1 and ISC0 bits of the ISC register are used to realize a LIN-bus communication operation by UART2 in coordination with an external interrupt and the timer array unit. The ISC4 to ISC2 bits are used to select the serial data input source and serial clock input source of CSI00. The ISC7 to ISC5 bits are used to select the serial data input source and serial clock input source of CSI01. When bit 0 is set to 1, the input signal of the serial data input (RxD2) pin is selected as an external interrupt (INTP0) that can be used to detect a wakeup signal. When bit 1 is set to 1, the input signal of the serial data input (RxD2) pin is selected as a timer input, so that wake up signal can be detected, the low width of the break field, and the pulse width of the sync field can be measured by the timer. When bit 2 is set to 1, the ELCL output signal can be selected as the serial data input source of CSI00. Bits 3 and 4 can be used to select the SCK00 pin input, ELCL output signal, or TO01 output signal as the serial clock input source of CSI00. When bit 5 is set to 1, the ELCL output signal can be selected as the serial data input source of CSI01. Bits 6 and 7 can be used to select the SCK01 pin input, ELCL output signal, or TO01 output signal as the serial clock input source of CSI01. The ISC register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of the ISC register is 00H following a reset.
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Figure 15 - 22 Format of Input Switch Control Register (ISC)
Address: After reset: R/W:
F0073H 00H R/W
Symbol ISC
7 ISC7
6 ISC6
5 ISC5
4 ISC4
3 ISC3
2 ISC2
1 ISC1
0 ISC0
ISC7 0 0 1 1
ISC6 0 1 0 1
Switch of the serial clock input source of CSI01Note 1 Input signal of the SCK01 pin (normal operation) ELCL output signal TO01 output signal Setting prohibited
ISC5 0 1
Switch of the serial data input source of CSI01Note 2 Input signal of the SI01 pin (normal operation) ELCL output signal
ISC4 0 0 1 1
ISC3 0 1 0 1
Switch of the serial clock input source of CSI00Note 3 Input signal of the SCK00 pin (normal operation) ELCL output signal TO01 output signal Setting prohibited
ISC2 0 1
Switch of the serial data input of CSI00Note 4 Input signal of the SI00 pin (normal operation) ELCL output signal
ISC1 0 1
Switching channel 7 input of timer array unit Uses the input signal of the TI07 pin as a timer input (normal operation). Input signal of the RxD2 pin is used as timer input (detects the wakeup signal and measures the low width of the break field and the pulse width of the sync field).
ISC0
Switching external interrupt (INTP0) input
0
Uses the input signal of the INTP0 pin as an external interrupt (normal operation).
1
Uses the input signal of the RxD2 pin as an external interrupt (wakeup signal detection).
Note 1. Note 2. Note 3. Note 4.
When UART mode or simplified I2C mode is to be selected for channel 1, set the ISC7 and ISC6 bits to 0. When UART mode or simplified I2C mode is to be selected for channel 1, set the ISC5 bit to 0. When UART mode or simplified I2C mode is to be selected for channel 0, set the ISC4 and ISC3 bits to 0. When UART mode or simplified I2C mode is to be selected for channel 0, set the ISC2 bit to 0.
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15.3.17 Noise filter enable register 0 (NFEN0)
The NFEN0 register is used to set whether the noise filter can be used for the input signal from the serial data input pin to each channel. Disable the noise filter of the pin used for SPI (CSI) or simplified I2C communication, by clearing the corresponding bit of this register to 0. Enable the noise filter of the pin used for UART communication, by setting the corresponding bit of this register to 1. When the noise filter is enabled, after synchronization is performed with the operation clock (fMCK) of the target channel, 2-clock match detection is performed. When the noise filter is disabled, only synchronization is performed with the operation clock (fMCK) of the target channel. The NFEN0 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of the NFEN0 register is 00H following a reset.
Figure 15 - 23 Format of Noise Filter Enable Register 0 (NFEN0)
Address: After reset: R/W:
F0070H 00H R/W
Symbol
7
6
5
4
3
2
1
0
NFEN0
0
SNFEN30
0
SNFEN20
0
SNFEN10
0
SNFEN00
SNFEN30
Use of noise filter of RxD3 pin
0
Noise filter OFF
1
Noise filter ON
Set SNFEN30 to 1 to use the RxD3 pin. Clear SNFEN30 to 0 to use the other than RxD3 pin.
SNFEN20
Use of noise filter of RxD2 pin
0
Noise filter OFF
1
Noise filter ON
Set SNFEN20 to 1 to use the RxD2 pin. Clear SNFEN20 to 0 to use the other than RxD2 pin.
SNFEN10
Use of noise filter of RxD1 pin
0
Noise filter OFF
1
Noise filter ON
Set the SNFEN10 bit to 1 to use the RxD1 pin. Clear SNFEN10 to 0 to use the other than RxD1 pin.
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SNFEN00
Use of noise filter of RxD0 pin
0
Noise filter OFF
1
Noise filter ON
Set the SNFEN00 bit to 1 to use the RxD0 pin. Clear SNFEN00 to 0 to use the other than RxD0 pin.
Caution Be sure to clear bits 7 to 5, 3, and 1 for 30- to 64-pin products and bits 7, 5, 3, and 1 for 80- to 128-pin products to "0".
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.3.18 Registers controlling port functions of serial input/output pins
Using the serial array unit requires setting of the registers that control the port functions multiplexed on the target channel (port mode register (PMxx), port register (Pxx), port input mode register (PIMxx), port output mode register (POMxx), port mode control A register (PMCAxx), port mode control T register (PMCTxx), port mode control E register (PMCEx), port function output enable register 1 (PFOE1)). For details, see 4.3.1 Port mode registers (PMxx), 4.3.2 Port registers (Pxx), 4.3.4 Port input mode registers (PIMxx), 4.3.5 Port output mode registers (POMxx), 4.3.7 Port mode control A registers (PMCAxx), 4.3.8 Port mode control T registers (PMCTxx), 4.3.9 Port mode control E registers (PMCEx), and 4.3.15 Port function output enable registers (PFOEx). Specifically, using a port pin with a multiplexed serial data or serial clock output function (e.g. P02/ANI17/SO10/TxD1) for serial data or serial clock output, requires setting the corresponding bits in the port mode control A register (PMCAxx), port mode control T register (PMCTxx), port mode control E register (PMCEx), and port mode register (PMxx) to 0, and the corresponding bit in the port register (Pxx) to 1. And set the corresponding bit in the port function output enable register 1 (PFOE1) to 1. When using the port pin in N-ch open-drain output (VDD toleranceNote 1/EVDD toleranceNote 2) mode, set the corresponding bit in the port output mode register (POMxx) to 1. When connecting an external device operating on a different potential (1.8 V, 2.5 V or 3 V), see 4.4.5 Handling different potential (1.8 V, 2.5 V, or 3 V) by using I/O buffers.
Example: When P02/ANI17/SO10/TxD1 is to be used for serial data output
Set the PMCA02 bit of port mode control A register 0 to 0.
Set the PMCT02 bit of port mode control T register 0 to 0.
Set the PMCE02 bit of port mode control E register 0 to 0.
Set the PM02 bit of port mode register 0 to 0.
Set the P02 bit of port register 0 to 1.
Specifically, using a port pin with a multiplexed serial data or serial clock input function (e.g. P03/ANI16/SI10/RxD1/SDA10) for serial data or serial clock input, requires setting the corresponding bit in the port mode register (PMxx) to 1, and the corresponding bits in the port mode control A register (PMCAxx), port mode control T register (PMCTxx), and port mode control E register (PMCEx) to 0. In this case, the corresponding bit in the port register (Pxx) can be set to 0 or 1. When the TTL input buffer is selected, set the corresponding bit in the port input mode register (PIMxx) to 1. When connecting an external device operating on a different potential (1.8 V, 2.5 V or 3 V), see 4.4.5 Handling different potential (1.8 V, 2.5 V, or 3 V) by using I/O buffers.
Example: When P03/ANI16/SI10/RxD1/SDA10 is to be used for serial data input Set the PMCA03 bit of port mode control A register 0 to 0. Set the PMCT03 bit of port mode control T register 0 to 0. Set the PMCE03 bit of port mode control E register 0 to 0. Set the PM03 bit of port mode register 0 to 1. Set the P03 bit of port register 0 to 0 or 1.
Note 1. Note 2.
30- to 52-pin products 64- to 128-pin products
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.3.19 UART loopback select register (ULBS)
The ULBS register is used to enable the UART loopback function. This register has bits to individually control UART channels. When the bit corresponding to each channel is set to 1, the UART loopback function is selected, and output from the transmission shift register is looped back to the reception shift register. The ULBS register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of the ULBS register is 00H following a reset.
Figure 15 - 24 Format of UART Loopback Select Register (ULBS)
Address: After reset: R/W:
F0079H 00H R/W
Symbol
7
ULBS
0
6
<5>
<4>
<3>
<2>
<1>
<0>
0
ULBS5
ULBS4
ULBS3
ULBS2
ULBS1
ULBS0
ULBSn
Selection of the UART loopback function
0
Inputs the states of the RxD0 to RxD3 pins of serial array unit UART0 to UART3 to the
reception shift register.
1
Loops back output from the transmission shift register to the reception shift register.
Caution Be sure to set bits 6 and 7 to "0".
Remark n = 0 to 3
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.4
Operation Stop Mode
Each serial interface of serial array unit has the operation stop mode. In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the pin for serial interface can be used as port function pins in this mode.
15.4.1 Stopping the Operation by Units
The stopping of the operation by units is set by using peripheral enable register 0 (PER0). The PER0 register is used to enable or disable the supply of a clock signal to various on-chip peripheral modules. Clock supply to an on-chip peripheral module that is not to be used can be stopped to decrease power consumption and noise. To stop the operation of serial array unit 0, set bit 2 (SAU0EN) to 0. To stop the operation of serial array unit 1, set bit 3 (SAU1EN) to 0.
Figure 15 - 25 Peripheral Enable Register 0 (PER0) Setting When Stopping the Operation by Units (a) Peripheral enable register 0 (PER0) ... Set only the bit of SAUm to be stopped to 0.
PER0
7
RTCEN ×
6
IICA1ENNote ×
5
ADCEN ×
4
IICA0EN ×
3
SAU1EN 0/1
2
SAU0EN 0/1
1
TAU1ENNote ×
0
TAU0EN ×
Control of SAUm input clock 0: Stops supply of input clock
1: Supplies input clock
Note
These bits are only present in products with 80, 100, and 128 pins.
Caution 1. If SAUmEN = 0, writing to the registers which control serial array unit m is ignored, and, even if the register is read, only the initial value is read Note that this does not apply to the following registers. · Input switch control register (ISC) · Noise filter enable register 0 (NFEN0) · Port input mode registers 0, 1, 4, 5, 8, 14 (PIM0, PIM1, PIM4, PIM5, PIM8, PIM14) · Port output mode registers 0, 1, 4, 5, 7 to 9, 14 (POM0, POM1, POM4, POM5, POM7 to POM9, POM14) · Port mode control A registers 0, 3, 14 (PMCA0, PMCA3, PMCA14) · Port mode control T registers 0, 3 (PMCT0, PMCT3) · Port mode control E register 0 (PMCE0) · Port mode registers 0, 1, 3 to 5, 7 to 9, 14 (PM0, PM1, PM3 to PM5, PM7 to PM9, PM14) · Port registers 0, 1, 3 to 5, 7 to 9, 14 (P0, P1, P3 to P5, P7 to P9, P14)
Caution 2. Be sure to clear the following bits to 0. Bits 6 and 1 in the 30-, 32-, 36-, 40-, 44-, 48-, 52-, and 64-pin products
Remark ×: Bits not used with serial array units (depending on the settings of other peripheral functions) 0/1: Set to 0 or 1 depending on the usage of the user
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.4.2 Stopping the Operation by Channels
The stopping of the operation by channels is set using each of the following registers.
Figure 15 - 26 Each Register Setting When Stopping the Operation by Channels
(a) Serial channel stop register m (STm) ... The STm is a trigger register that is used to enable stopping communication/count by each channel.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
STm 0
0
0
0
0
0
0
0
0
0
0
STm3Note STm2Note STm1 STm0
0 0/1 0/1 0/1 0/1
1: Clears the SEmn bit to 0 and stops the communication operation * Because the STmn bit is a trigger bit, it is cleared immediately when SEmn = 0.
(b) Serial channel enable status register m (SEm) ... This register indicates whether data transmission/reception operation of each channel is enabled or stopped.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SEm 0
0
0
0
0
0
0
0
0
0
0
SEm3Note SEm2Note SEm1 SEm0
0 0/1 0/1 0/1 0/1
0: Operation stops
* The SEm is a read-only status register, whose operation is stopped by using the STm register. With a channel whose operation is stopped, the value of the CKOmn bit of the SOm register can be set by software.
(c) Serial output enable register m (SOEm) ... This register is used to enable or stop output of the serial communication operation of each channel.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SOEm 0
0
0
0
0
0
0
0
0
0
0
0
SOEm3
Note
0/1
SOEm2
Note
0/1
SOEm1
0/1
SOEm0
0/1
0: Stops output by serial communication operation * For channel n, whose serial output is stopped, the SOmn bit value of the SOm register can be set by software.
(d) Serial output register m (SOm) ...The SOm is a buffer register for serial output of each channel.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SOm 0
0
0
0
CKOm3
Note
0/1
CKOm2
Note
0/1
CKOm1
0/1
CKOm0
0/1
0
0
0
0
SOm3
Note
0/1
SOm2
Note
0/1
SOm1
0/1
SOm0
0/1
1: Serial clock output value is "1"
1: Serial data output value is "1"
* When using pins corresponding to each channel as port function pins, set the corresponding CKOmn, SOmn bits to "1".
Note
These bits are only present in products with 80 to 128 pins of serial array unit 1.
Remark 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3) Remark 2. : Setting disabled (fixed by hardware), 0/1: Set to 0 or 1 depending on the usage of the user
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.5
Operation of 3-Wire Serial SPI (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21,
CSI30, CSI31) Communication
This is a clocked communication function that uses three lines: serial clock (SCK) and serial data (SI and SO) lines. [Data transmission/reception]
· Data length of 7 or 8 bits · Phase control of transmit/receive data · MSB/LSB first selectable [Clock control]
· Master/slave selection
· Phase control of I/O clock
· Setting of transfer period by prescaler and internal counter of each channel
· Maximum transfer rateNote During master communication: Max. fCLK/2 (CSI00 only)
Max. fCLK/4
During slave communication:
Max. fMCK/6
[Interrupt function]
· Transfer end interrupt/buffer empty interrupt [Error detection flag]
· Overrun error
In addition, SPIs (CSIs) of following channels support the SNOOZE mode. In the SNOOZE mode, data can be received without CPU processing upon detecting SCK input in the STOP mode. The SNOOZE mode is only available in the following SPIs (CSIs), which support asynchronous reception. · 30- to 64-pin products: CSI00 · 80- to 128-pin products: CSI00, CSI20
Note
Set up the transfer rate within a range satisfying the SCK cycle time (tKCY). For details, see CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
The channels supporting 3-wire serial SPI (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) are channels 0 to 3 of SAU0 and channels 0 to 3 of SAU1.
<30- and 32-pin products>
Unit 0
1
Channel 0 1 2 3 0 1
Used as SPI (CSI) CSI00 -- -- CSI11 CSI20 --
Used as UART UART0
UART1
UART2 (supporting LIN-bus)
Used as Simplified I2C IIC00 -- -- IIC11 IIC20 --
<36-, 40-, and 44-pin products>
Unit 0
1
Channel 0 1 2 3 0 1
Used as SPI (CSI) CSI00 -- -- CSI11 CSI20 CSI21
Used as UART UART0
UART1
UART2 (supporting LIN-bus)
Used as Simplified I2C IIC00 -- -- IIC11 IIC20 IIC21
<48- and 52-pin products>
Unit 0
1
Channel 0 1 2 3 0 1
Used as SPI (CSI) CSI00 CSI01 -- CSI11 CSI20 CSI21
Used as UART UART0
UART1
UART2 (supporting LIN-bus)
Used as Simplified I2C IIC00 IIC01 -- IIC11 IIC20 IIC21
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<64-pin products>
Unit 0
1
Channel 0 1 2 3 0 1
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Used as SPI (CSI) CSI00 CSI01 CSI10 CSI11 CSI20 CSI21
Used as UART UART0
UART1
UART2 (supporting LIN-bus)
Used as Simplified I2C IIC00 IIC01 IIC10 IIC11 IIC20 IIC21
<80-, 100-, and 128-pin products>
Unit 0
1
Channel 0 1 2 3 0 1 2 3
Used as SPI (CSI) CSI00 CSI01 CSI10 CSI11 CSI20 CSI21 CSI30 CSI31
Used as UART UART0 UART1
UART2 (supporting LIN-bus) UART3
Used as Simplified I2C IIC00 IIC01 IIC10 IIC11 IIC20 IIC21 IIC30 IIC31
3-wire serial SPI (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) performs the following seven types of
communication operations.
· Master transmission
(See 15.5.1.)
· Master reception
(See 15.5.2.)
· Master transmission/reception (See 15.5.3.)
· Slave transmission
(See 15.5.4.)
· Slave reception
(See 15.5.5.)
· Slave transmission/reception (See 15.5.6.)
· SNOOZE mode function
(See 15.5.7.)
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.5.1 Master Transmission
Master transmission is that the RL78 microcontroller outputs a transfer clock and transmits data to another device.
3-Wire Serial SPI
CSI00
CSI01
CSI10
CSI11
CSI20
CSI21
CSI30
CSI31
Target channel
Channel 0 Channel 1 Channel 2 Channel 3 Channel 0 Channel 1 Channel 2 Channel 3 of SAU0 of SAU0 of SAU0 of SAU0 of SAU1 of SAU1 of SAU1 of SAU1
Pins used
SCK00, SO00
SCK01, SO01
SCK10, SO10
SCK11, SO11
SCK20, SO20
SCK21, SO21
SCK30, SO30
SCK31, SO31
Interrupt
INTCSI00 INTCSI01 INTCSI10 INTCSI11 INTCSI20 INTCSI21 INTCSI30 INTCSI31
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected.
Error detection flag None
Transfer data length 7 or 8 bits
Transfer rateNote
Max. fCLK /2 [Hz] (CSI00 only), fCLK /4 [Hz] Min. fCLK (2 × 215 × 128) [Hz] fCLK: System clock frequency
Data phase
Selectable by the DAPmn bit of the SCRmn register · DAPmn = 0: Data output starts from the start of the operation of the serial clock. · DAPmn = 1: Data output starts half a clock cycle before the start of the serial clock operation.
Clock phase
Selectable by the CKPmn bit of the SCRmn register · CKPmn = 0: Non-reverse · CKPmn = 1: Reverse
Data direction
MSB or LSB first
Note
Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics specified in the electrical characteristics. For details, see CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13
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(1) Register setting
Figure 15 - 27 Example of Contents of Registers for Master Transmission of 3-Wire Serial SPI (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31)
(a) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CKSmn CCSmn
STSmn
SISmn0
MDmn2 MDmn1 MDmn0
SMRmn 0/1
0
0
0
0
0
0
0
0
0
1
0
0
0
0 0/1
Operation clock (fMCK) of channel n 0: Prescaler output clock CKm0 set by the SPSm register 1: Prescaler output clock CKm1 set by the SPSm register
Interrupt source of channel n 0: Transfer end interrupt 1: Buffer empty interrupt
(b) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9
8
7
TXEmn RXEmn DAPmn CKPmn
EOCmn PTCmn1 PTCmn0 DIRmn
SCRmn 1
0 0/1 0/1 0
0
0
0
0/1
6
5
4
3
SLCmn1 SLCmn0
0
0
0
0
Selection of the data and clock phase (For details about the setting, see 15.3 Registers to Control the Serial Array Unit.)
Selection of data transfer sequence 0: Inputs/outputs data with MSB first 1: Inputs/outputs data with LSB first.
2
1
0
DLSmn1 DLSmn0
1 1Note 0/1
Setting of data length 0: 7-bit data length 1: 8-bit data length
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOp)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Baud rate setting
SDRmn
0
(Operation clock (fMCK) division setting)
Transmit data (Transmit data setting)
SIOp
(d) Serial output register m (SOm) ... Set only the bit of the target channel.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CKOm3 CKOm2 CKOm1 CKOm0
SOm3 SOm2 SOm1 SOm0
SOm 0
0
0
0 0/1 0/1 0/1 0/1 0
0
0
0 0/1 0/1 0/1 0/1
Communication starts when a bit is 1 if the clock phase is nonreverse (the CKPmn bit of the SCRmn = 0). If the clock phase is reversed (CKPmn = 1), communication starts when a bit is 0.
(e) Serial output enable register m (SOEm) ... Set only the bit of the target channel to 1.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SOEm3 SOEm2 SOEm1 SOEm0
SOEm 0
0
0
0
0
0
0
0
0
0
0
0 0/1 0/1 0/1 0/1
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(f) Serial channel start register m (SSm) ... Set only the bit of the target channel to 1.
15 SSm 0
Note
14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SSm3 SSm2 SSm1 SSm0
0
0
0
0
0
0
0
0
0
0
0 0/1 0/1 0/1 0/1
Only provided for the SCR00 and SCR01 registers and the SCR10 and SCR11 registers of 80- to 128-pin products. This bit is fixed to 1 for the other registers.
Remark 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13
Remark 2. : Setting is fixed in the SPI (CSI) master transmission mode, : Setting disabled (set to the initial value) 0/1: Set to 0 or 1 depending on the usage of the user
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RL78/G23 (2) Operation procedure
Figure 15 - 28 Initial Setting Procedure for Master Transmission
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Starting initial setting Setting the PRR0 register Setting the PER0 register Setting the SPSm register Setting the SMRmn register Setting the SCRmn register Setting the SDRmn register Setting the SOm register Setting of the SOEm register
Setting port Writing to the SSm register
Completing initial setting
Release the serial array unit from the reset state. Start clock supply to the serial array unit.
Set the operation clock.
Set an operation mode, etc.
Set a communication format.
Set a transfer baud rate (setting the transfer clock by dividing the operation clock (fMCK)).
Set the initial output level of the serial clock (CKOmn) and serial data (SOmn).
Set the SOEmn bit to 1 and enable data output of the target channel.
Setting a port register and a port mode register (Enable data output and clock output of the target channel) Set the SSmn bit of the target channel to 1 (SEmn bit = 1 : to enable operation). Setting of SAU is completed. Write transmit data to the SIOp register (bits 7 to 0 of the SDRmn register) and start communication.
Figure 15 - 29 Procedure for Stopping Master Transmission
Starting setting to stop
(Selective) (Essential)
No TSFmn = 0?
Yes Writing the STm register
(Essential) (Selective)
Changing setting of the SOEm register
Changing setting of the SOm register
(Selective)
Setting the PER0 register
Setting the PRR0 register
Stop setting is completed
If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait)
Write 1 to the STmn bit of the target channel (stopping operation by setting SEmn = 0).
Set the SOEmn bit to 0 and stop the output of the target channel.
The levels of the serial clock (CKOmn) and serial data (SOmn) on the target channel can be changed if necessitated by an emergency.
Stop clock supply to the serial array unit.
Reset the serial array unit.
The master transmission is stopped. Go to the next processing.
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RL78/G23 Figure 15 - 30 Procedure for Resuming Master Transmission
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Starting setting for resumption
(Essential) (Essential)
No Slave ready?
Yes
Port manipulation
(Selective) Changing setting of the SPSm register
(Selective) Changing setting of the SDRmn register
(Selective) Changing setting of the SMRmn register
(Selective) Changing setting of the SCRmn register
(Selective) Changing setting of the SOEm register
Wait until stop the communication target (slave) or communication operation completed.
Disable data output and clock output of the target channel by setting a port register and a port mode register.
Re-set the register to change the operation clock setting.
Re-set the register to change the transfer baud rate setting (setting the transfer clock by dividing the operation clock (fMCK)).
Re-set the register to change serial mode register mn (SMRmn) setting.
Re-set the register to change serial communication operation setting register mn (SCRmn) setting.
Set the SOEmn bit to 0 to stop output from the target channel.
(Selective )
Changing setting of the SOm register
Set the initial output level of the serial clock (CKOmn) and serial data (SOmn).
(Essential) Changing setting of the SOEm register
Set the SOEmn bit to 1 and enable output from the target channel.
(Essential)
Port manipulation
Enable data output and clock output of the target channel by setting a port register and a port mode register.
(Essential) Writing to the SSm register
Completing resumption setting
Set the SSmn bit of the target channel to 1 (SEmn = 1 : to enable operation).
Setting is completed. Sets transmit data to the SIOp register (bits 7 to 0 of the SDRmn register) and start communication.
Remark If PRR0 is rewritten while stopping the communication to reset the serial array unit, wait until the communication target (slave) stops or communication finishes, and then perform initialization instead of restarting the communication.
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(3) Processing flow (in single-transmission mode) Figure 15 - 31 Timing Chart of Master Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0)
SSmn STmn SEmn SDRmn SCKp pin SOp pin
Shift register mn
INTCSIp
TSFmn
Transmit data 1
Transmit data 1 Shift operation Data transmission
Transmit data 2
Transmit data 2 Shift operation Data transmission
Transmit data 3
Transmit data 3 Shift operation Data transmission
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Figure 15 - 32 Flowchart of Master Transmission (in Single-Transmission Mode)
Starting SPI (CSI) communication
Main routine
Interrupt processing routine
SAU initial setting
For the initial setting, refer to Figure 15 - 28. (Select the transfer end interrupt.)
Setting transmit data Enables interrupt
Set data for transmission and the number of data. Clear communication end flag (Storage area, Transmission data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software)
Clear interrupt request flag (xxIF), reset interrupt mask (xxMK) and set interrupt enable (EI).
Writing transmit data to SIOp (= SDRmn [7:0])
Wait for transmit completes
Transfer end interrupt
Read transmit data from storage area and write it to SIOp. Update transmit data pointer.
Writing to SIOp makes SOp and SCKp signals out (communication starts)
When Transfer end interrupt is generated, it moves to interrupt processing routine
Transmitting next data?
Yes
Writing transmit data to SIOp (= SDRmn [7:0])
No
Sets communication completion flag
Read transmit data, if any, from storage area and write it to SIOp. Update transmit data pointer. If not, set transmit end flag
RETI
No Transmission completed?
Yes Disable interrupt (MASK)
Check completion of transmission by verifying transmit end flag
Set STmn bit to 1
End of communication
Main routine
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(4) Processing flow (in continuous transmission mode)
Figure 15 - 33 Timing Chart of Master Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0)
SSmn <1> STmn SEmn
SDRmn
SCKp pin SOp pin Shift
register mn INTCSIp
MDmn0 TSFmn BFFmn
Transmit data 1
Transmit data 2
Transmit data 1
Shift operation
Data transmission
<6>
Transmit data 3
Transmit data 2
Shift operation
Transmit data 3
Shift operation
Data transmission
Data transmission <4>
<2><3> <2>
<3> <2>
<3>
<5>
Note
Note
If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn (SSRmn) is 1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten.
Caution
The MDmn0 bit of serial mode register mn (SSRmn) can be rewritten even during operation. However, rewrite it before transfer of the last bit is started, so that it has been rewritten before the transfer end interrupt of the last transmit data.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Figure 15 - 34 Flowchart of Master Transmission (in Continuous Transmission Mode)
Starting setting
Main routine
<1> SAU initial setting
For the initial setting, refer to Figure 15 - 28. (Select buffer empty interrupt.)
Setting transmit data Enables interrupt
Set the data pointer for transmission and the number of data items. Clear communication end flag (Storage area, Transmission data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software)
Clear interrupt request flag (xxIF), reset interrupt mask (xxMK) and set interrupt enable (EI).
<2> Writing transmit data to SIOp (= SDRmn [7:0])
Read transmit data from storage area and write it
to SIOp. Update transmit data pointer.
Writing to SIOp makes SOp
and SCKp signals out
(communication starts)
Wait for transmit completes <3><5>
Buffer empty/transfer end interrupt
When transfer end interrupt is generated, it moves to interrupt processing routine.
Interrupt processing routine
Number of communication data 0?
Yes
Writing transmit data to SIOp (= SDRmn [7:0])
Subtract -1 from number of communication data
No
If transmit data is left, read them from storage
area then write into SIOp, and update transmit
data pointer and number of transmit data.
If no more transmit data, clear MDmn0 bit if it's
set. If not, finish.
MDmn0 = 1?
Yes
<4>
Clear MDmnY0ebsit to 0
No
Sets communication completion interrupt flag
RETI
Main routine
No
Set MDmn0 bit to 1 Yes
Transmission completed? Yes
Communication continued? No
Disable interrupt (MASK)
Check completion of transmission by verifying transmit end flag
<6>
Set STmn bit to 1
End of communication
Remark <1> to <6> in the figure correspond to <1> to <6> in Figure 15 - 33 Timing Chart of Master Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0).
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.5.2 Master Reception
Master reception is that the RL78 microcontroller outputs a transfer clock and receives data from another device.
3-Wire Serial SPI
CSI00
CSI01
CSI10
CSI11
CSI20
CSI21
CSI30
CSI31
Target channel
Channel 0 Channel 1 Channel 2 Channel 3 Channel 0 Channel 1 Channel 2 Channel 3 of SAU0 of SAU0 of SAU0 of SAU0 of SAU1 of SAU1 of SAU1 of SAU1
Pins used
SCK00, SI00
SCK01, SI01
SCK10, SI10
SCK11, SI11
SCK20, SI20
SCK21, SI21
SCK30, SI30
SCK31, SI31
Interrupt
INTCSI00 INTCSI01 INTCSI10 INTCSI11 INTCSI20 INTCSI21 INTCSI30 INTCSI31
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected.
Error detection flag Overrun error detection flag (OVFmn) only
Transfer data length 7 or 8 bits
Transfer rateNote
Max. fCLK/2 [Hz] (CSI00 only), fCLK/4 [Hz] Min. fCLK/(2 × 215 × 128)[Hz] fCLK: System clock frequency
Data phase
Selectable by the DAPmn bit of the SCRmn register · DAPmn = 0: Data input starts from the start of the operation of the serial clock. · DAPmn = 1: Data input starts half a clock cycle before the start of the serial clock operation.
Clock phase
Selectable by the CKPmn bit of the SCRmn register · CKPmn = 0: Non-reverse · CKPmn = 1: Reverse
Data direction
MSB or LSB first
Note
Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics specified in the electrical characteristics. For details, see CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(1) Register setting
Figure 15 - 35 Example of Contents of Registers for Master Reception of 3-Wire Serial SPI (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31)
(a) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CKSmn CCSmn
STSmn
SISmn0
MDmn2 MDmn1 MDmn0
SMRmn
0/1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0/1
Operation clock (fMCK) of channel n 0: Prescaler output clock CKm0 set by the SPSm register 1: Prescaler output clock CKm1 set by the SPSm register
Interrupt source of channel n 0: Transfer end interrupt 1: Buffer empty interrupt
(b) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9
8
7
TXEmn RXEmn DAPmn CKPmn
EOCmn PTCmn1 PTCmn0 DIRmn
SCRmn
1
0
0/1 0/1
0
0
0
0
0/1
6
5
4
3
SLCmn1 SLCmn0
0
0
0
0
Selection of the data and clock phase (For details about the setting, see 15.3 Registers to Control the Serial Array Unit.)
Selection of data transfer sequence 0: Inputs/outputs data with MSB first 1: Inputs/outputs data with LSB first
2
1
0
DLSmn1 DLSmn0
1
1Note 0/1
Setting of data length 0: 7-bit data length 1: 8-bit data length
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOp)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Baud rate setting
SDRmn
(Operation clock (fMCK) division setting)
0
Receive data (Write FFH as dummy data.)
SIOp
(d) Serial output register m (SOm) ... Set only the bit of the target channel.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CKOm3 CKOm2 CKOm1 CKOm0
SOm3 SOm2 SOm1 SOm0
SOm
0
0
0
0
0/1 0/1 0/1 0/1
0
0
0
0
×
×
×
×
Communication starts when a bit is 1 if the clock phase is nonreverse (the CKPmn bit of the SCRmn = 0). If the clock phase is reversed (CKPmn = 1), communication starts when a bit is 0.
(e) Serial output enable register m (SOEm) ...This register is not used in this mode.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SOEm3 SOEm2 SOEm1 SOEm0
SOEm
0
0
0
0
0
0
0
0
0
0
0
0
×
×
×
×
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(f) Serial channel start register m (SSm) ... Set only the bit of the target channel to 1.
15 SSm 0
Note
14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SSm3 SSm2 SSm1 SSm0
0
0
0
0
0
0
0
0
0
0
0 0/1 0/1 0/1 0/1
Only provided for the SCR00 and SCR01 registers and the SCR10 and SCR11 registers of 80- to 128-pin products. This bit is fixed to 1 for the other registers.
Remark 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13
Remark 2. : Setting is fixed in the SPI (CSI) master reception mode, : Setting disabled (set to the initial value) ×: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user
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RL78/G23 (2) Operation procedure
Figure 15 - 36 Initial Setting Procedure for Master Reception
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Starting initial setting
Setting the PRR0 register
Release the serial array unit from the reset state.
Setting the PER0 register
Start clock supply to the serial array unit.
Setting the SPSm register
Set the operation clock.
Setting the SMRmn register
Set an operation mode, etc.
Setting the SCRmn register Setting the SDRmn register
Setting the SOm register Setting port
Writing to the SSm register Completing initial setting
Set a communication format.
Set a transfer baud rate (setting the transfer clock by dividing the operation clock (fMCK)).
Set the initial output level of the serial clock (CKOmn).
Enable clock output of the target channel by setting a port register and a port mode register.
Set the SSmn bit of the target channel to 1 (SEmn bit = 1: to enable operation).
Initial setting is completed. Set dummy data to the SIOp register (bits 7 to 0 of the SDRmn register) and start communication.
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RL78/G23 Figure 15 - 37 Procedure for Stopping Master Reception
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Starting setting to stop
(Selective) (Essential)
No TSFmn = 0?
Yes Writing the STm register
(Essential)
Changing setting of the SOEm register
(Selective)
Changing setting of the SOm register
(Selective) Setting the PER0 register
Setting the PRR0 register Stop setting is completed
If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait.)
Write 1 to the STmn bit of the target channel (stopping operation by setting SEmn = 0).
Set the SOEmn bit to 0 and stop the output of the target channel.
The levels of the serial clock (CKOmn) on the target channel can be changed if necessitated by an emergency.
Stop clock supply to the serial array unit.
Reset the serial array unit.
After the stop setting is completed, go to the next processing.
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RL78/G23 Figure 15 - 38 Procedure for Resuming Master Reception
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Starting setting for resumption
(Essential) (Essential)
No
Completing slave preparations?
Yes
Port manipulation
Wait until stop the communication target (slave) or communication operation completed.
Disable clock output of the target channel by setting a port register and a port mode register.
(Selective) Changing setting of the SPSm register (Selective) Changing setting of the SDRmn register (Selective) Changing setting of the SMRmn register (Selective) Changing setting of the SCRmn register
Re-set the register to change the operation clock setting.
Re-set the register to change the transfer baud rate setting (setting the transfer clock by dividing the operation clock (fMCK)).
Re-set the register to change serial mode register mn (SMRmn) setting.
Re-set the register to change serial communication operation setting register mn (SCRmn) setting.
(Selective)
Changing setting of the SOm register
(Selective)
Clearing error flag
(Essential)
Port manipulation
Set the initial output level of the serial clock (CKOmn).
If the OVF flag remains set, clear this using serial flag clear trigger register mn (SIRmn).
Enable clock output of the target channel by setting a port register and a port mode register.
(Essential) Writing to the SSm register
Completing resumption setting
Set the SSmn bit of the target channel to 1 (SEmn bit = 1: to enable operation).
Setting is completed. Sets dummy data to the SIOp register (bits 7 to 0 of the SDRmn register) and start communication.
Remark If PRR0 is rewritten while stopping the communication to reset the serial array unit, wait until the communication target (slave) stops or communication finishes, and then perform initialization instead of restarting the communication.
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(3) Processing flow (in single-reception mode) Figure 15 - 39 Timing Chart of Master Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
SSmn STmn SEmn SDRmn
SCKp pin SIp pin Shift
register mn INTCSIp
TSFmn
Dummy data for reception Write
Receive data 1 Reception& shift operation
Receive data 1 Dummy data
Write Read
Receive data 2
Reception& shift operation
Receive data 2 Receive data 3
Dummy data Write Read
Read
Receive data 3 Reception& shift operation
Data reception
Data reception
Data reception
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Figure 15 - 40 Flowchart of Master Reception (in Single-Reception Mode)
Main routine
Interrupt processing routine
Starting SPI (CSI) communication
SAU initial setting
Setting receive data Enables interrupt
Writing dummy data to SIOp (= SDRmn [7:0])
For the initial setting, refer to Figure 15 - 36. (Select transfer end interrupt)
Setting storage area of the receive data, number of communication data (Storage area, Reception data pointer, and number of communication data are optionally set on the internal RAM by the software)
Clear interrupt request flag (xxIF), reset interrupt mask (xxMK) and set interrupt enable (EI)
Writing to SIOp makes SCKp signals out (communication starts)
Wait for receive completes
Transfer end interrupt
Reading receive data from SIOp (= SDRmn [7:0])
RETI No
All reception completed? Yes
Disable interrupt (MASK)
Set STmn bit to 1
End of communication
When transfer end interrupt is generated, it moves to interrupt processing routine
Read receive data then writes to storage area. Update receive data pointer and number of communication data.
Check the number of communication data
Main routine
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(4) Processing flow (in continuous reception mode) Figure 15 - 41 Timing Chart of Master Reception (in Continuous Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
SSmn <1> STmn SEmn
SDRmn
SCKp pin SIp pin Shift
register mn INTCSIp
MDmn0
Dummy data Dummy data Receive data 1 Dummy data
<2> Write <2> Write
<2> Write Read
Receive data 1 Reception & shift operation
Receive data 2 Reception & shift operation
Data reception
Data reception
TSFmn
BFFmn
<8>
Receive data 3 Receive data 2
Read
Read
Receive data 3 Reception & shift operation
Data reception <5>
<3>
<3>
<4>
<3> <4>
<6> <7>
Caution
The MDmn0 bit can be rewritten even during operation. However, rewrite it before receive of the last bit is started, so that it has been rewritten before the transfer end interrupt of the last receive data.
Remark 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 15 - 42 Flowchart of Master Reception (in Continuous Reception Mode).
Remark 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Figure 15 - 42 Flowchart of Master Reception (in Continuous Reception Mode)
Starting SPI (CSI) communication
SAU initial setting
For the initial setting, refer to Figure 15 - 36. (Select buffer empty interrupt)
<1>
Setting storage area of the receive data, number of
communication data
Setting receive data
(Storage area, Reception data pointer, and number of communication data are optionally set on the internal RAM by
the software)
Enables interrupt
Clear interrupt request flag (xxIF), reset interrupt mask (xxMK) and set interrupt enable (EI)
<2>
Writing dummy data to SIOp (= SDRmn [7:0])
Writing to SIOp makes SCKp signals out (communication starts)
Main routine
Interrupt processing routine
Wait for receive completes <3><6>
Buffer empty/transfer end interrupt
BFFmn = 1?
Yes
<4>
Reading receive data from
SIOp (= SDRmn [7:0])
<7>
Subtract -1 from number of communication data
When interrupt is generated, it moves to interrupt processing routine
No
Read receive data, if any, then write them to storage area, and update receive data pointer (also subtract -1 from number of communication data)
= 0
Number of communication
data?
<5>
= 1
Clear MDmn0 bit to 0
2
<2>
Writing dummy data to SIOp (= SDRmn [7:0])
Main routine
No Set MDmn0 bit to 1
RETI
Number of communication data = 0 ? Yes
Yes Communication continued?
No Disable interrupt (MASK)
<8>
Set STmn bit to 1
End of communication
When number of communication data becomes 0, receive completes
Remark <1> to <8> in the figure correspond to <1> to <8> in Figure 15 - 41 Timing Chart of Master Reception (in Continuous Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0).
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.5.3 Master Transmission/Reception
Master transmission/reception is that the RL78 microcontroller outputs a transfer clock and transmits/receives data to/from other device.
3-Wire Serial SPI
CSI00
CSI01
CSI10
CSI11
CSI20
CSI21
CSI30
CSI31
Target channel
Channel 0 Channel 1 Channel 2 Channel 3 Channel 0 Channel 1 Channel 2 Channel 3
of SAU0
of SAU0
of SAU0
of SAU0
of SAU1
of SAU1
of SAU1
of SAU1
Pins used
SCK00,
SCK01,
SCK10,
SCK11,
SCK20,
SCK21,
SCK30,
SCK31,
SI00, SO00 SI01, SO01 SI10, SO10 SI11, SO11 SI20, SO20 SI21, SO21 SI30, SO30 SI31, SO31
Interrupt
INTCSI00 INTCSI01 INTCSI10 INTCSI11 INTCSI20 INTCSI21 INTCSI30 INTCSI31
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected.
Error detection flag Overrun error detection flag (OVFmn) only
Transfer data length
7 or 8 bits
Transfer rateNote
Max. fCLK /2 [Hz] (CSI00 only), fCLK /4 [Hz] Min. fCLK/(2 × 215 × 128)[Hz] fCLK: System clock frequency
Data phase
Selectable by the DAPmn bit of the SCRmn register · DAPmn = 0: Data I/O starts at the start of the operation of the serial clock. · DAPmn = 1: Data I/O starts half a clock cycle before the start of the serial clock operation.
Clock phase
Selectable by the CKPmn bit of the SCRmn register · CKPmn = 0: Non-reverse · CKPmn = 1: Reverse
Data direction
MSB or LSB first
Note
Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics specified in the electrical characteristics. For details, see CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(1) Register setting
Figure 15 - 43 Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial SPI (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31)
(a) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CKSmn CCSmn
STSmn
SISmn0
MDmn2 MDmn1 MDmn0
SMRmn 0/1
0
0
0
0
0
0
0
0
0
1
0
0
0
0 0/1
Operation clock (fMCK) of channel n 0: Prescaler output clock CKm0 set by the SPSm register 1: Prescaler output clock CKm1 set by the SPSm register
Interrupt source of channel n 0: Transfer end interrupt 1: Buffer empty interrupt
(b) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9
8
7
TXEmn RXEmn DAPmn CKPmn
EOCmn PTCmn1 PTCmn0 DIRmn
SCRmn 1
1 0/1 0/1 0
0
0
0 0/1
6
5
4
3
SLCmn1 SLCmn0
0
0
0
0
Selection of the data and clock phase (For details about the setting, see 15.3 Registers to Control the Serial Array Unit.)
Selection of data transfer sequence 0: Inputs/outputs data with MSB first 1: Inputs/outputs data with LSB first
2
1
0
DLSmn1 DLSmn0
1 1Note 0/1
Setting of data length 0: 7-bit data length 1: 8-bit data length
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOp)
15 14 13 12 11 10 9
8
Baud rate setting
SDRmn
(Operation clock (fMCK) division setting)
0
7
6
5
4
3
2
1
0
Transmit data setting/receive data register
SIOp
(d) Serial output register m (SOm) ... Set only the bit of the target channel.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CKOm3 CKOm2 CKOm1 CKOm0
SOm3 SOm2 SOm1 SOm0
SOm 0
0
0
0 0/1 0/1 0/1 0/1 0
0
0
0 0/1 0/1 0/1 0/1
Communication starts when a bit is 1 if the clock phase is nonreverse (the CKPmn bit of the SCRmn = 0). If the clock phase is reversed (CKPmn = 1), communication starts when a bit is 0.
(e) Serial output enable register m (SOEm) ... Set only the bit of the target channel to 1.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SOEm3 SOEm2 SOEm1 SOEm0
SOEm 0
0
0
0
0
0
0
0
0
0
0
0 0/1 0/1 0/1 0/1
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(f) Serial channel start register m (SSm) ... Set only the bit of the target channel to 1.
15 SSm 0
Note
14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SSm3 SSm2 SSm1 SSm0
0
0
0
0
0
0
0
0
0
0
0 0/1 0/1 0/1 0/1
Only provided for the SCR00 and SCR01 registers and the SCR10 and SCR11 registers of 80- to 128-pin products. This bit is fixed to 1 for the other registers.
Remark 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13
Remark 2. : Setting is fixed in the SPI (CSI) master transmission/reception mode, : Setting disabled (set to the initial value) 0/1: Set to 0 or 1 depending on the usage of the user
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(2) Operation procedure Figure 15 - 44 Initial Setting Procedure for Master Transmission/Reception
Starting initial setting Setting the PRR0 register Setting the PER0 register Setting the SPSm register Setting the SMRmn register Setting the SCRmn register Setting the SDRmn register Setting the SOm register
Changing setting of the SOEm register Setting port
Writing to the SSm register Completing initial setting
Release the serial array unit from the reset state.
Start clock supply to the serial array unit.
Set the operation clock.
Set an operation mode, etc.
Set a communication format.
Set a transfer baud rate (setting the transfer clock by dividing the operation clock (fMCK)).
Set the initial output level of the serial clock (CKOmn) and serial data (SOmn).
Set the SOEmn bit to 1 and enable data output of the target channel.
Enable data output and clock output of the target channel by setting a port register and a port mode register. Set the SSmn bit of the target channel to 1 (SEmn bit = 1: to enable operation). Initial setting is completed. Set transmit data to the SIOp register (bits 7 to 0 of the SDRmn register) and start.
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Figure 15 - 45 Procedure for Stopping Master Transmission/Reception
Starting setting to stop
(Selective) (Essential)
No TSFmn = 0?
Yes Writing the STm register
(Essential)
Changing setting of the SOEm register
(Selective)
Changing setting of the SOm register
(Selective) Setting the PER0 register
Setting the PRR0 register Stop setting is completed
If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait.)
Write 1 to the STmn bit of the target channel (stopping operation by setting SEmn = 0).
Set the SOEmn bit to 0 and stop the output of the target channel.
The levels of the serial clock (CKOmn) and serial data (SOmn) on the target channel can be changed if necessitated by an emergency.
Release the serial array unit from the reset state.
Start clock supply to the serial array unit.
After the stop setting is completed, go to the next processing.
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Figure 15 - 46 Procedure for Resuming Master Transmission/Reception
Starting setting for resumption
(Essential) (Essential)
Completing slave
No
preparations?
Yes
Port manipulation
(Selective) Changing setting of the SPSm register
(Selective) Changing setting of the SDRmn register
(Selective) Changing setting of the SMRmn register
(Selective) Changing setting of the SCRmn register
(Selective)
Clearing error flag
(Selective) Changing setting of the SOEm register
(Selective)
Changing setting of the SOm register
(Selective) Changing setting of the SOEm register
(Essential)
Port manipulation
(Essential) Writing to the SSm register
Completing resumption setting
Wait until stop the communication target (slave) or communication operation completed.
Disable data output and clock output of the target channel by setting a port register and a port mode register.
Re-set the register to change the operation clock setting.
Re-set the register to change the transfer baud rate setting (setting the transfer clock by dividing the operation clock (fMCK)).
Re-set the register to change serial mode register mn (SMRmn) setting.
Re-set the register to change serial communication operation setting register mn (SCRmn) setting.
If the OVF flag remains set, clear this using serial flag clear trigger register mn (SIRmn).
Set the SOEmn bit to 0 to stop output from the target channel.
Set the initial output level of the serial clock (CKOmn) and serial data (SOmn).
Set the SOEmn bit to 1 and enable output from the target channel.
Enable data output and clock output of the target channel by setting a port register and a port mode register.
Set the SSmn bit of the target channel to 1 and set the SEmn bit to 1 (to enable operation).
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(3) Processing flow (in single-transmission/reception mode)
Figure 15 - 47 Timing Chart of Master Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
SSmn STmn SEmn SDRmn
SCKp pin SIp pin Shift
register mn SOp pin INTCSIp
TSFmn
Transmit data 1 Write
Receive data 1 Reception & shift operation
Transmit data 1
Receive data 1 Transmit data 2
Write Read
Receive data 2
Reception& shift operation Transmit data 2
Receive data 2 Receive data 3
Transmit data 3
Write Read
Read
Receive data 3 Reception & shift operation
Transmit data 3
Data transmission /reception
Data transmission /reception
Data transmission /reception
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Figure 15 - 48 Flowchart of Master Transmission/Reception (in Single-Transmission/Reception Mode)
Main routine
Starting SPI (CSI) communication
SAU initial setting
Setting transmission/reception data
Enables interrupt
Writing transmit data to SIOp (= SDRmn [7:0])
Wait for transmission/ reception completes
Transfer end interrupt
For the initial setting, refer to Figure 15 - 44. (Select transfer end interrupt)
Setting storage data and number of data for transmission/reception data (Storage area, Transmission data pointer, Reception data pointer, and number of communication data are optionally set on the internal RAM by the software) Clear interrupt request flag (xxIF), reset interrupt mask (xxMK) and set interrupt enable (EI)
Read transmit data from storage area and write it to SIOp. Update transmit data pointer. Writing to SIOp makes SOp
and SCKp signals out (communication starts)
When transfer end interrupt is generated, it moves to interrupt processing routine.
Read receive data from SIOp (= SDRmn [7:0])
Read receive data then writes to storage area, update receive data pointer
RETI
No
Transmission/reception
completed?
Yes Disable interrupt (MASK)
Set STmn bit to 1
End of communication
If there are the next data, it continues
Interrupt processing routine
Main routine
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(4) Processing flow (in continuous transmission/reception mode)
Figure 15 - 49 Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
SSmn <1> STmn SEmn SDRmn
SCKp pin SIp pin Shift
register mn SOp pin INTCSIp
MDmn0 TSFmn BFFmn
Transmit data 1 Transmit data 2
Write
Write
Receive data 1 Transmit data 3
Write Read
<8>
Receive data 3 Receive data 2
Read
Read
Receive data 1 Reception & shift operation
Transmit data 1
Receive data 2 Reception & shift operation
Transmit data 2
Receive data 3 Reception & shift operation
Transmit data 3
Data transmission/reception
Data transmission/reception
Data transmission/reception <5>
<2><3> Note 1
<2> Note 2 <2>
<4> <2> Note 2 <2> <4>
<6> <7>
Note 1. Note 2.
If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn (SSRmn) is 1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten. The transmit data can be read by reading the SDRmn register during this period. Reading this register does not affect the transfer operation.
Caution
The MDmn0 bit of serial mode register mn (SSRmn) can be rewritten even during operation. However, rewrite it before transfer of the last bit is started, so that it has been rewritten before the transfer end interrupt of the last transmit data.
Remark 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 15 - 50 Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode).
Remark 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Figure 15 - 50 Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode)
Main routine
Starting setting
For the initial setting, refer to Figure 15 - 44.
SAU initial setting
(Select buffer empty interrupt)
<1>
Setting transmission/reception data
Setting storage data and number of data for transmission/reception data (Storage area, Transmission data pointer, Reception data, Number of communication data and Communication end flag are optionally set on the internal RAM by the software)
Enables interrupt
Clear interrupt request flag (xxIF), reset interrupt mask (xxMK) and set interrupt enable (EI)
Writing dummy data to
<2>
SIOp (= SDRmn [7:0])
<3><6>
Wait for transmission/ reception completes
Buffer empty/transfer end interrupt
Read transmit data from storage area and write it to SIOp. Update transmit data pointer.
Writing to SIOp makes Sop and SCKp signals out (communication starts)
When transmission/reception interrupt is generated, it moves to interrupt processing routine
BFFmn = 1?
No
Yes
<4>
Reading reception data to
SIOp (= SDRmn [7:0])
Except for initial interrupt, read data received
<7>
then write them to storage area, and update
Subtract -1 from number of
receive data pointer
communication data
If transmit data is left (number of communication data is
equal or greater than 2), read them from storage area
= 0
Number of
= 1
then write into SIOp, and update transmit data pointer.
communication data?
If it's waiting for the last data to receive (number of
2 <5>
communication data is equal to 1), change interrupt timing to communication end
Writing transmit data to SIOp (= SDRmn [7:0])
Clear MDmn0 bit to 0
Interrupt processing routine
RETI
No Set MDmn0 bit to 1
Number of communication data = 0?
Yes
Yes Continuing Communication? No Disable interrupt (MASK)
<8>
Set STmn bit to 1
End of communication
Main routine
Remark <1> to <8> in the figure correspond to <1> to <8> in Figure 15 - 49 Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0).
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.5.4 Slave Transmission
Slave transmission is that the RL78 microcontroller transmits data to another device in the state of a transfer clock being input from another device.
3-Wire Serial SPI
CSI00
CSI01
CSI10
CSI11
CSI20
CSI21
CSI30
CSI31
Target channel
Channel 0 Channel 1 Channel 2 Channel 3 Channel 0 Channel 1 Channel 2 Channel 3 of SAU0 of SAU0 of SAU0 of SAU0 of SAU1 of SAU1 of SAU1 of SAU1
Pins used
SCK00, SO00
SCK01, SO01
SCK10, SO10
SCK11, SO11
SCK20, SO20
SCK21, SO21
SCK30, SO30
SCK31, SO31
Interrupt
INTCSI00 INTCSI01 INTCSI10 INTCSI11 INTCSI20 INTCSI21 INTCSI30 INTCSI31
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected.
Error detection flag Overrun error detection flag (OVFmn) only
Transfer data length 7 or 8 bits
Transfer rate
Max. fMCK/6 [Hz]Notes 1, 2
Data phase
Selectable by the DAPmn bit of the SCRmn register · DAPmn = 0: Data output starts from the start of the operation of the serial clock. · DAPmn = 1: Data output starts half a clock cycle before the start of the serial clock operation.
Clock phase
Selectable by the CKPmn bit of the SCRmn register · CKPmn = 0: Non-reverse · CKPmn = 1: Reverse
Data direction
MSB or LSB first
Note 1. Note 2.
Because the external serial clock input to the SCK00, SCK01, SCK10, SCK11, SCK20, SCK21, SCK30, and SCK31 pins is sampled internally and used, the fastest transfer rate is fMCK/6 [Hz]. Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics specified in the electrical characteristics. For details, see CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
Remark 1. fMCK:Operation clock frequency of target channel fSCK: Serial clock frequency
Remark 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(1) Register setting
Figure 15 - 51 Example of Contents of Registers for Slave Transmission of 3-Wire Serial SPI (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31)
(a) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CKSmn CCSmn
STSmn
SISmn0
MDmn2 MDmn1 MDmn0
SMRmn
0/1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0/1
Operation clock (fMCK) of channel n 0: Prescaler output clock CKm0 set by the SPSm register 1: Prescaler output clock CKm1 set by the SPSm register
Interrupt source of channel n 0: Transfer end interrupt 1: Buffer empty interrupt
(b) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9
8
7
TXEmn RXEmn DAPmn CKPmn
EOCmn PTCmn1 PTCmn0 DIRmn
SCRmn 1
0 0/1 0/1 0
0
0
0 0/1
6
5
4
3
SLCmn1 SLCmn0
0
0
0
0
Selection of the data and clock phase (For details about the setting, see 15.3 Registers to Control the Serial Array Unit.)
Selection of data transfer sequence 0: Inputs/outputs data with MSB first 1: Inputs/outputs data with LSB first
2
1
0
DLSmn1 DLSmn0
1
1 0/1
Setting of data length 0: 7-bit data length 1: 8-bit data length
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOp)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0000000
SDRmn
Baud rate setting
0
Transmit data setting
SIOp
(d) Serial output register m (SOm) ... Set only the bit of the target channel.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CKOm3 CKOm2 CKOm1 CKOm0
SOm3 SOm2 SOm1 SOm0
SOm 0
0
0
0
×
×
×
×
0
0
0
0 0/1 0/1 0/1 0/1
(e) Serial output enable register m (SOEm) ... Set only the bit of the target channel to 1.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SOEm3 SOEm2 SOEm1 SOEm0
SOEm 0
0
0
0
0
0
0
0
0
0
0
0 0/1 0/1 0/1 0/1
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(f) Serial channel start register m (SSm) ... Set only the bit of the target channel to 1.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SSm3 SSm2 SSm1 SSm0
SSm 0
0
0
0
0
0
0
0
0
0
0
0 0/1 0/1 0/1 0/1
Remark 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13
Remark 2. : Setting is fixed in the SPI (CSI) slave transmission mode, : Setting disabled (set to the initial value) ×: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user
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RL78/G23 (2) Operation procedure
Figure 15 - 52 Initial Setting Procedure for Slave Transmission
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Starting initial setting
Setting the PRR0 register
Release the serial array unit from the reset state.
Setting the PER0 register
Start clock supply to the serial array unit.
Setting the SPSm register
Set the operation clock.
Setting the SMRmn register
Set an operation mode, etc.
Setting the SCRmn register
Set a communication format.
Setting the SDRmn register Setting the SOm register
Changing setting of the SOEm register
Setting port Writing to the SSm register
Completing initial setting
Set bits 15 to 9 to 0000000B for baud rate setting.
Set the initial output level of the serial data (SOmn).
Set the SOEmn bit to 1 and enable data output of the target channel.
Enable data output of the target channel by setting a port register and a port mode register.
Set the SSmn bit of the target channel to 1 (SEmn bit = 1: to enable operation).
Initial setting is completed. Set transmit data to the SIOp register (bits 7 to 0 of the SDRmn register) and wait for a clock from the master.
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RL78/G23 Figure 15 - 53 Procedure for Stopping Slave Transmission
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Starting setting to stop
(Selective) (Essential)
No TSFmn = 0?
Yes Writing the STm register
(Essential)
Changing setting of the SOEm register
(Selective)
Changing setting of the SOm register
(Selective) Setting the PER0 register
Setting the PRR0 register
Stop setting is completed
If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait.)
Write 1 to the STmn bit of the target channel (stopping operation by setting SEmn = 0).
Set the SOEmn bit to 0 and stop the output of the target channel.
The levels of the serial data (SOmn) on the target channel can be changed if necessitated by an emergency.
Stop clock supply to the serial array unit.
Reset the serial array unit.
After the stop setting is completed, go to the next processing.
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RL78/G23 Figure 15 - 54 Procedure for Resuming Slave Transmission
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Starting setting for resumption
(Essential) (Selective)
Completing master
No
preparations?
Yes
Port manipulation
(Selective) Changing setting of the SPSm register
(Selective) Changing setting of the SDRmn register
(Selective) Changing setting of the SMRmn register
(Selective) Changing setting of the SCRmn register
(Selective)
Clearing error flag
(Selective) Changing setting of the SOEm register
(Essential)
Changing setting of the SOm register
(Essential) Changing setting of the SOEm register
(Essential)
Port manipulation
(Essential) Writing to the SSm register
(Essential)
Starting communication
Completing resumption setting
Wait until stop the communication target (master) or operation completed.
Disable data output of the target channel by setting a port register and a port mode register.
Re-set the register to change the operation clock setting.
Re-set the register to change the transfer baud rate setting (setting the transfer clock by dividing the operation clock (fMCK)).
Re-set the register to change serial mode register mn (SMRmn) setting.
Re-set the register to change serial communication operation setting register mn (SCRmn) setting.
If the OVF flag remains set, clear this using serial flag clear trigger register mn (SIRmn).
Set the SOEmn bit to 0 to stop output from the target channel.
Set the initial output level of the serial data (SOmn).
Set the SOEmn bit to 1 and enable output from the target channel.
Enable data output of the target channel by setting a port register and a port mode register.
Set the SSmn bit of the target channel to 1 (SEmn = 1: to enable operation).
Sets transmit data to the SIOp register (bits 7 to 0 of the SDRmn register) and wait for a clock from the master.
Remark If PRR0 is rewritten while stopping the communication to reset the serial array unit, wait until the communication target (master) stops or communication finishes, and then perform initialization instead of restarting the communication.
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(3) Processing flow (in single-transmission mode) Figure 15 - 55 Timing Chart of Slave Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0)
SSmn STmn SEmn
SDRmn SCKp pin
SOp pin Shift
register mn INTCSIp
TSFmn
Transmit data 1 Transmit data 1 Shift operation
Data transmission
Transmit data 2 Transmit data 2
Shift operation
Data transmission
Transmit data 3 Transmit data 3 Shift operation
Data transmission
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Figure 15 - 56 Flowchart of Slave Transmission (in Single-Transmission Mode)
Starting SPI (CSI) communication
Main routine
Interrupt processing
routine
SAU initial setting
Setting transmit data Enables interrupt
Writing transmit data to SIOp (= SDRmn [7:0])
Wait for transmit completes
Transfer end interrupt
Yes Yes
RETI
Transmitting next data? No
Continuing transmit? No
Disable interrupt (MASK)
Set STmn bit to 1
End of communication
For the initial setting, refer to Figure 15 - 52. (Select transfer end interrupt)
Set storage area and the number of data for transmit data (Storage area, Transmission data pointer, and number of communication data are optionally set on the internal RAM by the software) Clear interrupt request flag (xxIF), reset interrupt mask (xxMK) and set interrupt enable (EI).
Read transmit data from storage area and write it to SIOp. Update transmit data pointer.
Start communication when master start providing the clock
When transmit end, interrupt is generated
Determine if it completes by counting number of communication data
Main routine
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(4) Processing flow (in continuous transmission mode)
Figure 15 - 57 Timing Chart of Slave Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0)
SSmn <1> STmn SEmn
SDRmn SCKp pin
SOp pin Shift
register mn INTCSIp
MDmn0 TSFmn BFFmn
Transmit data 1
Transmit data 2
Transmit data 1
Shift operation
Transmit data 2
Shift operation
Data transmission
Data transmission
<2> <3> <2> Note
<3> <2>
<6>
Transmit data 3
Transmit data 3
Shift operation
Data transmission <4>
<3>
<5>
Note
If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn (SSRmn) is 1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten.
Caution The MDmn0 bit of serial mode register mn (SSRmn) can be rewritten even during operation. However, rewrite it before transfer of the last bit is started.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Figure 15 - 58 Flowchart of Slave Transmission (in Continuous Transmission Mode)
Starting setting
Main routine
SAU initial setting <1>
Setting transmit data
Enables interrupt
<2>
Writing transmit data to SIOp (=SDRmn[7:0])
Wait for transmit completes <3><5>
Buffer empty/transfer end interrupt
Number of communication data 1?
Yes Reading transmit data
For the initial setting, refer to Figure 15 - 52. (Select buffer empty interrupt)
Set storage area and the number of data for transmit data (Storage area, Transmission data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software)
Clear interrupt request flag (xxIF), reset interrupt mask (xxMK) and set interrupt enable (EI)
Read transmit data from buffer and write it to SIOp. Update transmit data pointer
Start communication when master start providing the clock
When buffer empty/transfer end interrupt is generated, it moves to interrupt processing routine
If transmit data is left, read them from storage area
No
then write into SIOp, and update transmit data pointer.
If not, change the interrupt to transmission end
interrupt.
Writing transmit data to SIOp (= SDRmn [7:0])
Clear MDmn0 bit to 0
<4>
Interrupt processing routine
No Set MDmn0 bit to 1
Subtract -1 from number of communication data
RETI
Number of communication data = -1? Yes
Yes Communication continued?
No Disable interrupt (MASK)
<6>
Set STmn bit to 1
End of communication
It is determined as follows depending on the number of communication data.
+1: Transmission of data is completed 0: During the last data being transmitted -1: Transmission of all data is completed
Main routine
Remark <1> to <6> in the figure correspond to <1> to <6> in Figure 15 - 57 Timing Chart of Slave Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0).
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.5.5 Slave Reception
Slave reception is that the RL78 microcontroller receives data from another device in the state of a transfer clock being input from another device.
3-Wire Serial SPI
CSI00
CSI01
CSI10
CSI11
CSI20
CSI21
CSI30
CSI31
Target channel
Channel 0 Channel 1 Channel 2 Channel 3 Channel 0 Channel 1 Channel 2 Channel 3
of SAU0
of SAU0
of SAU0
of SAU0
of SAU1
of SAU1
of SAU1
of SAU1
Pins used
SCK00, SI00
SCK01, SI01
SCK10, SI10
SCK11, SI11
SCK20, SI20
SCK21, SI21
SCK30, SI30
SCK31, SI31
Interrupt
INTCSI00 INTCSI01 INTCSI10 INTCSI11 INTCSI20 INTCSI21 INTCSI30 INTCSI31
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error detection flag Overrun error detection flag (OVFmn) only
Transfer data length 7 or 8 bits
Transfer rate
Max. fMCK/6 [Hz]Notes 1, 2
Data phase
Selectable by the DAPmn bit of the SCRmn register · DAPmn = 0: Data input starts from the start of the operation of the serial clock. · DAPmn = 1: Data input starts half a clock cycle before the start of the serial clock operation.
Clock phase Data direction
Selectable by the CKPmn bit of the SCRmn register · CKPmn = 0: Non-reverse · CKPmn = 1: Reverse
MSB or LSB first
Note 1. Note 2.
Because the external serial clock input to the SCK00, SCK01, SCK10, SCK11, SCK20, SCK21, SCK30, and SCK31 pins is sampled internally and used, the fastest transfer rate is fMCK/6 [Hz]. Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics specified in the electrical characteristics. For details, see CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
Remark 1. fMCK:Operation clock frequency of target channel fSCK: Serial clock frequency
Remark 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(1) Register setting
Figure 15 - 59 Example of Contents of Registers for Slave Reception of 3-Wire Serial SPI (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31)
(a) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CKSmn CCSmn
STSmn
SISmn0
MDmn2 MDmn1 MDmn0
SMRmn
0/1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
Operation clock (fMCK) of channel n 0: Prescaler output clock CKm0 set by the SPSm register 1: Prescaler output clock CKm1 set by the SPSm register
Interrupt source of channel n 0: Transfer end interrupt
(b) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9
8
7
TXEmn RXEmn DAPmn CKPmn
EOCmn PTCmn1 PTCmn0 DIRmn
SCRmn 0
1 0/1 0/1 0
0
0
0 0/1
6
5
4
3
SLCmn1 SLCmn0
0
0
0
0
Selection of the data and clock phase (For details about the setting, see 15.3 Registers to Control the Serial Array Unit.)
Selection of data transfer sequence 0: Inputs/outputs data with MSB first 1: Inputs/outputs data with LSB first
2
1
0
DLSmn1 DLSmn0
1 1Note 0/1
Setting of data length 0: 7-bit data length 1: 8-bit data length
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOp)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0000000
SDRmn
Baud rate setting
0
Receive data
SIOp
(d) Serial output register m (SOm) ... This register is not used in this mode.
15 14 13 12 11 10 9
8
7
6
5
CKOm3 CKOm2 CKOm1 CKOm0
SOm 0
0
0
0
×
×
×
×
0
0
0
4
3
2
1
0
SOm3 SOm2 SOm1 SOm0
0
×
×
×
×
(e) Serial output enable register m (SOEm) ...This register is not used in this mode.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SOEm3 SOEm2 SOEm1 SOEm0
SOEm 0
0
0
0
0
0
0
0
0
0
0
0
×
×
×
×
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(f) Serial channel start register m (SSm) ... Set only the bit of the target channel to 1.
15 SSm 0
Note
14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SSm3 SSm2 SSm1 SSm0
0
0
0
0
0
0
0
0
0
0
0 0/1 0/1 0/1 0/1
Only provided for the SCR00 and SCR01 registers and the SCR10 and SCR11 registers of 80- to 128-pin products. This bit is fixed to 1 for the other registers.
Remark 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13
Remark 2. : Setting is fixed in the slave reception mode, : Setting disabled (set to the initial value) ×: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user
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RL78/G23 (2) Operation procedure
Figure 15 - 60 Initial Setting Procedure for Slave Reception
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Starting initial settings Setting the PRR0 register
Release the serial array unit from the reset state.
Setting the PER0 register
Start clock supply to the serial array unit.
Setting the SPSm register
Set the operation clock.
Setting the SMRmn register
Set an operation mode, etc.
Setting the SCRmn register
Set a communication format.
Setting the SDRmn register Setting port
Writing to the SSm register Completing initial setting
Set bits 15 to 9 to 0000000B for baud rate setting.
Enable data input and clock input of the target channel by setting a port register and a port mode register.
Set the SSmn bit of the target channel to 1 (SEmn bit = 1: to enable operation). Wait for a clock from the master.
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RL78/G23
Figure 15 - 61 Procedure for Stopping Slave Reception
Starting setting to stop
(Selective ) (Essential)
No TSFmn = 0?
Yes Writing the STm register
(Essential)
Changing setting of the SOEm register
(Selective) Setting the PER0 register
Setting the PRR0 register
Stop setting is completed
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait.) Write 1 to the STmn bit of the target channel (stopping operation by setting SEmn = 0). Set the SOEmn bit to 0 and stop the output of the target channel.
Stop clock supply to the serial array unit.
Reset the serial array unit. After the stop setting is completed, go to the next processing.
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RL78/G23 Figure 15 - 62 Procedure for Resuming Slave Reception
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Starting setting for resumption
(Essential) (Essential)
Completing master
No
preparations?
Yes
Port manipulation
(Selective) Changing setting of the SPSm register
Wait until stop the communication target (master) or operation completed.
Disable input of data and clock signal to the target channel by setting a port register and a port mode register.
Re-set the register to change the operation clock setting.
(Selective) Changing setting of the SMRmn register
Re-set the register to change serial mode register mn (SMRmn) setting.
(Selective) Changing setting of the SCRmn register
(Selective)
Clearing error flag
(Essential)
Port manipulation
(Essential) Writing to the SSm register
Completing resumption setting
Re-set the register to change serial communication operation setting register mn (SCRmn) setting.
If the OVF flag remains set, clear this using serial flag clear trigger register mn (SIRmn).
Enable clock output of the target channel by setting a port register and a port mode register.
Set the SSmn bit of the target channel to 1 (SEmn bit = 1: to enable operation). Wait for a clock from the master.
Remark If PRR0 is rewritten while stopping the communication to reset the serial array unit, wait until the communication target (master) stops or communication finishes, and then perform initialization instead of restarting the communication.
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(3) Processing flow (in single-reception mode)
Figure 15 - 63 Timing Chart of Slave Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
SSmn STmn SEmn SDRmn
SCKp pin SIp pin Shift
register mn INTCSIp
TSFmn
Receive data 1 Reception& shift operation
Receive data 1 Read
Receive data 3 Receive data 2
Read
Read
Receive data 2 Reception& shift operation
Receive data 3 Reception& shift operation
Data reception
Data reception
Data reception
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Figure 15 - 64 Flowchart of Slave Reception (in Single-Reception Mode)
Main routine
Interrupt processing routine
Starting SPI (CSI) communication
SAU initial setting
Preparation for reception Enables interrupt
Wait for receive completes
Transfer end interrupt
Reading receive data from SIOp (= SDRmn [7:0])
RETI No
Reception completed? Yes
Disable interrupt (MASK) Set STmn bit to 1
End of communication
For the initial setting, refer to Figure15 - 60. (Select transfer end interrupt)
Clear storage area setting and the number of receive data (Storage area, Reception data pointer, and number of communication data are optionally set on the internal RAM by the software) Clear interrupt request flag(xxIF), reset interrupt mask (xxMK) and set interrupt enable (EI).
Start communication when master start providing the clock When reception ends, an interrupt is generated.
Read receive data then writes to storage area, and counts up the number of receive data. Update receive data pointer.
Check completion of number of receive data
Main routine
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.5.6 Slave Transmission/Reception
Slave transmission/reception is that the RL78 microcontroller transmits/receives data to/from another device in the state of a transfer clock being input from another device.
3-Wire Serial SPI
CSI00
CSI01
CSI10
CSI11
CSI20
CSI21
CSI30
CSI31
Target channel
Channel 0 Channel 1 Channel 2 Channel 3 Channel 0 Channel 1 Channel 2 Channel 3 of SAU0 of SAU0 of SAU0 of SAU0 of SAU1 of SAU1 of SAU1 of SAU1
Pins used
SCK00,
SCK01,
SCK10,
SCK11,
SCK20,
SCK21,
SCK30,
SCK31,
SI00, SO00 SI01, SO01 SI10, SO10 SI11, SO11 SI20, SO20 SI21, SO21 SI30, SO30 SI31, SO31
Interrupt
INTCSI00 INTCSI01 INTCSI10 INTCSI11 INTCSI20 INTCSI21 INTCSI30 INTCSI31
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected.
Error detection flag Overrun error detection flag (OVFmn) only
Transfer data length 7 or 8 bits
Transfer rate
Max. fMCK/6 [Hz]Notes 1, 2
Data phase
Selectable by the DAPmn bit of the SCRmn register · DAPmn = 0: Data I/O starts at the start of the operation of the serial clock. · DAPmn = 1: Data I/O starts half a clock cycle before the start of the serial clock operation.
Clock phase
Selectable by the CKPmn bit of the SCRmn register · CKPmn = 0: Non-reverse · CKPmn = 1: Reverse
Data direction
MSB or LSB first
Note 1. Note 2.
Because the external serial clock input to the SCK00, SCK01, SCK10, SCK11, SCK20, SCK21, SCK30, and SCK31 pins is sampled internally and used, the fastest transfer rate is fMCK/6 [Hz]. Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics specified in the electrical characteristics. For details, see CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
Remark 1. fMCK:Operation clock frequency of target channel fSCK: Serial clock frequency
Remark 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(1) Register setting
Figure 15 - 65 Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial SPI (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31)
(a) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SMRmn
CKSmn 0/1
CCSmn 1
0
0
0
0
STSmn
SISmn0
0
0
0
0
1
0
MDmn2 MDmn1 MDmn0
0
0
0 0/1
Operation clock (fMCK) of channel n 0: Prescaler output clock CKm0 set by the SPSm register 1: Prescaler output clock CKm1 set by the SPSm register
Interrupt source of channel n 0: Transfer end interrupt 1: Buffer empty interrupt
(b) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9
8
7
TXEmn RXEmn DAPmn CKPmn
EOCmn PTCmn1 PTCmn0 DIRmn
SCRmn 1
1 0/1 0/1 0
0
0
0 0/1
6
5
4
3
SLCmn1 SLCmn0
0
0
0
0
Selection of the data and clock phase (For details about the setting, see 15.3 Registers to Control the Serial Array Unit.)
Selection of data transfer sequence 0: Inputs/outputs data with MSB first 1: Inputs/outputs data with LSB first
2
1
0
DLSmn1 DLSmn0
1 1Note 0/1
Setting of data length 0: 7-bit data length 1: 8-bit data length
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOp)
15 14 13 12 11 10 9
8
0000000
SDRmn
Baud rate setting
0
7
6
5
4
3
2
1
0
Transmit data setting/receive data register
SIOp
(d) Serial output register m (SOm) ... Set only the bit of the target channel.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CKOm3 CKOm2 CKOm1 CKOm0
SOm3 SOm2 SOm1 SOm0
SOm 0
0
0
0
×
×
×
×
0
0
0
0 0/1 0/1 0/1 0/1
(e) Serial output enable register m (SOEm) ... Set only the bit of the target channel to 1.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SOEm3 SOEm2 SOEm1 SOEm0
SOEm 0
0
0
0
0
0
0
0
0
0
0
0 0/1 0/1 0/1 0/1
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(f) Serial channel start register m (SSm) ... Set only the bit of the target channel to 1.
15 SSm 0
Note
14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SSm3 SSm2 SSm1 SSm0
0
0
0
0
0
0
0
0
0
0
0 0/1 0/1 0/1 0/1
Only provided for the SCR00 and SCR01 registers and the SCR10 and SCR11 registers of 80- to 128-pin products. This bit is fixed to 1 for the other registers.
Caution Be sure to set transmit data to the SlOp register before the clock from the master is started.
Remark 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13
Remark 2. : Setting is fixed in the SPI (CSI) slave transmission/reception mode, : Setting disabled (set to the initial value) ×: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(2) Operation procedure Figure 15 - 66 Initial Setting Procedure for Slave Transmission/Reception
Starting initial setting Setting the PRR0 register
Release the serial array unit from the reset state.
Setting the PER0 register
Start clock supply to the serial array unit.
Setting the SPSm register
Set the operation clock.
Setting the SMRmn register
Set an operation mode, etc.
Setting the SCRmn register
Set a communication format.
Setting the SDRmn register
Set bits 15 to 9 to 0000000B for baud rate setting.
Setting the SOm register
Set the initial output level of the serial data (SOmn).
Changing setting of the SOEm register
Set the SOEmn bit to 1 and enable data output of the target channel.
Setting port
Enable data output of the target channel by setting a port register and a port mode register.
Writing to the SSm register Completing initial setting
Set the SSmn bit of the target channel to 1 (SEmn bit = 1: to enable operation).
Initial setting is completed. Set transmit data to the SIOp register (bits 7 to 0 of the SDRmn register) and wait for a clock from the master.
Caution Be sure to set transmit data to the SlOp register before the clock from the master is started.
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Figure 15 - 67 Procedure for Stopping Slave Transmission/Reception
Starting setting to stop
(Selective ) (Essential)
No TSFmn = 0?
Yes Writing the STm register
(Essential)
Changing setting of the SOEm register
(Selective )
Changing setting of the SOm register
(Selective) Setting the PER0 register
Setting the PRR0 register
Stop setting is completed
If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait.)
Write 1 to the STmn bit of the target channel (stopping operation by setting SEmn = 0).
Set the SOEmn bit to 0 and stop the output of the target channel.
The levels of the serial data (SOmn) on the target channel can be changed if necessitated by an emergency.
Stop clock supply to the serial array unit.
Reset the serial array unit.
After the stop setting is completed, go to the next processing.
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Figure 15 - 68 Procedure for Resuming Slave Transmission/Reception
Starting setting for resumption
(Essential) (Essential)
Completing master
No
preparations?
Yes
Port manipulation
(Selective) Changing setting of the SPSm register
(Selective) Changing setting of the SMRmn register
(Selective) Changing setting of the SCRmn register
(Selective)
Clearing error flag
(Selective) Changing setting of the SOEm register
(Selective)
Changing setting of the SOm register
(Selective) Changing setting of the SOEm register
(Essential)
Port manipulation
(Essential) Writing to the SSm register
(Essential)
Starting communication
Completing resumption setting
Wait until stop the communication target (master) or operation completed.
Disable data output of the target channel by setting a port register and a port mode register.
Re-set the register to change the operation clock setting.
Re-set the register to change serial mode register mn (SMRmn) setting.
Re-set the register to change serial communication operation setting register mn (SCRmn) setting.
If the OVF flag remains set, clear this using serial flag clear trigger register mn (SIRmn).
Set the SOEmn bit to 0 to stop output from the target channel.
Set the initial output level of the serial data (SOmn).
Set the SOEmn bit to 1 and enable output from the target channel.
Enable data output of the target channel by setting a port register and a port mode register.
Set the SSmn bit of the target channel to 1 (SEmn = 1: to enable operation).
Sets transmit data to the SIOp register (bits 7 to 0 of the SDRmn register) and wait for a clock from the master.
Caution 1. Be sure to set transmit data to the SlOp register before the clock from the master is started. Caution 2. If PRR0 is rewritten while stopping the communication to reset the serial array unit, wait until the communication
target (master) stops or communication finishes, and then perform initialization instead of restarting the communication.
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(3) Processing flow (in single-transmission/reception mode)
Figure 15 - 69 Timing Chart of Slave Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
SSmn STmn SEmn SDRmn
SCKp pin SIp pin Shift
register mn SOp pin INTCSIp
TSFmn
Write
Transmit data 1
Receive data 1 Reception & shift operation
Transmit data 1
Receive data 1 Transmit data 2
Write Read
Receive data 2
Reception & shift operation Transmit data 2
Receive data 2
Receive data 3
Write Read
Transmit data 3
Read
Receive data 3 Reception & shift operation
Transmit data 3
Data transmission/reception
Data transmission/reception
Data transmission/reception
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Figure 15 - 70 Flowchart of Slave Transmission/Reception (in Single-Transmission/Reception Mode)
Starting SPI (CSI) communication
Main routine
SAU initial setting
Setting transmission/reception data
Enables interrupt
For the initial setting, refer to Figure15 - 66. (Select transfer end interrupt)
Setting storage area and number of data for transmission/reception data (Storage area, Transmission/reception data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software)
Clear interrupt request flag(xxIF), reset interrupt mask (xxMK) and set interrupt enable (EI).
Interrupt processing routine
Writing transmit data to SIOp (= SDRmn [7:0])
Wait for transmission/ reception completes
Transfer end interrupt
Reading receive data from SIOp (= SDRmn [7:0])
RETI
Read transmit data from storage area and write it to SIOp. Update transmit data pointer.
Start communication when master start providing the clock
When transfer end interrupt is generated, it moves to interrupt processing routine
Read receive data and write it to storage area. Update receive data pointer.
Main routine
No Yes
Transmission/reception completed?
Yes
Transmission/reception next data?
No Disable interrupt (MASK)
Set STmn bit to 1
End of communication
Update the number of communication data and confirm if next transmission/reception data is available
Caution Be sure to set transmit data to the SlOp register before the clock from the master is started.
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(4) Processing flow (in continuous transmission/reception mode)
Figure 15 - 71 Timing Chart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
SSmn <1> STmn SEmn SDRmn
SCKp pin SIp pin Shift
register mn SOp pin INTCSIp
MDmn0 TSFmn BFFmn
Transmit data1 Transmit data2
Write
Write
Receive data1 Transmit data 3
Write Read
<8>
Receive data 3 Receive data 2
Read
Read
Receive data 1 Reception & shift operation
Transmit data 1
Receive data 2
Reception& shift operation Transmit data 2
Receive data 3 Reception & shift operation
Transmit data 3
Data transmission /reception
Data transmission /reception Data transmission /reception <5>
<2> <3> Note 1
<2> Note 2 <3>
<4> <2>
<3> <4>
Note 2
<6> <7>
Note 1. Note 2.
If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn (SSRmn) is 1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten. The transmit data can be read by reading the SDRmn register during this period. At this time, the transfer operation is not affected.
Caution
The MDmn0 bit of serial mode register mn (SSRmn) can be rewritten even during operation. However, rewrite it before transfer of the last bit is started, so that it has been rewritten before the transfer end interrupt of the last transmit data.
Remark 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 15 - 72 Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode).
Remark 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Figure 15 - 72 Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode)
Main routine
Starting setting
For the initial setting, refer to Figure 15 - 66.
<1>
SAU initial setting
(Select buffer empty interrupt)
Setting transmission/reception data
Enables interrupt
<3><6>
Wait for transmission completes
Buffer empty/transfer end interrupt
Setting storage area and number of data for transmission/reception data (Storage area, Transmission/reception data pointer, and number of communication data are optionally set on the internal RAM by the software)
Clear interrupt request flag (xxIF), reset interrupt mask (xxMK) and set interrupt enable (EI)
Start communication when master start providing the clock
When buffer empty/transfer end interrupt is generated, it moves interrupt processing routine
BFFmn = 1?
No
Yes
<4> Read receive data from SIOp (= SDRmn [7:0])
<7>
Other than the first interrupt, read reception data then writes to storage area, update receive data
Subtract -1 from number of
pointer
communication data
If transmit data is left (number of communication data 2),
= 0
Number of communication data?
= 1
read it from the storage area and write it to SIOp. Update
storage pointer.
2
If transmit completion (number of communication data = 1),
<5>
Change the transmission completion interrupt
Writing transmit data to SIOp (= SDRmn [7:0])
Clear MDmn0 bit to 0
Interrupt processing routine
Main routine
No Set MDmn0 bit to 1
Yes
<8>
RETI
Number of communication data = 0? Yes
Communication continued? No
Disable interrupt (MASK)
Set STmn bit to 1
End of communication
Caution Be sure to set transmit data to the SlOp register before the clock from the master is started.
Remark <1> to <8> in the figure correspond to <1> to <8> in Figure 15 - 71 Timing Chart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0).
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.5.7 SNOOZE Mode Function
The SNOOZE mode makes the SPI (CSI) perform reception operations upon SCKp pin input detection while in the STOP mode. Normally the SPI (CSI) stops communication in the STOP mode. However, using the SNOOZE mode enables the SPI (CSI) to perform reception operations without CPU operation upon detection of the SCKp pin input. Only the following channels can be set to the SNOOZE mode. · 30- to 64-pin products: CSI00 · 80- to 128-pin products: CSI00, CSI20
When using the SPI (CSI) in SNOOZE mode, make the following setting before switching to the STOP mode (See Figure 15 - 74 Flowchart of SNOOZE Mode Operation (once startup) and Figure 15 - 76 Flowchart of SNOOZE Mode Operation (continuous startup).) · When using the SNOOZE mode function, set the SWCm bit of serial standby control register m (SSCm) to 1 just
before switching to the STOP mode. After the initial setting has been completed, set the SSm0 bit of serial channel start register m (SSm) to 1. · The CPU shifts to the SNOOZE mode on detecting the valid edge of the SCKp signal following a transition to the STOP mode. A CSIp starts reception on detecting input of the serial clock on the SCKp pin.
Caution 1. The SNOOZE mode can only be specified when the high-speed on-chip oscillator clock or mediumspeed on-chip oscillator clock is selected for fCLK.
Caution 2. The maximum transfer rate when using CSIp in the SNOOZE mode is 1 Mbps.
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(1) SNOOZE mode operation (once startup) Figure 15 - 73 Timing Chart of SNOOZE Mode Operation (once startup) (Type 1: DAPmn = 0, CKPmn = 0)
State of the CPU SS00
Normal operation STOP mode <4>
<3>
ST00 <1>
SE00
SWC0 SSEC0 L
Clock request signal (internal signal)
SDR00
SCK00 pin SI00 pin
Shift register 00 INTCSI00
TSF00
SNOOZE mode
<11> <9>
Normal operation
<10>
<8> ReadNote
Receive data 1
Receive data 2
Receive data 1 Reception & shift operation
Receive data 2 Reception & shift operation
Data reception
Data reception
<2>
<5><6>
<7>
Note
Only read received data while SWCm = 1 and before the next valid edge of the SCKp pin input is detected.
Caution 1. Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode finishes, set the STm0 bit to 1 (the SEm0 bit is cleared and the operation stops). After the receive operation completes, also clear the SWCm bit to 0 (SNOOZE mode release).
Caution 2. When SWCm = 1, the BFFm0 and OVFm0 flags will not change.
Remark 1. <1> to <11> in the figure correspond to <1> to <11> in Figure 15 - 74 Flowchart of SNOOZE Mode Operation (once startup).
Remark 2. 30- to 64-pin products: m = 0; p = 00 80- to 128-pin products: m = 0, 1; p = 00, 20
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RL78/G23 Figure 15 - 74 Flowchart of SNOOZE Mode Operation (once startup)
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Normal operation
SNOOZE operation
TSFmn = 0 for all channels?
Yes
<1>
Set STm0 bit to 1
SAU initial setting
<2>
Setting SSCm register (SWCm = 1, SSECm = 0)
<3>
Set SSm0 bit to 1
Enables interrupt processing
<4>
Entered the STOP mode
No
Stops operation by setting SEm0 = 0.
SMRm0, SCRm0: Communication setting SDRm0[15:9]: Setting 0000000B
Setting SNOOZE mode
Communications waiting state (SEm0 = 1) Clear interrupt request flag (xxIF), reset interrupt mask (xxMK) and enable interrupt processing. CPU/peripheral hardware clock fCLK supplied to the SAU is stopped.
STO P mode
SNOOZE mode
<5> <6> <7>
<8> <9> <10> <11>
Reading receive data from SIOp (= SDRmn [7:0]) Set STm0 bit to 1 Set SWCm bit to 1 Set SSm0 bit to 1 End of SNOOZE mode
The valid edge of the SCKp pin detected (Entered the SNOOZE mode) Input of the serial clock on the SCKp pin (CSIp receive operation)
Transfer interrupt (INTCSIp) is generated (CSIp reception is completed)
The mode switches from SNOOZE to normal operation.
Stops operation by setting SEm0 = 0.
Reset SNOOZE mode setting It becomes communication ready state (SEm0 = 1) under normal operation
Normal operation
Remark 1. <1> to <11> in the figure correspond to <1> to <11> in Figure 15 - 73 Timing Chart of SNOOZE Mode Operation (once startup) (Type 1: DAPmn = 0, CKPmn = 0).
Remark 2. 30- to 64-pin products: m = 0; p = 00 80- to 128-pin products: m = 0, 1; p = 00, 20
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(2) SNOOZE mode operation (continuous startup) Figure 15 - 75 Timing Chart of SNOOZE Mode Operation (continuous startup) (Type 1: DAPmn = 0, CKPmn = 0)
State of the CPU Normal operation STOP mode
SS00 ST00 <1> SE00
<3> <4>
SWC0
SSEC0 L
Clock request signal (internal signal)
SDR00
SCK00 pin SI00 pin
Shift register 00 INTCSI00
TSF00
SNOOZE mode
Normal operation STOP mode <4>
<3> <9>
<10>
Receive data 1 <8> Read Note
Receive data 1 Reception & shift operation
Data reception
SNOOZE mode
Receive data 2 Receive data 2 Reception & shift operation Data reception
<2>
<5><6>
<7>
<2>
<5> <6>
Note
Only read received data while SWCm = 1 and before the next valid edge of the SCKp pin input is detected.
Caution 1. Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode finishes, set the STm0 bit to 1 (the SEm0 bit is cleared and the operation stops). After the receive operation completes, also clear the SWCm bit to 0 (SNOOZE mode release).
Caution 2. When SWCm = 1, the BFFm0 and OVFm0 flags will not change.
Remark 1. <1> to <10> in the figure correspond to <1> to <10> in Figure 15 - 76 Flowchart of SNOOZE Mode Operation (continuous startup).
Remark 2. 30- to 64-pin products: m = 0; p = 00 80- to 128-pin products: m = 0, 1; p = 00, 20
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Figure 15 - 76 Flowchart of SNOOZE Mode Operation (continuous startup)
SNOOZE operation
No TSFmn = 0 for all channels?
Yes
<1>
Set STm0 bit to 1
Stops operation by setting SEm0 = 0.
Normal operation
SAU initial setting
SMRm0, SCRm0: Communication setting SDRm0[15:9]: Setting 0000000B
<2>
Setting SSCm register (SWCm = 1, SSECm = 0)
Setting SNOOZE mode
<3>
Set SSm0 bit to 1
Communications waiting state (SEm0 = 1)
Enables interrupt processing
Clear interrupt request flag (xxIF), reset interrupt mask (xxMK) and enable interrupt processing.
<4>
Entered the STOP mode
CPU/peripheral hardware clock fCLK supplied to the SAU is stopped.
SNOOZE mode STOP mode
<5> <6> <7>
<8> <9> <10>
Reading receive data from SIOp (= SDRmn [7:0])
Set STm0 bit to 1
Clear SWCm bit to 0
The valid edge of the SCKp pin detected (Entered the SNOOZE mode) Input of the serial clock on the SCKp pin (CSIp receive operation)
Transfer interrupt (INTCSIp) is generated (CSIp reception is completed)
The mode switches from SNOOZE to normal operation.
Reset SNOOZE mode setting
Normal operation
Remark 1. <1> to <10> in the figure correspond to <1> to <10> in Figure 15 - 75 Timing Chart of SNOOZE Mode Operation (continuous startup) (Type 1: DAPmn = 0, CKPmn = 0).
Remark 2. 30- to 64-pin products: m = 0; p = 00 80- to 128-pin products: m = 0, 1; p = 00, 20
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.5.8 Calculating Transfer Clock Frequency
The transfer clock frequency for 3-wire serial SPI (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) communication can be calculated by the following expressions.
(1) Master
(Transfer clock frequency) = {Operation clock (fMCK) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [Hz]
(2) Slave (Transfer clock frequency) = {Frequency of serial clock (SCK) supplied by master} Note[Hz]
Note
The permissible maximum transfer clock frequency is fMCK/6.
Remark
The value of SDRmn[15:9] is the value of bits 15 to 9 of serial data register mn (SDRmn) (0000000B to 1111111B) and therefore is 0 to 127.
The operation clock (fMCK) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial mode register mn (SMRmn).
Table 15 - 2 Selection of Operation Clock For 3-Wire Serial SPI (1/2)
SMRmn Register
SPSm Register
CKSmn
PRS PRS PRS PRS PRS PRS PRS PRS m13 m12 m11 m10 m03 m02 m01 m00
0
×
×
×
×
0
0
0
0 fCLK
×
×
×
×
0
0
0
1 fCLK/2
×
×
×
×
0
0
1
0 fCLK/22
×
×
×
×
0
0
1
1 fCLK/23
×
×
×
×
0
1
0
0 fCLK/24
×
×
×
×
0
1
0
1 fCLK/25
×
×
×
×
0
1
1
0 fCLK/26
×
×
×
×
0
1
1
1 fCLK/27
×
×
×
×
1
0
0
0 fCLK/28
×
×
×
×
1
0
0
1 fCLK/29
×
×
×
×
1
0
1
0 fCLK/210
×
×
×
×
1
0
1
1 fCLK/211
×
×
×
×
1
1
0
0 fCLK/212
×
×
×
×
1
1
0
1 fCLK/213
×
×
×
×
1
1
1
0 fCLK/214
×
×
×
×
1
1
1
1 fCLK/215
Operation Clock (fMCK)Note
fCLK = 32 MHz
32 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.25 kHz 15.63 kHz 7.81 kHz 3.91 kHz 1.95 kHz 977 Hz
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Table 15 - 2 Selection of Operation Clock For 3-Wire Serial SPI (2/2)
SMRmn Register
SPSm Register
Operation Clock (fMCK)Note
CKSmn
PRS PRS PRS PRS PRS PRS PRS PRS m13 m12 m11 m10 m03 m02 m01 m00
fCLK = 32 MHz
1
0
0
0
0
×
×
×
× fCLK
32 MHz
0
0
0
1
×
×
×
× fCLK/2
16 MHz
0
0
1
0
×
×
×
× fCLK/22
8 MHz
0
0
1
1
×
×
×
× fCLK/23
4 MHz
0
1
0
0
×
×
×
× fCLK/24
2 MHz
0
1
0
1
×
×
×
× fCLK/25
1 MHz
0
1
1
0
×
×
×
× fCLK/26
500 kHz
0
1
1
1
×
×
×
× fCLK/27
250 kHz
1
0
0
0
×
×
×
× fCLK/28
125 kHz
1
0
0
1
×
×
×
× fCLK/29
62.5 kHz
1
0
1
0
×
×
×
× fCLK/210
31.25 kHz
1
0
1
1
×
×
×
× fCLK/211
15.63 kHz
1
1
0
0
×
×
×
× fCLK/212
7.81 kHz
1
1
0
1
×
×
×
× fCLK/213
3.91 kHz
1
1
1
0
×
×
×
× fCLK/214
1.95 kHz
1
1
1
1
×
×
×
× fCLK/215
977 Hz
Note
Other than above
Setting prohibited
When changing the clock selected for fCLK (by changing the system clock control register (CKC) value), do so after having stopped (serial channel stop register m (STm) = 000FH) the operation of the serial array unit (SAU).
Remark 1. ×: Don't care Remark 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.5.9
Procedure for Processing Errors that Occurred During 3-wire Serial SPI (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) Communication
The procedure for processing errors that occurred during 3-wire serial SPI (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) communication is described in Figure 15 - 77.
Figure 15 - 77 Processing Procedure in Case of Overrun Error
Software Manipulation
State of the Hardware
Remark
Reads serial data register mn (SDRmn). Reads serial status register mn (SSRmn).
The BFFmn bit of the SSRmn register is set This is to prevent an overrun error if the
to 0 and channel n is enabled to receive next reception is completed during error
data
processing.
The error type is identified and the read value is used to clear the error flag.
Writes 1 to serial flag clear trigger register The error flag is cleared. mn (SIRmn).
The error only during reading can be cleared, by writing the value read from the SSRmn register to the SIRmn register without modification.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13
The serial data output (SO00, SO01) and serial clock output (SCK00, SCK01) of channels 0 and 1 of serial array unit 0 can be selected as input for the logic and event link controller (ELCL). When the serial data output and serial clock output signals are to be used for event input to the ELCL but not for output to the SO0m and SCK0m pins, set the corresponding bit in port function output enable register 0 (PFOE0) to 0. See 4.3.15 Port function output enable registers (PFOEx) for details.
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.6
Operation of UART (UART0 to UART3) Communication
This is a start-stop synchronization communication function using two lines: serial data transmission (TxD) and serial data reception (RxD) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party. Full-duplex asynchronous communication UART communication can be performed by using a channel dedicated to transmission (even-numbered channel) and a channel dedicated to reception (odd-numbered channel). The LIN-bus can be implemented by using UART2, timer array unit 0 (channel 7), and an external interrupt (INTP0).
[Data transmission/reception] · Data length of 7, 8, or 9 bits Note · MSB/LSB first selectable · Level setting of transmit/receive data (selecting whether to reverse the level) · Parity bit appending and parity check functions · Stop bit appending, stop bit check function [Interrupt function]
· Transfer end interrupt/buffer empty interrupt · Error interrupt in case of framing error, parity error, or overrun error [Error detection flag]
· Framing error, parity error, or overrun error
In addition, UART reception of following channels supports the SNOOZE mode. In the SNOOZE mode, data can be received without CPU processing upon detecting RxD input in the STOP mode. The SNOOZE mode is only available in the following UARTs, which support the reception baud rate adjustment function.
· 30- to 64-pin products: UART0 · 80- to 128-pin products: UART0, UART2
The LIN-bus is accepted in UART2 (channels 0 and 1 of unit 1) (30-pin to 128-pin products only).
[LIN-bus functions]
· Wakeup signal detection · Break field (BF) detection · Sync field measurement, baud rate calculation
Using the external interrupt (INTP0) and the timer array unit 0 (channel 7)
Note
Only the following UARTs support the 9-bit data length. · 30- to 64-pin products: UART0 · 80- to 128-pin products: UART0, UART2
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
When the medium-speed on-chip oscillator clock (fIM) or low-speed on-chip oscillator clock (fIL) is selected for fCLK, use the medium-speed on-chip oscillator trimming register (MIOTRM) or the low-speed on-chip oscillator trimming register (LIOTRM) to correct the accuracy of the oscillation frequency.
UART0 uses channels 0 and 1 of SAU0. UART1 uses channels 2 and 3 of SAU0. UART2 uses channels 0 and 1 of SAU1. UART3 uses channels 2 and 3 of SAU1.
<30- and 32-pin products>
Unit 0
1
Channel 0 1 2 3 0 1
Used as SPI (CSI) CSI00 -- -- CSI11 CSI20 --
Used as UART UART0
UART1
UART2 (supporting LIN-bus)
Used as Simplified I2C IIC00 -- -- IIC11 IIC20 --
<36-, 40-, and 44-pin products>
Unit 0
1
Channel 0 1 2 3 0 1
Used as SPI (CSI) CSI00 -- -- CSI11 CSI20 CSI21
Used as UART UART0
UART1
UART2 (supporting LIN-bus)
Used as Simplified I2C IIC00 -- -- IIC11 IIC20 IIC21
<48- and 52-pin products>
Unit 0
1
Channel 0 1 2 3 0 1
Used as SPI (CSI) CSI00 CSI01 -- CSI11 CSI20 CSI21
Used as UART UART0
UART1
UART2 (supporting LIN-bus)
Used as Simplified I2C IIC00 IIC01 -- IIC11 IIC20 IIC21
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<64-pin products>
Unit 0
1
Channel 0 1 2 3 0 1
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Used as SPI (CSI) CSI00 CSI01 CSI10 CSI11 CSI20 CSI21
Used as UART UART0
UART1
UART2 (supporting LIN-bus)
Used as Simplified I2C IIC00 IIC01 IIC10 IIC11 IIC20 IIC21
<80-, 100-, and 128-pin products>
Unit 0
1
Channel 0 1 2 3 0 1 2 3
Used as SPI (CSI) CSI00 CSI01 CSI10 CSI11 CSI20 CSI21 CSI30 CSI31
Used as UART UART0 UART1
UART2 (supporting LIN-bus) UART3
Used as Simplified I2C IIC00 IIC01 IIC10 IIC11 IIC20 IIC21 IIC30 IIC31
Select a single function for each channel. Only the selected function is possible. If UART0 is selected for channels 0 and 1 of unit 0, for example, the CSI00 and CSI01 functions cannot be used. At this time, however, channel 2 or 3 of the same unit can be used for a function other than UART0, such as CSI10, UART1, and IIC10.
Caution
When using a serial array unit for UART, both the transmitter side (even-numbered channel) and the receiver side (odd-numbered channel) can only be used for UART.
UART performs the following four types of communication operations.
· UART transmission
(See 15.6.1.)
· UART reception
(See 15.6.2.)
· LIN transmission (UART2 only) (See 15.7.1.)
· LIN reception (UART2 only) (See 15.7.2.)
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.6.1 UART Transmission
UART transmission is an operation to transmit data from the RL78 microcontroller to another device asynchronously (start-stop synchronization). Of two channels used for UART, the even channel is used for UART transmission.
UART Target channel Pins used Interrupt
Error detection flag Transfer data length Transfer rateNote 2 Data phase
Parity bit
UART0
UART1
UART2
UART3
Channel 0 of SAU0
Channel 2 of SAU0
Channel 0 of SAU1
Channel 2 of SAU1
TxD0
TxD1
TxD2
TxD3
INTST0
INTST1
INTST2
INTST3
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected.
None 7, 8, or 9 bits Note 1
Max. fMCK/6 [bps] (SDRmn[15:9] = 2 or more), Min. fCLK/ (2 × 215 × 128) [bps]
Non-reverse output (default: high level) Reverse output (default: low level)
The following selectable · No parity bit · Appending 0 parity · Appending even parity · Appending odd parity
Stop bit
The following selectable · Appending 1 bit · Appending 2 bit
Data direction
MSB or LSB first
Note 1. Note 2.
Only the following UARTs support the 9-bit data length. · 30- to 64-pin products: UART0 · 80- to 128-pin products: UART0, UART2 Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics specified in the electrical characteristics. For details, see CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
Remark 1. fMCK: Operation clock frequency of target channel fCLK: System clock frequency
Remark 2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), mn = 00, 02, 10, 12
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(1) Register setting
Figure 15 - 78 Example of Contents of Registers for UART Transmission of UART (UART0 to UART3) (1/2)
(a) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CKSmn CCSmn
MDmn2 MDmn1 MDmn0
SMRmn 0/1
0
0
0
0
0
0
0
0
0
1
0
0
0
1 0/1
Operation clock (fMCK) of channel n 0: Prescaler output clock CKm0 set by the SPSm register 1: Prescaler output clock CKm1 set by the SPSm register
Interrupt source of channel n 0: Transfer end interrupt 1: Buffer empty interrupt
(b) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9
8
7
TXEmn RXEmn DAPmn CKPmn
EOCmn PTCmn1 PTCmn0 DIRmn
SCRmn 1
0
0
0
0
0 0/1 0/1 0/1
6
5
4
3
SLCmn1 SLCmn0
0 0/1 0/1 0
2
1
0
DLSmn1 DLSmn0
1 0/1Note 1 0/1
Setting of parity bit 00B: No parity 01B: Appending 0 parity 10B: Appending Even parity 11B: Appending Odd parity
Selection of data transfer sequence 0: Inputs/outputs data with MSB
first 1: Inputs/outputs data with LSB
first.
Setting of stop bit 01B: Appending 1 bit 10B: Appending 2 bit
(c) Serial data register mn (SDRmn) (lower 8 bits: TxDq)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SDRmn
Baud rate setting
0Note 2
Transmit data setting
TxDq
(d) Serial output level register m (SOLm) ... Set only the bit of the target channel.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SOLm2
SOLm0
SOLm 0
0
0
0
0
0
0
0
0
0
0
0
0 0/1 0 0/1
Note 1. Note 2.
0: Non-reverse (normal) transmission
1: Reverse transmission
Only provided for the SCR00 register and the SCR10 register of the 80- to 128-pin products. This bit is fixed to 1 for the other registers. When UART0 performs 9-bit communication, bits 0 to 8 of the SDRm0 register are used as the transmission data specification area. Only the following UARTs support the 9-bit data length. · 30- to 64-pin products: UART0
· 80- to 128-pin products: UART0 and UART2
Remark 1. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), q: UART number (q = 0 to 3), mn = 00, 02, 10, 12
Remark 2. : Setting is fixed in the UART transmission mode, : Setting disabled (set to the initial value) 0/1: Set to 0 or 1 depending on the usage of the user
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Figure 15 - 78 Example of Contents of Registers for UART Transmission of UART (UART0 to UART3) (2/2)
(e) Serial output register m (SOm) ... Set only the bit of the target channel.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CKOm3 CKOm2 CKOm1 CKOm0
SOm3 SOm2 SOm1 SOm0
SOm 0
0
0
0
×
×
×
×
0
0
0
0
× 0/1Note × 0/1Note
0: Serial data output value is "0" 1: Serial data output value is "1"
(f) Serial output enable register m (SOEm) ... Set only the bit of the target channel to 1.
15 14 13 12 11 10 9
8
7
6
5
4
SOEm 0
0
0
0
0
0
0
0
0
0
0
0
3
2
1
0
SOEm3 SOEm2 SOEm1 SOEm0
× 0/1 × 0/1
(g) Serial channel start register m (SSm) ... Set only the bit of the target channel to 1.
15 14 13 12 11 10 9
8
7
6
5
4
SSm 0
0
0
0
0
0
0
0
0
0
0
0
3
SSm3
×
2
SSm2
0/1
1
SSm1
×
0
SSm0
0/1
Note
Before transmission is started, be sure to set to 1 when the SOLmn bit of the target channel is set to 0, and set to 0 when the SOLmn bit of the target channel is set to 1. The value varies depending on the communication data during communication operation.
Remark 1. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), mn = 00, 02, 10, 12
Remark 2. : Setting is fixed in the UART transmission mode, : Setting disabled (set to the initial value) 0/1: Set to 0 or 1 depending on the usage of the user
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RL78/G23 (2) Operation procedure
Figure 15 - 79 Initial Setting Procedure for UART Transmission
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Starting initial setting Setting the PRR0 register Setting the PER0 register Setting the SPSm register Setting the SMRmn register Setting the SCRmn register Setting the SDRmn register
Changing setting of the SOLm register
Setting the SOm register
Changing setting of the SOEm register
Setting port Writing to the SSm register
Completing initial setting
Release the serial array unit from the reset state.
Start clock supply to the serial array unit.
Set the operation clock.
Set an operation mode, etc.
Set a communication format.
Set a transfer baud rate (setting the transfer clock by dividing the operation clock (fMCK)).
Set an output data level.
Set the initial output level of the serial data (SOmn). Set the SOEmn bit to 1 and enable data output of the target channel. Enable data output of the target channel by setting a port register and a port mode register. Set the SSmn bit of the target channel to 1 and set the SEmn bit to 1 (to enable operation). Initial setting is completed. Set transmit data to the SDRmn [7:0] bits (TXDq register) (8 bits) or the SDRmn [8:0] bits (9 bits) and start communication.
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RL78/G23 Figure 15 - 80 Procedure for Stopping UART Transmission
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Starting setting to stop
No
(Selective )
TSFmn = 0?
(Essential)
Yes Writing the STm register
(Essential) Setting the SOEm register
(Selective )
Changing setting of the SOm register
(Selective) Setting the PER0 register
Setting the PRR0 register
Stop setting is completed
If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait.)
Write 1 to the STmn bit of the target channel (stopping operation by setting SEmn = 0).
Set the SOEmn bit to 0 and stop the output of the target channel.
The levels of the serial data (SOmn) on the target channel can be changed if necessitated by an emergency.
Stop clock supply to the serial array unit.
Reset the serial array unit.
After the stop setting is completed, go to the next processing.
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RL78/G23 Figure 15 - 81 Procedure for Resuming UART Transmission
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Starting setting for resumption
(Essential) (Selective)
No
Communication target is ready?
Yes
Port manipulation
(Selective) Changing setting of the SPSm register
(Selective) Changing setting of the SDRmn register
(Selective) Changing setting of the SMRmn register
(Selective) Changing setting of the SCRmn register
(Selective) Changing setting of the SOLm register
Wait until stop the communication target or communication operation completed
Disable data output of the target channel by setting a port mode register.
Re-set the register to change the operation clock setting.
Re-set the register to change the transfer baud rate setting (setting the transfer clock by dividing the operation clock (fMCK)).
Re-set the register to change serial mode register mn (SMRmn) setting.
Re-set the register to change the serial communication operation setting register mn (SCRmn) setting.
Re-set the register to change serial output level register m (SOLm) setting.
(Selective) Changing setting of the SOEm register
Clear the SOEmn bit to 0 and stop output.
(Selective)
Changing setting of the SOm register
Set the initial output level of the serial data (SOmn).
(Essential) Changing setting of the SOEm register
Set the SOEmn bit to 1 and enable output.
(Essential)
Port manipulation
Enable data output of the target channel by setting a port register and a port mode register.
(Essential) Writing to the SSm register
Completing resumption setting
Set the SSmn bit of the target channel to 1 and set the SEmn bit to 1 (to enable operation).
Setting is completed. Set transmit data to the SDRmn [7:0] bits (TXDq register) (8 bits) or the SDRmn [8:0] bits (9 bits) and start communication.
Remark If PRR0 is rewritten while stopping the communication to reset the serial array unit, wait until the communication target stops or communication finishes, and then perform initialization instead of restarting the communication.
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(3) Processing flow (in single-transmission mode) Figure 15 - 82 Timing Chart of UART Transmission (in Single-Transmission Mode)
SSmn STmn SEmn SDRmn
TxDq pin Shift
register mn INTSTq
TSFmn
Transmit data 1
ST
Transmit data 1
Shift operation
P SP ST
Transmit data 2
Transmit data 2 Shift operation
P SP ST
Transmit data 3
Transmit data 3 Shift operation
P SP
Data transmission
Data transmission
Data transmission
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), q: UART number (q = 0 to 3), mn = 00, 02, 10, 12
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Figure 15 - 83 Flowchart of UART Transmission (in Single-Transmission Mode)
Starting UART communication
Main routine
SAU initial setting
For the initial setting, refer to Figure 15 - 79. (Select transfer end interrupt)
Setting transmit data
Enables interrupt
Writing transmit data to the SDRmn [7:0] bits (TXDq register) (8 bits) or
the SDRmn [8:0] bits (9 bits)
Set data for transmission and the number of data. Clear communication end flag (Storage area, transmission data pointer, number of communication data and communication end flag are optionally set on the internal RAM by the software).
Clear interrupt request flag (xxIF), reset interrupt mask (xxMK) and set interrupt enable (EI).
Read transmit data from storage area and write it to TxDq. Update transmit data pointer.
Communication starts by writing to SDRmn [7:0].
Interrupt processing routine
Wait for transmit completes Transfer end interrupt
When Transfer end interrupt is generated, it moves to interrupt processing routine.
Transmitting next data?
Yes Writing transmit data to the SDRmn [7:0] bits (TXDq register) (8 bits) or
the SDRmn [8:0] bits (9 bits)
No Read transmit data, if any, from storage area and write it to TxDq. Update transmit data pointer. If not, set transmit end flag.
Sets communication completion flag
RETI
No Transmission completed? Yes Disable interrupt (MASK)
Check completion of transmission by verifying transmit end flag.
Set STmn bit to 1
End of communication
Main routine
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(4) Processing flow (in continuous transmission mode) Figure 15 - 84 Timing Chart of UART Transmission (in Continuous Transmission Mode)
SSmn <1> STmn SEmn SDRmn
TxDq pin Shift
register mn INTSTq
MDmn0
Transmit data 1
Transmit data 2
ST
Transmit data 1
Shift operation
P SP ST
Transmit data 3
Transmit data 2 Shift operation
P SP ST
Data transmission
Data transmission
TSFmn BFFmn
<2><3>
<2>
<3>
<2>
<3>
Note
Transmit data 3 Shift operation
Data transmission <4>
<6> P SP
<5>
Note
If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn (SSRmn) is 1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten.
Caution
The MDmn0 bit of serial mode register mn (SSRmn) can be rewritten even during operation. However, rewrite it before transfer of the last bit is started, so that it has been rewritten before the transfer end interrupt of the last transmit data.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), q: UART number (q = 0 to 3), mn = 00, 02, 10, 12
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Figure 15 - 85 Flowchart of UART Transmission (in Continuous Transmission Mode)
Main routine
Starting UART communication
<1>
SAU initial setting
For the initial setting, refer to Figure 15 - 79. (Select buffer empty interrupt)
Setting transmit data
Set the data pointer for transmission and the number of data items. Clear communication end flag (Storage area, Transmission data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software)
Enables interrupt
Clear interrupt request flag (xxIF), reset interrupt mask (xxMK) and set interrupt enable (EI).
Writing transmit data to the <2> SDRmn[7:0] bits (TXDq
register) (8 bits) or the SDRmn[8:0] bits (9 bits)
Read transmit data from storage area and write it to TXDq. Update transmit data pointer.
Transmission starts by writing to the SDRmn[7:0] bits (TXDq register) (8 bits) or the SDRmn[8:0] bits (9 bits).
Wait for transmit completes <3>
When transfer end interrupt is generated, it moves to interrupt processing routine.
Buffer empty/transfer end interrupt
Number of communication data > 0?
Yes Writing transmit data to the
SDRmn[7:0] bits <2> (TXDq register) (8 bits) or
the SDRmn[8:0] bits (9 bits)
Subtract -1 from number of communication data
If transmit data is left, read them from storage area then
No
write into TXDq, and update transmit data pointer and
number of transmit data.
If no more transmit data, clear MDmn0 bit if it's set. If not,
finish.
MDmn0 = 1?
Yes <4>
Clear MDmn0 bit to 0
No
<5>
Sets communication completion interrupt flag
No Write 1 to MDmn0bit
RETI
Transmission completed? Yes
Check completion of transmission by verifying transmit end flag
Interrupt processing routine
Main routine
Yes Communication continued?
No Disable interrupt (MASK)
<6>
Write 1 to STmn bit
End of communication
Remark <1> to <6> in the figure correspond to <1> to <6> in Figure 15 - 84 Timing Chart of UART Transmission (in Continuous Transmission Mode).
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.6.2 UART Reception
UART reception is an operation wherein the RL78 microcontroller asynchronously receives data from another device (start-stop synchronization). For UART reception, the odd-number channel of the two channels used for UART is used. The SMR register of both the odd- and even-numbered channels must be set.
UART
UART0
UART1
UART2
UART3
Target channel
Channel 1 of SAU0
Channel 3 of SAU0
Channel 1 of SAU1
Channel 3 of SAU1
Pins used
RxD0
RxD1
RxD2
RxD3
Interrupt
INTSR0
INTSR1
INTSR2
INTSR3
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error interrupt
INTSRE0
INTSRE1
INTSRE2
INTSRE3
Error detection flag
· Framing error detection flag (FEFmn) · Parity error detection flag (PEFmn) · Overrun error detection flag (OVFmn)
Transfer data length 7, 8, or 9 bits Note 1
Transfer rateNote 2
Max. fMCK/6 [bps] (SDRmn[15:9] = 2 or more), Min. fCLK/ (2 × 215 × 128) [bps]
Data phase
Non-reverse output (default: high level) Reverse output (default: low level)
Parity bit
The following selectable · No parity bit (no parity check) · No parity judgment (0 parity) · Even parity check · Odd parity check
Stop bit
Appending 1 bit
Data direction
MSB or LSB first
Note 1. Note 2.
Only the following UARTs support the 9-bit data length. · 30- to 64-pin products: UART0 only · 80- to 128-pin products: UART0 and UART2 only Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics specified in the electrical characteristics. For details, see CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
Remark 1. fMCK: Operation clock frequency of target channel fCLK: System clock frequency
Remark 2. m: Unit number (m = 0, 1), n: Channel number (n = 1, 3), mn = 01, 03, 11, 13
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(1) Register setting
Figure 15 - 86 Example of Contents of Registers for UART Reception of UART (UART0 to UART3) (1/2) (a) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CKSmn CCSmn
STSmn
SISmn0
MDmn2 MDmn1 MDmn0
SMRmn 0/1
0
0
0
0
0
0
1
0
0/1
1
0
0
0
1
0
Operation clock (fMCK) of channel n 0: Prescaler output clock Ckm0 set by the SPSm register 1: Prescaler output clock CKm1 set by the SPSm register
0: Normal reception
1: Reverse reception
Operation mode of channel n 0: Transfer end interrupt
(b) Serial mode register mr (SMRmr)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CKSmr CCSmr
MDmr2 MDmr1 MDmr0
SMRmr 0/1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
Same setting value as CKSmn bit
Operation mode of channel r 0: Transfer end interrupt
(c) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9
8
7
TXEmn RXEmn DAPmn CKPmn
EOCmn PTCmn1 PTCmn0 DIRmn
SCRmn 0
1
0
0
0 0/1 0/1 0/1 0/1
6
5
4
3
SLCmn1 SLCmn0
0
0
1
0
Setting of parity bit 00B: No parity check 01B: No parity judgment 10B: Even parity check 11B: Odd parity check
Selection of data transfer sequence 0: Inputs/outputs data with MSB
first 1: Inputs/outputs data with LSB
first.
2
1
0
DLSmn1 DLSmn0
1 0/1Note 1 0/1
Setting of data length
(d) Serial data register mn (SDRmn) (lower 8 bits: RxDq)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SDRmn
Baud rate setting
0Note 2
Receive data register
RxDq
Note 1. Note 2.
Only provided for the SCR01 register and the SCR11 register of the 80- to 128-pin products. This bit is fixed to 1 for the other registers. When UART performs 9-bit communication, bits 0 to 8 of the SDRm1 register are used as the reception data specification area. Only the following UARTs support the 9-bit data length. · 30- to 64-pin products: UART0
· 80- to 128-pin products: UART0, UART2
Caution For the UART reception, be sure to set the SMRmr register of channel r to UART transmission mode that is to be paired with channel n.
Remark 1. m: Unit number (m = 0, 1), n: Channel number (n = 1, 3), mn = 01, 03, 11, 13 r: Channel number (r = n 1), q: UART number (q = 0 to 3)
Remark 2. : Setting is fixed in the UART reception mode, : Setting disabled (set to the initial value) 0/1: Set to 0 or 1 depending on the usage of the user
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Figure 15 - 86 Example of Contents of Registers for UART Reception of UART (UART0 to UART3) (2/2)
(e) Serial output register m (SOm) ... This register is not used in this mode.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CKOm3 CKOm2 CKOm1 CKOm0
SOm3 SOm2 SOm1 SOm0
SOm 0
0
0
0
×
×
×
×
0
0
0
0
×
×
×
×
(f) Serial output enable register m (SOEm) ...This register is not used in this mode.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SOEm3 SOEm2 SOEm1 SOEm0
SOEm 0
0
0
0
0
0
0
0
0
0
0
0
×
×
×
×
(g) Serial channel start register m (SSm) ... Set only the bit of the target channel to 1.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SSm3 SSm2 SSm1 SSm0
SSm 0
0
0
0
0
0
0
0
0
0
0
0 0/1 × 0/1 ×
Remark 1. m: Unit number (m = 0, 1) Remark 2. : Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user
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RL78/G23 (2) Operation procedure
Figure 15 - 87 Initial Setting Procedure for UART Reception
Starting initial setting
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Setting the PRR0 register
Release the serial array unit from the reset state.
Setting the PER0 register
Start clock supply to the serial array unit.
Setting the SPSm register
Set the operation clock.
Setting the SMRmn and SMRmr registers
Set an operation mode, etc.
Setting the SCRmn register
Set a communication format.
Setting the SDRmn register
Set a transfer baud rate (setting the transfer clock by dividing the operation clock (fMCK)).
Setting port Writing to the SSm register
Enable data input of the target channel by setting a port register and a port mode register.
Set the SSmn bit of the target channel to 1 and set the SEmn bit to 1 (to enable operation). Become wait for start bit detection.
Completing initial setting
Caution Set the RXEmn bit of SCRmn register to 1, and then be sure to set SSmn to 1 after at least 4 fMCK clock cycles have elapsed.
Figure 15 - 88 Procedure for Stopping UART Reception
Starting setting to stop
(Selective) (Essential)
No TSFmn = 0?
Yes Writing the STm register
(Selective) Setting the PER0 register
Setting the PRR0 register
Completing initial setting
If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait).
Write 1 to the STmn bit of the target channel (stopping operation by setting SEmn = 0).
Stop clock supply to the serial array unit.
Reset the serial array unit.
After the stop setting is completed, go to the next processing.
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RL78/G23 Figure 15 - 89 Procedure for Resuming UART Reception
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Starting setting for resumption
(Essential)
Communication
No
target is ready?
Yes
(Selective) Changing setting of the SPSm register
Wait until the communication target stops or communication operation is completed.
Re-set the register to change the operation clock setting.
(Selective) Changing setting of the SDRmn
(Selective)
Changing setting of the SMRmn and SMRmr registers
Re-set the register to change the transfer baud rate setting (setting the transfer clock by dividing the operation clock (fMCK)).
Re-set the registers to change serial mode registers mn, mr (SMRmn, SMRmr) setting.
(Selective)
Changing setting of the SCRmn register
(Selective)
Clearing error flag
(Essential)
Setting port
(Essential) Writing to the SSm register
Completing resumption setting
Re-set the register to change serial communication operation setting register mn (SCRmn) setting.
If the FEF, PEF, and OVF flags remain set, clear them using serial flag clear trigger register mn (SIRmn).
Enable data input of the target channel by setting a port register and a port mode register.
Set the SSmn bit of the target channel to 1 and set the SEmn bit to 1 (to enable operation). Become wait for start bit detection.
Caution Set the RXEmn bit of SCRmn register to 1, and then be sure to set SSmn to 1 after at least 4 fMCK clocks have elapsed.
Remark If PRR0 is rewritten while stopping the communication to reset the serial array unit, wait until the communication target stops or communication finishes, and then perform initialization instead of restarting the communication.
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RL78/G23 (3) Processing flow
Figure 15 - 90 Timing Chart of UART Reception
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
SSmn STmn SEmn SDRmn
RxDq pin Shift
register mn INTSRq
TSFmn
ST
Receive data 1
Shift operation
Receive data 1
P SP ST
Receive data 2 Shift operation
P SP ST
Receive data 3 Receive data 2
Receive data 3
P SP
Shift operation
Data reception
Data reception
Data reception
Remark m: Unit number (m = 0, 1), n: Channel number (n = 1, 3), mn = 01, 03, 11, 13 r: Channel number (r = n 1), q: UART number (q = 0 to 3)
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RL78/G23 Figure 15 - 91 Flowchart of UART Reception
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Main routine
Starting UART communication
SAU initial setting
For the initial setting, refer to Figure 15 - 87. (setting to mask for error interrupt)
Setting receive data Enables interrupt
Setting storage area of the receive data, number of communication data (storage area, reception data pointer, number of communication data are optionally set on the internal RAM by the software)
Clear interrupt request flag (xxIF), reset interrupt mask (xxMK) and set interrupt enable (EI)
Wait for receive completes
Transfer end interrupt Reading receive data from
the SDRmn[7:0] bits (RxDq register) (8 bits) or the SDRmn[8:0] bits (9 bits) Indicating normal reception?
Yes RETI
Starting reception if start bit is detected When receive complete, transfer end interrupt is generated.
Read receive data then writes to storage area. Update receive data pointer and number of communication data.
No
Error processing
No Reception completed?
Yes
Interrupt (mask)
Check the number of communication data, determine the completion of reception
Interrupt processing routine
Main routine
Writing 1 to the STmn bit End of UART
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.6.3 SNOOZE Mode Function
The SNOOZE mode makes the UART perform reception operations upon RxDq pin input detection while in the STOP mode. Normally the UART stops communication in the STOP mode. However, using the SNOOZE mode enables the UART to perform reception operations without CPU operation. Only the following channels can be set to the SNOOZE mode. · 30- to 64-pin products: UART0 · 80- to 128-pin products: UART0, UART2
When using UARTq in the SNOOZE mode, make the following settings before entering the STOP mode. (See Figure 15 - 94 Flowchart of SNOOZE Mode Operation (EOCm1 = 0, SSECm = 0/1 or EOCm1 = 1, SSECm = 0) and Figure 15 - 96 Flowchart of SNOOZE Mode Operation (EOCm1 = 1, SSECm = 1).) · In the SNOOZE mode, the baud rate setting for UART reception needs to be changed to a value different from that in
normal operation. Set the SPSm register and bits 15 to 9 of the SDRmn register with reference to Table 15 - 3. · Set the EOCmn and SSECmn bits. This is for enabling or stopping generation of an error interrupt (INTSRE0) when a
communication error occurs. · When using the SNOOZE mode function, set the SWCm bit of serial standby control register m (SSCm) to 1 just
before switching to the STOP mode. After the initial setting has been completed, set the SSm1 bit of serial channel start register m (SSm) to 1. · A UARTq starts reception in SNOOZE mode on detecting input of the start bit on the RxDq pin following a transition of the CPU to the STOP mode.
Caution 1. The SNOOZE mode can only be used when the high-speed on-chip oscillator clock or medium-speed on-chip oscillator clock is selected for fCLK. When the medium-speed on-chip oscillator clock is selected, use the medium-speed on-chip oscillator trimming register (MIOTRM) to correct the accuracy of the oscillation frequency.
<R> Caution 2. The maximum transfer rate in the SNOOZE mode is 115.2 kbps (when setting FWKUP = 1, fCLK = fIH (32 MHz)). When FWKUP is set to 1, fCLK cannot be set to a value other than fIH = 32 MHz.
Caution 3. When SWCm = 1, UARTq can be used only when the reception operation is started in the STOP mode. When used simultaneously with another SNOOZE mode function or interrupt, if the reception operation is started in a state other than the STOP mode, such as those given below, data may not be received correctly and a framing error or parity error may be generated. · When after the SWCm bit has been set to 1, the reception operation is started before the STOP mode is entered · When the reception operation is started while another function is in the SNOOZE mode · When after returning from the STOP mode to normal operation due to an interrupt or other cause, the reception operation is started before the SWCm bit is returned to 0
Caution 4. If a parity error, framing error, or overrun error occurs while the SSECm bit is set to 1, the PEFmn, FEFmn, or OVFmn flag is not set and an error interrupt (INTSREq) is not generated. Therefore, when the setting of SSECm = 1 is made, clear the PEFmn, FEFmn, and OVFmn flags before setting the SWC0 bit to 1 and read the value in bits 7 to 0 (RxDq register) of the SDRm1 register.
Caution 5. The CPU shifts from the STOP mode to the SNOOZE mode on detecting the valid edge of the RxDq signal. Note, however, that transfer through the UART channel may not start and the CPU may remain in the SNOOZE mode if an input pulse on the RxDq pin is too short to be detected as a start bit. In such cases, data may not be received correctly, and this may lead to a framing error or parity error in the next UART transfer.
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Table 15 - 3 Baud Rate Setting for UART Reception in SNOOZE Mode
High-speed On-chip Oscillator (fIH)
Operation Clock (fMCK)
Baud Rate for UART Reception in SNOOZE Mode
Baud Rate of 4800 bps
SDRmn [15:9]
Maximum Permissible Value
Minimum Permissible Value
32 MHz±1.0%Note
fCLK/25
105
2.27%
-1.53%
24 MHz±1.0%Note
fCLK/25
79
1.60%
-2.18%
16 MHz±1.0%Note
fCLK/24
105
2.27%
-1.53%
12 MHz±1.0%Note
fCLK/24
79
1.60%
-2.19%
8 MHz±1.0%Note
fCLK/23
105
2.27%
-1.53%
6 MHz±1.0%Note
fCLK/23
79
1.60%
-2.19%
4 MHz±1.0%Note
fCLK/22
105
2.27%
-1.53%
3 MHz±1.0%Note
fCLK/22
79
1.60%
-2.19%
2 MHz±1.0%Note
fCLK/2
105
2.27%
-1.54%
1 MHz±1.0%Note
fCLK
105
2.27%
-1.57%
Note
When the accuracy of the clock frequency of the high-speed on-chip oscillator is ±1.5% or ±2.0%, the permissible range becomes smaller as shown below. · In the case of fIH ±1.5%, perform (Maximum permissible value 0.5%) and (Minimum permissible value + 0.5%) to the
values in the above table. · In the case of fIH ±2.0%, perform (Maximum permissible value 1.0%) and (Minimum permissible value + 1.0%) to the
values in the above table.
Remark
The maximum permissible value and minimum permissible value are permissible values for the baud rate in UART reception. The baud rate on the transmitting side should be set to fall inside this range.
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(1) SNOOZE mode operation (EOCm1 = 0, SSECm = 0/1) Because of the setting of EOCm1 = 0, even though a communication error occurs, an error interrupt (INTSREq) is not generated, regardless of the setting of the SSECm bit. A transfer end interrupt (INTSRq) will be generated.
Figure 15 - 92 Timing Chart of SNOOZE Mode Operation (EOCm1 = 0, SSECm = 0/1)
State of the CPU Normal operation STOP mode
SS 01
<4 > <3>
ST 01 <1>
SE 01
SWC0
EOC 01 L
SSEC 0 L
Clock request signal (internal signal )
SNOOZE mode
<10>
<12>
<11 >
SDR01 RxD0 pin
ST
Receive data 1
<9> Read Note P SP
Shift register 01 INTSR0
INTSRE0 L TSF01 <2>
Shift operation
Data reception <7>
<6 >
<5>
<8>
Normal operation
Receive data 1
Receive data 2
ST
Receive data 2
P SP
Shift operation
Data reception
Note
Read the received data when SWCm = 1.
Caution
Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode finishes, set the STm1 bit to 1 (the SEm1 bit is cleared and the operation stops). After the receive operation completes, also clear the SWCm bit to 0 (SNOOZE mode release).
Remark 1. <1> to <12> in the figure correspond to <1> to <12> in Figure 15 - 94 Flowchart of SNOOZE Mode Operation (EOCm1 = 0, SSECm = 0/1 or EOCm1 = 1, SSECm = 0).
Remark 2. 30- to 64-pin products: m = 0; q = 0 80- to 128-pin products: m = 0, 1; q = 0, 2
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(2) SNOOZE mode operation (EOCm1 = 1, SSECm = 0: Error interrupt (INTSREq) generation is enabled) Because EOCm1 = 1 and SSECm = 0, an error interrupt (INTSREq) is generated when a communication error occurs.
Figure 15 - 93 Timing Chart of SNOOZE Mode Operation (EOCm1 = 1, SSECm = 0)
State of the CPU Normal operation STOP mode
SS01
<4> <3>
ST01 <1>
SE01
SWC0
EOC01 SSEC0 L
SNOOZE mode
<10>
<12>
<11>
Clock request signal (internal signal) SDR01
RxD0 pin Shift
register 01 INTSR0
INTSRE0 L
TSF01
<2>
ST
Receive data 1
Shift operation
<9> ReadNote P SP
Data reception <7>
<6>
<5>
<8>
Normal operation
Receive data 1
Receive data 2
ST
Receive data 2
Shift operation
P SP
Data reception
Note
Read the received data when SWCm = 1.
Caution
Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode finishes, set the STm1 bit to 1 (the SEm1 bit is cleared and the operation stops). After the receive operation completes, also clear the SWCm bit to 0 (SNOOZE mode release).
Remark 1. <1> to <12> in the figure correspond to <1> to <12> in Figure 15 - 94 Flowchart of SNOOZE Mode Operation (EOCm1 = 0, SSECm = 0/1 or EOCm1 = 1, SSECm = 0).
Remark 2. 30- to 64-pin products: m = 0; q = 0 80- to 128-pin products: m = 0, 1; q = 0, 2
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RL78/G23
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Figure 15 - 94 Flowchart of SNOOZE Mode Operation (EOCm1 = 0, SSECm = 0/1 or EOCm1 = 1, SSECm = 0)
Normal operation
SNOOZE mode STOP mode
Setting start
Does TSFmn = 0 on all channels?
Yes
<1>
Writing 1 to the STmn bit
SEmn = 0
SAU initial setting
<2>
Setting SSCm register
(SWCm = 1)
<3>
Writing 1 to the SSmn bit
SEm1 = 1
Enable interrupt
<4>
Entered the STOP mode
No
The operation of all channels is also stopped to switch to the STOP mode.
Channel 1 is specified for UART reception. Change to the UART reception baud rate in SNOOZE mode (SPSm register and bits 15 to 9 in SDRm1 register). SNOOZE mode setting
Communications waiting state
Clear interrupt request flag (xxIF), reset interrupt mask (xxMK) and set interrupt enable (IE). fCLK supplied to the SAU is stopped.
<5> <6>
<7> <8>
INTSREq
INTSRq
Reading receive data from the SDRmn[7:0] bits (RXDq
register) (8 bits) or the SDRmn[8:0] bits (9 bits)
<9> Reading receive data from the SDRmn[7:0] bits (RXDq register) (8 bits) or the SDRmn[8:0] bits (9 bits)
Writing 1 to the STm1 bit
<10> Writing 1 to the STm1 bit
Clear the SWCm bit to 0
<11> Clear the SWCm bit to 0
The valid edge of the RxDq pin detected (Entered the SNOOZE mode) Input of the start bit on the RxDq pin detected (UARTq receive operation)
Transfer end interrupt (INTSRq) or error interrupt (INTSREq) generated
The mode switches from SNOOZE to normal operation.
Stops operation by setting SEm1 = 0. Reset SNOOZE mode setting.
Error processing
Change to the UART reception baud rate in
normal operation
Writing 1 to the SSmn bit
<12>
Change to the UART reception baud rate in
normal operation
Writing 1 to the SSmn bit
Set the SPSm register and bits 15 to 9 in the SDRm1 register.
Communications waiting state (SEmn = 1)
Normal operation
Normal operation
Normal operation
Remark 1. <1> to <12> in the figure correspond to <1> to <12> in Figure 15 - 92 Timing Chart of SNOOZE Mode Operation (EOCm1 = 0, SSECm = 0/1) and Figure 15 - 93 Timing Chart of SNOOZE Mode Operation (EOCm1 = 1, SSECm = 0).
Remark 2. 30- to 64-pin products: m = 0; q = 0; n = 0 to 3 80- to 128-pin products: m = 0, 1; q = 0, 2; n = 0 to 3
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(3) SNOOZE mode operation (EOCm1 = 1, SSECm = 1: Error interrupt (INTSREq) generation is stopped) Because EOCm1 = 1 and SSECm = 1, an error interrupt (INTSREq) is not generated when a communication error occurs.
Figure 15 - 95 Timing Chart of SNOOZE Mode Operation (EOCm1 = 1, SSECm = 1)
State of the CPU Normal operation STOP mode
SS01
<4> <3>
ST01 <1>
SE01
SWC0
EOC01
SSEC0
Clock request signal (internal signal)
SDR01
SNOOZE mode
RxD0 pin Shift register 01
INTSR0 INTSRE0 L
TSF01 <2>
ST
Receive data 1
Shift operation
Data reception <6> <5>
Note
Read the received data when SWCm = 1.
STOP mode
Normal operation SNOOZE mode
<10>
<11> <11>
P SP <7>
Receive data 1
Receive data 2 Read Note <9>
ST
Receive data 2
Shift operation
P SP
Data reception <6> <5>
<7>, <11> <8>
Caution 1. Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode finishes, set the STm1 bit to 1 (the SEm1 bit is cleared and the operation stops). After the receive operation completes, also clear the SWCm bit to 0 (SNOOZE mode release).
Caution 2. If a parity error, framing error, or overrun error occurs while the SSECm bit is set to 1, the PEFm1, FEFm1, or OVFm1 flag is not set and an error interrupt (INTSREq) is not generated. Therefore, when the setting of SSECm = 1 is made, clear the PEFm1, FEFm1, and OVFm1 flags before setting the SWCm bit to 1 and read the value in SDRm1[7:0] (RxDq register) (8 bits) or SDRm1[8:0] (9 bits).
Remark 1. <1> to <11> in the figure correspond to <1> to <11> in Figure 15 - 96 Flowchart of SNOOZE Mode Operation (EOCm1 = 1, SSECm = 1).
Remark 2. 30- to 64-pin products: m = 0; q = 0 80- to 128-pin products: m = 0, 1; q = 0, 2
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Figure 15 - 96 Flowchart of SNOOZE Mode Operation (EOCm1 = 1, SSECm = 1)
Normal operation
Setting start
Does TSFmn = 0 on all channels?
Yes SIRm1 = 0007H
<1>
Writing 1 to the STmn bit
SEmn = 0
SAU initial setting
<2>
Setting SSCm register
(SWCm = 1, SSECm = 1)
Writing 1 to the SSmn bit
<3>
SEmn = 1
Setting interrupt <4>
Entered the STOP mode
No
Clear the all error flags
The operation of all channels is also stopped to switch to the STOP mode. Channel 1 is specified for UART reception. Change to the UART reception baud rate in SNOOZE mode (SPSm register and bits 15 to 9 in SDRm1 register). EOCm1: Make the setting to enable generation of error interrupt INTSREq. SNOOZE mode setting (make the setting to disable generation of error interrupt INTSREq in SNOOZE mode).
Communications waiting state
Clear interrupt request flag (xxIF), reset interrupt mask (xxMK) and set interrupt disable (DI). fCLK supplied to the SAU is stopped.
STOP SNOOZE mode mode
<5>
The valid edge of the RxDq pin detected
<6>
(Entered the SNOOZE mode)
Input of the start bit on the RxDq pin detected (UARTq receive operation)
<7> Reception error detected
If an error occurs, because the CPU switches to the STOP mode again, the error flag is not set.
STOP mode
SNOOZE mode
<7> <8>
INTSRq
<9>
Reading receive data from
the SDRmn[7:0] bits (RXDq
register) (8 bits) or the
SDRmn[8:0] bits (9 bits)
The valid edge of the RxDq pin detected (Entered the SNOOZE mode) Input of the start bit on the RxDq pin detected (UARTq receive operation) Transfer end interrupt (INTSRq) generated
The mode switches from SNOOZE to normal operation.
<10> Writing 1 to the STm1 bit
Stops operation by setting SEm1 = 0.
<11>
Setting SSCm register (SWCm = 0, SSECm = 0)
Change to the UART reception baud rate in
normal operation
Writing 1 to the SSmn bit
Normal operation
Reset SNOOZE mode setting
Set the SPSm register and bits 15 to 9 in the SDRm1 register.
Communications waiting state (SEmn = 1)
Normal operation
Caution
If a parity error, framing error, or overrun error occurs while the SSECm bit is set to 1, the PEFm1, FEFm1, or OVFm1 flag is not set and an error interrupt (INTSREq) is not generated. Therefore, when the setting of SSECm = 1 is made, clear the PEFm1, FEFm1, and OVFm1 flags before setting the SWCm bit to 1 and read the value in SDRm1[7:0] (RxDq register) (8 bits) or SDRm1[8:0] (9 bits).
Remark 1. <1> to <11> in the figure correspond to <1> to <11> in Figure 15 - 95 Timing Chart of SNOOZE Mode Operation (EOCm1 = 1, SSECm = 1).
Remark 2. 30- to 64-pin products: m = 0; q = 0; n = 0 to 3 80- to 128-pin products: m = 0, 1; q = 0, 2; n = 0 to 3
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15.6.4 Calculating Baud Rate
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(1) Baud rate calculation expression The baud rate for UART (UART0 to UART3) communication can be calculated by the following expressions.
(Baud rate) = {Operation clock (fMCK) frequency of target channel} ÷ (SDRmn[15:9]+1) ÷ 2 [bps]
Caution Setting serial data register mn (SDRmn) SDRmn[15:9] = (0000000B, 0000001B) is prohibited. Remark 1. When UART is used, the value of SDRmn[15:9] is the value of bits 15 to 9 of the SDRmn register (0000010B
to 1111111B) and therefore is 2 to 127. Remark 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13
The operation clock (fMCK) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial mode register mn (SMRmn).
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Table 15 - 4 Selection of Operation Clock For UART
SMRmn Register
CKSmn
SPSm Register
PRS PRS PRS PRS PRS PRS PRS PRS m13 m12 m11 m10 m03 m02 m01 m00
Operation Clock (fMCK)Note fCLK = 32 MHz
0
×
×
×
×
0
0
0
0 fCLK
32 MHz
×
×
×
×
0
0
0
1 fCLK/2
16 MHz
×
×
×
×
0
0
1
0 fCLK/22
8 MHz
×
×
×
×
0
0
1
1 fCLK/23
4 MHz
×
×
×
×
0
1
0
0 fCLK/24
2 MHz
×
×
×
×
0
1
0
1 fCLK/25
1 MHz
×
×
×
×
0
1
1
0 fCLK/26
500 kHz
×
×
×
×
0
1
1
1 fCLK/27
250 kHz
×
×
×
×
1
0
0
0 fCLK/28
125 kHz
×
×
×
×
1
0
0
1 fCLK/29
62.5 kHz
×
×
×
×
1
0
1
0 fCLK/210
31.25 kHz
×
×
×
×
1
0
1
1 fCLK/211
15.63 kHz
×
×
×
×
1
1
0
0 fCLK/212
7.81 kHz
×
×
×
×
1
1
0
1 fCLK/213
3.91 kHz
×
×
×
×
1
1
1
0 fCLK/214
1.95 kHz
×
×
×
×
1
1
1
1 fCLK/215
977 Hz
1
0
0
0
0
×
×
×
× fCLK
32 MHz
0
0
0
1
×
×
×
× fCLK/2
16 MHz
0
0
1
0
×
×
×
× fCLK/22
8 MHz
0
0
1
1
×
×
×
× fCLK/23
4 MHz
0
1
0
0
×
×
×
× fCLK/24
2 MHz
0
1
0
1
×
×
×
× fCLK/25
1 MHz
0
1
1
0
×
×
×
× fCLK/26
500 kHz
0
1
1
1
×
×
×
× fCLK/27
250 kHz
1
0
0
0
×
×
×
× fCLK/28
125 kHz
1
0
0
1
×
×
×
× fCLK/29
62.5 kHz
1
0
1
0
×
×
×
× fCLK/210
31.25 kHz
1
0
1
1
×
×
×
× fCLK/211
15.63 kHz
×
×
×
×
1
1
0
0 fCLK/212
7.81 kHz
×
×
×
×
1
1
0
1 fCLK/213
3.91 kHz
×
×
×
×
1
1
1
0 fCLK/214
1.95 kHz
×
×
×
×
1
1
1
1 fCLK/215
977 Hz
Other than above
Setting prohibited
Note
When changing the clock selected for fCLK (by changing the system clock control register (CKC) value), do so after having
stopped (serial channel stop register m (STm) = 000FH) the operation of the serial array unit (SAU).
Remark 1. ×: Don't care
Remark 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(2) Baud rate error during transmission The baud rate error of UART (UART0 to UART3) communication during transmission can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side.
(Baud rate error) = (Calculated baud rate value) ÷ (Target baud rate) × 100 - 100 [%]
Here is an example of setting a UART baud rate at fCLK = 32 MHz.
UART Baud Rate (Target Baud Rate)
Operation Clock (fMCK)
fCLK = 32 MHz
SDRmn[15:9]
Calculated Baud Rate
300 bps
fCLK/29
103
300.48 bps
600 bps
fCLK/28
103
600.96 bps
1200 bps
fCLK/27
103
1201.92 bps
2400 bps
fCLK/26
103
2403.85 bps
4800 bps
fCLK/25
103
4807.69 bps
9600 bps
fCLK/24
103
9615.38 bps
19200 bps
fCLK/23
103
19230.8 bps
31250 bps
fCLK/23
63
31250.0 bps
38400 bps
fCLK/22
103
38461.5 bps
76800 bps
fCLK/2
103
76923.1 bps
153600 bps
fCLK
103
153846 bps
312500 bps
fCLK
50
313725.5 bps
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), mn = 00, 02, 10, 12
Error from Target Baud Rate
+0.16% +0.16% +0.16% +0.16% +0.16% +0.16% +0.16% ±0.0% +0.16% +0.16% +0.16% +0.39%
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(3) Permissible baud rate range for reception The permissible baud rate range for reception during UART (UART0 to UART3) communication can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side.
(Maximum receivable baud rate) =
2 × k × Nfr 2 × k × Nfr - k + 2
× Brate
(Minimum receivable baud rate) =
2 × k × (Nfr - 1) 2 × k × Nfr - k - 2
× Brate
Brate: Calculated baud rate value at the reception side (See 15.6.4 (1) Baud rate calculation expression.) k: SDRmn[15:9] + 1 Nfr: 1 data frame length [bits]
= (Start bit) + (Data length) + (Parity bit) + (Stop bit)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 1, 3), mn = 01, 03, 11, 13
Figure 15 - 97 Permissible Baud Rate Range for Reception (1 Data Frame Length = 11 Bits)
Data frame length of SAU
Permissible minimum data frame length
Latch timing
Start
Bit 0
Bit 1
bit
Bit 7
Parity bit
Stop bit
FL 1 data frame (11 × FL)
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
(11 × FL) min.
Permissible maximum data frame length
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
(11 × FL) max.
As shown in Figure 15 - 97, the timing of latching receive data is determined by the division ratio set by bits 15 to 9 of serial data register mn (SDRmn) after the start bit is detected. If the last data (stop bit) is received before this latch timing, the data can be correctly received.
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.6.5
Procedure for Processing Errors that Occurred During UART (UART0 to UART3) Communication
The procedure for processing errors that occurred during UART (UART0 to UART3) communication is described in Figure 15 - 98 and Figure 15 - 99.
Figure 15 - 98 Processing Procedure in Case of Parity Error or Overrun Error
Software Manipulation
State of the Hardware
Remark
Reads serial data register mn (SDRmn). Reads serial status register mn (SSRmn).
The BFFmn bit of the SSRmn register is set to 0 and channel n is enabled to receive data
This is to prevent an overrun error if the next reception is completed during error processing.
The error type is identified and the read value is used to clear the error flag.
Writes 1 to serial flag clear trigger register mn (SIRmn).
The error flag is cleared.
Only the error generated during reading can be cleared, by writing the value read from the SSRmn register to the SIRmn register without modification.
Figure 15 - 99 Processing Procedure in Case of Framing Error
Software Manipulation
State of the Hardware
Remark
Reads serial data register mn (SDRmn). Reads serial status register mn (SSRmn).
The BFFmn bit of the SSRmn register is set This is to prevent an overrun error if the
to 0 and channel n is enabled to receive
next reception is completed during error
data
processing.
The error type is identified and the read value is used to clear the error flag.
Writes serial flag clear trigger register mn (SIRmn).
The error flag is cleared.
Only the error generated during reading can be cleared, by writing the value read from the SSRmn register to the SIRmn register without modification.
Sets the STmn bit of serial channel stop register m (STm) to 1.
The SEmn bit of serial channel enable status register m (SEm) is set to 0 and channel n stops operation.
Synchronization with other party of communication
Synchronization with the other party of communication is re-established and communication is resumed because it is considered that a framing error has occurred because the start bit has been shifted.
Sets the SSmn bit of serial channel start register m (SSm) to 1.
The SEmn bit of serial channel enable status register m (SEm) is set to 1 and channel n is enabled to operate.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.7
LIN Communication Operation
15.7.1 LIN Transmission
Of UART transmission, UART2 of the 30-, 32-, 36-, 40-, 44-, 48-, 52-, 64-, 80-, 100-, and 128-pin products support LIN communication. For LIN transmission, channel 0 of unit 1 is used.
UART
UART0
UART1
UART2
UART3
Support of LIN communication
Not supported
Not supported
Supported
Not supported
Target channel
--
--
Channel 0 of SAU1
--
Pins used
--
--
TxD2
--
Interrupt
--
--
INTST2
--
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected.
Error detection flag
None
Transfer data length 8 bits
Transfer rateNote
Max. fMCK/6 [bps] (SDR10[15:9] = 2 or more), Min. fCLK/ (2 × 215 × 128) [bps]
Data phase
Non-reverse output (default: high level) Reverse output (default: low level)
Parity bit
No parity bit
Stop bit
Appending 1 bit
Data direction
LSB first
Note
Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics specified in the electrical characteristics. For details, see CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C. In general, 2.4, 9.6, or 19.2 kbps is often used in LIN communication.
Remark fMCK: Operation clock frequency of target channel fCLK: System clock frequency
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol designed to reduce the cost of an automobile network. Communication of LIN is single-master communication and up to 15 slaves can be connected to one master. The slaves are used to control switches, actuators, and sensors, which are connected to the master via LIN. Usually, the master is connected to a network such as CAN (Controller Area Network). A LIN bus is a single-wire bus to which nodes are connected via transceiver conforming to ISO9141. According to the protocol of LIN, the master transmits a frame by attaching baud rate information to it. A slave receives this frame and corrects a baud rate error from the master. If the baud rate error of a slave is within ±15%, communication can be established. Figure 15 - 100 outlines a transmission operation of LIN.
Figure 15 - 100 Transmission Operation of LIN
LIN Bus
TxD2 (output) INTST2Note 3
Wakeup signal frame
Break field
Sync field
Protected
Identifier field
Data field
Data field
Checksum field
8-bit lengthNote 1
13-bit length Break
transmissionNote 2
55 H
PID
Data
Data
Checksum
transmission transmission transmission transmission transmission
Delimiter transmission
Note 1. Note 2.
Set the baud rate in accordance with the wakeup signal regulations and transmit data of 80H. A break field is defined to have a width of 13 bits and output a low level. Where the baud rate for main transfer is N [bps], therefore, the baud rate of the break field is calculated as follows.
(Baud rate of break field) = 9/13 × N
Note 3.
By transmitting data of 00H at this baud rate, a break field is generated. INTST2 is output upon completion of transmission. INTST2 is also output at BF transmission.
Remark The interval between fields is controlled by software.
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RL78/G23 Figure 15 - 101 Flowchart for LIN Transmission
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Note
Starting LIN communication
Operation of the hardware(Reference)
Transmitting wakeup signal frame (80H TXD2)
No TSF10 = 0?
Yes UART2 stop (1 ST10 bit)
Changing UART2 baud rate (zz SDR [15:9])
UART2 restart (1 SS10 bit)
BF transmission 00 TXD2
No TSF10 = 0?
Yes UART2 stop (1 ST10 bit)
Changing UART2 baud rate (xx SDR[15:9])
UART2 restart (1 SS10 bit)
Transmitting sync field 55H TXD2
No BFF10 = 0? Yes
Data TXD2
No BFF10 = 0?
Yes No
Completing all data transmission ? Yes No TSF10 = 0? Yes End of LIN communication
Transmitting wakeup signal frame Note
Wakeup signal frame generation
TxD2
8-bit length
Waiting for completion
80H
of transmission
Changing baud rate for BF
Waiting for completion of BF
transmission
TxD2
Return the baud rate
BF generation 13-bit length
000H
Transmitting sync field Waiting for buffer empty
Transmitting PID to checksum
Sync field data generation TxD2
55H
Waiting for buffer empty
Waiting for transmission PID to checksum
Waiting for completion of transmission (transmission completed to the LIN bus)
This is only required if the LIN-bus is being started from sleep mode.
Remark This flow assumes that the initial setting of the UART is completed and transmission is enabled.
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.7.2 LIN Reception
Of UART reception, UART2 of the 30-, 32-, 36-, 40-, 44-, 48-, 52-, 64-, 80-, 100-, and 128-pin products support LIN communication. For LIN reception, channel 1 of unit 1 is used.
UART
UART0
UART1
UART2
UART3
Support of LIN communication
Not supported
Not supported
Supported
Not supported
Target channel
--
--
Channel 1 of SAU1
--
Pins used
--
--
RxD2
--
Interrupt
--
--
INTSR2
--
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error interrupt
--
--
INTSRE2
--
Error detection flag
· Framing Error detection flag (FEF11) · Overrun Error detection flag (OVF11)
Transfer data length 8 bits
Transfer rateNote
Max. fMCK/6 [bps] (SDR11[15:9] = 2 or more), Min. fCLK/ (2 × 215 × 128) [bps]
Data phase
Non-reverse output (default: high level) Reverse output (default: low level)
Parity bit
No parity bit (The parity bit is not checked.)
Stop bit
Check the first bit
Data direction
LSB first
Note
Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics specified in the electrical characteristics. For details, see CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
Remark fMCK: Operation clock frequency of target channel fCLK: System clock frequency
Figure 15 - 102 outlines a reception operation of LIN.
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RL78/G23 Figure 15 - 102 Reception Operation of LIN
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
LIN Bus RxD2
Wakeup signal frame
Break field
Sync field
Protected identifier Data field Data field
field
Checksum field
Break reception
<2>
Header
55H reception
PID reception
Response
Data
Data
reception reception
Checksum reception
<5>
UART2 INTSR2
Edge detection (INTP0)
TM07 INTTM07
STOP
<1>
STOP
<3>
<4>
Pulse width measurement
Pulse interval measurement
Reception
Here is the flow of reception processing.
<1> The wakeup signal is detected by detecting an edge on the INTP0 interrupt pin. When the wakeup signal is detected, set TM07 to the pulse width measurement function to measure the low-level width of the BF signal. Then wait for BF signal reception.
<2> TM07 starts measuring the low-level width upon detection of the falling edge of the BF signal, and then captures the data upon detection of the rising edge of the BF signal. The captured data is used to judge whether it is the BF signal.
<3> When the BF signal has been received normally, change TM07 to pulse interval measurement and measure the interval between the falling edges of the RxD2 signal in the Sync field four times. (see 7.8.4 Operation for input pulse interval measurement.)
<4> Calculate a baud rate error from the bit interval of sync field (SF). Stop UART2 once and adjust (re-set) the baud rate.
<5> The checksum field should be distinguished by software. In addition, processing to initialize UART2 after the checksum field is received and to wait for reception of BF should also be performed by software.
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Figure 15 - 103 Flowchart of LIN Reception
Note
Starting LIN communication
State of LIN bus signal and operation of the hardware
Generate INTP0?
Yes
Starting in low-level width measurement mode for TM07
No
Wait for wakeup frame signalNote
The low-level width of RxD2 is measured using TM07 and BF is detected. Wait for BF detection.
Wakeup signal frame RxD2 pin
Edge detection
INTP0
No Generate INTTM07?
Yes No
11 bit lengths or more?
Yes Changing TM07 to pulse interval
measurement
If the detected pulse width is 11 bits or more, it is judged as BF.
Break field
RxD2 pin
Channel 7 of TAU0
INTTM07
Pulse width measurement
Channel 7
Set up TM07 to measure the interval between the falling edges.
Generate INTTM07?
Ignore the first INTTM07. No
Yes Sync field
No Generate INTTM07?
Yes Accumulate captured values
No Completed 4 times?
Yes ChangingTM07 to low-level
width measurement
Measure the intervals between five falling edges of SF, and accumulate the four captured values.
RxD2 pin
Channel 7 of TAU0
INTTM07
Pulse interval measurement
Accumulate four times
Change TM07 to low-level width measurement to detect a break field.
Calculate the baud rate
UART2 initial setting
Starting UART2 reception (1 SS11)
Divide the accumulated value by 8 to obtain the bit width. Use this value to determine the setting values of SPS1, SDR10, and SDR11.
Set up the initial setting of UART2 according to the LIN communication conditions.
Data reception
Completing all data transmission? Yes
Stop UART2 reception (1 ST11)
End of LIN communication
Receive the PID, data, and checksum fields (if the PID matches).
No
This is only required if the LIN bus is in sleep mode.
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Figure 15 - 104 and Figure 15 - 105 show the configuration of ports used for LIN reception. The wakeup signal transmitted from the master of LIN is received by detecting an edge of an external interrupt (INTP0). The length of the sync field transmitted from the master can be measured by using the external event capture operation of the timer array unit 0 to calculate a baud-rate error. By using the port input switching control (the ISC0 and ISC1 bits), the signal input to the reception port (RxD2) can be used as an external interrupt (INTP0) or sent to the timer array unit without additional external connections.
Figure 15 - 104 Port Configuration for Reception of LIN (30-, 32-, 36-, and 40-pin)
P14/RxD2/SI20/SDA20
Selector
RXD2 input
Port mode (PM14)
Output latch (P14)
P137/INTP0
Selector
INTP0 input
Port input switch control
(ISC0)
<ISC0> 0: Selects INTP0 (P137) 1: Selects RxD2 (P14)
Selector
Channel 7 input of timer array unit
Port input switch control
(ISC1)
<ISC1> 0: Do not use a timer input signal for channel 7. 1: Selects RxD2 (P14)
Remark ISC0, ISC1: Bits 0 and 1 of the input switch control register (ISC) (See Figure 15 - 22.)
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Figure 15 - 105 Port Configuration for Reception of LIN (44-, 48-, 52-, and 64-pin)
P14/RxD2/SI 20/SDA20
Selector
RXD2 input
Port mode (PM 14 )
Output latch ( P14 )
P137 / INTP0
Selector
INTP0 input
P 41/ TI07 /TO07
Selector
Port input switch control
(ISC 0)
<ISC 0> 0: Selects INTP0 (P137) 1: Selects RxD 2 (P14)
Selector
Channel 7 input of timer array unit
Port mode (PM 41 )
Output latch ( P41 )
Port input switch control
(ISC 1)
<ISC 1> 0: Selects TI07 (P41) 1: Selects RxD 2 (P14)
Remark ISC0, ISC1: Bits 0 and 1 of the input switch control register (ISC) (See Figure 15 - 22.)
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The peripheral functions used for the LIN communication operation are as follows.
<Peripheral functions used> · External interrupt (INTP0); Wakeup signal detection
Usage: To detect an edge of the wakeup signal and the start of communication · Channel 7 of timer array unit; Baud rate error detection, break field detection.
Usage: To detect the length of the sync field (SF) and divide it by the number of bits in order to detect a baud rate error. (The interval of the edge input to RxD2 is measured in the capture mode.) To measure the low-level width to detect the break field (BF).
· Channels 0 and 1 (UART2) of serial array unit 1 (SAU1)
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.8
Operation of Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31)
Communication
This is a clocked communication function to communicate with two or more devices by using two lines: serial clock (SCL) and serial data (SDA). This simplified I2C is designed for single communication with a device such as EEPROM, flash memory, or A/D converter, and therefore, it functions only as a master. Operate the control registers by software for setting the start and stop conditions while observing the specifications of the I2C bus line
[Data transmission/reception]
· Master transmission, master reception (only master function with a single master) · ACK output function Note and ACK detection function · Data length of 8 bits
(When an address is transmitted, the address is specified by the higher 7 bits, and the least significant bit is used for R/W control.) · Generation of start condition and stop condition for software [Interrupt function]
· Transfer end interrupt [Error detection flag]
· Overrun error · ACK error
* [Functions not supported by simplified I2C] · Slave transmission, slave reception · Multi-master function (arbitration loss detection function) · Clock stretch detection
Note
When receiving the last data, ACK will not be output if 0 is written to the SOEmn (SOEm register) bit and serial communication data output is stopped. See 15.8.3 (2) Processing flow for details.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13
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The channel supporting simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) is channels 0 to 3 of SAU0 and channel 0 and 1 of SAU1.
<30- and 32-pin products>
Unit 0
1
Channel 0 1 2 3 0 1
Used as SPI (CSI) CSI00 -- -- CSI11 CSI20 --
Used as UART UART0
UART1
UART2 (supporting LIN-bus)
Used as Simplified I2C IIC00 -- -- IIC11 IIC20 --
<36-, 40-, and 44-pin products>
Unit 0
1
Channel 0 1 2 3 0 1
Used as SPI (CSI) CSI00 -- -- CSI11 CSI20 CSI21
Used as UART UART0
UART1
UART2 (supporting LIN-bus)
Used as Simplified I2C IIC00 -- -- IIC11 IIC20 IIC21
<48- and 52-pin products>
Unit 0
1
Channel 0 1 2 3 0 1
Used as SPI (CSI) CSI00 CSI01 -- CSI11 CSI20 CSI21
Used as UART UART0
UART1
UART2 (supporting LIN-bus)
Used as Simplified I2C IIC00 IIC01 -- IIC11 IIC20 IIC21
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<64-pin products>
Unit 0
1
Channel 0 1 2 3 0 1
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Used as SPI (CSI) CSI00 CSI01 CSI10 CSI11 CSI20 CSI21
Used as UART UART0
UART1
UART2 (supporting LIN-bus)
Used as Simplified I2C IIC00 IIC01 IIC10 IIC11 IIC20 IIC21
<80-, 100-, and 128-pin products>
Unit 0
1
Channel 0 1 2 3 0 1 2 3
Used as SPI (CSI) CSI00 CSI01 CSI10 CSI11 CSI20 CSI21 CSI30 CSI31
Used as UART UART0 UART1
UART2 (supporting LIN-bus) UART3
Used as Simplified I2C IIC00 IIC01 IIC10 IIC11 IIC20 IIC21 IIC30 IIC31
Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) performs the following four types of communication
operations.
· Address field transmission
(See 15.8.1.)
· Data transmission
(See 15.8.2.)
· Data reception
(See 15.8.3.)
· Stop condition generation
(See 15.8.4.)
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15.8.1 Address Field Transmission
Address field transmission is a transmission operation that first executes in I2C communication to identify the target for transfer (slave). After a start condition is generated, an address (7 bits) and a transfer direction (1 bit) are transmitted in one frame.
Simplified I2C
IIC00
IIC01
IIC10
IIC11
IIC20
IIC21
IIC30
IIC31
Target channel
Channel 0 Channel 1 Channel 2 Channel 3 Channel 0 Channel 1 Channel 2 Channel 3
of SAU0
of SAU0
of SAU0
of SAU0
of SAU1
of SAU1
of SAU1
of SAU1
Pins used
SCL00,
SCL01,
SCL10,
SCL11,
SCL20,
SCL21,
SCL30,
SCL31,
SDA00Note 1 SDA01Note 1 SDA10Note 1 SDA11Note 1 SDA20Note 1 SDA21Note 1 SDA30Note 1 SDA31Note 1
Interrupt
INTIIC00 INTIIC01 INTIIC10 INTIIC11 INTIIC20 INTIIC21 INTIIC30 INTIIC31
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error detection flag ACK error detection flag (PEFmn)
Transfer data length 8 bits (transmitted with specifying the higher 7 bits as address and the least significant bit as R/W control)
Transfer rateNote 2
Max.fMCK/4 [Hz] (SDRmn[15:9] = 1 or more) fMCK: Operation clock frequency of target channel However, the following condition must be satisfied in each mode of I2C. · Max. 1 MHz (fast mode plus) · Max. 400 kHz (fast mode) · Max. 100 kHz (standard mode)
Data level
Non-reverse output (default: high level)
Parity bit
No parity bit
Stop bit
Appending 1 bit (for ACK transmission/reception timing)
Data direction
MSB first
Note 1. Note 2.
To perform communication via simplified I2C, set the N-ch open-drain output (VDD tolerance (30- to 52-pin products)/EVDD tolerance (64- to 128-pin products)) mode (POMxx = 1) with the port output mode register (POMxx). See 4.3 Registers to Control the Port Function and 4.5 Register Settings When Using Alternate Function for details. When IIC00, IIC10, IIC20, IIC30, IIC31 is communicating with an external device with a different potential, set the N-ch open-drain output (VDD tolerance (30- to 52-pin products)/EVDD tolerance (64- to 128-pin products)) mode (POMxx = 1) also for the clock input/output pins (SCL00, SCL10, SCL20, SCL30, SCL31). See 4.4.5 Handling different potential (1.8 V, 2.5 V, or 3 V) by using I/O buffers for details. Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics specified in the electrical characteristics. For details, see CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(1) Register setting
Figure 15 - 106 Example of Contents of Registers for Address Field Transmission of Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31)
(a) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
STSmn
SISmn0
CKSmn CCSmn
MDmn2 MDmn1 MDmn0
SMRmn 0/1
0
0
0
0
0
Note 1
Note 1
0
0
1
0
0
1
0
0
0
0
Operation clock (fMCK) of channel n 0: Prescaler output clock CKm0 set by the SPSm register 1: Prescaler output clock CKm1 set by the SPSm register
Operation mode of channel n 0: Transfer end interrupt
(b) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9
8
7
TXEmn RXEmn DAPmn CKPmn
EOCmn PTCmn1 PTCmn0 DIRmn
SCRmn 1
0
0
0
0
0
0
0
0
Setting of parity bit 00B: No parity
6
5
4
3
SLCmn1 SLCmn0
Note 2
0
0
1
0
2
1
0
DLSmn1 DLSmn0
1
1Note 3
1
Setting of stop bit 01B: Appending 1 bit (ACK)
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOr)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SDRmn
Baud rate setting
Transmit data setting (address + R/W) 0
SIOr
(d) Serial output register m (SOm)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CKOm3 CKOm2 CKOm1 CKOm0
SOm3 SOm2 SOm1 SOm0
SOm 0
0
0
0 0/1 0/1 0/1 0/1 0
0
0
0 0/1 0/1 0/1 0/1
Start condition is generated by manipulating the SOmn bit.
(e) Serial output enable register m (SOEm)
15 14 13 12 11 10
SOEm 0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
SOEm3 SOEm2 SOEm1 SOEm0
0
0
0
0
0
0 0/1 0/1 0/1 0/1
SOEmn = 0 until the start condition is generated, and SOEmn = 1 after generation.
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(f) Serial channel start register m (SSm) ... Set only the bit of the target channel to 1.
15 14 13 12 11 10
SSm 0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
SSm3 SSm2 SSm1 SSm0
0
0
0
0
0
0 0/1 0/1 0/1 0/1
SSmn = 0 until the start condition is generated, and SSmn = 1 after generation.
Note 1. Note 2. Note 3.
Only provided for the SMR00, SMR03, SMR11, and SMR13 registers. Only provided for the SCR00, SCR02, SCR10, and SCR12 registers. Only provided for the SCR00 and SCR01 registers and the SCR10 and SCR11 registers of 80- to 128-pin products. This bit is fixed to 1 for the other registers.
Remark 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13
Remark 2. : Setting is fixed in the IIC mode, : Setting disabled (set to the initial value) 0/1: Set to 0 or 1 depending on the usage of the user
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(2) Operation procedure Figure 15 - 107 Initial Setting Procedure for Simplified I2C Address Field Transmission
Starting initial setting Setting the PRR0 register
Release the serial array unit from the reset state.
Setting the PER0 register
Start clock supply to the serial array unit.
Setting the SPSm register
Set the operation clock.
Setting the SMRmn register
Set an operation mode, etc.
Setting the SCRmn register
Setting the SDRmn register
Setting the SOm register
Setting port
Completing initial setting
Note 1. Note 2.
30- to 52-pin products 64- to 128-pin products
Set a communication format.
Set a transfer baud rate (setting the transfer clock by dividing the operation clock (fMCK)).
Set the initial output level (1) of the serial data (SOmn) and serial clock (CKOmn).
Enable data output, clock output, and N-ch open-drain output (VDD tolerance Note 1/EVDD tolerance Note 2) of the target channel by setting the port register, port mode register, and port output mode register.
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RL78/G23 (3) Processing flow
Figure 15 - 108 Timing Chart of Address Field Transmission
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
SSmn SEmn SOEmn SDRmn SCLr output
SDAr output
SDAr input Shift
register mn INTIICr TSFmn
Address field transmission
CKOmn
bit manipulation D7 D6 D5 D4 D3 D2 D1 D0
SOmn bit manipulation
Address
R/W
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Shift operation
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Figure 15 - 109 Flowchart of Simplified I2C Address Field Transmission
Transmitting address field Default setting
Writing 0 to the SOmn bit Wait
For the initial setting, refer to Figure 15 - 107.
Set the SOmn bit to 0 Start condition generate To secure a hold time of SCL signal
Writing 0 to the CKOmn bit Writing 1 to the SOEmn bit
Drive the SCL signal low and prepare for communications.
Enable serial output
Writing 1 to the SSmn bit
Enables serial communications.
Writing address and R/W data to SIOr (SDRmn[7:0])
Transmitting address field
Transfer end interrupt generated?
Yes
Responded ACK? Yes
Address field transmissioncompleted
Wait for address field transmission No complete.
(Clear the interrupt request flag)
ACK response from the slave
will be confirmed in PEFmn bit.
if ACK (PEFmn = 0), to the next
No
processing, if NACK (PEFmn =
1) to error processing.
Communication error processing
To data transmission flow and data reception flow
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.8.2 Data Transmission
Data transmission is an operation to transmit data to the target for transfer (slave) after transmission of an address field. After all data are transmitted to the slave, a stop condition is generated and the bus is released.
Simplified I2C Target channel
IIC00
Channel 0 of SAU0
IIC01
Channel 1 of SAU0
IIC10
Channel 2 of SAU0
IIC11
Channel 3 of SAU0
IIC20
IIC21
IIC30
IIC31
Channel 0 Channel 1 Channel 2 Channel 3 of SAU1 of SAU1 of SAU1 of SAU1
Pins used Interrupt
SCL00, SDA00Note 1
INTIIC00
SCL01, SDA01Note 1
INTIIC01
SCL10, SDA10Note 1
INTIIC10
SCL11, SDA11Note 1
INTIIC11
SCL20, SDA20Note 1
INTIIC20
SCL21, SDA21Note 1
INTIIC21
SCL30, SDA30Note 1
INTIIC30
SCL31, SDA31Note 1
INTIIC31
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error detection flag ACK error flag (PEFmn)
Transfer data length Transfer rateNote 2
8 bits
Max.fMCK/4 [Hz] (SDRmn[15:9] = 1 or more) fMCK: Operation clock frequency of target channel However, the following condition must be satisfied in each mode of I2C. · Max. 1 MHz (fast mode plus) · Max. 400 kHz (fast mode) · Max. 100 kHz (standard mode)
Data level
Non-reverse output (default: high level)
Parity bit
No parity bit
Stop bit
Appending 1 bit (for ACK reception timing)
Data direction
MSB first
Note 1. Note 2.
To perform communication via simplified I2C, set the N-ch open-drain output (VDD tolerance (30- to 52-pin products)/EVDD tolerance (64- to 128-pin products)) mode (POMxx = 1) with the port output mode register (POMxx). For details, see 4.3 Registers to Control the Port Function and 4.5 Register Settings When Using Alternate Function. When IIC00, IIC10, IIC20, IIC30, IIC31 is communicating with an external device with a different potential, set the N-ch open-drain output (VDD tolerance (30- to 52-pin products)/EVDD tolerance (64- to 128-pin products)) mode (POMxx = 1) also for the clock input/output pins (SCL00, SCL10, SCL20, SCL30, SCL31). For details, see 4.4.5 Handling different potential (1.8 V, 2.5 V, or 3 V) by using I/O buffers. Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics specified in the electrical characteristics. For details, see CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(1) Register setting
Figure 15 - 110 Example of Contents of Registers for Data Transmission of Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31)
(a) Serial mode register mn (SMRmn) ... Do not manipulate this register during data transmission/reception.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CKSmn CCSmn
STSmn
SISmn0
MDmn2 MDmn1 MDmn0
SMRmn 0/1
0
0
0
0
0
0 0Note 1 0 0Note 1 1
0
0
1
0
0
(b) Serial communication operation setting register mn (SCRmn) ... Do not manipulate the bits of this register, except the TXEmn and RXEmn bits, during data transmission/reception.
15 14 13 12 11 10 9
8
7
TXEmn RXEmn DAPmn CKPmn
EOCmn PTCmn1 PTCmn0 DIRmn
SCRmn 1
0
0
0
0
0
0
0
0
6
5
4
3
SLCmn1 SLCmn0
0 0Note 2 1
0
2
1
0
DLSmn1 DLSmn0
1 1Note 3 1
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOr) ... During data transmission/reception, valid only lower 8-bits (SIOr)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SDRmn
Baud rate settingNote 4
0
Transmit data setting
SIOr
(d) Serial output register m (SOm) ... Do not manipulate this register during data transmission/reception.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CKOm3 CKOm2 CKOm1 CKOm0
SOm3 SOm2 SOm1 SOm0
SOm 0
0
0
0
0/1Note 5 0/1Note 5 0/1Note 5 0/1Note 5
0
0
0
0
0/1Note 5 0/1Note 5 0/1Note 5 0/1Note 5
(e) Serial output enable register m (SOEm) ... Do not manipulate this register during data transmission/reception.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SOEm3 SOEm2 SOEm1 SOEm0
SOEm 0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(f) Serial channel start register m (SSm) ... Do not manipulate this register during data transmission/reception.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SSm3 SSm2 SSm1 SSm0
SSm 0
0
0
0
0
0
0
0
0
0
0
0 0/1 0/1 0/1 0/1
Note 1. Note 2. Note 3.
Note 4. Note 5.
Only provided for the SMR01, SMR03, SMR11, and SMR13 registers. Only provided for the SCR00, SCR02, SCR10, and SCR12 registers. Only provided for the SCR00 and SCR01 registers and the SCR10 and SCR11 registers of 80- to 128-pin products. This bit is fixed to 1 for the other registers. Because the setting is completed by address field transmission, setting is not required. The value varies depending on the communication data during communication operation.
Remark 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13
Remark 2. : Setting is fixed in the IIC mode, : Setting disabled (set to the initial value) 0/1: Set to 0 or 1 depending on the usage of the user
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RL78/G23 (2) Processing flow
Figure 15 - 111 Timing Chart of Data Transmission
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
SSmn
"L"
SEmn
"H"
SOEmn
"H"
SDRmn
SCLr output SDAr output
SDAr input
Shift register mn
INTIICr
TSFmn
Transmit data 1
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 ACK
Shift operation
Figure 15 - 112 Flowchart of Simplified I2C Data Transmission
Address field transmission completed
Starting data transmission
Writing data to SIOr (SDRmn[7:0])
Transmission start by writing
Transfer end interrupt generated? Yes
Responded ACK?
No Wait for transmission complete. (Clear the interrupt request flag)
ACK acknowledgment from the slave
No
If ACK (PEF = 0), to the next process if NACK (PEF = 1), to error handling
Yes Communication error processing
No
Data transfer completed?
Yes
Data transmission completed
Stop condition generation
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.8.3 Data Reception
Data reception is an operation to receive data from the target for transfer (slave) after transmission of an address field. After all data are received from the slave, a stop condition is generated and the bus is released.
Simplified I2C
IIC00
IIC01
IIC10
IIC11
IIC20
IIC21
IIC30
IIC31
Target channel
Channel 0 Channel 1 Channel 2 Channel 3 Channel 0 Channel 1 Channel 2 Channel 3 of SAU0 of SAU0 of SAU0 of SAU0 of SAU1 of SAU1 of SAU1 of SAU1
Pins used
SCL00,
SCL01,
SCL10,
SCL11,
SCL20,
SCL21,
SCL30,
SCL31,
SDA00Note 1 SDA01Note 1 SDA10Note 1 SDA11Note 1 SDA20Note 1 SDA21Note 1 SDA30Note 1 SDA31Note 1
Interrupt
INTIIC00 INTIIC01 INTIIC10 INTIIC11 INTIIC20 INTIIC21 INTIIC30 INTIIC31
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error detection flag Overrun error detection flag (OVFmn) only
Transfer data length 8 bits
Transfer rateNote 2
Max.fMCK/4 [Hz] (SDRmn[15:9] = 1 or more) fMCK: Operation clock frequency of target channel However, the following condition must be satisfied in each mode of I2C. · Max. 1 MHz (fast mode plus) · Max. 400 kHz (fast mode) · Max. 100 kHz (standard mode)
Data level
Non-reverse output (default: high level)
Parity bit
No parity bit
Stop bit
Appending 1 bit (ACK transmission)
Data direction
MSB first
Note 1. Note 2.
To perform communication via simplified I2C, set the N-ch open-drain output (VDD tolerance (30- to 52-pin products)/EVDD tolerance (64- to 128-pin products)) mode (POMxx = 1) with the port output mode register (POMxx). For details, see 4.3 Registers to Control the Port Function and 4.5 Register Settings When Using Alternate Function. When IIC00, IIC10, IIC20, IIC30, IIC31 is communicating with an external device with a different potential, set the N-ch open-drain output (VDD tolerance (30- to 52-pin products)/EVDD tolerance (64- to 128-pin products)) mode (POMxx = 1) also for the clock input/output pins (SCL00, SCL10, SCL20, SCL30, SCL31). For details, see 4.4.5 Handling different potential (1.8 V, 2.5 V, or 3 V) by using I/O buffers. Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics specified in the electrical characteristics. For details, see CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
(1) Register setting
Figure 15 - 113 Example of Contents of Registers for Data Reception of Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31)
(a) Serial mode register mn (SMRmn) ... Do not manipulate this register during data transmission/reception.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CKSmn CCSmn
STSmn
SISmn0
MDmn2 MDmn1 MDmn0
SMRmn 0/1
0
0
0
0
0
0 0Note 1 0 0Note 1 1
0
0
1
0
0
(b) Serial communication operation setting register mn (SCRmn) ... Do not manipulate the bits of this register, except the TXEmn and RXEmn bits, during data transmission/reception.
15 14 13 12 11 10 9
8
7
TXEmn RXEmn DAPmn CKPmn
EOCmn PTCmn1 PTCmn0 DIRmn
SCRmn 0
1
0
0
0
0
0
0
0
6
5
4
3
SLCmn1 SLCmn0
0 0Note 2 1
0
2
1
0
DLSmn1 DLSmn0
1 1Note 3 1
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOr)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SDRmn
Baud rate settingNote 4
Dummy transmit data setting (FFH) 0
SIOr
(d) Serial output register m (SOm) ... Do not manipulate this register during data transmission/reception.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CKOm3 CKOm2 CKOm1 CKOm0
SOm3 SOm2 SOm1 SOm0
SOm 0
0
0
0 0/1Note 5 0/1Note 5 0/1Note 5 0/1Note 5 0
0
0
0
0/1Note 5 0/1Note 5 0/1Note 5 0/1Note 5
(e) Serial output enable register m (SOEm) ... Do not manipulate this register during data transmission/reception.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SOEm3 SOEm2 SOEm1 SOEm0
SOEm 0
0
0
0
0
0
0
0
0
0
0
0 0/1 0/1 0/1 0/1
(f) Serial channel start register m (SSm) ... Do not manipulate this register during data transmission/reception.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SSm3 SSm2 SSm1 SSm0
SSm 0
0
0
0
0
0
0
0
0
0
0
0 0/1 0/1 0/1 0/1
Note 1. Note 2. Note 3.
Only provided for the SMR01, SMR03, SMR11, and SMR13 registers. Only provided for the SCR00, SCR02, SCR10, and SCR12 registers. Only provided for the SCR00 and SCR01 registers and the SCR10 and SCR11 registers of 80- to 128-pin
products. This bit is fixed to 1 for the other registers. Note 4. Because the setting is completed by address field transmission, setting is not required. Note 5. The value varies depending on the communication data during communication operation. Remark 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31),
mn = 00 to 03, 10 to 13
Remark 2. : Setting is fixed in the IIC mode, : Setting disabled (set to the initial value)
0/1: Set to 0 or 1 depending on the usage of the user
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RL78/G23 (2) Processing flow
Figure 15 - 114 Timing Chart of Data Reception (a) When starting data reception
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
SSmn
STmn
SEmn
SOEmn
TXEmn, RXEmn
"H"
TXEmn = 1 / RXEmn = 0
SDRmn
SCLr output SDAr output
SDAr input
Shift register mn
INTIICr
TSFmn
TXEmn = 0 / RXEmn = 1 Dummy data (FFH)
Receive data
ACK D7 D6 D5 D4 D3 D2 D1 D0
Shift operation
(b) When receiving last data
STmn
SEmn
SOEmn
TXEmn, RXEmn SDRmn
Output by serial communication operation is enabled.
Dummy data (FFH)
Receive data
SCLr output
SDAr output
ACK
SDAr input D2 D1 D0
D7
Shift register mn
INTIICr
TSFmn
Shift operation
Output by serial communication operation is stopped. TXEmn = 0 / RXEmn = 1
Dummy data (FFH)
Receive data
NACK D6 D5 D4 D3 D2 D1 D0
Shift operation
Reception of last byte
SOmn bit SOmn bit manipulation manipulation
IIC operation stop CKOmn bit manipulation
Step condition
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13
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RL78/G23 Figure 15 - 115 Flowchart of Data Reception
Address field transmission completed Data reception
Writing 1 to the STmn bit Writing 0 to the TXEmn bit, and 1 to the RXEmn bit
Writing 1 to the SSmn bit
No Last byte received?
Yes Writing 0 to the SOEmn bit
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Stop operation for rewriting SCRmn register. Set the operation of the channel to receive-only mode. Operation restart
Disable output so that not the ACK response to the last received data.
Writing dummy data (FFH) to SIOr (SDRmn[7:0])
Starting reception operation
Transfer end interrupt generated?
Yes Reading SIOr (SDRmn[7:0])
No Data transfer completed? Yes Data reception completed
No
Wait for the completion of reception.
(Clear the interrupt request flag)
Reading receive data, perform processing (stored in the RAM etc.).
Stop condition generation
Caution ACK is not output when the last data is received (NACK). Communication is then completed by setting 1 in the STmn bit of serial channel stop register m (STm) to stop operation and generating a stop condition.
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.8.4 Stop Condition Generation
After all data are transmitted to or received from the target slave, a stop condition is generated and the bus is released. (1) Processing flow Figure 15 - 116 Timing Chart of Stop Condition Generation
STmn SEmn SOEmn Note
SCLr output SDAr output
Note
Operation stop
SOmn
CKOmn
SOmn
bit manipulation bit manipulation bit manipulation
Stop condition
During a receive operation, the SOEmn bit of serial output enable register m (SOEm) is cleared to 0 before receiving the last data.
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Figure 15 - 117 Flowchart of Stop Condition Generation
Completion of data transmission/data reception
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Starting generation of stop condition
Writing 1 to the STmn bit (the SEmn bit is cleared to 0)
Writing 0 to the SOEmn bit Writing 0 to the SOmn bit Writing 1 to the CKOmn bit
Wait Writing 1 to the SOmn bit End of IIC communication
Stops operation (CKOmn can be manipulated).
Disables output (SOmn can be manipulated).
Timing to satisfy the low width standard of SCL for the I2C bus. Secure a wait time so that the specifications of I2C on the slave side are satisfied.
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.8.5 Calculating Transfer Rate
The transfer rate for simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) communication can be calculated by the following expressions.
(Transfer rate) = {Operation clock (fMCK) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2
Caution
SDRmn[15:9] must not be set to 00000000B. Set SDRmn[15:9] to 0000001B or greater. The duty ratio of the SCL signal output by the simplified I2C is 50%. The I2C bus specifications define that the low-level width of the SCL signal is longer than the high-level width. If 400 kbps (fast mode) or 1 Mbps (fast mode plus) is specified, therefore, the low-level width of the SCL output signal becomes shorter than the value specified in the I2C bus specifications. Make sure that the SDRmn[15:9] value satisfies the I2C bus specifications.
Remark 1. The value of SDRmn[15:9] is the value of bits 15 to 9 of the SDRmn register (0000001B to 1111111B) and therefore is 1 to 127.
Remark 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13
The operation clock (fMCK) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial mode register mn (SMRmn).
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Table 15 - 5 Selection of Operation Clock For Simplified I2C
SMRmn Register
SPSm Register
Operation Clock (fMCK)Note
CKSmn
PRS PRS PRS PRS PRS PRS PRS PRS m13 m12 m11 m10 m03 m02 m01 m00
fCLK = 32 MHz
0
×
×
×
×
0
0
0
0 fCLK
32 MHz
×
×
×
×
0
0
0
1 fCLK/2
16 MHz
×
×
×
×
0
0
1
0 fCLK/22
8 MHz
×
×
×
×
0
0
1
1 fCLK/23
4 MHz
×
×
×
×
0
1
0
0 fCLK/24
2 MHz
×
×
×
×
0
1
0
1 fCLK/25
1 MHz
×
×
×
×
0
1
1
0 fCLK/26
500 kHz
×
×
×
×
0
1
1
1 fCLK/27
250 kHz
×
×
×
×
1
0
0
0 fCLK/28
125 kHz
×
×
×
×
1
0
0
1 fCLK/29
62.5 kHz
×
×
×
×
1
0
1
0 fCLK/210
31.25 kHz
×
×
×
×
1
0
1
1 fCLK/211
15.63 kHz
1
0
0
0
0
×
×
×
× fCLK
32 MHz
0
0
0
1
×
×
×
× fCLK/2
16 MHz
0
0
1
0
×
×
×
× fCLK/22
8 MHz
0
0
1
1
×
×
×
× fCLK/23
4 MHz
0
1
0
0
×
×
×
× fCLK/24
2 MHz
0
1
0
1
×
×
×
× fCLK/25
1 MHz
0
1
1
0
×
×
×
× fCLK/26
500 kHz
0
1
1
1
×
×
×
× fCLK/27
250 kHz
1
0
0
0
×
×
×
× fCLK/28
125 kHz
1
0
0
1
×
×
×
× fCLK/29
62.5 kHz
1
0
1
0
×
×
×
× fCLK/210
31.25 kHz
1
0
1
1
×
×
×
× fCLK/211
15.63 kHz
Other than above
Setting prohibited
Note
When changing the clock selected for fCLK (by changing the system clock control register (CKC) value), do so after having stopped (serial channel stop register m (STm) = 000FH) the operation of the serial array unit (SAU).
Remark 1. ×: Don't care Remark 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Here is an example of setting an I2C transfer rate where fMCK = fCLK = 32 MHz.
I2C Transfer Mode (Desired Transfer Rate)
Operation Clock (fMCK)
fCLK = 32 MHz
SDRmn[15:9]
Calculated Transfer Rate
Error from Desired Transfer Rate
100 kHz
fCLK/2
79
100 kHz
0.0%
400 kHz
fCLK
41
380 kHz
5.0%Note
1 MHz
fCLK
18
0.84 MHz
16.0%Note
Note
The error cannot be set to about 0% because the duty ratio of the SCL signal is 50%.
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CHAPTER 15 SERIAL ARRAY UNIT (SAU)
15.8.6
Procedure for Processing Errors that Occurred during Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) Communication
The procedure for processing errors that occurred during simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) communication is described in Figure 15 - 118 and Figure 15 - 119.
Figure 15 - 118 Processing Procedure in Case of Overrun Error
Software Manipulation
State of the Hardware
Remark
Reads serial data register mn (SDRmn). Reads serial status register mn (SSRmn).
The BFFmn bit of the SSRmn register is set This is to prevent an overrun error if the
to 0 and channel n is enabled to receive next reception is completed during error
data
processing.
The error type is identified and the read value is used to clear the error flag.
Writes 1 to serial flag clear trigger register The error flag is cleared. mn (SIRmn).
Only the error during reading can be cleared, by writing the value read from the SSRmn register to the SIRmn register without modification.
Figure 15 - 119 Processing Procedure in Case of ACK Error in Simplified I2C Mode
Software Manipulation
State of the Hardware
Remark
Reads serial status register mn (SSRmn).
The error type is identified and the read value is used to clear the error flag.
Writes serial flag clear trigger register mn The error flag is cleared. (SIRmn).
Only the error during reading can be cleared, by writing the value read from the SSRmn register to the SIRmn register without modification.
Sets the STmn bit of serial channel stop register m (STm) to 1.
The SEmn bit of serial channel enable status register m (SEm) is set to 0 and channel n stops operation.
Creates a stop condition. Creates a start condition.
The slave is not ready for reception because ACK is not returned. Therefore, a stop condition is created, the bus is released, and communication is started again from the start condition. Or, a restart condition is generated and transmission can be redone from address transmission.
Sets the SSmn bit of serial channel start register m (SSm) to 1.
The SEmn bit of serial channel enable status register m (SEm) is set to 1 and channel n is enabled to operate.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31),
mn = 00 to 03, 10 to 13
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
CHAPTER 16 SERIAL INTERFACE IICA (IICA)
The number of the serial Interface IICA channels depends on the product.
Number of serial interface channels
30-, 32-, 36-, and 40-pin products 1
44-, 48-, 52-, 56-, 64-, 80-, 100-, and 128-pin products 2
16.1
Functions of Serial Interface IICA
The serial interface IICA has the following three modes.
(1) Operation stop mode This mode is used when serial transfers are not performed. The operating power can be reduced in this mode.
(2) I2C bus mode (multimaster supported) This mode is used for 8-bit data transfers with several devices via two lines: a serial clock (SCLAn) line and a serial data bus (SDAAn) line. This mode complies with the I2C bus format and the master device can send start conditions, addresses, transfer directions, acknowledges (ACK), data, and stop conditions to the slave devices, via the serial data bus. The slave device automatically detects these states and data by hardware. This function can simplify the part of application program that controls the I2C bus. Since the SCLAn and SDAAn pins are used for open drain outputs, serial interface IICA requires pull-up resistors for the serial clock line and the serial data bus line.
(3) Wakeup mode The STOP mode can be released by generating an interrupt request signal (INTIICAn) when an extension code from the master device or the local address has been received while in STOP mode. This can be set by using the WUPn bit of IICA control register n1 (IICCTLn1). The all address match function is enabled by setting the SVADISn bit of the ICCTLn1 register to 1, allowing any received address is to be determined as a matched address. Figure 16 - 1 shows a block diagram of serial interface IICA.
Remark n = 0, 1
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RL78/G23 Figure 16 - 1 Block Diagram of Serial Interface IICA0
CHAPTER 16 SERIAL INTERFACE IICA (IICA)
SDAA0/ P61
WUP0
STOP mode controller
Internal bus
IICA status register 0 (IICS0)
IICA control register 00 (IICCTL00)
MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0
IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0
Filter
Noise eliminator DFC0
Slave address register 0 (SVA0)
Match signal
Clear Set
IICA shift register 0 (IICA0)
SO latch DQ
IICWL0
Start Condition generator
Stop Condition generator
IICCTL01.SVADIS0
N-ch opendrain output
PM61
Output Latch (P61)
TRC0 Output control
Data hold time correction
circuit
ACK detector
ACK generator
Wakeup controller
SCLA0/ P60
Filter
Noise eliminator DFC0
N-ch opendrain output
PM60
fCLK
Output Latch (P60)
fCLK/2
IICCTL01.PRS0
Selector
Start condition detector
Stop condition detector
Serial clock counter
Serial clock controller
fMCK Counter
Match signal
Clock stretch controller
Interrupt request signal generator
INTIICA0
IICS0.MSTS0, EXC0, COI0
IICA shift register 0 (IICA0)
IICCTL00.STT0, SPT0 IICS0.MSTS0, EXC0, COI0
Bus state detector
IICA low-level width setting register 0 (IICWL0)
IICA high-level width setting register 0 (IICWH0)
WUP0 CLD0 DAD0 SMC0 DFC0 PRS0
Internal bus
IICA control register 01 (IICCTL01)
STCF0 IICBSY0 STCEN0 IICRSV0
IICA flag register 0 (IICF0)
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
Figure 16 - 2 shows a serial bus configuration example. Figure 16 - 2 Example of the Serial Bus Configuration Using the I2C Bus
Master CPU1 Slave CPU1 Address 0
Serial data bus SDAAn
Serial clock SCLAn
+ VDD + VDD
SDAAn SCLAn
Master CPU2 Slave CPU2 Address 1
SDAAn SCLAn
Slave CPU3 Address 2
SDAAn SCLAn
Slave IC Address 3
Remark n = 0, 1
SDAAn SCLAn
Slave IC Address N
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
16.2
Configuration of Serial Interface IICA
Serial interface IICA includes the following hardware.
Table 16 - 1 Configuration of Serial Interface IICA
Item
Configuration
Registers
IICA shift register n (IICAn) Slave address register n (SVAn)
Control registers
Peripheral enable register 0 (PER0) Peripheral reset control register 0 (PRR0) IICA control register n0 (IICCTLn0) IICA status register n (IICSn) IICA flag register n (IICFn) IICA control register n1 (IICCTLn1) IICA low-level width setting register n (IICWLn) IICA high-level width setting register n (IICWHn) Port mode register 6 (PM6) Port register 6 (P6)
Remark n = 0, 1
(1) IICA shift register n (IICAn) The IICAn register is used to convert 8-bit serial data to 8-bit parallel data and vice versa in synchronization with the serial clock. The IICAn register can be used for both transmission and reception. The actual transmit and receive operations can be controlled by writing to and reading from the IICAn register. Release serial interface IICA from the clock stretch state and start data transfer by writing data to the IICAn register during the clock stretch period. The IICAn register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 16 - 3 Format of IICA Shift Register n (IICAn)
Address: FFF50H (IICA0), FFF54H (IICA1)
After reset: 00H
R/W:
R/W
Symbol
7
6
5
4
3
2
1
0
IICAn
Caution 1. Do not write data to the IICAn register during data transfer. Caution 2. Write to or read from the IICAn register only during the clock stretch period. Accessing the IICAn
register in a communication state other than during the clock stretch period is prohibited. When the device serves as the master, however, the IICAn register can be written only once after the communication trigger bit (STTn) is set to 1. Caution 3. When communication is reserved, write data to the IICAn register after the interrupt triggered by a stop condition is detected.
Remark n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
(2) Slave address register n (SVAn) This register holds seven bits (A6, A5, A4, A3, A2, A1, and A0) of the local address when in slave mode. The SVAn register can be set by an 8-bit memory manipulation instruction. However, rewriting to this register is prohibited while STDn = 1 (while the start condition is detected). The value of this register is 00H following a reset.
Figure 16 - 4 Format of Slave Address Register n (SVAn)
Address: F0234H (SVA0), F023CH (SVA1)
After reset: 00H
R/W:
R/W
Symbol
7
6
5
4
3
2
1
0
SVAn
A6
A5
A4
A3
A2
A1
A0
0Note
Note
Bit 0 is fixed to 0.
(3) SO latch The SO latch is used to retain the SDAAn pin's output level.
(4) Wakeup controller This circuit generates an interrupt request signal (INTIICAn) when the received address matches the address value set to the slave address register n (SVAn), when any address is received while the all address match function is enabled, or when an extension code is received.
(5) Serial clock counter This counter counts the serial clock cycles that are output or input during transmit/receive operations and is used to verify that 8-bit data was transmitted or received.
(6) Interrupt request signal generator This circuit controls the generation of interrupt request signals (INTIICAn). An I2C interrupt request is generated by the following two triggers. · Falling edge of eighth or ninth clock of the serial clock (set by the WTIMn bit) · Interrupt request generated when a stop condition is detected (set by the SPIEn bit)
Remark WTIMn bit: Bit 3 of IICA control register n0 (IICCTLn0) SPIEn bit: Bit 4 of IICA control register n0 (IICCTLn0)
(7) Serial clock controller In master mode, this circuit generates the serial clock, which is output via the SCLAn pin.
(8) Clock stretch controller This circuit controls the timing of clock stretching.
Remark n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
(9) ACK generator, stop condition detector, start condition detector, and ACK detector These circuits generate or detect each state.
(10) Data hold time correction circuit This circuit generates the hold time for data after the falling edge of the serial clock.
(11) Start condition generator This circuit generates a start condition when the STTn bit is set to 1. However, while communication reservations are disabled (IICRSVn bit = 1) and the bus is busy (IICBSYn bit = 1), start condition requests are ignored and the STCFn bit is set to 1.
(12) Stop condition generator This circuit generates a stop condition when the SPTn bit is set to 1.
(13) Bus state detector This circuit detects whether or not the bus is released by detecting start conditions and stop conditions. However, as the bus state cannot be detected immediately after the IICA operation is enabled, the initial state is set by the STCENn bit.
Remark 1. STTn bit: Bit 1 of IICA control register n0 (IICCTLn0) SPTn bit: Bit 0 of IICA control register n0 (IICCTLn0) IICRSVn bit: Bit 0 of IICA flag register n (IICFn) IICBSYn bit: Bit 6 of IICA flag register n (IICFn) STCFn bit: Bit 7 of IICA flag register n (IICFn) STCENn bit: Bit 1 of IICA flag register n (IICFn)
Remark 2. n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
16.3
Registers to Control Serial Interface IICA
The following registers are used to control serial interface IICA.
· Peripheral enable register 0 (PER0) · Peripheral reset control register 0 (PRR0) · IICA control register n0 (IICCTLn0) · IICA status register n (IICSn) · IICA flag register n (IICFn) · IICA control register n1 (IICCTLn1) · IICA low-level width setting register n (IICWLn) · IICA high-level width setting register n (IICWHn) · Port mode registers (PMxx) · Port registers (Pxx)
Remark n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
16.3.1 Peripheral enable register 0 (PER0)
The PER0 register is used to enable or disable the supply of a clock signal to various on-chip peripheral modules. Clock supply to an on-chip peripheral module that is not to be used can be stopped to decrease power consumption and noise. When serial interface IICAn is to be used, be sure to set bits 6 and 4 (IICA1EN and IICA0EN) of this register to 1. The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 16 - 5 Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H
After reset: 00H
R/W:
R/W
Symbol
<7>
PER0 RTCWEN
<6> IICA1EN
<5> ADCEN
<4> IICA0EN
<3> SAU1EN
<2> SAU0EN
<1> TAU1EN
<0> TAU0EN
IICAnEN
Control of supply of an input clock to the serial interface IICAn
0
Stops supply of an input clock.
· The SFRs used by the serial interface IICAn cannot be written.
· When an SFR used by the serial interface IICAn is read, the value returned is 00H or 0000H.
1
Enables supply of an input clock.
· The SFRs used by the serial interface IICAn can be read and written.
Caution 1. When setting serial interface IICA, make sure that the setting of the IICAnEN bit is 1 before setting the following registers. If IICAnEN = 0, the values of the registers which control the serial interface IICA are cleared to their initial values, and writing to them is ignored (except for port mode register 6 (PM6) and port register 6 (P6)). · IICA control register n0 (IICCTLn0) · IICA flag register n (IICFn) · IICA status register n (IICSn) · IICA control register n1 (IICCTLn1) · IICA low-level width setting register n (IICWLn) · IICA high-level width setting register n (IICWHn)
Caution 2. For details about notes on the number of pins, see CHAPTER 6 CLOCK GENERATOR. Caution 3. While the operation of a peripheral function is enabled, do not switch the setting of the corresponding
bit in the PER0 register. When switching the setting by the PER0 register, each peripheral function assigned to the PER0 register must be stopped.
Remark n = 0, 1
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16.3.2 Peripheral reset control register 0 (PRR0)
The PRR0 register is used to control resetting of the on-chip peripheral modules. Use bits 6 and 4 (IICA1RES, IICA0RES) of the PRR0 register to control reset or release from the reset for the corresponding serial interfaces IICA1 and IICA0.
Figure 16 - 6 Format of Peripheral Reset Control Register 0 (PRR0)
Address: F00F1H
After reset: 00H
R/W:
R/W
Symbol
7
PRR0
0
<6>
<5>
<4>
<3>
<2>
<1>
<0>
IICA1RES ADCRES IICA0RES SAU1RES SAU0RES TAU1RES TAU0RES
IICAnRES
Control resetting of the serial interface IICAn
0
Serial interface IICAn is released from the reset state.
1
Serial interface IICAn is in the reset state.
· The SFRs for use with the serial interface IICAn are initialized.
Remark n = 0, 1
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16.3.3 IICA control register n0 (IICCTLn0)
This register is used to enable or disable the I2C operations, set the timing of clock stretching, and set other I2C operations. The IICCTLn0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Note that bits SPIEn, WTIMn, and ACKEn must be set while the setting of IICEn is 0 or this module is in the clock stretch state. These bits can be set at the same time as setting the IICEn bit 1. The value of this register is 00H following a reset.
Remark n = 0, 1
Figure 16 - 7 Format of IICA Control Register n0 (IICCTLn0) (1/5)
Address: F0230H (IICCTL00), F0238H (IICCTL10)
After reset: 00H
R/W:
R/W
Symbol
<7>
<6>
<5>
IICCTLn0 IICEn
LRELn
WRELn
<4> SPIEn
<3> WTIMn
<2> ACKEn
<1> STTn
<0> SPTn
IICEn
I2C operation enable
0
Stop operation. Reset the IICA status register n (IICSn)Note. Stop internal operation.
1
Enable operation.
Be sure to set this bit (1) while the SCLAn and SDAAn lines are at high level.
Condition for clearing (IICEn = 0)
Condition for setting (IICEn = 1)
· Cleared by instruction · Reset
· Set by instruction
Note
The IICA status register n (IICSn), the STCFn and IICBSYn bits of the IICA flag register n (IICFn), and the CLDn and DADn bits of IICA control register n1 (IICCTLn1) are reset.
Caution
If the operation of I2C is enabled (IICEn = 1) when the SCLAn line is high level, the SDAAn line is low level, and the digital filter is turned on (DFCn bit of IICCTLn1 register = 1), a start condition will be inadvertently detected immediately. In this case, set (1) the LRELn bit by using a 1-bit memory manipulation instruction immediately after enabling operation of I2C (IICEn = 1).
Remark n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
Figure 16 - 7 Format of IICA Control Register n0 (IICCTLn0) (2/5)
LRELn
Notes 1, 2
Exit from communications
0
Normal operation
1
IICA exits from the current communications and sets standby mode. This setting is
automatically cleared to 0 after being executed.
Its uses include cases in which a locally irrelevant extension code has been received.
The SCLAn and SDAAn lines are set to high impedance.
The following flags of IICA control register n0 (IICCTLn0) and the IICA status register n (IICSn)
are cleared to 0.
· STTn · SPTn · MSTSn · EXCn · COIn · TRCn · ACKDn · STDn
The standby mode following exit from communications remains in effect until the following communications
entry conditions are met.
· After a stop condition is detected, restart is in master mode.
· An address match, extension code reception, or address reception with the all address match function
enabled occurs after the start condition.
Condition for clearing (LRELn = 0)
Condition for setting (LRELn = 1)
· Automatically cleared after execution
· Set by instruction
· Reset
WRELn
Notes 1, 2
Release from the clock stretch state
0
The interface is not released from the clock stretch state.
1
The interface is released from the clock stretch state. After release from the clock stretch
state, this bit is automatically cleared to 0.
When the WRELn bit is set (for release from the clock stretch state) during the clock stretch period at the
ninth clock pulse in the transmission state (TRCn = 1), the SDAAn line goes into the high impedance state
(TRCn = 0).
Condition for clearing (WRELn = 0)
Condition for setting (WRELn = 1)
· Automatically cleared after execution
· Set by instruction
· Reset
SPIEnNote 1
Enable/disable generation of interrupt request when stop condition is detected
0
Disable
1
Enable
If the WUPn bit of IICA control register n1 (IICCTLn1) is 1, no stop condition interrupt will be generated even if SPIEn = 1.
Condition for clearing (SPIEn = 0)
Condition for setting (SPIEn = 1)
· Cleared by instruction · Reset
· Set by instruction
Note 1. Note 2.
The setting of this bit has no effect while the setting of IICEn is 0. Reading the LRELn and WRELn bits always returns 0.
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Caution
If the operation of I2C is enabled (IICEn = 1) when the SCLAn line is high level, the SDAAn line is low level, and the digital filter is turned on (DFCn bit of IICCTLn1 register = 1), a start condition will be inadvertently detected immediately. In this case, set (1) the LRELn bit by using a 1-bit memory manipulation instruction immediately after enabling operation of I2C (IICEn = 1).
Remark n = 0, 1
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Figure 16 - 7 Format of IICA Control Register n0 (IICCTLn0) (3/5)
WTIMn
Note 1
Control of clock stretching and interrupt request generation
0
An interrupt request is generated on the falling edge of the eighth clock cycle.
Master mode: After the output of eight clock pulses, the clock output is set to the low level and
clock stretching is set.
Slave mode: After the input of eight clock pulses, the clock is set to the low level and clock
stretching is set for the master device.
1
An interrupt request is generated on the falling edge of the ninth clock cycle.
Master mode: After the output of nine clock pulses, the clock output is set to the low level and
clock stretching is set.
Slave mode: After the input of nine clock pulses, the clock is set to the low level and clock
stretching is set for the master device.
An interrupt is generated on the falling edge of the ninth clock cycle during address transfer independently of
the setting of this bit. The setting of this bit is valid when the address transfer is completed. In master mode,
clock stretching is inserted at the falling edge of the ninth clock cycle during address transfer. For a slave
device that has received a local address, clock stretching is inserted at the falling edge of the ninth clock
cycle after an acknowledge (ACK) is issued. However, if the slave device has received an extension code,
clock stretching is inserted at the falling edge of the eighth clock cycle. When an address is received while
the all address match function is enabled, clock stretching is inserted at the falling edge of the eighth clock
cycle.
Condition for clearing (WTIMn = 0)
Condition for setting (WTIMn = 1)
· Cleared by instruction
· Set by instruction
· Reset
ACKEn
Notes 1, 2
Acknowledgment control
0
Disable acknowledgment.
1
Enable acknowledgment. During the ninth clock period, the SDAAn line is set to low level.
Condition for clearing (ACKEn = 0)
Condition for setting (ACKEn = 1)
· Cleared by instruction · Reset
· Set by instruction
Note 1. Note 2.
The signal of this bit is invalid while IICEn is 0. Set this bit during that period. The set value is invalid during address transfer and if the code is not an extension code, and the all address match function is disabled. When the device serves as a slave and the addresses match, an acknowledgment is generated regardless of the set value.
Remark n = 0, 1
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Figure 16 - 7 Format of IICA Control Register n0 (IICCTLn0) (4/5)
STTn
Notes 1, 2
0 1
Start condition trigger
Do not generate a start condition. When bus is released (in standby state, when IICBSYn = 0): If this bit is set (1), a start condition is generated (startup as the master). When a third party is communicating: · When communication reservation function is enabled (IICRSVn = 0)
Functions as the start condition reservation flag. When set to 1, automatically generates a start condition after the bus is released.
· When communication reservation function is disabled (IICRSVn = 1)
Even if this bit is set (1), the STTn bit is cleared and the STTn clear flag (STCFn) is set (1). No start condition is generated.
In the clock stretch state (for a master device):
Generates a restart condition after release from the clock stretch state.
Cautions concerning set timing
· For master reception: Cannot be set to 1 during transfer. Can be set to 1 only during the clock stretch
period when the ACKEn bit has been cleared to 0 and slave has been notified of
final reception.
· For master transmission: A start condition cannot be generated normally during the acknowledge period.
Set to 1 during the clock stretch period that follows output of the ninth clock.
· Cannot be set to 1 at the same time as stop condition trigger (SPTn).
· Once STTn is set (1), setting it again (1) before the clear condition is met is not allowed.
Condition for clearing (STTn = 0)
Condition for setting (STTn = 1)
· Cleared by setting the STTn bit to 1 while
· Set by instruction
communication reservation is prohibited.
· Cleared by loss in arbitration
· Cleared after start condition is generated by master
device
· Cleared by LRELn = 1 (exit from communications)
· When IICEn = 0 (operation stop)
· Reset
Note 1. Note 2.
The signal of this bit is invalid while IICEn is 0. The STTn bit is always read as 0.
Remark 1. IICRSVn: Bit 0 of IIC flag register n (IICFn) STCFn: Bit 7 of IIC flag register n (IICFn)
Remark 2. n = 0, 1
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Figure 16 - 7 Format of IICA Control Register n0 (IICCTLn0) (5/5)
SPTnNote
Stop condition trigger
0
Stop condition is not generated.
1
Stop condition is generated (termination of master device's transfer).
Cautions concerning set timing · For master reception: Cannot be set to 1 during transfer.
Can be set to 1 only during the clock stretch period when the ACKEn bit has
been cleared to 0 and slave has been notified of final reception.
· For master transmission: A stop condition cannot be generated normally during the acknowledge period. Therefore, set it during the clock stretch period that follows output of the ninth clock.
· Cannot be set to 1 at the same time as start condition trigger (STTn). · The SPTn bit can be set to 1 only when in master mode.
· When the WTIMn bit has been cleared to 0, if the SPTn bit is set to 1 during the clock stretch period that
follows output of eight clock pulses, note that a stop condition will be generated during the high-level period of the ninth clock after release from the clock stretch state. The WTIMn bit should be changed from 0 to 1 during the clock stretch period following the output of eight clock pulses, and the SPTn bit should be set to 1 during the clock stretch period that follows the output of the ninth clock. · Once SPTn is set (1), setting it again (1) before the clear condition is met is not allowed.
Condition for clearing (SPTn = 0)
Condition for setting (SPTn = 1)
· Cleared by loss in arbitration
· Set by instruction
· Automatically cleared after stop condition is
detected · Cleared by LRELn = 1 (exit from communications) · When IICEn = 0 (operation stop) · Reset
Note
The SPTn bit is always read as 0.
Caution
When bit 3 (TRCn) of the IICA status register n (IICSn) is set to 1 (transmission state), bit 5 (WRELn) of IICA control register n0 (IICCTLn0) is set to 1 during the ninth clock and the interface is released from the clock stretch state, after which the TRCn bit is cleared (reception state) and the SDAAn line is set to the high impedance state. Release the interface from the clock stretch state while the TRCn bit is 1 (transmission state) by writing to the IICA shift register n.
Remark 1. Bit 0 (SPTn) becomes 0 when it is read after data setting. Remark 2. n = 0, 1
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16.3.4 IICA status register n (IICSn)
This register indicates the state of the I2C. The IICSn register can only be read by a 1-bit or 8-bit memory manipulation instruction while the setting of STTn is 1 or this module is in the clock stretch state. The value of this register is 00H following a reset.
Caution Remark
Reading the IICSn register while the address match wakeup function is enabled (WUPn = 1) in STOP mode is prohibited. When the WUPn bit is changed from 1 to 0 (wakeup operation is stopped), regardless of the INTIICAn interrupt request signal, the change in status is not reflected until the next start condition or stop condition is detected. To use the wakeup function, therefore, enable (SPIEn = 1) the interrupt generated by detecting a stop condition and read the IICSn register after the interrupt has been detected.
STTn: Bit 1 of IICA control register n0 (IICCTLn0)
WUPn: Bit 7 of IICA control register n1 (IICCTLn1)
Figure 16 - 8 Format of IICA Status Register n (IICSn) (1/4)
Address: FFF51H (IICS0), FFF55H (IICS1)
After reset: 00H
R/W:
R
Symbol
<7>
<6>
<5>
IICSn MSTSn
ALDn
EXCn
<4> COIn
<3> TRCn
<2> ACKDn
<1> STDn
<0> SPDn
MSTSn
Master status check flag
0
Slave device status or communication standby status
1
Master device communication status
Condition for clearing (MSTSn = 0)
Condition for setting (MSTSn = 1)
· When a stop condition is detected
· When a start condition is generated
· When ALDn = 1 (arbitration loss)
· Cleared by LRELn = 1 (exit from communications)
· When the IICEn bit changes from 1 to 0 (operation
stop)
· Reset
ALDn
Detection of arbitration loss
0
This status means either that there was no arbitration, or that the arbitration result was a "win".
1
This status indicates the arbitration result was a "loss". The MSTSn bit is cleared.
Condition for clearing (ALDn = 0)
Condition for setting (ALDn = 1)
· Automatically cleared after the IICSn register is readNote
· When the arbitration result is a "loss".
· When the IICEn bit changes from 1 to 0 (operation stop)
· Reset
Note
The ALDn bit is also cleared when a 1-bit memory manipulation instruction is executed for another bit in the IICSn register. Therefore, when using the ALDn bit, read the data of this bit before the data of the other bits.
Remark 1. LRELn: Bit 6 of IICA control register n0 (IICCTLn0) IICEn: Bit 7 of IICA control register n0 (IICCTLn0)
Remark 2. n = 0, 1
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Figure 16 - 8 Format of IICA Status Register n (IICSn) (2/4)
EXCn
Detection of extension code reception
0
Extension code was not received.
1
Extension code was received. Or, the all address match function is enabled.
Condition for clearing (EXCn = 0)
Condition for setting (EXCn = 1)
· When a start condition is detected
· When the higher four bits of the received address
· When a stop condition is detected
data is either "0000" or "1111" (set at the rising edge
· Cleared by LRELn = 1 (exit from communications) of the eighth clock).
· When the IICEn bit changes from 1 to 0 (operation · When an address is received while the all address
stop)
match function is enabled (IICCTLn1.SVADISn = 1)
· Reset
(set at the rising edge of the eighth clock).
COIn
Detection of matching addresses
0
Addresses do not match.
1
Addresses match. Or, the all address match function is enabled.
Condition for clearing (COIn = 0)
Condition for setting (COIn = 1)
· When a start condition is detected
· When the received address matches the local
· When a stop condition is detected
address (slave address register n (SVAn)) (set at
· Cleared by LRELn = 1 (exit from communications) the rising edge of the eighth clock).
· When the IICEn bit changes from 1 to 0 (operation · When an address is received while the all address
stop)
match function is enabled (IICCTLn1.SVADISn = 1)
· Reset
(set at the rising edge of the eighth clock).
Remark 1. LRELn: Bit 6 of IICA control register n0 (IICCTLn0) IICEn: Bit 7 of IICA control register n0 (IICCTLn0)
Remark 2. n = 0, 1
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Figure 16 - 8 Format of IICA Status Register n (IICSn) (3/4)
TRCn
Detection of transmit/receive status
0
Receive status (other than transmit status). The SDAAn line is set for high impedance.
1
Transmit status. The value in the SOn latch is enabled for output to the SDAAn line (valid
starting at the falling edge of the first byte's ninth clock).
Condition for clearing (TRCn = 0)
Condition for setting (TRCn = 1)
<Both master and slave> · When a stop condition is detected
<Master> · When a start condition is generated
· Cleared by LRELn = 1 (exit from communications) · When 0 (master transmission) is output to the LSB
· When the IICEn bit changes from 1 to 0 (operation (transfer direction specification bit) of the first byte
stop)
(during address transfer)
· Cleared by WRELn = 1Note (release from the clock <Slave>
stretch state)
· When 1 (slave transmission) is input to the LSB
· When the ALDn bit changes from 0 to 1 (arbitration (transfer direction specification bit) of the first byte
loss)
from the master (during address transfer)
· Reset
· When not used for communication (MSTSn, EXCn, COIn = 0)
<Master> · When "1" is output to the first byte's LSB (transfer
direction specification bit)
<Slave> · When a start condition is detected · When "0" is input to the first byte's LSB (transfer
direction specification bit)
Note
When bit 3 (TRCn) of the IICA status register n (IICSn) is set to 1 (transmission state), bit 5 (WRELn) of IICA control register n0 (IICCTLn0) is set to 1 during the ninth clock and the interface is released from the clock stretch state, after which the TRCn bit is cleared (reception state) and the SDAAn line is set to the high impedance state. Release the interface from the clock stretch state while the TRCn bit is 1 (transmission state) by writing to the IICA shift register n.
Remark 1. LRELn: Bit 6 of IICA control register n0 (IICCTLn0) IICEn: Bit 7 of IICA control register n0 (IICCTLn0)
Remark 2. n = 0, 1
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Figure 16 - 8 Format of IICA Status Register n (IICSn) (4/4)
ACKDn
Detection of acknowledge (ACK)
0
Acknowledge was not detected.
1
Acknowledge was detected.
Condition for clearing (ACKDn = 0)
Condition for setting (ACKDn = 1)
· When a stop condition is detected
· After the SDAAn line is set to low level at the rising
· At the rising edge of the next byte's first clock
edge of SCLAn line's ninth clock
· Cleared by LRELn = 1 (exit from communications)
· When the IICEn bit changes from 1 to 0 (operation
stop)
· Reset
STDn
Detection of start condition
0
Start condition was not detected.
1
Start condition was detected. This indicates that the address transfer period is in effect.
Condition for clearing (STDn = 0)
Condition for setting (STDn = 1)
· When a stop condition is detected
· When a start condition is detected
· At the rising edge of the next byte's first clock
following address transfer
· Cleared by LRELn = 1 (exit from communications)
· When the IICEn bit changes from 1 to 0 (operation
stop)
· Reset
SPDn
Detection of stop condition
0
Stop condition was not detected.
1
Stop condition was detected. The master device's communication is terminated and the bus is
released.
Condition for clearing (SPDn = 0)
Condition for setting (SPDn = 1)
· At the rising edge of the address transfer byte's first · When a stop condition is detected clock following setting of this bit and detection of a start condition
· When the WUPn bit changes from 1 to 0 · When the IICEn bit changes from 1 to 0 (operation
stop) · Reset
Remark 1. LRELn: Bit 6 of IICA control register n0 (IICCTLn0) IICEn: Bit 7 of IICA control register n0 (IICCTLn0)
Remark 2. n = 0, 1
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16.3.5 IICA flag register n (IICFn)
This register sets the operation mode of I2C and indicates the state of the I2C bus. The IICFn register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the STTn clear flag (STCFn) and I2C bus status flag (IICBSYn) bits are read-only. The IICRSVn bit can be used to enable or disable the communication reservation. The STCENn bit can be used to set the initial value of the IICBSYn bit. The IICRSVn and STCENn bits can be written only when the operation of I2C is disabled (bit 7 (IICEn) of IICA control register n0 (IICCTLn0) = 0). The IICFn register is read-only while the operation of the I2C is enabled. The value of this register is 00H following a reset.
Figure 16 - 9 Format of IICA Flag Register n (IICFn) (1/2)
Address: FFF52H (IICF0), FFF56H (IICF1)
After reset: 00H
R/W:
R/WNote
Symbol
<7>
<6>
5
4
3
IICFn STCFn IICBSYn
0
0
0
2
<1>
<0>
0
STCENn IICRSVn
STCFn
STTn clear flag
0
Generate start condition
1
Start condition generation unsuccessful: clear the STTn flag
Condition for clearing (STCFn = 0)
Condition for setting (STCFn = 1)
· Cleared by STTn = 1 · When IICEn = 0 (operation stop) · Reset
· Generating start condition unsuccessful and the STTn bit cleared to 0 when communication reservation is disabled (IICRSVn = 1).
IICBSYn
I2C bus status flag
0
Bus release status (communication initial status when STCENn = 1)
1
Bus communication status (communication initial status when STCENn = 0)
Condition for clearing (IICBSYn = 0)
Condition for setting (IICBSYn = 1)
· When a stop condition is detected · When IICEn = 0 (operation stop) · Reset
· When a start condition is detected · Setting of the IICEn bit when STCENn = 0
Note
Bits 7 and 6 are read-only.
Remark 1. STTn: Bit 1 of IICA control register n0 (IICCTLn0) Remark 2. IICEn: Bit 7 of IICA control register n0 (IICCTLn0) Remark 3. n = 0, 1
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Figure 16 - 9 Format of IICA Flag Register n (IICFn) (2/2)
STCENn
Initial start enable trigger
0
After operation is enabled (IICEn = 1), enable generation of a start condition upon detection of
a stop condition.
1
After operation is enabled (IICEn = 1), enable generation of a start condition without detecting
a stop condition.
Condition for clearing (STCENn = 0)
Condition for setting (STCENn = 1)
· Cleared by instruction · When a start condition is detected · Reset
· Set by instruction
IICRSVn
Communication reservation function disable bit
0
Enable communication reservation
1
Disable communication reservation
Condition for clearing (IICRSVn = 0)
Condition for setting (IICRSVn = 1)
· Cleared by instruction · Reset
· Set by instruction
Caution 1. Write to the STCENn bit only when the operation is stopped (IICEn = 0). Caution 2. As the bus release status (IICBSYn = 0) is recognized regardless of the actual bus status when
STCENn = 1. When generating the first start condition (STTn = 1), it is necessary to verify that no third party communications are in progress in order to prevent such communications from being destroyed. Caution 3. Write to the IICRSVn bit only when the operation is stopped (IICEn = 0).
Remark 1. STTn: Bit 1 of IICA control register n0 (IICCTLn0) Remark 2. IICEn: Bit 7 of IICA control register n0 (IICCTLn0) Remark 3. n = 0, 1
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16.3.6 IICA control register n1 (IICCTLn1)
This register is used to set the operation mode of I2C and detect the states of the SCLAn and SDAAn pins. The IICCTLn1 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the CLDn and DADn bits are read-only. Set the IICCTLn1 register, except the WUPn bit, while operation of I2C is disabled (bit 7 (IICEn) of IICA control register n0 (IICCTLn0) is 0). The value of this register is 00H following a reset.
Figure 16 - 10 Format of IICA Control Register n1 (IICCTLn1) (1/3)
Address: F0231H (IICCTL01), F0239H (IICCTL11)
After reset: 00H
R/W:
R/WNote 1
Symbol
<7>
<6>
<5>
<4>
<3>
<2>
1
<0>
IICCTLn1 WUPn
SVADISn
CLDn
DADn
SMCn
DFCn
0
PRSn
WUPn
Control of address match wakeup
0
Stops operation of address match wakeup function in STOP mode.
1
Enables operation of address match wakeup function in STOP mode.
To shift to STOP mode when WUPn = 1, execute the STOP instruction at least three cycles of fMCK after setting (1) the WUPn bit (see Figure 16 - 22 Flow When Setting WUPn = 1). Clear (0) the WUPn bit after the address has matched, an address has been received while the all address match function is enabled, or an extension code has been received. The subsequent communication can be entered by the clearing (0) WUPn bit. (The interface must be released from the clock stretch state and transmit data must be written after the WUPn bit has been cleared (0).) The interrupt timing when the address has matched, when an address has been received while the all address match function is enabled, or when an extension code has been received, while WUPn = 1, is identical to the interrupt timing when WUPn = 0. (A delay of the difference of sampling by the clock will occur.) Furthermore, when WUPn = 1, a stop condition interrupt is not generated even if the SPIEn bit is set to 1.
Condition for clearing (WUPn = 0)
Condition for setting (WUPn = 1)
· Cleared by instruction (after address match, address reception with the all address match function enabled, or extension code reception)
· Set by instruction (when the MSTSn, EXCn, and COIn bits are "0", and the STDn bit also "0" (communication not entered))Note 2
Note 1. Note 2.
Bits 5 and 4 are read-only. The status of the IICA status register n (IICSn) must be checked and the WUPn bit must be set during the period shown below.
<1>
<2>
SCLAn
SDAAn
Remark n = 0, 1
A6 A5 A4 A3 A2 A1 A0 R/W
The maximum time from reading IICSn to setting WUPn is the period from <1> to <2>. Check the IICSn operation status and set WUPn during this period.
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Figure 16 - 10 Format of IICA Control Register n1 (IICCTLn1) (2/3)
SVADISn
Address match disabling flag
0
Disables the all address match function.
1
Enables the all address match function.
When SVADISn = 1, IICA considers any address as address match, and performs the same operation as
that when an extension code is received.
Therefore, IICSn.COIn is set to 1, and IICSn.EXCn is set to 1. For details about extension code reception, see 16.5.11 Extension Code.
CLDn
Detection of SCLAn pin level (valid only when IICEn = 1)
0
The SCLAn pin was detected at low level.
1
The SCLAn pin was detected at high level.
Condition for clearing (CLDn = 0)
Condition for setting (CLDn = 1)
· When the SCLAn pin is at low level · When IICEn = 0 (operation stop) · Reset
· When the SCLAn pin is at high level
DADn
Detection of SDAAn pin level (valid only when IICEn = 1)
0
The SDAAn pin was detected at low level.
1
The SDAAn pin was detected at high level.
Condition for clearing (DADn = 0)
Condition for setting (DADn = 1)
· When the SDAAn pin is at low level · When IICEn = 0 (operation stop) · Reset
· When the SDAAn pin is at high level
SMCn
Operation mode switching
0
Operates in standard mode (fastest transfer rate: 100 kbps).
1
Operates in fast mode (fastest transfer rate: 400 kbps) or fast mode plus (fastest transfer rate:
1 Mbps).
Caution 1. The fastest operation frequency of the IICA operation clock (fMCK) is 20 MHz (max.).
Set bit 0 (PRSn) of the IICA control register n1 (IICCTLn1) to "1" only when the fCLK exceeds 20 MHz.
Caution 2. Note the minimum fCLK operation frequency when setting the transfer clock.
The minimum fCLK operation frequency for serial interface IICA is determined according to the mode.
Fast mode:
fCLK = 3.5 MHz (min.)
Fast mode plus: fCLK = 10 MHz (min.)
Normal mode: fCLK = 1 MHz (min.)
Remark 1. IICEn: Bit 7 of IICA control register n0 (IICCTLn0) Remark 2. n = 0, 1
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Figure 16 - 10 Format of IICA Control Register n1 (IICCTLn1) (3/3)
DFCn
Digital filter operation control
0
Digital filter off.
1
Digital filter on.
Use the digital filter only in fast mode and fast mode plus.
The digital filter is used for noise elimination.
The transfer clock does not vary, regardless of the DFCn bit being set (1) or cleared (0).
PRSn
IICA operation clock (fMCK)
0
Selects fCLK (1 MHz fCLK 20 MHz).
1
Selects fCLK/2 (20 MHz < fCLK).
Caution 1. The fastest operation frequency of the IICA operation clock (fMCK) is 20 MHz (max.).
Set bit 0 (PRSn) of the IICA control register n1 (IICCTLn1) to "1" only when the fCLK exceeds 20 MHz.
Caution 2. Note the minimum fCLK operation frequency when setting the transfer clock.
The minimum fCLK operation frequency for serial interface IICA is determined according to the mode.
Fast mode:
fCLK = 3.5 MHz (min.)
Fast mode plus: fCLK = 10 MHz (min.)
Normal mode: fCLK = 1 MHz (min.)
Remark 1. IICEn: Bit 7 of IICA control register n0 (IICCTLn0) Remark 2. n = 0, 1
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16.3.7 IICA low-level width setting register n (IICWLn)
This register is used to set the low-level width (tLOW) of the SCLAn pin signal that is output by serial interface IICA and to control the SDAAn pin signal. The IICWLn register can be set by an 8-bit memory manipulation instruction. Set the IICWLn register while operation of I2C is disabled (bit 7 (IICEn) of IICA control register n0 (IICCTLn0) is 0). The value of this register is FFH following a reset. For details about setting the IICWLn register, see 16.4.2 Setting transfer clock by using IICWLn and IICWHn registers. The data hold time is one-quarter of the time set by the IICWLn register.
Figure 16 - 11 Format of IICA Low-Level Width Setting Register n (IICWLn)
Address: F0232H (IICWL0), F023AH (IICWL1)
After reset: FFH
R/W:
R/W
Symbol
7
6
5
4
3
2
1
0
IICWLn
16.3.8 IICA high-level width setting register n (IICWHn)
This register is used to set the high-level width of the SCLAn pin signal that is output by serial interface IICA and to control the SDAAn pin signal. The IICWHn register can be set by an 8-bit memory manipulation instruction. Set the IICWHn register while operation of I2C is disabled (bit 7 (IICEn) of IICA control register n0 (IICCTLn0) is 0). The value of this register is FFH following a reset.
Figure 16 - 12 Format of IICA High-Level Width Setting Register n (IICWHn)
Address: F0233H (IICWH0), F023BH (IICWH1)
After reset: FFH
R/W:
R/W
Symbol
7
6
5
4
3
2
1
0
IICWHn
Remark 1. For setting procedures of the transfer clock on master side and of the IICWLn and IICWHn registers on slave side, see 16.4.2 (1) and 16.4.2 (2), respectively.
Remark 2. n = 0, 1
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16.3.9 Registers to control the port function multiplexed with the IICA I/O pins
When the IICA serial interface is to be used, set up the port mode register (PMxx) and port register (Pxx) related to the port function multiplexed with the pins of the given IICA channel. For details, see 4.3.1 Port mode registers (PMxx) and 4.3.2 Port registers (Pxx). When using the P60/SCLA0 pin as clock I/O and the P61/SDAA0 pin as serial data I/O, clear PM60 and PM61, and the output latches of P60 and P61 to 0. Set the IICEn bit (bit 7 of IICA control register n0 (IICCTLn0)) to 1 before setting the output mode because the P60/SCLA0 and P61/SDAA0 pins output a low level (fixed) when the IICEn bit is 0.
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16.4
I2C Bus Mode Functions
16.4.1 Pin Configuration
The serial clock pin (SCLAn) and the serial data bus pin (SDAAn) are configured as follows. (1) SCLAn....This pin is used for serial clock input and output.
This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. (2) SDAAn....This pin is used for serial data input and output.
This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. Since outputs from the serial clock line and the serial data bus line are N-ch open-drain outputs, an external pull-up resistor is required.
Figure 16 - 13 Pin Configuration Diagram
Master device
Clock output VSS
(Clock input)
Data output VSS
Data input
VDD
SCLAn
SCLAn
VDD
SDAAn
SDAAn
Slave device
(Clock output) VSS
Clock input
Data output VSS
Data input
Remark n = 0, 1
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16.4.2 Setting transfer clock by using IICWLn and IICWHn registers
(1) Setting transfer clock on master side
fMCK
Transfer clock =
IICWL + IICWH + fMCK (tR + tF)
At this time, the optimal setting values of the IICWLn and IICWHn registers are as follows.
(The fractional parts of all setting values are rounded up.)
· When the fast mode
0.52
IICWLn =
× fMCK
Transfer clock
0.48
IICWHn = (
Transfer clock
- tR - tF) × fMCK
· When the normal mode
0.47
IICWLn =
× fMCK
Transfer clock
0.53
IICWHn = (
Transfer clock
- tR - tF) × fMCK
· When the fast mode plus
0.50
IICWLn =
× fMCK
Transfer clock
0.50
IICWHn = (
- tR - tF) × fMCK
Transfer clock
(2) Setting IICWLn and IICWHn registers on slave side (The fractional parts of all setting values are rounded up.)
· When the fast mode IICWLn = 1.3 µs × fMCK
IICWHn = (1.2 µs - tR - tF) × fMCK
· When the normal mode IICWLn = 4.7 µs × fMCK
IICWHn = (5.3 µs - tR - tF) × fMCK
· When the fast mode plus IICWLn = 0.50 µs × fMCK
IICWHn = (0.50 µs - tR - tF) × fMCK
Caution 1. Caution 2.
The fastest operation frequency of the IICA operation clock (fMCK) is 20 MHz (max.). Set bit 0 (PRSn)
of the IICA control register n1 (IICCTLn1) to "1" only when the fCLK exceeds 20 MHz.
Note the minimum fCLK operation frequency when setting the transfer clock. The minimum fCLK
operation frequency for serial interface IICA is determined according to the mode.
Fast mode:
fCLK = 3.5 MHz (min.)
Fast mode plus: fCLK = 10 MHz (min.)
Normal mode: fCLK = 1 MHz (min.)
(Remarks are listed on the next page.)
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Remark 1. Calculate the rise time (tR) and fall time (tF) of the SDAAn and SCLAn signals separately, because they differ
depending on the pull-up resistance and wire load.
Remark 2. IICWLn: IICA low-level width setting register n
IICWHn: IICA high-level width setting register n
tF:
SDAAn and SCLAn signal falling times
tR:
SDAAn and SCLAn signal rising times
fMCK: IICA operation clock frequency Remark 3. n = 0, 1
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16.5
I2C Bus Definitions and Control Methods
The following section describes the I2C bus's serial data communication format and the signals used by the I2C bus. Figure 16 - 14 shows the transfer timing for the "start condition", "address", "data", and "stop condition" output via the I2C bus's serial data bus.
Figure 16 - 14 I2C Bus Serial Data Transfer Timing
SCLAn
1-7
89
1-8
9
1-8
9
SDAAn
Start
Address R/W ACK
condition
Data ACK
Data
ACK Stop condition
The master device generates the start condition, slave address, and stop condition. The acknowledge (ACK) can be generated by either the master or slave device (normally, it is output by the device that receives 8-bit data). The serial clock (SCLAn) is continuously output by the master device. However, for the slave device, the period over which the SCLAn pin is at the low level can be extended and clock stretching can be inserted.
16.5.1 Start Conditions
When the SCLAn pin is at high level, changing the SDAAn pin from the high level to the low level generates a stop condition. A stop condition is a signal that the master device generates to the slave device when starting a serial transfer. When the device is used as a slave, start conditions can be detected.
Figure 16 - 15 Start Conditions
SCLAn H SDAAn
A start condition is output when bit 1 (STTn) of IICA control register n0 (IICCTLn0) is set (1) after a stop condition has been detected (SPDn: Bit 0 of the IICA status register n (IICSn) = 1). When a start condition is detected, bit 1 (STDn) of the IICSn register is set (1).
Remark n = 0, 1
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16.5.2 Address
The address is defined by the 7 bits of data that follow the start condition. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines. Therefore, each slave device connected via the bus lines must have a unique address. The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data matches the data values stored in the slave address register n (SVAn). If the address data matches the SVAn register values, the slave device is selected and communicates with the master device until the master device generates a start condition or stop condition.
Figure 16 - 16 Addresses
SCLAn
1
2
3
4
5
6
7
8
9
SDAAn INTIICAn
A6 A5 A4 A3 A2 A1 A0 R/W Address
Note
Note
INTIICAn is not issued if data other than a local address or extension code is received while the all address match function is disabled during slave device operation.
Addresses are output when a total of 8 bits consisting of the slave address and the transfer direction described in 16.5.3 Transfer Direction Specification are written to the IICA shift register n (IICAn). The received addresses are written to the IICAn register. The slave address is assigned to the higher 7 bits of the IICAn register.
16.5.3 Transfer Direction Specification
In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this transfer direction specification bit has a value of "0", it indicates that the master device is transmitting data to a slave device. When the transfer direction specification bit has a value of "1", it indicates that the master device is receiving data from a slave device.
Figure 16 - 17 Transfer Direction Specification
SCLAn
1
2
3
4
5
6
7
8
9
SDAAn INTIICAn
A6 A5 A4 A3 A2 A1 A0 R/W
Transfer direction specification Note
Note
INTIICAn is not issued if data other than a local address or extension code is received while the all address match function is disabled during slave device operation.
Remark n = 0, 1
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16.5.4 Acknowledge (ACK)
ACK is used to check the status of serial data at the transmission and reception sides. The reception side returns ACK each time it has received 8-bit data. The transmission side usually receives ACK after transmitting 8-bit data. When ACK is returned from the reception side, it is assumed that reception has been correctly performed and processing is continued. Whether ACK has been detected can be checked by using bit 2 (ACKDn) of the IICA status register n (IICSn). When the master receives the last data item, it does not return ACK and instead generates a stop condition. If a slave does not return ACK after receiving data, the master outputs a stop condition or restart condition and stops transmission. If ACK is not returned, the possible causes are as follows.
<1> Reception was not performed normally. <2> The final data item was received. <3> The reception side specified by the address does not exist.
To generate ACK, the reception side makes the SDAAn line low at the ninth clock (indicating normal reception). Automatic generation of ACK is enabled by setting bit 2 (ACKEn) of IICA control register n0 (IICCTLn0) to 1. Bit 3 (TRCn) of the IICSn register is set to the value of the eighth bit that follows 7-bit address information. Usually, set the ACKEn bit to 1 for reception (TRCn = 0). If a slave can receive no more data during reception (TRCn = 0) or does not require the next data item, then the slave must inform the master, by clearing the ACKEn bit to 0, that it will not receive any more data. When the master does not require the next data item during reception (TRCn = 0), it must clear the ACKEn bit to 0 so that ACK is not generated. In this way, the master informs a slave at the transmission side that it does not require any more data (transmission will be stopped).
Figure 16 - 18 ACK
SCLAn SDAAn
1
2
3
4
5
6
7
8
9
A6 A5 A4 A3 A2 A1 A0 R/W ACK
When the local address is received, ACK is automatically generated, regardless of the value of the ACKEn bit. When an address other than that of the local address is received, ACK is not generated (NACK). When an extension code is received, or when an address is received while the all address match function is enabled, ACK is generated if the ACKEn bit is set to 1 in advance. How ACK is generated when data is received depends on the setting of the timing of clock stretching as follows.
· When 8th cycle clock stretching is selected (bit 3 (WTIMn) of the IICCTLn0 register = 0): By setting the ACKEn bit to 1 before release from the clock stretch state, ACK is generated at the falling edge of the eighth clock cycle of the SCLAn pin.
· When 9th cycle clock stretching is selected (bit 3 (WTIMn) of the IICCTLn0 register = 1): ACK is generated if the ACKEn bit is set to 1 in advance.
Remark n = 0, 1
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16.5.5 Stop Condition
When the SCLAn pin is at high level, changing the SDAAn pin from low level to high level generates a stop condition. A stop condition is a signal that the master device generates to the slave device when serial transfer has been completed. When the device is used as a slave, stop conditions can be detected.
Figure 16 - 19 Stop Condition
SCLAn H SDAAn
A stop condition is generated when bit 0 (SPTn) of IICA control register n0 (IICCTLn0) is set to 1. When the stop condition is detected, bit 0 (SPDn) of the IICA status register n (IICSn) is set to 1 and INTIICAn is generated when bit 4 (SPIEn) of the IICCTLn0 register is set to 1.
Remark n = 0, 1
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16.5.6 Clock stretching
Clock stretching is used to notify the other party in communications that a device (master or slave) is preparing to transmit or receive data (i.e., the interface is in the clock stretch state). Setting the SCLAn pin to the low level indicates the clock stretch state to the other party. When clock stretching is released for both the master and slave devices, the next data transfer can start.
Figure 16 - 20 Clock Stretching (1/2)
(1) When clock stretching is set for the ninth and eighth clock cycles for the master and slave devices, respectively (master: transmission, slave: reception, and ACKEn = 1)
Master
IICAn
The signal line from the master returns to the high impedance state but the slave signal is in the clock stretch state (at the low level).
Clock stretching is inserted after output of the ninth clock pulse.
IICAn data write (release from the clock stretch state)
SCLAn
6789
123
Slave
IICAn SCLAn
Clock stretching is inserted after output of the eighth clock pulse.
FFH is written to IICAn or WRELn is set to 1.
ACKEn H
Transfer lines SCLAn
Clock stretching from the slave device Clock stretching from the master device
678
9
123
Remark n = 0, 1
SDAAn
D2 D1 D0
ACK
D7 D6 D5
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Figure 16 - 20 Clock Stretching (2/2)
(2) When clock stretching is set for the ninth clock cycle for both the master and slave devices (master: transmission, slave: reception, and ACKEn = 1)
Master
IICAn SCLAn
The clock is stretched after the output of the ninth clock pulse for both the master and slave devices.
IICAn data write (release from the clock stretch state)
6789
1
23
Slave
IICAn
FFH is written to IICAn or WRELn is set to 1.
SCLAn ACKEn H
Transfer lines SCLAn
Clock stretching from both the master
and slave devices
Clock stretching from the slave device
6 789
123
SDAAn
D2 D1 D0 ACK
D7
D6 D5
Generate according to previously set ACKEn value
Remark ACKEn: Bit 2 of IICA control register n0 (IICCTLn0) WRELn: Bit 5 of IICA control register n0 (IICCTLn0)
Clock stretching is automatically generated depending on the setting of bit 3 (WTIMn) of IICA control register n0 (IICCTLn0). Normally, the receiving side releases the clock stretch state when bit 5 (WRELn) of the IICCTLn0 register is set to 1 or when FFH is written to the IICA shift register n (IICAn), and the transmitting side releases the clock stretch state when data is written to the IICAn register. The master device can also releases the clock stretch state via either of the following methods.
· By setting bit 1 (STTn) of the IICCTLn0 register to 1 · By setting bit 0 (SPTn) of the IICCTLn0 register to 1
Remark n = 0, 1
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16.5.7 Release from clock stretching
The I2C interface usually releases the clock stretch state by the following processing.
· Writing data to the IICA shift register n (IICAn)
· Setting bit 5 (WRELn) of IICA control register n0 (IICCTLn0) (release from the clock stretch state)
· Setting bit 1 (STTn) of the IICCTLn0 register (generating start condition)Note
· Setting bit 0 (SPTn) of the IICCTLn0 register (generating stop condition)Note
Note
Master only
Executing the above processing for release from clock stretching leads to IICA releasing the clock stretch state after which communications are resumed. To release the clock stretch state and transmit data (including addresses), write the data to the IICAn register. To receive data after release from the clock stretch state, or to complete data transmission, set bit 5 (WRELn) of the IICCTLn0 register to 1. To generate a restart condition after release from the clock stretch state, set bit 1 (STTn) of the IICCTLn0 register to 1. To generate a stop condition after release from the clock stretch state, set bit 0 (SPTn) of the IICCTLn0 register to 1. Execute the processing for release only once for each period in the clock stretch state. If, for example, data is written to the IICAn register after release from the clock stretch state by setting the WRELn bit to 1, an incorrect value may be output to SDAAn line because the timing for changing the SDAAn line conflicts with the timing for writing the IICAn register. In addition to the above, communications are stopped if the IICEn bit is cleared to 0 when communications have been aborted, so that the clock stretch state can be released. If the I2C bus has deadlocked due to noise, the device can exit from communications by setting bit 6 (LRELn) of the IICCTLn0 register to 1, so that the clock stretch state can be released.
Caution
If the processing for release from clock stretching is executed when WUPn = 1, the clock stretch state will not be released.
Remark n = 0, 1
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16.5.8
Timing of Generation of the Interrupt Request Signal (INTIICAn) and Control of Clock Stretching
The setting of bit 3 (WTIMn) of IICA control register n0 (IICCTLn0) determines the timing by which INTIICAn is generated and controls clock stretching, as shown in Table 16 - 2.
Table 16 - 2 INTIICAn Generation Timing and Control of Clock Stretching
WTIMn
During Slave Device Operation
Address
Data Reception
Data Transmission
During Master Device Operation
Address
Data Reception
Data Transmission
0
9Notes 1, 2
8Note 2
8Note 2
9
8
8
1
9Notes 1, 2
9Note 2
9Note 2
9
9
9
Note 1.
Note 2. Remark
The slave device's INTIICAn signal and clock stretching occur at the falling edge of the ninth clock cycle only when there is a match with the address set to the slave address register n (SVAn). At this point, ACK is generated regardless of the value set to the IICCTLn0 register's bit 2 (ACKEn). For a slave device that has received an extension code, or has received an address while the all address match function is enabled, INTIICAn occurs at the falling edge of the eighth clock. However, if the address does not match after restart, INTIICAn is generated at the falling edge of the ninth clock cycle, but clock stretching does not occur. If the received address does not match the contents of the slave address register n (SVAn), the all address match function is disabled, and extension code is not received, neither INTIICAn nor clock stretching occurs. The numbers in the table indicate the pulses of the serial clock signal. Interrupt requests and control of clock stretching are both synchronized with the falling edge of these clock pulses.
(1) During address transmission/reception · Slave device operation: The timing of the interrupt and clock stretching depends on the conditions described in Note 1 and Note 2 above, regardless of the setting of the WTIMn bit. · Master device operation: The interrupt and clock stretching occur at the falling edge of the ninth clock cycle, regardless of the setting of the WTIMn bit.
(2) During data reception · Master/slave device operation: The timing of the interrupt and clock stretching depends on the setting of the WTIMn bit.
(3) During data transmission · Master/slave device operation: The timing of the interrupt and clock stretching depends on the setting of the WTIMn bit.
Remark n = 0, 1
(4) Release from clock stretching
The four types of processing for release from clock stretching are as follows.
· Writing data to the IICA shift register n (IICAn)
· Setting bit 5 (WRELn) of IICA control register n0 (IICCTLn0) (release from the clock stretch state)
· Setting bit 1 (STTn) of the IICCTLn0 register (generating start condition)Note
· Setting bit 0 (SPTn) of the IICCTLn0 register (generating stop condition)Note
Note
Master only
When 8th cycle clock stretching has been selected (WTIMn = 0), the presence/absence of ACK generation must be determined before release from the clock stretch state.
(5) Detection of stop condition INTIICAn is generated when a stop condition is detected (only when SPIEn = 1).
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
16.5.9 Address Match Detection Method
In I2C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match can be detected automatically by hardware. An interrupt request signal (INTIICAn) occurs only when the address set to the slave address register n (SVAn) matches the slave address sent by the master device, when an address is received while the all address match function is enabled (IICCTLn1.SVADISn = 1), or when an extension code has been received.
16.5.10 Error Detection
In I2C bus mode, the status of the serial data bus (SDAAn) during data transmission is captured by the IICA shift register n (IICAn) of the transmitting device, so the IICA data prior to transmission can be compared with the transmitted IICA data to enable detection of transmission errors. A transmission error is judged as having occurred when the compared data values do not match.
Remark n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
16.5.11 Extension Code
(1) When the higher 4 bits of the receive address are either "0000" or "1111", the extension code reception flag (EXCn) is set to 1 for extension code reception and an interrupt request signal (INTIICAn) is issued at the falling edge of the eighth clock. When an address is received while the all address match function is enabled, it is also determined that an extension code has been received. The local address stored in the slave address register n (SVAn) is not affected.
(2) The settings below are specified if 11110xx0 is transferred from the master by using a 10-bit address transfer while
the SVAn register is set to 11110xx0 or if an address is received while the all address match function is enabled.
Note that INTIICAn occurs at the falling edge of the eighth clock.
· Higher four bits of data match or the all address match function is enabled: EXCn = 1
· Seven bits of data match or the all address match function is enabled:
COIn = 1
Remark
EXCn: Bit 5 of IICA status register n (IICSn) COIn: Bit 4 of IICA status register n (IICSn)
(3) Since the processing after the interrupt request occurs differs according to the data that follows the extension code, such processing is performed by software. If the extension code is received or an address is received with the all address match function enabled during operation as a slave, then the slave device is participating in communication even if its address does not match. For example, after the extension code is received, if you do not wish to operate the target device as a slave device, set bit 6 (LRELn) of IICA control register n0 (IICCTLn0) to 1 to set the standby mode for the next communication operation.
Table 16 - 3 Bit Definitions of Major Extension Codes
Slave Address
R/W Bit
Description
0000 000
0
General call address
1111 0xx
0
10-bit slave address specification (during address authentication)
1111 0xx
1
10-bit slave address specification (after address match, when read command is issued)
Remark 1. See the I2C bus specifications issued by NXP Semiconductors for details of extension codes other than those described above.
Remark 2. n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
16.5.12 Arbitration
When several master devices simultaneously generate a start condition (when the STTn bit is set to 1 before the STDn bit is set to 1), communication among the master devices is performed as the number of clocks are adjusted until the data differs. This kind of operation is called arbitration. When one of the master devices loses in arbitration, an arbitration loss flag (ALDn) in the IICA status register n (IICSn) is set (1) via the timing by which the arbitration loss occurred, and the SCLAn and SDAAn lines are both set to high impedance, which releases the bus. The arbitration loss is detected by checking ALDn = 1 by software at the timing of the next interrupt request (the eighth or ninth clock cycle, when a stop condition is detected, etc.). For details of interrupt request timing, see 16.5.8 Timing of Generation of the Interrupt Request Signal (INTIICAn) and Control of Clock Stretching.
Remark
STDn: Bit 1 of IICA status register n (IICSn) STTn: Bit 1 of IICA control register n0 (IICCTLn0)
Figure 16 - 21 Arbitration Timing Example
Master 1 SCLAn
SDAAn Master 2
SCLAn
SDAAn Transfer lines
SCLAn
SDAAn
Remark n = 0, 1
Hi-Z Hi-Z Master 1 loses arbitration
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
Table 16 - 4 Status During Arbitration and Interrupt Request Generation Timing
Status During Arbitration
Interrupt Request Generation Timing
During address transmission
At falling edge of eighth or ninth clock following byte transferNote 1
Read/write data after address transmission
During extension code transmission
Read/write data after extension code transmission
During data transmission
During ACK transfer period after data transmission
When restart condition is detected during data transfer
When stop condition is detected during data transfer
When stop condition is generated (when SPIEn = 1)Note 2
When data is at low level while attempting to generate a restart At falling edge of eighth or ninth clock following byte transferNote 1 condition
When stop condition is detected while attempting to generate a When stop condition is generated (when SPIEn = 1)Note 2 restart condition
When data is at low level while attempting to generate a stop At falling edge of eighth or ninth clock following byte transferNote 1 condition
When SCLAn is at low level while attempting to generate a restart condition
Note 1. Note 2.
When the WTIMn bit (bit 3 of IICA control register n0 (IICCTLn0)) = 1, an interrupt request occurs at the falling edge of the ninth clock. When WTIMn = 0, the extension code's slave address is received, and an address is received while the all address match function is enabled, an interrupt request occurs at the falling edge of the eighth clock. When there is a chance that arbitration will occur, set SPIEn = 1 for master device operation.
Remark 1. SPIEn: Bit 4 of IICA control register n0 (IICCTLn0) Remark 2. n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
16.5.13 Wakeup Function
The I2C bus slave function is a function that generates an interrupt request signal (INTIICAn) when the local address is received, an address is received while the all address match function is enabled, or an extension code is received. This function makes processing more efficient by preventing unnecessary INTIICAn signal from occurring when addresses do not match while the all address match function is disabled. When a start condition is detected, wakeup standby mode is set. Even a master that has generated a start condition enters the wakeup standby state while transmitting an address because the master may become a slave due to an arbitration loss. To use the wakeup function in the STOP mode, set the WUPn bit to 1. Addresses can be received regardless of the operation clock. An interrupt request signal (INTIICAn) is also generated when the local address is received, an address is received while the all address match function is enabled, or an extension code is received. Operation returns to normal operation by using an instruction to clear (0) the WUPn bit after this interrupt has been generated. Figure 16 - 22 shows the flow for setting WUPn = 1 and Figure 16 - 23 shows the flow for setting WUPn = 0 upon an address match (or when the all address match function is enabled).
Figure 16 - 22 Flow When Setting WUPn = 1
START
No MSTSn = STDn = EXCn = COIn =0?
Yes
WUPn = 1
Wait
Waits for three cycles of fMCK.
STOP instruction execution
Remark n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
Figure 16 - 23 Flow When Setting WUPn = 0 upon Address Match (or When the All Address Match Function is Enabled) (Including Extension Code Reception)
No INTIICAn = 1?
Yes
WUPn = 0
STOP mode state
Wait
Waits for five cycles of fMCK.
Reading IICSn
Executes processing corresponding to the operation to be executed after checking the operation state of serial interface IICA.
Use the following flows to perform the processing to release the STOP mode other than by an interrupt request signal
(INTIICAn) generated from serial interface IICA. · When operating next IIC communication as master: Flow shown in Figure 16 - 24.
· When operating next IIC communication as slave:
When released by INTIICAn interrupt:
Same as the flow in Figure 16 - 23.
When released by other than INTIICAn interrupt: Wait for INTIICAn interrupt with WUPn left set to 1.
Remark n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
Figure 16 - 24 When Operating as Master Device after Releasing STOP Mode other than by INTIICAn
START SPIEn = 1
WUPn = 1
Wait
Wait for three cycles of fMCK.
STOP instruction
STOP mode state
Releasing STOP mode Releases STOP mode by an interrupt other than INTIICAn.
WUPn = 0
INTIICAn = 1? Yes
Reading IICSn
No
Generates a STOP condition or selects as a slave device.
Remark n = 0, 1
Executes processing corresponding to the operation to be executed after checking the operation state of serial interface IICA.
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
16.5.14 Communication Reservation
(1) When communication reservation function is enabled (bit 0 (IICRSVn) of IICA flag register n (IICFn) = 0) To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not used.
· When arbitration results in neither master nor slave operation · While the all address match function is disabled, when an extension code is received and slave operation is
disabled (ACK is not returned and the bus was released by setting bit 6 (LRELn) of IICA control register n0 (IICCTLn0) to 1 and exiting from communication)
If bit 1 (STTn) of the IICCTLn0 register is set to 1 while the bus is not used, a start condition is automatically generated and wait state is entered after the bus is released (after a stop condition is detected). If an address is written to the IICA shift register n (IICAn) after bit 4 (SPIEn) of the IICCTLn0 register was set to 1, and it was detected by generation of an interrupt request signal (INTIICAn) that the bus was released (detection of the stop condition), then the device automatically starts communication as the master. Data written to the IICAn register before the stop condition is detected is invalid. When the STTn bit has been set to 1, the operation mode (as start condition or as communication reservation) is determined according to the bus status.
· If the bus has been released ........................................ a start condition is generated · If the bus has not been released (standby mode) ........ communication reservation
Check whether the communication reservation operates or not by using the MSTSn bit (bit 7 of the IICA status register n (IICSn)) after the STTn bit is set to 1 and the wait time elapses. Use software to secure the wait time calculated by the following expression.
Wait time from setting STTn = 1 to checking the MSTSn flag: (IICWLn setting value + IICWHn setting value + 4)/fMCK + tF × 2
Remark 1. IICWLn: IICWHn: tF: fMCK:
Remark 2. n = 0, 1
IICA low-level width setting register n IICA high-level width setting register n SDAAn and SCLAn signal falling times IICA operation clock frequency
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
Figure 16 - 25 shows the communication reservation timing. Figure 16 - 25 Communication Reservation Timing
Program processing STTn = 1
Write to IICAn
Communi-
Hardware processing cation
reservation
Set SPDn and INTIICAn
Set STDn
SCLAn
123456789
1 2 3 4 56
SDAAn
Generate by master device with bus mastership
Remark
IICAn: IICA shift register n STTn: Bit 1 of IICA control register n0 (IICCTLn0) STDn: Bit 1 of IICA status register n (IICSn) SPDn: Bit 0 of IICA status register n (IICSn)
Communication reservations are accepted via the timing shown in Figure 16 - 26. After bit 1 (STDn) of the IICA status register n (IICSn) is set to 1, a communication reservation can be made by setting bit 1 (STTn) of IICA control register n0 (IICCTLn0) to 1 before a stop condition is detected.
Figure 16 - 26 Timing for Accepting Communication Reservations
SCLAn SDAAn
STDn SPDn
Standby mode (Communication can be reserved by setting STTn to 1 during this period.)
Figure 16 - 27 shows the communication reservation protocol.
Remark n = 0, 1
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RL78/G23 Figure 16 - 27 Communication Reservation Protocol
CHAPTER 16 SERIAL INTERFACE IICA (IICA)
DI
SET1 STTn
Define communication reservation
Wait
Sets STTn flag (communication reservation)
Defines that communication reservation is in effect (defines and sets user flag to any part of RAM)
Secures wait timeNote 1 by software.
(Communication reservation)Note 2 Yes
MSTSn = 0?
Confirmation of communication reservation
No
(Generate start condition)
Cancel communication reservation
Clear user flag
MOV IICAn, #××H
IICAn write operation
EI
Note 1. Note 2.
The wait time is calculated as follows. (IICWLn setting value + IICWHn setting value + 4)/fMCK + tF × 2 The communication reservation operation executes a write to the IICA shift register n (IICAn) when a stop condition interrupt request occurs.
Remark 1. STTn: Bit 1 of IICA control register n0 (IICCTLn0)
MSTSn: Bit 7 of IICA status register n (IICSn)
IICAn: IICA shift register n
IICWLn: IICA low-level width setting register n
IICWHn: IICA high-level width setting register n
tF:
SDAAn and SCLAn signal falling times
fMCK: IICA operation clock frequency Remark 2. n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
(2) When communication reservation function is disabled (bit 0 (IICRSVn) of IICA flag register n (IICFn) = 1) When bit 1 (STTn) of IICA control register n0 (IICCTLn0) is set to 1 when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated. The following two statuses are included in the status where bus is not used.
· When arbitration results in neither master nor slave operation · While the all address match function is disabled, when an extension code is received and slave operation is
disabled (ACK is not returned and the bus was released by setting bit 6 (LRELn) of the IICCTLn0 register to 1 and exiting from communication)
To confirm whether the start condition was generated or request was rejected, check STCFn (bit 7 of the IICFn register). It takes up to 5 cycles of fMCK until the STCFn bit is set to 1 after setting STTn = 1. Therefore, secure the time by software.
Remark n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
16.5.15 Cautions
(1) When STCENn = 0 Immediately after I2C operation is enabled (IICEn = 1), the bus communication status (IICBSYn = 1) is recognized regardless of the actual bus status. When changing from a mode in which no stop condition has been detected to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication. When using multiple masters, it is not possible to perform master device communication when the bus has not been released (when a stop condition has not been detected). Use the following sequence for generating a stop condition.
<1> Set IICA control register n1 (IICCTLn1). <2> Set bit 7 (IICEn) of IICA control register n0 (IICCTLn0) to 1. <3> Set bit 0 (SPTn) of the IICCTLn0 register to 1.
(2) When STCENn = 1 Immediately after I2C operation is enabled (IICEn = 1), the bus released status (IICBSYn = 0) is recognized regardless of the actual bus status. To generate the first start condition (STTn = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications.
(3) If other I2C communications are already in progress If I2C operation is enabled and the device participates in communication already in progress when the SDAAn pin is low and the SCLAn pin is high, the IICA recognizes that the SDAAn pin has gone low (detects a start condition). If the value on the bus at this time can be recognized as an extension code or the all address match function is enabled, ACK is returned, but this interferes with other I2C communications. To avoid this, start the IICA in the following sequence. <1> Clear bit 4 (SPIEn) of the IICCTLn0 register to 0 to disable generation of an interrupt request signal (INTIICAn) when the stop condition is detected. <2> Set bit 7 (IICEn) of the IICCTLn0 register to 1 to enable the operation of the IICA. <3> Wait for detection of the start condition. <4> Set bit 6 (LRELn) of the IICCTLn0 register to 1 before ACK is returned (4 to 72 cycles of fMCK after setting the IICEn bit to 1), to forcibly disable detection.
(4) Setting the STTn and SPTn bits (bits 1 and 0 of the IICCTLn0 register) again after they are set and before they are cleared to 0 is prohibited.
(5) When transmission is reserved, set the SPIEn bit (bit 4 of the IICCTLn0 register) to 1 so that an interrupt request is generated when the stop condition is detected. Transfer is started when communication data is written to the IICA shift register n (IICAn) after the interrupt request is generated. Unless the interrupt is generated when the stop condition is detected, the device stops in the wait state because the interrupt request is not generated when communication is started. However, it is not necessary to set the SPIEn bit to 1 when the MSTSn bit (bit 7 of the IICA status register n (IICSn)) is detected by software.
Remark n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
16.5.16 Communication Operations
The following shows three operation procedures with the flowchart.
(1) Master operation in single-master system The flowchart when using the RL78/G23 as the master in a single master system is shown below. This flowchart is broadly divided into the initial settings and communication processing. Execute the initial settings at startup. If communication with the slave is required, prepare the communication and then execute communication processing.
(2) Master operation in multi-master system In the I2C bus multimaster system, whether the bus is released or used cannot be judged by the I2C bus specifications when a device takes part in a communication. Here, when data and clock are at a high level for a certain period (1 frame), the RL78/G23 takes part in a communication with bus released state. This flowchart is broadly divided into the initial settings, communication waiting, and communication processing. The processing when the RL78/G23 looses in arbitration and is specified as the slave is omitted here, and only the processing as the master is shown. Execute the initial settings at startup to take part in a communication. Then, wait for the communication request as the master or wait for the specification as the slave. The actual communication is performed in the communication processing, and it supports the transmission/reception with the slave and the arbitration with other masters.
(3) Slave operation An example of when the RL78/G23 is used as the I2C bus slave is shown below. When used as the slave, operation is started by an interrupt. Execute the initial settings at startup, then wait for the INTIICAn interrupt occurrence (communication waiting). When an INTIICAn interrupt occurs, the communication status is judged and its result is passed as a flag over to the main processing. By checking the flags, necessary communication processing is performed.
Remark n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
(1) Master operation in single-master system Figure 16 - 28 Master Operation in Single-Master System
Initial setting
START
Setting the PER0 register Initializing I2C busNote Setting port
IICWLn, IICWHn XXH
Release the serial interface IICAn from the reset state and start clock supply.
Setting of the port multiplexed with the pin to be used. First, set the port to input mode and the output latch to 0 (see 16.3.9 Registers to control the port function multiplexed with the IICA I/O pins). Sets a transfer clock.
SVAn XXH
Sets a local address.
IICFn 0XH Setting STCENn, IICRSVn = 0
Sets a start condition.
Setting IICCTLn1
IICCTLn0 0XX111XXB ACKEn = WTIMn = SPIEn = 1
IICCTLn0 1XX111XXB IICEn = 1
Setting port
Set the port from input mode to output mode and enable the output of the I 2C bus (see 16.3.9 Registers to control the port function multiplexed with the IICA I/O pins).
STCENn = 1?
No SPTn = 1
Yes
Prepares for starting communication (generates a stop condition).
INTIICAn interrupt occurs?
Yes
No Waits for detection of the stop condition.
STTn = 1 Writing IICAn
Prepares for starting communication (generates a start condition).
Starts communication (specifies an address and transfer direction).
INTIICAn interrupt occurs?
Yes
No Waits for detection of acknowledge.
No
ACKDn = 1?
Yes
TRCn = 1?
No
Yes Writing IICAn
Starts transmission.
INTIICAn interrupt occurs?
Yes
No Waits for data transmission.
ACKDn = 1?
No
Yes
No
End of transfer?
Yes
Restart? Yes
No SPTn = 1 END
ACKEn = 1 WTIMn = 0
WRELn = 1
Starts reception.
INTIICAn interrupt occurs?
Yes Reading IICAn
No
Waits for data reception.
End of transfer?
No
Yes ACKEn = 0
WTIMn = 1 WRELn = 1
INTIICAn interrupt occurs?
Yes
No
Waits for detection of acknowledge.
Communication processing
Note
Release (SCLAn and SDAAn pins = high level) the I2C bus in conformance with the specifications of the product that is
communicating. If EEPROM is outputting a low level to the SDAAn pin, for example, set the SCLAn pin in the output port
mode, and output a clock pulse from the output port until the SDAAn pin is constantly at high level.
Remark 1. Conform to the specifications of the product that is communicating, with respect to the transmission and reception formats.
Remark 2. n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
(2) Master operation in multi-master system Figure 16 - 29 Master Operation in Multi-Master System (1/3)
START
Setting the PER0 register Release the serial interface IICAn from the reset state and start clock supply.
Setting port IICWLn, IICWHn XXH
Setting of the port multiplexed with the pin to be used. First, set the port to input mode and the output latch to 0 (see 16.3.9 Registers to control the port function multiplexed with the IICA I/O pins).
Selects a transfer clock.
SVAn XXH
Sets a local address.
IICFn 0XH Setting STCENn and IICRSVn
Sets a start condition.
Setting IICCTLn1
IICCTLn0 0XX111XXB ACKE0n = WTIMn = SPIEn = 1
IICCTLn0 1XX111XXB IICE0 = 1
Setting port
Set the port from input mode to output mode and enable the output of the I2C bus (see 16.3.9 Registers to control the port function multiplexed with the IICA I/O pins).
Initial setting
Checking bus statusNote
Releases the bus for a specific period.
Bus status is being checked.
No
INTIICAn
interrupt occurs?
Yes
SPDn = 1?
No
STCENn = 1?
No
Yes
Yes
Slave operation
SPTn = 1
INTIICAn interrupt occurs?
Yes
SPDn = 1?
Yes
1
· Waiting to be specified as a slave by other master
· Waiting for a communication start request (depends on user program)
Prepares for starting Communication (generates a stop condition).
No Waits for detection of the stop condition.
No
Slave operation
Note
Waits for a communication
Master operation starts?
No (No communication start request)
Yes (Communication start request)
SPIEn = 0
SPIEn = 1
IICRSVn = 0?
No
INTIICAn interrupt occurs?
Yes Slave operation
Yes
A
B
Enables reserving Disables reserving communication. communication.
No Waits for a communication request.
Confirm that the bus is released (CLDn bit = 1, DADn bit = 1) for a specific period (for example, for a period of one frame). If the SDAAn pin is constantly at low level, decide whether to release the I2C bus (SCLAn and SDAAn pins = high level) in conformance with the specifications of the product that is communicating.
Remark n = 0, 1
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RL78/G23 Figure 16 - 29 Master Operation in Multi-Master System (2/3)
CHAPTER 16 SERIAL INTERFACE IICA (IICA)
Note
A Enables reserving communication.
STTn = 1 Wait
Prepares for starting communication (generates a start condition).
Secure wait timeNote by software.
Communication processing
MSTSn = 1?
No
Yes
INTIICAn
No
interrupt occurs?
Waits for bus release
(communication being reserved).
Yes
Wait state after stop condition
No EXCn = 1 or COIn = 1?
was detected and start condition
was generated by the communication
Yes
reservation function. C
Slave operation
The wait time is calculated as follows. (IICWLn setting value + IICWHn setting value + 4)/fMCK + tF × 2
Communication processing
B Disables reserving communication.
IICBSYn = 0?
No
Yes D
STTn = 1 Wait
Prepares for starting communication (generates a start condition).
Wait for five cycles of fMCK.
STCFn = 0?
No
Yes
C
INTIICAn interrupt occurs?
Yes
No Waits for bus release
EXCn = 1 or COIn = 1? Yes
No Detects a stop condition.
Slave operation
D
Remark 1. IICWLn: IICA low-level width setting register n
IICWHn: IICA high-level width setting register n
tF:
SDAAn and SCLAn signal falling times
fMCK: IICA operation clock frequency Remark 2. n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
Figure 16 - 29 Master Operation in Multi-Master System (3/3)
Communication processing
C Writing IICAn
Starts communication (specifies an address and transfer direction).
INTIICAn interrupt occurs?
Yes
MSTSn = 1?
No Waits for detection of ACK.
No
Yes
2
No
ACKDn = 1?
Yes
TRCn = 1?
No
Yes WTIMn = 1
Writing IICAn
Starts transmission.
INTIICAn interrupt occurs?
Yes
MSTSn = 1?
No Waits for data transmission.
No
Yes
2
ACKDn = 1?
No
Yes
No
Transfer end?
Yes
Restart? Yes
No SPTn = 1
STTn = 1
END
C
2
ACKEn = 1 WTIMn = 0
WRELn = 1
Starts reception.
INTIICAn interrupt occurs?
Yes
MSTSn = 1?
Yes Reading IICAn
No Waits for data reception.
No
2
Transfer end?
No
Yes ACKEn = 0
WTIMn = 1
WRELn = 1
INTIICAn interrupt occurs?
Yes
MSTSn = 1?
Yes
No Waits for detection of ACK.
No 2
Communication processing
EXCn = 1 or COIn = 1? No
Yes Slave operation
1
Does not participate in communication.
Remark 1. Conform to the specifications of the product that is communicating, with respect to the transmission and reception formats. Remark 2. To use the device as a master in a multi-master system, read the MSTSn bit each time interrupt INTIICAn has occurred to
check the arbitration result. Remark 3. To use the device as a slave in a multi-master system, check the status by using the IICA status register n (IICSn) and IICA
flag register n (IICFn) each time interrupt INTIICAn has occurred, and determine the processing to be performed next. Remark 4. n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
(3) Slave operation The processing procedure of the slave operation is as follows. Basically, the slave operation is event-driven. Therefore, processing by the INTIICAn interrupt (processing that must substantially change the operation status such as detection of a stop condition during communication) is necessary. In the following explanation, it is assumed that the all address match function is disabled and the extension code is not supported for data communication. It is also assumed that the INTIICAn interrupt servicing only performs status transition processing, and that actual data communication is performed by the main processing.
INTIICAn
Flag
Interrupt servicing
Setting IICA
Data
Main processing
Setting
Therefore, data communication processing is performed by preparing the following three flags and passing them to the main processing instead of INTIICAn.
<1> Communication mode flag
This flag indicates the following two communication statuses.
Clear mode:
Status in which data communication is not performed
Communication mode: Status in which data communication is performed (from valid address detection to stop
condition detection, no detection of ACK from master, address mismatch)
<2> Ready flag This flag indicates that data communication is enabled. Its function is the same as the INTIICAn interrupt for ordinary data communication. This flag is set by interrupt servicing and cleared by the main processing. Clear this flag by interrupt servicing when communication is started. However, the ready flag is not set by interrupt servicing when the first data is transmitted. Therefore, the first data is transmitted without the flag being cleared (an address match is interpreted as a request for the next data).
<3> Communication direction flag This flag indicates the direction of communication. Its value is the same as the TRCn bit.
Remark n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
The main processing of the slave operation is explained next. Start serial interface IICA and wait until communication is enabled. When communication is enabled, execute communication by using the communication mode flag and ready flag (processing of the stop condition and start condition is performed by an interrupt. Here, check the status by using the flags). The transmission operation is repeated until the master no longer returns ACK. If ACK is not returned from the master, communication is completed. For reception, the necessary amount of data is received. When communication is completed, ACK is not returned as the next data. After that, the master generates a stop condition or restart condition. Exit from the communication status occurs in this way.
Figure 16 - 30 Slave Operation Flowchart (1)
Initial setting
START
Setting the PER0 register Setting port
IICWLn, IICWHn XXH
Release the serial interface IICAn from the reset state and start clock supply.
Setting of the port multiplexed with the pin to be used. First, set the port to input mode and the output latch to 0 (see 16.3.9 Registers to control the port function multiplexed with the IICA I/O pins).
Selects a transfer clock.
SVAn XXH
Sets a local address.
IICFn 0XH Setting IICRSVn
Sets a start condition.
Setting IICCTLn1
IICCTLn0 0XX011XXB ACKEn = WTIMn = 1, SPIn = 0
IICCTLn0 1XX011XXB IICEn = 1
Setting port
Set the port from input mode to output mode and enable the output of the I2C bus (see 16.3.9 Registers to control the port function multiplexed with the IICA I/O pins).
No
Communication
mode flag = 1?
Yes
Communication
No
direction flag = 1?
Yes
Writing IICAn
Starts transmission.
No
Communication
mode flag = 1?
Yes
No
Communication
direction flag = 1?
Yes
No Ready flag = 1?
Yes
Clearing ready flag
Yes ACKDn = 1?
No
Clearing communication mode flag WRELn = 1
SPIEn = 1
WRELn = 1
Starts reception.
Communication
No
mode flag = 1?
Yes
Communication
No
direction flag = 1?
Yes No
Ready flag = 1?
Yes Reading IICAn
Clearing ready flag
Communication processing
Remark 1. Conform to the specifications of the product that is communicating, with respect to the transmission and reception formats. Remark 2. n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
An example of the processing procedure of the slave with the INTIICAn interrupt is explained below (processing is performed assuming that the all address match function is disabled and no extension code is used). The INTIICAn interrupt checks the status, and the following operations are performed. <1> Communication is stopped if the stop condition is issued. <2> If the start condition is issued, the address is checked and communication is completed if the address does not match. If the address matches, the communication mode is set, wait is canceled, and processing returns from the interrupt (the ready flag is cleared). <3> For data transmit/receive, only the ready flag is set. Processing returns from the interrupt with the I2C bus remaining in the wait state.
Remark <1> to <3> above correspond to <1> to <3> in Figure 16 - 31 Slave Operation Flowchart (2).
Figure 16 - 31 Slave Operation Flowchart (2)
INTIICAn generated
Yes SPDn = 1?
No
Yes STDn = 1?
No <3>
Set ready flag
<1>
<2>
No COIn = 1?
Yes
Communication direction flag TRCn
Set communication mode flag Clear ready flag
Clear communication direction flag, ready flag, and
communication mode flag
Interrupt servicing completed
Remark n = 0, 1
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16.5.17 Timing of I2C Interrupt Request Signal (INTIICAn) Occurrence
The timing of transmitting or receiving data and generation of interrupt request signal INTIICAn, and the value of the IICA status register n (IICSn) when the INTIICAn signal is generated are shown below.
Remark 1. ST:
Start condition
AD6 to AD0: Address
R/W:
Transfer direction specification
ACK:
Acknowledge
D7 to D0: Data
SP:
Stop condition
Remark 2. n = 0, 1
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(1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception)
(i) When WTIMn = 0
ST AD6 to AD 0 R/W ACK
D7 to D0
1
ACK 2
D7 to D0
SPTn = 1
ACK SP
345
1: IICSn = 1000×110B 2: IICSn = 1000×000B 3: IICSn = 1000×000B (Sets the WTIMn bit to 1)Note 4: IICSn = 1000××00B (Sets the SPTn bit to 1)
5: IICSn = 00000001B
Note Remark
To generate a stop condition, set the WTIMn bit to 1 and change the timing for generating the INTIICAn interrupt request signal. : Always generated
: Generated only when SPIEn = 1 ×: Don't care
(ii) When WTIMn = 1
ST AD6 to AD 0 R/W ACK
D7 to D0
1
ACK
D7 to D0
2
1: IICSn = 1000×110B 2: IICSn = 1000×100B 3: IICSn = 1000××00B (Sets the SPTn bit to 1)
4: IICSn = 00000001B
SPTn = 1
ACK SP
3 4
Remark
: Always generated : Generated only when SPIEn = 1
×: Don't care
Remark n = 0, 1
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(b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) (i) When WTIMn = 0
ST AD6 to AD 0 R/ W ACK D7 to D 0 1
STTn = 1
ACK ST
2 3
AD6 to AD 0 R/W ACK D7 to D 0 4
SPTn = 1
ACK SP
56 7
1: IICSn = 1000×110B 2: IICSn = 1000×000B (Sets the WTIMn bit to 1)Note 1 3: IICSn = 1000××00B (Clears the WTIMn bit to 0Note 2, sets the STTn bit to 1) 4: IICSn = 1000×110B 5: IICSn = 1000×000B (Sets the WTIMn bit to 1)Note 3 6: IICSn = 1000××00B (Sets the SPTn bit to 1)
7: IICSn = 00000001B
Note 1.
Note 2. Note 3.
Remark
To generate a start condition, set the WTIMn bit to 1 and change the timing for generating the INTIICAn interrupt request signal. Clear the WTIMn bit to 0 to restore the original setting. To generate a stop condition, set the WTIMn bit to 1 and change the timing for generating the INTIICAn interrupt request signal. : Always generated
: Generated only when SPIEn = 1 ×: Don't care
(ii) When WTIMn = 1
ST AD6 to AD 0 R/W ACK D7 to D 0 1
STTn = 1
ACK ST
2
AD6 to AD 0 R/W ACK D7 to D 0 3
SPTn = 1
ACK SP
45
1: IICSn = 1000×110B 2: IICSn = 1000××00B (Sets the STTn bit to 1) 3: IICSn = 1000×110B 4: IICSn = 1000××00B (Sets the SPTn bit to 1)
5: IICSn = 00000001B
Remark
: Always generated : Generated only when SPIEn = 1
×: Don't care
Remark n = 0, 1
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(c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) (i) When WTIMn = 0
ST AD6 to AD 0 R/W ACK
D7 to D 0
1
ACK 2
D7 to D 0
1: IICSn = 1010×110B 2: IICSn = 1010×000B 3: IICSn = 1010×000B (Sets the WTIMn bit to 1)Note 4: IICSn = 1010××00B (Sets the SPTn bit to 1)
5: IICSn = 00000001B
SPTn = 1
ACK SP
3 45
Note Remark
To generate a stop condition, set the WTIMn bit to 1 and change the timing for generating the INTIICAn interrupt request signal. : Always generated
: Generated only when SPIEn = 1 ×: Don't care
(ii) When WTIMn = 1
ST AD6 to AD 0 R/W ACK
D7 to D 0
ACK
D7 to D 0
1
2
1: IICSn = 1010×110B 2: IICSn = 1010×100B 3: IICSn = 1010××00B (Sets the SPTn bit to 1)
4: IICSn = 00000001B
SPTn = 1
ACK SP
3 4
Remark
: Always generated : Generated only when SPIEn = 1
×: Don't care
Remark n = 0, 1
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(2) Slave device operation (slave address data reception) (a) Start ~ Address ~ Data ~ Data ~ Stop
(i) When WTIMn = 0
CHAPTER 16 SERIAL INTERFACE IICA (IICA)
ST AD6 to AD 0 R/W ACK
D7 to D 0
ACK
D7 to D0
ACK SP
1
2
3
4
1: IICSn = 0001×110B 2: IICSn = 0001×000B 3: IICSn = 0001×000B
4: IICSn = 00000001B
Remark
: Always generated : Generated only when SPIEn = 1
×: Don't care
(ii) When WTIMn = 1
ST AD6 to AD 0 R/W ACK 1
D7 to D 0
1: IICSn = 0001×110B 2: IICSn = 0001×100B 3: IICSn = 0001××00B
4: IICSn = 00000001B
ACK
D7 to D0
2
ACK SP 3 4
Remark
: Always generated : Generated only when SPIEn = 1
×: Don't care
Remark n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
(b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIMn = 0 (after restart, matches with SVAn, the all address match function is disabled)
ST AD6 to AD 0 R/W ACK D7 to D 0 1
1: IICSn = 0001×110B 2: IICSn = 0001×000B 3: IICSn = 0001×110B 4: IICSn = 0001×000B
5: IICSn = 00000001B
ACK ST 2
AD6 to AD 0 R/W ACK D7 to D 0 3
ACK SP
4
5
Remark : Always generated : Generated only when SPIEn = 1
×: Don't care
(ii) When WTIMn = 1 (after restart, matches with SVAn, the all address match function is disabled)
ST AD6 to AD 0 R/W ACK D7 to D 0 1
ACK ST AD6 to AD 0 R/W ACK D7 to D 0
2
3
ACK SP 4 5
1: IICSn = 0001×110B 2: IICSn = 0001××00B 3: IICSn = 0001×110B 4: IICSn = 0001××00B
5: IICSn = 00000001B
Remark
: Always generated : Generated only when SPIEn = 1
×: Don't care
Remark n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
(c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIMn = 0 (after restart, does not match address (= extension code, the all address match function is disabled))
ST AD6 to AD 0 R/W ACK D7 to D 0 ACK ST AD6 to AD 0 R/W ACK D7 to D 0 ACK SP
1
2
3
4
5
1: IICSn = 0001×110B 2: IICSn = 0001×000B 3: IICSn = 0010×010B 4: IICSn = 0010×000B
5: IICSn = 00000001B
Remark
: Always generated : Generated only when SPIEn = 1
×: Don't care
(ii) When WTIMn = 1 (after restart, does not match address (= extension code, the all address match function is disabled))
ST AD6 to AD 0 R/W ACK D7 to D 0 1
1: IICSn = 0001×110B 2: IICSn = 0001××00B 3: IICSn = 0010×010B 4: IICSn = 0010×110B 5: IICSn = 0010××00B
6: IICSn = 00000001B
ACK ST 2
AD6 to AD 0 R/W ACK D7 to D 0 3 4
ACK SP 5 6
Remark
: Always generated : Generated only when SPIEn = 1
×: Don't care
Remark n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
(d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIMn = 0 (after restart, does not match address (= not extension code, the all address match function is disabled))
ST AD6 to AD 0 R/W ACK D7 to D 0 1
ACK ST AD6 to AD 0 R/W ACK D7 to D 0
2
3
ACK SP 4
1: IICSn = 0001×110B 2: IICSn = 0001×000B 3: IICSn = 00000×10B
4: IICSn = 00000001B
Remark
: Always generated : Generated only when SPIEn = 1
×: Don't care
(ii) When WTIMn = 1 (after restart, does not match address (= not extension code, the all address match function is disabled))
ST AD6 to AD 0 R/W ACK D7 to D 0 1
ACK ST AD6 to AD 0 R/W ACK D7 to D 0
2
3
ACK SP 4
1: IICSn = 0001×110B 2: IICSn = 0001××00B 3: IICSn = 00000×10B
4: IICSn = 00000001B
Remark
: Always generated : Generated only when SPIEn = 1
×: Don't care
Remark n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
(3) Slave device operation (when receiving extension code and the all address match function is disabled) The device is always participating in communication when it receives an extension code.
(a) Start ~ Code ~ Data ~ Data ~ Stop (i) When WTIMn = 0
ST AD6 to AD 0 R/W ACK
D7 to D 0
ACK
D7 to D 0
ACK SP
1
2
3
4
1: IICSn = 0010×010B 2: IICSn = 0010×000B 3: IICSn = 0010×000B
4: IICSn = 00000001B
Remark
: Always generated : Generated only when SPIEn = 1
×: Don't care
(ii) When WTIMn = 1
ST AD6 to AD 0 R/W ACK
D7 to D 0
12
1: IICSn = 0010×010B 2: IICSn = 0010×110B 3: IICSn = 0010×100B 4: IICSn = 0010××00B
5: IICSn = 00000001B
ACK
D7 to D 0
3
ACK SP 4 5
Remark
: Always generated : Generated only when SPIEn = 1
×: Don't care
Remark n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
(b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIMn = 0 (after restart, matches with SVAn, the all address match function is disabled)
ST AD6 to AD 0 R/W ACK D7 to D 0 1
1: IICSn = 0010×010B 2: IICSn = 0010×000B 3: IICSn = 0001×110B 4: IICSn = 0001×000B
5: IICSn = 00000001B
ACK ST 2
AD6 to AD 0 R/W ACK D7 to D 0 3
ACK SP
4
5
Remark
: Always generated : Generated only when SPIEn = 1
×: Don't care
(ii) When WTIMn = 1 (after restart, matches with SVAn, the all address match function is disabled)
ST AD6 to AD 0 R/W ACK D7 to D 0 1 2
ACK ST AD6 to AD 0 R/W ACK D7 to D 0
3
4
ACK SP 56
1: IICSn = 0010×010B 2: IICSn = 0010×110B 3: IICSn = 0010××00B 4: IICSn = 0001×110B 5: IICSn = 0001××00B
6: IICSn = 00000001B
Remark
: Always generated : Generated only when SPIEn = 1
×: Don't care
Remark n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
(c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIMn = 0 (after restart, extension code reception, the all address match function is disabled)
ST AD6 to AD 0 R/W ACK 1
D7 to D 0
ACK ST AD6 to AD 0 R/W ACK
2
3
D7 to D 0
ACK SP
4
5
1: IICSn = 0010×010B 2: IICSn = 0010×000B 3: IICSn = 0010×010B 4: IICSn = 0010×000B
5: IICSn = 00000001B
Remark : Always generated : Generated only when SPIEn = 1
×: Don't care
(ii) When WTIMn = 1 (after restart, extension code reception, the all address match function is disabled)
ST AD6 to AD 0 R/W ACK D7 to D 0 1 2
ACK ST AD6 to AD 0 R/W ACK D7 to D 0
3
4 5
ACK SP 67
1: IICSn = 0010×010B 2: IICSn = 0010×110B 3: IICSn = 0010××00B 4: IICSn = 0010×010B 5: IICSn = 0010×110B 6: IICSn = 0010××00B
7: IICSn = 00000001B
Remark
: Always generated : Generated only when SPIEn = 1
×: Don't care
Remark n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
(d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIMn = 0 (after restart, does not match address (= not extension code, the all address match function is disabled))
ST AD6 to AD 0 R/W ACK 1
D7 to D 0
ACK ST AD6 to AD 0 R/W ACK D7 to D 0
2
3
ACK SP 4
1: IICSn = 0010×010B 2: IICSn = 0010×000B 3: IICSn = 00000×10B
4: IICSn = 00000001B
Remark
: Always generated : Generated only when SPIEn = 1
×: Don't care
(ii) When WTIMn = 1 (after restart, does not match address (= not extension code, the all address match function is disabled))
ST AD6 to AD 0 R/W ACK D7 to D 0 12
ACK ST AD6 to AD 0 R/W ACK D7 to D 0
3
4
ACK SP 5
1: IICSn = 0010×010B 2: IICSn = 0010×110B 3: IICSn = 0010××00B 4: IICSn = 00000×10B
5: IICSn = 00000001B
Remark
: Always generated : Generated only when SPIEn = 1
×: Don't care
Remark n = 0, 1
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(4) Operation without communication (a) Start ~ Code ~ Data ~ Data ~ Stop
ST AD6 to AD 0 R/W ACK
D7 to D 0
ACK
D7 to D 0
ACK SP 1
1: IICSn = 00000001B
Remark : Generated only when SPIEn = 1
(5) Arbitration loss operation (operation as slave after arbitration loss) When the device is used as a master in a multi-master system, read the MSTSn bit each time interrupt request signal INTIICAn has occurred to check the arbitration result.
(a) When arbitration loss occurs during transmission of slave address data (i) When WTIMn = 0
ST AD6 to AD 0 R/W ACK
D7 to D 0
1
ACK 2
D7 to D 0
ACK SP
3
4
1: IICSn = 0101×110B 2: IICSn = 0001×000B 3: IICSn = 0001×000B
4: IICSn = 00000001B
Remark
: Always generated : Generated only when SPIEn = 1
×: Don't care
Remark n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
ST AD6 to AD 0 R/W ACK
D7 to D 0
1
1: IICSn = 0101×110B 2: IICSn = 0001×100B 3: IICSn = 0001××00B
4: IICSn = 00000001B
ACK
D7 to D 0
2
ACK SP 3 4
Remark
: Always generated : Generated only when SPIEn = 1
×: Don't care
(b) When arbitration loss occurs during transmission of extension code (the all address match function is disabled) (i) When WTIMn = 0
ST AD6 to AD 0 R/W ACK 1
D7 to D 0
ACK 2
D7 to D 0
ACK SP
3
4
1: IICSn = 0110×010B 2: IICSn = 0010×000B 3: IICSn = 0010×000B
4: IICSn = 00000001B
Remark
: Always generated : Generated only when SPIEn = 1
×: Don't care
Remark n = 0, 1
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(ii) When WTIMn = 1
ST AD6 to AD 0 R/W ACK
D7 to D 0
12
1: IICSn = 0110×010B 2: IICSn = 0010×110B 3: IICSn = 0010×100B 4: IICSn = 0010××00B
5: IICSn = 00000001B
ACK
D7 to D 0
3
ACK SP 4 5
Remark
: Always generated : Generated only when SPIEn = 1
×: Don't care
(6) Operation when arbitration loss occurs (no communication after arbitration loss) When the device is used as a master in a multi-master system, read the MSTSn bit each time interrupt request signal INTIICAn has occurred to check the arbitration result.
(a) When arbitration loss occurs during transmission of slave address data (when WTIMn = 1)
ST AD6 to AD 0 R/W ACK 1
D7 to D 0
ACK
D7 to D 0
ACK SP 2
1: IICSn = 01000110B 2: IICSn = 00000001B
Remark : Always generated : Generated only when SPIEn = 1
Remark n = 0, 1
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(b) When arbitration loss occurs during transmission of extension code (the all address match function is disabled)
ST AD6 to AD 0 R/W ACK 1
D7 to D 0
ACK
D7 to D 0
ACK SP 2
1: IICSn = 0110×010B Sets LRELn = 1 by software
2: IICSn = 00000001B
Remark
: Always generated : Generated only when SPIEn = 1
×: Don't care
(c) When arbitration loss occurs during transmission of data (i) When WTIMn = 0
ST AD6 to AD 0 R/W ACK 1
D7 to D 0
ACK 2
D7 to D 0
ACK SP 3
1: IICSn = 10001110B 2: IICSn = 01000000B
3: IICSn = 00000001B
Remark : Always generated : Generated only when SPIEn = 1
Remark n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
ST AD6 to AD 0 R/W ACK 1
D7 to D 0
1: IICSn = 10001110B 2: IICSn = 01000100B
3: IICSn = 00000001B
ACK
D7 to D 0
2
ACK SP 3
Remark : Always generated : Generated only when SPIEn = 1
(d) When loss occurs due to restart condition during data transfer (i) Not extension code (Example: unmatches with SVAn, the all address match function is disabled)
ST AD6 to AD 0 R/W ACK D7 to Dm 1
ST AD6 to AD 0 R/W ACK D7 to D 0 2
ACK SP 3
1: IICSn = 1000×110B 2: IICSn = 01000110B
3: IICSn = 00000001B
Remark
: Always generated : Generated only when SPIEn = 1
×: Don't care m = 6 to 0
Remark n = 0, 1
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(ii) Extension code (the all address match function is disabled)
ST AD6 to AD 0 R/W ACK D7 to Dm 1
ST AD6 to AD 0 R/W ACK 2
D7 to D 0
ACK SP 3
1: IICSn = 1000×110B 2: IICSn = 01100010B Sets LRELn = 1 by software
3: IICSn = 00000001B
Remark
: Always generated : Generated only when SPIEn = 1
×: Don't care m = 6 to 0
(e) When loss occurs due to stop condition during data transfer
ST AD6 to AD 0 R/W ACK D7 to Dm 1
1: IICSn = 10000110B 2: IICSn = 01000001B
SP 2
Remark
: Always generated : Generated only when SPIEn = 1
×: Don't care m = 6 to 0
Remark n = 0, 1
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(f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition (i) When WTIMn = 0
ST AD6 to AD 0 R/W ACK D7 to D 0 1
STTn = 1 ACK D7 to D 0
2 3
ACK 4
D7 to D0
ACK SP 5
1: IICSn = 1000×110B 2: IICSn = 1000×000B (Sets the WTIMn bit to 1) 3: IICSn = 1000×100B (Clears the WTIMn bit to 0) 4: IICSn = 01000000B
5: IICSn = 00000001B
Remark : Always generated : Generated only when SPIEn = 1
×: Don't care
(ii) When WTIMn = 1
ST AD6 to AD 0 R/W ACK D7 to D 0 1
STTn = 1 ACK D7 to D 0
2
ACK D7 to D0 3
ACK SP 4
1: IICSn = 1000×110B 2: IICSn = 1000×100B (Sets the STTn bit to 1) 3: IICSn = 01000100B
4: IICSn = 00000001B
Remark
: Always generated : Generated only when SPIEn = 1
×: Don't care
Remark n = 0, 1
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(g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition (i) When WTIMn = 0
ST AD6 to AD 0 R/W ACK 1
D7 to D 0
STTn = 1 ACK SP
23 4
1: IICSn = 1000×110B 2: IICSn = 1000×000B (Sets the WTIMn bit to 1) 3: IICSn = 1000××00B (Sets the STTn bit to 1)
4: IICSn = 01000001B
Remark
: Always generated : Generated only when SPIEn = 1
×: Don't care
(ii) When WTIMn = 1
ST AD6 to AD 0 R/W ACK 1
D7 to D 0
STTn = 1 ACK SP
23
1: IICSn = 1000×110B 2: IICSn = 1000××00B (Sets the STTn bit to 1)
3: IICSn = 01000001B
Remark : Always generated : Generated only when SPIEn = 1
×: Don't care
Remark n = 0, 1
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(h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition (i) When WTIMn = 0
ST AD6 to AD 0 R/W ACK D7 to D 0 1
SPTn = 1 ACK D7 to D 0
2 3
ACK D7 to D0 4
ACK SP 5
1: IICSn = 1000×110B 2: IICSn = 1000×000B (Sets the WTIMn bit to 1) 3: IICSn = 1000×100B (Clears the WTIMn bit to 0) 4: IICSn = 01000100B
5: IICSn = 00000001B
Remark : Always generated : Generated only when SPIEn = 1
×: Don't care
(ii) When WTIMn = 1
ST AD6 to AD 0 R/W ACK D7 to D 0 1
SPTn = 1
ACK D7 to D 0
2
ACK D7 to D0 3
ACK SP 4
1: IICSn = 1000×110B 2: IICSn = 1000×100B (Sets the SPTn bit to 1) 3: IICSn = 01000100B
4: IICSn = 00000001B
Remark
: Always generated : Generated only when SPIEn = 1
×: Don't care
Remark n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
16.6
Timing Charts
When using the I2C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRCn bit (bit 3 of the IICA status register n (IICSn)), which specifies the data transfer direction, and then starts serial communication with the slave device. Figure 16 - 32 and Figure 16 - 33 show timing charts of the data communication. The IICA shift register n (IICAn)'s shift operation is synchronized with the falling edge of the serial clock (SCLAn). The transmit data is transferred to the SO latch and is output (MSB first) via the SDAAn pin. Data input via the SDAAn pin is captured into IICAn at the rising edge of SCLAn. In the timing charts described in this section, it is assumed that the all address match function is disabled.
Remark n = 0, 1
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Figure 16 - 32 Example of Master to Slave Communications (9th Cycle Clock Stretching Is Selected for Both the Master and Slave) (1/4)
(1) Start condition to address to data
Master side
IICAn <2>
ACKDn (ACK detection)
WTIMn (8th or 9th cycle clock stretching) H
ACKEn (ACK control) H
MSTSn (communication status)
STTn (ST trigger)
<1>
SPTn (SP trigger) L
WRELn (release from clock stretching ) L
INTIICAn (interrupt)
TRCn (transmit/receive)
Bus line
SCLAn (bus) (clock line)
SDAAn (bus) (data line)
Note 2
Slave side
IICAn
ACKDn (ACK detection)
STDn (ST detection)
SPDn (SP detection)
WTIMn (8th or 9th cycle clock stretching) H
ACKEn (ACK control) H
MSTSn
(communication status)
L
WRELn (release from clock stretching )
INTIICAn (interrupt)
TRCn (transmit/receive)
L
Note 1 <5>
Start condition
<4>
AD6 AD5 AD4 AD3 AD2 AD1 AD0
W ACK
D17
Slave address
<3>
<6> Note 3
: Clock stretching by the slave device : Clock stretching by both the master and slave devices
Note 1. Note 2. Note 3.
For release from the clock stretch state during transmission by a master device, write data to the IICAn register instead of setting the WRELn bit. Make sure that the time between the fall of the SDAAn pin signal and the fall of the SCLAn pin signal is at least 4.0 µs when specifying standard mode and at least 0.6 µs when specifying fast mode. For release from the clock stretch state during reception by a slave device, write FFH to IICAn or set the WRELn bit.
Remark n = 0, 1
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The meanings of <1> to <6> in (1) Start condition to address to data in Figure 16 - 32 are explained below. <1> The start condition trigger is set by the master device (STTn = 1) and a start condition (i.e. SCLAn = 1 and SDAAn
changes from 1 to 0) is generated once the bus data line goes low (SDAAn). When the start condition is subsequently detected, the master device enters the master device communication status (MSTSn = 1). The master device is ready to communicate once the bus clock line goes low (SCLAn = 0) after the hold time has elapsed. <2> The master device writes the address + W (transmission) to the IICA shift register n (IICAn) and transmits the slave address. <3> In the slave device if the address received matches the address (SVAn value) of a slave deviceNote, that slave device sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKDn = 1) at the rising edge of the 9th clock. <4> The master device issues an interrupt (INTIICAn: end of address transmission) at the falling edge of the 9th clock. The slave device with the address matching the transmitted slave address sets the clock stretch state (SCLAn = 0) and issues an interrupt (INTIICAn: address match)Note. <5> The master device writes the data to transmit to the IICAn register and releases the clock stretch state set by the master device. <6> If the slave device releases the clock stretch state (WRELn = 1), the master device starts transferring data to the slave device.
Note
If the transmitted address does not match the address of the slave device, the slave device does not return an ACK to the master device (NACK: SDAAn = 1). The slave device also does not issue the INTIICAn interrupt (address match) and does not set the clock stretch state. The master device, however, issues the INTIICAn interrupt (end of address transmission) regardless of whether it receives an ACK or NACK.
Remark 1. <1> to <15> in Figure 16 - 32 represent the entire procedure for communicating data using the I2C bus. Figure 16 - 32 (1) Start condition to address to data shows the processing from <1> to <6>, Figure 16 - 32 (2) Address to data to data shows the processing from <3> to <10>, and Figure 16 - 32 (3) Data to data to stop condition shows the processing from <7> to <15>.
Remark 2. n = 0, 1
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Figure 16 - 32 Example of Master to Slave Communications (9th Cycle Clock Stretching Is Selected for Both the Master and Slave) (2/4)
(2) Address to data to data
Master side
IICAn
ACKDn (ACK detection)
WTIMn (8th or 9th cycle clock stretching) H
ACKEn (ACK control) H
MSTSn (communication status) H
STTn (ST trigger) L
SPTn (SP trigger) L
WRELn (release from clock stretching) L
INTIICAn (interrupt)
TRCn (transmit/receive) H
Note 1 <5>
Note 1 <9>
Bus line
SCLAn (bus)
(clock line)
<4>
<8>
SDAAn (bus)
(data line) W ACK
D17
D16 D15 D14 D13 D12 D11 D10 ACK
D27
<3>
<7>
Slave side
IICAn
ACKDn (ACK detection)
STDn (ST detection)
SPDn (SP detection) L
WTIMn (8th or 9th cycle clock stretching) H
ACKEn (ACK control) H
MSTSn (communication status) L
WRELn (release from clock stretching)
INTIICAn (interrupt)
TRCn (transmit/receive) L
<6> Note 2
<10> Note 2
: Clock stretching by the slave device : Clock stretching by both the master and slave devices
Note 1. Note 2.
For release from the clock stretch state during transmission by a master device, write data to the IICAn register instead of setting the WRELn bit. For release from the clock stretch state during reception by a slave device, write FFH to IICAn or set the WRELn bit.
Remark n = 0, 1
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The meanings of <3> to <10> in (2) Address to data to data in Figure 16 - 32 are explained below. <3> In the slave device if the address received matches the address (SVAn value) of a slave deviceNote, that slave
device sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKDn = 1) at the rising edge of the 9th clock. <4> The master device issues an interrupt (INTIICAn: end of address transmission) at the falling edge of the 9th clock. The slave device with the address matching the transmitted slave address sets the clock stretch state (SCLAn = 0) and issues an interrupt (INTIICAn: address match)Note. <5> The master device writes the data to transmit to the IICA shift register n (IICAn) and releases the clock stretch state set by the master device. <6> If the slave device releases the clock stretch state (WRELn = 1), the master device starts transferring data to the slave device. <7> After data transfer is completed, because of ACKEn = 1, the slave device sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKDn = 1) at the rising edge of the 9th clock. <8> The master device and slave device set the clock stretch state (SCLAn = 0) at the falling edge of the 9th clock, and both the master device and slave device issue an interrupt (INTIICAn: end of transfer). <9> The master device writes the data to transmit to the IICAn register and releases the clock stretch state set by the master device. <10>The slave device reads the received data and releases the clock stretch state (WRELn = 1). The master device then starts transferring data to the slave device.
Note
If the transmitted address does not match the address of the slave device, the slave device does not return an ACK to the master device (NACK: SDAAn = 1). The slave device also does not issue the INTIICAn interrupt (address match) and does not set the clock stretch state. The master device, however, issues the INTIICAn interrupt (end of address transmission) regardless of whether it receives an ACK or NACK.
Remark 1. <1> to <15> in Figure 16 - 32 represent the entire procedure for communicating data using the I2C bus. Figure 16 - 32 (1) Start condition to address to data shows the processing from <1> to <6>, Figure 16 - 32 (2) Address to data to data shows the processing from <3> to <10>, and Figure 16 - 32 (3) Data to data to stop condition shows the processing from <7> to <15>.
Remark 2. n = 0, 1
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Figure 16 - 32 Example of Master to Slave Communications (9th Cycle Clock Stretching Is Selected for Both the Master and Slave) (3/4)
(3) Data to data to stop condition
Master side
IICAn
ACKDn (ACK detection)
WTIMn (8th or 9th cycle clock stretching) H
ACKEn (ACK control) H
MSTSn (communication status)
STTn (ST trigger)
L
SPTn (SP trigger)
WRELn (release from clock stretching)
L
INTIICAn (interrupt)
TRCn (transmit/receive)
Bus line
Note 1 <9>
<14> Stop condition
SCLAn (bus)
(clock line) <8>
SDAAn (bus) (data line)
D150
ACK
<7>
Slave side
D167
<12> D166 D165 D164 D163 D162 D161 D160 ACK
<11>
Note 2 <15>
IICAn
ACKDn (ACK detection)
STDn L (ST detection)
SPDn (SP detection)
WTIMn H (8th or 9th cycle clock stretching)
ACKEn H
(ACK control)
MSTSn (communication status)
L
WRELn (release from clock stretching)
INTIICAn (interrupt)
TRCn (transmit/receive)
L
<10> Note 3
<13> Note 3
: Clock stretching by the master device : Clock stretching by the slave device : Clock stretching by both the master and slave devices
Note 1. Note 2. Note 3.
For release from the clock stretch state during transmission by a master device, write data to the IICAn register instead of setting the WRELn bit. Make sure that the time between the rise of the SCLAn pin signal and the generation of the stop condition after a stop condition has been issued is at least 4.0 µs when specifying standard mode and at least 0.6 µs when specifying fast mode. For release from the clock stretch state during reception by a slave device, write FFH to IICAn or set the WRELn bit.
Remark n = 0, 1
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The meanings of <7> to <15> in (3) Data to data to stop condition in Figure 16 - 32 are explained below. <7> After data transfer is completed, because of ACKEn = 1, the slave device sends an ACK by hardware to the master
device. The ACK is detected by the master device (ACKDn = 1) at the rising edge of the 9th clock. <8> The master device and slave device set the clock stretch state (SCLAn = 0) at the falling edge of the 9th clock, and
both the master device and slave device issue an interrupt (INTIICAn: end of transfer). <9> The master device writes the data to transmit to the IICA shift register n (IICAn) and releases the clock stretch state
set by the master device. <10>The slave device reads the received data and releases the clock stretch state (WRELn = 1). The master device
then starts transferring data to the slave device. <11>When data transfer is complete, the slave device (ACKEn =1) sends an ACK by hardware to the master device.
The ACK is detected by the master device (ACKDn = 1) at the rising edge of the 9th clock. <12>The master device and slave device set the clock stretch state (SCLAn = 0) at the falling edge of the 9th clock, and
both the master device and slave device issue an interrupt (INTIICAn: end of transfer). <13>The slave device reads the received data and releases the clock stretch state (WRELn = 1). <14>By the master device setting a stop condition trigger (SPTn = 1), the bus data line is cleared (SDAAn = 0) and the
bus clock line is set (SCLAn = 1). After the stop condition setup time has elapsed, by setting the bus data line (SDAAn = 1), the stop condition is then generated (i.e. SCLAn =1 and SDAAn changes from 0 to 1). <15>When a stop condition is generated, the slave device detects the stop condition and issues an interrupt (INTIICAn: stop condition).
Remark 1. <1> to <15> in Figure 16 - 32 represent the entire procedure for communicating data using the I2C bus. Figure 16 - 32 (1) Start condition to address to data shows the processing from <1> to <6>, Figure 16 - 32 (2) Address to data to data shows the processing from <3> to <10>, and Figure 16 - 32 (3) Data to data to stop condition shows the processing from <7> to <15>.
Remark 2. n = 0, 1
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Figure 16 - 32 Example of Master to Slave Communications (9th Cycle Clock Stretching Is Selected for Both the Master and Slave) (4/4)
(4) Data to restart condition to address
Master side
IICAn
ACKDn (ACK detection)
WTIMn (8th or 9th cycle clock stretching) H
ACKEn (ACK control) H
MSTSn (communication status) H
STTn (ST trigger)
SPTn (SP trigger) L
WRELn (release from clock stretching) L
INTIICAn (interrupt)
TRCn (transmit/receive) H
Bus line
SCLAn (bus) (clock line) <8>
SDAAn (bus) (datal ine) D13 D12 D11 D10 ACK <7>
Slave side
IICAn
ACKDn (ACK detection)
STDn (ST detection)
SPDn (SP detection) L
WTIMn (8th or 9th cycle clock stretching) H
ACKEn (ACK control) H
MSTSn (communication status) L
WRELn
<i>
(release from clock stretching)
INTIICAn (interrupt)
TRCn (transmit/receive) L
<iii> <ii>
Note 1
Restart condition
AD6 AD5 AD4 AD3 AD2 AD1 Slave address
Note 2
: Clock stretching by the master device : Clock stretching by the slave device : Clock stretching by both the master and slave devices
Note 1. Note 2.
Make sure that the time between the rise of the SCLAn pin signal and the generation of the start condition after a restart condition has been issued is at least 4.7 µs when specifying standard mode and at least 0.6 µs when specifying fast mode. For release from the clock stretch state during reception by a slave device, write FFH to IICAn or set the WRELn bit.
Remark n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
The following describes the operations in Figure 16 - 32 (4) Data to restart condition to address. After the operations in steps <7> and <8>, the operations in steps <i> to <iii> are performed. These steps return the processing to step <3>, the data transmission step. <7> After data transfer is completed, because of ACKEn = 1, the slave device sends an ACK by hardware to the master
device. The ACK is detected by the master device (ACKDn = 1) at the rising edge of the 9th clock.
<8> The master device and slave device set the clock stretch state (SCLAn = 0) at the falling edge of the 9th clock, and both the master device and slave device issue an interrupt (INTIICAn: end of transfer). <i> The slave device reads the received data and releases the clock stretch state (WRELn = 1). <ii> The start condition trigger is set again by the master device (STTn = 1) and a start condition (i.e. SCLAn =1 and SDAAn changes from 1 to 0) is generated once the bus clock line goes high (SCLAn = 1) and the bus data line goes low (SDAAn = 0) after the restart condition setup time has elapsed. When the start condition is subsequently detected, the master device is ready to communicate once the bus clock line goes low (SCLAn = 0) after the hold time has elapsed. <iii> The master device writing the address + R/W (transmission) to the IICA shift register (IICAn) enables the slave address to be transmitted.
Remark n = 0, 1
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Figure 16 - 33 Example of Slave to Master Communications (8th Cycle Clock Stretching Is Selected for the Master and 9th Cycle Clock Stretching Is Selected for the Slave) (1/3)
(1) Start condition to address to data
Master side
IICAn
ACKDn (ACK detection)
WTIMn (8th or 9th cycle clock stretching)
ACKEn (ACK control)
H
MSTSn (communication status)
STTn <1> (ST trigger)
SPTn L (SP trigger)
WRELn (release from clock stretching)
INTIICAn (interrupt)
TRCn (transmit/receive)
Bus line
SCLAn (bus) (clock line)
SDAAn (bus) (data line)
Slave side
IICAn
ACKDn (ACK detection)
STDn (ST detection)
SPDn (SP detection)
WTIMn (8th or 9th cycle clock stretching)
H
ACKEn H (ACK control)
MSTSn L (communication status)
WRELn L (release from clock stretching)
INTIICAn (interrupt)
TRCn (transmit/receive)
<2> Note 2
<5>
<7> Note 1
Start condition
AD6 AD5 AD4 AD3 AD2 AD1 AD0 Slave address
<4>
R ACK <3>
<6>
D17 Note 3
: Clock stretching by the master device : Clock stretching by the slave device : Clock stretching by both the master and slave devices
Note 1. Note 2.
Note 3.
For release from the clock stretch state during reception by a master device, write FFH to IICAn or set the WRELn bit. Make sure that the time between the fall of the SDAAn pin signal and the fall of the SCLAn pin signal is at least 4.0 µs when specifying standard mode and at least 0.6 µs when specifying fast mode. For release from the clock stretch state during transmission by a slave device, write data to the IICAn register instead of setting the WRELn bit.
Remark n = 0, 1
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The meanings of <1> to <7> in (1) Start condition to address to data in Figure 16 - 33 are explained below. <1> The start condition trigger is set by the master device (STTn = 1) and a start condition (i.e. SCLAn = 1 and SDAAn
changes from 1 to 0) is generated once the bus data line goes low (SDAAn). When the start condition is subsequently detected, the master device enters the master device communication status (MSTSn = 1). The master device is ready to communicate once the bus clock line goes low (SCLAn = 0) after the hold time has elapsed. <2> The master device writes the address + R (reception) to the IICA shift register n (IICAn) and transmits the slave address. <3> In the slave device if the address received matches the address (SVAn value) of a slave deviceNote, that slave device sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKDn = 1) at the rising edge of the 9th clock. <4> The master device issues an interrupt (INTIICAn: end of address transmission) at the falling edge of the 9th clock. The slave device with the address matching the transmitted slave address sets the clock stretch state (SCLAn = 0) and issues an interrupt (INTIICAn: address match)Note. <5> The timing at which the master device sets the clock stretch state changes to the 8th clock (WTIMn = 0). <6> The slave device writes the data to transmit to the IICAn register and releases the clock stretch state set by the slave device. <7> The master device releases the clock stretch state (WRELn = 1) and starts transferring data from the slave device to the master device.
Note
If the transmitted address does not match the address of the slave device, the slave device does not return an ACK to the master device (NACK: SDAAn = 1). The slave device also does not issue the INTIICAn interrupt (address match) and does not set the clock stretch state. The master device, however, issues the INTIICAn interrupt (end of address transmission) regardless of whether it receives an ACK or NACK.
Remark 1. <1> to <19> in Figure 16 - 33 represent the entire procedure for communicating data using the I2C bus. Figure 16 - 33 (1) Start condition to address to data shows the processing from <1> to <7>, Figure 16 - 33 (2) Address to data to data shows the processing from <3> to <12>, and Figure 16 - 33 (3) Data to data to stop condition shows the processing from <8> to <19>.
Remark 2. n = 0, 1
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Figure 16 - 33 Example of Slave to Master Communications (8th Cycle Clock Stretching Is Selected for the Master and 9th Cycle Clock Stretching Is Selected for the Slave) (2/3)
(2) Address to data to data
Master side
IICAn
ACKDn (ACK detection)
WTIMn (8th or 9th cycle clock stretching)
ACKEn (ACK control) H
MSTSn (communication status) H
STTn (ST trigger) L
SPTn (SP trigger) L
WRELn (release from clock stretching)
INTIICAn (interrupt)
TRCn (transmit/receive)
L
<5>
Note 1 <7>
Note 1 <9>
Bus line
SCLAn (bus)
(clock line) <4>
SDAAn (bus)
(data line) R ACK
D17
<3> Slave side
IICAn
ACKDn (ACK detection)
STDn (ST detection)
SPDn (SP detection) L
WTIMn (8th or 9th cycle clock stretching)
H
ACKEn (ACK control) H
MSTSn (communication status) L
WRELn (release from clock stretching) L
INTIICAn (interrupt)
TRCn (transmit/receive) H
<6> Note 2
<8>
<11>
D16 D15 D14 D13 D12 D11 D10
ACK
D27
<10>
<12> Note 2
: Clock stretching by the master device : Clock stretching by the slave device : Clock stretching by both the master and slave devices
Note 1. Note 2.
For release from the clock stretch state during reception by a master device, write FFH to IICAn or set the WRELn bit. For release from the clock stretch state during transmission by a slave device, write data to the IICAn register instead of setting the WRELn bit.
Remark n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
The meanings of <3> to <12> in (2) Address to data to data in Figure 16 - 33 are explained below. <3> In the slave device if the address received matches the address (SVAn value) of a slave deviceNote, that slave
device sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKDn = 1) at the rising edge of the 9th clock. <4> The master device issues an interrupt (INTIICAn: end of address transmission) at the falling edge of the 9th clock. The slave device with the address matching the transmitted slave address sets the clock stretch state (SCLAn = 0) and issues an interrupt (INTIICAn: address match)Note. <5> The master device changes the timing of clock stretching to the 8th clock (WTIMn = 0). <6> The slave device writes the data to transmit to the IICA shift register n (IICAn) and releases the clock stretch state set by the slave device. <7> The master device releases the clock stretch state (WRELn = 1) and starts transferring data from the slave device to the master device. <8> The master device sets the clock stretch state (SCLAn = 0) at the falling edge of the 8th clock, and issues an interrupt (INTIICAn: end of transfer). Because of ACKEn = 1 in the master device, the master device then sends an ACK by hardware to the slave device. <9> The master device reads the received data and releases the clock stretch state (WRELn = 1). <10>The ACK is detected by the slave device (ACKDn = 1) at the rising edge of the 9th clock. <11>The slave device sets the clock stretch state (SCLAn = 0) at the falling edge of the 9th clock, and the slave device issue an interrupt (INTIICAn: end of transfer). <12>By the slave device writing the data to transmit to the IICAn register, the clock stretch state set by the slave device is released. The slave device then starts transferring data to the master device.
Note
If the transmitted address does not match the address of the slave device, the slave device does not return an ACK to the master device (NACK: SDAAn = 1). The slave device also does not issue the INTIICAn interrupt (address match) and does not set the clock stretch state. The master device, however, issues the INTIICAn interrupt (end of address transmission) regardless of whether it receives an ACK or NACK.
Remark 1. <1> to <19> in Figure 16 - 33 represent the entire procedure for communicating data using the I2C bus. Figure 16 - 33 (1) Start condition to address to data shows the processing from <1> to <7>, Figure 16 - 33 (2) Address to data to data shows the processing from <3> to <12>, and Figure 16 - 33 (3) Data to data to stop condition shows the processing from <8> to <19>.
Remark 2. n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
Figure 16 - 33 Example of Slave to Master Communications (8th Cycle Clock Stretching Is Changed to 9th Cycle Clock Stretching for the Master and 9th Cycle Clock Stretching Is Selected for the Slave) (3/3)
(3) Data to data to stop condition
Master side
IICAn
ACKDn (ACK detection)
WTIMn (8th or 9th cycle clock stretching )
ACKEn (ACK control)
MSTSn (communication status)
STTn (ST trigger) L
SPTn (SP trigger)
WRELn (release from clock stretching)
INTIICAn (interrupt)
TRCn (transmit/receive) L
Note 1 <9>
<14>
Note 1 <17> <15>
Bus line
Stop condition
SCLAn (bus) (clock line)
<8> SDAAn (bus)
(data line) D150
<11> ACK
Slave side
<10>
D167
D166
D165
D164 D163
D162
<13> D161 D160
IICAn
ACKDn (ACK detection)
STDn (ST detection) L
SPDn (SP detection)
WTIMn (8th or 9th cycle clock stretching )
H
ACKEn (ACK control)
H
MSTSn (communication status) L
WRELn (release from clock stretching)
INTIICAn (interrupt)
<12> Note 3
TRCn (transmit/receive)
<16> Note 2
NACK <19>
<18> Notes 1, 4
Note 4
: Clock stretching by the master device : Clock stretching by the slave device : Clock stretching by both the master and slave devices
Note 1. Note 2.
Note 3.
Note 4.
For release from the clock stretch state, write FFH to IICAn or set the WRELn bit. Make sure that the time between the rise of the SCLAn pin signal and the generation of the stop condition after a stop condition has been issued is at least 4.0 µs when specifying standard mode and at least 0.6 µs when specifying fast mode. For release from the clock stretch state during transmission by a slave device, write data to the IICAn register instead of setting the WRELn bit. If the clock stretch state during transmission by a slave device is released by setting the WRELn bit, the TRCn bit will be cleared.
Remark n = 0, 1
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CHAPTER 16 SERIAL INTERFACE IICA (IICA)
The meanings of <8> to <19> in (3) Data to data to stop condition in Figure 16 - 33 are explained below. <8> The master device sets the clock stretch state (SCLAn = 0) at the falling edge of the 8th clock, and issues an
interrupt (INTIICAn: end of transfer). Because of ACKEn = 0 in the master device, the master device then sends an ACK by hardware to the slave device. <9> The master device reads the received data and releases the clock stretch state (WRELn = 1). <10>The ACK is detected by the slave device (ACKDn = 1) at the rising edge of the 9th clock. <11>The slave device sets the clock stretch state (SCLAn = 0) at the falling edge of the 9th clock, and the slave device issue an interrupt (INTIICAn: end of transfer). <12>By the slave device writing the data to transmit to the IICA register, the clock stretch state set by the slave device is released. The slave device then starts transferring data to the master device. <13>The master device issues an interrupt (INTIICAn: end of transfer) at the falling edge of the 8th clock, and sets the clock stretch state (SCLAn = 0). Because ACK control (ACKEn = 1) is performed, the bus data line is at the low level (SDAAn = 0) at this stage. <14>The master device sets NACK as the response (ACKEn = 0) and changes the timing at which it sets the clock stretch state to the 9th clock (WTIMn = 1). <15>If the master device releases the clock stretch state (WRELn = 1), the slave device detects the NACK (ACK = 0) at the rising edge of the 9th clock. <16>The master device and slave device set the clock stretch state (SCLAn = 0) at the falling edge of the 9th clock, and both the master device and slave device issue an interrupt (INTIICAn: end of transfer). <17>When the master device issues a stop condition (SPTn = 1), the bus data line is cleared (SDAAn = 0) and the master device releases the clock stretch state. The master device then waits until the bus clock line is set (SCLAn = 1). <18>The slave device acknowledges the NACK, halts transmission, and releases the clock stretch state (WRELn = 1) to end communication. Once the slave device releases the clock stretch state, the bus clock line is set (SCLAn = 1). <19>Once the master device recognizes that the bus clock line is set (SCLAn = 1) and after the stop condition setup time has elapsed, the master device sets the bus data line (SDAAn = 1) and issues a stop condition (i.e. SCLAn =1 and SDAAn changes from 0 to 1). The slave device detects the generated stop condition and slave device issue an interrupt (INTIICAn: stop condition).
Remark 1. <1> to <19> in Figure 16 - 33 represent the entire procedure for communicating data using the I2C bus. Figure 16 - 33 (1) Start condition to address to data shows the processing from <1> to <7>, Figure 16 - 33 (2) Address to data to data shows the processing from <3> to <12>, and Figure 16 - 33 (3) Data to data to stop condition shows the processing from <8> to <19>.
Remark 2. n = 0, 1
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CHAPTER 17 SERIAL INTERFACE UARTA (UARTA)
CHAPTER 17 SERIAL INTERFACE UARTA (UARTA)
The number of channels of the serial interface UARTA depends on the product.
Number of channels
30- and 32-pin products --
36- and 40-pin products 1
44-, 48-, 52-, 64-, 80-, 100-, and 128-pin 2
17.1
Overview
The serial interface (UARTAn, n = 0, 1) supports the following two modes.
(1) Operation stop mode This mode is used when serial communication is not executed; power consumption can be reduced.
(2) UART mode This is a UART mode that supports continuous transmission. The list below outlines the features:
UARTAn performs an asynchronous communication. It has the following functions. · Maximum transfer rate: 153.6 kbps · Transmission and reception using two pins
TxDAn: Transmit data output pin RxDAn: Receive data input pin · Character length of transfer data selectable from 5, 7, and 8 bits · Baud rate arbitrarily settable with the dedicated internal 8-bit baud rate generator · Transmission and reception independent of each other (full-duplex communication) · MSB or LSB first transfer selectable · Inversion control of communication logic level provided · Transmit clock output is available (CLKAn) · Operating clock independent of the CPU/peripheral hardware clock selectable
Remark n: Unit number (n = 0, 1)
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Figure 17 - 1 shows a block diagram of UARTAn and Table 17 - 1 shows the pin configuration of UARTAn.
Selector Selector
Figure 17 - 1 Block Diagram of UARTAn
INTURn INTUREn
Reception unit
UARTAn ALVn
Reception control
Baud rate generator
Inversion control Filter
Receive shift register RXBAn
RxDAn
P register (output latch)
PM register (I/O control)
<R>
Internal bus
UTAnCK
UTASEL
fMXP fIHP fIMP
fSXP ELCL
fSEL
fSEL/2 fSEL/22
Prescaler fSEL/23 fSEL/24 fSEL/25 fSEL/26
fUTAn Selector
INTUTn
Clock control
BRGCAn
ASIMAn0
Register block
ASIMAn1
Baud rate generator Transmission control
ASISAn
ASCTAn
TXBAn Transmit shift
register
Transmission unit
ALVn
Inversion control
TxDAn
UTAnOEN
ULBSn
P register (output latch)
UARTA0 only
PFOE15
ELCL
PORT
PM register (I/O control)
P register (output latch)
UARTA0 only
PFOE14 ELCL
PM register (I/O control)
RxDAn
CLKAn TxDAn
Table 17 - 1 UARTAn Pin Configuration (n = 0, 1)
Name
I/O
RxDAn
Input
Serial data input signal
TxDAn
Output
Serial data output signal
CLKAn
Output
Serial clock output signal
Remark
fMXP: High-speed peripheral clock frequency fIHP: High-speed on-chip oscillator peripheral clock frequency fIMP: Middle-speed on-chip oscillator peripheral clock frequency fSXP: Low-speed peripheral clock frequency fSEL: Selected clock to be divided for the UARTA fUTAn: UARTAn operation clock ELCL: Event input from the ELCL
Function
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CHAPTER 17 SERIAL INTERFACE UARTA (UARTA)
17.2
Registers to Control the Serial Interface UARTA
The following registers are used to control the serial interface UARTA.
· Peripheral enable register 1 (PER1) · Transmit buffer register (TXBAn) (n = 0, 1) · Receive buffer register (RXBAn) (n = 0, 1) · Operation mode setting register 0 (ASIMAn0) (n = 0, 1) · Operation mode setting register 1 (ASIMAn1) (n = 0, 1) · Baud rate generator control register (BRGCAn) (n = 0, 1) · Status register (ASISAn) (n = 0, 1) · Status clear trigger register (ASCTAn) (n = 0, 1) · UARTA clock select register 0 (UTA0CK) · UARTA clock select register 1 (UTA1CK) · UART loopback select register (ULBS)
Remark
UARTAn uses the following registers, in addition to those listed above. · Port mode registers (PM0, PM3, PM4, PM7, PM8, and PM12) (See CHAPTER 4 PORT FUNCTIONS) · Port registers (P0, P3, P4, P7, P8, and P12) (See CHAPTER 4 PORT FUNCTIONS) · Pull-up resistor option register (PU0, PU3, PU4, PU7, PU8, and PU12) (See CHAPTER 4 PORT FUNCTIONS) · Port input mode register (PIM0, PIM3, PIM4, PIM7, and PIM8) (See CHAPTER 4 PORT FUNCTIONS) · Port output mode register (POM0, POM3, POM4, POM7, POM8, and POM12) (See CHAPTER 4 PORT FUNCTIONS) · Port mode control T register (PMCT7) (See CHAPTER 4 PORT FUNCTIONS) · Port mode control A register (PMCA12) (See CHAPTER 4 PORT FUNCTIONS) · Port function output enable register (PFOE1) (See CHAPTER 4 PORT FUNCTIONS)
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CHAPTER 17 SERIAL INTERFACE UARTA (UARTA)
17.2.1 Peripheral enable register 1 (PER1)
The PER1 register is used to enable or disable the supply of a clock signal to various on-chip peripheral modules. Clock supply to an on-chip peripheral module that is not to be used can be stopped to decrease power consumption and noise. To use UARTA0 or UARTA1, be sure to set bit 2 (UTAEN) of this register to 1. The PER1 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of the PER1 register is 00H following a reset.
Figure 17 - 2 Format of Peripheral Enable Register 1 (PER1)
Address: After reset: R/W:
F00FAH 00H R/W
Symbol
<7>
PER1 DACEN
<6> SMSEN
<5> CMPEN
<4> TML32EN
<3> DTCEN
<2> UTAEN
<1> REMCEN
<0> CTSUEN
UTAEN
Control of supply of an input clock to the serial interface UARTAn
0
Stops supply of an input clock.
· The SFRs used by the serial interface UARTAn cannot be written.
· When an SFR used by the serial interface UARTAn is read, the value returned is 00H or
0000H.
1
Enables supply of an input clock.
· The SFRs used by the serial interface UARTAn can be read and written.
Caution 1. Make sure that the setting of the UTAEN bit is 1 before using UARTAn. If UTAEN = 0, writing to the registers which control UARTAn is ignored.
Caution 2. For a precautionary note on the number of pins of RL78/G23 products, see CHAPTER 6 CLOCK GENERATOR.
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17.2.2 Transmit buffer register (TXBAn) (n = 0, 1)
TXBAn is a buffer register for setting transmit data. Transmission starts by writing data for transmission to the TXBAn register. The TXBAn register can be set by an 8-bit memory manipulation instruction. The value of this register is FFH following a reset.
Figure 17 - 3 Format of Transmit Buffer Register (TXBAn)
Address: After reset: R/W:
F0300H (TXBA0), F0308H (TXBA1) FFH R/W
Symbol
7
6
5
4
3
2
1
0
TXBAn
Bits 7 to 0
Function
--
When a character length of 8 bits is specified:
· Data in bits 7 to 0 of TXBAn are transferred.
When a character length of 7 bits is specified:
· Data in bits 6 to 0 of TXBAn are transferred in either MSB- or LSB-first mode; bit 7 is invalid. When a character length of 5 bits is specified: · Data in bits 4 to 0 of TXBAn are transferred in either MSB- or LSB-first mode; bits 7 to 5 are
invalid.
Caution 1. When the TXBFAn bit of the ASISAn register is 1, do not write data for transmission to the TXBAn register.
Caution 2. After setting the TXEAn bit of the ASIMAn0 register to 1, wait for the period of at least one cycle of the UARTAn operation clock (fUTAn) before setting the first data for transmission in the TXBAn register. If data for transmission is set within one cycle of the UARTAn operation clock after the TXEAn bit is set to 1, the start of transmission is delayed by one cycle of the UARTAn operation clock.
Remark
Data is transferred from the TXBAn register to this register, and is then transmitted as serial data through the TxDAn pin. In the first transmission, data is transferred from the TXBAn register to this register immediately after data is written to the TXBAn register. In continuous transmission, data is transferred after transmission of one frame and just before generation of the transmission completion interrupt. The transmit shift register cannot be manipulated directly by a program.
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CHAPTER 17 SERIAL INTERFACE UARTA (UARTA)
17.2.3 Receive buffer register (RXBAn) (n = 0, 1)
The RXBAn register stores the parallel data converted by the receive shift register. Every time one byte of data is received, the next receive data is transferred from the receive shift registerNote to this register. The RXBAn register can be read by an 8-bit memory manipulation instruction. The value of this register is FFH following a reset.
Figure 17 - 4 Format of Receive Buffer Register (RXBAn)
Address: After reset: R/W:
F0301H (RXBA0), F0309H (RXBA1) FFH R
Symbol
7
6
5
4
3
2
1
0
RXBAn
Bits 7 to 0
Function
--
When a character length of 8 bits is specified:
· Receive data is transferred to bits 7 to 0 of this register.
When a character length of 7 bits is specified:
· Receive data is transferred to bits 6 to 0 of this register in either MSB- or LSB-first mode; bit
7 is always 0.
When a character length of 5 bits is specified:
· Receive data is transferred to bits 4 to 0 of this register in either MSB- or LSB-first mode; bits
7 to 5 are always 0.
Note
The receive shift register converts the serial data that is input through the RxDAn pin to parallel data. The receive shift register cannot be manipulated directly by a program.
Caution If an overrun error (OVEAn) occurs, the data received at that time are not stored in the RXBAn register.
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17.2.4 Operation mode setting register 0 (ASIMAn0) (n = 0, 1)
The ASIMAn0 register is an 8-bit register that controls serial communication of the serial interface UARTAn. The ASIMAn0 register can be set by 1-bit or 8-bit memory manipulation instructions. The value of this register is 01H following a reset.
Figure 17 - 5 Format of Operation Mode Setting Register 0 (ASIMAn0)
Address: After reset: R/W:
F0302H (ASIMA00), F030AH (ASIMA10) 01H R/W
Symbol
<7>
<6>
<5>
4
3
2
<1>
<0>
ASIMAn0 UARTAENn TXEAn
RXEAn
0
0
0
ISSMAn ISRMAn
UARTAENn
Note 1
UART operation enable
0
Disables the UART operation clock. Resets the internal circuits.Note 2
1
Enables the UART operation clock.
TXEAn 0 1
Transmission enable Disables transmission. (Resets the transmission circuit.) Enables transmission.
RXEAn 0 1
Reception enable Disables reception. (Resets the reception circuit.) Enables reception.
ISSMAn
Transmit interrupt mode select
0
The INTUTn interrupt is generated on completion of transmission.
1
The INTUTn interrupt is generated when the transmit buffer becomes empty. (for continuous
transmission)
ISRMAn
Receive interrupt mode select
0
The INTUREn interrupt is generated when a reception error occurs. (INTURn is not
generated.)
1
The INTURn interrupt is generated when a reception error occurs. (INTUREn is not
generated.)
Note 1.
When UARTAENn = 0, the level being output from the TxDAn pin and the level being input from the RxDAn pin are determined according to the setting of the ALVn bit as described below. · When ALVn = 0, output from the TxDAn pin is high.
Note 2.
· When ALVn = 1, output from the TxDAn pin is low. The ASISAn and RXBAn registers are reset by clearing the UARTAENn bit to 0.
Caution 1. Be sure to clear bits 4, 3, and 2 to 0. Caution 2. To start transmission, set the UARTAENn bit to 1 and then set the TXEAn bit to 1.
To stop transmission, clear the TXEAn bit to 0 and then clear the UARTAENn bit to 0. Caution 3. To start reception, set the UARTAENn bit to 1 and then set the RXEAn bit to 1.
To stop reception, clear the RXEAn bit to 0 and then clear the UARTAENn bit to 0.
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<R> <R>
Caution 4. Follow the procedure below when setting the UARTAENn bit to 1 and then setting the RXEAn bit to 1. · When ALVn = 0, the setting must be made while the level being input to the RxDAn pin is high.
Otherwise, reception will start at that point and a framing error may occur.
· When ALVn = 1, the setting must be made while the level being input to the RxDAn pin is low.
Otherwise, reception will start at that point and a framing error may occur.
Caution 5. The TXEAn and RXEAn bits are synchronized with the UARTAn operation clock (fUTAn). To enable transmission or reception again, set the TXEAn or RXEAn bit to 1 at least two cycles of the UARTAn operation clock after clearing the TXEAn or RXEAn bit to 0. If the bit is set to 1 within two cycles of the UARTAn operation clock after the clearing, the transmission or reception circuit may not be able to be initialized.
Caution 6. After setting TXEAn bit to 1, wait for at least one cycle of the UARTAn operation clock (fUTAn) before setting the transmit data in the TXBAn register.
Caution 7. Clear the RXEAn bit to 0 before modifying the ISRMAn bit.
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17.2.5 Operation mode setting register 1 (ASIMAn1) (n = 0, 1)
The ASIMAn1 register is an 8-bit register that controls serial communication of the serial interface UARTAn. The ASIMAn1 register can be set by 1-bit or 8-bit memory manipulation instructions. The ASIMAn1 register must be modified while TXEAn = 0 and RXEAn = 0. The value of this register is 1AH following a reset.
Figure 17 - 6 Format of Operation Mode Setting Register 1 (ASIMAn1)
Address: After reset: R/W:
F0303H (ASIMA01), F030BH (ASIMA11) 1AH R/W
Symbol
7
ASIMAn1
0
6
5
4
3
2
1
0
PSn1
PSn0
CLn1
CLn0
SLn
DIRn
ALVn
PSn1
0 0 1 1
PSn0
0 1 0 1
Transmission/reception parity bit setting 1, 0
Transmission
Reception
No parity bit is output.
Data is received without parity.
0 parity is output.
Data is received with 0 parity.Note
Odd parity is output.
Check is made for odd parity.
Even parity is output.
Check is made for even parity.
CLn1 0 0 1 1
CLn0 0 1 0 1
Transmission/reception character length setting 1, 0 Character length of data = 5 bits Setting prohibited Character length of data = 7 bits Character length of data = 8 bits
SLn
0
Stop bit length = 1 bit
1
Stop bit length = 2 bits
Transmission stop bit length setting
DIRn 0 1
MSB first LSB first
Transmission/reception order setting
ALVn
Transmission/reception level setting
0
Positive logic (wait state = high level, start bit = low level, stop bit = high level)
1
Negative logic (wait state = low level, start bit = high level, stop bit = low level)
Note
When "Data is received with 0 parity" is set, parity check is not performed. Accordingly the PEAn bit of the ASISAn register is not set: no error interrupts are generated.
Caution 1. Clear both the TXEAn and RXEAn bits to 0 before modifying the ASIMAn1 register. Caution 2. Reception is always handled as including a stop bit. The setting of the SLn bit does not affect
reception.
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17.2.6 Baud rate generator control register (BRGCAn) (n = 0, 1)
The BRGCAn register sets the frequency divisor for the 8-bit counter in the serial interface UARTAn. The BRGCAn register can be set by an 8-bit memory manipulation instruction. The value of this register is FFH following a reset.
Figure 17 - 7 Format of Baud Rate Generator Control Register (BRGCAn)
Address: After reset: R/W:
F0304H (BRGCA0), F030CH (BRGCA1) FFH R/W
Symbol
7
6
5
4
3
2
1
0
BRGCAn
Bits 7 to 0
Function
--
Controls the UART baud rate (serial transfer speed).
For details on the settings, see Table 17 - 2.
Caution Modify the BRGCAn bits while the TXEAn and RXEAn bits are 0 (in the transmission/reception stopped state).
Table 17 - 2 BRGCAn Settings
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 k
Selection of 8-bit counter output clock
0
0
0
0
0
0
0
X
X
Setting prohibited
0
0
0
0
0
0
1
0
2
fUTAn/2
0
0
0
0
0
0
1
1
3
fUTAn/3
:
:
:
:
:
:
:
:
:
:
1
1
1
1
1
1
0
0 252
fUTAn/252
1
1
1
1
1
1
0
1 253
fUTAn/253
1
1
1
1
1
1
1
0 254
fUTAn/254
1
1
1
1
1
1
1
1 255
fUTAn/255
Caution The baud rate is one half the frequency of the output clock signal from the 8-bit counter.
Remark 1. k: The value set with the BRGCAn register (k = 2, 3, 4, 5, 6, ..., 255) Remark 2. X: Don't care.
For an example of the baud rate setting, see 17.3.4 (3) (c) Baud rate setting example.
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17.2.7 Status register (ASISAn) (n = 0, 1)
The ASISAn register indicates the error status and the transmission status on completion of reception by the serial interface UARTAn. It consists of three error flag bits (PEAn, FEAn, and OVEAn) and two transmission status flag bits (TXBFAn and TXSFAn). The ASISAn register is read-only and can be read by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset. The PEAn, FEAn, and OVEAn bits are initialized by clearing the UARTAENn or RXEAn bit to 0. These bits are also cleared by writing to the corresponding bit of the ASCTAn register. The TXBFAn and TXSFAn bits are initialized by clearing the UARTAENn or TXEAn bit to 0.
Figure 17 - 8 Format of Status Register (ASISAn)
Address: After reset: R/W:
F0305H (ASISA0), F030DH (ASISA1) 00H R
Symbol
7
ASISAn
0
6
5
4
3
0
TXBFAn TXSFAn
0
2 PEAn
1 FEAn
0 OVEAn
TXBFAn --
Transmit buffer data flag [Setting condition] · Data is written to the TXBAn register. (Data exists in the TXBAn register.) [Clearing conditions] · The UARTAENn or TXEAn bit is cleared to 0. · Data is transferred to the transmit shift register.
TXSFAn --
Transmit shift register data flag [Setting condition] · Data is transferred from the TXBAn register. (Data is being transmitted.) [Clearing conditions] · The UARTAENn or TXEAn bit is cleared to 0. · Data is transferred from the transmit shift register and then no subsequent data is transferred
from the TXBAn register.
PEAn --
Parity error flag [Setting condition] · The parity of the received data does not match the parity bit. [Clearing conditions] · The UARTAENn or RXEAn bit is cleared to 0. · 1 is written to the PECTAn bit.
FEAn --
Framing error flag [Setting condition] · A stop bit is not detected when receiving data. [Clearing conditions] · The UARTAENn or RXEAn bit is cleared to 0. · 1 is written to the FECTAn bit.
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CHAPTER 17 SERIAL INTERFACE UARTA (UARTA)
OVEAn
Overrun error flag
--
[Setting condition]
· The next reception is completed before the receive data in the RXBAn register is read.
[Clearing conditions]
· The UARTAENn or RXEAn bit is cleared to 0.
· 1 is written to the OVECTAn bit.
Caution 1. Be sure to clear bits 7, 6, and 3 to 0. Caution 2. For continuous transmission, be sure to check that the TXBFAn flag is 0 after writing the first transmit
data (the first byte) to the TXBAn register and then write the next transmit data (the second byte) to the TXBAn register. Otherwise, the transmit data become undefined. However, the TXBFAn flag need not be checked when continuous transmission is performed by using the transmit buffer empty interrupt (ISSMAn bit = 1). Caution 3. When initializing the transmission unit (TXEAn = 0) after completion of continuous transmission, be sure to check that the TXSFAn flag is 0 after the transmission completion interrupt is generated, and then initialize the unit. Otherwise, the transmit data become undefined. Caution 4. The operation of the PEAn bit depends on the setting of the PSn1 and PSn0 bits of the ASIMAn1 register. Caution 5. For the receive data, only the first 1 bit of the stop bits is checked regardless of the stop bit length. Caution 6. When an overrun error occurs, the next receive data is not written to the RXBAn register and discarded.
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17.2.8 Status clear trigger register (ASCTAn) (n = 0, 1)
The ASCTAn register sets the trigger to clear the error status on completion of reception of the serial interface UARTAn. It contains 3 bits of the error clear trigger flags (PECTAn, FECTAn, and OVECTAn). The ASCTAn register can be written by an 8-bit or 1-bit memory manipulation instruction. When the ASCTAn register is read, 00H is always read. The value of this register is 00H following a reset. Writing 1 to the PECTAn, FECTAn, and OVECTAn bits clears the PEAn, FEAn, and OVEAn bits of the ASISAn register, respectively. When writing 0, the corresponding error flags are not cleared.
Figure 17 - 9 Format of Status Clear Trigger Register (ASCTAn)
Address: After reset: R/W:
F0306H (ASCTA0), F030EH (ASCTA1) 00H R/W
Symbol
7
6
5
4
3
<2>
<1>
<0>
ASCTAn
0
0
0
0
0
PECTAn FECTAn OVECTAn
PECTAn
Note
Parity error flag clear trigger
0
Does not clear the PEAn flag. (The flag is retained.)
1
Clears the PEAn flag.
FECTAn
Note
Framing error flag clear trigger
0
Does not clear the FEAn flag. (The flag is retained.)
1
Clears the FEAn flag.
OVECTAn
Note
Overrun error flag clear trigger
0
Does not clear the OVEAn flag. (The flag is retained.)
1
Clears the OVEAn flag.
Note
When reading the ASCTAn register, 0 is returned.
Caution
After writing 1 to the trigger bit, the corresponding error flag is cleared on the next rising edge of the operating clock (fUTAn). Accordingly, if reading the ASISAn register immediately after writing 1 to the trigger bit, the corresponding error flag may not have been cleared yet.
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CHAPTER 17 SERIAL INTERFACE UARTA (UARTA)
17.2.9 UARTA clock select register 0 (UTA0CK)
The UTA0CK register selects the operating clock of the UARTAn. The UTASEL1 and UTASEL0 bits select the clock source, fSEL, for UARTAn from fMXP, fIH, and fIMP. The bits from UTA0CK3 to UTA0CK0 select the operating clock for UARTA0 from fSEL/1 to fSEL/64, fSXP, and ELCL. Setting the UTA0OEN bit to 1 selects the UARTA0 clock output mode, and the operating clock for UARTA0 is output from the CLKA0 pin.
Figure 17 - 10 Format of UARTA0 Clock Select Register (UTA0CK)
Address: After reset: R/W:
F0310H 00H R/W
Symbol
7
6
5
4
3
2
1
0
UTA0CK UTA0OEN
0
UTASEL1 UTASEL0 UTA0CK3 UTA0CK2 UTA0CK1 UTA0CK0
UTA0OEN
0
Disables CLKA0 output.
1
Enables CLKA0 output.
UARTA0 clock output function enable
UTASEL1 0 0 1 1
UTASEL0
0
Stop
1
fMXP
0
fIHP
1
fIMP
fSEL clock select
UTA0CK3 UTA0CK2 UTA0CK1 UTA0CK0
UARTA0 operation clock select (fUTA0)
0
0
0
0
fSEL
0
0
0
1
fSEL/2
0
0
1
0
fSEL/4
0
0
1
1
fSEL/8
0
1
0
0
fSEL/16
0
1
0
1
fSEL/32
0
1
1
0
fSEL/64
1
0
0
0
fSXP
1
0
0
1
ELCL
Other than above
Setting prohibited
Caution This register should be read or written when the TXEAn and RXEAn bits are 0 (in the transmission/reception stopped state).
Remark
fMXP: High-speed peripheral clock frequency fIHP: High-speed on-chip oscillator peripheral clock frequency fIMP: Middle-speed on-chip oscillator peripheral clock frequency fSXP: Low-speed peripheral clock frequency fSEL: Selected clock to be divided for the UARTA ELCL: Event input from the ELCL
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17.2.10 UARTA clock select register 1 (UTA1CK)
The UTA1CK register selects the operating clock of UARTA1. The bits from UTA1CK3 to UTA1CK0 select the operating clock for UARTA1 from fSEL/1 to fSEL/64, fSXP, and ELCL. Setting the UTA1OEN bit to 1 selects the UARTA1 clock output mode, and the operating clock for UARTA1 is output from the CLKA1 pin.
Figure 17 - 11 Format of UARTA1 Clock Select Register (UTA1CK)
Address: After reset: R/W:
F0311H 00H R/W
Symbol
7
6
5
4
3
2
1
0
UTA1CK UTA1OEN
0
0
0
UTA1CK3 UTA1CK2 UTA1CK1 UTA1CK0
UTA0OEN
0
Disables CLKA1 output.
1
Enables CLKA1 output.
UARTA1 clock output function enable
UTA1CK3 UTA1CK2 UTA1CK1 UTA1CK0
UARTA1 operation clock select (fUTA1)
0
0
0
0
fSEL
0
0
0
1
fSEL/2
0
0
1
0
fSEL/4
0
0
1
1
fSEL/8
0
1
0
0
fSEL/16
0
1
0
1
fSEL/32
0
1
1
0
fSEL/64
1
0
0
0
fSXP
1
0
0
1
ELCL
Other than above
Setting prohibited
Caution This register should be read or written when the TXEAn and RXEAn bits are 0 (in the transmission/reception stopped state).
Remark
fSXP: Low-speed peripheral clock frequency fSEL: Selected clock to be divided for the UARTA ELCL: Event input from the ELCL
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17.2.11 UART loopback select register (ULBS)
The ULBS register is used to enable the UART loopback function. This register has a bit to control loopback for each UART. Setting a bit to 1 enables the loopback function for the given UART, with the output from the transmit shift register being looped back to the receive buffer register. The ULBS register can be set by 1-bit or 8-bit memory manipulation instructions. The value of the ULBS register is 00H following a reset.
Figure 17 - 12 Format of the UART Loopback Select Register (ULBS)
Address: After reset: R/W:
F0079H 00H R/W
Symbol
7
ULBS
0
6
<5>
<4>
<3>
<2>
<1>
<0>
0
ULBS5
ULBS4
ULBS3
ULBS2
ULBS1
ULBS0
ULBS5 0 1
Selection of the UART loopback function The state of the RxDA1 pin of the serial interface UARTA1 is input to the receive shift register. The output from the transmit shift register is looped back to the receive shift register.
ULBS4
Selection of the UART loopback function
0
The state of the RxDA0 pin of the serial interface UARTA0 is input to the receive shift register.
1
The output from the transmit shift register is looped back to the receive shift register.
Caution 1. Be sure to clear bits 7 and 6 to "0". Caution 2. When using the loopback function in UARTA0, set the PFOE14 bit of the port function output enable
register 1 (PFOE1) to 1.
Remark The RxDA0 pin can be used only in the products with 36 to 128 pins. The RxDA1 pin can be used only in the products with 44 to 128 pins.
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17.3
Operation
UARTAn operates in the following two modes. · Operation stop mode · UART mode
CHAPTER 17 SERIAL INTERFACE UARTA (UARTA)
17.3.1 Operation Stop Mode
In the operation stop mode, serial communication is not performed, and thus the power consumption can be reduced. In addition, in this mode, the pins can be used as ordinary port pins. To set the operation stop mode, clear bits 7, 6, and 5 (UARTAENn, TXEAn, RXEAn) of the ASIMAn0 register to 0. The bus clock is not stopped by the above setting. To completely stop operation, clear the UTAEN bit of the PER1 register to 0 after the above setting.
17.3.2 UART Mode
In this mode, one byte of data is transmitted and one byte is received following the start bit. That is, operation is full duplex. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates.
(1) Communication procedure Figure 17 - 13 shows the flowchart of communication procedure.
Figure 17 - 13 Flowchart of Communication Procedure
Enable clock supply
Set the UTAEN bit of the PER1 register to 1.
Baud rate setting Operation mode setting 1 Operation mode setting 2
Enable operation Enable communication
Write transmit data
Set the BRGCAn register.
Set bits 0 to 6 (ALVn, DIRn, SLn, CLn0, CLn1, PSn0, and PSn1) of the ASIMAn1 register.
Set bits 0 and 1 (ISRMAn and ISSMAn) of the ASIMAn0 register.
Set bit 7 (UARTAENn) of the ASIMAn0 register to 1.
Set bit 6 (TXEAn) of the ASIMAn0 register to 1 to enable transmission. Set bit 5 (RXEAn) of the ASIMAn0 register to 1 to enable reception.
Write transmit data to the TXBAn register.
Start of transmission
Caution When using the receiving function, set the port mode registers to input mode. When using the transmitting function, set the port mode registers to output mode, and set the port registers to 1.
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Using a port pin with a multiplexed serial data output function (P83/TxDA0Note 3) for serial data output requires setting the corresponding bit in the port mode register (PMxx) to 0 and the corresponding bit in the port register (Pxx) to 1. Using a port pin with a multiplexed serial clock output function (P85/CLKA0Note 3) for serial clock output requires setting the corresponding bit in the port mode register (PMxx) to 0 and the corresponding bit in the port register (Pxx) to 1. When using the port pin in N-ch open drain output (VDD toleranceNote 1/EVDD toleranceNote 2) mode, set the corresponding bit in the port output mode register (POMxx) to 1. When connecting an external device operating on a different potential (1.8 V, 2.5 V or 3 V), see 4.4.5 Handling different potential (1.8 V, 2.5 V, or 3 V) by using I/O buffers.
Example: When P83/TxDA0 is to be used for serial data outputNote 3 Set the PM83 bit of the port mode register 8 to 0. Set the P83 bit of the port register 8 to 1.
Using a port pin with a multiplexed serial data or serial clock input function (e.g. P84/RxDA0Note 3) for serial data or serial clock input requires setting the corresponding bit in the port mode register (PMxx) to 1. In this case, the corresponding bit in the port register (Pxx) can be set to 0 or 1. When the TTL input buffer is selected, set the corresponding bit in the port input mode register (PIMxx) to 1. When connecting an external device operating on a different potential (1.8 V, 2.5 V or 3 V), see 4.4.5 Handling different potential (1.8 V, 2.5 V, or 3 V) by using I/O buffers.
Example: When P84/RxDA0 is to be used for serial data inputNote 3 Set the PM84 bit of the port mode register 8 to 1. Set the P84 bit of the port register 8 to 0 or 1.
Note 1. Note 2. Note 3.
For products with 30 to 52 pins For products with 64 to 128 pins For products with 100 to 128 pins
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(2) Format and waveform example of transmit/receive data The following describes the communication data format of UARTAn. Figure 17 - 14 shows the data format.
Figure 17 - 14 Transmit/Receive Data Format
1. LSB first
One data frame
Start
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Stop
Character bits
2. MSB first
One data frame
Start
D7
D6
D5
D4
D3
D2
D1
D0
Parity
Stop
Character bits
One data frame consists of the following bits. · Start bit: 1 bit · Character bits: 5, 7 or 8 bits · Parity bit: Even parity, odd parity, 0 parity, or no parity · Stop bit: 1 or 2 bits The character bit length, the parity, the stop bit length, the transfer direction (LSB/MSB first), and the TxDAn pin output (direct/inverted) in one data frame are specified by the ASIMAn1 register.
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CHAPTER 17 SERIAL INTERFACE UARTA (UARTA)
Figure 17 - 15 shows the examples of transmit/receive data waveforms. Figure 17 - 15 Example of Transmit/Receive Data Waveform
Character length: 8 bits, LSB first, Even parity, Stop bit: 1 bit, Transfer data: 55H One data frame
Start
D0
D1
D2
D3
D4
D5
D6
Character length: 8 bits, MSB first, Even parity, Stop bit: 1 bit, Transfer data: 55H One data frame
D7
Parity
Stop
Start
D7
D6
D5
D4
D3
D2
D1
D0
Parity
Stop
Character length: 8 bits, MSB first, Even parity, Stop bit: 1 bit, Transfer data: 55H, Transmit/receive data level inversion One data frame
Start
D7
D6
D5
D4
D3
D2
D1
D0
Parity
Stop
Character length: 7 bits, LSB first, Odd parity, Stop bit: 2 bits, Transfer data: 36H One data frame
Start
D0
D1
D2
D3
D4
D5
D6
Parity
Stop
Stop
Character length: 5 bits, LSB first, No parity, Stop bit: 1 bit, Transfer data: 17H One data frame
Start
D0
D1
D2
D3
D4
Stop
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CHAPTER 17 SERIAL INTERFACE UARTA (UARTA)
(3) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmitting and reception sides. With even/odd parity, a 1-bit (odd number) error can be detected. With zero/no parity, an error cannot be detected.
(a) Even parity · In transmission Data for transmission, including the parity bit, are controlled so that an even number of bits have the value "1". The value of the parity bit is set as follows. If the data for transmission have an odd number of bits with the value "1": 1 If the data for transmission have an even number of bits with the value "1": 0 · In reception In the data for reception, including the parity bit, the number of bits with the value "1" , is counted. If it is odd, a parity error occurs.
(b) Odd parity · In transmission Unlike even parity, data for transmission, including the parity bit, are controlled so that an odd number of bits have the value "1". If the data for transmission have an odd number of bits with the value "1": 0 If the data for transmission have an even number of bits with the value "1": 1 · In reception In the data for reception, including the parity bit, the number of bits with the value "1" , is counted. If it is even, a parity error occurs.
(c) 0 parity The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. The parity bit is not detected when the data is received. Therefore, a parity error does not occur regardless of whether the parity bit is "0" or "1".
(d) No parity No parity bit is appended to the transmit data. Reception is performed assuming that there is no parity bit. A parity error does not occur, because there is no parity bit.
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CHAPTER 17 SERIAL INTERFACE UARTA (UARTA)
(4) Normal transmission Transmission is enabled by setting bit 7 (UARTAENn) of the operation mode setting register 0 (ASIMAn0) to 1 and then setting bit 6 (TXEAn) of ASIMAn0 to 1. Transmission can be started by writing the data for transmission to the transmission buffer register (TXBAn). The start bit, parity bit, and stop bit are automatically appended to the data. When transmission is started, the data in the TXBAn register are transferred to the transmit shift register. After that, the transmit data are sequentially output from the transmit shift register to the TxDAn pin in the specified transfer direction. When transmission is completed, the parity and stop bits which are set by the ASIMAn0 register are appended and a transmission completion interrupt request signal (INTUTn) is generated. Transmission is suspended until the next transmit data is written to the TXBAn register.
Figure 17 - 16 shows the timing of the transmission completion interrupt request signal (INTUTn). INTUTn is issued at the following timing.
(a) When ISSMAn = 0 (INTUTn functions as a transmission completion interrupt.) INTUTn is issued after the output of the last stop bit.
(b) ISSMAn = 1 (INTUTn functions as a transfer buffer empty interrupt.) INTUTn is issued when the start bit is output.
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Figure 17 - 16 Interrupt Output Timing
(1) When ISSMAn = 0 (Transmission completion interrupt)
Stop bit: 1 bit
One data frame
Start
D0
D1
D2
D3
D4
D5
D6
D7
Parity Stop
INTUTn
Stop bit: 2 bits
One data frame
Start
D0
D1
D2
D3
D4
D5
D6
D7
Parity Stop
Stop
INTUTn
(2) When ISSMAn = 1 (Transmit buffer empty interrupt)
Stop bit: 1 bit
One data frame
Start
D0
D1
D2
D3
D4
D5
D6
D7
Parity Stop
INTUTn
Stop bit: 2 bits
One data frame
Start
D0
D1
D2
D3
D4
D5
D6
D7
Parity Stop
Stop
INTUTn
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(5) Continuous transmission
UARTAn has two separate registers for continuous transmission: the transmit buffer register (TXBAn) and the transmit shift register. At the moment the transmit shift register starts a shift operation, the next transmit data can be written to the transmit buffer register (TXBAn). This operation enables continuous transmission, thereby improving communication rate. Note that continuous transmission is not achieved when writing to the TXBAn register is not completed within the maximum number of clock cycles defined below from generation of the transmit buffer register (TXBAn) empty interrupt.
Maximum number of clock cycles = Data transfer length × 2k - (2k + 3) k: the value set with the BRGCAn bits (k = 2, 3, 4, 5, 6, ..., 255)
An example of calculating the maximum number of clock cycles is described below. When the BRGCAn register = 02H (k = 2), start bit = 1 bit, character length = 8 bits, parity used, and stop bit = 1 bit: The maximum number of clock cycles = Transfer length × 2k - (2k + 3) = 11 × 2 × 2 - (2 × 2 + 3) = 37 (Writing must be completed within 37 clock cycles.)
Continuous transmission is achieved by the following two methods.
(a) Continuous transmission by polling
Continuous transmission is achieved by polling the transmit buffer data flag (bit 5: TXBFAn) and the transmit shift register data flag (bit 4: TXSFAn) of the status register (ASISAn). When using this method, clear bit 1 (ISSMAn) of the operation mode setting register 0 (ASIMAn0) to 0.
· At the start of and during continuous transmission
At the start of continuous transmission, write the first byte of data to the TXBAn register, check that the transmit buffer data flag (TXBFAn) is 0, and then write the second byte of data. In a similar way, check that the TXBFAn flag is 0 and then write the subsequent data to the TXBAn register.
TXBFAn
Determination flag indicating that writing to TXBAn is enabled or disabled at the start of continuous transmission
0
Writing is enabled.
1
Writing is disabled.
Caution To determine if continuous transmission is enabled or disabled, only check the TXBFAn flag. The TXSFAn flag must not be used for the determination in combination with this flag.
· Completion of continuous transmission
In continuous transmission, when data in the transmit shift register and the TXBAn register are transmitted after the required number of transmit data are written to the TXBAn register, the continuous transmission is completed. To confirm the completion, check the setting of the transmit shift register data flag (TXSFAn).
TXSFAn
Confirmation flag indicating whether transmission is in progress or not
0
Transmission is completed.
1
Transmission is in progress.
Caution 1. When initializing the transmission unit after completion of continuous transmission, check that the TXSFAn flag is 0 after the transmission completion interrupt is generated, and then initialize the unit.
Caution 2. During continuous transmission, after transmission of one data frame, the subsequent transmission may be completed before execution of the INTUTn interrupt processing. This can be detected by incorporating the program that counts the number of transmit data and by referencing the TXSFAn flag.
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Figure 17 - 17 shows a flow example of continuous transmission processing by polling. Figure 17 - 17 Flow Example of Continuous Transmission Processing by Polling
Set registers
ISSMAn = 0
The required number of transmit data are written
to TXBAn?
NO
YES
Read ASISAn
NO
TXBFAn = 0?
YES
Write transmit data to TXBAn
Read ASISAn TXSFAn = 0?
NO
YES
End of transmission processing
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(b) Continuous transfer by using an interrupt Continuous transmission is achieved by using the interrupt (INTUTn). An interrupt can be generated when data in the transmit buffer register (TXBAn) are transferred to the transmit shift register by setting bit 1 (ISSMAn) to 1 in the operation mode setting register 0 (ASIMAn0). With this setting, continuous transmission is enabled by writing data to the TXBAn register on occurrence of the INTUTn interrupt. In addition, the transfer completion interrupt can be generated on completion of continuous transmission by clearing the ISSMAn bit to 0 after writing the last transmit data to the TXBAn register.
Figure 17 - 18 shows a flow example of continuous transmission using interrupt.
Figure 17 - 18 Flow Example of Continuous Transmission Using Interrupt
Set registers
(ISSMAn = 1)
Write to TXBAn
Waiting for INTUTn
Transmit buffer register empty interrupt
Generation of INTUTn
The required number
NO
of transmit data are
written to TXBAn?
YES
Set ASIMAn0
( ISSMAn = 0)
Waiting for INTUTn
Transfer completion interrupt
Generation of INTUTn
End of transmission processing
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CHAPTER 17 SERIAL INTERFACE UARTA (UARTA)
Figure 17 - 19 and Figure 17 - 20 show the timing charts when the continuous transmission is started and completed, respectively.
Figure 17 - 19 Timing Chart When Continuous Transmission Is Started
TxDAn ISSMAn INTUTn
TXBAn 00H
Start
Data 1
Parity Stop Start
Output when ISSM = 1 Data 1
Data 2
Data 2
Parity Stop Start
Data 3
Shift register 00H
Data 1
Data 2
Data 3
TXBFAn TXSFAn
Caution When the ASISAn register is read, both the TXBFAn and TXSFAn bits are read as 1 within this period. Accordingly, use only the TXBFAn flag to determine if writing is enabled or disabled.
Figure 17 - 20 Timing Chart When Continuous Transmission Is Completed
TxDAn
Parity Stop Start
ISSMAn
INTUTn
TXBAn Data n - 1
Data n - 1
Parity Stop Start
Data n
Parity Stop
Data n
Output when ISSM = 0
Shift register
Data n - 1
Data n
00H
TXBFAn
TXSFAn UARTAENn or
TXEAn
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(6) Normal reception
When setting bit 7 (UARTAENn) of the operation mode setting register 0 (ASIMAn0) to 1 and then setting bit 5 (RXEAn) of the ASIMAn0 register to 1, reception is enabled, and sampling of the input to the RxDAn pin is performed. When the ALVn bit is 0, the 8-bit counter of the baud rate generator starts counting on detection of the falling edge on the RxDAn pin. When the counter reaches the set value of the baud rate generator control register (BRGCAn), the input to the RxDAn pin is sampled again (at the point indicated with in Figure 17 - 21). If the RxDAn pin is low, it is regarded as a start bit. When the ALVn bit is 1, the 8-bit counter of the baud rate generator starts counting on detection of the rising edge on the RxDAn pin. When the counter reaches the set value of the baud rate generator control register (BRGCAn), the input to the RxDAn pin is sampled again (at the point indicated with in Figure 17 - 21). If the RxDAn pin is high, it is regarded as a start bit. Figure 17 - 21 shows the timing chart of receive operation. On detection of a start bit, receive operation is started: serial data is sequentially stored in the receive shift register at a specified baud rate. On reception of a stop bit, the reception completion interrupt (INTURn) is generated, and at the same time, the data in the receive shift register is written to the receive buffer register (RXBAn). Note that when an overrun error (OVEAn) occurs, the data received on occurrence of the error is not written to the RXBAn register. When a parity error (PEAn) or a framing error (FEAn) occurs during reception, reception continues until a stop bit is received. After completion of the reception, the reception error interrupt (INTURn/INTUREn) set in the ISRMAn bit is generated. When a reception error occurs, read the status register (ASISAn) and then read the receive buffer register (RXBAn) to clear the error flag. If the receive buffer register (RXBAn) is not read, an overrun error will occur when the next data is received: the reception error state will continue. Reception is always handled as including a stop bit. Accordingly, the second stop bit is ignored.
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RL78/G23 Figure 17 - 21 Timing of UART Receive Operation
CHAPTER 17 SERIAL INTERFACE UARTA (UARTA)
Stop bit : 1 bit
One data frame
RxDAn
Start
D0
D1
D2
D3
D4
D5
D6
D7
Parity Stop
rxd_in INTURn RXBAn
Start
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Stop
Stop bit : 2 bits
One data frame
Writing to RXBAn
RxDAn
Start
D0
D1
D2
D3
D4
D5
D6
D7
Parity Stop
Stop
rxd_in INTURn RXBAn
Start
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Stop
Writing to RXBAn
Remark 1. rxd_in: The internal signal generated by latching RxDAn with a noise filter (rxd_in is delayed relative to RxDAn by maximum of 3 cycles of the UART operation clock.)
Remark 2. The INTUR output timing in the figure is just an example. The timing relative to RxDAn varies according to the setting of the BRGCAn register.
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CHAPTER 17 SERIAL INTERFACE UARTA (UARTA)
(7) Reception error
Three types of errors may occur during reception; parity error, framing error, and overrun error. When these errors occur, the corresponding error flag in the status register (ASISAn) is set, and the reception error interrupt (INTURn or INTUREn) is generated. The type of the reception error can be identified by the reception error interrupt processing routine, which reads and checks the contents of the status register (ASISAn). The contents of the ASISAn register is cleared to 0 by setting the corresponding bit of the status clear trigger register (ASCTAn) to 1. Table 17 - 3 shows the causes of the reception errors.
Table 17 - 3 Causes of Reception Errors
Error flag
Reception error
PEAn
Parity error
FEAn OVEAn
Framing error Overrun error
Cause
The parity specified for reception does not match the parity of receive data.
No stop bit is detected.
Before the receive data is read from the receive buffer, the next data reception is completed.
Setting bit 0 (ISRMAn) of the operation mode setting register 0 (ASIMAn0) to 0 allows the reception error interrupt to be separated from the reception completion interrupt (INTURn) and allows it to be generated as the error interrupt (INTUREn). Figure 17 - 22 shows the interrupt output waveform which varies depending on the setting of the ISRMAn bit.
Figure 17 - 22 Various Interrupt Output Waveforms Depending on ISRMAn Setting
When ISRMAn = 0, the error interrupt is separated from INTUR.
Reception is completed without an error.
Reception is completed with an error.
INTURn
INTURn
INTUREn
INTUREn
When ISRMAn = 1, the error interrupt is included in INTUR.
Reception is completed without an error.
Reception is completed with an error.
INTURn
INTURn
INTUREn
INTUREn
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CHAPTER 17 SERIAL INTERFACE UARTA (UARTA)
17.3.3 Receive Data Noise Filter
This filter samples the receive data (RxDAn), and determines the level when the same level is sampled twice. The receive data is delayed by maximum of three cycles of the operating clock because of the circuit configuration. Figure 17 - 23 shows the noise filter circuit.
Figure 17 - 23 Noise Filter
UARTAENn
Match detector
RxDAn
Internal signal enb
RXEAn Operating clock
Caution 1. When ALVn = 0 (wait state = high level; start bit = low level), the initial value of the receive data (RxDAn) needs to be "high".
Caution 2. When ALVn = 1 (wait state = low level; start bit = high level), the initial value of the receive data (RxDAn) needs to be "low".
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CHAPTER 17 SERIAL INTERFACE UARTA (UARTA)
17.3.4 Baud Rate Generator
The baud rate generator consists of 8-bit programmable counters, and generates a serial clock for transmission/reception of UARTAn. An 8-bit counter is provided each for transmission and reception.
(1) Configuration of baud rate generator (a) UARTAn operation clock
When bit 7 (UARTAENn) = 1 in the operation mode setting register 0 (ASIMAn0), the UARTAn operation clock (fUTAn) is supplied to each module. When UARTAENn = 0, the UARTAn operation clock is fixed to low level.
(b) Transmission counter This counter is cleared to 0 and stops when bit 7 (UARTAENn) = 0 or bit 6 (TXEAn) = 0 in the operation mode setting register 0 (ASIMAn0). It starts counting when UARTAENn = 1 and TXEAn = 1. The counter is cleared to 0 when the first transmit data is written to the transmit buffer register (TXBAn). When continuous transmission is performed, the counter is cleared to 0 again when transmission of one frame of data has been completed. If there is no data to be transmitted next, the counter is not cleared to 0 and continues counting until the UARTAENn or TXEAn bit is cleared to 0. When UARTAENn = 0 or TXEAn =0 in the ASIMAn0 register, the counter stops at 00H.
(c) Reception counter This counter is cleared to 0 and stops when bit 7 (UARTAENn) = 0 or bit 5 (RXEAn) = 0 in the operation mode setting register 0 (ASIMAn0). It starts counting when the start bit is detected. The counter stops operation after one frame has been received, until the next start bit is detected. When UARTAENn = 0 or RXEAn = 0 in the ASIMAn0 register, the counter stops at 00H.
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CHAPTER 17 SERIAL INTERFACE UARTA (UARTA)
Figure 17 - 24 shows the configuration of the baud rate generator. Figure 17 - 24 Configuration of Baud Rate Generator
Baud rate generator
UARTAENn, TXEAn (or RXEAn )
fUTAn
8-bit counter Match detector
1/2
Baud rate
Bits 7 to 0 of BRGCAn
(2) Generation of serial clock A serial clock to be generated can be specified by using the baud rate generator control register (BRGCAn). The baud rate generator divides the frequency of the input clock signal to the 8-bit counter (fUTAn) by the divisor set by the BRGCAn register. The result of this division is further divided by 2 to produce the serial clock.
(3) Baud rate calculation
(a) Baud rate calculation expression The baud rate can be calculated by the following expression. Baud rate = fUTAn ÷ (2 × k) [bps]
fUTAn: Frequency of operating clock k: Value set by bits 7 to 0 of the BRGCAn register (k = 2, 3, 4, ..., 255)
(b) Baud rate error The baud rate error can be calculated by the following expression.
Error =
Actual baud rate (baud rate with error) -1 ×100 [%]
Desired baud rate (correct baud rate)
Caution 1. Keep the baud rate error during transmission to within the permissible error range on the reception side.
Caution 2. Make sure that the baud rate error during reception satisfies the permissible baud rate error range during reception. Permissible baud rate error during reception is described in 17.3.4 (2) (d) Permissible baud rate range during reception.
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CHAPTER 17 SERIAL INTERFACE UARTA (UARTA)
(c) Baud rate setting example
Table 17 - 4 Set Data of Baud Rate Generator (1/4)
Desired baud rate
No division
(UTAnCK3 to UTAnCK0 =
0000B)
Error from k the desired
baud rate
In operation with fIHP = 32 MHz (UTASEL1 and UTASEL0 = 10B)
×1/2
×1/4
×1/8
×1/16
×1/32
(UTAnCK3 to UTAnCK0 =
0001B)
(UTAnCK3 to UTAnCK0 =
0010B)
(UTAnCK3 to UTAnCK0 =
0011B)
(UTAnCK3 to UTAnCK0 =
0100B)
(UTAnCK3 to UTAnCK0 =
0101B)
Error from
Error from
Error from
Error from
Error from
k the desired k the desired k the desired k the desired k the desired
baud rate
baud rate
baud rate
baud rate
baud rate
×1/64
(UTAnCK3 to UTAnCK0 =
0110B)
Error from k the desired
baud rate
200 bps
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
300 bps
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
600 bps
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
1200 bps
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
208 0.16%
2400 bps
Disabled
Disabled
Disabled
Disabled
Disabled
208 0.16% 104 0.16%
4800 bps
Disabled
Disabled
Disabled
Disabled
208 0.16% 104 0.16% 52 0.16%
9600 bps
Disabled
Disabled
Disabled
208 0.16% 104 0.16% 52 0.16% 26 0.16%
19200 bps
Disabled
Disabled
208 0.16% 104 0.16% 52 0.16% 26 0.16% 13 0.16%
38400 bps
Disabled
208 0.16% 104 0.16% 52 0.16% 26 0.16% 13 0.16%
Disabled
76800 bps 208 0.16% 104 0.16% 52 0.16% 26 0.16% 13 0.16%
Disabled
Disabled
115200 bps 139 -0.08% 69 0.64% 35 -0.79% 17 2.12%
Disabled
Disabled
Disabled
153600 bps 104 0.16% 52 0.16% 26 0.16% 13 0.16%
Disabled
Disabled
Disabled
Remark
k: Value set by bits 7 to 0 of the baud rate generator control register (BRGCAn) (k = 2, 3, 4, ..., 255) n: Unit number (n = 0, 1)
Table 17 - 5 Set Data of Baud Rate Generator (2/4)
Desired baud rate
No division
(UTAnCK3 to UTAnCK0 =
0000B)
Error from k the desired
baud rate
In operation with fIMP = 4 MHz (UTASEL1 and UTASEL0 = 11B)
×1/2
×1/4
×1/8
×1/16
×1/32
(UTAnCK3 to UTAnCK0 =
0001B)
(UTAnCK3 to UTAnCK0 =
0010B)
(UTAnCK3 to UTAnCK0 =
0011B)
(UTAnCK3 to UTAnCK0 =
0100B)
(UTAnCK3 to UTAnCK0 =
0101B)
Error from
Error from
Error from
Error from
Error from
k the desired k the desired k the desired k the desired k the desired
baud rate
baud rate
baud rate
baud rate
baud rate
×1/64
(UTAnCK3 to UTAnCK0 =
0110B)
Error from k the desired
baud rate
200 bps
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
156 0.16%
300 bps
Disabled
Disabled
Disabled
Disabled
Disabled
208 0.16% 104 0.16%
600 bps
Disabled
Disabled
Disabled
Disabled
208 0.16% 104 0.16% 52 0.16%
1200 bps
Disabled
Disabled
Disabled
208 0.16% 104 0.16% 52 0.16% 26 0.16%
2400 bps
Disabled
Disabled
208 0.16% 104 0.16% 52 0.16% 26 0.16% 13 0.16%
4800 bps
Disabled
208 0.16% 104 0.16% 52 0.16% 26 0.16% 13 0.16%
Disabled
9600 bps
208 0.16% 104 0.16% 52 0.16% 26 0.16% 13 0.16%
Disabled
Disabled
19200 bps 104 0.16% 52 0.16% 26 0.16% 13 0.16%
Disabled
Disabled
Disabled
38400 bps 52 0.16% 26 0.16% 13 0.16%
Disabled
Disabled
Disabled
Disabled
76800 bps 26 0.16% 13 0.16%
Disabled
Disabled
Disabled
Disabled
Disabled
115200 bps 17 2.12%
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
153600 bps 13 0.16%
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Remark
k: Value set by bits 7 to 0 of the baud rate generator control register (BRGCAn) (k = 2, 3, 4, ..., 255) n: Unit number (n = 0, 1)
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CHAPTER 17 SERIAL INTERFACE UARTA (UARTA)
Table 17 - 6 Set Data of Baud Rate Generator (3/4)
Desired baud rate
No division
(UTAnCK3 to UTAnCK0 =
0000B)
Error from k the desired
baud rate
In operation with fMXP = 20 MHz (UTASEL1 and UTASEL0 = 01B)
×1/2
×1/4
×1/8
×1/16
×1/32
(UTAnCK3 to UTAnCK0 =
0001B)
(UTAnCK3 to UTAnCK0 =
0010B)
(UTAnCK3 to UTAnCK0 =
0011B)
(UTAnCK3 to UTAnCK0 =
0100B)
(UTAnCK3 to UTAnCK0 =
0101B)
Error from
Error from
Error from
Error from
Error from
k the desired k the desired k the desired k the desired k the desired
baud rate
baud rate
baud rate
baud rate
baud rate
×1/64
(UTAnCK3 to UTAnCK0 =
0110B)
Error from k the desired
baud rate
200 bps
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
300 bps
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
600 bps
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
255 2.12%
1200 bps
Disabled
Disabled
Disabled
Disabled
Disabled
255 2.12% 130 0.16%
2400 bps
Disabled
Disabled
Disabled
Disabled
255 2.12% 130 0.16% 65 0.16%
4800 bps
Disabled
Disabled
Disabled
255 2.12% 130 0.16% 65 0.16% 33 -1.36%
9600 bps
Disabled
Disabled
255 2.12% 130 0.16% 65 0.16% 33 -1.36% 16 1.73%
19200 bps
Disabled
255 2.12% 130 0.16% 65 0.16% 33 -1.36% 16 1.73%
8
1.73%
38400 bps 255 2.12% 130 0.16% 65 0.16% 33 -1.36% 16 1.73%
8
1.73%
4
1.73%
76800 bps 130 0.16% 65 0.16% 33 -1.36% 16 1.73%
8
1.73%
4
1.73%
Disabled
115200 bps 87 -0.22% 43 0.94% 22 -1.36% 11 -1.36%
Disabled
Disabled
Disabled
153600 bps 65 0.16% 33 -1.36% 16 1.73%
8
1.73%
4
1.73%
Disabled
Disabled
Remark
k: Value set by bits 7 to 0 of the baud rate generator control register (BRGCAn) (k = 2, 3, 4, ..., 255) n: Unit number (n = 0, 1)
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CHAPTER 17 SERIAL INTERFACE UARTA (UARTA)
Table 17 - 7 Set Data of Baud Rate Generator (4/4)
Desired baud rate
In operation with fSXP = 32.768 kHz
(UTAnCK3 to UTAnCK0 = 1000B)
k
Error from the desired baud rate
In operation with ELCL = 32 MHz
(UTAnCK3 to UTAnCK0 = 1001B)
k
Error from the desired baud rate
200 bps
82
-0.10%
Disabled
300 bps
55
-0.70%
Disabled
600 bps
27
-1.14%
Disabled
1200 bps
14
-2.48%
Disabled
2400 bps
7
-2.48%
Disabled
4800 bps
Disabled
Disabled
9600 bps
Disabled
Disabled
19200 bps
Disabled
Disabled
38400 bps
Disabled
Disabled
76800 bps
Disabled
208
0.16%
115200 bps
Disabled
139
-0.08%
153600 bps
Disabled
104
0.16%
Remark
k: Value set by bits 7 to 0 of the baud rate generator control register (BRGCAn) (k = 2, 3, 4, ..., 255) n: Unit number (n = 0, 1)
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CHAPTER 17 SERIAL INTERFACE UARTA (UARTA)
(d) Permissible baud rate range during reception Figure 17 - 25 shows the permissible error from the baud rate on the transmitting side during reception.
Figure 17 - 25 Permissible Baud Rate Range during Reception
Data length: 8 bits, with parity, stop bit: 1 bit One data frame (11 x FL)
Start D0
D1
D2
D3
D4
D5
D6
D7 Parity Stop
FL FLmin
Start D0
D1
D2
D3
D4
D5
D6
D7 Parity Stop
FLmax
Start D0
D1
D2
D3
D4
D5
D6
D7 Parity Stop
Latch timing
Caution Be sure to make settings so that the baud rate error during reception is within the permissible error range. Use the calculation expression below to check if the error is within the permissible range.
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CHAPTER 17 SERIAL INTERFACE UARTA (UARTA)
After the start bit is detected, the latch timing of receive data is determined by the counter specified with the baud rate generator control register (BRGCAn). If the whole frame including the stop bit has been received before this latching, reception can proceed correctly. Assuming that 11 bits of data are received, the theoretical values can be calculated as follows.
· The relation between 1-bit data length and baud rate
FL = (Brate) - 1 Brate: Baud rate of UART k: Set value of BRGCAn FL: 1-bit data length Margin of latch timing: 1 clock
· Minimum permissible data frame length (FLmin)
FLmin = 11 × FL - k - 1 × FL = 21k + 1 FL
2k
2k
· Maximum permissible baud rate for reception on the transmitting side (BRmax)
BRmax = (FLmin/11) - 1 =
22k Brate
21k + 1
· Maximum permissible data frame length (FLmax) FLmax = 21k + 1 FL × 11 20k
· Minimum permissible baud rate for reception on the transmitting side (BRmin)
BRmin = (FLmax/11)- 1 =
20k Brate
21k - 1
Table 17 - 8 shows the permissible baud rate error between UART and the transmitting side can be calculated from the above minimum and maximum baud rate expressions.
Table 17 - 8 Maximum/Minimum Permissible Baud Rate Error
Division ratio (k)
Maximum permissible baud rate error
Minimum permissible baud rate error
2
+2.32%
-2.43%
4
+3.52%
-3.61%
8
+4.14%
-4.19%
20
+4.51%
-4.53%
50
+4.66%
-4.67%
100
+4.71%
-4.71%
255
+4.74%
-4.74%
Remark 1. The permissible error of reception depends on the number of bits in one frame, input clock frequency, and division ratio (k). The higher the input clock frequency and the division ratio (k), the higher the permissible error.
Remark 2. k: Set value of BRGCAn
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CHAPTER 17 SERIAL INTERFACE UARTA (UARTA)
17.4
Points for Caution when the Serial Interface UARTA is to be Used
17.4.1 Port Setting for RxDAn Pin
When ALVn = 0 (wait state = high level, start bit = low level), the initial value of receive data (RxDAn) must be high. When ALVn = 1 (wait state = low level, start bit = high level), the initial value of receive data (RxDAn) must be low. Accordingly, port setting is required for the RxDAn pin before setting UARTAENn = 1.
17.4.2 Serial Interfaces
The serial data output (TxDA0) and serial clock output (CLKA0) of UARTA0 are selectable as inputs for the logic and event link controller (ELCL). If TxDA0 or CLKA0 is to be used as an input for the ELCL, you need to clear the corresponding bit in port function output enable register 1 (PFOE1) to 0 so that the signal is not output to the TxDA0 and CLKA0 pins. For details, see 4.3.15 Port function output enable registers (PFOEx).
17.4.3 Point for Caution when Selecting the UARTAn Operation Clock (fUTAn)
When the middle-speed on-chip oscillator peripheral clock (fIMP) is selected for fUTAn, communication may not be executed correctly due to the oscillation frequency accuracy of the middle-speed on-chip oscillator. Adjust the accuracy, therefore, by using the middle-speed on-chip oscillator trimming register (MIOTRM). When the low-speed peripheral clock (fSXP) is selected for fUTAn and the low-speed on-chip oscillator peripheral clock (fIL) is selected for fSXP, communication may not be executed correctly due to the oscillation frequency accuracy of the low-speed on-chip oscillator. Adjust the accuracy, therefore, by using the low-speed on-chip oscillator trimming register (LIOTRM).
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CHAPTER 18 REMOTE CONTROL SIGNAL RECEIVER (REMC)
CHAPTER 18 REMOTE CONTROL SIGNAL RECEIVER (REMC)
The remote control signal receiver is provided in the 32 to 128-pin products.
18.1
Remote Control Signal Receiver
The remote control signal receiver can receive data by checking the width and period of an external pulse input signal. Table 18 - 1 lists the specifications of the remote control signal receiver. Figure 18 - 1 shows a block diagram of the remote control signal receiver.
Table 18 - 1 Specifications of Remote Control Signal Receiver
Item
Description
Number of provided units
1
External pulse input
RIN0
Operating clock
Low-speed peripheral clock (fSXP) Timer interrupt (INTTM06)
Detection patterns
Header pattern Data '0' pattern Data '1' pattern Special data pattern
Receive buffer
8 bytes (64 bits)
Compare bit count
1 to 16 bits
Interrupt request signal
INTREMC
Interrupt sources
Header pattern matchNote 1 Compare matchNote 1 Completion of data receptionNote 1 Special data pattern matchNote 1 Data '0' pattern or data '1' pattern match Receive buffer full Receive error
Selectable functions
Input signal inversion Digital filter (matching three or two times)Note 2 Pattern end setting
Low power consumption
The clock supply can be stopped by setting the PER1.REMCEN bit. SNOOZE mode can shift to normal operation mode by using the REMC interrupt request signal.
Note 1. Note 2.
The interrupt mode is selectable from either the normal interrupt mode or the sequential interrupt mode. In the normal interrupt mode, the OR condition of multiple interrupt sources is applied. In the sequential interrupt mode, the AND condition of multiple interrupt sources is applied. The sampling clock of the digital filter is an operating clock selected by the REMCON1.CSRC bit, or fSXP. When transition to the SNOOZE mode is enabled, select the low-speed peripheral clock (fSXP) as the sampling clock of the digital filter.
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CHAPTER 18 REMOTE CONTROL SIGNAL RECEIVER (REMC)
Figure 18 - 1 Block Diagram of Remote Control Signal Receiver
External pulse signal input (RIN0)
fSXP
Timer interrupt (INTTM06)
REMSTC.DNFSL REMCON0
Sampling clock select
Digital filer
Operating
clock selection
REMCON1
Internal peripheral bus
Edge detection
Internal input signal
REMTIM
REMSTC.SNZON
SNOOZE mode function setting
Interrupt control
REMSTS
REMINT
Base timer
Status control
Clock request
Interrupt signal (INTREMC)
Comparator
Receive compare registers
HDPMIN D0PMIN D1PMIN SDPMIN REMPE
HDPMAX D0PMAX D1PMAX SDPMAX
Data determination
Receive registers REMRBIT
REMDAT0 REMDAT1
REMDAT7
Internal peripheral bus
Comparator
REMCPD REMCPC
REMCON0: Function select register 0 REMCON1: Function select register 1 REMSTS: Status register REMINT: Interrupt control register REMCPC: Compare control register REMCPD: Compare value setting register HDPMIN: Header pattern minimum width setting register HDPMAX: Header pattern maximum width setting register D0PMIN: Data '0' pattern minimum width setting register D0PMAX: Data '0' pattern maximum width setting register D1PMIN: Data '1' pattern minimum width setting register D1PMAX: Data '1' pattern maximum width setting register REMSTC: Receiver standby control register
SDPMIN: Special data pattern minimum width setting register SDPMAX: Special data pattern maximum width setting register REMPE: Pattern end setting register REMRBIT: Receive bit count register REMDAT0: Receive data 0 register REMDAT1: Receive data 1 register REMDAT2: Receive data 2 register REMDAT3: Receive data 3 register REMDAT4: Receive data 4 register REMDAT5: Receive data 5 register REMDAT6: Receive data 6 register REMDAT7: Receive data 7 register REMTIM: Measurement result register
Table 18 - 2 shows the input pin used for the remote control signal receiver.
Table 18 - 2 Pin Configuration of Remote Control Signal Receiver
Pin Name
I/O
RIN0
Input
External pulse signal input
Function
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CHAPTER 18 REMOTE CONTROL SIGNAL RECEIVER (REMC)
18.2
Registers to Control the Remote Control Signal Receiver
The following registers are used to control the remote control signal receiver.
· Peripheral enable register 1 (PER1) · Peripheral reset control register 1 (PRR1) · Function select register 0 (REMCON0) · Function select register 1 (REMCON1) · Status register (REMSTS) · Interrupt control register (REMINT) · Compare control register (REMCPC) · Compare value setting register (REMCPD) · Header pattern minimum width setting register (HDPMIN) · Header pattern maximum width setting register (HDPMAX) · Data '0' pattern minimum width setting register (D0PMIN) · Data '0' pattern maximum width setting register (D0PMAX) · Data '1' pattern minimum width setting register (D1PMIN) · Data '1' pattern maximum width setting register (D1PMAX) · Special data pattern minimum width setting register (SDPMIN) · Special data pattern maximum width setting register (SDPMAX) · Pattern end setting register (REMPE) · Receiver standby control register (REMSTC) · Receive bit count register (REMRBIT) · Receive data 0 register (REMDAT0) · Receive data j register (REMDATj) (j = 1 to 7) · Measurement result register (REMTIM)
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CHAPTER 18 REMOTE CONTROL SIGNAL RECEIVER (REMC)
18.2.1 Peripheral enable register 1 (PER1)
The PER1 register is used to enable or disable the supply of a clock signal to various on-chip peripheral modules. Clock supply to an on-chip peripheral module that is not to be used can be stopped to decrease power consumption and noise. To use the remote control signal receiver, be sure to set bit 1 (REMCEN) of this register to 1. The PER1 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of the PER1 register is 00H following a reset.
Figure 18 - 2 Format of Peripheral Enable Register 1 (PER1)
Address: After reset: R/W:
F00FAH 00H R/W
Symbol
<7>
PER1 DACEN
<6> SMSEN
<5> CMPEN
<4> TML32EN
<3> DTCEN
<2> UTAEN
<1> REMCEN
<0> CTSUEN
REMCEN
Control of supply of an input clock to the remote control signal receiver
0
Stops supply of an input clock.
· The SFRs used by the remote control signal receiver cannot be written.
· When an SFR used by the remote control signal receiver is read, the value returned is 00H
or 0000H.
1
Enables supply of an input clock.
· The SFRs used by the remote control signal receiver can be read and written.
Caution The functions that are mounted depend on the product. For details on the PER1 register, see the description in CHAPTER 6 CLOCK GENERATOR.
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CHAPTER 18 REMOTE CONTROL SIGNAL RECEIVER (REMC)
18.2.2 Peripheral reset control register 1 (PRR1)
The PRR1 register is used to control resetting of the on-chip peripheral modules. Each bit in this register controls resetting and release from the reset state of the corresponding on-chip peripheral module. To place the remote control signal receiver in the reset state, be sure to set bit 1 (REMCRES) of this register to 1. The PRR1 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of the PRR1 register is 00H following a reset.
Figure 18 - 3 Format of Peripheral Reset Control Register 1 (PRR1)
Address: After reset: R/W:
F00FBH 00H R/W
Symbol
<7>
<6>
<5>
<4>
3
PRR1 DACRES SMSRES CMPRES TML32RES
0
2
<1>
<0>
0
REMCRES CTSURES
REMCRES
Control resetting of the remote control signal receiver
0
The remote control signal receiver is released from the reset state.
1
The remote control signal receiver is in the reset state.
· The SFRs for use with the remote control signal receiver are initialized.
Caution 1. Be sure to set bits 3 and 2 to "0". Caution 2. The provided functions differ depending on the product. For details about the PRR1 register, see
CHAPTER 24 RESET FUNCTION.
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18.2.3 Function select register 0 (REMCON0)
The REMCON0 register has flags for indicating the operating status of the remote control signal receiver and the level of the input signal, and is used to control the input signal inversion, control the digital filter, and select the receive error capture operation. Rewriting the REMCON0 register is prohibited when the REMC is in operation (when REMCON1.EN = 1). The REMCON0 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of the REMCON0 register is 00H following a reset.
Figure 18 - 4 Format of Function Select Register 0 (REMCON0)
Address: After reset: R/W:
F0640H 00H R/WNote 1
Symbol REMCON0
7
6
5
0
FILSELNote 2
0
4 ECNote 2
<3> INFLGNote 3
2 FILNote 2
1
<0>
INVNote 2 ENFLGNote 3
FILSEL
Note 2
Digital Filter Function Select
0
Digital filter for matching three times
1
Digital filter for matching two times
ECNote 2
Receive Error Capture Operation Select
0
Captures the data after an error pattern is received.
1
Does not capture the data after an error pattern is received.
This bit can be used to set capture operation to the REMRBIT and REMDATj registers (j = 0 to 7) after an
error pattern is received.
INFLG
Note 3
Input Signal Flag
0
The level of the internal input signal of the remote control signal receiver is low.
1
The level of the internal input signal of the remote control signal receiver is high.
This flag can be used to confirm the level of the internal input signal of the remote control signal receiver. The confirmed level is the result set by the INV and FIL bits.
FILNote 2
Digital Filter Enable/Disable Setting
0
Disables the digital filter for matching three or two times.
1
Enables the digital filter for matching three or two times.
This bit enables or disables the digital filter.
INVNote 2
0
Not inverted
1
Inverted
Input Signal Inversion
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ENFLG
Note 3
Remote Control Status Flag
0
Stopped
1
Operating
This flag can be used to confirm whether the remote control signal receiver is stopped or operating.
This flag changes after zero to one cycle of the operating clock when a value is written to the REMCON1.EN
bit. Note 1. Note 2.
Note 3.
Bits 3 and 0 are read-only. These bits can be rewritten when the REMCON1.EN bit and the REMCON0.ENFLG flag are both 0 (REMC is stopped). These flags become 0 when the REMCON1.EN bit is set to 0.
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18.2.4 Function select register 1 (REMCON1)
The REMCON1 register is used to set the operation conditions of the remote control signal receiver such as operating clock, reception mode, and interrupt mode. The REMCON1 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of the REMCON1 register is 00H following a reset.
Figure 18 - 5 Format of Function Select Register 1 (REMCON1)
Address: After reset: R/W:
F0641H 00H R/W
Symbol
7
REMCON1
0
6
5
4
<3>
<2>
0
CSRCNote 1
0
INTMDNote 1
EN
1
0
TYP[1:0] Note 2
CSRCNote 1
Operating Clock Select
0
Low-speed peripheral clock (fSXP)
1
Timer interrupt (INTTM06)
Use channel 6 of timer array unit 0 in the interval timer mode.
This bit selects the operating clock for the remote control signal receiver.
INTMD
Note 1
Interrupt Mode Select
0
Normal interrupt mode (OR condition)
1
Sequential interrupt mode (AND condition)
This bit can be used to select the interrupt mode.
In normal interrupt mode, an interrupt is generated when the OR condition of the interrupt sources enabled
(set to 1) in the interrupt control register (REMINT) is met.
In sequential interrupt mode, if all the interrupt generation conditions of the sources (compare match, data
reception complete, header pattern match, and special data pattern match) whose interrupt enable bit of the
REMINT register is set to 1 are met, an interrupt (INTREMC) is generated.
EN
Remote Control
0
Operation disabled
1
Operation enabled
This bit enables or disables REMC operation. Use the REMCON0.ENFLG flag to confirm whether operation has started or not.
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TYP[1:0] Note 2
Receive Mode Select
0
0
Format A
0
1
Format B
1
0
Format C
1
1
Setting prohibited
These bits can be used to select the format for capturing the remote control signal waveform.
For details of each format, see 18.3.3 Pattern Setting.
Note 1. Note 2.
These bits can be rewritten when the REMCON1.EN bit and the REMCON0.ENFLG flag are both 0 (REMC is stopped). To rewrite the TYP[1:0] bits when the REMCON1.EN bit or REMCON0.ENFLG flag is 1 (REMC is operating), change the values of these bits one bit at a time.
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18.2.5 Status register (REMSTS)
The REMSTS register is used to indicate the reception status and error occurrence status of the remote control signal receiver. The REMSTS register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of the REMSTS register is 00H following a reset.
Figure 18 - 6 Format of Status Register (REMSTS)
Address: After reset: R/W:
F0642H 00H R/WNotes 1, 2
Symbol REMSTS
<7> SDFLG
<6> D1FLG
<5> D0FLG
<4> HDFLG
<3>
BFULFLG
Note 2
<2> DRFLG
<1> REFLG
<0> CPFLG
SDFLG
Special Data Pattern Match Flag
0
Mismatch
1
Match
<Clearing conditions>
· When the DRFLG flag changes from 0 to 1 (next frame reception starts)
· When the REFLG flag changes from 0 to 1 · See Table 18 - 3 Measurement Results and Flags.
<Setting condition> · See Table 18 - 3 Measurement Results and Flags.
D1FLG
Data '1' Pattern Match Flag
0
Mismatch
1
Match
<Clearing conditions>
· When the DRFLG flag changes from 0 to 1 (next frame reception starts)
· When the REFLG flag changes from 0 to 1 · See Table 18 - 3 Measurement Results and Flags.
<Setting condition>
· See Table 18 - 3 Measurement Results and Flags.
D0FLG
Data '0' Pattern Match Flag
0
Mismatch
1
Match
<Clearing conditions>
· When the DRFLG flag changes from 0 to 1 (next frame reception starts)
· When the REFLG flag changes from 0 to 1 · See Table 18 - 3 Measurement Results and Flags.
<Setting condition>
· See Table 18 - 3 Measurement Results and Flags.
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HDFLG
Header Pattern Match Flag
0
Mismatch
1
Match
<Clearing conditions>
· When the DRFLG flag changes from 0 to 1 (next frame reception starts)
· When the REFLG flag changes from 0 to 1 · See Table 18 - 3 Measurement Results and Flags.
<Setting condition>
· See Table 18 - 3 Measurement Results and Flags.
BFULFLG
Note 2
Receive Buffer Full Flag
0
Receive buffer is empty.
1
Receive buffer is full (64 bits received).
<Clearing conditions>
· When the HDFLG flag changes from 0 to 1
· When the DRFLG flag changes from 0 to 1 (next frame reception starts)
· This flag becomes 0 after one to two cycles of the operating clock when 0 is written to the BFULFLG flag.
<Setting condition>
· When the value of the REMRBIT register becomes 64
DRFLG
Data Receiving Flag
0
Waiting for data reception.
1
Data is being received.
This flag indicates the state of receiving the remote control signal.
<Clearing conditions>
· This flag becomes 0 after one cycle of the operating clock when the value of the base timer is greater than
any value of the HDPMAX, D0PMAX, D1PMAX, SDPMAX, and REMPE registers.
<Setting condition>
· Rising edge of REMC internal input signal (when the REMCON0.INV bit is 0)
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REFLG
Receive Error Flag
0
No error has occurred.
1
An error has occurred.
This flag indicates that a receive error has occurred. The setting conditions differ depending on the value of the REMCON1.TYP[1:0] bits. <Clearing conditions> · The header pattern is detected · When the DRFLG flag changes from 0 to 1 (next frame reception starts) <Setting conditions> When the REMCON1.TYP[1:0] bits are 00B (format A): · The data '0', data '1', or special data pattern is detected prior to receiving the header pattern · The width between a rising edge and the next rising edge of the input signal is not the header, data '0', data
'1', or special data pattern (when the REMCON0.INV bit is 0) · A conflict occurs between when data reception is completed (timing when the DRFLG flag changes from 1
to 0) and when the input signal level changes (new signal). When the REMCON1.TYP[1:0] bits are 01B (format B): · The data '0', data '1', or special data pattern is detected prior to receiving the header pattern · The width between a falling edge and the next falling edge of the input signal is not the data '0', data '1', or
special data pattern (when the REMCON0.INV bit is 0) · A conflict occurs between when data reception is completed (timing when the DRFLG flag changes from 1
to 0) and when the input signal level changes (new signal). When the REMCON1.TYP[1:0] bits are 10B (format C): · The width between a rising edge and the next rising edge of the input signal is not the header, data '0', data
'1', or special data pattern (when the REMCON0.INV bit is 0) · A conflict occurs between when data reception is completed (timing when the DRFLG flag changes from 1
to 0) and when the input signal level changes (new signal).
CPFLG
Compare Match Flag
0
Mismatch
1
Match
This flag indicates the comparison result between the value of the REMCPD register specified by the
REMCPC.CPN[3:0] bits and the data to be stored in the REMDAT1 and REMDAT0 registers.
<Clearing conditions>
· When the DRFLG flag changes from 0 to 1 (next frame reception starts)
· When the HDFLG flag changes from 0 to 1
<Setting condition>
· When the value of the REMCPD register matches the value to be stored in the REMDAT1 and REMDAT0
registers (when the setting value of the REMCPC.CPN[3:0] bits is n, bits n to 0 in the REMCPD register
match bits n to 0 in the REMDAT1 and REMDAT0 registers)
Note 1. Note 2.
Bits 7 to 4 and 2 to 0 are read-only. Bit 3 can only be written with 0 to clear the flag. However, if this flag is written when changing the
REMCON0.INFLG flag, the value read from this flag may become undefined.
Caution 1. If updating and reading data overlap, an undefined value may be read. For details on reading this register, see 18.4.5 Reading Registers.
Caution 2. This register becomes 00H when the REMCON1.EN bit is set to 0.
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Table 18 - 3 Measurement Results and Flags
Comparison Result between REMTIM Register Value (Measurement Result) and Each Register
HDFLG
Flag Value
D0FLG
D1FLG
SDFLG
Between HDPMIN and HDPMAX
1
0
0
0
Between D0PMIN and D0PMAX
0
1Note
0
0
Between D1PMIN and D1PMAX
0
0
1Note
0
Between SDPMIN and SDPMAX
0
0
0
1Note
Values not listed above
0
0
0
0
Note
When the REMCON1.TYP[1:0] bits are 00B or 01B, the D0FLG, D1FLG, and SDFLG flags remain unchanged until the header pattern is detected.
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18.2.6 Interrupt control register (REMINT)
The REMINT register is used to enable or disable generation of each interrupt. Rewriting the REMINT register is prohibited when the REMC is in operation. Rewrite this register while the REMCON1.EN bit and the REMCON0.ENFLG flag are both 0 (REMC is stopped). The REMINT register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of the REMINT register is 00H following a reset.
Figure 18 - 7 Format of Interrupt Control Register (REMINT)
Address: After reset: R/W:
F0643H 00H R/W
Symbol REMINT
<7> SDINT
6
<5>
<4>
<3>
<2>
<1>
<0>
0
DINTNote
HDINT
BFULINT DRINTNote REINT
CPINT
SDINT 0 1
Disabled Enabled
Special Data Pattern Match Interrupt Enable
DINT 0 1
Disabled Enabled
Data '0' Pattern or Data '1' Pattern Match Interrupt Enable
HDINT 0 1
Disabled Enabled
Header Pattern Match Interrupt Enable
BFULINT
0
Disabled
1
Enabled
Receive Buffer Full Interrupt Enable
DRINTNote
0
Disabled
1
Enabled
Data Receiving Interrupt Enable
REINT 0 1
Disabled Enabled
Receive Error Interrupt Enable
CPINT
Compare Match Interrupt Enable
0
Disabled
1
Enabled
Note
Rewriting this bit is also allowed when REMC is operating (when REMCON1.EN = 1).
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18.2.7 Compare control register (REMCPC)
The REMCPC register is used to specify the number of bits to compare the value of the REMCPD register and the data to be stored in the REMDAT1 and REMDAT0 registers when the compare function is used. Rewriting the REMCPC register is prohibited when the REMC is in operation. This register can be rewritten when the REMCON1.EN bit and the REMCON0.ENFLG flag are both 0 (REMC is stopped). The REMCPC register can be set by an 8-bit memory manipulation instruction. The value of the REMCPC register is 00H following a reset.
Figure 18 - 8 Format of Compare Control Register (REMCPC)
Address: After reset: R/W:
F0645H 00H R/W
Symbol
7
6
5
4
3
2
1
0
REMCPC
0
0
0
0
CPN[3:0]
CPN[3:0]
Compare Bit Count Specification
0 0 0 0 Bit 0 in the REMCPD register is compared with bit 0 in the REMDAT0 register.
0 0 0 1 Bits 1 and 0 in the REMCPD register are compared with bits 1 and 0 in the
REMDAT0 register.
·
·
0 1 1 1 Bits 7 to 0 in the REMCPD register are compared with bits 7 to 0 in the
REMDAT0 register.
·
·
1 0 0 1 Bits 9 to 0 in the REMCPD register are compared with bits 1 and 0 in the
REMDAT1 register and bits 7 to 0 in the REMDAT0 register.
·
·
1 1 1 1 Bits 15 to 0 in the REMCPD register are compared with bits 7 to 0 in the
REMDAT1 register and bits 7 to 0 in the REMDAT0 register.
When the setting value of the CPN[3:0] bits is n, bits n to 0 are compared.
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18.2.8 Compare value setting register (REMCPD)
The REMCPD register is used to set the value to be compared with the data in the REMDAT1 and REMDAT0 registers when the compare function is used. The REMCPC.CPN[3:0] bits can be used to set the number of bits to be compared. Rewriting the REMCPD register is prohibited when the REMC is in operation (when REMCON1.EN = 1). The REMCPD register can be set by a 16-bit memory manipulation instruction. The value of the REMCPD register is 0000H following a reset.
Figure 18 - 9 Format of Compare Value Setting Register (REMCPD)
Address: After reset: R/W:
F0646H, F0647H 0000H R/W
Symbol
15
14
13
12
11
10
9
8
REMCPD
CPD[15:8]
7
6
5
4
3
2
1
0
CPD[7:0]
18.2.9 Header pattern minimum width setting register (HDPMIN)
The HDPMIN register is used to set the minimum width of the header pattern. The setting range is from 000H to 7FFH. When the interval between the edges of an external input signal measured using the base timer is between HDPMIN and HDPMAX, the pattern of the signal is detected as a header pattern. Rewriting the HDPMIN register is prohibited when the REMC is in operation (when REMCON1.EN = 1). The HDPMIN register can be set by a 16-bit memory manipulation instruction. The value of the HDPMIN register is 0000H following a reset.
Figure 18 - 10 Format of Header Pattern Minimum Width Setting Register (HDPMIN)
Address: After reset: R/W:
F0648H, F0649H 0000H R/W
Symbol
15
14
13
12
11
10
9
8
HDPMIN
0
0
0
0
0
HDPMIN[10:8]
7
6
5
4
3
2
1
0
HDPMIN[7:0]
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18.2.10 Header pattern maximum width setting register (HDPMAX)
The HDPMAX register is used to set the maximum width of the header pattern. The setting range is from 000H to 7FFH. When the interval between the edges of an external input signal measured using the base timer is between HDPMIN and HDPMAX, the pattern of the signal is detected as a header pattern. Rewriting the HDPMAX register is prohibited when the REMC is in operation (when REMCON1.EN = 1). The HDPMAX register can be set by a 16-bit memory manipulation instruction. The value of the HDPMAX register is 0000H following a reset.
Figure 18 - 11 Format of Header Pattern Maximum Width Setting Register (HDPMAX)
Address: After reset: R/W:
F064AH, F064BH 0000H R/W
Symbol
15
14
13
12
11
10
9
8
HDPMAX
0
0
0
0
0
HDPMAX[10:8]
7
6
5
4
3
2
1
0
HDPMAX[7:0]
18.2.11 Data '0' pattern minimum width setting register (D0PMIN)
The D0PMIN register is used to set the minimum width of the data '0' pattern. The setting range is from 00H to FFH. When the interval between the edges of an external input signal measured using the base timer is between D0PMIN and D0PMAX, the pattern of the signal is detected as a data '0' pattern. Rewriting the D0PMIN register is prohibited when the REMC is in operation (when REMCON1.EN = 1). The D0PMIN register can be set by an 8-bit memory manipulation instruction. The value of the D0PMIN register is 00H following a reset.
Figure 18 - 12 Format of Data '0' Pattern Minimum Width Setting Register (D0PMIN)
Address: After reset: R/W:
F064CH 00H R/W
Symbol
7
6
5
4
3
2
1
0
D0PMIN
D0PMIN[7:0]
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18.2.12 Data '0' pattern maximum width setting register (D0PMAX)
The D0PMAX register is used to set the maximum width of the data '0' pattern. The setting range is from 00H to FFH. When the interval between the edges of an external input signal measured using the base timer is between D0PMIN and D0PMAX, the pattern of the signal is detected as a data '0' pattern. Rewriting the D0PMAX register is prohibited when the REMC is in operation (when REMCON1.EN = 1). The D0PMAX register can be set by an 8-bit memory manipulation instruction. The value of the D0PMAX register is 00H following a reset.
Figure 18 - 13 Format of Data '0' Pattern Maximum Width Setting Register (D0PMAX)
Address: After reset: R/W:
F064DH 00H R/W
Symbol
7
6
5
4
3
2
1
0
D0PMAX
D0PMAX[7:0]
18.2.13 Data '1' pattern minimum width setting register (D1PMIN)
The D1PMIN register is used to set the minimum width of the data '1' pattern. The setting range is from 00H to FFH. When the interval between the edges of an external input signal measured using the base timer is between D1PMIN and D1PMAX, the pattern of the signal is detected as a data '1' pattern. Rewriting the D1PMIN register is prohibited when the REMC is in operation (when REMCON1.EN = 1). The D1PMIN register can be set by an 8-bit memory manipulation instruction. The value of the D1PMIN register is 00H following a reset.
Figure 18 - 14 Format of Data '1' Pattern Minimum Width Setting Register (D1PMIN)
Address: After reset: R/W:
F064EH 00H R/W
Symbol
7
6
5
4
3
2
1
0
D1PMIN
D1PMIN[7:0]
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18.2.14 Data '1' pattern maximum width setting register (D1PMAX)
The D1PMAX register is used to set the maximum width of the data '1' pattern. The setting range is from 00H to FFH. When the interval between the edges of an external input signal measured using the base timer is between D1PMIN and D1PMAX, the pattern of the signal is detected as a data '1' pattern. Rewriting the D1PMAX register is prohibited when the REMC is in operation (when REMCON1.EN = 1). The D1PMAX register can be set by an 8-bit memory manipulation instruction. The value of the D1PMAX register is 00H following a reset.
Figure 18 - 15 Format of Data '1' Pattern Maximum Width Setting Register (D1PMAX)
Address: After reset: R/W:
F064FH 00H R/W
Symbol
7
6
5
4
3
2
1
0
D1PMAX
D1PMAX[7:0]
18.2.15 Special data pattern minimum width setting register (SDPMIN)
The SDPMIN register is used to set the minimum width of the special data pattern. The setting range is from 000H to 7FFH. When the interval between the edges of an external input signal measured using the base timer is between SDPMIN and SDPMAX, the pattern of the signal is detected as a special data pattern. Rewriting the SDPMIN register is prohibited when the REMC is in operation (when REMCON1.EN = 1). The SDPMIN register can be set by a 16-bit memory manipulation instruction. The value of the SDPMIN register is 0000H following a reset.
Figure 18 - 16 Format of Special Data Pattern Minimum Width Setting Register (SDPMIN)
Address: After reset: R/W:
F0650H, F0651H 0000H R/W
Symbol
15
14
13
12
11
10
9
8
SDPMIN
0
0
0
0
0
SDPMIN[10:8]
7
6
5
4
3
2
1
0
SDPMIN[7:0]
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18.2.16 Special data pattern maximum width setting register (SDPMAX)
The SDPMAX register is used to set the maximum width of the special data pattern. The setting range is from 000H to 7FFH. When the interval between the edges of an external input signal measured using the base timer is between SDPMIN and SDPMAX, the pattern of the signal is detected as a special data pattern. Rewriting the SDPMAX register is prohibited when the REMC is in operation (when REMCON1.EN = 1). The SDPMAX register can be set by a 16-bit memory manipulation instruction. The value of the SDPMAX register is 0000H following a reset.
Figure 18 - 17 Format of Special Data Pattern Maximum Width Setting Register (SDPMAX)
Address: After reset: R/W:
F0652H, F0653H 0000H R/W
Symbol
15
14
13
12
11
10
9
8
SDPMAX
0
0
0
0
0
SDPMAX[10:8]
7
6
5
4
3
2
1
0
SDPMAX[7:0]
18.2.17 Pattern end setting register (REMPE)
The REMPE register is used to set the width of the pattern end. The setting range is from 000H to 7FFH. The timing when the REMSTS.DRFLG flag changes from 1 to 0 can be set. Rewriting the REMPE register is prohibited when the REMC is in operation (when REMCON1.EN = 1). The REMPE register can be set by a 16-bit memory manipulation instruction. The value of the REMPE register is 0000H following a reset.
Figure 18 - 18 Format of Pattern End Setting Register (REMPE)
Address: After reset: R/W:
F0654H, F0655H 0000H R/W
Symbol
15
14
13
12
11
10
9
8
REMPE
0
0
0
0
0
PE[10:8]
7
6
5
4
3
2
1
0
PE[7:0]
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18.2.18 Receiver standby control register (REMSTC)
The REMSTC register is used to control the startup of reception (SNOOZE mode) upon receiving the remote control signal in the STOP mode and select the sampling clock of the digital filter. Rewriting the REMSTC register is prohibited when the REMC is in operation (when REMCON1.EN = 1). The REMSTC register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of the REMSTC register is 00H following a reset.
Figure 18 - 19 Format of Receiver Standby Control Register (REMSTC)
Address: After reset: R/W:
F0656H 00H R/W
Symbol
7
6
5
4
3
2
1
<0>
REMSTC
0
0
0
0
0
0
DNFSLNote SNZONNote
DNFSLNote
Digital Filter Clock Selection
0
REMC operating clock is selected as a sampling clock
1
fSXP is selected as a sampling clock
This bit is used to select the sampling clock of the digital filter. Set this bit to 1 when setting the SNZON bit to
1 (transition from STOP mode to SNOOZE mode is enabled).
SNZON
Note
SNOOZE Mode Operation Control
0
Disables transition from STOP mode to SNOOZE mode.
1
Enables transition from STOP mode to SNOOZE mode.
· When the input level of the RIN0 pin is changed in the STOP mode, the STOP mode is exited, and remote control reception is performed without operating the CPU (the SNOOZE mode).
· Use the SNOOZE mode only when the timer interrupt (INTTM06) is selected as the REMC operating clock. In this case, select a clock that can operate in SNOOZE mode as the count clock for channel 6 of timer array unit 0.
· When using SNOOZE mode, set channel 6 of timer array unit 0 to interval timer mode and enable the count operation before shifting to STOP mode.
· Even when SNOOZE mode is to be used, set the SNZON bit to 0 after return from SNOOZE mode. Set the SNZON bit to 1 when the transition to STOP mode is to be repeated.
· When setting the SNZON bit to 1, set the REMCON0.FIL bit to 1 (enables the digital filter) and set the DNFSL bit to 1 (fSXP is selected as a sampling clock).
· After returning from STOP mode due to a compare match interrupt or header pattern match interrupt, set the SNZON bit to 0.
Note
Set this bit to 1 when the REMCON1.EN bit and the REMCON0.ENFLG flag are both 0 (REMC is stopped).
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18.2.19 Receive bit count register (REMRBIT)
The REMRBIT register indicates the number of received bits. All the bits of the REMRBIT register are initialized when the setting of the REMCON1.EN bit is 0. The REMRBIT register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of the REMRBIT register is 00H following a reset.
Figure 18 - 20 Format of Receive Bit Count Register (REMRBIT)
Address: After reset: R/W:
F0657H 00H R/WNotes 1, 2
Symbol
7
6
5
4
3
2
1
<0>
REMRBIT 0Note 2
RBIT[6:1]Note 1
RBIT[0]
RBIT[6:0]
Receive Bit Count Check
These bits indicate the bit position of the buffer to be stored by counting the detected data `0' pattern or data `1' pattern. · When the receive bit count exceeds 64 (40H), the value returns to 1. · The header pattern and special data pattern are not counted. · If an error is detected while the REMCON0.EC bit is 1, the value is not incremented even when the data '0'
pattern or data '1' pattern is detected. · The REMRBIT register becomes 0 when the REMSTS.DRFLG flag changes from 0 to 1. · The REMRBIT register becomes 0 when the REMSTS.HDFLG flag changes from 0 to 1. When 0 is written to the REMRBIT.RBIT[0] bit, the value of the REMRBIT register becomes 00H after one to two cycles of the operating clock.
Note 1. Note 2.
Bits 6 to 1 are read-only. Bit 7 is read as undefined. The write value should be 0.
Caution If updating and reading data overlap, an undefined value may be read. For details on reading this register, see 18.4.5 Reading Registers.
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18.2.20 Receive data 0 register (REMDAT0)
The REMDAT0 register holds received data. All the bits of the REMDAT0 register are initialized when the setting of the REMCON1.EN bit is 0. The REMDAT0 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of the REMDAT0 register is 00H following a reset.
Figure 18 - 21 Format of Receive Data 0 Register (REMDAT0)
Address: After reset: R/W:
F0658H 00H R/WNote
Symbol
7
6
5
4
3
2
1
<0>
REMDAT0
DAT0[7:1]Note
DAT0[0]
DAT0[7:0]
Receive Data 0 Store
When data '0' pattern or data '1' pattern is detected, the result is sequentially stored bit by bit starting from the REMDAT0.DAT0[0] bit as received data. For details on storing received data, see 18.3.8 Receive Data Buffer.
When 0 is written to the REMDAT0.DAT0[0] bit, the value of the REMDAT0 register becomes 00H after one
to two cycles of the operating clock.
Note
Bits 7 to 1 are read-only.
Caution If updating and reading data overlap, an undefined value may be read. For details on reading this register, see 18.4.5 Reading Registers.
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18.2.21 Receive data j register (REMDATj) (j = 1 to 7)
The REMDATj register holds received data. All the bits of the REMDATj register are initialized when the setting of the REMCON1.EN bit is 0. The REMDATj register can be read by an 8-bit memory manipulation instruction. The value of the REMDATj register is 00H following a reset.
Figure 18 - 22 Format of Receive Data j Register (REMDATj)
Address: After reset: R/W:
F0659H to F065FH 00H R
Symbol
7
6
5
4
3
2
1
0
REMDATj
DATj[7:0]
DATj[7:0]
Receive Data j Store
When data '0' pattern or data '1' pattern is detected, the result is sequentially stored bit by bit starting from the REMDATj.DATj[0] bit as received data. For details on storing received data, see 18.3.8 Receive Data Buffer.
Caution If updating and reading data overlap, an undefined value may be read. For details on reading this register, see 18.4.5 Reading Registers.
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CHAPTER 18 REMOTE CONTROL SIGNAL RECEIVER (REMC)
18.2.22 Measurement result register (REMTIM)
The REMTIM register indicates the measurement result of each pattern width. All the bits of the REMTIM register are initialized when the setting of the REMCON1.EN bit is 0. The REMTIM register can be read by a 16-bit memory manipulation instruction. The value of the REMTIM register is 0000H following a reset.
Figure 18 - 23 Format of Measurement Result Register (REMTIM)
Address: After reset: R/W:
F0660H, F0661H 0000H R
Symbol
15
14
13
12
11
10
9
8
REMTIM
0
0
0
0
0
TIM[10:8]
7
6
5
4
3
2
1
0
TIM[7:0]
TIM[10:0]
Measurement Result
The value of the base timer is captured when any of the following patterns is detected. · Header pattern · Data '0' pattern · Data `1' pattern · Special data pattern · Data pattern other than the above (receive error)
Caution If updating and reading data overlap, an undefined value may be read. For details on reading this register, see 18.4.5 Reading Registers.
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18.3
Operation
18.3.1 Overview of REMC Operation
Figure 18 - 24 shows an example of the remote control signal. The signal begins with a header, followed by a sequence of data. This header differs from the subsequent sequence of data in waveform, allowing the header and the data to be distinguished. The sequence of data contains custom code and data code, and 0 or 1 is distinguished depending on the bit length. After a stop bit, there is an interval during which the signal does not change (frame space), thus constituting a frame. The time between the edges of the external input signal is measured using the base timer in the REMC. The patterns of the remote control signal are detected and the data is captured according to the measurement results.
Figure 18 - 24 Example of Remote Control Signal
'1' '0' '0' '1'
Stop bit
Header
Data One frame
Frame space
Next frame header
18.3.2 Initial Setting
Initialize the REMC according to the procedure shown in Figure 18 - 25 to receive the remote control signal. Set the REMCON1.EN bit to 0 if the REMC is operating. Then the REMCON0.ENFLG flag becomes 0 and the REMC stops the operation. Set the format for the remote control signal waveform by the REMCON1.TYP[1:0] bits; select the signal inversion or non-inversion by the REMCON0.INV bit; select the operating clock by the REMCON1.CSRC bit; and set the digital filter by the REMCON0.FIL, REMCON0.FILSEL, and REMSTC.DNFSL bits, while the REMCON0.ENFLG flag is 0. Set the detecting width for each data pattern into the HDPMIN, HDPMAX, D0PMIN, D0PMAX, D1PMIN, D1PMAX, SDPMIN, SDPMAX, and REMPE registers. Make any other settings such as enabling interrupts by the REMINT register and setting of the compare function by the REMCPC and REMCPD registers if required. After all necessary register settings are completed, set the REMCON1.EN bit to 1 to start REMC operation.
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Figure 18 - 25 Example of Flowchart for Initial Settings of REMC
Start
PRR1.REMCRES = 0
[1] Release the REMC from the reset state.
[1]
Enable supplying the clock.
PER1.REMCEN = 1
REMCON1.EN = 0 and REMCON0.ENFLG = 0?
Yes
[2] Stop the REMC if it is operating.
No
[2]
REMCON1.EN = 0
No [3]
REMCON0.ENFLG = 0?
Yes Set the REMCON1.TYP[1:0] bits
[4]
Set the REMCON0.INV bit
[5]
Set the REMCON1.CSRC bit
[6]
Set the REMCON0.FIL, REMCON0.FILSEL,
and REMSTC.DNFSL bits
Set the HDPMIN and HDPMAX registers
Set the D0PMIN and D0PMAX registers
[7]
Set the D1PMIN and D1PMAX registers
Set the SDPMIN and SDPMAX registers
Set the REMPE register
[8]
Set any other registers
End
[3] Select the format for the remote control signal waveform.
[4] Select whether the input signal to be inverted or not.
[5] Select the REMC operating clock. [6] Configure the digital filter. [7] Set the minimum and maximum values for each
data pattern detection width.
[8] Set any other registers if required.
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18.3.3 Pattern Setting
The format for capturing the remote control signal reception waveform can be set by setting the REMCON1.TYP[1:0] bits. Figure 18 - 26 and Figure 18 - 27 show examples of a remote control signal reception waveform captured by setting the REMCON1.TYP[1:0] bits.
When the REMCON1.TYP[1:0] bits are 00B (format A) The measured result is determined from the setting value of the header pattern at the rising edge of the internal input signal. When the header pattern is received, the measured result is determined from the setting values of the data '0', data '1' and special data patterns at the rising edge of the internal input signal.
When the REMCON1.TYP[1:0] bits are 01B (format B) The measured result is determined from the setting value of the header pattern at the falling edge of the internal input signal. When the header pattern is received, the measured result is determined from the setting values of the data '0', data '1' and special data patterns at the falling edge of the internal input signal. The header pattern is detected once within one frame.
When the REMCON1.TYP[1:0] bits are 10B (format C) The measured result is determined from the setting values of the header, data '0', data '1' and special data patterns at the rising edge of the internal input signal.
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Figure 18 - 26 Example of Remote Control Signal Reception Waveform Captured by Setting REMCON1.TYP[1:0] Bits (REMCON0.INV = 0)
TYP[1:0] = 00B
Header
Data
Header
Data
Header
Data Special Data
TYP[1:0] = 01B
Header
Data
TYP[1:0] = 10B
Data
Header
Data Special Data
Header
Data
Data
Header
Data
Header
Data
Header
Data
Special
Header
Data
Data
TYP[1:0] TYP[1:0] = 00B
Header Pattern
Data '0' Pattern
Data '1' Pattern
TYP[1:0] = 01B
TYP[1:0] = 10B
TYP[1:0]: Bits in the REMCON1 register Measurement starts Pattern determined
When TYP[1:0] = 01B, the number of detecting the header pattern within the receive frame is one. The above diagram applies when the REMCON0.INV bit is 0.
Special Data Pattern
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Figure 18 - 27 Example of Remote Control Signal Reception Waveform Captured by Setting REMCON1.TYP[1:0] Bits (REMCON0.INV = 1)
TYP[1:0] = 00B
Header
Data
Header
Data
Header
Data Special Data
TYP[1:0] = 01B
Header
Data
TYP[1:0] = 10B
Data
Header
Data Special Data
Header
Data
Data
Header
Data
Header
Data
Header
Data
Special
Header
Data
Header
TYP[1:0] TYP[1:0] = 00B
Header Pattern
Data '0' Pattern
Data '1' Pattern
TYP[1:0] = 01B
TYP[1:0] = 10B
TYP[1:0]: Bits in the REMCON1 register Measurement starts Pattern determined
When TYP[1:0] = 01B, the number of detecting the header pattern within the receive frame is one. The above diagram applies when the REMCON0.INV bit is 1.
Special Data Pattern
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18.3.4 Operating Clock
The REMC can use either of the following clock signals as its operating clock: the low-speed peripheral clock (fSXP) and timer interrupt (INTTM06). When transition from the STOP mode to the SNOOZE mode is enabled, select the low-speed peripheral clock (fSXP) as the clock of the digital filter. When selecting the timer interrupt (INTTM06) as the REMC operating clock, see CHAPTER 7 TIMER ARRAY UNIT (TAU) to confirm the operating clock setting for channel 6 of timer array unit 0. The following describes how to supply these clock signals.
18.3.4.1 When using fSXP as the REMC operating clock
This section describes the procedure for using the low-speed peripheral clock (fSXP) as the REMC operating clock. (a) When using the low-speed on-chip oscillator clock (fIL) as the low-speed peripheral clock (fSXP)
The low-speed on-chip oscillator clock (fIL) is supplied as the REMC operating clock by setting bit 4 (WUTMMCK0) of the subsystem clock supply mode control register (OSMC) to 1 and setting the REMCON1.CSRC bit to 0. For details, see 6.1 Functions of Clock Generator. (b) When using the subsystem clock (fSX) as the low-speed peripheral clock (fSXP) The subsystem clock oscillator starts to oscillate by setting bits 7 and 4 (RTCLPC and WUTMMCK0) of the subsystem clock supply mode control register (OSMC) to 0, setting the subsystem clock operation mode by bits 5 and 4 (EXCLKS and OSCSELS) of the clock operation mode control register (CMC), and setting bit 6 (XTSTOP) of the clock operation status control register (CSC) to 0. Then, after the oscillation stabilization time for the subsystem clock is secured by using the timer function or another function, by using software, the subsystem clock (fSX) is supplied as the REMC operating clock by setting the REMCON1.CSRC bit to 0. For the subsystem clock setting, see 6.6.3 Example of setting the XT1 oscillator clock.
18.3.4.2 When using INTTM06 as the REMC operating clock
The timer interrupt (INTTM06) is supplied as the REMC operating clock by setting the RECOM1.CSRC bit to 1. Operate channel 6 of timer array unit 0 in the interval timer mode. For details about the operation of timer array unit 0, see CHAPTER 7 TIMER ARRAY UNIT (TAU).
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18.3.5 RIN0 Input
The options below can be selected in RIN0 input. · Input polarity · Digital filter Figure 18 - 28 shows the configuration of RIN0 internal input signal generation.
Figure 18 - 28 RIN0 Internal Input Signal Generation Configuration
RIN0 pin fSXP
Operating clock
REMCON0.INV
0 1
1 0
REMSTC.DNFSL
REMCON0.FILSEL
Digital filtering for matching 3 or 2 times
REMCON0.FIL
0
1
Synchronizer
Base timer reset signal
REMCON0.INFLG (internal input signal)
The input polarity of the RIN0 pin can be inverted. Whether to invert or not can be selected by the REMCON0.INV bit. When the REMCON0.FIL bit is 1 (digital filter enabled), if the signal input to the RIN0 pin holds the same level for k sequential cycles (k = 3 or 2; value selected by the REMCON0.FILSEL bit), that level is transferred to the internal circuit. This enables noise to be eliminated from k cycles of the sampling clock. The sampling clock of the digital filter is selectable from the REMC operating clock and fSXP by setting the REMSTC.DNFSL bit. When setting the REMSTC.SNZON bit to 1 (transition from STOP mode to SNOOZE mode is enabled), set the REMCON0.FIL bit to 1 (the digital filter is enabled) and the REMSTC.DNFSL bit to 1 (fSXP is selected as a sampling clock). Input to the RIN0 pin is transferred as the REMCON0.INFLG flag (input signal flag) and the base timer reset signal to the internal circuit in synchronization with the operating clock. The base timer reset signal is used to initialize the internal base timer to the pattern detection corresponding to the REMCON1.TYP[1:0] setting. There is a delay caused by internal processing after the input to the RIN0 pin is changed and before these signals are generated. Figure 18 - 29 shows digital filtering for RIN0 input.
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Figure 18 - 29 Digital Filtering for RIN0 Input
Sampling clock
RIN0 pin input Digital filter output
Operating clock
Matches three times*1 Internal processing (1 cycle)
Matches three times*1 Internal processing
Internal processing (3 to 4 cycles)
Eliminated by digital filter
Base timer reset signal
INFLG flag
Synchronization (1 to 2 cycles of operating clock)
Delay of 3 to 4 cycles of sampling clock + 1 to 2 cycles of operating clock*2
Synchronization
Note 1. Note 2.
The above applies when the REMCON0.FIL bit is 1 (digital filter enabled) and the REMCON0.FILSEL bit is 0 (matches three times). When the FILSEL bit is 1 (matches twice), the signal is output earlier by one cycle of sampling clock than that in this figure. When the FIL bit is 0 (digital filter disabled), a delay becomes one to two cycles of the operating clock for synchronization.
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18.3.6 Pattern Detection
The REMC has a function that detects the following patterns. · Header pattern · Data '0' pattern · Data `1' pattern · Special data pattern Using the base timer included in the REMC, the time between the edges of the external input signal is measured to determine which pattern matches the measurement result. This enables detection of the remote control signal and capturing the data. The width for determining each pattern can be set to any value using each pattern setting register. Figure 18 - 30 shows the waveform of REMC operation.
Figure 18 - 30 Waveform of REMC Operation
Internal input signal
7FFH
REMPE setting
Header
HDPMAX setting
HDPMIN setting
Base timer count operation
D1PMAX setting
D1PMIN setting D0PMAX setting
D0PMIN setting
001H
Header detection area
Data '1' detection area Data '0' detection area
Data '1' Data '0' Data '1' Data
DRFLG
REMSTS operation
HDFLG D1FLG
D0FLG
Data reception starts Header detection Data '1' detection Data '0' detection
Stop bit Frame space
Next frame
Count stops
Pattern end detection
Data reception starts
Cleared when next frame is detected
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18.3.6.1 Header pattern detection
The header pattern can be detected by setting the minimum width of the header pattern in the HDPMIN register and the maximum width in the HDPMAX register. The minimum and maximum widths of the header pattern must be "1 < HDPMIN register value HDPMAX register value".
Minimum width (maximum width) of header pattern
Setting value n =
Operating clock cycle time
When not using the header pattern, set the HDPMIN and HDPMAX registers to 000H. Make sure that the setting value of the header pattern is different from the setting values of data '0', data '1', and special data patterns, and the setting ranges are not overlapped.
When the REMCON1.TYP[1:0] bits are 00B or 01B, if the data '0', data '1', or special data pattern is detected before the header pattern is detected, the following occur: · The REMSTS.REFLG flag becomes 1 (an error has occurred). · The REMSTS.D0FLG, REMSTS.D1FLG, and REMSTS.SDFLG flags remain unchanged. · The REMDAT0 to REMDAT7 registers remain unchanged.
When the REMCON1.TYP[1:0] bits are 01B, the number of detecting the header pattern is one while the DRFLG flag is 1.
18.3.6.2 Data `0' pattern detection
The data `0' pattern can be detected by setting the minimum width of the data `0' pattern in the D0PMIN register and the maximum width in the D0PMAX register. The minimum and maximum widths of the data `0' pattern must be "1 < D0PMIN register value D0PMAX register value".
Minimum width (maximum width) of data "0" pattern
Setting value n =
Operating clock cycle time
When not using the data '0' pattern, set the D0PMIN and D0PMAX registers to 00H. Make sure that the setting value of the data '0' pattern is different from the setting values of the header, data '1', and special data patterns, and the setting ranges are not overlapped.
When the REMCON1.TYP[1:0] bits are 00B or 01B, if the data '0' pattern or data '1' pattern is detected before the header pattern is detected, the following occur: · The REMSTS.REFLG flag becomes 1 (an error has occurred). · The REMSTS.D0FLG, REMSTS.D1FLG, and REMSTS.SDFLG flags remain unchanged. · The REMDAT0 to REMDAT7 registers remain unchanged.
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18.3.6.3 Data `1' pattern detection
The data `1' pattern can be detected by setting the minimum width of the data `1' pattern in the D1PMIN register and the maximum width in the D1PMAX register. The minimum and maximum widths of the data `1' pattern must be "1 < D1PMIN register value D1PMAX register value".
Minimum width (maximum width) of data "1" pattern
Setting value n =
Operating clock cycle time
When not using the data '1' pattern, set the D1PMIN and D1PMAX registers to 00H. Make sure that the setting value of the data '1' pattern is different from the setting values of the header, data '0', and special data patterns, and the setting ranges are not overlapped.
When the REMCON1.TYP[1:0] bits are 00B or 01B, if the data '0' pattern or data '1' pattern is detected before the header pattern is detected, the following occur: · The REMSTS.REFLG flag becomes 1 (an error has occurred). · The REMSTS.D0FLG, REMSTS.D1FLG, and REMSTS.SDFLG flags remain unchanged. · The REMDAT0 to REMDAT7 registers remain unchanged.
18.3.6.4 Special data pattern detection
The special data pattern can be detected by setting the minimum width of the special data pattern in the SDPMIN register and the maximum width in the SDPMAX register. The minimum and maximum widths of the special data pattern must be "1 < SDPMIN register value SDPMAX register value".
Minimum width (maximum width) of special data pattern
Setting value n =
Operating clock cycle time
When not using the special data pattern, set the SDPMIN and SDPMAX registers to 000H. Make sure that the setting value of the special data pattern is different from the setting values of the header, data '0', and data '1' patterns, and the setting ranges are not overlapped.
When the REMCON1.TYP[1:0] bits are 00B or 01B, if the special data pattern is detected before the header pattern is detected, the following occur: · The REMSTS.REFLG flag becomes 1 (an error has occurred). · The REMSTS.SDFLG flag remains unchanged. · The REMDAT0 to REMDAT7 registers remain unchanged.
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18.3.6.5 Examples of setting pattern setting registers
For the header, data '0', data '1', and special data pattern setting registers, make sure that the minimum to maximum values of each pattern are different, and the setting ranges do not overlap as shown in Figure 18 - 31.
Figure 18 - 31 Examples of Setting Pattern Setting Registers
Header pattern setting
HDPMIN setting value HDPMAX setting value
Special data pattern setting
SDPMIN setting value SDPMAX setting value
Data '1' pattern setting Data '0' pattern setting
D1PMIN setting value D1PMAX setting value D0PMIN setting value D0PMAX setting value
Data '0' detection range
Data '1' detection range
Special data detection range
Header detection range
18.3.6.6 Updating status flags upon pattern detection
The detected patterns can be confirmed by reading the following flags: header pattern match flag (REMSTS.HDFLG), data '0' pattern match flag (REMSTS.D0FLG), data '1' pattern match flag (REMSTS.D1FLG), and special data pattern match flag (REMSTS.SDFLG). These flags are cleared when a different pattern is detected. If a pattern other than the above patterns is detected, it is detected as an error pattern. This can be confirmed by reading the receive error flag (REMSTS.REFLG). This flag is cleared when the next frame is received. Figure 18 - 32 shows an example of pattern detection and flag operation.
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Figure 18 - 32 Example of Flag Operation
Normal reception Internal input signal
DRFLG HDFLG D0FLG D1FLG Error reception Internal input signal DRFLG HDFLG D0FLG D1FLG REFLG
Header Data '0' Data '1' Data '0' Data '1' Data '0'
Next frame starts
Pattern end detected
Data reception starts
Header detected
Data '0' detected
Data '1' detected
Error Header Data '0' Data '1' data Data '1' Data '0'
Next frame starts
Pattern end detected
Data reception starts
Header detected
Data '0' detected
Data '1' detected
Error detected
Becomes 0 when next frame is received
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18.3.7 Pattern End
The timing when the REMSTS.DRFLG flag becomes 0 can be set.
When setting the REMPE register, be sure to set that the REMPE value > HDPMAX, D0PMAX, D1PMAX, or SDPMAX value.
When the REMPE value HDPMAX, D0PMAX, D1PMAX, or SDPMAX value, the value specified in the REMPE register is not used to set the timing when the REMSTS.DRFLG flag becomes 0. In this case, data reception is completed according to the largest value from among the setting values of the HDPMAX, D0PMAX, D1PMAX, and SDPMAX registers. Figure 18 - 33 shows operation of the data reception complete flag for each pattern end setting.
Figure 18 - 33 Operation of Data Reception Complete Flag for Each Pattern End Setting
When the REMPE setting value is smaller than the D0PMAX or D1PMAX setting value
Input waveform
Data '0' Data '1'
Data '1'
DRFLG
When the D1PMAX register value is greater than the REMPE register value, the REMPE setting value is ignored and the REMSTS.DRFLG flag is changed from 1 to 0 according to the D1PMAX register setting.
When the REMPE setting value is greater than the D0PMAX and D1PMAX setting value
Input waveform
Data '0' Data '1'
Data '1'
DRFLG
When the REMCON1.TYP[1:0] bits are 00B and the REMCON0.INV bit is 0
The REMSTS.DRFLG flag changes from 1 to 0 by setting the REMPE register.
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18.3.8 Receive Data Buffer
The receive data j register (REMDATj) (j = 0 to 7) is an 8-byte (64-bit) buffer for storing received data. When data '0' pattern or data '1' pattern is detected, the detection result is sequentially stored starting from the REMDAT0.DAT0[0] bit as shown in Figure 18 - 34. The REMRBIT register is counted up at the same time, so the number of the current received bits can be checked by reading the REMRBIT register. See Table 18 - 4 for the relationship between the number of received bits and the location where data is stored. The values of the REMDATj and REMRBIT registers do not change even when the header pattern or special data pattern is received. If the REMDATj or REMRBIT register is read while the data is being updated, the value read may be undefined.
Figure 18 - 34 Operation of Receive Data Buffer
Internal input signal
REMSTS.DRFLG
REMSTS.HDFLG
REMSTS.D0FLG
REMSTS.D1FLG
Header
Data '0'
Data '1'
Data '1'
Data '0'
Data '1'
Data '0'
Data '1'
Data '1'
Data reception starts
Header detection
Data '0' detection
Data '0' detection
Data '0' detection
Data '1' detection Data '1' detection
Data '1' detection
Data '1' detection
DAT0[0] DAT0[1] DAT0[2] DAT0[3] DAT0[4] DAT0[5] DAT0[6]
0 1 1 0 1 0 1
REMRBIT
0
1
2
3
4
5
6
7
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CHAPTER 18 REMOTE CONTROL SIGNAL RECEIVER (REMC)
Table 18 - 4 Relationship between Number of Received Bits and Location Where Data is Stored
Number of Received Bits
Location Where Data is Stored
Register Name
Bit Name
Number of Received Bits
Location Where Data is Stored
Register Name
Bit Name
1
REMDAT0
DAT0[0]
33
REMDAT4
DAT4[0]
2
DAT0[1]
34
DAT4[1]
3
DAT0[2]
35
DAT4[2]
4
DAT0[3]
36
DAT4[3]
5
DAT0[4]
37
DAT4[4]
6
DAT0[5]
38
DAT4[5]
7
DAT0[6]
39
DAT4[6]
8
DAT0[7]
40
DAT4[7]
9
REMDAT1
DAT1[0]
41
REMDAT5
DAT5[0]
10
DAT1[1]
42
DAT5[1]
11
DAT1[2]
43
DAT5[2]
12
DAT1[3]
44
DAT5[3]
13
DAT1[4]
45
DAT5[4]
14
DAT1[5]
46
DAT5[5]
15
DAT1[6]
47
DAT5[6]
16
DAT1[7]
48
DAT5[7]
17
REMDAT2
DAT2[0]
49
REMDAT6
DAT6[0]
18
DAT2[1]
50
DAT6[1]
19
DAT2[2]
51
DAT6[2]
20
DAT2[3]
52
DAT6[3]
21
DAT2[4]
53
DAT6[4]
22
DAT2[5]
54
DAT6[5]
23
DAT2[6]
55
DAT6[6]
24
DAT2[7]
56
DAT6[7]
25
REMDAT3
DAT3[0]
57
REMDAT7
DAT7[0]
26
DAT3[1]
58
DAT7[1]
27
DAT3[2]
59
DAT7[2]
28
DAT3[3]
60
DAT7[3]
29
DAT3[4]
61
DAT7[4]
30
DAT3[5]
62
DAT7[5]
31
DAT3[6]
63
DAT7[6]
32
DAT3[7]
64
DAT7[7]
Note
When the data exceeds 64 bits, the REMDATj register is sequentially overwritten from the first bit.
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CHAPTER 18 REMOTE CONTROL SIGNAL RECEIVER (REMC)
When 0 is written to the REMDAT0.DAT0[0] bit, the values of the REMDAT0 to REMDAT7 registers become 00H after one to two cycles of the operating clock. Figure 18 - 35 shows the REMDATj/REMRBIT register operation when 00H is written to the REMDAT0 register.
Figure 18 - 35 REMDATj/REMRBIT Register Operation (00H is Written to REMDAT0 Register)
Internal input signal REMCON0.ENFLG
REMSTS.DRFLG REMSTS.D0FLG REMSTS.D1FLG
Data '0' Data '1' Data '1' Data '0' Data '1'
Data '1'
Write 0. Data '1'
REMDAT0 REMDAT1
REMRBIT
00H
00H 02H 06H 06H
F6H
00H 01H
00H
01H
00H
Becomes 00H when 0 is written to the DAT0[0] bit in the REMDAT0 register
0
1
2
3
4
8
9
0
1
When 0 is written to the REMRBIT.RBIT[0] bit, the value of the REMRBIT register becomes 00H after one to two cycles of the operating clock. When the REMCON1.TYP[1:0] bits are 00B or 01B, if the header pattern is detected during data reception, the value of the REMRBIT register is initialized to 00H and the received data is sequentially overwritten from the REMDAT0.DAT0[0] bit. Figure 18 - 36 shows operation of header pattern detection during data reception.
Figure 18 - 36 Operation of Header Pattern Detection during Data Reception
Internal input signal REMSTS.DRFLG REMSTS.HDFLG REMSTS.D0FLG REMSTS.D1FLG
REMRBIT REMDAT0
Header
Data '0' Data '1'
Header
Data '1' Data '0'
Data reception starts Header detection Data '0' detection Data '1' detection
0 00H
1 00H
2 02H
Becomes 00H when header is received
0
1
2
Data '1' is overwritten to b0
03H 01H
Data '0' is overwritten to b1
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CHAPTER 18 REMOTE CONTROL SIGNAL RECEIVER (REMC)
When the data exceeds 64 bits, the buffer is sequentially overwritten from the first bit. Figure 18 - 37 shows the REMRBIT register operation when the REMSTS.BFULFLG flag becomes 1.
Figure 18 - 37 REMRBIT Register Operation (REMSTS.BFULFLG Flag = 1)
Internal input signal REMDAT0 REMDAT7 REMRBIT
REMSTS.BFULFLG
Data '0' Data '1' Data '0' Data '1'
Write 0 Data '1' Data '0' Data '1'
Data '1' Data '0' Data '0' Data '1' Data '0'
xxxx_xxxx
xxxx_xxx1 xxxx_xx01 xxxx_x101
xxxx_xxxx xxx0_xxxx xx10_xxxx x010_xxxx
1010_xxxx
60 61 62 63
64
1
2
xxxx_xxxx
xxxx_xxx0 xxxx_xx10 xxxx_x010
xxxx_xxxx x1xx_xxxx
01xx_xxxx
62 63 64
1
2
3
Becomes 0 when 0 is written to the REMSTS.BFULFLG flag. Or becomes 0 at the start of the next frame.
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CHAPTER 18 REMOTE CONTROL SIGNAL RECEIVER (REMC)
18.3.9 Compare Function
The REMC has a function to compare the value of the REMCPD register with the value of the REMDAT1 and REMDAT0 registers. As a result of comparison, it can be detected that the first 1 to 16 bits of the remote control signal are the specific values. Figure 18 - 38 shows the operation timing of the receive buffer and the compare function.
When using the compare function, set registers as shown below: · Select bits to be compared by setting the REMCPC.CPN[3:0] bits
(when the setting value is n, bits n to 0 are compared. n: 0 to 15). · Set the compare data in the REMCPD register.
When the value of the REMRBIT register becomes the bit count specified by the REMCPC.CPN[3:0] bits, if the value of the REMDAT1 and REMDAT0 registers matches the value of the REMCPD register, the REMSTS.CPFLG flag becomes 1 (compare match).
When the value of the REMRBIT register matches the bit count specified by the REMCPC.CPN[3:0] bits during reception of 64 bits or more, even if the value of the REMDAT1 and REMDAT0 registers matches the value of the REMCPD register, the REMSTS.CPFLG flag does not become 1 (compare match).
Figure 18 - 38 Receive Buffer and Compare Function
Internal input signal
Data '0' Data '1'
Data '1' Data '0'
REMCON0.ENFLG
REMDAT0 REMDAT1
0000_0000
0000_0000
Data '0' is stored in b0
0000_0010 0000_0110 0000_0110
Data '1' is Data '1' is stored in b1 stored in
b2
0000_0000
Data '0' is stored in b3
REMRBIT
0
1
2
3
4
REMCPD REMSTS.CPFLG
XXXX_X110 Compare match
The above applies under the following conditions: · The REMCON1.TYP[1:0] bits are 10B · The REMCPC.CPN[3:0] bits are set to 2 (bits 2 to 0 are compared)
Data '1' Data '0'
1111_0110
Data '1' is stored in b7
0000_0001
Data '1' is stored in
b0
8
9
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CHAPTER 18 REMOTE CONTROL SIGNAL RECEIVER (REMC)
18.3.10 Error Pattern Reception
When the error pattern is detected during data reception, subsequent operation differs depending on the setting of the REMCON0.EC bit. Figure 18 - 39 shows operation of the REMDAT0 and REMRBIT registers when the REMCON0.EC bit is set to 0. If an error is detected while the REMCON0.EC bit is 0, the data when the error is detected is not captured, but data is captured when the data `0' pattern or data `1' pattern is detected later. Figure 18 - 40 shows operation of the REMDAT0 and REMRBIT registers when the REMCON0.EC bit is set to 1. If an error is detected while the REMCON0.EC bit is 1, the values of the REMRBIT and REMDAT0 to REMDAT7 registers are not updated even when the data `0' pattern or data `1' pattern is detected later. Once the REMSTS.DRFLG flag is cleared and after data reception is completed, if data reception starts again, the REMSTS.REFLG flag is cleared and data is captured.
Figure 18 - 39 REMDAT0 and REMRBIT Registers Operation upon Error Detection (REMCON0.EC Bit = 0)
REMCON0.EC = 0
Data '0' Data '1'
Error data Data '0' Data '1' Data '0' Data '1' Data '1'
Data '1' Data '0'
Internal input signal
REMCON0.ENFLG
REMSTS.DRFLG
REMSTS.D0FLG
REMSTS.D1FLG
REMSTS.REFLG
REMRBIT
0
1
Does not change when error is detected
2
3
4
5
6
7
0
1
REMDAT0
00H
00H
02H
02H 0AH 0AH 2AH
6AH
6BH
When error is detected, data is not received
Does not become 00H when reception starts Receive data is overwritten
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CHAPTER 18 REMOTE CONTROL SIGNAL RECEIVER (REMC)
Figure 18 - 40 REMDAT0 and REMRBIT Registers Operation upon Error Detection (REMCON0.EC Bit = 1)
REMCON0.EC = 1
Internal input signal REMCON0.ENFLG
REMSTS.DRFLG REMSTS.D0FLG REMSTS.D1FLG REMSTS.REFLG
Data '0' Data '1'
Error data Data '0' Data '1' Data '0' Data '1' Data '1'
Data '1' Data '0'
REMRBIT
0
REMDAT0
00H
1
2
00H
02H
0
1
03H After error is detected, data is not updated
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CHAPTER 18 REMOTE CONTROL SIGNAL RECEIVER (REMC)
18.3.11 Storing Base Timer Value When Pattern is Detected
The measurement result register (REMTIM) holds the base timer value when any of the following patterns is detected. This register allows each pattern width to be measured. Figure 18 - 41 shows an operation example of the measurement function. · Header pattern · Data '0' pattern · Data `1' pattern · Special data pattern · Data pattern other than the above (receive error)
Figure 18 - 41 Operation Example of Measurement Function
Internal input signal
7FFH
REMPE setting
Base timer count operation
HDPMAX setting
575H
HDPMIN setting
D1PMAX setting
67H
D1PMIN setting D0PMAX setting
33H
D0PMIN setting
001H
DRFLG
REMTIM
Data '1' Data '0' Data '1'
Header
Data
Data reception starts
575H 67H 33H
Stop bit Frame space
Next frame
Count stops
Pattern end detection
67H
Data reception starts
Not captured when pattern end is detected
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CHAPTER 18 REMOTE CONTROL SIGNAL RECEIVER (REMC)
18.3.12 Interrupts
The REMC generates the following interrupt requests: compare match, receive error, data reception complete, receive buffer full, header pattern match, data '0' pattern or data '1' pattern match, and special data pattern match interrupts. An interrupt request is output when the generation conditions for these interrupt requests and the generation conditions for the selected interrupt mode are met. There are two interrupt modes, normal interrupt mode (OR condition) and sequential interrupt mode (AND condition), which can be selected by using the REMCON1.INTMD bit. In normal interrupt mode, if any of the interrupt generation conditions of sources whose interrupt enable bit of the REMINT register is set to 1 is met, an interrupt request signal (INTREMC) is generated. In sequential interrupt mode, if all the interrupt generation conditions of the sources (compare match, data reception complete, header pattern match, and special data pattern match) whose interrupt enable bit of the REMINT register is set to 1 are met, an interrupt (INTREMC) is generated. Table 18 - 5 lists the interrupt sources of the REMC. Refer to CHAPTER 21 INTERRUPT FUNCTIONS for details on interrupt control.
Table 18 - 5 REMC Interrupt Sources
Interrupt source
Interrupt Request Generation Condition
Compare match
When the REMSTS.CPFLG flag changes from 0 to 1
Receive error
When the REMSTS.REFLG flag changes from 0 to 1 (When a receive error is detected)
Completion of data reception
When the REMSTS.DRFLG flag changes from 1 to 0
Receive buffer full
When the REMSTS.BFULFLG flag changes from 0 to 1
Header pattern match
When the REMSTS.HDFLG flag changes from 0 to 1 (When the header pattern is detected)
Data `0' pattern or data `1' pattern match
· When the REMSTS.D0FLG flag changes from 0 to 1 (When the data `0' pattern is detected)
· When the REMSTS.D1FLG flag changes from 0 to 1 (When the data `1' pattern is detected)
Special data pattern match When the REMSTS.SDFLG flag changes from 0 to 1 (When the special data pattern is detected)
Interrupt Status Flag
REMSTS.CPFLG REMSTS.REFLG
REMSTS.DRFLG
REMSTS.BFULFLG REMSTS.HDFLG
REMSTS.D0FLG, REMSTS.D1FLG
REMSTS.SDFLG
Interrupt Enable Bit REMINT.CPINT REMINT.REINT REMINT.DRINT
REMINT.BFULINT REMINT.HDINT REMINT.DINT
REMINT.SDINT
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CHAPTER 18 REMOTE CONTROL SIGNAL RECEIVER (REMC)
18.3.13 SNOOZE Mode Function
In the SNOOZE mode, the REMC performs remote control data reception operation when detecting a change in the input level of the RIN0 pin. When the timer interrupt (INTTM06) is selected as the REMC operating clock, normally the REMC reception operation stops in STOP mode. However, using the SNOOZE mode enables remote control data reception without CPU operation upon detection of a change in the input level of the RIN0 pin. The SNOOZE mode can only be used when the timer interrupt (INTTM06) is selected as the REMC operating clock. In this case, select a CPU/peripheral hardware clock that can operate in SNOOZE mode as the count clock for channel 6 of timer array unit 0. When using the REMC in SNOOZE mode, make the following setting before switching to the STOP mode. · Make initial settings of each register immediately before switching to STOP mode. To enable remote control data
reception in SNOOZE mode, set the REMCON0.FIL bit to 1 (enables the digital filter) and set the REMSTC.DNFSL bit to 1 (fSXP is selected as a sampling clock). · After the initial settings have been completed, set the REMSTC.SNZON bit to 1, and then set the REMCON1.EN bit to 1. · The CPU shifts to the SNOOZE mode on detecting the valid edge of the RIN0 pin input following a transition to the STOP mode. When the timer interrupt (IMTTM06) is supplied as the REMC operating clock, the REMC starts reception. · After returning to normal operation mode due to generation of an interrupt source specified in the REMINT register such as a compare match interrupt and header pattern match interrupt, set the SNZON bit to 0.
Caution
The SNOOZE mode can only be specified when the high-speed on-chip oscillator clock (fIH) or medium-speed on-chip oscillator clock (fIM) is selected for the count clock for channel 6 of timer array unit 0.
Remark
When the low-speed peripheral clock (fSXP) is selected for the operating clock, remote control data reception operation is available even in STOP mode. The current consumption in STOP mode is large. Therefore, select a mode in accordance with your system.
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CHAPTER 18 REMOTE CONTROL SIGNAL RECEIVER (REMC)
Table 18 - 6 shows the relationship between the conditions for returning from SNOOZE mode to normal operation mode and interrupt modes.
Table 18 - 6 Interrupt Modes and Transition from SNOOZE Mode
Normal interrupt mode
Sequential interrupt mode
Selectable interrupt sources
Header pattern match Compare match Completion of data reception Special data pattern match Data '0' pattern or data '1' pattern match Receive buffer full Receive error
Header pattern match Compare match Special data pattern match Completion of data reception Data '0' pattern or data '1' pattern match Receive buffer full Receive error
SNOOZE Normal operation mode returning conditions
· Any of the following interrupts that are enabled in REMINT is generated. Header pattern match Compare match Special data pattern match Completion of data reception Data '0' pattern or data '1' pattern match Receive buffer full Receive error
Either of the following conditions:
· Among the following interrupt sources, all of those enabled in REMINT are generated. Header pattern match Compare match Special data pattern match Completion of data reception
· Any of the following interrupts that are enabled in REMINT is generated. Data '0' pattern or data '1' pattern match Receive buffer full Receive error
SNOOZE STOP transition conditions
Data reception is completed while data reception complete interrupt is disabled, and none of the enabled interrupts are generated.
Data reception is completed while data reception complete interrupt is disabled, and not all the enabled interrupts are generated.
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CHAPTER 18 REMOTE CONTROL SIGNAL RECEIVER (REMC)
Figure 18 - 42 SNOOZE Mode Continued Operation in Response to a Compare Mismatch
Reference: Normal STOP Mode transition operation mode mode
REMCON0.ENFLG
SNOOZE mode
REMSTC.SNZON
Header Data '0' Data '1' Data '1' Data '0'
RIN0 input
Clock request signal The oscillator stops
Operating clock
Clock request signal The oscillator restarts
REMSTS.CPFLG REMINT.DRINT
Compare mismatch
REMC interrupt signal
No REMC interrupt is generated
STOP mode
Pattern end detection Clock request signal is negated The oscillator stops
Figure 18 - 43 Returning from SNOOZE Mode in Response to a Compare Match
Reference: Normal STOP Mode transition operation mode mode
REMCON0.ENFLG
SNOOZE mode
Normal operation mode
Returns from the SNOOZE mode in response to an REMC interrupt
REMSTC.SNZON
Cleared by software after return Header Data '0' Data '1' Data '1' Data '0'
RIN0 input
Clock request signal The oscillator stops
Operating clock
Clock request signal The oscillator restarts
REMSTS.CPFLG REMINT.DRINT
Pattern end detection Clock request signal is negated
Compare match Set by software after return
REMC interrupt signal
An REMC interrupt is generated
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CHAPTER 18 REMOTE CONTROL SIGNAL RECEIVER (REMC)
Figure 18 - 44 Example of Flowchart for Setting up SNOOZE Mode
Start of setup
Normal operation
REMCON1.EN = 0 and REMCON0.ENFLG = 0?
Yes Initial settings of REMC
REMCON1.CSRC = 1
REMCON0.FIL = 1 REMSTC register DNFSL = 1, SNZON = 1 REMINT register setting Initial setting of channel 6 of timer array unit 0
TMMK06 = 1
TS0.TS06 = 1
REMCON1.EN = 1
REMCIF = 0
REMCMK = 0
EI instruction execution
STOP instruction execution
No REMCON1.EN = 0
Disable the remote control reception operation. Make initial settings such as the format of the remote control reception waveform and data pattern detection widths.
Set INTTM06 as the operating clock.
Enable the digital filter.
Set fSXP as the clock of the digital filter. Enable the SNOOZE mode operation.
Specify the interrupt to be used to return from SNOOZE mode to normal operation mode. Set the timer channel to interval timer mode and select a clock that can operate in SNOOZE mode as the operating clock. For details, see CHAPTER 7 TIMER ARRAY UNIT. Mask interrupts in channel 6 of timer array unit 0 to prevent the CPU from being released from SNOOZE mode due to an INTTM06 interrupt.
Enable the operation of channel 6 of timer array unit 0.
Enable the remote control reception operation.
Clear the INTREMC interrupt flag.
Clears the mask of the INTREMC interrupts.
STOP mode
SNOOZE mode
No
Detection of the valid
edge of the RIN0 pin
Yes
The CPU shifts to the SNOOZE mode on detecting the valid edge of the RIN0 pin. The clock is supplied to channel 6 of the timer array unit 0, and INTTM06 is generated. The REMC uses INTTM06 as the operating clock and performs reception operation.
The interrupt enabled in REMINT is generated
Yes The mode returns to normal operation mode when the specified interrupt is generated.
No Completion of reception
The mode shifts to STOP mode when reception is completed while the specified interrupt is not generated.
Normal operation
REMSTC.SNZON = 0 Normal operation
Disable the SNOOZE mode operation.
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CHAPTER 18 REMOTE CONTROL SIGNAL RECEIVER (REMC)
18.4
Points for Caution when the Remote Control Signal Receiver is to be Used
18.4.1 Register Access when Starting Operation of the Remote Control Signal Receiver
The REMCON1.EN bit controls starting/stopping of operation of the remote control signal receiver. The REMCON0.ENFLG flag indicates that the operation is enabled or disabled. After the REMCON1.EN bit is set to 1 (operation enabled), it takes up to zero to one cycle of the operating clock before the REMC circuit starts operating and the REMCON0.ENFLG flag becomes 1. During this period, do not access the REMC related registers (listed in 18.2.1 to 18.2.22) except for the REMCON0.ENFLG flag.
18.4.2 Timing of Changing the Register Values
Change the following registers only when the REMCON1.EN bit and REMCON0.ENFLG flag are both 0 (REMC is stopped) · REMCON0 register · REMCON1 register (except for bits 0 to 2) · REMINT register (except for bits 2 and 5) · REMCPC register · REMCPD register · Pattern width setting registers for header, data '0', data '1', and special data patterns · Pattern end setting register · REMSTC register
When rewriting the REMCON1.TYP[1:0] bits while the REMCON1.EN bit or REMCON0.ENFLG flag is 1 (REMC is operating), change the values of these bits one bit at a time. If the REMCON1.TYP[1:0] bits are rewritten when the REMCON0.INFLG flag changes, the signal captured into the remote control signal receiver may be undefined. After 0 is written to bit 0 in the REMDAT0 or REMRBIT register or the REMSTS.BFULFLG flag, do not write 0 to the same bit again for two cycles of the operating clock. If 0 is written when the REMCON0.INFLG flag changes, the values of the REMDATj and REMRBIT registers and the REMSTS.BFULFLG flag may be undefined.
18.4.3 RIN0 Input Control
If the REMCON0.FILSEL, FIL, or INV bit is rewritten, the signal captured into the remote control signal receiver is undefined for three cycles of the digital filter sampling clock.
18.4.4 Changing the Operating Clock
When the REMCON1.CSRC bit is rewritten, set the following registers again: REMCON0, REMCON1, REMINT, REMCPC, REMCPD, REMPE, and header, data '0', data '1', and special data pattern width setting registers.
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CHAPTER 18 REMOTE CONTROL SIGNAL RECEIVER (REMC)
18.4.5 Reading Registers
When the following registers are read while data changes, an undefined value may be read. Flags in the REMCON0 and REMSTS registers (except for the REMSTS.DRFLG flag) and registers REMTIM, REMDAT0 to REMDAT7, and REMRBIT
Follow the procedures below to avoid reading an undefined value. · Using an interrupt
Set the REMINT.DRINT bit to 1 (data reception complete interrupt enabled) and read the registers within the REMC interrupt routine. · Polling by a program 1 Set the REMINT.DRINT bit to 1 (data reception complete interrupt enabled) and poll the REMCIF flag by a program. Read the registers when the flag becomes 1 (interrupt request generated). · Polling by a program 2 (1) Poll the REMSTS.DRFLG flag. (2) When the REMSTS.DRFLG flag becomes 1, poll this flag until it becomes 0. (3) Read the necessary content of the registers when the REMSTS.DRFLG flag becomes 0.
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
The term "8 higher-order bits of the address" in this chapter indicates bits 15 to 8 of 20-bit address as shown below. 20-bit address
4 highest-order bits 8 higher-order bits
8 lower-order bits 4 lower-order bits
Unless otherwise specified, the 4 highest-order address bits all become 1 (values are of the form FxxxxH).
19.1
Functions of DTC
The data transfer controller (DTC) transfers data between memories without using the CPU. The DTC is activated by a peripheral function interrupt and transfers data. The DTC and CPU use the same bus, and the DTC takes priority over the CPU in using the bus. Table 19 - 1 lists the DTC Specifications.
Table 19 - 1 DTC Specifications (1/2)
Item
Specification
Activation sources
30 sources (30- and 32-pin products)/32 sources (36-pin products)/33 sources (40-pin products)/35 sources (44-pin products)/36 sources (48- and 52-pin products)/37 sources (64-pin products)/39 sources (80-, 100-, and 128-pin products)
Allocatable control data
24 sets
Address space available for use with DTC transfer
Address space Source
64 Kbytes (F0000H to FFFFFH), excluding general-purpose registers
Special function registers (SFRs), RAM area (excluding general-purpose registersNote 1), mirror areaNote 2, data flash memory areaNote 2, extended special function registers (2nd SFRs)
Destination
Special function registers (SFRs), RAM area (excluding general-purpose registers), extended special function registers (2nd SFRs)
Maximum number of transfers
Normal mode Repeat mode
256 times 255 times
Maximum size of block to be transferred
Normal mode (8-bit transfer) 256 bytes Normal mode (16-bit transfer) 512 bytes
Repeat mode
255 bytes
Unit of transfers
8 bits/16 bits
Transfer mode
Normal mode
Transfers end on completion of the transfer causing the DTCCTj register value to change from 1 to 0.
Repeat mode
On completion of the transfer causing the DTCCTj register value to change from 1 to 0, the repeat area address is initialized and the DTRLDj register value is reloaded to the DTCCTj register to continue transfers.
Address control
Normal mode
Fixed or incremented
Repeat mode
Addresses of the area not selected as the repeat area are fixed or incremented.
Priority of activation sources
Refer to Table 19 - 3 DTC Activation Sources and Vector Addresses.
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
Table 19 - 1 DTC Specifications (2/2)
Item
Specification
Interrupt request Normal mode
When the data transfer causing the DTCCTj register value to change from 1 to 0 is performed, the activation source interrupt request is generated for the CPU, and interrupt handling is performed on completion of the data transfer.
Repeat mode
When the data transfer causing the DTCCTj register value to change from 1 to 0 is performed while the RPTINT bit in the DTCCRj register is 1 (interrupt generation enabled), the activation source interrupt request is generated for the CPU, and interrupt handling is performed on completion of the data transfer.
Transfer start
When bits DTCENi0 to DTCENi7 in the DTCENi registers are 1 (activation enabled), data transfer is started each time the corresponding DTC activation sources are generated.
Transfer stop
Normal mode
When bits DTCENi0 to DTCENi7 are set to 0 (activation disabled). When the data transfer causing the DTCCTj register value to change from 1 to 0 is completed.
Note 1. Note 2.
Repeat mode
When bits DTCENi0 to DTCENi7 are set to 0 (activation disabled). When the data transfer causing the DTCCTj register value to change from 1 to 0 is completed while the RPTINT bit is 1 (interrupt generation enabled).
If the internal RAM is placed in standby mode or shutdown mode (RAMSDMD = 1) by the memory power reduction control register (PSMCR), the internal RAM cannot be set as a DTC transfer source or destination. In the HALT mode or SNOOZE mode, these areas cannot be set as the sources for DTC transfer since the flash memory is stopped. If the internal RAM is placed in standby mode or shutdown mode (RAMSDMD = 1) by the memory power reduction control register (PSMCR), the internal RAM cannot be set as a DTC transfer source or destination.
Remark i = 0 to 4, j = 0 to 23
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
19.2
Configuration of DTC
Figure 19 - 1 shows the DTC Block Diagram.
Figure 19 - 1 DTC Block Diagram
Peripheral interrupt signal
Peripheral interrupt signal
Interrupt source/ transfer activation source selection
Data transfer control
Remark i = 0 to 4
DTCENi
DTCBAR
Internal bus
RAM
Control data vector table
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
19.3
Registers to Control the DTC
The following registers are used to control the DTC.
· Peripheral enable register 1 (PER1) · DTC activation enable register i (DTCENi) (i = 0 to 4) · DTC base address register (DTCBAR)
The DTC control data are listed below. DTC control data is allocated in the DTC control data area in RAM. The DTCBAR register is used to set the 256-byte area, including the DTC control data area and the DTC vector table area where the start address for control data is stored.
· DTC control register j (DTCCRj) (j = 0 to 23) · DTC block size register j (DTBLSj) (j = 0 to 23) · DTC transfer count register j (DTCCTj) (j = 0 to 23) · DTC transfer count reload register j (DTRLDj) (j = 0 to 23) · DTC source address register j (DTSARj) (j = 0 to 23) · DTC destination address register j (DTDARj) (j = 0 to 23)
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
19.3.1 Allocation of DTC control data area and DTC vector table area
The DTCBAR register is used to set the 256-byte area where DTC control data and the vector table are allocated within the RAM area. Figure 19 - 2 shows a Memory Map Example when the DTCBAR Register is Set to FBH. In the 192-byte DTC control data area, the space not used by the DTC can be used as RAM.
Figure 19 - 2 Memory Map Example when the DTCBAR Register is Set to FBH
FFFFFH FFF00H FFEE0H
Special function registers (SFRs)
General-purpose registers
RAM
Mirror
F1000H F0800H
F0000H
Data flash memory
Reserved Extended special function
registers (2nd SFRs)
Reserved
FFC00H FFBFFH
FFB40H FFB27H
00000H
Code flash memory
FFB00H Value set in the DTCBAR register
DTC control data area 192 bytes
Reserved area 24 bytes
DTC vector table area 40 bytes
Areas used by the DTC 256 bytes
The areas where the DTC control data and vector table can be allocated differ depending on the product.
Caution 1. It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space as the DTC control data area or DTC vector table area.
Caution 2. Make sure the stack area, the DTC control data area, and the DTC vector table area do not overlap. Caution 3. The internal RAM area in the following products cannot be used as the DTC control data area or DTC vector table
area when using the on-chip debugging trace function. R7F100GxG (x = A, B, C, E, F, G, J, L, M, P): FC300H to FC6FFH R7F100GxJ (x = A, B, C, E, F, G, J, L, M, P, S): FA300H to FA6FFH R7F100GxL, R7F100GxN (x = F, G, J, L, M, P, S): F4300H to F46FFH
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
19.3.2 Control data allocation
Control data is allocated beginning with each start address in the order: Registers DTCCRj, DTBLSj, DTCCTj, DTRLDj, DTSARj, and DTDARj (j = 0 to 23). The 8 higher-order bits for start addresses 0 to 23 are set by the DTCBAR register, and the 8 lower-order bits are separately set according to the vector table assigned to each activation source. Figure 19 - 3 shows Control Data Allocation.
Caution 1. Change the data in registers DTCCRj, DTBLSj, DTCCTj, DTRLDj, DTSARj, and DTDARj when the corresponding bit among bits DTCENi0 to DTCENi7 (i = 0 to 4) in the DTCENi register is set to 0 (activation disabled).
Caution 2. Do not access DTCCRj, DTBLSj, DTCCTj, DTRLDj, DTSARj, or DTDARj using a DTC transfer.
Figure 19 - 3 Control Data Allocation
Start addresses of control data
Addresses
FxxF8H Control data 23 FxxyyH Control data j
FxxBEH DTDAR15 register
FxxBCH DTSAR15 register
FxxBBH DTRLD15 register When j = 15 FxxBAH DTCCT15 register
FxxB9H DTBLS15 register FxxB8H DTCCR15 register
8 bytes
Fxx50H Fxx48H Fxx40H
Control data 2 Control data 1 Control data 0
Remark xx: Value set in the DTCBAR register
Fxx48H DTCCR1 register Fxx46H DTDAR0 register
Fxx44H DTSAR0 register
Fxx43H Fxx42H Fxx41H Fxx40H
DTRLD0 register DTCCT0 register DTBLS0 register DTCCR0 register
8 bytes
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Table 19 - 2 Start Addresses of Control Data
j
Address
11
Fxx98H
10
Fxx90H
9
Fxx88H
8
Fxx80H
7
Fxx78H
6
Fxx70H
5
Fxx68H
4
Fxx60H
3
Fxx58H
2
Fxx50H
1
Fxx48H
0
Fxx40H
Remark xx: Value set in the DTCBAR register
CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
j
Address
23
FxxF8H
22
FxxF0H
21
FxxE8H
20
FxxE0H
19
FxxD8H
18
FxxD0H
17
FxxC8H
16
FxxC0H
15
FxxB8H
14
FxxB0H
13
FxxA8H
12
FxxA0H
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
19.3.3 Vector table
When the DTC is activated, one control data is selected according to the data read from the vector table which has been assigned to each activation source, and the selected control data is read from the DTC control data area. Table 19 - 3 lists the DTC Activation Sources and Vector Addresses. A one byte of the vector table is assigned to each activation source, and data from 40H to F8H is stored in each area to select one of the 24 control data sets. The 8 higher-order bits for the vector address are set by the DTCBAR register, and 00H to 27H are allocated to the 8 lowerorder bits corresponding to the activation source.
Caution
Change the start address of the DTC control data area to be set in the vector table when the corresponding bit among bits DTCENi0 to DTCENi7 (i = 0 to 4) in the DTCENi register is set to 0 (activation disabled).
Figure 19 - 4 Start Addresses of Control Data and Vector Table
Example: When DTCBAR is set to FBH.
FFBF8H
Control data 23
Example: When the DTC activating trigger is generated as a result of the A/D conversion
The DTC reads the control data at FFB88H in the control data area according to the value of the vector table (88H) and transfers the data from the ADC.
FFB88H
Control data 15
FFB50H FFB48H FFB40H
Control data 2 Control data 1 Control data 0
FFB24H
68H
FFB0AH
88H
FFB02H
48H
FFB01H
50H
FFB00H
F8H
Comparator detection 1
End of A/D conversion
INTP1 INTP0 Reserved
DTC control data area FFB40H to FFBF8H (when DTCBAR is set to FBH)
DTC vector table FFB00H to FFB27H (when DTCBAR is set to FBH)
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
Table 19 - 3 DTC Activation Sources and Vector Addresses
DTC Activation Source (Interrupt Request Source)
Reserved INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6Note 5 INTP7Note 6 Key inputNote 3 A/D conversion end UART0 reception transfer end/CSI01 transfer end or buffer empty/IIC01 transfer end UART0 transmission transfer end/CSI00 transfer end or buffer empty/IIC00 transfer end UART1 reception transfer end/CSI11 transfer end or buffer empty/IIC11 transfer end UART1 transmission transfer end/CSI10 transfer end or buffer empty/IIC10 transfer end UART2 reception transfer end/CSI21 transfer end or buffer empty/IIC21 transfer end UART2 transmission transfer end/CSI20 transfer end or buffer empty/IIC20 transfer end UART3 reception transfer end/CSI31 transfer end or buffer empty/IIC31 transfer endNote 7 UART3 transmission transfer end/CSI30 transfer end or buffer empty/IIC30 transfer endNote 7 UARTA0 reception transfer endNote 2 UARTA0 transmission transfer end/buffer emptyNote 2 UARTA1 reception transfer endNote 4 UARTA1 transmission transfer end/buffer emptyNote 4 End of channel 0 of timer array unit 0 count or capture End of channel 1 of timer array unit 0 count or capture End of channel 2 of timer array unit 0 count or capture End of channel 3 of timer array unit 0 count or capture End of channel 4 of timer array unit 0 count or capture End of channel 5 of timer array unit 0 count or capture End of channel 6 of timer array unit 0 count or capture End of channel 7 of timer array unit 0 count or capture Fixed-cycle signal of realtime clock/alarm match detection Interval signal detection of 32-bit interval timer Request to write to a configuration register of an individual channel of the capacitive sensing unit (CTSUWR) Request to transfer data measured by the capacitive sensing unit (CTSURD) Comparator detection 0 Comparator detection 1 Event output from the logic and event link controller Event output from the SNOOZE mode sequencer Voltage detectionNote 1
Source No.
Vector Address
0
Address set in the DTCBAR register + 00H
1
Address set in the DTCBAR register + 01H
2
Address set in the DTCBAR register + 02H
3
Address set in the DTCBAR register + 03H
4
Address set in the DTCBAR register + 04H
5
Address set in the DTCBAR register + 05H
6
Address set in the DTCBAR register + 06H
7
Address set in the DTCBAR register + 07H
8
Address set in the DTCBAR register + 08H
9
Address set in the DTCBAR register + 09H
10 Address set in the DTCBAR register + 0AH
11 Address set in the DTCBAR register + 0BH
12 Address set in the DTCBAR register + 0CH
13 Address set in the DTCBAR register + 0DH
14 Address set in the DTCBAR register + 0EH
15 Address set in the DTCBAR register + 0FH
16 Address set in the DTCBAR register + 10H
17 Address set in the DTCBAR register + 11H
18 Address set in the DTCBAR register + 12H
19 Address set in the DTCBAR register + 13H
20 Address set in the DTCBAR register + 14H
21 Address set in the DTCBAR register + 15H
22 Address set in the DTCBAR register + 16H
23 Address set in the DTCBAR register + 17H
24 Address set in the DTCBAR register + 18H
25 Address set in the DTCBAR register + 19H
26 Address set in the DTCBAR register + 1AH
27 Address set in the DTCBAR register + 1BH
28 Address set in the DTCBAR register + 1CH
29 Address set in the DTCBAR register + 1DH
30 Address set in the DTCBAR register + 1EH
31 Address set in the DTCBAR register + 1FH
32 Address set in the DTCBAR register + 20H
33 Address set in the DTCBAR register + 21H
34 Address set in the DTCBAR register + 22H 35 Address set in the DTCBAR register + 23H 36 Address set in the DTCBAR register + 24H 37 Address set in the DTCBAR register + 25H 38 Address set in the DTCBAR register + 26H 39 Address set in the DTCBAR register + 27H
Priority Highest
Lowest
Note 1.
Note 2. Note 3. Note 4. Note 5. Note 6. Note 7.
When bit 6 (LVD0SEL) of the option byte (000C1H) is set to 0 or when bit 7 (LVD1SEL) of the voltage detection level register (LVIS) is set to 0 For 36- to 128-pin products only. For 40- to 128-pin products only. For 44- to 128-pin products only. For 48- to 128-pin products only. For 64- to 128-pin products only. For 80- to 128-pin products only.
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
19.3.4 Peripheral enable register 1 (PER1)
The PER1 register is used to enable or disable the supply of a clock signal to various on-chip peripheral modules. Clock supply to an on-chip peripheral module that is not to be used can be stopped to decrease power consumption and noise. If the DTC is to be used, be sure to set bit 3 (DTCEN) to 1.
The PER1 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 19 - 5 Format of Peripheral Enable Register 1 (PER1)
Address: After reset: R/W:
F00FAH 00H R/W
Symbol
<7>
PER1 DACEN
<6> SMSEN
<5> CMPEN
<4> TML32EN
<3> DTCEN
<2> UTAEN
<1> REMCEN
<0> CTSUEN
DTCEN
Control of supply of an input clock to the DTC
0
Stops supply of an input clock.
· The SFRs used by the DTC cannot be written.
1
Enables supply of an input clock.
· The DTC can operate.
Caution The functions mounted depend on the product. For details on the PER1 register, see CHAPTER 6 CLOCK GENERATOR.
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
19.3.5 DTC control register j (DTCCRj) (j = 0 to 23)
The DTCCRj register is used to control the DTC operating mode.
Figure 19 - 6 Format of DTC Control Register j (DTCCRj)
Address: After reset: R/W:
Refer to 19.3.2 Control data allocation. Undefined R/W
Symbol
7
DTCCRj
0
6
5
4
3
2
1
0
SZ
RPTINT
CHNE
DAMOD SAMOD RPTSEL MODE
SZ
0
8 bits
1
16 bits
Transfer data size selection
RPTINT
Enabling/disabling repeat mode interrupts
0
Interrupt generation disabled
1
Interrupt generation enabled
The setting of the RPTINT bit is invalid when the MODE bit is 0 (normal mode).
CHNE
Enabling/disabling chain transfers
0
Chain transfers disabled
1
Chain transfers enabled
Set the CHNE bit in the DTCCR23 register to 0 (chain transfers disabled).
DAMOD
Transfer destination address control
0
Fixed
1
Incremented
The setting of the DAMOD bit is invalid when the MODE bit is 1 (repeat mode) and the RPTSEL bit is 0
(transfer destination is the repeat area).
SAMOD
Transfer source address control
0
Fixed
1
Incremented
The setting of the SAMOD bit is invalid when the MODE bit is 1 (repeat mode) and the RPTSEL bit is 1
(transfer source is the repeat area).
RPTSEL
Repeat area selection
0
Transfer destination is the repeat area.
1
Transfer source is the repeat area.
The setting of the RPTSEL bit is invalid when the MODE bit is 0 (normal mode).
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
MODE 0 1
Normal mode Repeat mode
Transfer mode selection
Caution Do not access the DTCCRj register using a DTC transfer.
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
19.3.6 DTC block size register j (DTBLSj) (j = 0 to 23)
This register is used to set the block size of the data to be transferred by one activation.
Figure 19 - 7 Format of DTC Block Size Register j (DTBLSj)
Address: After reset: R/W:
Refer to 19.3.2 Control data allocation. Undefined R/W
Symbol
7
DTBLSj DTBLSj7
6 DTBLSj6
5 DTBLSj5
4 DTBLSj4
3 DTBLSj3
2 DTBLSj2
1 DTBLSj1
0 DTBLSj0
DTBLSj
8-Bit Transfer
Transfer Block Size
00H 256 bytes
512 bytes
01H 1 byte
2 bytes
02H 2 bytes
4 bytes
03H 3 bytes
6 bytes
·
·
·
·
·
·
·
·
·
FDH 253 bytes
506 bytes
FEH 254 bytes
508 bytes
FFH 255 bytes
510 bytes
Caution Do not access the DTBLSj register using a DTC transfer.
16-Bit Transfer
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
19.3.7 DTC transfer count register j (DTCCTj) (j = 0 to 23)
This register is used to set the number of DTC data transfers. The value is decremented by 1 each time DTC transfer is activated once.
Figure 19 - 8 Format of DTC Transfer Count Register j (DTCCTj)
Address: After reset: R/W:
Refer to 19.3.2 Control data allocation. Undefined R/W
Symbol
7
DTCCTj DTCCTj7
6 DTCCTj6
5 DTCCTj5
4 DTCCTj4
3 DTCCTj3
2 DTCCTj2
1 DTCCTj1
0 DTCCTj0
DTCCTj
Number of Transfers
00H 256 times
01H Once
02H 2 times
03H 3 times
·
·
·
·
·
·
FDH 253 times
FEH 254 times
FFH 255 times
Caution Do not access the DTCCTj register using a DTC transfer.
19.3.8 DTC transfer count reload register j (DTRLDj) (j = 0 to 23)
This register is used to set the initial value of the transfer count register in repeat mode. Since the value of this register is reloaded to the DTCCT register in repeat mode, set the same value as the initial value of the DTCCT register.
Figure 19 - 9 Format of DTC Transfer Count Reload Register j (DTRLDj)
Address: After reset: R/W:
Refer to 19.3.2 Control data allocation. Undefined R/W
Symbol
7
DTRLDj DTRLDj7
6 DTRLDj6
5 DTRLDj5
4 DTRLDj4
3 DTRLDj3
2 DTRLDj2
Caution Do not access the DTRLDj register using a DTC transfer.
1 DTRLDj1
0 DTRLDj0
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
19.3.9 DTC source address register j (DTSARj) (j = 0 to 23)
This register is used to specify the transfer source address for data transfer. When the SZ bit in the DTCCRj register is set to 1 (16-bit transfer), the lowest-order bit is ignored and the address is handled as an even address.
Figure 19 - 10 Format of DTC Source Address Register j (DTSARj)
Address: After reset: R/W:
Refer to 19.3.2 Control data allocation. Undefined R/W
Symbol
15
14
13
12
11
10
9
DTSARj DTSARj15 DTSARj14 DTSARj13 DTSARj12 DTSARj11 DTSARj10 DTSARj9
8 DTSARj8
7 DTSARj7
6 DTSARj6
5 DTSARj5
4 DTSARj4
3 DTSARj3
2 DTSARj2
1 DTSARj1
0 DTSARj0
Caution 1. Do not set the general-purpose register (FFEE0H to FFEFFH) space to the transfer source address. Caution 2. Do not access the DTSARj register using a DTC transfer.
19.3.10 DTC destination address register j (DTDARj) (j = 0 to 23)
This register is used to specify the transfer destination address for data transfer. When the SZ bit in the DTCCRj register is set to 1 (16-bit transfer), the lowest-order bit is ignored and the address is handled as an even address.
Figure 19 - 11 Format of DTC Destination Address Register j (DTDARj)
Address: After reset: R/W:
Refer to 19.3.2 Control data allocation. Undefined R/W
Symbol
15
14
13
12
11
10
9
DTDARj DTDARj15 DTDARj14 DTDARj13 DTDARj12 DTDARj11 DTDARj10 DTDARj9
8 DTDARj8
7 DTDARj7
6 DTDARj6
5 DTDARj5
4 DTDARj4
3 DTDARj3
2 DTDARj2
1 DTDARj1
0 DTDARj0
Caution 1. Do not set the general-purpose register (FFEE0H to FFEFFH) space to the transfer destination address. Caution 2. Do not access the DTDARj register using a DTC transfer.
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
19.3.11 DTC activation enable register i (DTCENi) (i = 0 to 4)
This is an 8-bit register which enables or disables DTC activation by interrupt sources. Table 19 - 4 lists the Correspondences between interrupt Sources and Bits DTCENi0 to DTCENi7. The DTCENi register can be set by a 1-bit or 8-bit memory manipulation instruction.
Caution 1. Modify bits DTCENi0 to DTCENi7 if an activation source corresponding to the bit has not been generated.
Caution 2. Do not access the DTCENi register using a DTC transfer. Caution 3. The assigned functions differ depending on the product. For the bits to which no function is
assigned, be sure to set their values to 0.
Figure 19 - 12 Format of DTC Activation Enable Register i (DTCENi) (i = 0 to 4)
Address: After reset: R/W:
F02E8H (DTCEN0), F02E9H (DTCEN1), F02EAH (DTCEN2), F02EBH (DTCEN3), F02ECH (DTCEN4) 00H R/W
Symbol
7
DTCENi DTCENi7
6 DTCENi6
5 DTCENi5
4 DTCENi4
3 DTCENi3
2 DTCENi2
1 DTCENi1
0 DTCENi0
DTCENi7
DTC activation enable i7
0
Activation disabled
1
Activation enabled
The DTCENi7 bit is set to 0 (activation disabled) by a condition for generating a transfer end interrupt.
DTCENi6
DTC activation enable i6
0
Activation disabled
1
Activation enabled
The DTCENi6 bit is set to 0 (activation disabled) by a condition for generating a transfer end interrupt.
DTCENi5
DTC activation enable i5
0
Activation disabled
1
Activation enabled
The DTCENi5 bit is set to 0 (activation disabled) by a condition for generating a transfer end interrupt.
DTCENi4
DTC activation enable i4
0
Activation disabled
1
Activation enabled
The DTCENi4 bit is set to 0 (activation disabled) by a condition for generating a transfer end interrupt.
DTCENi3
DTC activation enable i3
0
Activation disabled
1
Activation enabled
The DTCENi3 bit is set to 0 (activation disabled) by a condition for generating a transfer end interrupt.
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DTCENi2
DTC activation enable i2
0
Activation disabled
1
Activation enabled
The DTCENi2 bit is set to 0 (activation disabled) by a condition for generating a transfer end interrupt.
DTCENi1
DTC activation enable i1
0
Activation disabled
1
Activation enabled
The DTCENi1 bit is set to 0 (activation disabled) by a condition for generating a transfer end interrupt.
DTCENi0
DTC activation enable i0
0
Activation disabled
1
Activation enabled
The DTCENi0 bit is set to 0 (activation disabled) by a condition for generating a transfer end interrupt.
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
Table 19 - 4 Correspondences between Interrupt Sources and Bits DTCENi0 to DTCENi7
Register
DTCENi7 Bit
DTCENi6 Bit
DTCENi5 Bit
DTCENi4 Bit
DTCENi3 Bit
DTCENi2 Bit
DTCENi1 Bit
DTCENi0 Bit
DTCEN0
Reserved
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTP6Note 5
DTCEN1
INTP7Note 6
Key inputNote 3
A/D conversion end
UART0 reception transfer end/CSI01 transfer end or buffer empty/IIC01 transfer end
UART0 transmission transfer end/CSI00 transfer end or buffer empty/IIC00 transfer end
UART1 reception transfer end/CSI11 transfer end or buffer empty/IIC11 transfer end
UART1 transmission transfer end/CSI10 transfer end or buffer empty/IIC10 transfer end
UART2 reception transfer end/CSI21 transfer end or buffer empty/IIC21 transfer end
DTCEN2
UART2 transmission transfer end/CSI20 transfer end or buffer empty/IIC20 transfer end
UART3 reception transfer end/CSI31 transfer end or buffer empty/IIC31 transfer endNote 7
UART3 transmission transfer end/CSI30 transfer end or buffer empty/IIC30 transfer end
Note 7
UARTA0 reception transfer endNote 2
UARTA0 transmission transfer end/buffer emptyNote 2
UARTA1 reception transfer endNote 4
UARTA1 transmission transfer end/buffer emptyNote 4
End of channel 0 of timer array unit 0 count or capture
DTCEN3
End of channel 1 of timer array unit 0 count or capture
End of channel 2 of timer array unit 0 count or capture
End of channel 3 of timer array unit 0 count or capture
End of channel 4 of timer array unit 0 count or capture
End of channel 5 of timer array unit 0 count or capture
End of channel 6 of timer array unit 0 count or capture
End of channel 7 of timer array unit 0 count or capture
Fixed-cycle signal of realtime clock/alarm match detection
DTCEN4
Interval signal detection of 32bit interval timer
Request to write to a configuration register of an individual channel of the capacitive sensing unit
Request to transfer data measured by the capacitive sensing unit
Comparator detection 0
Comparator detection 1
Event output from the logic and event link controller
Event output from the SNOOZE mode sequencer
Voltage detectionNote 1
Note 1.
Note 2. Note 3. Note 4. Note 5. Note 6. Note 7.
When bit 6 (LVD0SEL) of the option byte (000C1H) is set to 0 or when bit 7 (LVD1SEL) of the voltage detection level register (LVIS) is set to 0 For 36- to 128-pin products only. For 40- to 128-pin products only. For 44- to 128-pin products only. For 48- to 128-pin products only. For 64- to 128-pin products only. For 80- to 128-pin products only.
Caution For the bits to which no function is assigned, be sure to set their values to 0.
Remark i = 0 to 4
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
19.3.12 DTC base address register (DTCBAR)
This is an 8-bit register used to set the following addresses: the vector address where the start address of the DTC control data area is stored and the address of the DTC control data area. The value of the DTCBAR register is handled as the 8 higher-order bits to generate a 16-bit address. The DTCBAR register can be set by an 8-bit memory manipulation instruction.
Caution 1. Change the DTCBAR register value with all DTC activation sources set to activation disabled. Caution 2. Do not rewrite the DTCBAR register more than once. Caution 3. Do not access the DTCBAR register using a DTC transfer. Caution 4. For the allocation of the DTC control data area and the DTC vector table area, refer to the cautions in
19.3.1 Allocation of DTC control data area and DTC vector table area.
Figure 19 - 13 Format of the DTC Base Address Register (DTCBAR)
Address: After reset: R/W:
F02E0H FDH R/W
Symbol
7
6
5
4
3
2
1
0
DTCBAR DTCBAR7 DTCBAR6 DTCBAR5 DTCBAR4 DTCBAR3 DTCBAR2 DTCBAR1 DTCBAR0
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
19.4
DTC Operation
When the DTC is activated, the DTC reads control data from the DTC control data area, proceeds with data transfer according to the control data, and writes back the control data after data transfer to the DTC control data area. Twentyfour sets of control data can be stored in the DTC control data area, which allows 24 types of data transfers to be performed. There are two transfer modes (normal mode and repeat mode) and two transfer sizes (8-bit transfer and 16-bit transfer). When the CHNE bit in the DTCCRj (j = 0 to 23) register is set to 1 (chain transfers enabled), multiple control data is read and data transfers are continuously performed by one activation source (chain transfers). A transfer source address is specified by the 16-bit register DTSARj, and a transfer destination address is specified by the 16-bit register DTDARj. The values in registers DTSARj and DTDARj are separately incremented or fixed according to the control data after the data transfer.
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
19.4.1 Activation sources
The DTC is activated by an interrupt signal from the peripheral functions. The interrupt signals to activate the DTC are selected with the DTCENi (i = 0 to 4) register. The DTC sets the corresponding bit among bits DTCENi0 to DTCENi7 in the DTCENi register to 0 (activation disabled) during operation when the setting of data transfer (the first transfer in chain transfers) is either of the following: · A transfer that causes the DTCCTj (j = 0 to 23) register value to change to 0 in normal mode · A transfer that causes the DTCCTj register value to change to 0 while the RPTINT bit in the DTCCRj register is 1
(interrupt generation enabled) in repeat mode Figure 19 - 14 shows DTC Internal Operation Flowchart.
Figure 19 - 14 DTC Internal Operation Flowchart
DTC activation source generation
Read vector
Read control data
Yes Branch (1)
No Transfer data
Write back control data
Yes CHNE = 1?
No
Branch (1) 0 is written to the bit among bits DTCENi0 to DTCENi7 and an interrupt request is generated when transfer is either of the following: - A transfer that causes the DTCCTj (j = 0 to 23) register value to change from 1 to 0 in normal mode - A transfer that causes the DTCCTj register value to change from 1 to 0 while the RPTINT bit is 1 in repeat mode
Remark: DTCENi0 to DTCENi7: Bits in DTCENi (i = 0 to 4) register RPTINT, CHNE: Bits in DTCCRj (j = 0 to 23) register
(Note)
Write 0 to the bit among bits DTCENi0 to DTCENi7 Generate an interrupt request
Read control data
Transfer data
Read control data
Transfer data
Write back control data
Yes CHNE = 1?
No
Write back control data
Yes CHNE = 1?
No
Transfer data
Write back control data
Yes CHNE = 1?
No
End
Interrupt handling
Note
0 is not written to the bit among bits DTCENi0 to DTCENi7 for data transfers activated by the setting to enable chain transfers (the CHNE bit is 1). Also, no interrupt request is generated.
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
19.4.2 Normal mode
One to 256 bytes of data are transferred by one activation during 8-bit transfer and 2 to 512 bytes during 16-bit transfer. The number of transfers can be 1 to 256 times. When the data transfer causing the DTCCTj (j = 0 to 23) register value to change to 0 is performed, the DTC generates an interrupt request corresponding to the activation source to the interrupt controller during DTC operation, and sets the corresponding bit among bits DTCENi0 to DTCENi7 (i = 0 to 4) in the DTCENi register to 0 (activation disabled). Table 19 - 5 shows Register Functions in Normal Mode. Figure 19 - 15 shows Date Transfers in Normal Mode.
Table 19 - 5 Register Functions in Normal Mode
Register Name
Symbol
Function
DTC block size register j
DTBLSj
Size of the data block to be transferred by one activation
DTC transfer count register j
DTCCTj
Number of data transfers
DTC transfer count reload register j
DTRLDj
Not usedNote
DTC source address register j
DTSARj
Data transfer source address
DTC destination address register j
DTDARj
Data transfer destination address
Note
Initialize this register to 00H when parity error resets are enabled (RPERDIS = 0) using the RAM parity error detection function.
Remark j = 0 to 23
Figure 19 - 15 Data Transfers in Normal Mode
FFFFFH
SRC
Transfer
DST
Size of the data block to be transferred by one activation (N bytes)
DTBLSj register = N DTSARj register = SRC DTDARj register = DST
j = 0 to 23
F0000 H
DTCCR Register Setting
DAMOD SAMOD RPTSEL MODE
0
0
X
0
0
1
X
0
1
0
X
0
1
1
X
0
Source Address Control
Fixed Incremented Fixed Incremented
Destination Address Control
Fixed Fixed Incremented Incremented
Source Address after Transfer
SRC SRC + N SRC SRC + N
X: 0 or 1
Destination Address after Transfer
DST DST DST + N DST + N
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
(1) Example 1 of using normal mode: Consecutively capturing A/D conversion results The DTC is activated by an A/D conversion end interrupt and the value of the A/D conversion result register is transferred to RAM.
· The vector address is FFB0AH and control data is allocated at FFBA0H to FFBA7H. · Transfers 2-byte data of the A/D conversion result register (FFF1EH, FFF1FH) to 80 bytes of FFD80H to FFDCFH
of RAM 40 times.
Figure 19 - 16 Example 1 of Using Normal Mode: Consecutively Capturing A/D Conversion Results
DTCBAR = FBH
Vector address (FFB0AH) = A0H DTCCR12 (FFBA0H) = 48H DTBLS12 (FFBA1H) = 01H DTCCT12 (FFBA2H) = 28H
DTSAR12 (FFBA4H) = FF1EH DTDAR12 (FFBA6H) = FD80H
DTCEN15 = 1
Starting A/D conversion
A/D conversion result register
RAM
FDCEH FD80H
A/D conversion end interrupt?
Yes
DTCCT12 = 01H? No
Data transfer
No
Yes Occurrence of A/D conversion end interrupt DTCEN15 = 0
Data transfer
Interrupt handling
The processing shown inside the dotted lines is automatically executed by the DTC.
The value of the DTRLD12 register is not used because of normal mode, but initialize the register to 00H when parity error resets are enabled (RPERDIS = 0) using the RAM parity error detection function.
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
(2) Example 2 of using normal mode: UART0 consecutive transmission The DTC is activated by a UART0 transmit buffer empty interrupt and the value of RAM is transferred to the UART0 transmit buffer.
· The vector address is FFB0CH and control data is allocated at FFBC8H to FFBCFH. · Transfers 8 bytes of data at addresses from FFCF8H to FFCFFH of RAM to the UART0 transmit buffer (FFF10H).
Figure 19 - 17 Example 2 of Using Normal Mode: UART0 Consecutive Transmission
DTCBAR = FBH
Vector address (FFB0CH) = C8H DTCCR17 (FFBC8H) = 04H DTBLS17 (FFBC9H) = 01H DTCCT17 (FFBCAH) = 08H
DTSAR17 (FFBCCH) = FCF8H DTDAR17 (FFBCEH) = FF10H
DTCEN13 = 1
Starting UART0 transmission
RAM
FCFFH
UART0 transmit buffer
FCF8H
Transmit buffer empty interrupt?
Yes
DTCCT17 = 01H? No
Data transfer
No
Yes Occurrence of UART0 transmit buffer empty interrupt DTCEN13 = 0
Data transfer
Interrupt handling
The processing shown inside the dotted lines is automatically executed by the DTC.
The value of the DTRLD17 register is not used because of normal mode, but initialize the register to 00H when parity error resets are enabled (RPERDIS = 0) using the RAM parity error detection function. Start the first UART0 transmission by software. The second and subsequent transmissions proceeds automatically by using transmit buffer empty interrupts to activate the DTC.
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
19.4.3 Repeat mode
One to 255 bytes of data are transferred by one activation. Either of the transfer source or destination should be specified as the repeat area. The number of transfers can be 1 to 255 times. On completion of the specified number of transfers, the DTCCTj (i = 0 to 23) register and the address specified for the repeat area are initialized to continue transfers. When the data transfer causing the DTCCTj register value to change to 0 is performed while the RPTINT bit in the DTCCRj register is 1 (interrupt generation enabled), the DTC generates an interrupt request corresponding to the activation source to the interrupt controller during DTC operation, and sets the corresponding bit among bits DTCENi0 to DTCENi7 (i = 0 to 4) in the DTCENi register to 0 (activation disabled). When the RPTINT bit in the DTCCRj register is 0 (interrupt generation disabled), no interrupt request is generated even if the data transfer causing the DTCCTj register value to change to 0 is performed. Also, bits DTCENi0 to DTCENi7 are not set to 0. Table 19 - 6 lists Register Functions in Repeat Mode. Figure 19 - 18 shows Data Transfers in Repeat Mode.
Table 19 - 6 Register Functions in Repeat Mode
Register Name
Symbol
DTC block size register j
DTBLSj
DTC transfer count register j
DTCCTj
DTC transfer count reload register j
DTRLDj
DTC source address register j DTC destination address register j
Remark j = 0 to 23
DTSARj DTDARj
Function Size of the data block to be transferred by one activation Number of data transfers This register value is reloaded to the DTCCT register (the number of transfers is initialized). Data transfer source address Data transfer destination address
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RL78/G23 Figure 19 - 18 Data Transfers in Repeat Mode
DTCCTj register 1 FFFFFH
CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
SRC
Transfer
DST
Size of the data block to be transferred by one activation (N bytes)
DTBLSj register = N DTCCTj register 1 DTSARj register = SRC DTDARj register = DST
j = 0 to 23
F0000H
DTCCR Register Setting
DAMOD SAMOD RPTSEL MODE
0
X
1
1
1
X
1
1
X
0
0
1
X
1
0
1
Source Address Destination Address Source Address
Control
Control
after Transfer
Repeat area Fixed
SRC + N
Repeat area Incremented
SRC + N
Fixed
Repeat area
SRC
Incremented Repeat area
SRC + N
X: 0 or 1
Destination Address after Transfer
DST DST + N DST + N DST + N
DTCCTj register = 1 FFFFFH
SRC/DST
DTBLSj register = N DTCCTj register = 1 DTSARj register = SRC DTDARj register = DST
j = 0 to 23
SRC0/DST0
Address of the repeat area is initialized after a data transfer.
F0000H
DTCCR Register Setting
DAMOD SAMOD RPTSEL MODE
0
X
1
1
1
X
1
1
X
0
0
1
X
1
0
1
Source Address Destination Address Source Address
Control
Control
after Transfer
Repeat area Fixed
SRC0
Repeat area Incremented
SRC0
Fixed
Repeat area
SRC
Incremented Repeat area
SRC + N
SRC0: Initial source address value DST0: Initial destination address value X: 0 or 1
Destination Address after Transfer
DST DST + N DST0 DST0
Caution 1. When repeat mode is used, the 8 lower-order bits of the initial value for the repeat area address must be 00H. Caution 2. When repeat mode is used, the data size of the repeat area must be set to 255 bytes or less.
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
(1) Example 1 of using repeat mode: Outputting stepping motor control pulses using port pins The DTC is activated using the interval timer function of channel 0 of timer array unit 0, and the patterns of the motor control pulse stored in the code flash memory are transferred to the general-purpose port pins.
· The vector address is FFC14H and control data is allocated at FFCD0H to FFCD7H. · Transfers 8-byte data at addresses from 02000H to 02007H of the code flash memory from the mirror area
(F2000H to F2007H) to port register 1 (FFF01H). · A repeat mode interrupt is disabled.
Figure 19 - 19 Example 1 of Using Repeat Mode: Outputting Stepping Motor Control Pulses Using Port Pins
DTCBAR = FCH
Vector address (FFC14H) = D0H DTCCR18 (FFCD0H) = 03H DTBLS18 (FFCD1H) = 01H DTCCT18 (FFCD2H) = 08H DTRLD18 (FFCD3H) = 08H
DTSAR18 (FFCD4H) = 2000H DTDAR18 (FFCD6H) = FF01H
DTCEN24 = 1
2007H
Code flash memory
2000H
Port register 1
Timer setting
Setting P10 to P13 to output mode
Starting timer operation Data transfer
Timer channel 00
No
count end interrupt?
Yes
Yes DTCCT18 = 01H?
No
DTCCT18 = DTRLD18
Data transfer
P13 P12 P11 P10
Example of 1-2 phase excitation
To stop the output, stop the timer first and then clear DTCEN24.
The processing shown inside the dotted lines is automatically executed by the DTC.
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
(2) Example 2 of using repeat mode: Outputting a sine wave using the 8-bit D/A converter The DTC is activated using an interrupt of the interval timer function of channel 0 of timer array unit 1, and the table of the sine wave stored in the data flash memory is transferred to the 8-bit D/A conversion value setting register 0 (F0330H). The timer interval time is set to the D/A output setup time.
· The vector address is FFC17H and control data is allocated at FFCD8H to FFCDFH. · Transfers 255-byte data at addresses from F1200H to F12FEH of the data flash memory to the D/A conversion
value setting register 0 (F0330H). · A repeat mode interrupt is disabled.
Figure 19 - 20 Example 2 of Using Repeat Mode: Outputting a Sine Wave Using the 8-bit D/A Converter
DTCBAR = FCH
Vector address (FFC17H) = D8H DTCCR19 (FFCD8H) = 03H DTBLS19 (FFCD9H) = 01H DTCCT19 (FFCDAH) = FFH DTRLD19 (FFCDBH) = FFH
DTSAR19 (FFCDCH) = 1200H DTDAR19 (FFCDEH) = FF1CH
DTCEN20 = 1
12FFH
D/A conversion value setting register 0
Data flash memory
1200H
Timer setting
Enabling D/A conversion Starting timer operation
Data transfer DTCCT19 = DTRLD19
Timer channel 10
No
count end interrupt?
Yes
Yes DTCCT19 = 01H?
No
Data transfer
To stop the output, stop the timer first and then clear DTCEN20. Caution Timer array unit 1 is provided in 80- to 128-pin products.
The processing shown inside the dotted lines is automatically executed by the DTC.
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
19.4.4 Chain transfers
When the CHNE bit in the DTCCRj (j = 0 to 22) register is 1 (chain transfers enabled), multiple data transfers can be continuously performed by one activation source. When the DTC is activated, one control data is selected according to the data read from the vector address corresponding to the activation source, and the selected control data is read from the DTC control data area. When the CHNE bit for the control data is 1 (chain transfers enabled), the next control data immediately following the current control data is read to continue a transfer after the current transfer is completed. This operation is repeated until the data transfer with the control data for which the CHNE bit is 0 (chain transfers disabled) is completed. When chain transfers are performed using multiple control data, the number of transfers set for the first control data is enabled, and the number of transfers set for the second and subsequent control data to be processed will be invalid. Figure 19 - 21 shows Data Transfers during Chain Transfers.
Figure 19 - 21 Data Transfers during Chain Transfers
FFFFFH
DTC activation source generation
DTDAR2 register
DTSAR2 register
DTRLD2 register DTCCT2 register
DTBLS2 register DTCCR2 register
DTDAR1 register
DTSAR1 register
DTRLD1 register DTBLS1 register
DTCCT1 register DTCCR1 register
Higher address Lower address
Control data 2 (the CHNE bit is 0)
Control data 1 (the CHNE bit is 1)
Read vector Read control data 1
Transfer data Write back control data 1
Read control data 2 Transfer data
F0000H
Write back control data 2 End of DTC transfers
Note 1. Note 2.
Set the CHNE bit in the DTCCR23 register to 0 (chain transfers disabled). During chain transfers, bits DTCENi0 to DTCENi7 (i = 0 to 4) in the DTCENi register are not set to 0 (activation disabled) for the second and subsequent transfers. Also, no interrupt request is generated.
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
(1) Example of using chain transfers: Consecutively capturing A/D conversion results and UART0 transmission The DTC is activated by an A/D conversion end interrupt and A/D conversion results are transferred to RAM, and then transmitted using the UART0.
· The vector address is FFB0AH. · The control data for capturing A/D conversion results is allocated at FFBA0H to FFBA7H. · The control data for UART0 transmission is allocated at FFBA8H to FFBAFH. · Transfers 2-byte data of the A/D conversion result register (FFF1FH, FFF1EH) to FFD80H to FFDCFH of RAM,
and transfers the 1 higher-order byte (FFF1FH) of the A/D conversion result register to the UART transmit buffer (FFF10H).
Figure 19 - 22 Example of Using Chain Transfers: Consecutively Capturing A/D Conversion Results and UART0 Transmission
DTCBAR = FBH
Setting the control data for capturing
A/D conversion results Vector address (FFB0AH) = A0H
DTCCR12 (FFBA0H) = 58H DTBLS12 (FFBA1H) = 01H DTCCT12 (FFBA2H) = 50H DTSAR12 (FFBA4H) = FF1EH DTDAR12 (FFBA6H) = FD80H
Setting the control data for UART0 transmission Vector address (FFB0CH) = C8H DTCCR17 (FFBC8H) = 00H DTBLS17 (FFBC9H) = 01H DTCCT17 (FFBCAH) = 00H DTSAR17 (FFBCCH) = FF1FH DTDAR17 (FFBCEH) = FF10H
DTCEN15 = 1
UART0 setting
Starting A/D conversion
A/D conversion result register
UART0 transmit buffer
RAM
FDCEH FD80H
A/D conversion
No
end interrupt?
Yes
Yes DTCCT12 = 01H?
No
Transfer from A/D conversion result register to RAM
Transfer from A/D conversion result register to UART0 transmit buffer
Occurrence of A/D conversion end interrupt request DTCEN15 = 0
Transfer from A/D conversion result register to RAM
Transfer from A/D conversion result register to UART0 transmit buffer
The processing shown inside the dotted lines is automatically executed by the DTC.
Interrupt handling
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
19.5
Points for Caution when the DTC is to be Used
19.5.1 Setting DTC control data and vector table
· Do not access the DTC extended special function registers (2nd SFRs), the DTC control data area, the DTC vector table area, or the general-purpose register (FFEE0H to FFEFFH) space using a DTC transfer.
· Modify the DTC base address register (DTCBAR) while all DTC activation sources are set to activation disabled. · Do not rewrite the DTC base address register (DTCBAR) twice or more. · Modify the data of the DTCCRj, DTBLSj, DTCCTj, DTRLDj, DTSARj, or DTDARj register when the corresponding bit
among bits DTCENi0 to DTCENi7 in the DTCENi (i = 0 to 4) register is 0 (activation disabled). · Modify the start address of the DTC control data area to be set in the vector table when the corresponding bit among
bits DTCENi0 to DTCENi7 in the DTCENi (i = 0 to 4) register is 0 (activation disabled).
19.5.2 Allocation of DTC control data area and DTC vector table area
The areas where the DTC control data and vector table can be allocated differ depending on the product and usage conditions. · It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space as the DTC control data area or DTC
vector table area. · Make sure the stack area, the DTC control data area, and the DTC vector table area do not overlap. · The internal RAM area in the following products cannot be used as the DTC control data area or DTC vector table area
when using the on-chip debugging trace function. R7F100GxG (x = A, B, C, E, F, G, J, L, M, P): FC300H to FC6FFH R7F100GxJ (x = A, B, C, E, F, G, J, L, M, P, S): FA300H to FA6FFH R7F100GxL, R7F100GxN (x = F, G, J, L, M, P, S): F4300H to F46FFH · Initialize the DTRLD register to 00H even in normal mode when parity error resets are enabled (RPERDIS = 0) using the RAM parity error detection function. · If the internal RAM is placed in standby mode or shutdown mode (RAMSDMD = 1) by the memory power reduction control register (PSMCR), the internal RAM cannot be used as the DTC control data area or DTC vector table area. · The area where debug monitor programs are allocated when using the on-chip debugging function cannot be used as the DTC control data area or DTC vector table area. For details, see 34.4 Allocation of Memory Spaces to User Resources.
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
19.5.3 DTC pending instruction
Even if a DTC transfer request is generated, DTC transfer is held pending immediately after the following instructions. Also, the DTC is not activated between PREFIX instruction code and the instruction immediately after that code. · Call/return instruction · Unconditional branch instruction · Conditional branch instruction · Read access instruction for code flash memory · Bit manipulation instructions for IFxx, MKxx, PRxx, and PSW, and an 8-bit manipulation instruction that has the ES
register as operand · Instruction for accessing the data flash memory · Multiply/divide/multiply & accumulate instruction (excluding MULU)
Caution 1. When a DTC transfer request is acknowledged, all interrupt requests are held pending until DTC transfer is completed.
Caution 2. While the DTC is held pending by the DTC pending instruction, all interrupt requests are held pending.
19.5.4 Operation when accessing data flash memory space
When accessing the data flash space after an instruction execution from the start of DTC data transfer, a wait of three clock cycles will be inserted to the next instruction.
Instruction 1 DTC data transfer Instruction 2 The wait of three clock cycles occurs. MOV A, ! Data Flash space
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
19.5.5 Number of DTC execution clock cycles
Table 19 - 7 lists the Operations following DTC Activation and Required Number of Cycles for each operation.
Table 19 - 7 Operations following DTC Activation and Required Number of Cycles
Vector Read 1
Read 4
Control Data Write-back Note 1
Data read Note 2
Data Write Note 2
Note 1. Note 2.
For the number of clock cycles required for control data write-back, refer to Table 19 - 8 Number of Clock Cycles Required for Control Data Write-Back Operation. For the number of clock cycles required for data read/write, refer to Table 19 - 9 Number of Clock Cycles Required for One Data Read/Write Operation.
Table 19 - 8 Number of Clock Cycles Required for Control Data Write-Back Operation
DTCCR Register Setting DAMOD SAMOD RPTSEL MODE
Address Setting Source Destination
DTCCTj Register
Control Register to be Written Back
DTRLDj Register
DTSARj Register
DTDARj Register
0
0
X
0
Fixed
Fixed
Written back Written back Not written
Not written
back
back
0
1
X
0
Incremented Fixed
Written back Written back Written back Not written
back
1
0
X
0
Fixed Incremented Written back Written back Not written Written back
back
1
1
X
0
Incremented Incremented Written back Written back Written back Written back
0
X
1
1
Repeat
Fixed
Written back Written back Written back Not written
area
back
1
X
1
1
Incremented Written back Written back Written back Written back
X
0
0
1
Fixed
Repeat
Written back Written back Not written Written back
area
back
X
1
0
1
Incremented
Written back Written back Written back Written back
Remark j = 0 to 23; X: 0 or 1
Number of Clock Cycles 1
2
2
3 2
3 2
3
Table 19 - 9 Number of Clock Cycles Required for One Data Read/Write Operation
Operation
RAM
Code Flash Memory
Data Flash Memory
Special function register (SFR)
Extended special function register (2nd SFR)
No Wait State
Wait States
Data read
1
2
4
1
1
1 + number of
wait cyclesNote
Data write
1
--
--
1
1
1 + number of
wait cyclesNote
Note
The number of wait cycles differs depending on the specifications of the register to be accessed in the extended special function register (2nd SFR) area.
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CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
19.5.6 DTC response time
Table 19 - 10 lists the DTC Response Time. The DTC response time is the time from when the DTC activation source is detected until DTC transfer starts. It does not include the number of DTC execution clock cycles.
Table 19 - 10 DTC Response Time Response Time
Minimum Time 3 cycles
Maximum Time 19 cycles
Note that the response from the DTC may be further delayed under the following cases. The number of delayed clock cycles differs depending on the condition. · When executing an instruction from the internal RAM
Maximum response time: 20 cycles · When executing a DTC pending instruction (refer to 19.5.3 DTC pending instruction)
Maximum response time: Maximum response time for each condition + execution clock cycles for the instruction to be held pending under the condition. · When accessing the TRJ0 register that a wait occurs Maximum response time: Maximum response time for each condition + 1 cycle
Remark 1 cycle: 1/fCLK (fCLK: CPU/peripheral hardware clock)
19.5.7 DTC activation sources
· After inputting a DTC activation source, do not input the same activation source again until DTC transfer is completed. · While a DTC activation source is generated, do not manipulate the DTC activation enable bit corresponding to the
source. · If DTC activation sources conflict, their priority levels are determined in order to select the source for activation when
the CPU acknowledges the DTC transfer. For details on the priority levels of activation sources, refer to 19.3.3 Vector table. · When DTC activation is enabled under either of the following conditions, a DTC transfer is started and an interrupt is generated after completion of the transfer. Therefore, check the monitor flag (CnMON) of the comparator before enabling DTC activation as required (n = 0, 1).
The comparator is set to an interrupt request on one-edge detection (CnEDG = 0), an interrupt request at the rising edge for the comparator (CnEPO = 0), and IVCMP > comparator n reference voltageNote
The comparator is set to an interrupt request on one-edge detection (CnEDG = 0), an interrupt request at the falling edge for the comparator (CnEPO = 1), and IVCMP < comparator n reference voltageNote
Note
n = 0: IVREF0 or internal reference voltage n = 1: IVREF1 or D/A converter output 0
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19.5.8 Operation in standby mode
CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
Status
DTC Operation
HALT mode
OperableNote 1
STOP mode
DTC activation sources can be acceptedNote 3
SNOOZE mode
OperableNotes 2, 4, 5, 6
Note 1. Note 2. Note 3. Note 4.
Note 5.
Note 6.
When the subsystem clock is selected as fCLK, operation is disabled if the RTCLPC bit of the OSMC register is 1. The SNOOZE mode can only be specified when the high-speed on-chip oscillator clock or middle-speed on-chip oscillator clock is selected as fCLK. In the STOP mode, detecting a DTC activation source enables transition to SNOOZE mode and DTC transfer. After completion of transfer, the chip returns to the STOP mode. However, since the code flash memory and the data flash memory are stopped during the SNOOZE mode, the flash memory cannot be set as the transfer source. When a transfer end interrupt from the CSIp in SNOOZE mode is being used as the DTC activation source, use the transfer end interrupt to release the chip from the SNOOZE mode and start processing by the CPU after completion of DTC transfer, or use a chain transfer to make the settings for reception by the CSIp (writing 1 to the STm0 bit, writing 0 to the SWCm bit, setting the SSCm register, and writing 1 to the SSm0 bit) again. When a transfer end interrupt from the UARTq in SNOOZE mode is being used as the DTC activation source, use the transfer end interrupt to release the chip from the SNOOZE mode and start processing by the CPU after completion of DTC transfer, or use a chain transfer to make the settings for reception by the UARTq (writing 1 to the STm1 bit, writing 0 to the SWCm bit, setting the SSCm register, and writing 1 to the SSm1 bit) again. When an A/D conversion end interrupt from the A/D converter in SNOOZE mode is being used as the DTC activation source, use the A/D conversion end interrupt to release the chip from the SNOOZE mode and start processing by the CPU after completion of DTC transfer, or use a chain transfer to make the settings for the SNOOZE mode function of the A/D converter (writing 1 to the AWC bit after having written 0 to it) again.
Caution If the internal RAM is placed in standby mode or shutdown mode (RAMSDMD = 1) by the memory power reduction control register (PSMCR), the internal RAM cannot be set as a DTC transfer source or destination.
Remark 30- to 64-pin products: p = 00; m = 0 80- to 128-pin products: p = 00, 20; m = 0, 1
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CHAPTER 20 LOGIC AND EVENT LINK CONTROLLER (ELCL)
CHAPTER 20 LOGIC AND EVENT LINK CONTROLLER (ELCL)
20.1
Functions of ELCL
The logic and event link controller (ELCL) links signals output by peripheral functions to other specified peripheral functions through internal logic cell blocks, allowing direct communications between peripheral functions without CPU intervention. The ELCL has the following functions.
· Eight event signals selected from among up to 99 signals from peripheral functions can be linked to specified peripheral functions without CPU intervention. The destinations for connection of these eight signals are selected from among up to 29 event input terminals of the specified peripheral functions.
· Event signals from peripheral functions can be input to logic cells (including AND, OR, and EX-OR circuits) to change the link conditions.
· Event signals from peripheral functions can also be input to selectors to specify conditions for activating the selected peripheral functions.
· Event signals from peripheral functions can also be input to flip-flops to link the signals to the selected peripheral functions in synchronization with a selected clock.
20.2
Configuration of ELCL
Figure 20 - 1 shows a block diagram of the ELCL.
Figure 20 - 1 Block Diagram of ELCL
Input signal select registers n (n = 0 to 11) ELISELn4 ELISELn3 ELISELn2 ELISELn1 ELISELn0
Output signal select registers n (n = 0 to 7) ELOSELn3 ELOSELn2 ELOSELn1 ELOSELn0
ELOENCTL Output signal enable register
Peripheral functions (event output side)
Clock Port Interrupt
Event controller (link processor) Logic cell block L1 Logic cell block L2 Logic cell block L3
Peripheral functions (event receiving side)
DTC
Port
Interrupt
......
Input signal selectors 0 to 11
...... Output signal selector Output controller
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Figure 20 - 2 Block Diagram of Logic Cell Block L1
ELISEL0 ELISEL1 ELISEL2 ELISEL3 ELISEL4 ELISEL5 ELISEL6 ELISEL7 ELISEL8 ELISEL9 ELISEL10 ELISEL11
Signal selection block 3 of event link L1
Signal selection block 2 of event link L1
Signal selection block 1 of event link L1
Signal selection block 0 of event link L1 (selection of the signals to be input to the logic cell, selector, and flip-flops 0 and 1)
Event link L1 signal select registers n (n = 0 to 3)
Event link L1 output select registers n (n = 0 to 3)
ELL1SELn3 ELL1SELn2 ELL1SELn1 ELL1SELn0 ELL1SELnZ
ELL1LNKn3 ELL1LNKn2 ELL1LNKn1 ELL1LNKn0
Selector Decoder
Signal selection block 5 of event link L1
Signal selection block 4 of event link L1 (setting or resetting of flip-flops 0 and 1)
Event link L1 signal select registers n (n = 4, 5)
Event link L1 output select registers n (n = 4, 5)
ELL1SELn2 ELL1SELn1 ELL1SELn0 ELL1SELnZ
ELL1LNKn3 ELL1LNKn2 ELL1LNKn1 ELL1LNKn0
Logic cell block L1 control
register (ELL1CTL)
ELL1T101 ELL1T100
0
1
Selector
Logic cell 0
Logic cell block L1 control register (ELL1CTL)
ELL1T111
ELL1T110
0
1
Output signal 0 Output signal 1 Output signal 2 Output signal 3 Output signal 4
Selector
Logic cell 1
Selector
Signal selection block 6 of event link L1 (selection of the clock of flip-flops 0 and 1) Event link L1 signal select register 6
ELL1SEL62 ELL1SEL61 ELL1SEL60 ELL1SEL6Z
Event link L1 output select register 6 ELL1LNK61 ELL1LNK60
Selector
Logic cell block L1 control register ELL1T31EN ELL1T30EN
0
1 Selector
S
R
0
1
Flip-flop 0
S
R
0
1
Flip-flop 1
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Figure 20 - 3 Block Diagram of Logic Cell Block L2
ELISEL0 ELISEL1 ELISEL2 ELISEL3 ELISEL4 ELISEL5 ELISEL6 ELISEL7 ELISEL8 ELISEL9 ELISEL10 ELISEL11 Output signal 0 from logic cell block L1 Output signal 1 from logic cell block L1 Output signal 2 from logic cell block L1 Output signal 3 from logic cell block L1 Output signal 4 from logic cell block L1
Signal selection block 3 of event link L2
Signal selection block 2 of event link L2
Signal selection block 1 of event link L2
Signal selection block 0 of event link L2 (selection of the signals to be input to logic cells 0 and 1, selector, flip-flops, or setting and resetting of flip-flop 0)
Event link L2 signal select registers n (n = 0 to 3)
Event link L2 output select registers n (n = 0 to 3)
ELL2SELn4 ELL2SELn3 ELL2SELn2 ELL2SELn1 ELL2SELn0 ELL2SELnZ ELL2LNKn3 ELL2LNKn2 ELL2LNKn1 ELL2LNKn0
Selector Decoder
Signal selection block 4 of event link L2 (setting of flip-flop 1) Event link L2 signal select register 4
ELL2SEL42 ELL2SEL41 ELL2SEL40 ELL2SEL4Z
Event link L2 output select register 4 ELL2LNK40
Selector
Signal selection block 5 of event link L2 (resetting of flip-flop 1) Event link L2 signal select register 5
ELL2SEL52 ELL2SEL51 ELL2SEL50 ELL2SEL5Z
Event link L2 output select register 5 ELL2LNK50
Selector
Signal selection block 6 of event link L2 (selection of the clock inputs of flip-flops 0 and 1) Event link L2 signal select register 6
ELL2SEL62 ELL2SEL61 ELL2SEL60 ELL2SEL6Z
Event link L2 output select register 6 ELL2LNK61 ELL2LNK60
Logic cell block L2 control
register (ELL2CTL)
ELL2T101 ELL2T100
0
1
Selector
Logic cell 0
Logic cell block L2 control register (ELL2CTL)
ELL2T111
ELL2T110
0
1
Output signal 0 Output signal 1 Output signal 2 Output signal 3 Output signal 4
Selector
Logic cell 1
0 1
Selector
S
R 0 1
Flip-flop 0
S
R 0 1
Flip-flop 1
Selector
Logic cell block L2 control register ELL2T31EN ELL2T30EN
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Figure 20 - 4 Block Diagram of Logic Cell Block L3
ELISEL0 ELISEL1 ELISEL2 ELISEL3 ELISEL4 ELISEL5 ELISEL6 ELISEL7 ELISEL8 ELISEL9 ELISEL10 ELISEL11 Output signal 0 from logic cell block L2 Output signal 1 from logic cell block L2 Output signal 2 from logic cell block L2 Output signal 3 from logic cell block L2 Output signal 4 from logic cell block L2
Signal selection block 3 of event link L3 Signal selection block 2 of event link L3
Signal selection block 1 of event link L3
Signal selection block 0 of event link L3 (selection of the signals to be input to logic cells 0 and 1, selector, and flip-flops, and setting or resetting of flip-flop 0)
Event link L3 signal select registers n (n = 0 to 3)
Event link L3 output select registers n (n = 0 to 3)
ELL3SELn4 ELL3SELn3 ELL3SELn2 ELL3SELn1 ELL3SELn0 ELL3SELnZ ELL3LNKn3 ELL3LNKn2 ELL3LNKn1 ELL3LNKn0
Selector Decoder
Signal selection block 4 of event link L3 (setting of flip-flop 1) Event link L3 signal select register 4
ELL3SEL42 ELL3SEL41 ELL3SEL40 ELL3SEL4Z
Event link L3 output select register 4 ELL3LNK40
Selector
Signal selection block 5 of event link L3 (resetting of flip-flop 1) Event link L3 signal select register 5
ELL3SEL52 ELL3SEL51 ELL3SEL50 ELL3SEL5Z
Event link L3 output select register 5 ELL3LNK50
Selector
Signal selection block 6 of event link L3 (selection of the clock inputs of flip-flops 0 and 1) Event link L3 signal select register 6
ELL3SEL62 ELL3SEL61 ELL3SEL60 ELL3SE6Z
Event link L3 output select register 6 ELL3LNK61 ELL3LNK60
Logic cell block L3 control register (ELL3CTL)
ELL3T101
ELL3T100
0
1
Selector
Logic cell 0
Logic cell block L3 control register (ELL3CTL)
ELL3T111
ELL3T110
0
1
Output signal 0 Output signal 1 Output signal 2 Output signal 3 Output signal 4
Selector
Logic cell 1
0 1
Selector
S
R 0 1
Flip-flop 0
S
R 0 1
Flip-flop 1
Selector
Logic cell block L3 control register
ELL3T31EN ELL3T30EN
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Table 20 - 1 and Table 20 - 2 list the connections in logic cell block L1. The signals to be input to logic cell block L1 are selectable from among the event-output peripheral functions specified in the input signal select registers n (ELISELn) (n = 0 to 11). The event link L1 signal select registers n (ELL1SELn) (n = 0 to 6) can be used to specify the signal to be input to signal selection block n (n = 0 to 6) of event link L1. The event link L1 output select registers n (ELL1LNKn) (n = 0 to 6) can be used to specify the destinations of the signals to be output from the given block. The ELL1CTL register can be used to select the connections to logic cells and enable or stop flip-flops. The signals output from logic cell block L1 can be used as inputs to event-receiving peripheral functions or as inputs to logic cell block L2.
Table 20 - 1 Connections in Logic Cell Block L1 (1)
Signal selection block n of event link L1
Input Signal
Destination of the signal to be output from signal selection block n of event link L1
Signal selection block 0 of event link L1Note 1
· Signals selected by the ELISEL0 to ELISEL11 registers Use the ELL1SEL0 register to select one signal to be input to logic cell block L1 from among the signals selectable by the above registers.
· Logic cell 0 (input 0 or input 1) · Logic cell 1 (input 0 or input 1) · Selector (selection, input 0 or input 1) · Flip-flop 0 (input) · Flip-flop 1 (input) Use the ELL1LNK0 register to select one of the above destinations.
Signal selection block 1 of event link L1Note 1
· Signals selected by the ELISEL0 to ELISEL11 registers Use the ELL1SEL1 register to select one signal to be input to logic cell block L1 from among the signals selectable by the above registers.
· Logic cell 0 (input 0 or input 1) · Logic cell 1 (input 0 or input 1) · Selector (selection, input 0 or input 1) · Flip-flop 0 (input) · Flip-flop 1 (input) Use the ELL1LNK1 register to select one of the above destinations.
Signal selection block 2 of event link L1Note 1
· Signals selected by the ELISEL0 to ELISEL11 registers Use the ELL1SEL2 register to select one signal to be input to logic cell block L1 from among the signals selectable by the above registers.
· Logic cell 0 (input 0 or input 1) · Logic cell 1 (input 0 or input 1) · Selector (selection, input 0 or input 1) · Flip-flop 0 (input) · Flip-flop 1 (input) Use the ELL1LNK2 register to select one of the above destinations.
Signal selection block 3 of event link L1Note 1
· Signals selected by the ELISEL0 to ELISEL11 registers Use the ELL1SEL3 register to select one signal to be input to logic cell block L1 from among the signals selectable by the above registers.
· Logic cell 0 (input 0 or input 1) · Logic cell 1 (input 0 or input 1) · Selector (selection, input 0 or input 1) · Flip-flop 0 (input) · Flip-flop 1 (input) Use the ELL1LNK3 register to select one of the above destinations.
Signal selection block 4 of event link L1Note 2
· Signals selected by the ELISEL6 to ELISEL11 registers Use the ELL1SEL4 register to select one signal to be input to logic cell block L1 from among the signals selectable by the above registers.
· Flip-flop 0 (set or reset) · Flip-flop 1 (set or reset) Use the ELL1LNK4 register to select one of the above destinations.
Signal selection block 5 of event link L1Note 2
· Signals selected by the ELISEL6 to ELISEL11 registers Use the ELL1SEL5 register to select one signal to be input to logic cell block L1 from among the signals selectable by the above registers.
· Flip-flop 0 (set or reset) · Flip-flop 1 (set or reset) Use the ELL1LNK5 register to select one of the above destinations.
Signal selection block 6 of event link L1
· fCLK (fCLK 16 MHz) Use the ELISEL6 to ELISEL11 registers and the ELL1SEL6 register to select fCLK.
· Flip-flop 0 (clock) · Flip-flop 1 (clock) Use the ELL1LNK6 register to select one of the above destinations.
Note 1. Note 2.
Select different destinations for signal selection blocks 0 to 6 of event link L1; do not connect two or more signals to a single destination. Do not connect a single signal to both the set and reset control of flip-flop 0 or 1. Make sure that there is no period during which the signals for set and for reset are both high at the same time.
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Table 20 - 2 Connections in Logic Cell Block L1 (2) Signal output from logic cell block L1
Signal 0 output from logic cell block L1 Signal 1 output from logic cell block L1 Signal 2 output from logic cell block L1 Signal 3 output from logic cell block L1 Signal 4 output from logic cell block L1
Signal source Output from logic cell 0 in logic cell block L1 Output from logic cell 1 in logic cell block L1 Output from the selector in logic cell block L1 Output from flip-flop 0 in logic cell block L1 Output from flip-flop 1 in logic cell block L1
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CHAPTER 20 LOGIC AND EVENT LINK CONTROLLER (ELCL)
Table 20 - 3 and Table 20 - 4 list the connections in logic cell block L2. The signals to be input to logic cell block L2 are selectable from among the event-output peripheral functions specified by the input signal select registers n (ELISELn) (n = 0 to 11) and the signals output from logic cell block L1. The event link L2 output select registers n (ELL1LNKn) (n = 0 to 6) can be used to specify the destinations of the signals to be output from the given block. The ELL2CTL register can be used to select the connections to logic cells and enable or stop flip-flops. The signals output from logic cell block L2 can be used as inputs to event-receiving peripheral functions or as inputs to logic cell block L3.
Table 20 - 3 Connections in Logic Cell Block L2 (1)
Signal selection block n of event link L2
Input Signal
Destination of the signal to be output from signal selection block n of event link L2
Signal selection block 0 of event link L2Notes 1, 2
· Signals selected by the ELISEL0 to ELISEL11 registers · Signals 0 to 4 output from logic cell block L1 Use the ELL2SEL0 register to select one signal to be input to logic cell block L2 from among the signals selectable by the above registers.
· Logic cell 0 (input 0 or input 1) · Logic cell 1 (input 0 or input 1) · Selector (selection, input 0 or input 1) · Flip-flop 0 (input, set, or reset) · Flip-flop 1 (input) Use the ELL2LNK0 register to select one of the above destinations.
Signal selection block 1 of event link L2Notes 1, 2
· Signals selected by the ELISEL0 to ELISEL11 registers · Signals 0 to 4 output from logic cell block L1 Use the ELL2SEL1 register to select one signal to be input to logic cell block L2 from among the signals selectable by the above registers.
· Logic cell 0 (input 0 or input 1) · Logic cell 1 (input 0 or input 1) · Selector (selection, input 0 or input 1) · Flip-flop 0 (input, set, or reset) · Flip-flop 1 (input) Use the ELL2LNK1 register to select one of the above destinations.
Signal selection block 2 of event link L2Notes 1, 2
· Signals selected by the ELISEL0 to ELISEL11 registers · Signals 0 to 4 output from logic cell block L1 Use the ELL2SEL2 register to select one signal to be input to logic cell block L2 from among the signals selectable by the above registers.
· Logic cell 0 (input 0 or input 1) · Logic cell 1 (input 0 or input 1) · Selector (selection, input 0 or input 1) · Flip-flop 0 (input, set, or reset) · Flip-flop 1 (input) Use the ELL2LNK2 register to select one of the above destinations.
Signal selection block 3 of event link L2Notes 1, 2
· Signals selected by the ELISEL0 to ELISEL11 registers · Signals 0 to 4 output from logic cell block L1 Use the ELL2SEL3 register to select one signal to be input to logic cell block L2 from among the signals selectable by the above registers.
· Logic cell 0 (input 0 or input 1) · Logic cell 1 (input 0 or input 1) · Selector (selection, input 0 or input 1) · Flip-flop 0 (input, set, or reset) · Flip-flop 1 (input) Use the ELL2LNK3 register to select one of the above destinations.
Signal selection block 4 of event link L2Note 2
· Signals selected by the ELISEL6 to ELISEL11 registers Use the ELL2SEL4 register to select one signal to be input to logic cell block L2 from among the signals selectable by the above registers.
· Flip-flop 1 (set) Use the ELL2LNK4 register to select one of the above destinations.
Signal selection block 5 of event link L2Note 2
· Signals selected by the ELISEL6 to ELISEL11 registers Use the ELL2SEL5 register to select one signal to be input to logic cell block L2 from among the signals selectable by the above registers.
· Flip-flop 1 (reset) Use the ELL2LNK5 register to select one of the above destinations.
Signal selection block 6 of event link L2
· fCLK (fCLK 16 MHz) Use the ELISEL6 to ELISEL11 registers and the ELL2SEL6 register to select fCLK.
· Flip-flop 0 (clock) · Flip-flop 1 (clock) Use the ELL2LNK6 register to select one of the above destinations.
Note 1. Note 2.
Select different destinations for signal selection blocks 0 to 6 of event link L1; do not connect two or more signals to a single destination. Do not connect a single signal to both the set and reset control of flip-flop 0 or 1. Make sure that there is no period during which the signals for set and for reset are both high at the same time.
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Table 20 - 4 Connections in Logic Cell Block L2 (2) Signal output from logic cell block L2
Signal 0 output from logic cell block L2 Signal 1 output from logic cell block L2 Signal 2 output from logic cell block L2 Signal 3 output from logic cell block L2 Signal 4 output from logic cell block L2
Signal source Output from logic cell 0 in logic cell block L2 Output from logic cell 1 in logic cell block L2 Output from the selector in logic cell block L2 Output from flip-flop 0 in logic cell block L2 Output from flip-flop 1 in logic cell block L2
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CHAPTER 20 LOGIC AND EVENT LINK CONTROLLER (ELCL)
Table 20 - 5 and Table 20 - 6 list the connections in logic cell block L3. The signals to be input to logic cell block L3 are selectable from among the event-output peripheral functions specified in the input signal select registers n (ELISELn) (n = 0 to 11) and the signals output from logic cell block L2. The event link L1 signal select registers n (ELL1SELn) (n = 0 to 6) can be used to specify the signal to be input to signal selection block n (n = 0 to 6) of event link L3. The event link L3 output select registers n (ELL3LNKn) (n = 0 to 6) can be used to specify the destinations of the signals to be output from the given block. The ELL3CTL register can be used to select the connections to logic cells and enable or stop flipflops. The signals output from logic cell block L3 can be used as inputs to event-receiving peripheral functions or as inputs to logic cell block L3.
Table 20 - 5 Connections in Logic Cell Block L3 (1)
Signal selection block n of event link L3
Input Signal
Destination of the signal to be output from signal selection block n of event link L3
Signal selection block 0 of event link L3Notes 1, 2
· Signals selected by the ELISEL0 to ELISEL11 registers · Signals 0 to 4 output from logic cell block L2 Use the ELL3SEL0 register to select one signal to be input to logic cell block L3 from among the signals selectable by the above registers.
· Logic cell 0 (input 0 or input 1) · Logic cell 1 (input 0 or input 1) · Selector (selection, input 0 or input 1) · Flip-flop 0 (input, set, or reset) · Flip-flop 1 (input) Use the ELL3LNK0 register to select one of the above destinations.
Signal selection block 1 of event link L3Notes 1, 2
· Signals selected by the ELISEL0 to ELISEL11 registers · Signals 0 to 4 output from logic cell block L2 Use the ELL3SEL1 register to select one signal to be input to logic cell block L3 from among the signals selectable by the above registers.
· Logic cell 0 (input 0 or input 1) · Logic cell 1 (input 0 or input 1) · Selector (selection, input 0 or input 1) · Flip-flop 0 (input, set, or reset) · Flip-flop 1 (input) Use the ELL3LNK1 register to select one of the above destinations.
Signal selection block 2 of event link L3Notes 1, 2
· Signals selected by the ELISEL0 to ELISEL11 registers · Signals 0 to 4 output from logic cell block L2 Use the ELL3SEL2 register to select one signal to be input to logic cell block L3 from among the signals selectable by the above registers.
· Logic cell 0 (input 0 or input 1) · Logic cell 1 (input 0 or input 1) · Selector (selection, input 0 or input 1) · Flip-flop 0 (input, set, or reset) · Flip-flop 1 (input) Use the ELL3LNK2 register to select one of the above destinations.
Signal selection block 3 of event link L3Notes 1, 2
· Signals selected by the ELISEL0 to ELISEL11 registers · Signals 0 to 4 output from logic cell block L2 Use the ELL3SEL3 register to select one signal to be input to logic cell block 3 from among the signals selectable by the above registers.
· Logic cell 0 (input 0 or input 1) · Logic cell 1 (input 0 or input 1) · Selector (selection, input 0 or input 1) · Flip-flop 0 (input, set, or reset) · Flip-flop 1 (input) Use the ELL3LNK3 register to select one of the above destinations.
Signal selection block 4 of event link L3Note 2
· Signals selected by the ELISEL6 to ELISEL11 registers Use the ELL3SEL4 register to select one signal to be input to logic cell block L3 from among the signals selectable by the above registers.
· Flip-flop 1 (set) Use the ELL3LNK4 register to select one of the above destinations.
Signal selection block 5 of event link L3Note 2
· Signals selected by the ELISEL6 to ELISEL11 registers Use the ELL3SEL5 register to select one signal to be input to logic cell block L3 from among the signals selectable by the above registers.
· Flip-flop 1 (reset) Use the ELL3LNK5 register to select one of the above destinations.
Signal selection block 6 of event link L3
· fCLK (fCLK 16 MHz) Use the ELISEL6 to ELISEL11 registers and the ELL3SEL6 register to select fCLK.
· Flip-flop 0 (clock) · Flip-flop 1 (clock) Use the ELL3LNK6 register to select one of the above destinations.
Note 1. Note 2.
Select different destinations for signal selection blocks 0 to 6 of event link L1; do not connect two or more signals to a single destination. Do not connect a single signal to both the set and reset control of flip-flop 0 or 1. Make sure that there is no period during which the signals for set and for reset are both high at the same time.
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Table 20 - 6 Connections in Logic Cell Block L3 (2) Signal output from logic cell block L3
Signal 0 output from logic cell block L3 Signal 1 output from logic cell block L3 Signal 2 output from logic cell block L3 Signal 3 output from logic cell block L3 Signal 4 output from logic cell block L3
Signal source Output from logic cell 0 in logic cell block L3 Output from logic cell 1 in logic cell block L3 Output from the selector in logic cell block L3 Output from flip-flop 0 in logic cell block L3 Output from flip-flop 1 in logic cell block L3
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20.3
Registers to Control the ELCL
The following registers are used to control the ELCL.
· Input signal select registers n (ELISELn) (n = 0 to 11) · Event link L1 signal select registers n (ELL1SELn) (n = 0 to 3) · Event link L1 signal select registers n (ELL1SELn) (n = 4, 5) · Event link L1 signal select register 6 (ELL1SEL6) · Logic cell block L1 control register (ELL1CTL) · Event link L1 output select registers n (ELL1LNKn) (n = 0 to 3) · Event link L1 output select registers n (ELL1LNKn) (n = 4, 5) · Event link L1 output select register 6 (ELL1LNK6) · Event link L2 signal select registers n (ELL2SELn) (n = 0 to 3) · Event link L2 signal select registers n (ELL2SELn) (n = 4, 5) · Event link L2 signal select register 6 (ELL2SEL6) · Logic cell block L2 control register (ELL2CTL) · Event link L2 output select registers n (ELL2LNKn) (n = 0 to 3) · Event link L2 output select registers n (ELL2LNKn) (n = 4, 5) · Event link L2 output select register 6 (ELL2LNK6) · Event link L3 signal select registers n (ELL3SELn) (n = 0 to 3) · Event link L3 signal select registers n (ELL3SELn) (n = 4, 5) · Event link L3 signal select register 6 (ELL3SEL6) · Logic cell block L3 control register (ELL3CTL) · Event link L3 output select registers n (ELL3LNKn) (n = 0 to 3) · Event link L3 output select registers n (ELL3LNKn) (n = 4, 5) · Event link L3 output select register 6 (ELL3LNK6) · Output signal select registers n (ELOSELn) (n = 0 to 7) · Output signal enable register (ELOENCTL) · Output signal monitor register (ELOMONI)
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CHAPTER 20 LOGIC AND EVENT LINK CONTROLLER (ELCL)
20.3.1 Input signal select registers n (ELISELn) (n = 0 to 11)
These registers are used to select event signals to be input from event-outputting peripheral functions. The event signals selected by these registers are linked to the event-receiving peripheral functions though logic cell blocks L1 to L3. These registers can be set by an 8-bit memory manipulation instruction. The value of each ELISELn register is 00H following a reset.
Figure 20 - 5 Format of Input Signal Select Registers n (ELISELn) (n = 0 to 11)
Address: After reset: R/W:
F0680H (ELISEL0) to F068BH (ELISEL11) 00H R/W
Symbol
7
6
5
4
3
2
1
0
ELISELn
0
0
0
ELISEL n4
ELISEL n3
ELISEL n2
ELISEL n1
ELISEL n0
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ELISELn (n = 0 to 5)
ELISEL n4
ELISEL n3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ELISEL n2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1
1
1
1
ELISEL n1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
0
1
1
ELISEL n0
Event Source
0
Transmit data output from SAU0 channel 0
1
Transmit data output from SAU0 channel 1
0
Serial clock output from SAU0 channel 0
1
Serial clock output from SAU0 channel 1
0
Input pin (P11)
1
Input pin (P50)
0
Serial clock output from UARTA0Note 1
1
Output from TAU0 channel 0
0
Output from TAU0 channel 1
1
Output from TAU0 channel 2
0
Output from TAU0 channel 3
1
Output from TAU0 channel 4
0
Output from TAU0 channel 5
1
Output from TAU0 channel 6
0
Output from TAU0 channel 7
1
Input pin (P10)
0
Input pin (P51)
1
Comparator detection 0
0
Comparator detection 1
1
Transmit data output 0 from UARTA0Note 1
0
Input pin (P12)
1
Input pin 0Note 2
0
Input pin 1Note 2
1
INTC0Note 3
0
INTC1Note 3
1
INTC2Note 3
0
INTC3Note 3
1
Input pin (P137)
0
Output from flip-flop 0 of logic cell block L1 in
the ELCL
1
Output from flip-flop 1 of logic cell block L1 in
the ELCL
0
Output from flip-flop 1 of logic cell block L2 in
the ELCL
1
Output from flip-flop 1 of logic cell block L3 in
the ELCL
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CHAPTER 20 LOGIC AND EVENT LINK CONTROLLER (ELCL)
ELISELn (n = 6 to 11)
ELISEL n4
ELISEL n3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ELISEL n2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
ELISEL n1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
ELISEL n0
Event Source
0
Transmit data output from SAU0 channel 0
1
Transmit data output from SAU0 channel 1
0
Serial clock output from SAU0 channel 0
1
Serial clock output from SAU0 channel 1
0
Input pin (P11)
1
Input pin (P50)
0
Serial clock output from UARTA0Note 1
1
Output from TAU0 channel 0
0
Output from TAU0 channel 1
1
Output from TAU0 channel 2
0
Output from TAU0 channel 3
1
Output from TAU0 channel 4
0
Output from TAU0 channel 5
1
Output from TAU0 channel 6
0
Output from TAU0 channel 7
1
Input pin (P10)
0
Input pin (P51)
1
Comparator detection 0
0
Comparator detection 1
1
Transmit data output 0 from UARTA0Note 1
0
Input pin (P12)
1
INTC4Note 4
0
INTC5Note 4
1
INTC6Note 4
0
INTC7Note 4
1
INTC8Note 4
0
INTC9Note 4
1
fCLK
0
fIHP
1
fIMP
0
fSXP
1
Setting prohibited
Note 1. Only 30- to 128-pin products support this.
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Note 2.
The event sources selected for input pins 0 and 1 depend on which of the ELISELn (n = 0 to 5) registers is being set.
Register
Input Pin 0
Event Source
Input Pin 1
ELISEL0
Input pin (P20)
Input pin (P120)
ELISEL1
Input pin (P21)
Input pin (P121)
ELISEL2
Input pin (P22)
Input pin (P122)
ELISEL3
Input pin (P23)
Input pin (P147)
ELISEL4
Input pin (P30)
Input pin (P00)
ELISEL5
Input pin (P31)
Input pin (P01)
Note 3.
The interrupt sources that are selectable as event sources for INTC0 to INTC3 depend on which of the ELISELn (n = 0 to 5) registers is being set. Use the interrupt request signals as the hardware triggers for eventreceiving peripheral functions.
Register
INTC0
Event Source
INTC1
INTC2
INTC3
ELISEL0
INTP6
INTURE0
INTTM16
INTUT1
INTTM10
ELISEL1
INTP7
INTURE1
INTTM17
INTUR1
INTTM11
ELISEL2
INTP8
INTTM12
INTST3/ INTCSI30/ INTIIC30
INTIICA1
ELISEL3
INTP9
INTSRE3 INTTM13H
INTSR3/ INTCSI31/ INTIIC31
No connection
ELISEL4
INTKR
INTTM14
INTUT0
No connection
ELISEL5
INTTM13
INTTM15
INTUR0
No connection
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Note 4.
The interrupt sources that are selectable as event sources for INTC4 to INTC9 depend on which of the ELISELn (n = 6 to 11) registers is being set. Use the interrupt request signals as the hardware triggers for event-receiving peripheral functions.
Register
INTC4
INTC5
Event Source
INTC6
INTC7
INTC8
INTC9
ELISEL6
INTP0
INTTM00
INTTM06
INTST2/ INTCSI20/ INTIIC20
INTSR1/ INTCSI11/ INTIIC11
INTSMSE
ELISEL7
INTP1
INTTM01 INTITL
INTSR2/ INTCSI21/ INTIIC21
INTSRE1 INTP10 INTTM03H INTCMP0
ELISEL8
INTP2
INTTM02 INTWDTI INTSRE2 INTREMC INTP11
INTTM11H
INTCMP1
ELISEL9
INTP3
INTTM03 INTRTC
INTST0/ INTCSI00/ INTIIC00
INTSR0/ INTCSI01/ INTIIC01
INTCTSUW R
ELISEL10
INTP4
INTTM04
INTTM07
INTSRE0 INTLVI INTTM01H
INTCTSUR D
ELISEL11
INTP5
INTTM05
INTIICA0
INTST1/ INTCSI10/ INTIIC10
INTAD
INTCTSUF N
Caution 1. Be sure to set bits 7 to 5 to 0. Caution 2. Do not change the setting of this register while the output signal enable register (ELOENCTL) is set to
enable the output of a signal.
Remark
fCLK: CPU/peripheral hardware clock frequency fIHP: High-speed on-chip oscillator peripheral clock frequency fIMP: Middle-speed on-chip oscillator peripheral clock frequency fSXP: Low-speed peripheral clock frequency
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CHAPTER 20 LOGIC AND EVENT LINK CONTROLLER (ELCL)
20.3.2 Event link L1 signal select registers n (ELL1SELn) (n = 0 to 3)
These registers are used to select event signals to be linked to the input of the logic cells (pass-through, AND, OR, and EX-OR circuits), selector, and flip-flops in logic cell block L1. Specify an event signal from among those selected by input signal select registers n (ELISELn). These registers can be set by an 8-bit memory manipulation instruction. The value of each ELL1SELn register is 00H following a reset.
Figure 20 - 6 Format of Event Link L1 Signal Select Registers n (ELL1SELn) (n = 0 to 3)
Address: After reset: R/W:
F0690H (ELL1SEL0) to F0693H (ELL1SEL3) 00H R/W
Symbol
7
6
5
4
3
2
1
0
ELL1SELn ELL1SEL nZ
0
0
0
ELL1SEL ELL1SEL ELL1SEL ELL1SEL
n3
n2
n1
n0
ELL1SEL nZ
Control of event signal output level
0
Positive logic output
1
Negative logic output (inverted level)
ELL1SEL ELL1SEL ELL1SEL ELL1SEL
n3
n2
n1
n0
Selection of target signal to be linked
0
0
0
0
No selection (fixed to 0).
0
0
0
1
Signal selected by input signal select register 0 is to be
linked.
0
0
1
0
Signal selected by input signal select register 1 is to be
linked.
0
0
1
1
Signal selected by input signal select register 2 is to be
linked.
0
1
0
0
Signal selected by input signal select register 3 is to be
linked.
0
1
0
1
Signal selected by input signal select register 4 is to be
linked.
0
1
1
0
Signal selected by input signal select register 5 is to be
linked.
0
1
1
1
Signal selected by input signal select register 6 is to be
linked.
1
0
0
0
Signal selected by input signal select register 7 is to be
linked.
1
0
0
1
Signal selected by input signal select register 8 is to be
linked.
1
0
1
0
Signal selected by input signal select register 9 is to be
linked.
1
0
1
1
Signal selected by input signal select register 10 is to be
linked.
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ELL1SEL ELL1SEL ELL1SEL ELL1SEL
n3
n2
n1
n0
Selection of target signal to be linked
1
1
0
0
Signal selected by input signal select register 11 is to be
linked.
Others
Setting prohibited.
Caution 1. Be sure to set bits 6 to 4 to 0.
Caution 2. Do not change the setting of this register while the output signal enable register (ELOENCTL) is set to
enable the output of a signal.
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CHAPTER 20 LOGIC AND EVENT LINK CONTROLLER (ELCL)
20.3.3 Event link L1 signal select registers n (ELL1SELn) (n = 4, 5)
These registers are used to select event signals to be linked to the set control and reset control of the flip-flops in logic cell block L1. Specify an event signal from among those selected by input signal select registers n (ELISELn). These registers can be set by an 8-bit memory manipulation instruction. The value of each ELL1SELn register is 00H following a reset.
Figure 20 - 7 Format of Event Link L1 Signal Select Registers n (ELL1SELn) (n = 4, 5)
Address: After reset: R/W:
F0694H (ELL1SEL4), F0695H (ELL1SEL5) 00H R/W
Symbol
7
6
5
4
3
2
1
0
ELL1SELn ELL1SEL nZ
0
0
0
0
ELL1SEL ELL1SEL ELL1SEL
n2
n1
n0
ELL1SEL nZ
Control of event signal output level
0
Positive logic output
1
Negative logic output (inverted level)
ELL1SEL ELL1SEL ELL1SEL
n2
n1
n0
Selection of target signal to be linked
0
0
0
No selection (fixed to 0).
0
0
1
Signal selected by input signal select register 6 is to be linked.
0
1
0
Signal selected by input signal select register 7 is to be linked.
0
1
1
Signal selected by input signal select register 8 is to be linked.
1
0
0
Signal selected by input signal select register 9 is to be linked.
1
0
1
Signal selected by input signal select register 10 is to be linked.
1
1
0
Signal selected by input signal select register 11 is to be linked.
Others
Setting prohibited.
Caution 1. Be sure to set bits 6 to 3 to 0. Caution 2. Do not change the setting of this register while the output signal enable register (ELOENCTL) is set to
enable the output of a signal.
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CHAPTER 20 LOGIC AND EVENT LINK CONTROLLER (ELCL)
20.3.4 Event link L1 signal select register 6 (ELL1SEL6)
This register is used to select an event signal to be linked to the clock of the flip-flops in logic cell block L1. Specify an event signal from among those selected by input signal select registers n (ELISELn). This register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 20 - 8 Format of Event Link L1 Signal Select Register 6 (ELL1SEL6)
Address: After reset: R/W:
F0696H 00H R/W
Symbol
7
6
5
4
3
2
1
0
ELL1SEL6 ELL1SEL 6Z
0
0
0
0
ELL1SEL ELL1SEL ELL1SEL
62
61
60
ELL1SEL 6Z
Control of event signal output level
0
Positive logic output
1
Negative logic output (inverted level)
ELL1SEL ELL1SEL ELL1SEL
62
61
60
Selection of target signal to be linked
0
0
0
No selection (fixed to 0).
0
0
1
Signal selected by input signal select register 6 is to be linked.
0
1
0
Signal selected by input signal select register 7 is to be linked.
0
1
1
Signal selected by input signal select register 8 is to be linked.
1
0
0
Signal selected by input signal select register 9 is to be linked.
1
0
1
Signal selected by input signal select register 10 is to be linked.
1
1
0
Signal selected by input signal select register11 is to be linked.
Others
Setting prohibited.
Caution 1. Be sure to set bits 6 to 3 to 0. Caution 2. Do not change the setting of this register while the output signal enable register (ELOENCTL) is set to
enable the output of a signal.
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CHAPTER 20 LOGIC AND EVENT LINK CONTROLLER (ELCL)
20.3.5 Logic cell block L1 control register (ELL1CTL)
This register is used to select logic circuits to be used in the logic cells of logic cell block L1. Pass-through, an AND circuit, an OR circuit, or an EX-OR circuit can be selected for each logic cell. This register is also used to enable or stop flip-flops 0 and 1 in logic cell block L1. This register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 20 - 9 Format of Logic Cell Block L1 Control Register (ELL1CTL)
Address: After reset: R/W:
F0697H (ELL1CTL) 00H R/W
Symbol
7
6
5
ELL1CTL ELL1T 31EN
ELL1T 30EN
0
4
3
2
1
0
0
ELL1T 111
ELL1T 110
ELL1T 101
ELL1T 100
ELL1T 31EN
0 1
Selection of enabling or stopping flip-flop 1 in logic cell block L1
The flip-flop is stopped (the flip-flop is in the reset state). The flip-flop is enabled.
ELL1T 30EN
0 1
Selection of enabling or stopping flip-flop 0 in logic cell block L1
The flip-flop is stopped (the flip-flop is in the reset state). The flip-flop is enabled.
ELL1T 111 0 0 1 1
ELL1T 110 0 1 0 1
Selection of the logic circuit to be used in logic cell 1 of logic cell block L1
Pass-through is selected. AND circuit is selected. OR circuit is selected. EX-OR circuit is selected.
ELL1T 101
ELL1T 100
Selection of the logic circuit to be used in logic cell 0 of logic cell block L1
0
0
Pass-through is selected.
0
1
AND circuit is selected.
1
0
OR circuit is selected.
1
1
EX-OR circuit is selected.
Caution 1. Be sure to set bits 5 and 4 to 0. Caution 2. Do not change the setting of this register while the output signal enable register (ELOENCTL) is set to
enable the output of a signal.
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CHAPTER 20 LOGIC AND EVENT LINK CONTROLLER (ELCL)
20.3.6 Event link L1 output select registers n (ELL1LNKn) (n = 0 to 3)
These registers are used to specify the destinations where the event signals selected by event link L1 signal select registers n (ELL1SELn) are to be linked. Select an input of a logic cell (pass-through, AND circuit, OR circuit, or EX-OR circuit), the selector, or a flip-flop in logic cell block L1 as a destination. These registers can be set by an 8-bit memory manipulation instruction. The value of each ELL1LNKn register is 00H following a reset.
Figure 20 - 10 Format of Event Link L1 Output Select Registers n (ELL1LNKn) (n = 0 to 3)
Address: After reset: R/W:
F0698H (ELL1LNK0) to F069BH (ELL1LNK3) 00H R/W
Symbol
7
6
5
4
3
2
1
0
ELL1LNKn
0
0
0
0
ELL1LNK ELL1LNK ELL1LNK ELL1LNK
n3
n2
n1
n0
ELL1LNK ELL1LNK ELL1LNK ELL1LNK
n3
n2
n1
n0
Selection of link destination
0
0
0
0
No link.
0
0
0
1
Linked to input 0 of logic cell 0 in logic cell block L1.
0
0
1
0
Linked to input 1 of logic cell 0 in logic cell block L1.
0
0
1
1
Linked to input 0 of logic cell 1 in logic cell block L1.
0
1
0
0
Linked to input 1 of logic cell 1 in logic cell block L1.
0
1
0
1
Linked to the selection control of the selector in logic cell
block L1.
0
1
1
0
Linked to input 0 of the selector in logic cell block L1.
0
1
1
1
Linked to input 1 of the selector in logic cell block L1.
1
0
0
0
Linked to the input of flip-flop 0 in logic cell block L1.
1
0
0
1
Linked to the input of flip-flop 1 in logic cell block L1.
Others
Setting prohibited.
Caution 1. Be sure to set bits 7 to 4 to 0. Caution 2. Select different destinations for event link L1 signal selection blocks 0 to 6; do not connect two or
more signals to a single destination. Caution 3. Do not change the setting of this register while the output signal enable register (ELOENCTL) is set to
enable the output of a signal.
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CHAPTER 20 LOGIC AND EVENT LINK CONTROLLER (ELCL)
20.3.7 Event link L1 output select registers n (ELL1LNKn) (n = 4, 5)
These registers are used to specify the destinations where the event signals selected by event link L1 signal select registers n (ELL1SELn) are to be linked. The signals can be linked to the set control or reset control of the flip-flops in logic cell block L1. These registers can be set by an 8-bit memory manipulation instruction. The value of each ELL1LNKn register is 00H following a reset.
Figure 20 - 11 Format of Event Link L1 Output Select Registers n (ELL1LNKn) (n = 4, 5)
Address: After reset: R/W:
F069CH (ELL1LNK4), F069DH (ELL1LNK5) 00H R/W
Symbol
7
6
5
4
3
2
1
0
ELL1LNKn
0
0
0
0
ELL1LNK ELL1LNK ELL1LNK ELL1LNK
n3
n2
n1
n0
ELL1LNK n3
Control of the link to flip-flop in logic cell block L1
0
No link.
1
Linked to the reset control of flip-flop 1 in logic cell block L1.
ELL1LNK n2
Control of the link to flip-flop in logic cell block L1
0
No link.
1
Linked to the set control of flip-flop 1 in logic cell block L1.
ELL1LNK n1
Control of the link to flip-flop in logic cell block L1
0
No link.
1
Linked to the reset control of flip-flop 0 in logic cell block L1.
ELL1LNK n0
Control of the link to flip-flop in logic cell block L1
0
No link.
1
Linked to the set control of flip-flop 0 in logic cell block L1.
Caution 1. Be sure to set bits 7 to 4 to 0. Caution 2. Do not connect a single signal to both the set control and reset control of flip-flop 0 or 1. Caution 3. Do not change the setting of this register while the output signal enable register (ELOENCTL) is set to
enable the output of a signal.
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CHAPTER 20 LOGIC AND EVENT LINK CONTROLLER (ELCL)
20.3.8 Event link L1 output select register 6 (ELL1LNK6)
This register is used to specify the destinations where the event signal selected by event link L1 signal select register 6 (ELL1SEL6) is to be linked. The signal can be linked to the clock of the flip-flops in logic cell block L1. This register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 20 - 12 Format of Event Link L1 Output Select Register 6 (ELL1LNK6)
Address: After reset: R/W:
F069EH (ELL1LNK6) 00H R/W
Symbol
7
6
5
4
3
2
1
0
ELL1LNK6
0
0
0
0
0
0
ELL1LNK ELL1LNK
61
60
ELL1LNK 61
Control of the link to flip-flop in logic cell block L1
0
No link.
1
Linked to the clock of flip-flop 1 in logic cell block L1.
ELL1LNK 60
Control of the link to flip-flop in logic cell block L1
0
No link.
1
Linked to the clock of flip-flop 0 in logic cell block L1.
Caution 1. Be sure to set bits 7 to 2 to 0. Caution 2. Do not change the setting of this register while the output signal enable register (ELOENCTL) is set to
enable the output of a signal.
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CHAPTER 20 LOGIC AND EVENT LINK CONTROLLER (ELCL)
20.3.9 Event link L2 signal select registers n (ELL2SELn) (n = 0 to 3)
These registers are used to select event signals to be linked to the input of the logic cells (pass-through, AND, OR, and EX-OR circuits) and selector, and the input, set control, and reset control of the flip-flops in logic cell block L2. Choose one of the event signals selected by input signal select registers n (ELISELn). In addition, the signals output from logic cell block L1 can be selected as event signals. These registers can be set by an 8-bit memory manipulation instruction. The value of each ELL2SELn register is 00H following a reset.
Figure 20 - 13 Format of Event Link L2 Signal Select Registers n (ELL2SELn) (n = 0 to 3)
Address: After reset: R/W:
F06A0H (ELL2SEL0) to F06A3H (ELL2SEL3) 00H R/W
Symbol
7
6
ELL2SELn ELL2SEL nZ
0
5
4
3
2
1
0
0
ELL2SEL ELL2SEL ELL2SEL ELL2SEL ELL2SEL
n4
n3
n2
n1
n0
ELL2SEL nZ
Control of event signal output level
0
Positive logic output
1
Negative logic output (inverted level)
ELL2 ELL2 ELL2 ELL2 ELL2 SELn4 SELn3 SELn2 SELn1 SELn0
Selection of target signal to be linked
0
0
0
0
0 No selection (fixed to 0).
0
0
0
0
1 Signal selected by input signal select register 0 is to be
linked.
0
0
0
1
0 Signal selected by input signal select register 1 is to be
linked.
0
0
0
1
1 Signal selected by input signal select register 2 is to be
linked.
0
0
1
0
0 Signal selected by input signal select register 3 is to be
linked.
0
0
1
0
1 Signal selected by input signal select register 4 is to be
linked.
0
0
1
1
0 Signal selected by input signal select register 5 is to be
linked.
0
0
1
1
1 Signal selected by input signal select register 6 is to be
linked.
0
1
0
0
0 Signal selected by input signal select register 7 is to be
linked.
0
1
0
0
1 Signal selected by input signal select register 8 is to be
linked.
0
1
0
1
0 Signal selected by input signal select register 9 is to be
linked.
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ELL2 ELL2 ELL2 ELL2 ELL2 SELn4 SELn3 SELn2 SELn1 SELn0
Selection of target signal to be linked
0
1
0
1
1 Signal selected by input signal select register 10 is to be
linked.
0
1
1
0
0 Signal selected by input signal select register 11 is to be
linked.
0
1
1
0
1 Output signal 0 from logic cell block L1 is to be linked.
0
1
1
1
0 Output signal 1 from logic cell block L1 is to be linked.
0
1
1
1
1 Output signal 2 from logic cell block L1 is to be linked.
1
0
0
0
0 Output signal 3 from logic cell block L1 is to be linked.
1
0
0
0
1 Output signal 4 from logic cell block L1 is to be linked.
Others
Setting prohibited.
Caution 1. Be sure to set bits 6 and 5 to 0.
Caution 2. Do not change the setting of this register while the output signal enable register (ELOENCTL) is set to
enable the output of a signal.
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20.3.10 Event link L2 signal select registers n (ELL2SELn) (n = 4, 5)
These registers are used to select event signals to be linked to the set control and reset control of the flip-flops in logic cell block L2. Specify an event signal from among those selected by input signal select registers n (ELISELn). These registers can be set by an 8-bit memory manipulation instruction. The value of each ELL2SELn register is 00H following a reset.
Figure 20 - 14 Format of Event Link L2 Signal Select Registers n (ELL2SELn) (n = 4, 5)
Address: After reset: R/W:
F06A4H (ELL2SEL4), F06A5H (ELL2SEL5) 00H R/W
Symbol
7
6
5
4
3
2
1
0
ELL2SELn ELL2SEL nZ
0
0
0
0
ELL2SEL ELL2SEL ELL2SEL
n2
n1
n0
ELL2SEL nZ
Control of event signal output level
0
Positive logic output
1
Negative logic output (inverted level)
ELL2SEL ELL2SEL ELL2SEL
n2
n1
n0
Selection of target signal to be linked
0
0
0
No selection (fixed to 0).
0
0
1
Signal selected by input signal select register 6 is to be linked.
0
1
0
Signal selected by input signal select register 7 is to be linked.
0
1
1
Signal selected by input signal select register 8 is to be linked.
1
0
0
Signal selected by input signal select register 9 is to be linked.
1
0
1
Signal selected by input signal select register 10 is to be linked.
1
1
0
Signal selected by input signal select register 11 is to be linked.
Others
Setting prohibited.
Caution 1. Be sure to set bits 6 to 3 to 0. Caution 2. Do not change the setting of this register while the output signal enable register (ELOENCTL) is set to
enable the output of a signal.
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20.3.11 Event link L2 signal select register 6 (ELL2SEL6)
This register is used to select an event signal to be linked to the clock of the flip-flops in logic cell block L2. Specify an event signal from among those selected by input signal select registers n (ELISELn). This register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 20 - 15 Format of Event Link L2 Signal Select Register 6 (ELL2SEL6)
Address: After reset: R/W:
F06A6H (ELL2SEL6) 00H R/W
Symbol
7
6
5
4
3
2
1
0
ELL2SEL6 ELL2SEL 6Z
0
0
0
0
ELL2SEL ELL2SEL ELL2SEL
62
61
60
ELL2SEL 6Z
Control of event signal output level
0
Positive logic output
1
Negative logic output (inverted level)
ELL2SEL ELL2SEL ELL2SEL
62
61
60
Selection of target signal to be linked
0
0
0
No selection (fixed to 0).
0
0
1
Signal selected by input signal select register 6Note is to be linked.
0
1
0
Signal selected by input signal select register 7Note is to be linked.
0
1
1
Signal selected by input signal select register 8Note is to be linked.
1
0
0
Signal selected by input signal select register 9Note is to be linked.
1
0
1
Signal selected by input signal select register 10Note is to be linked.
1
1
0
Signal selected by input signal select register 11Note is to be linked.
Others
Setting prohibited.
Note
Select a clock signal in the corresponding one of input signal select registers 6 to 11.
Caution 1. Be sure to set bits 6 to 3 to 0. Caution 2. Do not change the setting of this register while the output signal enable register (ELOENCTL) is set to
enable the output of a signal.
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20.3.12 Logic cell block L2 control register (ELL2CTL)
This register is used to select logic circuits to be used in the logic cells of logic cell block L2. Pass-through, an AND circuit, an OR circuit, or an EX-OR circuit can be selected for each logic cell. This register is also used to enable or stop flip-flops 0 and 1 in logic cell block L2. This register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 20 - 16 Format of Logic Cell Block L2 Control Register (ELL2CTL)
Address: After reset: R/W:
F06A7H (ELL2CTL) 00H R/W
Symbol
7
6
5
ELL2CTL ELL2T 31EN
ELL2T 30EN
0
4
3
2
1
0
0
ELL2T 111
ELL2T 110
ELL2T 101
ELL2T 100
ELL2T 31EN
0 1
Selection of enabling or stopping flip-flop 1 in logic cell block L2
The flip-flop is stopped (the flip-flop is in the reset state). The flip-flop is enabled.
ELL2T 30EN
0 1
Selection of enabling or stopping flip-flop 0 in logic cell block L2
The flip-flop is stopped (the flip-flop is in the reset state). The flip-flop is enabled.
ELL2T 111 0 0 1 1
ELL2T 110 0 1 0 1
Selection of the logic circuit to be used in logic cell 1 of logic cell block L2
Pass-through is selected. AND circuit is selected. OR circuit is selected. EX-OR circuit is selected.
ELL2T 101
ELL2T 100
Selection of the logic circuit to be used in logic cell 0 of logic cell block L2
0
0
Pass-through is selected.
0
1
AND circuit is selected.
1
0
OR circuit is selected.
1
1
EX-OR circuit is selected.
Caution 1. Be sure to set bits 5 and 4 to 0. Caution 2. Do not change the setting of this register while the output signal enable register (ELOENCTL) is set to
enable the output of a signal.
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20.3.13 Event link L2 output select registers n (ELL2LNKn) (n = 0 to 3)
These registers are used to specify the destinations where the event signals selected by event link L2 signal select registers n (ELL2SELn) are to be linked. Select an input of a logic cell (pass-through, AND circuit, OR circuit, or EX-OR circuit) or the selector, or the input, set control, or reset control of a flip-flop in logic cell block L2 as a destination. These registers can be set by an 8-bit memory manipulation instruction. The value of each ELL2LNKn register is 00H following a reset.
Figure 20 - 17 Format of Event Link L2 Output Select Registers n (ELL2LNKn) (n = 0 to 3)
Address: After reset: R/W:
F06A8H (ELL2LNK0) to F06ABH (ELL2LNK3) 00H R/W
Symbol
7
6
5
4
3
2
1
0
ELL2LNKn
0
0
0
0
ELL2LNK ELL2LNK ELL2LNK ELL2LNK
n3
n2
n1
n0
ELL2 LNKn3
ELL2 LNKn2
ELL2 LNKn1
ELL2 LNKn0
Selection of link destination
0
0
0
0
No link.
0
0
0
1
Linked to input 0 of logic cell 0 in logic cell block L2.
0
0
1
0
Linked to input 1 of logic cell 0 in logic cell block L2.
0
0
1
1
Linked to input 0 of logic cell 1 in logic cell block L2.
0
1
0
0
Linked to input 1 of logic cell 1 in logic cell block L2.
0
1
0
1
Linked to the selection control of the selector in logic cell
block L2.
0
1
1
0
Linked to input 0 of the selector in logic cell block L2.
0
1
1
1
Linked to input 1 of the selector in logic cell block L2.
1
0
0
0
Linked to the input of flip-flop 0 in logic cell block L2.
1
0
0
1
Linked to the input of flip-flop 1 in logic cell block L2.
1
0
1
0
Linked to the set control of flip-flop 0 in logic cell block L2.
1
0
1
1
Linked to the reset control of flip-flop 0 in logic cell block L2.
Others
Setting prohibited.
Caution 1. Be sure to set bits 7 to 4 to 0. Caution 2. Select different destinations for event link L2 signal selection blocks 0 to 6; do not connect two or
more signals to a single destination. Caution 3. Do not change the setting of this register while the output signal enable register (ELOENCTL) is set to
enable the output of a signal.
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20.3.14 Event link L2 output select registers n (ELL2LNKn) (n = 4, 5)
These registers are used to specify the destinations where the event signals selected by event link L2 signal select registers n (ELL2SELn) are to be linked. The signals can be linked to the set control or reset control of a flip-flop in logic cell block L2. These registers can be set by an 8-bit memory manipulation instruction. The value of each ELL2LNKn register is 00H following a reset.
Figure 20 - 18 Format of Event Link L2 Output Select Registers n (ELL2LNKn) (n = 4, 5)
Address: After reset: R/W:
F06ACH (ELL2LNK4), F06ADH (ELL2LNK5) 00H R/W
Symbol
7
6
5
4
3
2
1
ELL2LNKn
0
0
0
0
0
0
0
ELL2LNK5 register
ELL2LNK 50
Control of the link to flip-flop in logic cell block L2
0
No link.
1
Linked to the reset control of flip-flop 1 in logic cell block L2.
0
ELL2LNK n0
ELL2LNK4 register
ELL2LNK 40
Control of the link to flip-flop in logic cell block L2
0
No link.
1
Linked to the set control of flip-flop 1 in logic cell block L2.
Caution 1. Be sure to set bits 7 to 1 to 0. Caution 2. Do not connect a single signal to both the set control and reset control of flip-flop 0 or 1. Caution 3. Do not change the setting of this register while the output signal enable register (ELOENCTL) is set to
enable the output of a signal.
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20.3.15 Event link L2 output select register 6 (ELL2LNK6)
This register is used to specify the destinations where the event signal selected by event link L2 signal select register 6 (ELL2SEL6) is to be linked. The signal can be linked to the clock of the flip-flops in logic cell block L2. This register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 20 - 19 Format of Event Link L2 Output Select Register 6 (ELL2LNK6)
Address: After reset: R/W:
F06AEH (ELL2LNK6) 00H R/W
Symbol
7
6
5
4
3
2
1
0
ELL2LNK6
0
0
0
0
0
0
ELL2LNK ELL2LNK
61
60
ELL2LNK 61
Control of the link to flip-flop in logic cell block L2
0
No link.
1
Linked to the clock of flip-flop 1 in logic cell block L2.
ELL2LNK 60
Control of the link to flip-flop in logic cell block L2
0
No link.
1
Linked to the clock of flip-flop 0 in logic cell block L2.
Caution 1. Be sure to set bits 7 to 2 to 0. Caution 2. Do not change the setting of this register while the output signal enable register (ELOENCTL) is set to
enable the output of a signal.
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20.3.16 Event link L3 signal select registers n (ELL3SELn) (n = 0 to 3)
These registers are used to select event signals to be linked to the input of the logic cells (pass-through, AND, OR, and EX-OR circuits) and selector, and the input, set control, and reset control of the flip-flops in logic cell block L3. Specify an event signal from among those selected by input signal select registers n (ELISELn). In addition, the signals output from logic cell block L2 can be selected as event signals. These registers can be set by an 8-bit memory manipulation instruction. The value of each ELL3SELn register is 00H following a reset.
Figure 20 - 20 Format of Event Link L3 Signal Select Registers n (ELL3SELn) (n = 0 to 3)
Address: After reset: R/W:
F06B0H (ELL3SEL0) to F06B3H (ELL3SEL3) 00H R/W
Symbol
7
6
ELL3SELn ELL3SEL nZ
0
5
4
3
2
1
0
0
ELL3SEL ELL3SEL ELL3SEL ELL3SEL ELL3SEL
n4
n3
n2
n1
n0
ELL3SELnZ 0 1
Control of event signal output level Positive logic output Negative logic output (inverted level)
ELL3 ELL3 ELL3 ELL3 ELL3 SELn4 SELn3 SELn2 SELn1 SELn0
Selection of target signal to be linked
0
0
0
0
0 No selection (fixed to 0).
0
0
0
0
1 Signal selected by input signal select register 0 is to be
linked.
0
0
0
1
0 Signal selected by input signal select register 1 is to be
linked.
0
0
0
1
1 Signal selected by input signal select register 2 is to be
linked.
0
0
1
0
0 Signal selected by input signal select register 3 is to be
linked.
0
0
1
0
1 Signal selected by input signal select register 4 is to be
linked.
0
0
1
1
0 Signal selected by input signal select register 5 is to be
linked.
0
0
1
1
1 Signal selected by input signal select register 6 is to be
linked.
0
1
0
0
0 Signal selected by input signal select register 7 is to be
linked.
0
1
0
0
1 Signal selected by input signal select register 8 is to be
linked.
0
1
0
1
0 Signal selected by input signal select register 9 is to be
linked.
0
1
0
1
1 Signal selected by input signal select register 10 is to be
linked.
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ELL3 ELL3 ELL3 ELL3 ELL3 SELn4 SELn3 SELn2 SELn1 SELn0
Selection of target signal to be linked
0
1
1
0
0 Signal selected by input signal select register 11 is to be
linked.
0
1
1
0
1 Output signal 0 from logic cell block L2 is to be linked.
0
1
1
1
0 Output signal 1 from logic cell block L2 is to be linked.
0
1
1
1
1 Output signal 2 from logic cell block L2 is to be linked.
1
0
0
0
0 Output signal 3 from logic cell block L2 is to be linked.
1
0
0
0
1 Output signal 4 from logic cell block L2 is to be linked.
Others
Setting prohibited.
Caution 1. Be sure to set bits 6 and 5 to 0.
Caution 2. Do not change the setting of this register while the output signal enable register (ELOENCTL) is set to
enable the output of a signal.
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20.3.17 Event link L3 signal select registers n (ELL3SELn) (n = 4, 5)
These registers are used to select event signals to be linked to the set control and reset control of the flip-flops in logic cell block L3. Specify an event signal from among those selected by input signal select registers n (ELISELn). These registers can be set by an 8-bit memory manipulation instruction. The value of each ELL3SELn register is 00H following a reset.
Figure 20 - 21 Format of Event Link L3 Signal Select Registers n (ELL3SELn) (n = 4, 5)
Address: After reset: R/W:
F06B4H (ELL3SEL4), F06B5H (ELL3SEL5) 00H R/W
Symbol
7
6
5
4
3
2
1
0
ELL3SELn ELL3SEL nZ
0
0
0
0
ELL3SEL ELL3SEL ELL3SEL
n2
n1
n0
ELL3SEL nZ
Control of event signal output level
0
Positive logic output
1
Negative logic output (inverted level)
ELL3SEL ELL3SEL ELL3SEL
n2
n1
n0
Selection of target signal to be linked
0
0
0
No selection (fixed to 0).
0
0
1
Signal selected by input signal select register 6 is to be linked.
0
1
0
Signal selected by input signal select register 7 is to be linked.
0
1
1
Signal selected by input signal select register 8 is to be linked.
1
0
0
Signal selected by input signal select register 9 is to be linked.
1
0
1
Signal selected by input signal select register 10 is to be linked.
1
1
0
Signal selected by input signal select register 11 is to be linked.
Others
Setting prohibited.
Caution 1. Be sure to set bits 6 to 3 to 0. Caution 2. Do not change the setting of this register while the output signal enable register (ELOENCTL) is set to
enable the output of a signal.
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20.3.18 Event link L3 signal select register 6 (ELL3SEL6)
This register is used to select an event signal to be linked to the clock of the flip-flops in logic cell block L3. Specify an event signal from among those selected by input signal select registers n (ELISELn). This register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 20 - 22 Format of Event Link L3 Signal Select Register 6 (ELL3SEL6)
Address: After reset: R/W:
F06B6H (ELL3SEL6) 00H R/W
Symbol
7
6
5
4
3
2
1
0
ELL3SEL6 ELL3SEL 6Z
0
0
0
0
ELL3SEL ELL3SEL ELL3SEL
62
61
60
ELL3SEL 6Z
Control of event signal output level
0
Positive logic output
1
Negative logic output (inverted level)
ELL3SEL ELL3SEL ELL3SEL
62
61
60
Selection of target signal to be linked
0
0
0
No selection (fixed to 0).
0
0
1
Signal selected by input signal select register 6Note is to be linked.
0
1
0
Signal selected by input signal select register 7Note is to be linked.
0
1
1
Signal selected by input signal select register 8Note is to be linked.
1
0
0
Signal selected by input signal select register 9Note is to be linked.
1
0
1
Signal selected by input signal select register 10Note is to be linked.
1
1
0
Signal selected by input signal select register 11Note is to be linked.
1
1
1
No selection (fixed to 0).
Note
Select a clock signal in the corresponding one of input signal select registers 6 to 11.
Caution 1. Be sure to set bits 6 to 3 to 0. Caution 2. Do not change the setting of this register while the output signal enable register (ELOENCTL) is set to
enable the output of a signal.
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20.3.19 Logic cell block L3 control register (ELL3CTL)
This register is used to select logic circuits to be used in the logic cells of logic cell block L3. Pass-through, an AND circuit, an OR circuit, or an EX-OR circuit can be selected for each logic cell. This register is also used to enable or stop flip-flops 0 and 1 in logic cell block L3. This register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 20 - 23 Format of Logic Cell Block L3 Control Register (ELL3CTL)
Address: After reset: R/W:
F06B7H 00H R/W
Symbol
7
6
5
ELL3CTL ELL3T 31EN
ELL3T 30EN
0
4
3
2
1
0
0
ELL3T 111
ELL3T 110
ELL3T 101
ELL3T 100
ELL3T31 EN
Selection of enabling or stopping flip-flop 1 in logic cell block L3
0
The flip-flop is stopped (the flip-flop is in the reset state).
1
The flip-flop is enabled.
ELL3T30 EN
Selection of enabling or stopping flip-flop 0 in logic cell block L3
0
The flip-flop is stopped (the flip-flop is in the reset state).
1
The flip-flop is enabled.
ELL3T 111 0 0 1 1
ELL3T 110 0 1 0 1
Selection of the logic circuit to be used in logic cell 1 of logic cell block L3
Pass-through is selected. AND circuit is selected. OR circuit is selected. EX-OR circuit is selected.
ELL3T 101
ELL3T 100
Selection of the logic circuit to be used in logic cell 0 of logic cell block L3
0
0
Pass-through is selected.
0
1
AND circuit is selected.
1
0
OR circuit is selected.
1
1
EX-OR circuit is selected.
Caution 1. Be sure to set bits 5 and 4 to 0. Caution 2. Do not change the setting of this register while the output signal enable register (ELOENCTL) is set to
enable the output of a signal.
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20.3.20 Event link L3 output select registers n (ELL3LNKn) (n = 0 to 3)
These registers are used to specify the destinations where the event signals selected by event link L3 signal select registers n (ELL3SELn) are to be linked. Select an input of a logic cell (pass-through, AND circuit, OR circuit, or EX-OR circuit) or the selector, or the input, set control, or reset control of a flip-flop in logic cell block L3 as a destination. These registers can be set by an 8-bit memory manipulation instruction. The value of each ELL3LNKn register is 00H following a reset.
Figure 20 - 24 Format of Event Link L3 Output Select Registers n (ELL3LNKn) (n = 0 to 3)
Address: After reset: R/W:
F06B8H (ELL3LNK0) to F06BBH (ELL3LNK3) 00H R/W
Symbol
7
6
5
4
3
2
1
0
ELL3LNKn
0
0
0
0
ELL3LNK ELL3LNK ELL3LNK ELL3LNK
n3
n2
n1
n0
ELL3 LNKn3
ELL3 LNKn2
ELL3 LNKn1
ELL3 LNKn0
Selection of link destination
0
0
0
0
No link.
0
0
0
1
Linked to input 0 of logic cell 0 in logic cell block L3.
0
0
1
0
Linked to input 1 of logic cell 0 in logic cell block L3.
0
0
1
1
Linked to input 0 of logic cell 1 in logic cell block L3.
0
1
0
0
Linked to input 1 of logic cell 1 in logic cell block L3.
0
1
0
1
Linked to the selection control of the selector in logic cell
block L3.
0
1
1
0
Linked to input 0 of the selector in logic cell block L3.
0
1
1
1
Linked to input 1 of the selector in logic cell block L3.
1
0
0
0
Linked to the input of flip-flop 0 in logic cell block L3.
1
0
0
1
Linked to the input of flip-flop 1 in logic cell block L3.
1
0
1
0
Linked to the set control of flip-flop 0 in logic cell block L3.
1
0
1
1
Linked to the reset control of flip-flop 0 in logic cell block L3.
Others
Setting prohibited.
Caution 1. Be sure to set bits 7 to 4 to 0. Caution 2. Select different destinations for event link L3 signal selection blocks 0 to 6; do not connect two or
more signals to a single destination. Caution 3. Do not change the setting of this register while the output signal enable register (ELOENCTL) is set to
enable the output of a signal.
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20.3.21 Event link L3 output select registers n (ELL3LNKn) (n = 4, 5)
These registers are used to specify the destinations where the event signals selected by event link L3 signal select registers n (ELL3SELn) are to be linked. The signals can be linked to the set control or reset control of a flip-flop in logic cell block L3. These registers can be set by an 8-bit memory manipulation instruction. The value of each ELL3LNKn register is 00H following a reset.
Figure 20 - 25 Format of Event Link L3 Output Select Registers n (ELL3LNKn) (n = 4, 5)
Address: After reset: R/W:
F06BCH (ELL3LNK4), F06BDH (ELL3LNK5) 00H R/W
Symbol
7
6
5
4
3
2
1
ELL3LNKn
0
0
0
0
0
0
0
ELL3LNK5 register
ELL3LNK 50
Control of the link to flip-flop in logic cell block L3
0
No link.
1
Linked to the reset control of flip-flop 1 in logic cell block L3.
0
ELL3LNK n0
ELL3LNK4 register
ELL3LNK 40
Control of the link to flip-flop in logic cell block L3
0
No link.
1
Linked to the set control of flip-flop 1 in logic cell block L3.
Caution 1. Be sure to set bits 7 to 1 to 0. Caution 2. Do not connect a single signal to both the set control and reset control of flip-flop 0 or 1. Caution 3. Do not change the setting of this register while the output signal enable register (ELOENCTL) is set to
enable the output of a signal.
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CHAPTER 20 LOGIC AND EVENT LINK CONTROLLER (ELCL)
20.3.22 Event link L3 output select register 6 (ELL3LNK6)
This register is used to specify the destinations where the event signal selected by event link L3 signal select register 6 (ELL3SEL6) is to be linked. The signal can be linked to the clock of the flip-flops in logic cell block L3. This register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 20 - 26 Format of Event Link L3 Output Select Register 6 (ELL3LNK6)
Address: After reset: R/W:
F06BEH (ELL3LNK6) 00H R/W
Symbol
7
6
5
4
3
2
1
0
ELL3LNK6
0
0
0
0
0
0
ELL3LNK ELL3LNK
61
60
ELL3LNK 61
Control of the link to flip-flop in logic cell block L3
0
No link.
1
Linked to the clock of flip-flop 1 in logic cell block L3.
ELL3LNK 60
Control of the link to flip-flop in logic cell block L3
0
No link.
1
Linked to the clock of flip-flop 0 in logic cell block L3.
Caution 1. Be sure to set bits 7 to 2 to 0. Caution 2. Do not change the setting of this register while the output signal enable register (ELOENCTL) is set to
enable the output of a signal.
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CHAPTER 20 LOGIC AND EVENT LINK CONTROLLER (ELCL)
20.3.23 Output signal select registers n (ELOSELn) (n = 0 to 7)
These registers are used to select signals to be output to the event-receiving peripheral functions. Select a signal from among those output from logic cell blocks L1 to L3. These registers can be set by an 8-bit memory manipulation instruction. The value of each ELOSELn register is 00H following a reset.
Figure 20 - 27 Format of Output Signal Select Registers n (ELOSELn) (n = 0 to 7)
Address: After reset: R/W:
F06C0H (ELOSEL0) to F06C7H (ELOSEL7) 00H R/W
Symbol
7
6
5
4
3
2
1
0
ELOSELn ELOSELnZ
0
0
0
ELOSELn3 ELOSELn2 ELOSELn1 ELOSELn0
ELO SELnZ
0 1
Control of output signal level
Positive logic output Negative logic output (inverted level)
ELO SELn3
0 0 0 0 0 0 0 0 1 1 1 1 1
ELO SELn2
0 0 0 0 1 1 1 1 0 0 0 0 1
ELO SELn1
0 0 1 1 0 0 1 1 0 0 1 1 0
ELO SELn0
0 1 0 1 0 1 0 1 0 1 0 1 0
Selection of output signal
No selection. Output signal 0 from logic cell block L1 (output of logic cell 0) is selected. Output signal 1 from logic cell block L1 (output of logic cell 1) is selected. Output signal 2 from logic cell block L1 (output of selector) is selected. Output signal 3 from logic cell block L1 (output of flip-flop 0) is selected. Output signal 4 from logic cell block L1 (output of flip-flop 1) is selected. Output signal 0 from logic cell block L2 (output of logic cell 0) is selected. Output signal 1 from logic cell block L2 (output of logic cell 1) is selected. Output signal 2 from logic cell block L2 (output of selector) is selected. Output signal 3 from logic cell block L2 (output of flip-flop 0) is selected. Output signal 4 from logic cell block L2 (output of flip-flop 1) is selected. Output signal 0 from logic cell block L3 (output of logic cell 0) is selected. Output signal 1 from logic cell block L3 (output of logic cell 1) is selected.
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CHAPTER 20 LOGIC AND EVENT LINK CONTROLLER (ELCL)
ELO SELn3
1
ELO SELn2
1
ELO SELn1
0
ELO SELn0
1
1
1
1
0
1
1
1
1
Caution Be sure to set bits 6 to 4 to 0.
Selection of output signal
Output signal 2 from logic cell block L3 (output of selector) is selected. Output signal 3 from logic cell block L3 (output of flip-flop 0) is selected. Output signal 4 from logic cell block L3 (output of flip-flop 1) is selected.
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CHAPTER 20 LOGIC AND EVENT LINK CONTROLLER (ELCL)
20.3.24 Output signal enable register (ELOENCTL)
This register enables or disables the output of the signals selected by the ELOSELn registers. This register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 20 - 28 Format of Output Signal Enable Register (ELOENCTL)
Address: After reset: R/W:
F06C8H (ELOENCTL) 00H R/W
Symbol ELOENCTL
7
ELOEN CTL7
6
ELOEN CTL6
5
ELOEN CTL5
4
ELOEN CTL4
3
ELOEN CTL3
2
ELOEN CTL2
1
ELOEN CTL1
0
ELOEN CTL0
ELOENC TLn
Enable or disable of the output of signal [n]
0
Output is disabled.
1
Output is enabled.Note
Note
Only make the setting to enable the output of a signal after confirming that the event source signal is in a state which does not affect the operation of the peripheral function at the event destination.
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CHAPTER 20 LOGIC AND EVENT LINK CONTROLLER (ELCL)
Table 20 - 7 shows the correspondence between the bits in the output signal enable register and the event-receiving peripheral functions. Each signal output from the ELCL is connected to multiple destinations. When a destination does not use the signal from the ELCL, make settings in the destination so that the signal from the ELCL is not selected as an input signal for the destination. For the selection of input signals, refer to the chapter of each destination peripheral function.
Table 20 - 7 Bits in Output Signal Enable Register and Event-Receiving Peripheral Functions
Register and Bit Name
Destination 1
Destination 2
Event-Receiving Peripheral Function
Destination 3
Destination 4
Destination 5
Destination 6
ELOENCTL. Output pin (P50) Output pin (P01) Event link
Output pin (P10) --
--
ELOENCTL0
interrupt
(INTELCL)Note 3
ELOENCTL. Output pin (P51) Output pin (P60) DTC activation Output pin (P11) --
--
ELOENCTL1
triggerNote 3
ELOENCTL. Serial clock input Output pin (P61) SMS activation Output pin (P12) --
--
ELOENCTL2 to SAU0 channel
triggerNote 3
0
ELOENCTL. Serial clock input Timer input to
--
Output pin (P13) --
--
ELOENCTL3 to SAU0 channel TAU0
1
channel 0Note 1
ELOENCTL. Receive data
Timer input to
--
Output pin (P14) --
--
ELOENCTL4 input to SAU0
TAU0
channel 0
channel 1Note 1
ELOENCTL. Receive data
--
--
Output pin (P15) Hardware trigger Clock input to
ELOENCTL5 input to SAU0
for A/D converter UARTA (UARTA0,
channel 1
Note 3
UARTA1)Note 2
ELOENCTL. -- ELOENCTL6
Timer input to
--
TAU0 channel 5
Note 1
Output pin (P16)
Hardware trigger for D/A converter 0Note 3
Hardware trigger for CTSUNote 3
ELOENCTL. --
--
--
Output pin (P17) Hardware trigger TML32 operating
ELOENCTL7
for D/A converter clock, capture
1Note 3
triggerNote 3
Note 1.
Note 2. Note 3.
The widths at high and low level of the timer array unit to be linked should be at least 1/fMCK + 10 ns. Accordingly, make the following settings to select an operating clock with a frequency which matches that requirement: use timer clock select register 0 (TPS0) to select the operating clock, and use noise filter enable register 1 (NFEN1) to enable or disable the noise filter. Only supported in the 30- to 128-pin products. In hardware trigger operation, the rising edge is detected as a trigger.
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CHAPTER 20 LOGIC AND EVENT LINK CONTROLLER (ELCL)
20.3.25 Output signal monitor register (ELOMONI)
This register is used to monitor output signals n selected by the ELOSELn registers (n = 0 to 7). Each bit returns the level of the corresponding output signal when this register is read. This register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 20 - 29 Format of Output Signal Monitor Register (ELOMONI)
Address: After reset: R/W:
F06C9H 00H R
Symbol
7
6
5
4
3
2
1
0
ELOMONI ELOMONI7 ELOMONI6 ELOMONI5 ELOMONI4 ELOMONI3 ELOMONI2 ELOMONI1 ELOMONI0
ELOMON In
Level of output signal n
0
The signal level is 0.
1
The signal level is 1.
Caution
Depending on the timing with which this register is read, the value read for output signal n may not be correct. If the value read is incorrect, wait for enough time to confirm the stability of output signal n and then read the register again.
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CHAPTER 20 LOGIC AND EVENT LINK CONTROLLER (ELCL)
20.4
ELCL Operation
The ELCL inputs event signals from peripheral functions to logic cell blocks to convert them to signals that match the desired purpose before sending them to the event-receiving peripheral functions. A logic cell block has logic cells (pass-through, AND, OR, and EX-OR circuits), a selector, and flip-flops. The path for sending an event signal generated by a peripheral function to the interrupt control circuit as an interrupt request is separated from the path for using the signal as an ELCL event. Therefore, the interrupt function settings do not affect the use of an interrupt request signal as an ELCL event signal. For example, an interrupt request signal for which use as a trigger for an interrupt service routing has been disabled by using the corresponding bit of the interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L, MK3H), can still be used as an ELCL event signal. Figure 20 - 30 shows the relationship between interrupt service routing and the ELCL. The figure shows an example of a peripheral function that has an interrupt request status flag and an enable bit for controlling enabling and disabling of the interrupt. A peripheral function that receives an event from the ELCL performs the operation specific to the peripheral function after reception of an event.
Figure 20 - 30 Relationship between Interrupt Service Routing and ELCL
Peripheral function (event output side)
Interrupt request (event signal)
Status flagNote
Interrupt enable control Note
ELCL
Peripheral function (event receiving side)
Interrupt control circuit
CPU
Note
Some peripheral functions do not have status flags or interrupt enable control.
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CHAPTER 20 LOGIC AND EVENT LINK CONTROLLER (ELCL)
20.5
Procedure of Setting the ELCL
Figure 20 - 31 shows a procedure of setting the ELCL. Set up the registers in the ELCL while output by the event-output peripheral functions and reception by the event-receiving peripheral functions are disabled. After enabling output in step 11, enable reception by the event-receiving peripheral functions, and then enable output by the event-output peripheral functions.
Figure 20 - 31 Procedure of Setting the ELCL
Start setting up the ELCL.
1. Disable output and reception by peripheral functions.
2. Set input signal select registers 0 to 11 (ELISELn).
3. Set event link L1 to L3 signal select registers 0 to 3 (ELL1SELn, ELL2SELn, and ELL3SELn).
4. Set event link L1 to L3 signal select registers 4 and 5 (ELL1SELn, ELL2SELn, and ELL3SELn).
5. Set event link L1 to L3 signal select registers 6 (ELL1SEL6, ELL2SEL6, and ELL3SEL6).
6. Set logic cell block L1 to L3 control registers (ELL1CTL, ELL2CTL, and ELL3CTL).
7. Set output select registers 0 to 3 (ELL1LNKn, ELL2LNKn, and ELL3LNKn) for event links L1 to L3.
8. Set event link L1 to L3 output select registers 4 and 5 (ELL1LNKn, ELL2LNKn, and ELL3LNKn).
9. Set event link L1 to L3 output select registers 6 (ELL1LNK6, ELL2LNK6, and ELL3LNK6).
10. Set output signal select registers 0 to 7 (ELOSEL0 to ELOSEL7).
11. Set the output signal enable register (ELOENCTL).
12. Enable reception and output by the selected peripheral modules.
Start of ELCL operations
Disable operation of the event-output peripheral functions or disable output of the signals to the ELCL. Disable operation of the event-receiving peripheral functions or disable input of the signals from the ELCL. Select an event signal from among those from the event-output peripheral functions.
Select the signals to be input from signal selectors 0 to 3 to event links L1 to L3 from among the signals specified in the ELISEL0 to ELISEL11 registers and the output signals from logic cell blocks L2 and L3.
Select the signals to be input from signal selection blocks 4 and 5 to event links L1 to L3 from among the signals specified in the ELISEL6 to ELISEL11 registers.
Select the signal to be input from signal selection block 6 to event links L1 to L3 from among the signals specified in the ELISEL6 to ELISEL11 registers.
Select logic cells and set flip-flop operations.
Specify the destinations for linking of each event signal as a logic cell, selector, or flip-flop.
Specify the destinations for linking of the event signals. The signals can be linked to the set or reset control of flip-flops.
Specify the destinations for linking of the event signals. The signals can be linked to the clock inputs of flip-flops.
Select the signals to be output from the ELCL to the inputs of event-receiving peripheral modules.
Enable or disable the output of the signals selected by the ELOSEL0 to ELOSEL7 registers.
Enable operation of the event-receiving peripheral modules or enable input of the signals from the ELCL. Enable the operation of the event-output peripheral modules or enable output of the signals to the ELCL.
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CHAPTER 20 LOGIC AND EVENT LINK CONTROLLER (ELCL)
(1) Example of ELCL settings (OR circuit) Figure 20 - 32 shows an OR circuit configuration as an example of the result of ELCL settings. Table 20 - 8 is a list of the register settings for this example.
Figure 20 - 32 Example of ELCL Settings (OR Circuit)
ELCL
P50 P01
P51
Table 20 - 8 Example of ELCL Register Settings (OR Circuit)
No. Register Symbol
Register Name
Initial Value
Setting
Description
1 PORT.PMCE0 --
00H
00H
A signal other than the ELCL signal is selected
for output from the P01 pin.
2 ELISEL0
Input signal select register 0
00H
05H
P50 is selected.
2 ELISEL1
Input signal select register 1
00H
10H
P51 is selected.
3 ELL1SEL0
Event link L1 signal select register 0
00H
01H
Input signal selector 0 is selected.
3 ELL1SEL1
Event link L1 signal select register 1
00H
02H
Input signal selector 1 is selected.
6 ELL1CTL
Logic cell block L1 control register
00H
02H
The OR circuit is selected in logic cell 0.
9 ELL1LNK0
Event link L1 output select register 0
00H
01H
Linked to 0 of logic cell block L1.
9 ELL1LNK1
Event link L1 output select register 1
00H
02H
Linked to 1 of logic cell block L1.
10 ELOSEL0
Output signal select register 0
00H
01H
Output signal [0] from logic cell block L1 is
selected.
11 ELOENCTL
Output signal enable register
00H
01H
Output [0] is enabled. The signal is output to
P01.
12 PORT.PMCE0 --
00H
02H
The signal from the ELCL is selected for the
output from the P01 pin.
Caution 1. The numbers in the No. column correspond to the step numbers (1 to 12) in Figure 20 - 31 Procedure of Setting the ELCL.
Caution 2. Steps 2 to 10 can be done in any order, but modifying the register values specified in steps 2 to 10 is prohibited after the output signal enable register is set up in step 11.
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CHAPTER 20 LOGIC AND EVENT LINK CONTROLLER (ELCL)
(2) Example of ELCL settings (AND circuit) Figure 20 - 33 shows an AND circuit configuration as an example of the result of ELCL settings. Table 20 - 9 is a list of the register settings for this example.
Figure 20 - 33 Example of ELCL Settings (AND Circuit)
ELCL
P50 P01
P51
Table 20 - 9 Example of ELCL Register Settings (AND Circuit)
No. Register Symbol
Register Name
Initial Value
Setting
Description
1 PORT.PMCE0 --
00H
00H
A signal other than the ELCL signal is selected
for output from the P01 pin.
2 ELISEL0
Input signal select register 0
00H
05H
P50 is selected.
2 ELISEL1
Input signal select register 1
00H
10H
P51 is selected.
3 ELL1SEL0
Event link L1 signal select register 0
00H
01H
Input signal selector 0 is selected.
3 ELL1SEL1
Event link L1 signal select register 1
00H
02H
Input signal selector 1 is selected.
6 ELL1CTL
Logic cell block L1 control register
00H
01H
The AND circuit is selected in logic cell 0.
9 ELL1LNK0
Event link L1 output select register 0
00H
01H
Linked to 0 of logic cell block L1.
9 ELL1LNK1
Event link L1 output select register 1
00H
02H
Linked to 1 of logic cell block L1.
10 ELOSEL0
Output signal select register 0
00H
01H
Output signal [0] from logic cell block L1 is
selected.
11 ELOENCTL
Output signal enable register
00H
01H
Output [0] is enabled. The signal is output to
P01.
12 PORT.PMCE0 --
00H
02H
The signal from the ELCL is selected for the
output from the P01 pin.
Caution 1. The numbers in the No. column correspond to the step numbers (1 to 12) in Figure 20 - 31 Procedure of Setting the ELCL.
Caution 2. Steps 2 to 10 can be done in any order, but modifying the register values specified in steps 2 to 10 is prohibited after the output signal enable register is set up in step 11.
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CHAPTER 20 LOGIC AND EVENT LINK CONTROLLER (ELCL)
20.6
Points for Caution when the ELCL is to be Used
(1) When the SO00, SO01, SCK00, SCK01, TxDA0, CLKA0, or TO00 to TO07 is to be selected as an input to the ELCL but not for output to a pin, set the corresponding PFOEmn (m = 0, 1, n = 0 to 7) bit in the PFOEm register to 0. For details of the setting, see CHAPTER 4 PORT FUNCTIONS.
(2) Each signal output from the ELCL is linked to multiple peripheral functions as shown in Table 20 - 7. When a destination peripheral function is not to use a signal output from the ELCL, make settings for the destination peripheral function so that the signal from the ELCL is not selected as an input signal at the destination. For details on how to select the signal from the ELCL, refer to the chapters on each of the destination peripheral functions.
(3) Do not change the values of the following registers after output of signals is enabled in the output signal enable register (ELOENCTL). Input signal select registers n (ELISELn) (n = 0 to 11) Event link L1 signal select registers n (ELL1SELn) (n = 0 to 3) Event link L1 signal select registers n (ELL1SELn) (n = 4, 5) Event link L1 signal select register 6 (ELL1SEL6) Logic cell block L1 control register (ELL1CTL) Event link L1 output select registers n (ELL1LNKn) (n = 0 to 3) Event link L1 output select registers n (ELL1LNKn) (n = 4, 5) Event link L1 output select register 6 (ELL1LNK6) Event link L2 signal select registers n (ELL2SELn) (n = 0 to 3) Event link L2 signal select registers n (ELL2SELn) (n = 4, 5) Event link L2 signal select register 6 (ELL2SEL6) Logic cell block L2 control register (ELL2CTL) Event link L2 output select registers n (ELL2LNKn) (n = 0 to 3) Event link L2 output select registers n (ELL2LNKn) (n = 4, 5) Event link L2 output select register 6 (ELL2LNK6) Event link L3 signal select registers n (ELL3SELn) (n = 0 to 3) Event link L3 signal select registers n (ELL3SELn) (n = 4, 5) Event link L3 signal select register 6 (ELL3SEL6) Logic cell block L3 control register (ELL3CTL) Event link L3 output select registers n (ELL3LNKn) (n = 0 to 3) Event link L3 output select registers n (ELL3LNKn) (n = 4, 5) Event link L3 output select register 6 (ELL3LNK6) Output signal select registers n (ELOSELn) (n = 0 to 7)
(4) The ELCL outputs signals with the use of multiple input signals, logic cell blocks, and output controllers. Note that deviations in the timing between these elements may lead to the generation of glitches or expected outputs not being obtained. If an expected output not being obtained may create serious problems for a user system, stop attempting to use the ELCL or employ an external circuit as a workaround.
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CHAPTER 21 INTERRUPT FUNCTIONS
CHAPTER 21 INTERRUPT FUNCTIONS
The interrupt function switches the program execution to other processing. When the branch processing is finished, the program returns to the interrupted processing. The number of interrupt sources differs, depending on the product.
30-pin
Maskable External
6
interrupts
Internal
31
32-pin 6 32
36-pin 6 35
40-pin 7 35
44-pin 7 39
48-pin 10 39
52-pin 12 39
64-pin 13 39
80- and 100-pin
13
44
128-pin 13 48
21.1
Interrupt Function Types
The following two types of interrupt functions are used. (1) Maskable interrupts
These interrupts undergo mask control. Maskable interrupts can be divided into four priority groups by setting the priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR03H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L, PR13H). Multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated. If two or more interrupt requests, each having the same priority, are simultaneously generated, then they are processed according to the default priority of vectored interrupt servicing. For default priority, see Table 21 - 1. A standby release signal is generated and STOP, HALT, and SNOOZE modes are released. External interrupt requests and internal interrupt requests are provided as maskable interrupts. (2) Software interrupt This is a vectored interrupt generated by executing the BRK instruction. It is acknowledged even when interrupts are disabled. The software interrupt does not undergo interrupt priority control.
21.2
Interrupt Sources and Configuration
Interrupt sources include maskable interrupts and a software interrupt. In addition, they also have up to seven reset sources (see Table 21 - 1). The vector codes that store the program start address when branching due to the generation of a reset or various interrupt requests are two bytes each, so interrupts jump to a 64 K address of 00000H to 0FFFFH.
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Table 21 - 1 Interrupt Source List (1/4)
Name
Interrupt Source Trigger
CHAPTER 21 INTERRUPT FUNCTIONS
Internal/External Vector Table Address
Basic Configuration TypeNote 2 128-pin 100-pin 80-pin 64-pin 52-pin 48-pin 44-pin 40-pin 36-pin 32-pin 30-pin
Interrupt Type Default PriorityNote 1
Maskable
0 INTWDTI 1 INTLVI
Watchdog timer interval Note 3 (75% of overflow time + 1/2fIL)
Voltage detection Note 4
Internal 00004H (A) 00006H
2 INTP0
Pin input edge detection
External 00008H (B)
3 INTP1
0000AH
4 INTP2
0000CH
5 INTP3
0000EH
6 INTP4
00010H
7 INTP5
00012H
8 INTST2/ INTCSI20/ INTIIC20
UART2 transmission transfer end or buffer empty interrupt/CSI20 transfer end or buffer empty interrupt/IIC20 transfer end
Internal 00014H (A)
9 INTSR2/ INTCSI21/ INTIIC21
UART2 reception transfer end/CSI21 transfer end or buffer empty interrupt/IIC21 transfer end
00016H
10 INTSRE2 UART2 reception communication error occurrence
00018H
INTTM11H End of timer channel 11 count or capture (at higher 8-bit timer operation)
11 INTELCL Event link interrupt
0001AH
12 INTSMSE Event output from the SNOOZE mode sequencer
0001CH
13 INTST0/ INTCSI00/ INTIIC00
UART0 transmission transfer end or buffer empty interrupt/CSI00 transfer end or buffer empty interrupt/IIC00 transfer end
0001EH
14 INTTM00
End of timer channel 00 count or capture
00020H
15 INTSRE0 UART0 reception communication error occurrence
00022H
INTTM01H End of timer channel 01 count or capture (at higher 8-bit timer operation)
16 INTST1/ INTCSI10/ INTIIC10
UART1 transmission transfer end or buffer empty interrupt/CSI10 transfer end or buffer empty interrupt/IIC10 transfer end
00024H
17 INTSR1/ INTCSI11/ INTIIC11
UART1 reception transfer end/CSI11 transfer end or buffer empty interrupt/IIC11 transfer end
00026H
Note 6 Note 6 Note 6 Note 6 Note 6 Note 6 Note 6
Note 5 Note 5
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Table 21 - 1 Interrupt Source List (2/4)
Name
Interrupt Source Trigger
CHAPTER 21 INTERRUPT FUNCTIONS
Internal/External Vector Table Address
Basic Configuration TypeNote 2 128-pin 100-pin 80-pin 64-pin 52-pin 48-pin 44-pin 40-pin 36-pin 32-pin 30-pin
Maskable Interrupt Type Default PriorityNote 1
18 INTSRE1 UART1 reception communication error occurrence
Internal 00028H (A)
INTTM03H End of timer channel 03 count or capture (at higher 8-bit timer operation)
19 INTIICA0 End of IICA0 communication
0002AH
Note 7 Note 7 Note 7 Note 7 Note 7
20 INTSR0/ INTCSI01/ INTIIC01
UART0 reception transfer end/CSI01 transfer end or buffer empty interrupt/IIC01 transfer end
0002CH
21 INTTM01
End of timer channel 01 count or capture (at 16-bit/lower 8-bit timer operation)
0002EH
22 INTTM02 End of timer channel 02 count or capture
00030H
23 INTTM03
End of timer channel 03 count or capture (at 16-bit/lower 8-bit timer operation)
00032H
24 INTAD
End of A/D conversion
00034H
25 INTRTC
Fixed-cycle signal of realtime clock/alarm match detection
00036H
26 INTITL
Interval signal of 32-bit interval timer detection
00038H
27 INTKR
Key return signal detection
External 0003AH (C)
28 INTST3/ UART3 transmission transfer end or Internal 0003CH (A) INTCSI30/ buffer empty interrupt/CSI30 INTIIC30 transfer end or buffer empty interrupt/IIC30 transfer end
29 INTSR3/ INTCSI31/ INTIIC31
UART3 reception transfer end/CSI31 transfer end or buffer empty interrupt/IIC31 transfer end
0003EH
30 INTTM13
End of timer channel 13 count or capture (at 16-bit/lower 8-bit timer operation)
00040H
31 INTTM04 End of timer channel 04 count or capture
00042H
32 INTTM05 End of timer channel 05 count or capture
00044H
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Table 21 - 1 Interrupt Source List (3/4)
Name
Interrupt Source Trigger
CHAPTER 21 INTERRUPT FUNCTIONS
Maskable Interrupt Type Default PriorityNote 1 Internal/External Vector Table Address Basic Configuration TypeNote 2 128-pin 100-pin 80-pin 64-pin 52-pin 48-pin 44-pin 40-pin 36-pin 32-pin 30-pin
33 INTTM06
End of timer channel 06 count or Internal 00046H (A) capture
34 INTTM07
End of timer channel 07 count or capture
00048H
35 INTP6
Pin input edge detection
External 0004AH (B)
36 INTP7
0004CH
37 INTP8
0004EH
38 INTP9
00050H
39 INTFL
Reserved
00052H
40 INTP10
Pin input edge detection
External 00054H
INTCMP0 Comparator detection 0
Internal
41 INTP11
Pin input edge detection
External 00056H
INTCMP1 Comparator detection 1
Internal
42 INTURE0
UARTA0 reception communication Internal 00058H (A) error occurrence
INTTM10
End of timer channel 10 count or capture
43 INTURE1
UARTA1 reception communication error occurrence
0005AH
INTTM11
End of timer channel 11 count or capture (at 16-bit/lower 8-bit timer operation)
44 INTTM12
End of timer channel 12 count or capture
0005CH
45 INTSRE3
UART3 reception communication error occurrence
0005EH
INTTM13H
End of timer channel 13 count or capture (at higher 8-bit timer operation)
46 INTCTSUWR Request to write to a configuration register of an individual CTSU channel
00060H
47 INTIICA1
End of IICA1 communication
00062H
48 INTCTSURD Request to transfer data measured by the CTSU
00064H
49 INTCTSUFN End of measurement by the CTSU
00066H
50 INTREMC REMC interrupt request
00068H
51 INTUT0
UARTA0 transmission transfer end or buffer empty interrupt
0006AH
52 INTUR0
UARTA0 reception transfer end
0006CH
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Table 21 - 1 Interrupt Source List (4/4)
Name
Interrupt Source Trigger
CHAPTER 21 INTERRUPT FUNCTIONS
Internal/External Vector Table Address
Basic Configuration TypeNote 2 128-pin 100-pin 80-pin 64-pin 52-pin 48-pin 44-pin 40-pin 36-pin 32-pin 30-pin
Maskable Interrupt Type Default PriorityNote 1
Software
53 INTUT1 54 INTUR1 55 INTTM14 56 INTTM15 57 INTTM16 58 INTTM17 BRK
UARTA1 transmission transfer end Internal 0006EH (A) or buffer empty interrupt
UARTA1 reception transfer end
00070H
End of timer channel 14 count or capture
00072H
End of timer channel 15 count or capture
00074H
End of timer channel 16 count or capture
00076H
End of timer channel 17 count or capture
00078H
Execution of BRK instruction
0007EH (D)
RESET
RESET pin input
00000H
POR
Power-on-reset
LVD
Voltage detection
WDT
Overflow of watchdog timer
TRAP
Execution of illegal instruction
IAW
Illegal-memory access
RPE
RAM parity error
Note 1.
Note 2. Note 3. Note 4.
Note 5. Note 6. Note 7.
The default priority determines the sequence of interrupts if two or more maskable interrupts occur simultaneously. Zero indicates the highest priority and 58 indicates the lowest priority. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 21 - 1. When the value of bit 7 (WDTINT) in the option byte (000C0H) is 1. When the value of bit 6 (LVD1SEL) in the voltage detection level register (LVIS) is 0 or the value of bit 7 (LVD0SEL) in the option byte (000C1H) is 1. INTSR2 is only present in this product. INTST1 is only present in this product. INTSR0 is only present in this product.
Reset
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RL78/G23 Figure 21 - 1 Basic Configuration of Interrupt Function (1/2) (A) Internal maskable interrupt
Internal bus
CHAPTER 21 INTERRUPT FUNCTIONS
MK
IE
PR1 PR0 ISP1 ISP0
Interrupt request
IF
(B) External maskable interrupt (INTPn)
External interrupt edge enable register (EGP, EGN)
Priority controller
Vector table address generator
Standby release signal
Internal bus
MK
IE
PR1 PR0
ISP1 ISP0
INTPn pin input
Edge detector
IF
Priority controller
Vector table address generator
Standby release signal
Remark 1. IF:
Interrupt request flag
IE:
Interrupt enable flag
ISP0: In-service priority flag 0
ISP1: In-service priority flag 1
MK: Interrupt mask flag
PR0: Priority specification flag 0
PR1: Priority specification flag 1
Remark 2. 30-, 32-, 36-, 40-, and 44-pin: n = 0 to 5
48-pin:
n = 0 to 6, 8, 9
52-pin:
n = 0 to 6, 8 to 11
64-, 80-, 100-, and 128-pin:
n = 0 to 11
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CHAPTER 21 INTERRUPT FUNCTIONS
Figure 21 - 1 Basic Configuration of Interrupt Function (2/2) (C) External maskable interrupt (INTKR)
Key return mode register (KRM)
Internal bus
MK
IE
PR1 PR 0
ISP1 ISP0
KRn pin input
(D) Software interrupt
Key Interrupt detector
IF
Priority controller
Vector table address generator
Standby release signal
Internal bus
Interrupt request
Remark 1. IF:
Interrupt request flag
IE:
Interrupt enable flag
ISP0: In-service priority flag 0
ISP1: In-service priority flag 1
MK: Interrupt mask flag
PR0: Priority specification flag 0
PR1: Priority specification flag 1
Remark 2. 40- and 44-pin:
n = 0 to 3
48-pin:
n = 0 to 5
52-, 64-, 80-, 100-, and 128-pin: n = 0 to 7
Vector table address generator
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CHAPTER 21 INTERRUPT FUNCTIONS
21.3
Registers to Control the Interrupt Functions
The following registers are used to control the interrupt functions.
· Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L, IF3H) · Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L, MK3H) · Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR03H, PR10L,
PR10H, PR11L, PR11H, PR12L, PR12H, PR13L, PR13H) · External interrupt rising edge enable registers (EGP0, EGP1), External interrupt falling edge enable registers
(EGN0, EGN1) · Program status word (PSW)
Table 21 - 2 shows a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to interrupt request sources.
128-pin 100-pin 80-pin 64-pin 52-pin 48-pin 44-pin 40-pin 36-pin 32-pin 30-pin
Table 21 - 2 Flags Corresponding to Interrupt Request Sources (1/5)
Interrupt Source
Interrupt Request Flag Register
Interrupt Mask Flag Register
Priority Specification Flag Register
INTWDTI INTLVINote
WDTIIF LVIIFNote
IF0L
WDTIMK LVIMKNote
MK0L
WDTIPR0, WDTIPR1 LVIPR0, LVIPR1Note
PR00L, PR10L
INTP0
PIF0
PMK0
PPR00, PPR10
INTP1
PIF1
PMK1
PPR01, PPR11
INTP2
PIF2
PMK2
PPR02, PPR12
INTP3
PIF3
PMK3
PPR03, PPR13
INTP4
PIF4
PMK4
PPR04, PPR14
INTP5
PIF5
PMK5
PPR05, PPR15
Note
The DLVD0F and DLVD1F bits of the LVIM register can be used to confirm which voltage detector has issued the given interrupt, LVD0 or LVD1. For details, see 26.3.1 Voltage detection register (LVIM).
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128-pin 100-pin 80-pin 64-pin 52-pin 48-pin 44-pin 40-pin 36-pin 32-pin 30-pin
Table 21 - 2 Flags Corresponding to Interrupt Request Sources (2/5)
Interrupt Source
Interrupt Request Flag Register
Interrupt Mask Flag Register
Priority Specification Flag Register
INTST2Note 1 STIF2Note 1 IF0H
INTCSI20
Note 1
CSIIF20Note 1
STMK2Note 1
MK0H
CSIMK20Note 1
STPR02, STPR12Note 1
CSIPR020, CSIPR120Note 1
PR00H, PR10H
INTIIC20Note 1 IICIF20Note 1
IICMK20Note 1
IICPR020, IICPR120
Note 1
INTSR2Note 2 SRIF2Note 2
INTCSI21
Note 2
CSIIF21Note 2
INTIIC21Note 2 IICIF21Note 2
SRMK2Note 2 CSIMK21Note 2
IICMK21Note 2
SRPR02, SRPR12Note 2
CSIPR021, CSIPR121Note 2
IICPR021, IICPR121
Note 2
INTSRE2
Note 3
SREIF2Note 3
SREMK2Note 3
SREPR02, SREPR12
Note 3
INTTM11H
Note 3
TMIF11HNote 3
TMMK11HNote 3
TMPR011H,TMPR111H
Note 3
INTELCL
ELCLIF
INTSMSE SMSEIF
INTST0Note 4 STIF0Note 4
INTCSI00
Note 4
CSIIF00Note 4
INTIIC00Note 4 IICIF00Note 4
ELCLMK SMSEMK STMK0Note 4 CSIMK00Note 4
IICMK00Note 4
ELCLPR0, ELCLPR1
SMSEPR0, SMSEPR1
STPR00, STPR10Note 4
CSIPR000, CSIPR100Note 4
IICPR000, IICPR100
Note 4
INTTM00
INTSRE0
Note 5
TMIF00 SREIF0Note 5
TMMK00 SREMK0Note 5
TMPR000, TMPR100
SREPR00, SREPR10
Note 5
INTTM01H
Note 5
TMIF01HNote 5
TMMK01HNote 5
TMPR001H, TMPR101HNote 5
Note 1. Note 2. Note 3.
Note 4. Note 5.
If one of the interrupt sources INTST2, INTCSI20, and INTIIC20 is generated, bit 0 of the IF0H register is set to 1. Bit 0 of the MK0H, PR00H, and PR10H registers supports these three interrupt sources. If one of the interrupt sources INTSR2, INTCSI21, and INTIIC21 is generated, bit 1 of the IF0H register is set to 1. Bit 1 of the MK0H, PR00H, and PR10H registers supports these three interrupt sources. Do not use a UART2 reception error interrupt and an interrupt of channel 1 of TAU1 (at higher 8-bit timer operation) at the same time because they share flags for the interrupt request sources. If the UART2 reception error interrupt is not used (EOC01 = 0), UART2 and channel 1 of TAU1 (at higher 8-bit timer operation) can be used at the same time. If one of the interrupt sources INTSRE2 and INTTM11H is generated, bit 2 of the IF0H register is set to 1. Bit 2 of the MK0H, PR00H, and PR10H registers supports these two interrupt sources. If one of the interrupt sources INTST0, INTCSI00, and INTIIC00 is generated, bit 5 of the IF0H register is set to 1. Bit 5 of the MK0H, PR00H, and PR10H registers supports these three interrupt sources. Do not use a UART0 reception error interrupt and an interrupt of channel 1 of TAU0 (at higher 8-bit timer operation) at the same time because they share flags for the interrupt request sources. If the UART0 reception error interrupt is not used (EOC01 = 0), UART0 and channel 1 of TAU0 (at higher 8-bit timer operation) can be used at the same time. If one of the interrupt sources INTSRE0 and INTTM01H is generated, bit 7 of the IF0H register is set to 1. Bit 7 of the MK0H, PR00H, and PR10H registers supports these two interrupt sources.
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Table 21 - 2 Flags Corresponding to Interrupt Request Sources (3/5)
128-pin 100-pin 80-pin 64-pin 52-pin 48-pin 44-pin 40-pin 36-pin 32-pin 30-pin
Interrupt Source
Interrupt Request Flag Register
Interrupt Mask Flag Register
Priority Specification Flag Register
INTST1Note 1 STIF1Note 1 IF1L
INTCSI10
Note 1
CSIIF10Note 1
STMK1Note 1
MK1L
CSIMK10Note 1
STPR01, STPR11Note 1
CSIPR010,CSIPR110
Note 1
PR01L, PR11L
INTIIC10Note 1 IICIF10Note 1
IICMK10Note 1
IICPR010, IICPR110
Note 1
INTSR1Note 2 SRIF1Note 2
INTCSI11
Note 2
CSIIF11Note 2
SRMK1Note 2 CSIMK11Note 2
SRPR01, SRPR11Note 2
CSIPR011, CSIPR111
Note 2
INTIIC11Note 2 IICIF11Note 2
INTSRE1
Note 3
SREIF1Note 3
IICMK11Note 2 SREMK1Note 3
IICPR011, IICPR111Note 2
SREPR01, SREPR11
Note 3
INTTM03H
Note 3
TMIF03HNote 3
TMMK03HNote 3
TMPR003H,TMPR103H
Note 3
INTIICA0
IICAIF0
INTSR0Note 4 SRIF0Note 4
INTCSI01
Note 4
CSIIF01Note 4
INTIIC01Note 4 IICIF01Note 4
IICAMK0 SRMK0Note 4 CSIMK01Note 4
IICMK01Note 4
IICAPR00, IICAPR10
SRPR00, SRPR10Note 4
CSIPR001, CSIPR101Note 4
IICPR001, IICPR101
Note 4
INTTM01
TMIF01
INTTM02
TMIF02
INTTM03
TMIF03
INTAD
ADIF
IF1H
INTRTC
RTCIF
INTITL
ITLIF
INTKR
KRIF
INTST3Note 5 STIF3Note 5
INTCSI30
Note 5
CSIIF30Note 5
INTIIC30Note 5 IICIF30Note 5
TMMK01
TMMK02
TMMK03
ADMK
MK1H
RTCMK
ITLMK
KRMK
STMK3Note 5 CSIMK30Note 5
IICMK30Note 5
TMPR001, TMPR101
TMPR002, TMPR102
TMPR003, TMPR103
ADPR0, ADPR1 RTCPR0, RTCPR1
PR01H, PR11H
ITLPR0, ITLPR1
KRPR0, KRPR1
STPR03, STPR13Note 5
CSIPR030, CSIPR130Note 5
IICPR030, IICPR130
Note 5
INTSR3Note 6 SRIF3Note 6
INTCSI31
Note 6
CSIIF31Note 6
INTIIC31Note 6 IICIF31Note 6
SRMK3Note 6 CSIMK31Note 6
IICMK31Note 6
SRPR03, SRPR13Note 6
CSIPR031, CSIPR131Note 6
IICPR031, IICPR131
Note 6
INTTM13 INTTM04
TMIF13 TMIF04
TMMK13 TMMK04
TMPR013, TMPR113 TMPR004, TMPR104
Note 1. Note 2. Note 3.
If one of the interrupt sources INTST1, INTCSI10, and INTIIC10 is generated, bit 0 of the IF1L register is set to 1. Bit 0 of the MK1L, PR01L, and PR11L registers supports these three interrupt sources. If one of the interrupt sources INTSR1, INTCSI11, and INTIIC11 is generated, bit 1 of the IF1L register is set to 1. Bit 1 of the MK1L, PR01L, and PR11L registers supports these three interrupt sources. Do not use a UART1 reception error interrupt and an interrupt of channel 3 of TAU0 (at higher 8-bit timer operation) at the same time because they share flags for the interrupt request sources. If the UART1 reception error interrupt is not used (EOC03 = 0), UART1 and channel 3 of TAU0 (at higher 8-bit timer operation) can be used at the same time. If one of the interrupt sources INTSRE1 and INTTM03H is generated, bit 2 of the IF1L register is set to 1. Bit 2 of the MK1L, PR01L, and PR11L registers supports these two interrupt sources.
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CHAPTER 21 INTERRUPT FUNCTIONS
Note 4. Note 5. Note 6.
If one of the interrupt sources INTSR0, INTCSI01, and INTIIC01 is generated, bit 4 of the IF1L register is set to 1. Bit 4 of the MK1L, PR01L, and PR11L registers supports these three interrupt sources. If one of the interrupt sources INTST3, INTCSI30, and INTIIC30 is generated, bit 4 of the IF1H register is set to 1. Bit 4 of the MK1H, PR01H, and PR11H registers supports these three interrupt sources. If one of the interrupt sources INTSR3, INTCSI31, and INTIIC31 is generated, bit 5 of the IF1H register is set to 1. Bit 5 of the MK1H, PR01H, and PR11H registers supports these three interrupt sources.
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CHAPTER 21 INTERRUPT FUNCTIONS
128-pin 100-pin 80-pin 64-pin 52-pin 48-pin 44-pin 40-pin 36-pin 32-pin 30-pin
Table 21 - 2 Flags Corresponding to Interrupt Request Sources (4/5)
Interrupt Source
Interrupt Request Flag Register
Interrupt Mask Flag Register
Priority Specification Flag Register
INTTM05 INTTM06 INTTM07 INTP6 INTP7
TMIF05 TMIF06 TMIF07 PIF6 PIF7
IF2L
TMMK05 TMMK06 TMMK07 PMK6 PMK7
MK2L
TMPR005, TMPR105 TMPR006, TMPR106 TMPR007, TMPR107 PPR06, PPR16 PPR07, PPR17
PR02L, PR12L
INTP8
PIF8
INTP9
PIF9
INTFL
FLIF
INTP10Note 1 PIF10Note 1 IF2H
INTCMP0
Note 1
CMPIF0Note 1
INTP11Note 2 PIF11Note 2
INTCMP1
Note 2
CMPIF1Note 2
INTURE0
Note 3
UREIF0Note 3
INTTM10
Note 3
TMIF10Note 3
INTURE1
Note 4
UREIF1Note 4
PMK8
PMK9
FLMK
PMK10Note 1
MK2H
CMPMK0Note 1
PMK11Note 2 CMPMK1Note 2
UREMK0Note 3
TMMK10Note 3 UREMK1Note 4
PPR08, PPR18
PPR09, PPR19
FLPR0, FLPR1
PPR010, PPR110Note 1
CMPPR00, CMPPR10Note 1
PPR011, PPR111Note 2
PR02H, PR12H
CMPPR01, CMPPR11Note 2
UREPR00, UREPR10Note 3
TMPR010, TMPR110Note 3
UREPR01, UREPR11
Note 4
INTTM11
Note 4
TMIF11Note 4
TMMK11Note 4
TMPR011, TMPR111
Note 4
INTTM12
INTSRE3
Note 5
TMIF12 SREIF3Note 5
INTTM13H
Note 5
TMIF13H
Note 5
INTCTSUWR CTSUWRIF
INTIICA1
IICAIF1
TMMK12 SREMK3Note 5 TMMK13HNote 5 CTSUWRMK IICAMK1
TMPR012, TMPR112
SREPR03, SREPR13Note 5
TMPR013H, TMPR113HNote 5
CTSUWRPR0, CTSUWRPR1
IICAPR01, IICAPR11
Note 1. Note 2. Note 3.
Note 4.
Do not use INTP10 and comparator 0 at the same time because they share the same flag as interrupt request sources. If an interrupt from either the INTP10 or INTCMP0 source is generated, bit 0 of the IF2H register is set to 1. Bit 0 of the MK2H, PR02H, and PR12H registers supports these two interrupt sources. Do not use INTP11 and comparator 1 at the same time because they share the same flag as interrupt request sources. If an interrupt from either the INTP11 or INTCMP1 source is generated, bit 1 of the IF2H register is set to 1. Bit 1 of the MK2H, PR02H, and PR12H registers supports these two interrupt sources. Do not use a UARTA0 reception error interrupt and an interrupt of channel 0 of TAU1 (at lower 8-bit timer operation) at the same time because they share flags for the interrupt request sources. If the UARTA0 reception error interrupt is not used (ISRMA0 = 1), UARTA0 and channel 0 of TAU1 (at lower 8-bit timer operation) can be used at the same time. If one of the interrupt sources INTURE0 and INTTM10 is generated, bit 2 of the IF2H register is set to 1. Bit 2 of the MK2H, PR02H, and PR12H registers supports these two interrupt sources. Do not use a UARTA1 reception error interrupt and an interrupt of channel 1 of TAU1 (at higher 8-bit timer operation) at the same time because they share flags for the interrupt request sources. If the UARTA1 reception error interrupt is not used (ISRMA1 = 1), UARTA1 and channel 1 of TAU1 (at higher 8-bit timer operation) can be used at the same time. If one of the interrupt sources INTURE1 and INTTM11 is generated, bit 3 of the IF2H register is set to 1. Bit 3 of the MK2H, PR02H, and PR12H registers supports these two interrupt sources.
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CHAPTER 21 INTERRUPT FUNCTIONS
Note 5.
Do not use a UART3 reception error interrupt and an interrupt of channel 3 of TAU1 (at higher 8-bit timer operation) at the same time because they share flags for the interrupt request sources. If the UART3 reception error interrupt is not used (EOC03 = 0), UART3 and channel 3 of TAU1 (at higher 8-bit timer operation) can be used at the same time. If one of the interrupt sources INTSRE3 and INTTM13H is generated, bit 4 of the IF2H register is set to 1. Bit 4 of the MK2H, PR02H, and PR12H registers supports these two interrupt sources.
128-pin 100-pin 80-pin 64-pin 52-pin 48-pin 44-pin 40-pin 36-pin 32-pin 30-pin
Table 21 - 2 Flags Corresponding to Interrupt Request Sources (5/5)
Interrupt Source
Interrupt Request Flag Register
Interrupt Mask Flag Register
Priority Specification Flag Register
INTCTSURD CTSURDIF IF3L
CTSURDMK
MK3L
CTSURDPR0, CTSURDPR1
PR03L, PR13L
INTCTSUFN CTSUFNIF
CTSUFNMK
CTSUFNPR0, CTSUFNPR1
INTREMC REMCIF
REMCMK
REMCPR0, REMCPR1
INTUT0
UTIF0
UTMK0
UTPR00, UTPR10
INTUR0
URIF0
URMK0
URPR00, URPR10
INTUT1
UTIF1
UTMK1
UTPR01, UTPR11
INTUR1
URIF1
URMK1
URPR01, URPR11
INTTM14
TMIF14
TMMK14
TMPR014, TMPR114
INTTM15 INTTM16
TMIF15 TMIF16
IF3H
TMMK15 TMMK16
MK3H
TMPR015, TMPR115 TMPR016, TMPR116
PR03H, PR13H
INTTM17
TMIF17
TMMK17
TMPR017, TMPR117
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CHAPTER 21 INTERRUPT FUNCTIONS
21.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L, IF3H)
The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when the given interrupt request is acknowledged, a reset signal is generated, or an instruction is executed. When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is entered. The IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L, and IF3H registers can be set by a 1-bit or 8-bit memory manipulation instruction. When the IF0L and IF0H registers, the IF1L and IF1H registers, the IF2L and IF2H registers, and the IF3L and IF3H registers are combined to form 16-bit registers IF0, IF1, IF2, and IF3, they can be set by a 16-bit memory manipulation instruction. The value of each register is 00H following a reset.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks increases by 2 clocks.
Figure 21 - 2 Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L, IF3H) (1/2)
Address: After reset: R/W:
FFFE0H 00H R/W
Symbol IF0L
<7> PIF5
<6> PIF4
<5> PIF3
<4> PIF2
<3> PIF1
<2> PIF0
<1> LVIIF
<0> WDTIIF
Address: After reset: R/W:
FFFE1H 00H R/W
Symbol IF0H
<7>
SREIF0 TMIF01H
<6> TMIF00
<5>
STIF0 CSIIF00 IICIF00
<4> SMSEIF
<3> ELCLIF
<2>
SREIF2 TMIF11H
<1>
SRIF2 CSIIF21 IICIF21
<0>
STIF2 CSIIF20 IICIF20
Address: After reset: R/W:
FFFE2H 00H R/W
Symbol IF1L
<7> TMIF03
<6> TMIF02
<5> TMIF01
<4>
SRIF0 CSIIF01 IICIF01
<3> IICAIF0
<2>
SREIF1 TMIF03H
<1>
SRIF1 CSIIF11 IICIF11
<0>
STIF1 CSIIF10 IICIF10
Address: After reset: R/W:
FFFE3H 00H R/W
Symbol IF1H
<7> TMIF04
<6> TMIF13
<5>
SRIF3 CSIIF31 IICIF31
<4>
STIF3 CSIIF30 IICIF30
<3> KRIF
<2> ITLIF
<1> RTCIF
<0> ADIF
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CHAPTER 21 INTERRUPT FUNCTIONS
Figure 21 - 2 Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L, IF3H) (2/2)
Address: After reset: R/W:
FFFD0H 00H R/W
Symbol IF2L
<7> FLIF
<6> PIF9
<5> PIF8
<4> PIF7
<3> PIF6
<2> TMIF07
<1> TMIF06
<0> TMIF05
Address: After reset: R/W:
FFFD1H 00H R/W
Symbol IF2H
<7> IICAIF1
<6> CTSUWRIF
<5>
SREIF3 TMIF13H
<4> TMIF12
<3>
UREIF1 TMIF11
<2>
UREIF0 TMIF10
<1>
PIF11 CMPIF1
<0>
PIF10 CMPIF0
Address: After reset: R/W:
FFFD2H 00H R/W
Symbol
<7>
IF3L TMIF14
<6> URIF1
<5> UTIF1
<4> URIF0
<3> UTIF0
<2>
<1>
<0>
REMCIF CTSUFNIF CTSURDIF
Address: After reset: R/W:
FFFD3H 00H R/W
Symbol
7
6
5
4
3
<2>
<1>
<0>
IF3H
0
0
0
0
0
TMIF17
TMIF16
TMIF15
xxIFx
Interrupt request flag
0
No interrupt request signal is generated
1
Indicates the generation of the interrupt request signal and the interrupt request currently
being in the active state.
Caution 1. The available registers and bits differ depending on the product. For details about the registers and bits available for each product, see Table 21 - 2. Be sure to set bits that are not available to the initial value.
Caution 2. When manipulating a flag of the interrupt request flag register, use a 1-bit memory manipulation instruction (CLR1). When describing in C language, use a bit manipulation instruction such as "IF0L.0 = 0;" or "_asm("clr1 IF0L.0");" because the compiled assembler must be a 1-bit memory manipulation instruction (CLR1). If a program is described in C language using an 8-bit memory manipulation instruction such as "IF0L & = 0xfe;" and compiled, it becomes the assembler of three instructions. mov a, IF0L and a, #0FEH mov IF0L, a
In this case, even if the request flag of the another bit of the same interrupt request flag register (IF0L) is set to 1 at the timing between "mov a, IF0L" and "mov IF0L, a", the flag is cleared to 0 at "mov IF0L, a". Therefore, care must be exercised when using an 8-bit memory manipulation instruction in C language.
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CHAPTER 21 INTERRUPT FUNCTIONS
21.3.2
Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L, MK3H)
The interrupt mask flags are used to enable/disable the corresponding maskable interrupt. The MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L, and MK3H registers can be set by a 1-bit or 8-bit memory manipulation instruction. When the MK0L and MK0H registers, the MK1L and MK1H registers, and the MK2L and MK2H registers, and the MK3L and MK3H registers are combined to form 16-bit registers MK0, MK1, MK2, and MK3, they can be set by a 16-bit memory manipulation instruction. The value of each register is FFH following a reset.
Remark
If an instruction that writes data to this register is executed, the number of instruction execution clocks increases by 2 clocks.
Figure 21 - 3 Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L, MK3H) (1/2)
Address: After reset: R/W:
FFFE4H FFH R/W
Symbol MK0L
<7> PMK5
<6> PMK4
<5> PMK3
<4> PMK2
<3> PMK1
<2> PMK0
<1> LVIMK
<0> WDTIMK
Address: After reset: R/W:
FFFE5H FFH R/W
Symbol
<7>
MK0H SREMK0 TMMK01H
<6> TMMK00
<5>
STMK0 CSIMK00 IICMK00
<4> SMSEMK
<3> ELCLMK
<2>
SREMK2 TMMK11H
<1>
SRMK2 CSIMK21 IICMK21
<0>
STMK2 CSIMK20 IICMK20
Address: After reset: R/W:
FFFE6H FFH R/W
Symbol MK1L
<7> TMMK03
<6> TMMK02
<5> TMMK01
<4>
SRMK0 CSIMK01 IICMK01
<3> IICAMK0
<2>
SREMK1 TMMK03H
<1>
SRMK1 CSIMK11 IICMK11
<0>
STMK1 CSIMK10 IICMK10
Address: After reset: R/W:
FFFE7H FFH R/W
Symbol MK1H
<7> TMMK04
<6> TMMK13
<5>
SRMK3 CSIMK31 IICMK31
<4>
STMK3 CSIMK30 IICMK30
<3> KRMK
<2> ITLMK
<1> RTCMK
<0> ADMK
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Figure 21 - 3 Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L, MK3H) (2/2)
Address: After reset: R/W:
FFFD4H FFH R/W
Symbol MK2L
<7> FLMK
<6> PMK9
<5> PMK8
<4> PMK7
<3> PMK6
<2> TMMK07
<1> TMMK06
<0> TMMK05
Address: After reset: R/W:
FFFD5H FFH R/W
Symbol MK2H
<7> IICAMK1
<6>
<5>
CTSUWRM SREMK3
K
TMMK13H
<4> TMMK12
<3>
UREMK1 TMMK11
<2>
UREMK0 TMMK10
<1>
PMK11 CMPMK1
<0>
PMK10 CMPMK0
Address: After reset: R/W:
FFFD6H FFH R/W
Symbol
<7>
MK3L TMMK14
<6> URMK1
<5> UTMK1
<4> URMK0
<3> UTMK0
<2>
<1>
<0>
REMCMK CTSUFNMK CTSURDMK
Address: After reset: R/W:
FFFD7H FFH R/W
Symbol
7
6
5
4
3
<2>
<1>
<0>
MK3H
1
1
1
1
1
TMMK17 TMMK16 TMMK15
xxMKx
Interrupt servicing control
0
Interrupt servicing enabled
1
Interrupt servicing disabled
Caution
The available registers and bits differ depending on the product. For details about the registers and bits available for each product, see Table 21 - 2. Be sure to set bits that are not available to the initial value.
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CHAPTER 21 INTERRUPT FUNCTIONS
21.3.3
Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR03H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L, PR13H)
The priority specification flag registers are used to set the corresponding maskable interrupt priority level. A priority level is set by using the PR0xy and PR1xy registers in combination (xy = 0L, 0H, 1L, 1H, 2L, 2H, 3L, or 3H). The PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR03H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L, and PR13H registers can be set by a 1-bit or 8-bit memory manipulation instruction. If the PR00L and PR00H registers, the PR01L and PR01H registers, the PR02L and PR02H registers, the PR03L and PR03H registers, the PR10L and PR10H registers, the PR11L and PR11H registers, the PR12L and PR12H registers, and the PR13L and PR13H registers are combined to form 16-bit registers PR00, PR01, PR02, PR03, PR10, PR11, PR12, and PR13, they can be set by a 16-bit memory manipulation instruction. The value of each register is FFH following a reset.
Remark
If an instruction that writes data to this register is executed, the number of instruction execution clocks increases by 2 clocks.
Figure 21 - 4 Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR03H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L, PR13H) (1/4)
Address: After reset: R/W:
FFFE8H FFH R/W
Symbol PR00L
<7> PPR05
<6> PPR04
<5> PPR03
<4> PPR02
<3> PPR01
<2> PPR00
<1> LVIPR0
<0> WDTIPR0
Address: After reset: R/W:
FFFECH FFH R/W
Symbol PR10L
<7> PPR15
<6> PPR14
<5> PPR13
<4> PPR12
<3> PPR11
<2> PPR10
<1> LVIPR1
<0> WDTIPR1
Address: After reset: R/W:
FFFE9H FFH R/W
Symbol
<7>
PR00H SREPR00 TMPR001H
<6> TMPR000
<5>
STPR00 CSIPR000 IICPR000
<4> SMSEPR0
<3> ELCLPR0
<2>
SREPR02 TMPR011H
<1>
SRPR02 CSIPR021 IICPR021
<0>
STPR02 CSIPR020 IICPR020
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CHAPTER 21 INTERRUPT FUNCTIONS
Figure 21 - 4 Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR03H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L, PR13H) (2/4)
Address: After reset: R/W:
FFFEDH FFH R/W
Symbol
<7>
PR10H SREPR10 TMPR101H
<6> TMPR100
<5>
STPR10 CSIPR100 IICPR100
<4> SMSEPR1
<3> ELCLPR1
<2>
SREPR12 TMPR111H
<1>
SRPR12 CSIPR121 IICPR121
<0>
STPR12 CSIPR120 IICPR120
Address: After reset: R/W:
FFFEAH FFH R/W
Symbol PR01L
<7> TMPR003
<6> TMPR002
<5> TMPR001
<4>
SRPR00 CSIPR001 IICPR001
<3> IICAPR00
<2>
SREPR01 TMPR003H
<1>
SRPR01 CSIPR011 IICPR011
<0>
STPR01 CSIPR010 IICPR010
Address: After reset: R/W:
FFFEEH FFH R/W
Symbol PR11L
<7> TMPR103
<6> TMPR102
<5> TMPR101
<4>
SRPR10 CSIPR101 IICPR101
<3> IICAPR10
<2>
SREPR11 TMPR103H
<1>
SRPR11 CSIPR111 IICPR111
<0>
STPR11 CSIPR110 IICPR110
Address: After reset: R/W:
FFFEBH FFH R/W
Symbol PR01H
<7> TMPR004
<6> TMPR013
<5>
SRPR03 CSIPR031 IICPR031
<4>
STPR03 CSIPR030 IICPR030
<3> KRPR0
<2> ITLPR0
<1> RTCPR0
<0> ADPR0
Address: After reset: R/W:
FFFEFH FFH R/W
Symbol PR11H
<7> TMPR104
<6> TMPR113
<5>
SRPR13 CSIPR131 IICPR131
<4>
STPR13 CSIPR130 IICPR130
<3> KRPR1
<2> ITLPR1
<1> RTCPR1
<0> ADPR1
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CHAPTER 21 INTERRUPT FUNCTIONS
Figure 21 - 4 Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR03H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L, PR13H) (3/4)
Address: After reset: R/W:
FFFD8H FFH R/W
Symbol PR02L
<7> FLPR0
<6> PPR09
<5> PPR08
<4> PPR07
<3> PPR06
<2>
<1>
<0>
TMPR007 TMPR006 TMPR005
Address: After reset: R/W:
FFFDCH FFH R/W
Symbol PR12L
<7> FLPR1
<6> PPR19
<5> PPR18
<4> PPR17
<3> PPR16
<2>
<1>
<0>
TMPR107 TMPR106 TMPR105
Address: After reset: R/W:
FFFD9H FFH R/W
Symbol
<7>
PR02H IICAPR01
<6>
<5>
CTSUWRP SREPR03
R0
TMPR013H
<4> TMPR012
<3>
UREPR01 TMPR011
<2>
UREPR00 TMPR010
<1>
PPR011 CMPPR01
<0>
PPR010 CMPPR00
Address: After reset: R/W:
FFFDDH FFH R/W
Symbol PR12H
<7> IICAPR11
<6>
<5>
CTSUWRP SREPR13
R1
TMPR113H
<4> TMPR112
<3>
UREPR11 TMPR111
<2>
UREPR10 TMPR110
<1>
PPR111 CMPPR11
<0>
PPR110 CMPPR10
Address: After reset: R/W:
FFFDAH FFH R/W
Symbol
<7>
PR03L TMPR014
<6> URPR01
<5> UTPR01
<4> URPR00
<3> UTPR00
<2>
<1>
<0>
REMCPR0
CTSUFNPR CTSURDPR
0
0
Address: After reset: R/W:
FFFDEH FFH R/W
Symbol
<7>
PR13L TMPR114
<6> URPR11
<5> UTPR11
<4> URPR10
<3> UTPR10
<2>
<1>
<0>
REMCPR1
CTSUFNPR CTSURDPR
1
1
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CHAPTER 21 INTERRUPT FUNCTIONS
Figure 21 - 4 Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR03H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L, PR13H) (4/4)
Address: After reset: R/W:
FFFDBH FFH R/W
Symbol
7
6
5
4
3
<2>
<1>
<0>
PR03H
1
1
1
1
1
TMPR017 TMPR016 TMPR015
Address: After reset: R/W:
FFFDFH FFH R/W
Symbol
7
6
5
4
3
<2>
<1>
<0>
PR13H
1
1
1
1
1
TMPR117 TMPR116 TMPR115
xxPR1x
xxPR0x
Priority level selection
0
0
Specify level 0 (high priority level)
0
1
Specify level 1
1
0
Specify level 2
1
1
Specify level 3 (low priority level)
Caution
The available registers and bits differ depending on the product. For details about the registers and bits available for each product, see Table 21 - 2. Be sure to set bits that are not available to the initial value.
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CHAPTER 21 INTERRUPT FUNCTIONS
21.3.4
External interrupt rising edge enable registers (EGP0, EGP1), External interrupt falling edge enable registers (EGN0, EGN1)
These registers specify the valid edge for INTP0 to INTP11. The EGP0, EGP1, EGN0, and EGN1 registers can be set by a 1-bit or 8-bit memory manipulation instruction. The value of each register is 00H following a reset.
Figure 21 - 5 Format of External Interrupt Rising Edge Enable Registers (EGP0, EGP1) and External Interrupt Falling Edge Enable Registers (EGN0, EGN1)
Address: After reset: R/W:
FFF38H 00H R/W
Symbol EGP0
7 EGP7
6 EGP6
5 EGP5
4 EGP4
3 EGP3
2 EGP2
1 EGP1
0 EGP0
Address: After reset: R/W:
FFF39H 00H R/W
Symbol EGN0
7 EGN7
6 EGN6
5 EGN5
4 EGN4
3 EGN3
2 EGN2
1 EGN1
0 EGN0
Address: After reset: R/W:
FFF3AH 00H R/W
Symbol
7
6
5
4
3
2
1
0
EGP1
0
0
0
0
EGP11
EGP10
EGP9
EGP8
Address: After reset: R/W:
FFF3BH 00H R/W
Symbol
7
6
5
4
3
2
1
EGN1
0
0
0
0
EGN11
EGN10
EGN9
EGPn
EGNn
INTPn pin valid edge selection (n = 0 to 11)
0
0
Edge detection disabled
0
1
Falling edge
1
0
Rising edge
1
1
Both rising and falling edges
Table 21 - 3 shows the ports corresponding to the EGPn and EGNn bits.
0 EGN8
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CHAPTER 21 INTERRUPT FUNCTIONS
Table 21 - 3 Interrupt Request Signals Corresponding to EGPn and EGNn Bits
Detection Enable Bit
Interrupt Request Signal
64-, 80-, 100-, and 128-pin
52-pin
48-pin
30-, 32-, 36-, 40-, and 44-pin
EGP0
EGN0 INTP0
EGP1
EGN1 INTP1
EGP2
EGN2 INTP2
EGP3
EGN3 INTP3
EGP4
EGN4 INTP4
EGP5
EGN5 INTP5
EGP6
EGN6 INTP6
EGP7
EGN7 INTP7
EGP8
EGN8 INTP8
EGP9
EGN9 INTP9
EGP10 EGN10 INTP10
EGP11 EGN11 INTP11
Caution
When the input port pins used for the external interrupt functions are switched to the output mode, the INTPn interrupt might be generated upon detection of a valid edge. When switching the input port pins to the output mode, set the port mode register (PMxx) to 0 after disabling the edge detection (by setting EGPn and EGNn to 0).
Remark 1. For edge detection ports, see 2.1 Functions of Port Pins. Remark 2. n = 0 to 11
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CHAPTER 21 INTERRUPT FUNCTIONS
21.3.5 Program status word (PSW)
The program status word is a register used to hold the instruction execution result and the current state for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP0 and ISP1 flags that control multiple interrupt servicing are mapped to the PSW. Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated instructions (EI and DI). When a vectored interrupt request is acknowledged, if the BRK instruction is executed, the contents of the PSW are automatically saved into a stack and the IE flag is reset to 0. Upon acknowledgment of a maskable interrupt request, if the value of the priority specification flag register of the acknowledged interrupt is not 00, its value minus 1 is transferred to the ISP0 and ISP1 flags. The PSW contents are also saved into the stack with the PUSH PSW instruction. They are restored from the stack with the RETI, RETB, and POP PSW instructions. The value of the PSW is 06H following a reset.
Figure 21 - 6 Configuration of Program Status Word
PSW
<7> <6> <5> <4> <3> <2> <1> 0 IE Z RBS1 AC RBS0 ISP1 ISP0 CY
After a reset 06H
Used when normal instruction is executed
ISP1 ISP0 Priority of interrupt currently being serviced
0
0 Enables interrupts of level 0
(while an interrupt of level 1 or 0 is being serviced ).
0
1 Enables interrupts of levels 0 and 1
(while an interrupt of level 2 is being serviced ).
1
0 Enables interrupts of levels 0 to 2
(while an interrupt of level 3 is being serviced ).
1
1 Enables all interrupts
(waits for acknowledgment of an interrupt).
IE Interrupt request acknowledgment enable/disable 0 Disabled 1 Enabled
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CHAPTER 21 INTERRUPT FUNCTIONS
21.4
Interrupt Servicing Operations
21.4.1 Maskable interrupt request acknowledgment
A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1). However, a low-priority interrupt request is not acknowledged during servicing of a higher priority interrupt request. The times from generation of a maskable interrupt request until vectored interrupt servicing is performed are listed in Table 21 - 4 below. For the interrupt request acknowledgment timing, see Figure 21 - 8 and Figure 21 - 9.
Table 21 - 4 Times from Generation of Maskable Interrupt Request until Servicing
Minimum Time
Maximum TimeNote
Servicing time
9 clocks
16 clocks
Note
Maximum time does not apply when an instruction from the internal RAM area is executed.
Remark 1 clock: 1/fCLK (fCLK: CPU clock)
If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level specified in the priority specification flag is acknowledged first. If two or more interrupt requests have the same priority level, the request with the highest default priority is acknowledged first. An interrupt request that is held pending is acknowledged when it becomes acknowledgeable. Figure 21 - 7 shows the interrupt request acknowledgment algorithm. If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then PC, the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged interrupt are transferred to the ISP1 and ISP0 flags. The vector table data determined for each interrupt request is loaded into the PC and program control branches to the specified servicing. Restoring from an interrupt is possible by using the RETI instruction.
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RL78/G23 Figure 21 - 7 Interrupt Request Acknowledgment Processing Algorithm
CHAPTER 21 INTERRUPT FUNCTIONS
Start
No
xxIF = 1?
Yes (interrupt request generation)
xxMK = 0?
No
Yes
Interrupt request held pending
(xxPR1, xxPR0) (ISP1, ISP0)
No (low priority)
Yes (high priority)
Interrupt request held pending
Is priority higher than other interrupt requests
simultaneously generated?
Yes
No
Interrupt request held pending
Is default priority Note higher than other interrupt requests with the
same priority simultaneously
generated?
Yes
No
Interrupt request held pending
IE = 1?
No
Yes
Vectored interrupt servicing
Interrupt request held pending
Note
For the default priority, refer to Table 21 - 1 Interrupt Source List.
Remark
xxIF:
Interrupt request flag
xxMK:
Interrupt mask flag
xxPR0:
Priority specification flag 0
xxPR1:
Priority specification flag 1
IE:
Flag that controls acknowledgment of maskable interrupt request (1 = Enable, 0 = Disable)
ISP0, ISP1: Flags that indicate the priority level of the interrupt currently being serviced (see Figure 21 - 6)
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CHAPTER 21 INTERRUPT FUNCTIONS
Figure 21 - 8 Interrupt Request Acknowledgment Timing (Minimum Time)
CPU processing
Instruction
Instruction
6 clocks
PSW and PC saved, Instruction jump to interrupt
servicing
Interrupt servicing program
xxIF
Remark 1 clock: 1/fCLK (fCLK: CPU clock)
9 clocks
Figure 21 - 9 Interrupt Request Acknowledgment Timing (Maximum Time)
CPU processing
Instruction
xxIF
Instruction
Remark 1 clock: 1/fCLK (fCLK: CPU clock)
8 clocks
Previous interrupt instruction
6 clocks
PSW and PC saved, jump to interrupt servicing
Interrupt servicing program
16 clocks
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CHAPTER 21 INTERRUPT FUNCTIONS
21.4.2 Software interrupt request acknowledgment
A software interrupt request is acknowledged by BRK instruction execution. Software interrupts cannot be disabled. If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (PSW), then program counter (PC), the IE flag is reset (0), the contents of the vector table (0007EH, 0007FH) are loaded into the PC, and program control branches to the specified servicing. Restoring from a software interrupt is possible by using the RETB instruction.
Caution The RETI instruction cannot be used for restoring from the software interrupt.
21.4.3 Multiple interrupt servicing
Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected (IE = 1). When an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (IE = 0). Therefore, to enable multiple interrupt servicing, it is necessary to set the IE flag to 1 with the EI instruction during interrupt servicing to enable interrupt acknowledgment. Moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to interrupt priority control. Two types of priority control are available: default priority control and programmable priority control. Programmable priority control is used for multiple interrupt servicing. In the interrupt enabled state, if an interrupt request with a priority higher than that of the interrupt currently being serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority equal to or lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple interrupt servicing. However, when setting the IE flag to 1 during the interruption at level 0, other level 0 interruptions can be allowed. Interrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have a lower priority are held pending. When servicing of the current interrupt ends, the pending interrupt request is acknowledged following execution of at least one main processing instruction. Table 21 - 5 shows relationship between interrupt requests enabled for multiple interrupt servicing and Figure 21 - 10 shows multiple interrupt servicing examples.
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Table 21 - 5 Relationship between Interrupt Requests Enabled for Multiple Interrupt Servicing during Interrupt Servicing
Multiple Interrupt Request Maskable Interrupt
Priority Level 0 (PR = 00)
IE = 1 IE = 0
Maskable Interrupt Request
Priority Level 1 Priority Level 2
(PR = 01)
(PR = 10)
IE = 1 IE = 0 IE = 1 IE = 0
Priority Level 3 (PR = 11)
IE = 1 IE = 0
Software Interrupt Request
Processing in progress ISP1 = 0
ISP0 = 0
ISP1 = 0
ISP0 = 1
ISP1 = 1
ISP0 = 0
Waiting for reception ISP1 = 1
ISP0 = 1
Remark 1. : Multiple interrupt servicing enabled Remark 2. : Multiple interrupt servicing disabled Remark 3. ISP0, ISP1, and IE are flags contained in the PSW.
ISP1 = 0, ISP0 = 0: An interrupt of level 1 or level 0 is being serviced. ISP1 = 0, ISP0 = 1: An interrupt of level 2 is being serviced. ISP1 = 1, ISP0 = 0: An interrupt of level 3 is being serviced. ISP1 = 1, ISP0 = 1: Wait for an interrupt acknowledgment (all interrupts are enabled). IE = 0: Interrupt request acknowledgment is disabled. IE = 1: Interrupt request acknowledgment is enabled. Remark 4. PR is a flag contained in the PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR03H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L, and PR13H registers. PR = 00: Specify level 0 with xxPR1x = 0, xxPR0x = 0 (higher priority level) PR = 01: Specify level 1 with xxPR1x = 0, xxPR0x = 1 PR = 10: Specify level 2 with xxPR1x = 1, xxPR0x = 0 PR = 11: Specify level 3 with xxPR1x = 1, xxPR0x = 1 (lower priority level)
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Figure 21 - 10 Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice
Main processing
INTxx servicing
INTyy servicing
INTzz servicing
EI
INTxx (PR = 11)
IE = 0 EI
INTyy (PR = 10)
IE = 0 EI
INTzz (PR = 01)
IE = 0 RETI
IE = 1
RETI
IE = 1
RETI
IE = 1
During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple interrupt servicing takes place. Before each interrupt request is acknowledged, the EI instruction must always be issued to enable interrupt request acknowledgment.
Example 2. Multiple interrupt servicing does not occur due to priority control
Main processing
INTxx servicing
INTyy servicing
EI
IE = 0
EI
INTxx (PR = 10)
INTyy (PR = 11)
RETI
IE = 1
1 instruction execution
IE = 0
IE = 1
RETI
Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower than that of INTxx, and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction.
PR = 00: Specify level 0 with xxPR1x = 0, xxPR0x = 0 (higher priority level) PR = 01: Specify level 1 with xxPR1x = 0, xxPR0x = 1 PR = 10: Specify level 2 with xxPR1x = 1, xxPR0x = 0 PR = 11: Specify level 3 with xxPR1x = 1, xxPR0x = 1 (lower priority level) IE = 0: Interrupt request acknowledgment is disabled. IE = 1: Interrupt request acknowledgment is enabled.
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Figure 21 - 10 Examples of Multiple Interrupt Servicing (2/2)
Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled
Main processing
INTxx servicing INTyy servicing
EI
INTxx (PR = 11)
IE = 0
INTyy (PR = 00)
RETI
IE = 1
1 instruction execution
IE = 0
IE = 1
RETI
Interrupts are not enabled during servicing of interrupt INTxx (EI instruction is not issued), therefore, interrupt request INTyy is not acknowledged and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction.
PR = 00: Specify level 0 with xxPR1x = 0, xxPR0x = 0 (higher priority level) PR = 01: Specify level 1 with xxPR1x = 0, xxPR0x = 1 PR = 10: Specify level 2 with xxPR1x = 1, xxPR0x = 0 PR = 11: Specify level 3 with xxPR1x = 1, xxPR0x = 1 (lower priority level) IE = 0: Interrupt request acknowledgment is disabled IE = 1: Interrupt request acknowledgment is enabled.
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21.4.4 Interrupt request held pending
There are instructions where, even if an interrupt request is issued while the instructions are being executed, interrupt request acknowledgment is held pending until the end of execution of the next instruction. These instructions (instructions that hold interrupt requests pending) are listed below.
· MOV PSW, #byte · MOV PSW, A · MOV1 PSW. bit, CY · SET1 PSW. bit · CLR1 PSW. bit · RETB · RETI · POP PSW · BTCLR PSW. bit, $addr20 · EI · DI · SKC · SKNC · SKZ · SKNZ · SKH · SKNH · Write instructions for the IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L, IF3H, MK0L, MK0H, MK1L, MK1H, MK2L,
MK2H, MK3L, MK3H, PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR03H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L, and PR13H registers
Figure 21 - 11 shows the timing at which interrupt requests are held pending.
Figure 21 - 11 Holding Interrupt Requests Pending
CPU processing xxIF
Instruction N
Instruction M
PSW and PC saved, jump to interrupt servicing
Interrupt servicing program
Remark 1. Instruction N: Instruction to hold interrupt requests pending Remark 2. Instruction M: Instruction other than the instruction to hold interrupt requests pending
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CHAPTER 22 KEY INTERRUPT FUNCTION
CHAPTER 22 KEY INTERRUPT FUNCTION
The number of key interrupt input channels differs, depending on the product.
Number of the key interrupt input channels
30-, 32-, and 36-pin products
--
40- and 44-pin products 4
48-pin products 6
52-, 64-, 80-, 100-, and 128-pin products
8
22.1
Functions of the Key Interrupt
A key interrupt (INTKR) can be generated by inputting a rising edge/falling edge to the key interrupt input pins (KR0 to KR7).
Table 22 - 1 Assignment of the Key Interrupt Detection Pins
Key interrupt pins
Key return mode register 0 (KRM0)
KR0
KRM00
KR1
KRM01
KR2
KRM02
KR3
KRM03
KR4
KRM04
KR5
KRM05
KR6
KRM06
KR7
KRM07
Remark
Pins KR0 to KR3 are only present in the 40- and 44-pin products. Pins KR0 to KR5 are only present in the 48-pin products. Pins KR0 to KR7 are only present in the 52-, 64-, 80-, 100-, and 128-pin products.
22.2
Configuration of the Key Interrupt
The key interrupt includes the following hardware blocks.
Table 22 - 2 Configuration of the Key Interrupt
Item
Control registers
Key return control register (KRCTL) Key return mode register 0 (KRM0) Key return flag register (KRF) Port mode register 7 (PM7)
Configuration
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RL78/G23 Figure 22 - 1 Block Diagram of the Key Interrupt
KREG KR7
KREG KR2
KREG KR1
KREG KR0
CHAPTER 22 KEY INTERRUPT FUNCTION
KRMD
KRF7 KRMD
KRF2 KRMD
KRF1 KRMD
KRF0
S electo r
Sel ector
Selector
INTKR
Sele ctor
KRM07
KRM02 KRM01 KRM00
Key return mode register 0 (KRM0)
Remark
Pins KR0 to KR3 are only present in the 40- and 44-pin products. Pins KR0 to KR5 are only present in the 48-pin products. Pins KR0 to KR7 are only present in the 52-, 64-, 80-, 100-, and 128-pin products.
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22.3
Registers to Control the Key Interrupt
The following registers are used to control the key interrupt.
· Key return control register (KRCTL) · Key return mode register 0 (KRM0) · Key return flag register (KRF) · Port mode registers 7 (PM7)
22.3.1 Key return control register (KRCTL)
This register controls the usage of the key return flags (KRF0 to KRF7) and sets the detection edge. The KRCTL register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Figure 22 - 2 Format of Key return control register (KRCTL)
Address: After reset: R/W:
FFF34H 00H R/W
Symbol
<7>
6
5
4
3
2
1
<0>
KRCTL KRMD
0
0
0
0
0
0
KREG
KRMD 0 1
Usage of key return flags (KRF0 to KRF7) Does not use key return flags Uses key return flags
KREG 0 1
Falling edge Rising edge
Selection of detection edge (KR0 to KR7)
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22.3.2 Key return mode register 0 (KRM0)
The KRM0 register controls the KR0 to KR7 signals. The KRM0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Figure 22 - 3 Format of Key return mode register 0 (KRM0)
Address: After reset: R/W:
FFF37H 00H R/W
Symbol KRM0
7 KRM07
6 KRM06
5 KRM05
4 KRM04
3 KRM03
2 KRM02
1 KRM01
0 KRM00
KRM0n
Key interrupt mode control
0
Does not detect key interrupt signal
1
Detects key interrupt signal
Caution 1. The on-chip pull-up resistor can be applied by setting the corresponding key interrupt input pins (bits) in pull-up resistor register 7 (PU7) to 1.
Caution 2. An interrupt will be generated if the target bit of the KRM0 register is set while a low level (KREG is set to 0) or a high level (KREG is set to 1) is being input to the key interrupt input pin. To ignore this interrupt, set the KRM0 register after disabling interrupt servicing by using the interrupt mask flag. Afterward, clear the interrupt request flag and enable interrupt servicing after waiting for the key interrupt input high-level and low-level widths (see 37.4 AC Characteristics).
Caution 3. The pins not used in the key interrupt mode can be used as normal port pins.
Remark 1. n = 0 to 7 Remark 2. Pins KR0 to KR3 are only present in the 40- and 44-pin products.
Pins KR0 to KR5 are only present in the 48-pin products. Pins KR0 to KR7 are only present in the 52-, 64-, 80-, 100-, and 128-pin products.
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22.3.3 Key return flag register (KRF)
This register controls the key interrupt flags (KRF0 to KRF7). The KRF register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Figure 22 - 4 Format of Key return flag register (KRF)
Address: After reset: R/W:
FFF35H 00H R/WNote
Symbol KRF
7 KRF7
6 KRF6
5 KRF5
4 KRF4
3 KRF3
2 KRF2
1 KRF1
0 KRF0
KRFn
Key interrupt flag (n = 0 to 7)
0
No key interrupt signal has been detected.
1
A key interrupt signal has been detected.
Note
Writing 1 has no effect. To clear the KRFn bit, write 0 to the corresponding bit and 1 to the other bits using an 8-bit memory manipulation instruction.
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22.3.4 Port mode registers 7 (PM7)
This register sets the input and output of port 7 in 1-bit units. To use a key interrupt input (KR0 to KR7), set the corresponding bit in this register to 1. The PM7 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to FFH. The on-chip pull-up resistor can be applied by setting the corresponding key interrupt input pins (bits) in the pull-up resistor register 7 (PU7) to 1.
Figure 22 - 5 Format of Port mode registers 7 (PM7)
Address: After reset: R/W:
FFF27H FFH R/W
Symbol PM7
7 PM77
6 PM76
5 PM75
4 PM74
3 PM73
2 PM72
1 PM71
0 PM70
PM7n 0 1
I/O mode selection for PM7n pin (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off)
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CHAPTER 23 STANDBY FUNCTION
CHAPTER 23 STANDBY FUNCTION
23.1
Standby Function
The standby function reduces the operating current of the system, and the following three modes are available.
(1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the high-speed system clock oscillator, high-speed on-chip oscillator, middle-speed on-chip oscillator, or subsystem clock oscillator is operating before the HALT mode is set, oscillation of each clock continues. In this mode, the operating current is not decreased as much as in the STOP mode, but the HALT mode is effective for restarting operation immediately upon interrupt request generation and carrying out intermittent operations frequently.
(2) STOP mode STOP instruction execution sets the STOP mode. In the STOP mode, the high-speed system clock oscillator, highspeed on-chip oscillator, and middle-speed on-chip oscillator stop, stopping the whole system, thereby considerably reducing the CPU operating current. Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out. However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is released when the X1 clock is selected, select the HALT mode if it is necessary to start processing immediately upon interrupt request generation.
(3) SNOOZE mode In SNOOZE mode, the RL78/G23 is released from STOP mode and the following peripheral modules can operate without CPU intervention. For details, see the chapters on the individual modules. · CHAPTER 12 A/D CONVERTER (ADC) · CHAPTER 15 SERIAL ARRAY UNIT (SAU) · CHAPTER 18 REMOTE CONTROL SIGNAL RECEIVER (REMC) · CHAPTER 19 DATA TRANSFER CONTROLLER (DTC) · CHAPTER 29 SNOOZE MODE SEQUENCER (SMS) · CHAPTER 30 CAPACITIVE SENSING UNIT (CTSU2L)
This can only be specified when the high-speed on-chip oscillator or middle-speed on-chip oscillator is selected for the CPU/peripheral hardware clock (fCLK).
In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is set are held. The I/O port output latches and output buffer statuses are also heldNote.
Note
This excludes memory which has been placed in shutdown mode by the PSMCR register.
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Caution 1. Shifting to the STOP mode is only enabled when the CPU is operating on the main system clock. Do not execute the STOP instruction while the CPU operates with the subsystem clock. Shifting to the HALT mode is enabled whether the CPU is operating on the main system clock or the subsystem clock.
Caution 2. When shifting to the STOP mode, be sure to stop the peripheral hardware operating with main system clock before executing the STOP instruction (excluding the peripheral modules which use the SNOOZE mode function and the timer array unit when in use by the remote control signal receiver (REMC) in SNOOZE mode).
Caution 3. It can be selected by WDTON of the option byte or WUTMMCK0 of the subsystem clock supply mode control register (OSMC) whether the low-speed on-chip oscillator continues oscillating or stops in the HALT or STOP mode. For details, see 6.1 Functions of Clock Generator (2) Subsystem clock <2> Low-speed on-chip oscillator.
Remark
30- to 64-pin products: p = 00; q = 0; m = 0 80- to 128-pin products: p = 00, 20; q = 0, 2; m = 0, 1
23.2
Registers to Control the Standby Function
The following registers are used to control the standby function.
· Subsystem clock supply mode control register (OSMC) · Oscillation stabilization time counter status register (OSTC) · Oscillation stabilization time select register (OSTS) · Standby mode release setting register (WKUPMD) · Memory power reduction control register (PSMCR)
Remark
For details of the OSMC, OSTC, and OSTS registers, see CHAPTER 6 CLOCK GENERATOR. For registers which control the SNOOZE mode function, see the following chapters. · CHAPTER 12 A/D CONVERTER (ADC) · CHAPTER 15 SERIAL ARRAY UNIT (SAU) · CHAPTER 18 REMOTE CONTROL SIGNAL RECEIVER (REMC) · CHAPTER 19 DATA TRANSFER CONTROLLER (DTC) · CHAPTER 29 SNOOZE MODE SEQUENCER (SMS) · CHAPTER 30 CAPACITIVE SENSING UNIT (CTSU2L)
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23.2.1 Standby mode release setting register (WKUPMD)
The WKUPMD register is used to set the operation at the time of release from the standby mode. The WKUPMD register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 23 - 1 Format of Standby Mode Release Setting Register (WKUPMD)
Address: After reset: R/W:
F0215H 00H R/W
Symbol
7
6
5
4
3
2
1
<0>
WKUPMD
0
0
0
0
0
0
0
FWKUP
FWKUP
Setting for starting the high-speed on-chip oscillator at the times of release from STOP mode and of transitions to SNOOZE modeNotes 1, 2
0
Starting of the high-speed on-chip oscillator is at normal speed.Note 3
1
Starting of the high-speed on-chip oscillator is at high speed.Note 3
Note 1. Note 2.
Note 3.
This setting is only available when the high-speed on-chip oscillator is selected for the CPU clock. This register is initialized when the RL78/G23 is released from STOP mode in response to thee generation of a reset signal, so starting of the high-speed on-chip oscillator is at normal speed. For the activation time, see 23.3.2 STOP mode. The accuracy of the high-speed on-chip oscillator's frequency depends on whether starting of the high-speed on-chip oscillator is at normal speed or at high speed. See CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
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23.2.2 Memory power reduction control register (PSMCR)
The PSMCR register is used to control the reduction of power consumption by the RAM. The leakage current can be reduced by placing the RAM in shutdown mode. The supply of power to the shut-down part of the RAM stops. Accordingly, that RAM does not retain data. The PSMCR register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 23 - 2 Format of Memory Power Reduction Control Register (PSMCR)
Address: After reset: R/W:
F0216H 00H R/W
Symbol
7
6
5
4
3
2
<1>
<0>
PSMCR
0
0
0
0
0
0
RAMSDMD RAMSDS
RAMSDMD RAMSDS
Operating mode of the RAM
0
0
Normal mode (continues to operate)
1
0
Standby mode
1
1
Shutdown mode
Other than above Setting prohibited
Caution 1. Shutdown mode applies to all RAM other than that in the range from FF000H to FFEFFH. The RAM that in the range from FF000H to FFEFFH continues to operate and retains data.
Caution 2. Do not access RAM while it is in the standby mode or shutdown mode.
Follow the procedure below to switch the operating mode of the RAM from normal mode to shutdown mode.
Figure 23 - 3 Procedure for Settings to Switch from Normal Mode to Shutdown Mode
Normal mode RAMSDMD = 1 Standby mode Waiting (80 ns) RAMSDS = 1 Shutdown mode
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Follow the procedure below to switch the operating mode of the RAM from shutdown mode to normal mode. Figure 23 - 4 Procedure for Settings to Switch from Shutdown Mode to Normal Mode
Shutdown mode RAMSDS = 0 Standby mode
Waiting (1.2 µs) RAMSDMD = 0 Normal mode
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23.3
Standby Function Operation
23.3.1 HALT mode
(1) HALT mode The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU clock before the setting was the high-speed system clock, high-speed on-chip oscillator clock, middle-speed onchip oscillator clock, or subsystem clock. The operating statuses in the HALT mode are shown below.
Caution
Because the interrupt request signal is used to clear the HALT mode, if the interrupt mask flag is 0 (the interrupt processing is enabled) and the interrupt request flag is 1 (the interrupt request signal is generated), the HALT mode is not entered even if the HALT instruction is executed in such a situation.
Table 23 - 1 Operating Statuses in HALT Mode (1) (1/2)
HALT Mode Setting
When HALT Instruction is Executed While CPU is Operating on Main System Clock
Item System clock
Main system clock fIH
fIM
fX
fEX
Subsystem clock
fXT fEXS fIL
CPU Code flash memory Data flash memory RAM Port (latch)
Timer array unit RTC 32-bit interval timer Watchdog timer
When CPU is Operating on High-speed On-chip
Oscillator Clock (fIH)
When CPU is Operating on Middle-speed On-
chip Oscillator Clock (fIM)
When CPU is Operating on X1 Clock (fX)
When CPU is Operating on External Main System
Clock (fEX)
Clock supply to the CPU is stopped
Operation continues (cannot be stopped)
Operation disabled
Operation disabled
Operation continues (cannot be stopped)
Operation disabled
Operation disabled
Operation disabled
Operation continues (cannot be stopped) Cannot operate
Retains the state before the transition to HALT mode
Cannot operate
Operation continues (cannot be stopped)
Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0 bit of subsystem clock supply mode control register (OSMC) WUTMMCK0 = 1 or SELLOSC = 1: Oscillates (Setting of WUTMMCK0 = 1 and SELLOSC = 1 is prohibited when the subsystem clocks X (fSX) and XR (fSXR) are operating.) WUTMMCK0 = 0, SELLOSC = 0, and WDTON = 0: Stop WUTMMCK0 = 0, SELLOSC = 0, WDTON = 1, and WDSTBYON = 1: Oscillates WUTMMCK0 = 0, SELLOSC = 0, WDTON = 1, and WDSTBYON = 0: Stop
Operation stopped
Operation stopped (capable of operations in response to access by the DTC or SMS) Retains the state before the transition to HALT mode (capable of operations in response to access by the DTC, SMS or ELCL) Operation enabled Operation enabled Operation enabled See CHAPTER 11 WATCHDOG TIMER (WDT).
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Table 23 - 1 Operating Statuses in HALT Mode (1) (2/2)
HALT Mode Setting
When HALT Instruction is Executed While CPU is Operating on Main System Clock
Item Clock output/buzzer output A/D converter D/A converter Comparator Serial array unit Serial interface IICA Serial interface UARTA Remote control signal receiver Data transfer controller (DTC) SNOOZE mode sequencer Logic and event link controller (ELCL) Power-on-reset function Voltage detection function External interrupt Key interrupt function Capacitive sensing unit (CTSU) CRC operation function High-speed CRC
General-purpose CRC Illegal-memory access detection function RAM parity error detection function RAM guard function SFR guard function
When CPU is Operating on High-speed On-chip
Oscillator Clock (fIH)
When CPU is Operating on Middle-speed On-
chip Oscillator Clock (fIM)
When CPU is Operating on X1 Clock (fX)
When CPU is Operating on External Main System
Clock (fEX)
Operation enabled
Operation-enabled function blocks can be linked Operation enabled
Capable of operations in response to access by the DTC or SMS to obtain data for calculations from the RAM area Capable of operations in response to access by the DTC or SMS
Remark
Operation stopped: Operation is automatically stopped before switching to HALT mode.
Operation disabled: Operation is stopped before switching to the HALT mode.
fIH: High-speed on-chip oscillator clock fIL: Low-speed on-chip oscillator clock
fIM: Middle-speed on-chip oscillator clock fX: X1 clock
fEX: External main system clock
fXT: XT1 clock
fEXS: External subsystem clock
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Table 23 - 2 Operating Statuses in HALT Mode (2) (1/2)
HALT Mode Setting
When HALT Instruction is Executed While CPU is Operating on Subsystem Clock
Item
System clock
Main system clock fIH
fIM
fX
fEX
Subsystem clock
fXT
fEXS
fIL
CPU Code flash memory Data flash memory RAM Port (latch)
Timer array unit
RTC 32-bit interval timer
Watchdog timer Clock output/buzzer output
A/D converter D/A converter
Comparator
Serial array unit
Serial interface IICA Serial interface UARTA
Remote control signal receiver
Data transfer controller (DTC)
When CPU is Operating on XT1 Clock (fXT)
When CPU is Operating on External Subsystem Clock
(fEXS)
When CPU is Operating on Low-speed on-chip oscillator
clock (fIL)
Clock supply to the CPU is stopped Operation disabled
Operation continues (cannot be stopped)
Cannot operate
Cannot operate
Operation continues (cannot be stopped)
Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0 bit of subsystem clock supply mode control register (OSMC) WUTMMCK0 = 1: Oscillates (Setting of WUTMMCK0 = 1 and SELLOSC = 1 is prohibited when the subsystem clocks X (fSX) and XR (fSXR) are operating.) WUTMMCK0 = 0, SELLOSC = 0, and WDTON = 0: Stop WUTMMCK0 = 0, SELLOSC = 0, WDTON = 1, and WDSTBYON = 1: Oscillates WUTMMCK0 = 0, SELLOSC = 0, WDTON = 1, and WDSTBYON = 0: Stop
Operation stopped
Operation disabled
Operation disabled
Operation continues (cannot be stopped)
Operation stopped (capable of operations in response to access by the DTC or SMS)
Retains the state before the transition to HALT mode (capable of operations in response to access by the DTC, SMS or ELCL)
Operates when the RTCLPC bit is 0 (operation is disabled when the Operation enabled RTCLPC bit is not 0).
Operation enabled
Operates when the RTCLPC bit is 0 (operation is disabled when the Operation enabled RTCLPC bit is not 0).
See CHAPTER 11 WATCHDOG TIMER (WDT).
Operates when the RTCLPC bit is 0 (operation is disabled when the Operation enabled RTCLPC bit is not 0).
Operation disabled
Retains the state before the transition to HALT mode (capable of operation when RTCLPC = 0 and in response to access by the DTC, SMS, and ELCL)
Operation enabled (when the RTCLPC bit is 0, or when the digital filter is not used)
Operation enabled
Operates when the RTCLPC bit is 0 (operation is disabled when the Operation enabled RTCLPC bit is not 0).
Operation disabled
Operates when the RTCLPC bit is 0 (operation is disabled when the Operation enabled RTCLPC bit is not 0).
Operates when the RTCLPC bit is 0 (operation is disabled when the Operation enabled RTCLPC bit is not 0).
Operates when the RTCLPC bit is 0 (operation is disabled when the Operation enabled RTCLPC bit is not 0).
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Table 23 - 2 Operating Statuses in HALT Mode (2) (2/2)
HALT Mode Setting
When HALT Instruction is Executed While CPU is Operating on Subsystem Clock
Item SNOOZE mode sequencer
Logic and event link controller (ELCL) Power-on-reset function Voltage detection function External interrupt Key interrupt function Capacitive sensing unit (CTSU)
CRC operation function
High-speed CRC
General-purpose CRC
Illegal-memory access detection function
RAM parity error detection function
RAM guard function
SFR guard function
When CPU is Operating on XT1 Clock (fXT)
When CPU is Operating on External Subsystem Clock
(fEXS)
When CPU is Operating on Low-speed on-chip oscillator
clock (fIL)
Operates when the RTCLPC bit is 0 (operation is disabled when the Operation enabled RTCLPC bit is not 0).
Operation-enabled function blocks can be linked
Operation enabled
Operates when the RTCLPC bit is 0 (operation is disabled when the Operation enabled RTCLPC bit is not 0).
Operation disabled
Capable of operations in response to access by the DTC or SMS to obtain data for calculations from the RAM area
Capable of operations in response to access by the DTC or SMS
Remark
Operation stopped: Operation is automatically stopped before switching to the HALT mode.
Operation disabled: Operation is stopped before switching to the HALT mode.
fIH: High-speed on-chip oscillator clock fIL: Low-speed on-chip oscillator clock
fIM: Middle-speed on-chip oscillator clock fX: X1 clock
fEX: External main system clock
fXT: XT1 clock
fEXS: External subsystem clock
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(2) HALT mode release The HALT mode can be released by the following two sources.
(a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed.
Figure 23 - 5 HALT Mode Release by Interrupt Request Generation
Standby release signal Note 1
HALT instruction
Interrupt request
Status of CPU
High-speed system clock, High-speed on-chip oscillator clock, middle-speed on-chip oscillator clock,
or subsystem clock
Operating mode
HALT mode
Wait Note 2
Oscillation
Operating mode
Note 1. Note 2.
For details of the standby release signal, see Figure 21 - 1 Basic Configuration of Interrupt Function (1/2).
Wait time for HALT mode release
· When vectored interrupt servicing is carried out
Main system clock:
15 to 16 clock cycles
Subsystem clock (RTCLPC = 0): 10 to 11 clock cycles
Subsystem clock (RTCLPC = 1): 11 to 12 clock cycles
· When vectored interrupt servicing is not carried out
Main system clock:
9 to 10 clock cycles
Subsystem clock (RTCLPC = 0): 4 to 5 clock cycles
Subsystem clock (RTCLPC = 1): 5 to 6 clock cycles
Remark The broken lines indicate the case when the interrupt request which has released the standby mode is acknowledged.
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(b) Release by reset signal generation When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address.
Figure 23 - 6 HALT Mode Release by Reset (1/2) (1) When high-speed on-chip oscillator clock is used as CPU clock
HALT instruction
Reset signal
Status of CPU
High-speed on-chip oscillator clock
Normal operation (high-speed on -chip
oscillator clock )
HALT mode
Oscillates
(2) When high-speed system clock is used as CPU clock
Reset Note period
Oscillation stopped
Normal operation (high -speed on -chip
oscillator clock )
Oscillates
Wait for oscillation accuracy stabilization
HALT instruction
Reset signal
Normal operation
Status of CPU (high-speed system clock )
HALT mode
High-speed system clock (X1 oscillation )
Oscillates
Reset period Note
Oscillation Oscillation stopped stopped
Normal operation (high-speed on -chip
oscillator clock )
Oscillates
Oscillation stabilization time (check by using OSTC register )
Starting X1 oscillation is specified by software .
Note
For the reset processing time, see CHAPTER 24 RESET FUNCTION. For the reset processing time of the power-on-reset circuit (POR) and voltage detectors (LVD0 and LVD1), see CHAPTER 25 POWER-ON-RESET CIRCUIT (POR).
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RL78/G23 Figure 23 - 6 HALT Mode Release by Reset (2/2) (3) When subsystem clock is used as CPU clock
HALT instruction
CHAPTER 23 STANDBY FUNCTION
Note
Reset signal
Normal operation Status of CPU (subsystem clock )
HALT mode
Subsystem clock (XT1 oscillation )
Oscillates
Reset period
Note
Oscillation Oscillation stopped stopped
Normal operation mode (high -speed on -chip oscillator clock)
Oscillates
Oscillation stabilization time (check by using OSTC register )
Starting XT1 oscillation is specified by software.
For the reset processing time, see CHAPTER 24 RESET FUNCTION. For the reset processing time of the power-on-reset circuit (POR) and voltage detectors (LVD0 and LVD1), see CHAPTER 25 POWER-ON-RESET CIRCUIT (POR).
23.3.2 STOP mode
(1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the setting was the main system clock.
Caution
Because the interrupt request signal is used to clear the STOP mode, if the interrupt mask flag is 0 (the interrupt processing is enabled) and the interrupt request flag is 1 (the interrupt request signal is generated), the STOP mode is immediately cleared if set when the STOP instruction is executed in such a situation. Accordingly, once the STOP instruction is executed, the system returns to its normal operating mode after the elapse of release time from the STOP mode.
The operating statuses in the STOP mode are shown below.
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Table 23 - 3 Operating Statuses in STOP Mode (1/2)
STOP Mode Setting
When STOP Instruction is Executed While CPU is Operating on Main System Clock
Item System clock
Main system clock
Subsystem clock
fIH fIM fX fEX fXT fEXS fIL
CPU Code flash memory Data flash memory RAM Port (latch) Timer array unit RTC 32-bit interval timer Watchdog timer Clock output/buzzer output A/D converter D/A converter Comparator Serial array unit
Serial interface IICA Serial interface UARTA Remote control signal receiver Data transfer controller (DTC) SNOOZE mode sequencer Logic and event link controller (ELCL) Power-on-reset function Voltage detection function External interrupt Key interrupt function Capacitive sensing unit (CTSU)
When CPU is Operating on High-speed On-chip
Oscillator Clock (fIH)
When CPU is Operating on Middle-speed On-chip
Oscillator Clock (fIM)
When CPU is Operating on X1 Clock (fX)
When CPU is Operating on External Main System
Clock (fEX)
Clock supply to the CPU is stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Retains the state before the transition to STOP mode
Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0 bit of subsystem clock supply mode control register (OSMC) WUTMMCK0 = 1 or SELLOSC = 1: Oscillates (Setting of WUTMMCK0 = 1 and SELLOSC = 1 is prohibited when the subsystem clocks X (fSX) and XR (fSXR) are operating.) WUTMMCK0 = 0, SELLOSC = 0, and WDTON = 0: Stop WUTMMCK0 = 0, SELLOSC = 0, WDTON = 1, and WDSTBYON = 1: Oscillates WUTMMCK0 = 0, SELLOSC = 0, WDTON = 1, and WDSTBYON = 0: Stop
Operation stopped
Retains the state before the transition to STOP mode Operation stopped Operation enabled Capable of operation when fSXP is selected and RTCLPC = 0 See CHAPTER 11 WATCHDOG TIMER (WDT). Capable of operation when fSXP is selected and RTCLPC = 0 Wakeup operation is enabled (switching to SNOOZE mode) Retains the state before the transition to STOP mode Operation enabled (only when the digital filter is not used) Wakeup operation is enabled only for CSIp and UARTq (switching to SNOOZE mode) Operation is disabled for anything other than CSIp and UARTq Capable of waking up in response to address matching Capable of operation when fSXP is selected and RTCLPC = 0 Capable of operation in response to edge detection (switching to SNOOZE mode) DTC activation source receiving operation enabled (switching to SNOOZE mode) SMS activation source receiving operation enabled (switching to SNOOZE mode) Operation-enabled function blocks can be linked Operation enabled
CTSU activation source receiving operation enabled (switching to SNOOZE mode)
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Table 23 - 3 Operating Statuses in STOP Mode (2/2)
STOP Mode Setting
When STOP Instruction is Executed While CPU is Operating on Main System Clock
Item
CRC operation function
High-speed CRC
General-purpose CRC
Illegal-memory access detection function
RAM parity error detection function
RAM guard function
SFR guard function
When CPU is Operating on High-speed On-chip
Oscillator Clock (fIH)
Operation stopped
When CPU is Operating on Middle-speed On-chip
Oscillator Clock (fIM)
When CPU is Operating on X1 Clock (fX)
When CPU is Operating on External Main System
Clock (fEX)
Remark 1. Operation stopped: Operation is automatically stopped before switching to the STOP mode.
Operation disabled: Operation is stopped before switching to the STOP mode.
fIH:
High-speed on-chip oscillator clock fIL: Low-speed on-chip oscillator clock
fIM:
Middle-speed on-chip oscillator clock fX: X1 clock
fEX:
External main system clock
fXT: XT1 clock
fEXS: External subsystem clock Remark 2. 30- to 64-pin products: p = 00; q = 0
fSXP: Low-speed peripheral clock frequency
80- to 128-pin products: p = 00, 20; q = 0, 2
(2) STOP mode release The STOP mode can be released by the following two sources.
(a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed.
Figure 23 - 7 STOP Mode Release by Interrupt Request Generation (1/3)
(1) When high-speed/middle-speed on-chip oscillator clock is used as CPU clock
STOP instruction
Interrupt request
Standby release signal Note 1
Normal operation (high-speed /middle-speed
on-chip oscillator clock )
Status of CPU
STOP mode
STOP mode release time Note 2
Supply of the clock is stopped
Wait
Normal operation (high-speed /middle-speed
on-chip oscillator clock )
High -speed/middle -speed on-chip oscillator clock
Oscillates
Oscillation stopped
Oscillates
Wait for oscillation accuracy stabilization
Note 1. For details of the standby release signal, see Figure 21 - 1 Basic Configuration of Interrupt Function (1/2).
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Note 2.
STOP mode release time Supply of the clock is stopped: When high-speed on-chip oscillator clock: 3.9 to 5.2 µs (FWKUP = 0: Starting of the high-speed on-chip oscillator is at normal speed.) 0.6 to 0.8 µs (FWKUP = 1: Starting of the high-speed on-chip oscillator is at high speed.) The accuracy of the high-speed on-chip oscillator's frequency depends on whether starting of the high-speed on-chip oscillator is at normal speed or at high speed. See CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C. When middle-speed on-chip oscillator clock: 1.5 to 2.5 µs Wait: (common to the high-speed/middle-speed on-chip oscillator clock) · When vectored interrupt servicing is carried out: 7 clock cycles · When vectored interrupt servicing is not carried out: 1 clock cycle
Caution
To shorten oscillation stabilization time after the STOP mode is released when the CPU operates with the highspeed system clock (X1 oscillation), temporarily switch the CPU clock to the high-speed on-chip oscillator clock before the execution of the STOP instruction.
Remark 1. The clock supply stop time varies depending on the temperature conditions and STOP mode period. Remark 2. The broken lines indicate the case when the interrupt request that has released the standby mode is acknowledged.
Figure 23 - 7 STOP Mode Release by Interrupt Request Generation (2/3) (2) When high-speed system clock (X1 oscillation) is used as CPU clock
STOP instruction
Interrupt request
Standby release signal Note 1
Normal operation ( high - speed
Status of CPU system clock )
High-speed system clock (X1 oscillation )
Oscillates
STOP mode Oscillation stopped
STOP mode release time Note 2
Supply of the clock is stopped
Wait
Normal operation
( high - speed system clock )
Oscillates
Note 1. Note 2.
For details of the standby release signal, see Figure 21 - 1 Basic Configuration of Interrupt Function (1/2). STOP mode release time Supply of the clock is stopped: Oscillation stabilization time (set by OSTS)
Wait: · When vectored interrupt servicing is carried out: · When vectored interrupt servicing is not carried out:
10 to 11 clock cycles 4 to 5 clock cycles
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Figure 23 - 7 STOP Mode Release by Interrupt Request Generation (3/3) (3) When high-speed system clock (external clock input) is used as CPU clock
STOP instruction
Interrupt request
Standby release signal Note 1
Status of CPU
Normal operation
(high-speed system clock )
High-speed system clock (external clock input)
Oscillates
STOP mode
STOP mode release time Note 2
Supply of the clock is stopped
Wait
Normal operation (high-speed system clock)
Oscillation stopped
Oscillates
Note 1. Note 2.
For details of the standby release signal, see Figure 21 - 1 Basic Configuration of Interrupt Function (1/2). STOP mode release time Supply of the clock is stopped: 50 to 51 cycles of the external clock
Wait: · When vectored interrupt servicing is carried out: · When vectored interrupt servicing is not carried out:
7 clock cycles 1 clock cycle
Caution
To reduce the oscillation stabilization time after release from the STOP mode while CPU operates based on the high-speed system clock (X1 oscillation), switch the clock to the high-speed on-chip oscillator clock temporarily before executing the STOP instruction.
Remark 1. The clock supply stop time varies depending on the temperature conditions and STOP mode period. Remark 2. The broken lines indicate the case when the interrupt request that has released the standby mode is acknowledged.
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(b) Release by reset signal generation When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address.
Figure 23 - 8 STOP Mode Release by Reset
(1) When high-speed on-chip oscillator clock is used as CPU clock
STOP instruction
Reset signal
Status of CPU High-speed on-chip
oscillator clock
Normal operation (high-speed on -chip
oscillator clock )
Oscillates
STOP mode
Reset period
Oscillation
Oscillation stopped stopped
Note
Normal operation (high -speed on -chip
oscillator clock )
Oscillates
Wait for oscillation accuracy stabilization
(2) When middle-speed on-chip oscillator clock is used as CPU clock
STOP instruction
Reset signal
Normal operation
(middle-speed on -chip oscillator clock )
Status of CPU
STOP mode
High-speed on-chip oscillator clock
Oscillates
Oscillation stopped
Reset period
Oscillation stopped
Note
Normal operation (high-speed on-chip
oscillator clock )
Oscillates
Wait for oscillation accuracy stabilization
Middle-speed on-chip oscillator clock
Oscillates
Oscillation stopped
(3) When high-speed system clock is used as CPU clock STOP instruction
Reset signal
Status of CPU High-speed system clock
(X1 oscillation )
Normal operation (high -speed system clock)
STOP mode
Reset period
Note
Oscillates
Oscillation Oscillation
Oscillation stopped stopped stopped
Normal operation (high -speed on-chip
oscillator clock)
Oscillates
Oscillation stabilization time (Check by using OSTC register)
Starting X1 oscillation is specified by software .
Note
For the reset processing time, see CHAPTER 24 RESET FUNCTION. For the reset processing time of the power-on-reset circuit (POR) and voltage detectors (LVD0 and LVD1), see CHAPTER 25 POWER-ON-RESET CIRCUIT (POR).
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23.3.3 SNOOZE mode
(1) SNOOZE mode setting and operating statuses The RL78/G23 can be placed in SNOOZE mode, in which operation of the following peripheral modules is selectable. For details, see the chapters on the individual modules. · CHAPTER 12 A/D CONVERTER (ADC) · CHAPTER 15 SERIAL ARRAY UNIT (SAU) · CHAPTER 18 REMOTE CONTROL SIGNAL RECEIVER (REMC) · CHAPTER 19 DATA TRANSFER CONTROLLER (DTC) · CHAPTER 29 SNOOZE MODE SEQUENCER (SMS) · CHAPTER 30 CAPACITIVE SENSING UNIT (CTSU2L)
Also, the RL78/G23 can be placed in SNOOZE mode if the CPU clock before entry to SNOOZE mode is the highspeed on-chip oscillator clock or middle-speed on-chip oscillator clock.
In SNOOZE mode transition, wait status to be only following time.
Transition time from STOP mode to SNOOZE mode:
When high-speed on-chip oscillator clock:
3.9 to 5.2 µs (FWKUP = 0: Starting of the high-speed on-chip
oscillator is at normal speed.)
0 to 0.8 µs (FWKUP = 1: Starting of the high-speed on-chip
oscillator is at high speed.)
The accuracy of the high-speed on-chip oscillator's frequency
depends on whether starting of the high-speed on-chip oscillator
is at normal speed or at high speed. See CHAPTER 37
ELECTRICAL CHARACTERISTICS TA = -40 to +105°C.
When middle-speed on-chip oscillator clockNote: 1.3 to 2.5 µs
Remark
Transition time from STOP mode to SNOOZE mode varies depending on the temperature conditions and the STOP mode period.
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Transition time from SNOOZE mode to normal operation: When high-speed on-chip oscillator clock:
· When vectored interrupt servicing is carried out: "0.3 to 0.4 µs" + 7 clock cycles
· When vectored interrupt servicing is not carried out: "0.3 to 0.4 µs" + 1 clock cycle
When middle-speed on-chip oscillator clockNote:
· When vectored interrupt servicing is carried out: "0.6 to 1.2 µs" + 7 clock cycles
· When vectored interrupt servicing is not carried out: "0.6 to 1.2 µs" + 1 clock cycle
Note
This is selected when the setting of the MIOTRM register is its initial value.
The operating statuses in the SNOOZE mode are shown next.
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Table 23 - 4 Operating Statuses in SNOOZE Mode (1/2)
STOP Mode Setting
Generation of source conditions which lead to transitions to SNOOZE mode during STOP mode
Item System clock
When CPU is Operating on High-speed On-chip Oscillator Clock (fIH)
Clock supply to the CPU is stopped
When CPU is Operating on Middle-speed On-chip Oscillator Clock (fIM)
Main system clock Subsystem clock
fIH fIM fX fEX fXT fEXS fIL
CPU
Operation started Stopped Stopped
Stopped Operation started
Use of the status while in the STOP mode continues
Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0 bit of subsystem clock supply mode control register (OSMC) WUTMMCK0 = 1 or SELLOSC = 1: Oscillates (Setting of WUTMMCK0 = 1 and SELLOSC = 1 is prohibited when the subsystem clocks X (fSX) and XR (fSXR) are operating.) WUTMMCK0 = 0, SELLOSC = 0, and WDTON = 0: Stop WUTMMCK0 = 0, SELLOSC = 0, WDTON = 1, and WDSTBYON = 1: Oscillates WUTMMCK0 = 0, SELLOSC = 0, WDTON = 1, and WDSTBYON = 0: Stop
Operation stopped
Code flash memory Data flash memory
RAM
Operation stopped (capable of operations in response to access by the DTC or SMS)
Port (latch)
Retains the state before the transition to SNOOZE mode (capable of operations in response to access by the DTC, SMS or ELCL)
Timer array unit RTC
Capable of operations in response to access by the DTC, SMS or ELCL Operation enabled
32-bit interval timer Watchdog timer Clock output/buzzer output A/D converter D/A converter
Comparator
Capable of operation when fSXP is selected and RTCLPC = 0 See CHAPTER 11 WATCHDOG TIMER (WDT). Capable of operation when fSXP is selected and RTCLPC = 0 Operation enabled Retains the state before the transition to SNOOZE mode (capable of operation when RTCLPC = 0 and in response to access by the DTC, SMS, and ELCL) Operation enabled (when digital filter is not used)
Serial array unit Serial interface IICA
Only CSIp and USRTq are capable of operation. Operation of the types of modules other than CSIp and USRTq is disabled.
Capable of waking up in response to address matching
Serial interface UARTA Remote control signal receiver
Capable of operation when fSXP is selected and RTCLPC = 0 Operation enabled
Data transfer controller (DTC)
Operation enabled
SNOOZE mode sequencer Logic and event link controller (ELCL)
Operation enabled Operation-enabled function blocks can be linked
Power-on-reset function
Operation enabled
Voltage detection function External interrupt
Key interrupt function Capacitive sensing unit (CTSU)
Operation enabled
CRC operation function High-speed CRC Operation stopped
General-purpose Capable of operations in response to access by the DTC or SMS to obtain data for calculations from the
CRC
RAM area
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Table 23 - 4 Operating Statuses in SNOOZE Mode (2/2)
STOP Mode Setting
Generation of source conditions which lead to transitions to SNOOZE mode during STOP mode
When CPU is Operating
When CPU is Operating
Item
on High-speed On-chip Oscillator Clock (fIH)
on Middle-speed On-chip Oscillator Clock (fIM)
Illegal-memory access detection function RAM parity error detection function
Capable of operations in response to access by the DTC or SMS
RAM guard function
SFR guard function
Remark 1. Operation stopped: Operation is automatically stopped before switching to the STOP mode.
Operation disabled: Operation is stopped before switching to the STOP mode.
fIH: High-speed on-chip oscillator clock
fIL: Low-speed on-chip oscillator clock
fIM: Middle-speed on-chip oscillator clock
fX: X1 clock
fEX: External main system clock
fXT: XT1 clock
fEXS: External subsystem clock
fSX: Subsystem clock X
fSXR: Subsystem clock XR Remark 2. 30- to 64-pin products: p = 00; q = 0
fSXP: Low-speed peripheral clock frequency
80- to 128-pin products: p = 00, 20; q = 0, 2
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(2) Timing diagram when the interrupt request signal is generated in the SNOOZE mode
Figure 23 - 9 When the Interrupt Request Signal is Generated in the SNOOZE Mode
STOP
Trigger
instruction detection
Standby release signal Note 1
Normal operation Note 4
(high-speed/middle-speed
Status of CPU on-chip oscillator clock ) STOP mode Note 2
Interrupt request
SNOOZE mode
Note 3
H
L Normal operation Note 5 (high-speed/middle -speed on-chip oscillator clock )
High -speed/middle-speed on-chip oscillator clock
Oscillates
Oscillation stopped
Oscillates
Wait for oscillation accuracy stabilization
Note 1. Note 2. Note 3. Note 4. Note 5.
For details of the standby release signal, see Figure 21 - 1. Transition time from STOP mode to SNOOZE mode Transition time from SNOOZE mode to normal operation Enable the SNOOZE mode immediately before switching to the STOP mode. Be sure to release the SNOOZE mode immediately after return to the normal operation.
(3) Timing diagram when the interrupt request signal is not generated in the SNOOZE mode
Figure 23 - 10When the Interrupt Request Signal is not Generated in the SNOOZE Mode
STOP
Trigger
instruction detection
Standby release signal Note 1
Normal operation
Note 3
Status of CPU (high-speed /middle-speed STOP mode Note 2
on-chip oscillator clock )
High-speed/ middle-speed on-chip oscillator clock
Oscillates
Oscillation stopped
SNOOZE mode Oscillates
L STOP mode
(Waiting for a trigger to switch to the SNOOZE mode)
Oscillation stopped
Note 1. Note 2. Note 3.
Wait for oscillation accuracy stabilization For details of the standby release signal, see Figure 21 - 1. Transition time from STOP mode to SNOOZE mode Enable the SNOOZE mode immediately before switching to the STOP mode.
Remark
For details on the SNOOZE mode function, see the following chapters. · CHAPTER 12 A/D CONVERTER (ADC) · CHAPTER 15 SERIAL ARRAY UNIT (SAU) · CHAPTER 18 REMOTE CONTROL SIGNAL RECEIVER (REMC) · CHAPTER 19 DATA TRANSFER CONTROLLER (DTC) · CHAPTER 29 SNOOZE MODE SEQUENCER (SMS) · CHAPTER 30 CAPACITIVE SENSING UNIT (CTSU2L)
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CHAPTER 24 RESET FUNCTION
A reset is triggered by any of the following events.
(1) External reset input via the RESET pin (2) Internal reset due to detection of a program malfunction by the watchdog timer (3) Internal reset by comparison of supply voltage and detection voltage of the power-on-reset (POR) circuit (4) Internal reset by comparison of supply voltage and detection voltage of the voltage detectors (LVD0 and LVD1) (5) Internal reset due to execution of an illegal instructionNote (6) Internal reset due to a RAM parity error (7) Internal reset due to illegal-memory access
External and internal resets start program execution from the address at 0000H and 0001H when the reset signal is generated. A reset is applied when a low level is input to the RESET pin or the watchdog timer overflows, or on voltage detection by the POR, LVD0, or LVD1 circuit, execution of illegal instructionNote, generation of a RAM parity error, or illegal-memory access, and each module is set to the state shown in Table 24 - 1.
Note
In normal operation, executing the instruction code FFH triggers an internal reset, but this is not the case during emulation by the in-circuit emulator or on-chip debugging emulator.
Caution 1. For an external reset, input a low level for at least 10 µs to the RESET pin. To perform an external reset upon power application, input a low level to the RESET pin, turn power on, continue to input a low level to the pin for at least 10 µs within the operating voltage range shown in 37.4 AC Characteristics, and then input a high level to the pin.
Caution 2. During generation of a reset signal, the X1 clock, high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock, and low-speed on-chip oscillator clock stop oscillating. External main system clock input becomes invalid. The XT1 clock and external subsystem clock only stop oscillating or their inputs become invalid in the POR state.
Caution 3. The port pins become the following state because SFRs and 2nd SFRs are initialized after a reset. · P40: High-impedance during the external reset period or reset period by the POR. High level during other types of reset and after the reset is released (connected to the on-chip pull-up resistor). · P130: Low-level output during a reset and after the reset is released. · Ports other than P40 and P130: High-impedance during a reset and after the reset is released. The following registers are only initialized by a POR reset. · RTC-related registers · EXCLKS, OSCSELS, XTSEL, AMPHS1, and AMPHS0 bits of the CMC register
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RL78/G23 Figure 24 - 1 Block Diagram of Reset Function
CHAPTER 24 RESET FUNCTION
Watchdog timer reset signal
Reset signal by execution of illegal instruction Reset signal by RAM parity error
Reset signal by illegal-memory access
Internal bus Reset control flag register (RESF)
TRAP
WDTRF
RPERF
IAWRF
Set
Set
Set
Set
LVIRF Set
Clear Clear
Clear
Clear
Clear
Power-on-reset status register (PORSR) PORF
Clear
RESF register read signal RESET
Reset signal to LVIM/LVIS register
Power-on reset circuit reset signal
Voltage detector reset signal
Caution An LVD0 circuit internal reset does not reset the LVD0 circuit.
Reset signal
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CHAPTER 24 RESET FUNCTION
24.1
Timing of Reset Operation
This LSI is reset by input of the low level on the RESET pin and released from the reset state by input of the high level on the RESET pin. After reset processing, execution of the program with the high-speed on-chip oscillator clock as the operating clock starts.
Figure 24 - 2 Timing of Reset by RESET Input
High-speed on-chip oscillator clock
High-speed system clock (when X1 oscillation is selected)
CPU state
RESET
Internal reset signal
Normal operation
Port pin (other than P130)
Port pin (P130)
(Notes are listed on the next page.)
Delay
Wait for oscillation accuracy stabilization
Reset period (oscillation stopped)
Starting X1 oscillation is specified by software.
Normal operation (high-speed on-chip oscillator clock) Reset processing when an external reset is released Note 2
Hi-ZNote 3 Note 1
Release from the reset state proceeds automatically in the case of a reset due to a watchdog timer overflow, execution of an illegal instruction, detection of a RAM parity error, or detection of illegal-memory access. After reset processing, program execution starts with the high-speed on-chip oscillator clock as the operating clock.
Figure 24 - 3 Timing of Reset Due to Watchdog Timer Overflow, Execution of Illegal Instruction, Detection of RAM Parity Error, or Detection of Illegal-Memory Access
High-speed on-chip oscillator clock
High-speed system clock (when X1 oscillation is selected)
CPU state Watchdog timer overflow/ execution of illegal instruction/ detection of RAM parity error/ detection of illegal-memory access
Internal reset signal
Normal operation
Wait for oscillation accuracy stabilization
Starting X1 oscillation is specified by software.
Reset period
Reset
(oscillation stopped) processing
0.040 ms (typ.), 0.041 ms (max.)
Normal operation (high-speed on-chip oscillator clock)
Port pin (other than P130)
Port pin (P130)
(Notes are listed on the next page.)
Hi-Z Note 3 Note 1
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CHAPTER 24 RESET FUNCTION
Note 1. Note 2.
Note 3.
The P130 pin outputs a low-level signal following the application of a reset. If this pin was in use as a high-level output before the application of a reset, the output signal from the P130 pin can effectively be used as the reset signal for an external device that has an active-low reset signal. To de-assert the reset signal to the external device, set the P130 pin for high-level output by software. Reset times (times for release from the external reset state) The first external reset following release from the POR state: · When the LVD is in use: 0.506 ms (typ.), 0.694 ms (max.) · When the LVD is not in use: 0.201 ms (typ.), 0.335 ms (max.) The second or subsequent external reset following release from the POR state: · When the LVD is in use: 0.476 ms (typ.), 0.616 ms (max.) · When the LVD is not in use: 0.170 ms (typ.), 0.257 ms (max.) After power is supplied, the following voltage stabilization waiting time is required before reset processing starts after release from the external reset state. · 4.0 ms (typ.), 9.9 ms (max.) The state of the P40 pin is as follows. · High-impedance during the external reset period or reset period by the POR. · High level during other types of reset and after the reset is released (connected to the on-chip pull-up resistor).
A reset from the POR circuit or by LVD0 voltage detection is released when VDD VPOR or VDD VLVD0 after the reset. After reset processing, execution of the program starts with the high-speed on-chip oscillator clock as the operating clock. For details, see CHAPTER 25 POWER-ON-RESET CIRCUIT (POR) or CHAPTER 26 VOLTAGE DETECTOR (LVD).
Remark
VPOR: POR power supply rise detection voltage VLVD0: LVD0 detection voltage VLVD1: LVD1 detection voltage
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CHAPTER 24 RESET FUNCTION
Table 24 - 1 Operating States during a Reset (1/2)
Item
Operating State during a Reset
System clock
Clock supply to the CPU is stopped.
Main system clock
fIH
Operation stopped
fIM
fX
Operation stopped (the X1 and X2 pins are input port mode)
fEX
Clock input invalid (the pin is input port mode)
Subsystem clock
fXT
Operable (operation stops in the POR reset state, the XT1 and XT2 pins are input
port mode)
fEXS
Operable (operation stops in the POR reset state, the EXCLKS pin is input port
mode)
fIL
Operation stopped
CPU
Operation stopped
Code flash memory
Operation stopped
Data flash memory
Operation stopped
RAM
Operation stopped
Port (latch)
High-impedanceNote
Timer array unit
Operation stopped
RTC
Resets other than the POR reset: Operable POR reset: Only the values of calendar-related registers are retained.
32-bit interval timer
Operation stopped
Watchdog timer
Clock output/buzzer output
A/D converter
D/A converter
Comparator
Serial array unit
Serial interface IICA
Serial interface UARTA
Remote control signal receiver
Data transfer controller (DTC)
SNOOZE mode sequencer
Logic and event link controller (ELCL)
Power-on-reset function
Detection operation possible
Voltage detection function
LVD0: LVD0 operation is possible following an LVD0 reset but is stopped following other types of reset.
LVD1: Operation stopped
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CHAPTER 24 RESET FUNCTION
Table 24 - 1 Operating States during a Reset (2/2)
Item
Operating State during a Reset
External interrupt
Operation stopped
Key interrupt function
Capacitive sensing unit (CTSU)
CRC operation function
High-speed CRC
Generalpurpose CRC
Illegal-memory access detection function
RAM parity error detection function
RAM guard function
SFR guard function
Note
P40 and P130 become the following states.
· P40: High-impedance during the external reset period or reset period by the POR. High level during other types of reset
(connected to the on-chip pull-up resistor).
· P130: Low-level output during the reset period
Remark
fIH: High-speed on-chip oscillator clock fIM: Middle-speed on-chip oscillator clock fXT: XT1 oscillation clock fIL: Low-speed on-chip oscillator clock
fX: X1 oscillation clock fEX: External main system clock fEXS: External subsystem clock
Table 24 - 2 States of the Hardware Blocks after a Reset is Released
Program counter (PC)
Hardware
Stack pointer (SP) Program status word (PSW)
State after a Reset is Released The contents of the reset vector table (0000H, 0001H) are set.Note Undefined 06H
RAM
Data memory
Undefined
General-purpose registers
Undefined
Note
The contents of the PC are undefined during a reset and until the clock oscillation becomes stable after the reset is released.
Remark For the states of the special function registers (SFRs) after a reset is released, see 3.1.4 Special function register (SFR) area and 3.1.5 Extended special function register (2nd SFR: 2nd special function register) area.
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CHAPTER 24 RESET FUNCTION
24.2
Registers to Control the Reset Function
The following registers are used to control the reset function.
· Reset control flag register (RESF) · Power-on-reset status register (PORSR) · Peripheral reset control register 0 (PRR0) · Peripheral reset control register 1 (PRR1)
24.2.1 Reset control flag register (RESF)
Many internal reset generation sources exist in the RL78 microcontroller. The reset control flag register (RESF) is used to indicate which source has generated the reset request. The RESF register can be read by an 8-bit memory manipulation instruction. The flags TRAP, WDTRF, RPERF, IAWRF, and LVIRF are automatically cleared by any of the following event. Reset input via the RESET pin Reset by the power-on-reset (POR) circuit The RESF register is accessed.
Figure 24 - 4 Format of Reset Control Flag Register (RESF)
Address: After reset: R/W:
FFFA8H UndefinedNote 1 R
Symbol
7
6
RESF TRAP
0
5
4
3
2
1
0
WDTRF
0
RPERF
IAWRF
TRAP 0 1
Internal reset request by execution of illegal instructionNote 2 Internal reset request is not generated, or the RESF register is cleared. Internal reset request is generated.
0 LVIRF
WDTRF 0 1
Internal reset request by watchdog timer (WDT) Internal reset request is not generated, or the RESF register is cleared. Internal reset request is generated.
RPERF 0 1
Internal reset request t by RAM parity error Internal reset request is not generated, or the RESF register is cleared. Internal reset request is generated.
IAWRF 0 1
Internal reset request t by illegal-memory access Internal reset request is not generated, or the RESF register is cleared. Internal reset request is generated.
LVIRF 0 1
Internal reset request by voltage detector (LVD0 or LVD1) Internal reset request is not generated, or the RESF register is cleared. Internal reset request is generated.
Note 1. Note 2.
The value after reset varies depending on the reset source. See Table 24 - 3. In normal operation, executing the instruction code FFH triggers an internal reset, but this is not the case during emulation by the in-circuit emulator or on-chip debugging emulator.
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CHAPTER 24 RESET FUNCTION
Caution 1. Do not read data by a 1-bit memory manipulation instruction. Caution 2. When enabling RAM parity error resets (RPERDIS = 0), be sure to initialize the used RAM area at data
access or the used RAM area + 10 bytes at execution of instruction from the RAM area. Reset generation enables RAM parity error resets (RPERDIS = 0). For details, see 27.3.4 RAM parity error detection.
The state of the RESF register when a reset request is generated is shown in Table 24 - 3.
Table 24 - 3 State of the RESF Register when Reset Request is Generated
Reset Source
Reset by
Execution of
Reset by RAM
RESET Input Reset by POR
Reset by WDT
Illegal
Parity Error
Flag
Instruction
Reset by IllegalMemory Access
TRAP
Cleared (0)
Cleared (0)
Set (1)
Retained
Retained
Retained
WDTRF
Retained
Set (1)
RPERF
Retained
Set (1)
IAWRF
Retained
Set (1)
LVIRF
Retained
Reset by LVD0 or LVD1 Retained
Set (1)
The RESF register is automatically cleared after it is read by using an 8-bit memory manipulation instruction. Figure 24 - 5 shows the procedure for checking a reset source.
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RL78/G23 Figure 24 - 5 Example of Procedure for Checking Reset Source
After reset acceptance
CHAPTER 24 RESET FUNCTION
Read RESF register
Read the RESF register (clear the RESF register) and store the value of the RESF register in any RAM.
TRAP of RESF
Yes
register = 1?
No
WDTRF of RESF register = 1?
Internal reset request by the execution of the illegal instruction
generated
Yes
No
RPERF of RESF register = 1?
Internal reset request by the watchdog timer generated
Yes
No
IAWRF of RESF register = 1?
Internal reset request by the RAM parity error generated
Yes
No
LVIRF of RESF register = 1?
Internal reset request by the illegal-memory access generated
Yes
No
Power-on-reset/ external reset generated
Internal reset request by the voltage detector generated
The above flow is an example of the procedure for checking a reset source.
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CHAPTER 24 RESET FUNCTION
24.2.2 Power-on-reset status register (PORSR)
The PORSR register is used to check the occurrence of a power-on reset. Writing 1 to bit 0 (PORF) of the PORSR register enables this function. Writing 0 to the bit has no effect. Write 1 to the PORF bit in advance to enable checking of the occurrence of a power-on reset. The PORSR register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a power-on reset.
Caution 1. The PORSR register is reset only by a power-on reset; it retains the value when a reset caused by another source occurs.
Caution 2. If the PORF bit is set to 1, it guarantees that no power-on reset has occurred, but it does not guarantee that the RAM value is retained.
Figure 24 - 6 Format of Power-on-Reset Status Register (PORSR)
Address: After reset: R/W:
F00F9H 00H R/W
Symbol
7
6
5
4
3
2
1
<0>
PORSR
0
0
0
0
0
0
0
PORF
PORF 0 1
Checking occurrence of power-on reset A value 1 has not been written, or a power-on reset has occurred. No power-on reset has occurred.
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CHAPTER 24 RESET FUNCTION
24.2.3 Peripheral reset control register 0 (PRR0)
The PRR0 register is used to control resetting of the on-chip peripheral modules. Each bit in this register controls resetting and release from the reset state of the corresponding on-chip peripheral module. The PRR0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Figure 24 - 7 Format of Peripheral Reset Control Register 0 (PRR0)
Address: After reset: R/W:
F00F1H 00H R/W
Symbol
7
PRR0
0
<6>
<5>
<4>
<3>
<2>
<1>
<0>
IICA1RES ADCRES IICA0RES SAU1RES SAU0RES TAU1RES TAU0RES
PRR0n
Control resetting of the on-chip peripheral modules
0
The corresponding on-chip peripheral module is released from the reset state.
1
The corresponding on-chip peripheral module is in the reset state.
· The SFRs for use with the corresponding on-chip peripheral module are initialized.
Remark n = 0 to 6
The on-chip peripheral modules controlled by individual bits are as follows.
Table 24 - 4 On-chip Peripheral Modules Controlled by Individual Bits in PRR0
Bit
Bit Name
6
IICA1RES
5
ADCRES
4
IICA0RES
3
SAU1RES
2
SAU0RES
1
TAU1RES
0
TAU0RES
Caution
Be sure to set the following bits to 0. 30-, 32-, 36-, and 40-pin products: Bits 6 and 1 44-, 48-, 52-, and 64-pin products: Bit 1
Controlled On-chip Peripheral Modules Serial interface IICA1 A/D converter Serial interface IICA0 Serial array unit 1 Serial array unit 0 Timer array unit 1 Timer array unit 0
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CHAPTER 24 RESET FUNCTION
24.2.4 Peripheral reset control register 1 (PRR1)
The PRR1 register is used to control resetting of the on-chip peripheral modules. Each bit in this register controls resetting and release from the reset state of the corresponding on-chip peripheral module. The PRR1 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Figure 24 - 8 Format of Peripheral Reset Control Register 1 (PRR1)
Address: After reset: R/W:
F00FBH 00H R/W
Symbol
<7>
<6>
<5>
<4>
3
PRR1 DACRES SMSRES CMPRES TML32RES
0
2
<1>
<0>
0
REMCRES CTSURES
PRR1n
Control resetting of the on-chip peripheral modules
0
The corresponding on-chip peripheral module is released from the reset state.
1
The corresponding on-chip peripheral module is in the reset state.
· The SFRs for use with the corresponding on-chip peripheral module are initialized.
Remark n = 0, 1, 4 to 7
The on-chip peripheral modules controlled by individual bits are as follows.
Table 24 - 5 On-chip Peripheral Modules Controlled by Individual Bits in PRR1
Bit
Bit Name
Controlled On-chip Peripheral Modules
7
DACRES
D/A converter
6
SMSRES
SNOOZE mode sequencer
5
CMPRES
Comparator
4
TML32RES
32-bit interval timer
1
REMCRES
Remote control signal receiver
0
CTSURES
Capacitive sensing unit
Caution 1. Be sure to set the following bit to 0. 30-pin products: Bit 1
Caution 2. The UARTAENn bit in the ASIMAn0 register is used to control resetting of the UARTA. For details, see 17.2.4 Operation mode setting register 0 (ASIMAn0) (n = 0, 1).
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CHAPTER 25 POWER-ON-RESET CIRCUIT (POR)
CHAPTER 25 POWER-ON-RESET CIRCUIT (POR)
25.1
Functions of Power-on-reset Circuit
The power-on-reset circuit (POR) has the following functions.
· Generates internal reset signal at power on. The reset signal is released when the supply voltage (VDD) exceeds the detection voltage (VPOR). Note that the reset state must be retained until the operating voltage becomes in the range defined in 37.4 AC Characteristics. This is done by utilizing LVD0 or controlling the externally input reset signal.
· Compares supply voltage (VDD) and detection voltage (VPDR), generates internal reset signal when VDD < VPDR. Note that, after power supply is turned off, this LSI should be placed in the STOP mode, or in the reset state by utilizing LVD0 or externally input reset signal, before the operating voltage falls below the range defined in 37.4 AC Characteristics. When restarting the operation, make sure that the operating voltage has returned within the range of operation.
Caution
If an internal reset signal is generated by the power-on-reset circuit, the reset control flag register (RESF) and power-on-reset status register (PORSR) are cleared to 00H.
Remark 1. The RL78 microcontroller incorporates multiple hardware functions that generate an internal reset signal. A flag that indicates the reset source is located in the reset control flag register (RESF) for when an internal reset signal is generated by the watchdog timer (WDT), voltage detector (LVD), illegal instruction execution, RAM parity error, or illegal-memory access. The RESF register is not cleared to 00H and the flag is set to 1 when an internal reset signal is generated by the watchdog timer (WDT), voltage detector (LVD), illegal instruction execution, RAM parity error, or illegal-memory access. For details of the RESF register, see CHAPTER 24 RESET FUNCTION.
Remark 2. The power-on-reset status register (PORSR) is used to check the occurrence of an internal reset from the power-on-reset circuit. For details of the PORSR register, see CHAPTER 24 RESET FUNCTION.
Remark 3. VPOR: POR power supply rise detection voltage VPDR: POR power supply fall detection voltage For details, see 37.6.5 POR circuit characteristics.
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CHAPTER 25 POWER-ON-RESET CIRCUIT (POR)
25.2
Configuration of Power-on-reset Circuit
The block diagram of the power-on-reset circuit is shown in Figure 25 - 1.
Figure 25 - 1 Block Diagram of Power-on-reset Circuit
VDD
VDD
+ -
Reference voltage
source
Internal reset signal
25.3
Operation of Power-on-reset Circuit
The timing of generation of the internal reset signal by the power-on-reset circuit and voltage detector is shown on the following pages.
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Figure 25 - 2 Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (1/2) (1) When the externally input reset signal on the RESET pin is used
Supply voltage (VDD)
Lower limit voltage for guaranteed operation VPOR, VPDR = 1.50 V (typ.) 0 V
Note 5
Note 5
<R>
RESET pin
At least 10 µs
Wait for oscillation accuracy stabilization Note 1
Wait for oscillation accuracy stabilization Note 1
High-speed on-chip oscillator clock (fIH)
High-speed system clock (fMX)
(when X1 oscillation is selected)
CPU Operation stops
Internal reset signal
Starting oscillation is specified by software
Reset processing time
when external reset is released. Note 3
Normal operation (high-speed on-chip oscillator clock) Note 2
Voltage stabilization wait 4.0 ms (typ.), 9.9 ms (max.)
Starting oscillation is specified by software
Reset period (oscillation stop)
Normal operation (high-speed on-chip oscillator clock) Note 2
Reset processing time when external reset is released. Note 4
Operation stops
Note 1. Note 2. Note 3.
Note 4. Note 5.
The internal reset processing time includes the oscillation accuracy stabilization time of the high-speed on-chip oscillator clock. The high-speed on-chip oscillator clock and a high-speed system clock or subsystem clock can be selected as the CPU clock. To use the X1 clock, use the oscillation stabilization time counter status register (OSTC) to confirm the lapse of the oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse of the stabilization time. The time until normal operation starts includes the following reset processing time when the external reset is released (release from the first external reset following release from the POR state) after the RESET signal is driven high (1) as well as the voltage stabilization wait time after VPOR (1.50 V, typ.) is reached. With the LVD circuit in use: 0.506 ms (typ.), 0.694 ms (max.) With the LVD circuit not in use: 0.201 ms (typ.), 0.335 ms (max.) The reset processing times in the case of the second or subsequent external reset following release from the POR state are listed below. With the LVD circuit in use: 0.476 ms (typ.), 0.616 ms (max.) With the LVD circuit not in use: 0.170 ms (typ.), 0.257 ms (max.) After power is supplied, the reset state must be retained until the operating voltage becomes in the range defined in 37.4 AC Characteristics. This is done by controlling the externally input reset signal. After power supply is turned off, this LSI should be placed in the STOP mode, or in the reset state by utilizing the voltage detection circuit or externally input reset signal, before the voltage falls below the range of operation. When restarting the operation, make sure that the operating voltage has returned within the range of operation.
Caution For power-on reset, be sure to use the externally input reset signal on the RESET pin when LVD0 is off. For details, see CHAPTER 26 VOLTAGE DETECTOR (LVD).
Remark VPOR: POR power supply rise detection voltage VPDR: POR power supply fall detection voltage
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CHAPTER 25 POWER-ON-RESET CIRCUIT (POR)
Figure 25 - 2 Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (2/2) (2) LVD0 reset mode (option byte 000C1H: LVD0SEL = 1)
<R>
Supply voltage (VDD) VLVD0
Lower limit voltage for guaranteed operation
VPOR, VPDR = 1.50 V (typ.)
0 V
Wait for oscillation accuracy stabilization Note 1
Wait for oscillation accuracy stabilization Note 1
High-speed on-chip oscillator clock (fIH)
High-speed system clock (fMX) (when X1 oscillation
is selected)
CPU Operation stops
Starting oscillation is specified by software
Starting oscillation is specified by software
Normal operation (high-speed on-chip oscillator clock) Note 2
LVD reset processing time Note 3 Voltage stabilization wait + POR reset processing time 4.5 ms (typ.), 10.6 ms (max.)
Reset period (oscillation stop)
Normal operation Reset period (high-speed on-chip (oscillation oscillator clock) Note 2 stop)
LVD reset processing time Note 4
Internal reset signal
Note 1. Note 2. Note 3. Note 4.
The internal reset processing time includes the oscillation accuracy stabilization time of the high-speed on-chip oscillator clock. The high-speed on-chip oscillator clock and a high-speed system clock or subsystem clock can be selected as the CPU clock. To use the X1 clock, use the oscillation stabilization time counter status register (OSTC) to confirm the lapse of the oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse of the stabilization time. The time until normal operation starts includes the following LVD reset processing time after the LVD0 detection level (VLVD0) is reached as well as the voltage stabilization wait + POR reset processing time after the VPOR (1.50 V, typ.) is reached. LVD reset processing time: 0 to 0.041 ms (max.) When the power supply voltage is below the lower limit for operation and the power supply voltage is then restored after an internal reset is generated only by the voltage detector (LVD0), the following LVD reset processing time is required after the LVD0 detection level (VLVD0) is reached. LVD reset processing time: 0.040 ms (typ.), 0.041 ms (max.)
Remark 1. VLVDH, VLVDL: LVD detection voltage VPOR: POR power supply rise detection voltage VPDR: POR power supply fall detection voltage
Remark 2. When the LVD0 interrupt mode is selected (option byte 000C1H: LVD0SEL = 0), the time until normal operation starts after power is turned on is the same as the time specified in Note 3 of Figure 25 - 2 (2).
Remark 3. Operation of LVD1 is stopped when power is initially supplied. LVD1 is also stopped by an internal reset.
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CHAPTER 26 VOLTAGE DETECTOR (LVD)
CHAPTER 26 VOLTAGE DETECTOR (LVD)
26.1
Functions of Voltage Detector
Enabling, selecting the operation mode, and setting the detection voltage (VLVD0) for voltage detector 0 (LVD0) are done by using an option byte (000C1H). On the other hand, enabling, selecting the operation mode, and setting the detection voltage (VLVD1) for voltage detector 1 (LVD1) are done by using the voltage detection level register. The voltage detectors have the following functions.
· LVD0 and LVD1 compare the supply voltage (VDD) with the detection voltage (VLVD0, VLVD1), and generate an internal reset or internal interrupt signal.
· The option byte is used to select the detection voltage (VLVD0) for LVD0 from among 6 voltages (for details, see CHAPTER 32 OPTION BYTES).
· The voltage detection level register is used to select the detection voltage (VLVD1) for LVD1 from among 18 voltages.
· Operable in STOP mode. · After power is supplied, the reset state must be retained until the operating voltage becomes in the range defined in
37.4 AC Characteristics. This is done by utilizing LVD0 or controlling the externally input reset signal. After the power supply is turned off, this LSI should be placed in the STOP mode, or placed in the reset state by utilizing LVD0 or controlling the externally input reset signal before the voltage falls below the operating range.
The internal reset and internal interrupt signals are generated in each mode as follows.
Reset mode LVD0
Reset mode LVD1
Deasserts an internal reset signal on detecting VDD VLVD0. Generates an internal reset on detecting VDD < VLVD0 and retains the reset state until VDD VLVD0 is detected.
Generates an internal reset on detecting VDD < VLVD1 after LVD1 operation has been enabled.
Interrupt mode LVD0
Interrupt mode LVD1
Retains the state of an internal reset by the LVD immediately after a reset until VDD VLVD0. Releases the LVD internal reset by detecting VDD VLVD0. Generates an interrupt request signal (INTLVI) by detecting VDD < VLVD0 or VDD VLVD0 after the LVD internal reset is released.
Generates an interrupt request signal (INTLVI) on detecting VDD < VLVD1 after LVD1 operation has been enabled. After the first detection, generates an interrupt request signal (INTLVI) on detecting VDD < VLVD1 or VDD VLVD1.
While LVD0 or LVD1 is operating, whether the supply voltage is no less than or less than the detection level can be
<R>
checked by reading the voltage detection flag (LVDnF: bits 0 and 1 of the voltage detection register (LVIM)).
Bit 0 (LVIRF) of the reset control flag register (RESF) is set to 1 if reset occurs. For details of the RESF register, see
CHAPTER 24 RESET FUNCTION.
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CHAPTER 26 VOLTAGE DETECTOR (LVD)
26.2
Configuration of Voltage Detector
The block diagram of the voltage detector is shown in Figure 26 - 1.
Figure 26 - 1 Block Diagram of LVD0
VDD
<R>
Voltage detection level selector
VDD
VLVD0
N-ch
Internal reset signal 0
Internal reset signal
Controller
+
-
Reference voltage source
Internal reset signal 1
Internal interrupt signal 0
LVD0SEL of the option byte (000C1H)
INTLVI Internal interrupt signal 1
LVD1SEL of the voltage Detector detection level register (LVIS)
LVD0V2 to LVD0V0 of the option byte (000C1H)
LVD0EN of the option byte (000C1H)
LVD0F DLVD0F
DLVD0FCLR
Voltage detection register (LVIM)
LVD detection flag clearing register (LVDFCLR )
Internal bus
Figure 26 - 2 Block Diagram of LVD1
VDD
VDD
Voltage detection level selector
VLVD1
N-ch
+
-
Reference voltage source
Controller
Internal reset signal 1
Internal reset signal
Internal reset signal 0
Internal interrupt signal 1
INTLVI
Internal interrupt signal 0
Detector
<R>
LVD1EN LVD1SEL LVD1V4 LVD1V3 LVD1V2 LVD1V1 LVD1V0
LVISEN LVD1F DLVD1F
DLVD1FCLR
Voltage detection level register (LVIS)
Voltage detection register (LVIM)
LVD detection flag clearing register (LVDFCLR)
Internal bus
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CHAPTER 26 VOLTAGE DETECTOR (LVD)
26.3
Registers to Control the Voltage Detector
The following registers are used to control the voltage detector.
· User option byte (000C1H/040C1H): See CHAPTER 32 OPTION BYTES. · Voltage detection register (LVIM) · LVD detection flag clearing register (LVDFCLR) · Voltage detection level register (LVIS)
26.3.1 Voltage detection register (LVIM)
This register is used to specify whether to enable or disable rewriting the voltage detection level register (LVIS), as well
<R>
as to check the states of LVD0 and LVD1.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 26 - 3 Format of Voltage Detection Register (LVIM)
Address: After reset: R/W:
FFFA9H 00HNote 1 R/WNotes 2, 3
Symbol
<7>
6
5
4
<3>
<2>
<1>
<0>
LVIM LVISEN
0
0
0
DLVD1F DLVD0F
LVD1F
LVD0F
LVISEN
0 1Note 4
Specification of whether to enable or disable rewriting the voltage detection level register (LVIS)
Rewriting of the LVIS register is disabled. Rewriting of the LVIS register is enabled (reset and interrupt generation by LVD1 are masked).
DLVDnF 0 1
LVDn detection interrupt flag (n = 0, 1) The given LVDn interrupt has not been detected. The given LVDn interrupt has been detected.
<R>
LVDnF 0 1
Voltage detection flag (n = 0, 1) Supply voltage (VDD) detection voltage (VLVDn), or when LVD is off Supply voltage (VDD) < detection voltage (VLVDn)
Note 1.
Note 2. Note 3. Note 4.
The value after a reset is 01H when LVD0 operation is enabled and the power supply voltage (VDD) is less than the detection voltage (VLVD0). Bits 0 and 1 are read-only. Bits 2 and 3 are read-only. These bits are cleared by using the LVD detection flag clearing register (LVDFCLR). While the LVISEN bit is 1, the reset and interrupt generation by LVD1 are masked. Therefore, clear the LVISEN bit to 0 after having written a new value to the LVIS register.
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CHAPTER 26 VOLTAGE DETECTOR (LVD)
26.3.2 LVD detection flag clearing register (LVDFCLR)
This register is used to clear the interrupt detection flags (DLVD0F and DLVD1F) of the voltage detection register (LVIM). The LVDFCLR register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Figure 26 - 4 Format of LVD Detection Flag Clearing Register (LVDFCLR)
Address: After reset: R/W:
F0218H 00H R/W
Symbol
7
6
5
4
<3>
<2>
1
0
LVDFCLR
0
0
0
0
DLVD1FCLR DLVD0FCLR
0
0
DLVD1FCLRNote
Clearing DLVD1F
0
No effect
1
Writing 1 to this bit clears the DLVD1F flag.
DLVD0FCLRNote
Clearing DLVD0F
0
No effect
1
Writing 1 to this bit clears the DLVD0F flag.
Note
Only 1 can be written to this bit. Writing 0 has no effect. The bit is read as 0 even after 1 has been written to it.
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CHAPTER 26 VOLTAGE DETECTOR (LVD)
26.3.3 Voltage detection level register (LVIS)
This register is used to select the voltage detection level for LVD1. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 19H.
Figure 26 - 5 Format of Voltage Detection Level Register (LVIS)
Address: After reset: R/W:
FFFAAH 19H R/W
Symbol
<7>
<6>
5
LVIS LVD1EN LVD1SEL
0
4 LVD1V4
3 LVD1V3
2 LVD1V2
1 LVD1V1
0 LVD1V0
LVD1EN
0
Operation stopped
1
Operation enabled
Enabling operation of LVD1
LVD1SEL
0
Interrupt mode
1
Reset mode
Operation mode of LVD1
<R>
<R> <R>
LVD1V4 LVD1V3 LVD1V2 LVD1V1 LVD1V0
Detection voltages for LVD1Notes 1, 3, 4 Rising edge Falling edge
1
1
1
1
1
VLVD117
1.67 VNote 2 1.63 VNote 2
1
1
1
1
0
VLVD116
1.78 VNote 2 1.74 VNote 2
1
1
1
0
1
VLVD115
1.88 VNote 2 1.84 VNote 2
1
1
1
0
0
VLVD114
1.98 V
1.94 V
1
1
0
1
1
VLVD113
2.09 V
2.04 V
1
1
0
1
0
VLVD112
2.20 V
2.15 V
1
1
0
0
1
VLVD111
2.30 V
2.25 V
1
1
0
0
0
VLVD110
2.40 V
2.35 V
1
0
1
1
1
VLVD19
2.50 V
2.45 V
1
0
1
1
0
VLVD18
2.66 V
2.60 V
1
0
1
0
1
VLVD17
2.82 V
2.76 V
1
0
1
0
0
VLVD16
2.97 V
2.91 V
1
0
0
1
1
VLVD15
3.13 V
3.06 V
1
0
0
1
0
VLVD14
3.35 V
3.27 V
1
0
0
0
1
VLVD13
3.55 V
3.47 V
1
0
0
0
0
VLVD12
3.75 V
3.67 V
0
1
1
1
1
VLVD11
3.96 V
3.88 V
0
1
1
1
0
VLVD10
4.16 V
4.08 V
Note 1. Note 2. Note 3.
The LVD1V4 to LVD1V0 bits can only be rewritten once after release from the reset state. This setting can only be used when LVD0 is off. When setting LVD0 to reset mode, set the detection voltage of LVD1 higher than the detection voltage of LVD0.
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CHAPTER 26 VOLTAGE DETECTOR (LVD)
<R>
Note 4.
If LVD0 is set to interrupt mode and the LVD0 detection voltage is greater than the LVD1 detection voltage, LVD0 becomes undefined after the LVD1 setting following release from the reset state.
Caution When the values in the LVIS register are to be changed, do so according to the procedure described in Figures 26 - 10 and 26 - 11.
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CHAPTER 26 VOLTAGE DETECTOR (LVD)
26.4
Operation of Voltage Detector
26.4.1 When used as reset mode
Enabling, selecting the operation mode (reset mode: LVD0SEL = 1), and setting the detection voltage (VLVD0) for LVD0 are done by using an option byte (000C1H). On the other hand, enabling, selecting the operation mode (reset mode: LVD1SEL = 1), and setting the detection voltage (VLVD1) for LVD1 are done by using the voltage detection level register (LVIS).
· Operation in LVD reset mode
When LVD0 is set for the reset mode (the value of the LVD0SEL bit in the option byte is 1), the state of the internal
reset being applied by LVD0 is retained until the power supply voltage (VDD) exceeds the rising voltage detection level
(VLVD0) after power has been supplied. The internal reset is released when the supply voltage (VDD) exceeds the rising
voltage detection level (VLVD0).
At the fall of the operating voltage, an internal reset by LVD0 is generated when the power supply voltage (VDD) falls
below the falling voltage detection level (VLVD0).
Operation of LVD1 is stopped when power is initially supplied. When LVD1 operation is enabled, it generates an
internal reset when the power supply voltage (VDD) falls below the voltage detection level (VLVD1). If operation of LVD1
is enabled while the power supply voltage (VDD) is lower than the voltage detection level (VLVD1), it generates an
<R>
internal reset at the time its operation is enabled. If LVD1 is set for reset mode, LVD0 is placed in interrupt mode. In
addition, the generation of an internal reset by LVD1 places LVD0 in reset mode.
LVD1 detection voltage can only be set once after release from the reset state.
Figure 26 - 6 shows the timing of the internal reset signal generated in the LVD reset mode.
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<R> Figure 26 - 6 Timing of LVD0 Internal Reset Signal Generation
Supply voltage (VDD) VLVD0
Lower limit of operating voltage
VPOR, VPDR = 1.50 V (typ.)
LVD reset processing time
Delay for detection
LVD0F flag LVIRF flag (RESF register) LVD reset signal POR reset signal Internal reset signal Port pin (P130)
Set by software
CHAPTER 26 VOLTAGE DETECTOR (LVD)
Delay for detection
Delay for detection
Time Clear Clear
Cleared by software
Set by software
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RL78/G23 <R> Figure 26 - 7 Timing of LVD1 Internal Reset Signal Generation
Supply voltage (VDD) VLVD1 VLVD0
Lower limit of operating voltage
VPOR, VPDR = 1.50 V (typ.)
LVD reset processing time
Delay for detection
<R>
LVD1EN bit LVD1F flag LVIRF flag (RESF register) LVD reset signal POR reset signal Internal reset signal Port pin (P130)
Remark LVD0: Reset mode
Set by software
CHAPTER 26 VOLTAGE DETECTOR (LVD)
Delay for detection
Delay for detection
Time Clear Cleared by software Set by software
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CHAPTER 26 VOLTAGE DETECTOR (LVD)
26.4.2 When used as interrupt mode
Enabling, selecting the operation mode (interrupt mode: LVD0SEL = 0), and setting the detection voltage (VLVD0) for LVD0 are done by using an option byte (000C1H). On the other hand, enabling, selecting the operation mode (interrupt mode: LVD1SEL = 0), and setting the detection voltage (VLVD1) for LVD1 are done by using the voltage detection level register (LVIS).
· Operation in LVD interrupt mode When LVD0 is set for the interrupt mode (the value of the LVD0SEL bit in the option byte is 0), the state of the internal reset being applied by LVD0 is retained until the power supply voltage (VDD) exceeds the rising voltage detection level (VLVD0) immediately after a reset has been generated. The internal reset is released when the power supply voltage (VDD) exceeds the rising voltage detection level (VLVD0). After the internal reset signal has been deasserted, LVD0 generates an interrupt request signal (INTLVI) if the power supply voltage (VDD) falls below the voltage detection level (VLVD0). Similarly, when the power supply voltage (VDD) rises above the voltage detection level (VLVD0), LVD0 also generates an interrupt request signal (INTLVI). When the voltage falls, this LSI should be placed in the STOP mode, or placed in the reset state by controlling the externally input reset signal, before the voltage falls below the operating voltage range defined in 37.4 AC Characteristics. When restarting the operation, make sure that the power supply voltage has returned within the operating voltage range. Operation of LVD1 is stopped when power is initially supplied. When LVD1 operation is enabled, it generates an interrupt request signal (INTLVI) when the power supply voltage (VDD) falls below the voltage detection level (VLVD1). Similarly, when the power supply voltage (VDD) rises above the voltage detection level (VLVD1), LVD1 also generates an interrupt request signal (INTLVI). Note that if operation of LVD1 is enabled while the power supply voltage (VDD) is lower than the voltage detection level (VLVD1), it generates an interrupt request signal (INTLVI) at the time its operation is enabled. LVD1 detection voltage can only be set once after release from the reset state.
Figure 26 - 8 shows the timing of the interrupt request signal generated in the LVD interrupt mode.
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CHAPTER 26 VOLTAGE DETECTOR (LVD)
<R> Figure 26 - 8 Timing of LVD0 Interrupt Signal Generation
Supply voltage (VDD) VLVD0
Lower limit of operating voltage
VPOR, VPDR = 1.50 V (typ.)
LVD reset processing time
Delay for detection
Note 2
LVIMK flag (interrupt mask) (set by software)
LVD0F flag
HNote 1 Cleared by software
INTLVI LVIIF flag DLVD0F flag
Delay for detection
Delay for detection
Note 2
Time
Clear
LVD reset signal POR reset signal
Cleared by software
Internal reset signal
Note 1. Note 2.
The LVIMK flag is set to 1 by reset signal generation. When the voltage falls, this LSI should be placed in the STOP mode, or placed in the reset state by controlling the externally input reset signal, before the voltage falls below the operating voltage range defined in 37.4 AC Characteristics. When restarting the operation, make sure that the operating voltage has returned within the operating voltage range.
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<R> Figure 26 - 9 Timing of LVD1 Interrupt Signal Generation
Supply voltage (VDD) VLVD1 VLVD0
Lower limit of operating voltage
VPOR, VPDR = 1.50 V (typ.)
LVD reset processing time
Delay for detection
LVIMK flag (interrupt mask) (set by software)
LVD1EN bit
H Note Cleared by software
LVD1F flag
INTLVI LVIIF flag DLVD1F flag
<R>
LVD reset signal
POR reset signal
Note
Internal reset signal
The LVIMK flag is set to 1 by reset signal generation.
Remark LVD0: Reset mode
CHAPTER 26 VOLTAGE DETECTOR (LVD)
Delay for detection
Delay for detection
Cleared by software
T im e
Cleared by software
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CHAPTER 26 VOLTAGE DETECTOR (LVD)
26.5
Points for Caution when the Voltage Detector is to be Used
(1) Voltage fluctuation when power is supplied In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the detection voltages for LVD0 or LVD1, the system may be repeatedly reset and released from the reset state. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
<Action> After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software counter that uses a timer, and then initialize the ports.
Figure 26 - 10Example of Software Processing If Supply Voltage Fluctuation is 50 ms or Less in Vicinity of the Detection Voltages for LVD0 or LVD1
Reset
Initialization processing <1>
See Figure 24 - 5 Example of Procedure for Checking Reset Source.
Setting timer array unit (to measure 50 ms)
e.g. fCLK = High-speed on-chip oscillator clock (4.04 MHz (max.)) Source: fMCK = (4.04 MHz (max.))/28,
where comparison value = 789: 50 ms
Timer starts (TSmn = 1).
Note
Clearing WDT
No
50 ms have passed?
(TMIFmn = 1?)
Yes
Initialization processing <2>
Initial setting for the ports, setting of the division ratio of the system clock, settings of the timer and A/D converter, etc.
Note
If reset is generated again during this period, initialization processing <2> is not started.
Remark m = 0, 1 n = 0 to 7
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CHAPTER 26 VOLTAGE DETECTOR (LVD)
(2) Delays from the time an LVD0 or LVD1 reset source condition is satisfied until an LVD0 or LVD1 reset has been generated and deasserted The delay is from the time the power supply voltage (VDD) becomes less than the LVD0 or LVD1 falling detection voltage (VLVD0 or VLVD1) until the LVD0 or LVD1 reset is generated. In the same way, the delay is from the time the LVD0 or LVD1 rising detection voltage (VLVD0 or VLVD1) becomes no greater than the power supply voltage (VDD) until the LVD0 or LVD1 reset is deasserted. See Figure 26 - 11.
Figure 26 - 11 Delays from the Time an LVD0 or LVD1 Reset Source Condition is Satisfied until an LVD0 or LVD1 Reset has been Generated and Deasserted
Supply voltage (VDD)
VLV D0 or VLV D 1
LVD reset signal
<1>
<1>: Delay for detection (300 µs (max.))
Time <1>
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CHAPTER 26 VOLTAGE DETECTOR (LVD)
(3) Turning power on when LVD0 is off Use the external rest input via the RESET pin when LVD0 is off. For an external reset, input a low level for 10 µs or more to the RESET pin. To perform an external reset upon power application, input a low level to the RESET pin, turn power on, continue to input a low level to the pin for 10 µs or more within the operating voltage range shown in 37.4 AC Characteristics, and then input a high level to the pin.
(4) Operating voltage fall when LVD0 is off or the interrupt mode is selected When the operating voltage falls with LVD0 off or with the interrupt mode selected, this LSI should be placed in the STOP mode, or placed in the reset state by controlling the externally input reset signal before the voltage falls below the operating voltage range defined in 37.4 AC Characteristics. When restarting the operation, make sure that the operating voltage has returned within the operating voltage range.
<R>
(5) Procedure for setting the LVD1 detection voltage
Follow the procedure below to set the LVD1 detection voltage. After step 3, LVD1 is enabled after the stabilization
waiting time (at least 500 s) has elapsed.
1. Set the LVISEN bit of the LVIM register to 1.
2. Set the LVD1EN bit of the LVIS register to 1 and change the setting of the LVD1V4 to LVD1V0 bits.
3. Set the LVISEN bit of the LVIM register to 0.
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CHAPTER 27 SAFETY FUNCTIONS
CHAPTER 27 SAFETY FUNCTIONS
27.1
Overview of Safety Functions
The RL78/G23 provides the following safety functions to comply with the IEC60730 and IEC61508 safety standards.
These safety functions enable the microcontroller to self-diagnose abnormalities and safely stop operating if an
abnormality is detected.
(1) Flash memory CRC operation (high-speed CRC, general-purpose CRC)
This detects data errors in the flash memory by performing CRC operations.
The following two CRC functions are provided in the RL78/G23 and they can be used according to the application
or purpose of use.
· High-speed CRC:
The CPU can be stopped and a high-speed check executed on its entire code flash
memory area during the initialization routine.
· General-purpose CRC: This can be used for checking various data in addition to the code flash memory area
while the CPU is running.
(2) Flash memory guard function
This prevents rewriting of data in the flash memory due to incorrect CPU operations.
(3) RAM parity error detection
This detects parity errors when reading RAM data.
(4) RAM guard function
This prevents rewriting of data in RAM due to incorrect CPU operations.
(5) SFR guard function
This prevents rewriting of data in the SFRs due to incorrect CPU operations.
(6) Illicit memory access detection
This detects illicit accesses to invalid memory areas (such as areas where no memory is allocated and areas to
which access is restricted).
(7) Guard function of invalid memory access detection control register (IAWCTL)
This prevents rewriting of the invalid memory access detection control register due to incorrect CPU operations.
(8) Frequency detection
This function allows a self-check of the CPU/peripheral hardware clock frequencies using the timer array unit.
(9) Testing of the A/D converter
This test checks whether or not the A/D converter is operating normally by converting the A/D converter's positive
and negative reference voltages, analog input channels (ANIxx), temperature sensor output voltage, and internal
reference voltage.
(10) Detection of the digital output signal level of the I/O pins
This is used to read the output level of an I/O pin when the pin is in the output mode.
(11) UART loopback
This is used to confirm that the transmit data is output normally by shutting off the TXDn and RXDn pins of UARTn
and the TXDAm and RXDAm pins of UARTAm from the outside and connecting them within the MCU to loop back
the output from the transmission shift register to the reception shift register.
Remark 1. n = 0 to 3, m = 0, 1 Remark 2. For usage examples of the safety functions complying with the IEC60730 and IEC61508 safety standards,
refer to the application notes IEC60730/60335 Self Test Library for RL78 MCU (R01AN1062 and R01AN1296).
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CHAPTER 27 SAFETY FUNCTIONS
27.2
Registers to Control the Safety Functions
The following registers are used to control the safety functions.
· Flash memory CRC control register (CRC0CTL) · Flash memory CRC operation result register (PGCRCL) · CRC input register (CRCIN) · CRC data register (CRCD) · Code flash memory guard register (GFLASH0) · Data flash memory guard register (GFLASH1) · Flash security area guard register (GFLASH2) · RAM parity error control register (RPECTL) · Invalid memory access detection control register (IAWCTL)
RAM guard function SFR guard function Illicit memory access detection · Guard register of IAWCTL register (GIAWCTL) · Timer input select register 0 (TIS0) · A/D test register (ADTES) · Analog input channel specification register (ADS) · Port mode select register (PMS) · UART loopback select register (ULBS)
The content of each register is described in 27.3 Operation of Safety Functions.
27.3
Operation of Safety Functions
27.3.1 Flash memory CRC operation function (high-speed CRC)
The IEC60730 standard mandates the checking of data in the flash memory, and recommends using a CRC to do it. The high-speed CRC provided in the RL78/G23 can be used to check the entire code flash memory area during the initialization routine. The high-speed CRC can be executed only when the program is allocated on the RAM and in the HALT mode of the main system clock. The high-speed CRC performs an operation by reading 32-bit data per clock from the flash memory while stopping the CPU. This function therefore can finish a check in a shorter time (for example, 512 µs@32 MHz with 64-Kbyte flash memory). The CRC generator polynomial used complies with "X16 + X12 + X5 + 1" of CRC-16-CCITT. The high-speed CRC operates in MSB first order from bit 31 to bit 0.
Caution
The CRC operation result might differ during on-chip debugging because the monitor program is allocated.
Remark
The operation result is different between the high-speed CRC and the general-purpose CRC, because the general-purpose CRC operates in LSB first order.
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CHAPTER 27 SAFETY FUNCTIONS
27.3.1.1 Flash memory CRC control register (CRC0CTL)
This register is used to control the operation of the high-speed CRC ALU, as well as to specify the operation range. The CRC0CTL register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 27 - 1 Format of Flash Memory CRC Control Register (CRC0CTL)
Address: After reset: R/W:
F02F0H 00H R/W
Symbol
<7>
6
CRC0CTL CRC0EN
0
5 FEA5
4 FEA4
3 FEA3
2 FEA2
1 FEA1
0 FEA0
CRC0EN
Control of CRC ALU operation
0
Stops the operation.
1
Starts the operation according to HALT instruction execution.
FEA5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FEA4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
FEA3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0
FEA2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1
FEA1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
FEA0
High-speed CRC operation range
0 0000H to 03FFBH (16 Kbytes - 4 bytes)
1 0000H to 07FFBH (32 Kbytes - 4 bytes)
0 0000H to 0BFFBH (48 Kbytes - 4 bytes)
1 0000H to 0FFFBH (64 Kbytes - 4 bytes)
0 0000H to 13FFBH (80 Kbytes - 4 bytes)
1 0000H to 17FFBH (96 Kbytes - 4 bytes)
0 0000H to 1BFFBH (112 Kbytes - 4 bytes)
1 0000H to 1FFFBH (128 Kbytes - 4 bytes)
0 0000H to 23FFBH (144 Kbytes - 4 bytes)
1 0000H to 27FFBH (160 Kbytes - 4 bytes)
0 0000H to 2BFFBH (176 Kbytes - 4 bytes)
1 0000H to 2FFFBH (192 Kbytes - 4 bytes)
0 0000H to 33FFBH (208 Kbytes - 4 bytes)
1 0000H to 37FFBH (224 Kbytes - 4 bytes)
0 0000H to 3BFFBH (240 Kbytes - 4 bytes)
1 0000H to 3FFFBH (256 Kbytes - 4 bytes)
0 0000H to 43FFBH (272 Kbytes - 4 bytes)
1 0000H to 47FFBH (288 Kbytes - 4 bytes)
0 0000H to 4BFFBH (304 Kbytes - 4 bytes)
1 0000H to 4FFFBH (320 Kbytes - 4 bytes)
0 0000H to 53FFBH (336 Kbytes - 4 bytes)
1 0000H to 57FFBH (352 Kbytes - 4 bytes)
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CHAPTER 27 SAFETY FUNCTIONS
FEA5 FEA4 FEA3 FEA2 FEA1 FEA0
High-speed CRC operation range
0
1
0
1
1
0 0000H to 5BFFBH (368 Kbytes - 4 bytes)
0
1
0
1
1
1 0000H to 5FFFBH (384 Kbytes - 4 bytes)
0
1
1
0
0
0 0000H to 63FFBH (400 Kbytes - 4 bytes)
0
1
1
0
0
1 0000H to 67FFBH (416 Kbytes - 4 bytes)
0
1
1
0
1
0 0000H to 6BFFBH (432 Kbytes - 4 bytes)
0
1
1
0
1
1 0000H to 6FFFBH (448 Kbytes - 4 bytes)
0
1
1
1
0
0 0000H to 73FFBH (464 Kbytes - 4 bytes)
0
1
1
1
0
1 0000H to 77FFBH (480 Kbytes - 4 bytes)
0
1
1
1
1
0 0000H to 7BFFBH (496 Kbytes - 4 bytes)
0
1
1
1
1
1 0000H to 7FFFBH (512 Kbytes - 4 bytes)
1
0
0
0
0
0 0000H to 83FFBH (528 Kbytes - 4 bytes)
1
0
0
0
0
1 0000H to 87FFBH (544 Kbytes - 4 bytes)
1
0
0
0
1
0 0000H to 8BFFBH (560 Kbytes - 4 bytes)
1
0
0
0
1
1 0000H to 8FFFBH (576 Kbytes - 4 bytes)
1
0
0
1
0
0 0000H to 93FFBH (592 Kbytes - 4 bytes)
1
0
0
1
0
1 0000H to 97FFBH (608 Kbytes - 4 bytes)
1
0
0
1
1
0 0000H to 9BFFBH (624 Kbytes - 4 bytes)
1
0
0
1
1
1 0000H to 9FFFBH (640 Kbytes - 4 bytes)
1
0
1
0
0
0 0000H to A3FFBH (656 Kbytes - 4 bytes)
1
0
1
0
0
1 0000H to A7FFBH (672 Kbytes - 4 bytes)
1
0
1
0
1
0 0000H to ABFFBH (688 Kbytes - 4 bytes)
1
0
1
0
1
1 0000H to AFFFBH (704 Kbytes - 4 bytes)
1
0
1
1
0
0 0000H to B3FFBH (720 Kbytes - 4 bytes)
1
0
1
1
0
1 0000H to B7FFBH (736 Kbytes - 4 bytes)
1
0
1
1
1
0 0000H to BBFFBH (752 Kbytes - 4 bytes)
1
0
1
1
1
1 0000H to BFFFBH (768 Kbytes - 4 bytes)
Remark
Other than the above
Setting prohibited
Input the expected CRC operation result value to be used for comparison in the lowest 4 bytes of the flash memory. Note that the operation range will thereby be reduced by 4 bytes.
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27.3.1.2 Flash memory CRC operation result register (PGCRCL)
This register holds the high-speed CRC operation results. The PGCRCL register can be set by a 16-bit memory manipulation instruction. The value of this register is 0000H following a reset.
Figure 27 - 2 Format of Flash Memory CRC Operation Result Register (PGCRCL)
Address: After reset: R/W:
F02F2H 0000H R/W
Symbol
15
14
13
12
11
10
9
PGCRCL PGCRC15 PGCRC14 PGCRC13 PGCRC12 PGCRC11 PGCRC10 PGCRC9
8 PGCRC8
7 PGCRC7
6 PGCRC6
5 PGCRC5
4 PGCRC4
3 PGCRC3
2 PGCRC2
1 PGCRC1
0 PGCRC0
PGCRC15 to PGCRC0
High-speed CRC operation results
0000H to FFFFH
Holds the high-speed CRC operation results.
Caution The PGCRCL register can only be written if CRC0EN (bit 7 of the CRC0CTL register) = 1.
Figure 27 - 3 shows the flowchart of flash memory CRC operation function (high-speed CRC).
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<Operation flow> Figure 27 - 3 Flowchart of Flash Memory CRC Operation Function (High-speed CRC)
Start Set FEA5 to FEA0 bits
; Stores the expected CRC operation result ; value in the lowest 4 bytes.
; Sets the CRC operation range.
Copy HALT and RET instructions to RAM and initialize 10 bytes
All xxMKx = 1
; Copies the HALT and RET instructions to the ; RAM to execute them in the RAM. ; Initializes the 10 bytes after the RET instruction.
; Masks all interrupts.
CRC0EN = 1
; Enables CRC operation.
PGCRCL = 0000H Execute CALL instruction Execute HALT instruction
; Initializes the CRC operation result register.
; Calls the address of the HALT instruction ; copied to the RAM.
; CRC operation starts by HALT instruction ; execution.
CRC operation completed? No
Yes Execute RET instruction
CRC0EN = 0
; When the CRC operation is complete, the HALT ; mode is released and control is returned ; from instruction execution in the RAM.
; Prohibits CRC operation.
Read the value of PGCRCL
Compare the value with the expected CRC value
Match Normal termination
; Reads the CRC operation result. ; Compares the value with the expected value ; stored in advance.
No match Abnormal termination
Caution 1. The CRC operation is executed only on the code flash. Caution 2. Store the expected CRC operation value in the area below the operation range in the code flash. Caution 3. The CRC operation is enabled by executing the HALT instruction in the RAM area.
Be sure to execute the HALT instruction in the RAM area.
The expected CRC value can be calculated by using the CS+ integrated development environment. See the CS+ Integrated Development Environment user's manual for details.
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27.3.2 CRC operation (general-purpose CRC)
To guarantee safety during operation, the IEC61508 standard mandates the checking of data even while the CPU is operating. The general-purpose CRC handles CRC operation as a peripheral module while the CPU is operating. The generalpurpose CRC can be used for checking various data in addition to the code flash memory area. The data to be checked can be specified by using software (a user-created program). The CRC calculation function in the HALT mode can be used only during DMA transfer. The general-purpose CRC can operate either in the main system clock operation mode or in the subsystem clock operation mode. The CRC generator polynomial used is "X16 + X12 + X5 + 1" of CRC-16-CCITT. The data to be input is inverted in bit order and then calculated to allow for LSB-first communication. For example, if the data 12345678H is sent from the LSB, values are written to the CRCIN register in the order of 78H, 56H, 34H, and 12H, enabling a value of 08F6H to be obtained from the CRCD register. This is the result obtained by executing a CRC operation on the bit rows shown below, which consist of the data 12345678H inverted in bit order.
Data set in CRCIN Bit representation data
78H
56H
34H
12H
0111 1000 0101 0110 0011 0100 0001 0010
Bit reverse
Bit reverse data Result data
0001 1110 0110 1010 0010 1100 0100 1000
Operation with polynomial
0110 1111 0001 0000
Bit reverse
CRCD data
0000 1000 1111 0110 (08F6H)
Obtained result
Caution
Because the debugger rewrites the software break setting line to a break instruction during program execution, the CRC operation result differs if a software break is set in the CRC operation target area.
27.3.2.1 CRC input register (CRCIN)
The CRCIN is an 8-bit register to set the CRC operation data of the general-purpose CRC. The possible setting range is 00H to FFH. The CRCIN register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 27 - 4 Format of CRC Input Register (CRCIN)
Address: After reset: R/W:
FFFACH 00H R/W
Symbol
7
6
5
4
3
2
1
0
CRCIN
Bits 7 to 0 00H to FFH Data input
Function
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27.3.2.2 CRC data register (CRCD)
This register holds the CRC operation result of the general-purpose CRC. The setting range is 0000H to FFFFH. After one clock cycle of the CPU/peripheral hardware clock (fCLK) has elapsed from the time CRCIN register was written to, the CRC operation result is stored in the CRCD register. The CRCD register can be set by a 16-bit memory manipulation instruction. The value of this register is 0000H following a reset.
Figure 27 - 5 Format of CRC Data Register (CRCD)
Address: After reset: R/W:
F02FAH 0000H R/W
Symbol
15
14
13
12
11
10
9
8
CRCD
7
6
5
4
3
2
1
0
Caution 1. Read the value written to the CRCD register before writing to the CRCIN register. Caution 2. If conflict between writing a value and storing the operation result in the CRCD register occurs, the
writing is ignored.
<Operation flow>
Figure 27 - 6 CRC Operation Function (General-Purpose CRC)
START Specify the start and end
addresses Write 0000H to CRCD register
Read data
Store data in CRCIN register
Address+1
; Stores the start and end addresses in a ; general-purpose register. ; Initializes the CRCD register. ; Reads 8-bit data of the corresponding address. ; Executes CRC calculation for the 8-bit data.
Last address? No
Yes 1 clock wait (fCLK)
Read CRCD register End
; Gets the CRC result.
; Compares the value ; with the stored ; expected value and ; confirms that the ; values match.
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27.3.3 Flash memory guard function
To ensure safe operation, the IEC60730 standard requires protecting flash memory from rewriting of its data due to incorrect CPU operations. The RL78/G23 has functionality to protect data in the code flash memory, data flash memory, and the security area in the flash memory. Enabling this function disables writing to the protected area of the flash memory. Reading from the protected area is possible.
27.3.3.1 Code flash memory guard register (GFLASH0)
This register is used to protect the code flash memory against being rewritten. To allow rewriting of the code flash memory, set the GFLASH0.GFL0 bit to 0. To protect the code flash memory, set the GFLASH0.GFL0 bit to 1. Be sure to confirm that the value has been set to 1 before reading from the code flash memory.
Figure 27 - 7 Format of Code Flash Memory Guard Register (GFLASH0)
Address: After reset: R/W:
F0488H 0000H R/W
Symbol
15
14
13
12
11
10
9
8
GFLASH0
RKEY[7:0]
7
6
5
4
3
2
1
0
GFL0
The RKEY[7:0] bits contain the key code to control rewriting of the GFLASH0 register. When rewriting the GFL0 bit, set RKEY[7:0] to 30H and then write to all 16 bits of this register at once. The RKEY[7:0] bits return 00H when read.
GFL0 0 1
Control of rewriting the code flash memory Disables protection of the code flash memory (rewriting is allowed). Enables protection of the code flash memory (rewriting is not allowed).
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27.3.3.2 Data flash memory guard register (GFLASH1)
This register is used to protect the data flash memory against being rewritten. To allow rewriting of the data flash memory, set the GFLASH1.GFL1 bit to 0. To protect the data flash memory, set the GFLASH1.GFL1 bit to 1. Be sure to confirm that the value has been set to 1 before reading from the data flash memory.
Figure 27 - 8 Format of Data Flash Memory Guard Register (GFLASH1)
Address: After reset: R/W:
F048AH 0000H R/W
Symbol
15
14
13
12
11
10
9
8
GFLASH1
RKEY[7:0]
7
6
5
4
3
2
1
0
GFL1
The RKEY[7:0] bits contain the key code to control rewriting of the GFLASH1 register. When rewriting the GFL1 bit, set RKEY[7:0] to C5H and then write to all 16 bits of this register at once. The RKEY[7:0] bits return 00H when read.
GFL1 0 1
Control of rewriting the data flash memory Disables protection of the data flash memory (rewriting is allowed). Enables protection of the data flash memory (rewriting is not allowed).
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27.3.3.3 Flash security area guard register (GFLASH2)
This register is used to protect the flash memory's security area, which holds the security settings. To allow rewriting of the flash memory's security area, set the GFLASH2.GFL2 bit to 0.
Figure 27 - 9 Format of Flash Security Area Guard Register (GFLASH2)
Address: After reset: R/W:
F048CH 0000H R/W
Symbol
15
14
13
12
11
10
9
8
GFLASH2
RKEY[7:0]
7
6
5
4
3
2
1
0
GFL2
The RKEY[7:0] bits contain the key code to control rewriting of the GFLASH2 register. When rewriting the GFL2 bit, set RKEY[7:0] to 9AH and then write to all 16 bits of this register at once. The RKEY[7:0] bits return 00H when read.
GFL2 0 1
Control of rewriting the flash memory's security area Disables protection of the security area in the flash memory (rewriting is allowed). Enables protection of the security area in the flash memory (rewriting is not allowed).
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27.3.4 RAM parity error detection
The IEC60730 standard mandates the checking of RAM data. A single-bit parity bit is therefore added to all 8-bit data in the RL78/G23's RAM. By using this RAM parity error detection, the parity bit is appended when data is written, and the parity is checked when the data is read. This function can also be used to trigger a reset when a parity error occurs.
27.3.4.1 RAM parity error control register (RPECTL)
This register is used to control the parity error generation check bit and reset generation due to parity errors. The RPECTL register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 27 - 10 Format of RAM Parity Error Control Register (RPECTL)
Address: After reset: R/W:
F00F5H 00H R/W
Symbol
<7>
6
5
4
3
2
1
<0>
RPECTL RPERDIS
0
0
0
0
0
0
RPEF
RPERDIS
0
Enables parity error resets.
1
Disables parity error resets.
Parity error reset mask flag
RPEF
Parity error status flag
0
No parity error has occurred.
1
A parity error has occurred.
Caution
The parity bit is appended when data is written, and the parity is checked when the data is read. Therefore, while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data access is to proceed before reading data. The RL78's CPU executes look-ahead due to the pipeline operation, the CPU might read an uninitialized RAM area that is allocated beyond the RAM used, which causes a RAM parity error. Therefore, while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the RAM area + 10 bytes when instructions are fetched from RAM areas.
Remark 1. The parity error reset is enabled by default (RPERDIS = 0). Remark 2. Even if the parity error reset is disabled (RPERDIS = 1), the RPEF flag will be set (1) if a parity error occurs. If
parity error resets are enabled (RPERDIS = 0) with RPEF set to 1, a parity error reset is generated when the RPERDIS bit is cleared to 0. Remark 3. The RPEF flag in the RPECTL register is set (1) when the RAM parity error occurs and cleared (0) by writing 0 to it or by any reset source. When RPEF = 1, the value is retained even if RAM for which no parity error has occurred is read. Remark 4. The general registers are not included for RAM parity error detection.
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RL78/G23 Figure 27 - 11 Flowchart of RAM Parity Check
Start of check
CHAPTER 27 SAFETY FUNCTIONS
RPERF = 1Note Yes No
Check RAM.
Parity error No generated?
Yes
Internal reset generated
Normal operation
RPERDIS = 1 Disable parity error reset.
Check RAM. Read RAM.
RPEF = 1
Yes
No
Check if parity error was generated.
RPERDIS = 0
Enable parity error reset.
RAM failure processing
Note
To check the state following an internal reset triggered by a RAM parity error, see CHAPTER 24 RESET FUNCTION.
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27.3.5 RAM guard function
To guarantee safe operation, the IEC61508 standard requires important data stored in the RAM to be protected even if a CPU malfunction occurs. The RL78/G23 has functionality to protect data in the specified memory space. Enabling this function disables writing to the specified area of the RAM. Reading from the specified area is possible.
27.3.5.1 Invalid memory access detection control register (IAWCTL)
This register is used to control the detection of illicit memory accesses, and protection of the RAM and SFRs. Use the GRAM1 and GRAM0 bits to protect the RAM. The IAWCTL register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 27 - 12 Format of Invalid Memory Access Detection Control Register (IAWCTL)
Address: After reset: R/W:
F0078H 00H R/W
Symbol IAWCTL
7 IAWEN
6
5
4
3
0
GRAM1 GRAM0
0
2 GPORT
1 GINT
0 GCSC
GRAM1 GRAM0
Protected area in the RAM Note
0
0
Disabled. Writing to the RAM is allowed.
0
1
128 bytes from the base address of the RAM
1
0
256 bytes from the base address of the RAM
1
1
512 bytes from the base address of the RAM
Note
The base address of the RAM differs depending on the size of the RAM in the product.
Remark The protection of the RAM by this register is only effective against accesses from the CPU, data transfer controller (DTC), and SNOOZE mode sequencer (SMS).
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27.3.6 SFR guard function
To guarantee safe operation, the IEC61508 standard requires important data stored in the SFRs to be protected even if a CPU malfunction occurs. The RL78/G23 provides functionality to protect the data in the control registers for use with the ports, interrupts, clock control, voltage detection, and RAM parity error detection. Enabling this function disables writing to the protected area of the SFRs. Reading from the protected area is possible.
27.3.6.1 Invalid memory access detection control register (IAWCTL)
This register is used to control the detection of illicit memory accesses and the protection of the RAM and SFRs. Use the GPORT, GINT, and GCSC bits to protect the SFRs. The IAWCTL register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 27 - 13 Format of Invalid Memory Access Detection Control Register (IAWCTL)
Address: After reset: R/W:
F0078H 00H R/W
Symbol IAWCTL
7 IAWEN
6
5
4
3
0
GRAM1 GRAM0
0
2 GPORT
1 GINT
0 GCSC
<R>
GPORT 0 1
Protection of the port control registers Disabled. Reading from and writing to the port control registers are allowed. Enabled. Writing to the port control registers is not allowed. Reading from them is allowed. [Protected SFRs] PMxx, PUxx, PIMxx, POMxx, PMCAxx, PMCTxx, PMCExx, PFOEx, PDIDISxx, CCDE, CCSm, PTDC Note
GINT 0 1
Protection of the interrupt control registers Disabled. Reading from and writing to the interrupt control registers are allowed. Enabled. Writing to the interrupt control registers is not allowed. Reading from them is allowed. [Protected SFRs] IFxx, MKxx, PRxx, EGPx, EGNx
GCSC
Protection of the clock, voltage detector, and RAM parity error detection control registers
0
Disabled. Reading from and writing to the the clock, voltage detector, and RAM parity error
detection control registers are allowed.
1
Enabled. Writing to the the clock, voltage detector, and RAM parity error detection control
registers is not allowed. Reading from them is allowed.
[Protected SFRs] CMC, CSC, OSTS, CKC, PERx, OSMC, LVIM, LVIS, RPECTL, CKSEL,
PRRx, MOCODIV, WKUPMD, PSMCR
Note
The port registers (Pxx) are not protected.
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27.3.7 Illicit memory access detection
The IEC60730 standard mandates checking that the CPU and interrupts are operating correctly. The RL78/G23 provides functionality to trigger a reset when an invalid memory area is accessed. Access to the areas indicated as "Not allowed" in Figure 27 - 14 is detected as illicit.
Figure 27 - 14 Illicit Access Areas
FFFFFH
FFF00H FFEFFH FFEE0H FFEDFH
Special function registers (SFRs) 256 bytes
General-purpose registers 32 bytes
RAM Note
zzzzzH
Mirror
F1000H F0FFFH
F0800H F07FFH
Data flash memory Reserved
Special function registers (2nd SFRs) 2 Kbytes
F0000H EFFFFH
EF000H EEFFFH
Whether or not access is allowed
Read
Write
Instruction fetch
Allowed
Not allowed Allowed
Allowed
Not allowed
Not allowed
Allowed
Allowed Not allowed
Allowed
Reserved
yyyyyH xxxxxH
Code flash memory Note 00000H See the next page for the details of Note in the figure.
Not allowed
Not allowed
Not allowed
Allowed
Allowed
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Note
The following table lists the capacity and address of the code flash memory and RAM, and the lowest address of the area to be detected as illicit when accessed of each product.
Products
Code flash memory (00000H to xxxxxH)
R7F100GxF (x = A, B, C, E, F, G, J, L)
R7F100GxG (x = A, B, C, E, F, G, J, L, M, P)
R7F100GxH (x = A, B, C, E, F, G, J, L, M, P)
R7F100GxJ (x = A, B, C, E, F, G, J, L, M, P, S)
R7F100GxK (x = F, G, J, L, M, P, S)
R7F100GxL (x = F, G, J, L, M, P, S)
R7F100GxN (x = F, G, J, L, M, P, S)
98304 × 8 bits (00000H to 17FFFH)
131072 × 8 bits (00000H to 1FFFFH)
196608 × 8 bits (00000H to 2FFFFH)
262144 × 8 bits (00000H to 3FFFFH)
393216 × 8 bits (00000H to 5FFFFH)
524288 × 8 bits (00000H to 7FFFFH)
786432 × 8 bits (00000H to BFFFFH)
RAM (zzzzzH to FFEFFH)
12288 × 8 bits (FCF00H to FFEFFH)
16384 × 8 bits (FBF00H to FFEFFH)
20480 × 8 bits (FAF00H to FFEFFH)
24576 × 8 bits (F9F00H to FFEFFH)
32768 × 8 bits (F7F00H to FFEFFH)
49152 × 8 bits (F3F00H to FFEFFH)
49152 × 8 bits (F3F00H to FFEFFH)
Lowest address of the area to be detected as illicit when accessed for reading or
instruction fetching (yyyyyH) 18000H
20000H
30000H
40000H
60000H
80000H
C0000H
27.3.7.1 Invalid memory access detection control register (IAWCTL)
This register is used to control the detection of illicit memory accesses and the protection of the RAM and SFRs. Use the IAWEN bit to protect the SFRs. The IAWCTL register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 27 - 15 Format of Invalid Memory Access Detection Control Register (IAWCTL)
Address: After reset: R/W:
F0078H 00H R/W
Symbol IAWCTL
7 IAWEN
6
5
4
3
0
GRAM1 GRAM0
0
2 GPORT
1 GINT
0 GCSC
IAWENNote
Control of illicit memory access detection
0
Disables the detection of illicit memory accesses.
1
Enables the detection of illicit memory accesses.
Note
Only writing 1 to the IAWEN bit has an effect. Writing 0 to it has no effect after the IAWEN bit has been set to 1.
Remark When WDTON = 1 (watchdog timer operation enabled) is set in the option byte (000C0H), the illicit memory access detection is enabled even if IAWEN = 0.
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27.3.8 Guard function of invalid memory access detection control register
To ensure safe operation, the IEC60730 standard requires the setting for enabling or disabling illicit memory access detection to be protected from being rewritten even if a CPU malfunction occurs. The RL78/G23 provides functionality to protect the invalid memory access detection control register (IAWCTL) against being rewritten. Enabling the protection of the invalid memory access detection control register disables writing to the given register. Reading from the protected register is possible.
27.3.8.1 Guard register of IAWCTL register (GIAWCTL)
This register is used to protect the setting for enabling or disabling the illicit memory access detection. To allow rewriting of the invalid memory access detection control register (IAWCTL), set the GIAWCTL.GIA bit to 0 to disable protection of the IAWCTL register.
Figure 27 - 16 Format of Guard Register of IAWCTL Register (GIAWCTL)
Address: After reset: R/W:
F048EH 0000H R/W
Symbol
15
14
13
12
11
10
9
8
GIAWCTL
RKEY[7:0]
7
6
5
4
3
2
1
0
GIA
The RKEY[7:0] bits contain the key code to control rewriting of the GIAWCTL register. When rewriting the GIA bit, set RKEY[7:0] to C4H and then write to all 16 bits of this register at once. The RKEY[7:0] bits return 00H when read.
GIA
Control of rewriting the IAWCTL register
0
Disables protection of the IAWCTL register (rewriting is allowed).
1
Enables protection of the IAWCTL register (rewriting is not allowed).
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27.3.9 Frequency detection
The IEC60730 standard mandates checking that the oscillation frequency is correct. By using the CPU/peripheral hardware clock frequency (fCLK) to measure the pulse width of the input signal to channel 5 of the timer array unit 0 (TAU0), whether the proportional relationship between the two clock frequencies is correct can be determined. Note that, however, if one or both clock operations are completely stopped, the proportional relationship between the clocks cannot be determined.
<Clock frequencies to be compared> <1> CPU/peripheral hardware clock frequency (fCLK):
· High-speed on-chip oscillator clock (fIH) · High-speed system clock (fMX) <2> Input to channel 5 of the timer array unit · Timer input to channel 5 (TI05) · Low-speed on-chip oscillator clock (fIL) · Subsystem clock (fSUB) · Medium-speed on-chip oscillator clock (fIM)
Figure 27 - 17 Configuration of Frequency Detection Function
High-speed on-chip oscillator clock (fIH)
High-speed system clock (fMX)
TI05
Subsystem clock (fSUB)
Selector
Selector
fCLK
<1>
<2>
Channel 5 of timer
array unit 0
(TAU0)
Low-speed on-chip oscillator clock (fIL)
Medium-speed on-chip oscillator clock (fIM)
Watchdog timer (WDT)
If the results of input pulse interval measurement are abnormal, the clock frequency is considered to be abnormal. For details on the input pulse interval measurement, see 7.8.4 Operation for input pulse interval measurement.
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27.3.9.1 Timer input select register 0 (TIS0)
The TIS0 register is used to select the timer input of channel 5 of the timer array unit 0 (TAU0). The TIS0 register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 27 - 18 Format of Timer Input Select Register 0 (TIS0)
Address: After reset: R/W:
F0074H 00H R/W
Symbol
7
6
5
4
3
2
1
0
TIS0
0
0
0
0
0
TIS02
TIS01
TIS00
TIS02
TIS01
TIS00
0
0
0
0
0
1
0
1
1
1
0
0
1
0
1
Other than the above
Selection of timer input used with channel 5 Input signal of timer input pin (TI05) Event input signal from ELCL Medium-speed on-chip oscillator clock (fIM) Low-speed on-chip oscillator clock (fIL) Subsystem clock (fSUB) Setting prohibited
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27.3.10 Testing of the A/D converter
The IEC60730 standard mandates testing of the A/D converter. This test checks whether or not the A/D converter is operating normally by converting the A/D converter's positive and negative reference voltages, analog input channels (ANIxx), temperature sensor output voltage, and internal reference voltage. For details on the method of checking, refer to the application note (R01AN0955) Safety Function (A/D test).
Use the following procedure to check the analog multiplexer. <1> Select the ANIxx pin for A/D conversion using the ADTES register (ADTES1 = 0, ADTES0 = 0). <2> Perform A/D conversion for the ANIxx pin (conversion result 1-1). <3> Select the A/D converter's negative reference voltage for A/D conversion using the ADTES register (ADTES1 = 1,
ADTES0 = 0) <4> Perform A/D conversion of the negative reference voltage of the A/D converter (conversion result 2-1). <5> Select the ANIxx pin for A/D conversion using the ADTES register (ADTES1 = 0, ADTES0 = 0). <6> Perform A/D conversion for the ANIxx pin (conversion result 1-2). <7> Select the A/D converter's positive reference voltage for A/D conversion using the ADTES register (ADTES1 = 1,
ADTES0 = 1) <8> Perform A/D conversion of the positive reference voltage of the A/D converter (conversion result 2-2). <9> Select the ANIxx pin for A/D conversion using the ADTES register (ADTES1 = 0, ADTES0 = 0). <10>Perform A/D conversion for the ANIxx pin (conversion result 1-3). <11>Check that the conversion results 1-1, 1-2, and 1-3 are equal. <12>Check that the A/D conversion result 2-1 is all zero and the A/D conversion result 2-2 is all one.
Using the procedure above can confirm that the analog multiplexer is selected and all wiring is connected.
Remark 1. If the analog input voltage is variable during A/D conversion in steps <1> to <10> above, use another method to check the analog multiplexer.
Remark 2. The results of conversion might include an error. Consider an appropriate level of error in comparison of the results of conversion.
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RL78/G23 Figure 27 - 19 Configuration of Testing of the A/D converter
CHAPTER 27 SAFETY FUNCTIONS
ANI0/AVREFP ANI1/AVREFM
ANIxx ANIxx
VDD
Temperature sensor
Internal reference voltage
ADREFP1 ADREFP0
VSS ADREFM
ADISS ADS4 to ADS0
ADTES1, ADTES0
Positive reference voltage of A/D converter A/D converter Negative reference voltage of A/D converter
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27.3.10.1 A/D test register (ADTES)
This register is used to select the A/D converter's positive reference voltage, A/D converter's negative reference voltage, analog input channels (ANIxx), temperature sensor output voltage, or internal reference voltage as the target of A/D conversion. When testing the A/D converter, specify the following settings: · Select the negative reference voltage as the target of A/D conversion for zero-scale measurement. · Select the positive reference voltage as the target of A/D conversion for full-scale measurement.
The ADTES register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 27 - 20 Format of A/D Test Register (ADTES)
Address: After reset: R/W:
F0013H 00H R/W
Symbol
7
6
5
4
3
2
1
0
ADTES
0
0
0
0
0
0
ADTES1 ADTES0
ADTES1 ADTES0
A/D conversion target
0
0
ANIxx/temperature sensor output voltage/internal reference voltage
(This is specified using the analog input channel specification register (ADS).)
1
0
Negative reference voltage (selected with the ADREFM bit in the ADM2 register)
1
1
Positive reference voltage (selected with the ADREFP1 or ADREFP0 bit in the
ADM2 register)
Other than the above Setting prohibited
Caution Be sure to clear bits 7 to 2 to 0.
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27.3.10.2 Analog input channel specification register (ADS)
This register specifies the input channel of the analog voltage to be A/D converted. Set the A/D test register (ADTES) to 00H when measuring ANIxx, temperature sensor output voltage, or internal reference voltage. The ADS register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 27 - 21 Format of Analog Input Channel Specification Register (ADS)
Address: After reset: R/W:
FFF31H 00H R/W
Symbol
7
6
ADS ADISS
0
5
4
3
2
1
0
0
ADS4
ADS3
ADS2
ADS1
ADS0
<Select mode (ADMD = 0)>
ADISS ADS4 ADS3 ADS2 ADS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
0
1
0
0
1
1
0
0
0
1
1
0
0
0
1
1
1
0
0
1
1
1
0
1
0
0
0
0
1
0
0
0
0
1
0
0
1
0
1
0
0
1
0
1
0
1
0
0
1
0
1
0
0
1
0
1
1
0
1
0
1
1
0
1
1
0
0
0
1
1
0
0
0
1
1
0
1
0
1
1
0
1
1
0
0
0
0
1
0
0
0
0
Other than the above
ADS0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Analog input channel
Input source
ANI0
P20/ANI0/AVREFP pin
ANI1
P21/ANI1/AVREFM pin
ANI2
P22/ANI2 pin
ANI3
P23/ANI3 pin
ANI4
P24/ANI4 pin
ANI5
P25/ANI5 pin
ANI6
P26/ANI6 pin
ANI7
P27/ANI7 pin
ANI8
P150/ANI8 pin
ANI9
P151/ANI9 pin
ANI10
P152/ANI10 pin
ANI11
P153/ANI11 pin
ANI12
P154/ANI12 pin
ANI13
P155/ANI13 pin
ANI14
P156/ANI14 pin
Setting prohibited
ANI16
P03/ANI16 pinNote 1
ANI17
P02/ANI17 pinNote 2
ANI18
P147/ANI18 pin
ANI19
P120/ANI19 pin
ANI20
P100/ANI20 pin
ANI21
P37/ANI21 pin
ANI22
P36/ANI22 pin
ANI23
P35/ANI23 pin
ANI24
P117/ANI24 pin
ANI25
P116/ANI25 pin
ANI26
P115/ANI26 pin
Setting prohibited
--
Temperature sensor output voltage
--
Internal reference voltage
Setting prohibited
(Notes and Cautions are listed on the next page.)
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Note 1. Note 2.
The P01/ANI16 pin is specified in the 30-pin and 32-pin products. The P00/ANI17 pin is specified in the 30-pin and 32-pin products.
Caution 1. Be sure to clear bits 6 and 5 to 0. Caution 2. Select input mode for the ports which are set to analog input with the PMCA registers, using the port
mode registers 0 to 3, 10 to 12, 14, and 15 (PM0 to PM3, PM10 to PM12, PM14, and PM15). Caution 3. Do not use the ADS register to set the pins which should be set as digital I/O with the port mode
control A registers 0 to 3, 10 to 12, 14, and 15 (PMCA0 to PMCA3, PMCA10 to PMCA12, PMCA14, and PMCA15). Caution 4. Only rewrite the value of the ADISS bit while the conversion operation is stopped (ADCS = 0, ADCE = 0). Caution 5. If using AVREFP as the positive reference voltage source of the A/D converter, do not select ANI0 as an A/D conversion channel. Caution 6. If using AVREFM as the negative reference voltage source of the A/D converter, do not select ANI1 as an A/D conversion channel. Caution 7. When ADISS is 1, the internal reference voltage cannot be used for the positive reference voltage. In addition, the first conversion result obtained after setting ADISS to 1 is not available. For a detailed setting flow, see 12.7.5 Example of using the ADC when selecting the temperature sensor output voltage or internal reference voltage, and software trigger no-wait mode and one-shot conversion mode. Caution 8. If a transition is made to STOP mode or a transition is made to HALT mode during CPU operation with subsystem clock, do not set ADISS to 1. When ADISS is 1, the A/D converter reference voltage current (IADREF) shown in 37.3.2 Supply current characteristics is added.
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27.3.11 Detection of the digital output signal level of the I/O pins
The IEC60730 standard mandates checking that the I/O function is operating correctly. The RL78/G23 provides functionality to read the output level of an I/O pin when the pin is in the output mode.
27.3.11.1 Port mode select register (PMS)
This register is used to select whether to read the output latch value of a port or read the output level of a pin when the pin is in the output mode (PMmn bit of port mode register (PMm) is 0). The PMS register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 27 - 22 Format of Port Mode Select Register (PMS)
Address: After reset: R/W:
F007BH 00H R/W
Symbol
7
6
5
4
3
2
1
0
PMS
0
0
0
0
0
0
0
PMS0
PMS0
Selection of data to be read when pin is in output mode
0
Reads the value of the Pmn register.
1
Reads the digital output level of the pin.
Caution 1. Do not rewrite a port register (Pxx) with a 1-bit memory manipulation instruction when the setting of the PMS0 bit in the PMS register is 1. Use an 8-bit memory manipulation instruction to rewrite a port register (Pxx).
Caution 2. The setting of this register has no effect on the input port pins (P123, P124, and P137) and output port pin (P130).
Remark m = 0 to 12, 14, 15 n = 0 to 7
Caution 3. The setting of this register has no effect when the settings of the PMCAmn and PMCTmn bits are both 1. To read the digital output level of a pin with the PMCAmn bit and PMCTmn bit both set to 1, first clear the PMCAmn and PMCTmn bits to 0 and then set the PMS0 bit to 1.
Remark m = 0 to 3, 5 to 7, 10 to 12, 14, 15 n = 0 to 7
Caution 4. The setting of this register has no effect when the setting of the PDIDISmn bit is 1. To read the digital output level of a pin with the PDIDISmn bit set to 1, first clear the PDIDISmn bit to 0 and then set the PMS0 bit to 1.
Remark m = 0, 1, 3 to 5, 7 to 9, 12 to 14 n = 0 to 7
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27.3.12 UART loopback
The IEC60730 standard recommends to diagnose abnormalities of external interfaces (communications). The UART loopback is used to confirm the normal output of the UART transmit data by shutting off the RxD pin from the outside and connecting it within the MCU to loop back the output from the transmission shift register to the reception shift register.
When the UART loopback is selected, the transmit data from the TxD pin is controlled by the port functions so that it does not affect its communication partner.
· Communication with negative logic The port that also uses the TxD pin is set to the input mode (PMxx = 1) and an on-chip pull-up resistor is connected (PUxx = 1) to retain the setting of 1.
· Communication with positive logic 0 (PMxx = 0, Pxx = 0) is output from the port that also uses the TxD pin.
27.3.12.1 UART loopback select register (ULBS)
The ULBS register is used to enable the UART loopback. This register has respective bits for independently controlling each UART channel. Setting the bit corresponding to each channel to 1 will select the UART loopback and loop back the output of the transmission shift register to the reception shift register. The ULBS register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 27 - 23 Format of UART Loopback Select Register (ULBS)
Address: After reset: R/W:
F0079H 00H R/W
Symbol
7
ULBS
0
6
<5>
<4>
<3>
<2>
<1>
<0>
0
ULBS5
ULBS4
ULBS3
ULBS2
ULBS1
ULBS0
ULBS5 0 1
ULBS4 0 1
UART loopback selection Inputs the state of the RxDA1 pin of serial interface UARTA1 to the reception shift register. Loops back the output of the transmission shift register to the reception shift register.
UART loopback selection Note 2 Inputs the state of the RxDA0 pin of serial interface UARTA0 to the reception shift register. Loops back the output of the transmission shift register to the reception shift register.
ULBS3 0 1
UART loopback selection Note 1 Inputs the state of the RxD3 pin of serial array unit UART3 to the reception shift register. Loops back the output of the transmission shift register to the reception shift register.
ULBS2 0 1
UART loopback selection Note 1 Inputs the state of the RxD2 pin of serial array unit UART2 to the reception shift register. Loops back the output of the transmission shift register to the reception shift register.
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ULBS1 0 1
UART loopback selection Note 1 Inputs the state of the RxD1 pin of serial array unit UART1 to the reception shift register. Loops back the output of the transmission shift register to the reception shift register.
ULBS0 0 1
UART loopback selection Note 1 Inputs the state of the RxD0 pin of serial array unit UART0 to the reception shift register. Loops back the output of the transmission shift register to the reception shift register.
Note 1. Note 2.
For UART0, set the PFOE10 bit of the port function output enable register 1 (PFOE1) to 1 when using the loopback. For UART0, set the PFOE14 bit of the port function output enable register 1 (PFOE1) to 1 when using the loopback.
Caution Be sure to clear bits 7 and 6 to 0.
Remark The RxDA0 pin is only available in the 36-pin to 128-pin products. The RxDA1 is only available in the to 128-pin products.
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RL78/G23
CHAPTER 28 SECURITY FUNCTIONS
CHAPTER 28 SECURITY FUNCTIONS
28.1
True Random Number Generator
28.1.1 Function of the true random number generator
The true random number generator generates 32-bit random number seeds (which are true random numbers).
28.1.2 Registers to control the true random number generator
The following registers are used to control the true random number generator.
· Random number seed command register 0 (TRNGSCR0) · Random number seed data register (TRNGSDR)
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28.1.2.1 Random number seed command register 0 (TRNGSCR0)
The TRNGSCR0 register controls operation of the true random number generator. Setting the TRNGST bit to 1 after having set the TRNGEN bit to 1 starts the generation of a random number seed. When the true random number generator finishes generating the random number seed, the TRNGRDY bit is set to 1. Since the TRNGST bit serves as the trigger for starting the generation of a random number seed, it is cleared to 0 immediately after 1 having been written to it. The TRNGSCR0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Figure 28 - 1 Format of Random Number Seed Command Register 0 (TRNGSCR0)
Address: After reset: R/W:
F0542H 00H R/W
Symbol
<7>
6
5
4
<3>
<2>
1
0
TRNGSCR0 TRNGRDY
0
0
0
TRNGEN TRNGST
0
0
TRNGRDY
Random number seed generation status flag
0
A random number seed has not been generated or four rounds of reading from the
TRNGSDR register have been completed.
1
A random number seed has been generated.
TRNGEN
Control over operation of the true random number generator
0
Stops the true random number generator.
1
Enables the true random number generator.
TRNGST
Trigger to start generating a random number seed
0
The trigger is inactive.
1
Starts generation of a random number seed.
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CHAPTER 28 SECURITY FUNCTIONS
28.1.2.2 Random number seed data register (TRNGSDR)
The TRNGSDR register is an 8-bit register that holds the bytes of random number seeds generated by the true random number generator. The random number seed can be read from this register after the TRNGRDY bit is set to 1. As a random number seed consists of 32 bits, four rounds of access to the register are required for each seed. Bit 7 (TRNGRDY) of the TRNGSCR0 register is cleared to 0 following the four rounds of access. The TRNGSDR register can be read by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Figure 28 - 2 Format of Random Number Seed Data Register (TRNGSDR)
Address: After reset: R/W:
F0540H 00H R
Symbol
7
TRNGSDR
Caution
6
5
4
3
2
1
0
When the value of the TRNGRDY bit is 0, the value in the TRNGSDR register is 00H.
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28.1.3 Operations of the true random number generator
Figure 28 - 3 shows the procedure for using the true random number generator to generate a random number seed.
Figure 28 - 3 Procedure for Using the True Random Number Generator to Generate a Random Number Seed
Start of generation of a random number seed
Set the TRNGSCR0 register.
Set the TRNGEN bit of the TRNGSCR0 register to 1 to enable the true random number generator. Set the TRNGST bit to 1 to start generation of a random number seed.
TRNGRDY = 1? No
Yes Read from TRNGSDR
(the first round)
Read from TRNGSDR (the second round)
Read from TRNGSDR (the third round)
Read from TRNGSDR (the fourth round)
Set the TRNGSCR0 register.
End of generation of a random number seed
Wait until the value of the TRNGRDY bit of the TRNGSCR0 register becomes 1.
Read the first 8-bit unit of the random number seed that will currently be stored in the TRNGSDR register. Read the second 8-bit unit of the random number seed that will currently be stored in the TRNGSDR register.
Read the third 8-bit unit of the random number seed that will currently be stored in the TRNGSDR register.
Read the fourth 8-bit unit of the random number seed that will currently be stored in the TRNGSDR register.
Set the TRNGEN bit of the TRNGSCR0 register to 0 to disable the true random number generator.
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CHAPTER 28 SECURITY FUNCTIONS
28.2
Flash Read Protection
28.2.1 Function of flash read protection
The flash read protection function can be used to protect a specified range of the code flash memory area against read access by the CPU, DTC, or SMS. Note that fetching of instructions in the specified range by the CPU is still possible.
28.2.2 Setting of flash read protection
The settings for flash read protection are made through serial programming by using a flash memory programmer or through self-programming in the extra area. After the settings have been made, read access to addresses in the range of blocks in the code flash memory area between the start and end of the flash read protection becomes impossible. In addition, enabling fixing of the flash read protection settings makes changes to the blocks where flash read protection starts and ends impossible. However, fixing of the flash read protection settings can be released by using a flash memory programmer. Table 28 - 1 describes the settings for flash read protection and their functions. Table 28 - 2 describes the method of setting flash read protection.
Table 28 - 1 Settings for Flash Read Protection and their Functions
Item to Be Set
Function
Block where flash read protection starts
Specifies the number of the block where the read-access disabled area starts. The specifiable values are in the range from the block numbered 001H to the number of the block at the highest-order address in the code flash memory. The block for which the number is set as the block where protection starts is part of the read-access disabled area. Setting 000H as the block where protection starts is prohibited. The initial setting is outside the specifiable range.
Block where flash read protection ends
Specifies the number of the block where the read-access disabled area ends. The specifiable values are in the range from the number of the block where the protection starts to the number of the block at the highest-order address in the code flash memory. The block for which the number is set as the block where protection ends is part of the read-access disabled area. The initial setting is outside the specifiable range.
Fixing the flash read protection settings
Fixes the settings of the blocks where flash read protection starts and ends. When the "enabled" setting is made, changes to the blocks where protection starts and ends are not possible.
For details on the relationship between the addresses and block numbers, refer to Table 3 - 1 Correspondence between Addresses and Block Numbers in Flash Memory.
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Table 28 - 2 Method of Setting Flash Read Protection
Item to Be Set
Method of Setting
Method of Changing
Block where flash read protection starts
Using a flash memory programmer Using a flash memory programmer or self-programming. Note
or self-programming.
that the block where protection starts is not adjustable while
fixing of the flash read protection settings is enabled.
Block where flash read protection ends
Using a flash memory programmer Using a flash memory programmer or self-programming. Note
or self-programming.
that the block where protection ends is not adjustable while
fixing of the flash read protection settings is enabled.
Fixing the flash read protection settings
Using a flash memory programmer Fixing of the flash read protection settings can be released by
or self-programming.
using a flash memory programmer.Note If you do so, the values
for the start and end blocks are initialized.
Note
Release from the fixed setting is only possible when erasure of blocks is not prohibited, rewriting of boot cluster 0 is not prohibited, and the code and data flash memory areas are blank.
Caution 1. The settings for flash read protection in the extra area are not readable. To confirm that the settings for flash read protection are in place, read from the read-access disabled area and confirm that FFH is returned.
Caution 2. To specify the read-access disabled area for flash read protection, be sure to specify the numbers of both the block where protection starts and the block where it ends.
Caution 3. Reading from the read-access disabled area by using an on-chip debugger is also impossible. This means that program code allocated to the read access-disabled area cannot be debugged by using the on-chip debugger. Therefore, only make the settings for flash read protection after having debugged the program code in the protected areas.
Caution 4. When a part of boot cluster 0 or boot cluster 1 is to be set as a part of the read-access disabled area, boot swapping may cause data in the read-access disabled area to be swapped with data in the read access-enabled area. To prevent this, when setting a part of boot cluster 0 or boot cluster 1 as part of the read-access disabled area, make the setting for prohibiting the rewriting of boot cluster 0 so as to prohibit boot swapping itself.
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28.2.3 Operation
Reading by the CPU, DTC, or SMS from the area to which read access has been disabled with the use of flash read protection always returns FFH. Fetching of instructions in the read-access disabled area by the CPU is still possible. Note that even if program code is to be executed from the read-access disabled area, it is unable to read data that have been placed in the read-access disabled area. Place data for use with code to be executed from the read-access disabled area in areas that are not protected.
Figure 28 - 4 shows examples of setting read-access disabled areas for the application of flash read protection
Figure 28 - 4 Examples of Setting Read-Access Disabled Areas for the Application of Flash Read Protection
Example of setting a single block as the read-access disabled area
Start block: 020H End block: 020H
Example of setting multiple blocks as the read-access disabled area
Start block: 013H End block: 015H
1FFFFH
Block 3FH Block 3EH
Code flash memory area
10800H
Read-access disabled area
107FFH
Block 20H (serving as both the start
10000H
and end block)
0FFFFH
Block 1FH
1FFFFH
Code flash memory area
0B000H 0AFFFH
Read-access disabled area
09800H 097FFH
Block 3FH Block 3EH
Block 15H (end block) Block 14H Block 13H (start block) Block 12H
00000H
Block 01H Block 00H
00000H
Block 01H Block 00H
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CHAPTER 28 SECURITY FUNCTIONS
28.3
Unique ID
28.3.1 Function of a unique ID
A unique ID is a unique value that is allocated to an individual product and stored in the extra area. A unique ID is entered for each product at the time of manufacturing the MCUs. Changing the entered ID is not possible. The data length is 16 bytes (128 bits).
Caution The value of a unique ID is not a random number.
28.3.2 ASCII codes representing the product name
Product names are also stored as strings of ASCII codes in the extra area. Since the product names include indicators of the number of pins and capacity of the flash memory for the given product, conditional branch processing on the basis of the product name is possible.
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Table 28 - 3 shows the places of the unique ID, basic product name, and indicators of the number of pins and capacity of the flash memory in the memory map.
Table 28 - 3 Memory Map of the Unique ID and Product Name
Address
Item Name
Value to Be Entered
EFFC0H to EFFCFH
Unique ID
The unique value allocated to an individual product
EFFD5H EFFD6H
ASCII codes representing the 52H: "R"
product name
37H: "7"
EFFD7H
46H: "F"
EFFD8H
31H: "1"
EFFD9H
30H: "0"
EFFDAH
30H: "0"
EFFDBH
47H: "G"
EFFDCH
41H: "A" (30 pins) 42H: "B" (32 pins) 43H: "C" (36 pins) 45H: "E" (40 pins) 46H: "F" (44 pins) 47H: "G" (48 pins) 4AH: "J" (52 pins) 4CH: "L" (64 pins) 4DH: "M" (80 pins) 50H: "P" (100 pins) 53H: "S" (128 pins)
EFFDDH
46H: "F" (96-Kbyte flash memory) 47H: "G" (128-Kbyte flash memory) 48H: "H" (192-Kbyte flash memory) 4AH: "J" (256-Kbyte flash memory) 4BH: "K" (384-Kbyte flash memory) 4CH: "L" (512-Kbyte flash memory) 4EH: "N" (768-Kbyte flash memory)
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CHAPTER 29 SNOOZE MODE SEQUENCER (SMS)
CHAPTER 29 SNOOZE MODE SEQUENCER (SMS)
The SNOOZE mode sequencer sequentially handles 32 processes that have been set in advance. This function can be started by a signal from another peripheral function as the trigger even in the standby state. This means the sequencer can run through the processes independently of the CPU. Doing so with the CPU placed in the standby state reduces power consumption.
29.1
Functions of the SNOOZE Mode Sequencer
The SNOOZE mode sequencer can handle processing independently of the CPU and has the following functions.
· Sequentially handling a total of 32 processes with the use of desired commands from among 21 different ones · Able to operate even if the CPU is in the standby state · Waking the CPU up from the standby state · Directly starting the data transfer controller (DTC) up · Access to the RAM and special function register (SFR) area for the peripheral functions · 16-bit addition and subtraction · Branch processing · Automatically switching the source clock for use in waiting to the low-speed on-chip oscillator clock to ensure long
enough wait times
29.2
Configuration of the SNOOZE Mode Sequencer
Figure 29 - 1 is a block diagram of the SNOOZE mode sequencer.
Figure 29 - 1 Block Diagram of the SNOOZE Mode Sequencer
Sequencer general-purpose registers
(SMSGn, n = 0 to 15) SMSG0 SMSG1 SMSG15
INTSMSE interrupt DTC transfer request
... ...
Internal bus
Sequencer instruction registers (SMSIn, n = 0 to 31)
Sequencer status register (SMSS) SMSSTAT SZ SCY SMSCV4 SMSCV3 SMSCV2 SMSCV1 SMSCV0
SMSI0 SMSI1 SMSI2 SMSI31
Sequencer
Activating trigger
Selector
fIL
fCLK
INTITL INTP3 INTSR0 INTCSI00 INTAD ELCL output INTUR0 INTTM02 INTIICA0 INTLVI INTKR
SMSSTART SMSSTOP SMSTRGWAIT LONGWAIT SMSTRGSEL3 SMSTRGSEL2 SMSTRGSEL1 SMSTRGSEL0
Sequencer control register (SMSC) Internal bus
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CHAPTER 29 SNOOZE MODE SEQUENCER (SMS)
29.3
Registers to Control the SNOOZE Mode Sequencer
The following registers are used to control the SNOOZE mode sequencer.
· Peripheral enable register 1 (PER1) · Peripheral reset control register 1 (PRR1) · Sequencer instruction registers p (SMSIp) (p = 0 to 31) · Sequencer general-purpose registers n (SMSGn) (n = 0 to 15) · Sequencer control register (SMSC) · Sequencer status register (SMSS)
29.3.1 Peripheral enable register 1 (PER1)
This register is used to enable or disable the supply of a clock signal to various on-chip peripheral modules. Clock supply to an on-chip peripheral module that is not to be used can be stopped to decrease power consumption and noise. If the SNOOZE mode sequencer is to be used, be sure to set bit 6 (SMSEN) of this register to 1. The PER1 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset. For a precautionary note on the dependence on the number of pins of RL78/G23 products of the presence or absence of the PER bit, see CHAPTER 6 CLOCK GENERATOR.
Figure 29 - 2 Format of Peripheral Enable Register 1 (PER1)
Address: After reset: R/W:
F00FAH 00H R/W
Symbol
<7>
PER1 DACEN
<6> SMSEN
<5> CMPEN
<4> TML32EN
<3> DTCEN
<2> UTAEN
<1> REMCEN
<0> CTSUEN
SMSEN
Control of supply of an input clock to the SNOOZE mode sequencer
0
Stops supply of an input clock.
· The SFRs used by the SNOOZE mode sequencer cannot be written.
· When an SFR used by the SNOOZE mode sequencer is read, the value returned is 00H or
0000H.
1
Enables supply of an input clock.
· The SFRs used by the SNOOZE mode sequencer can be read and written.
Caution Do not change the value of the SMSEN bit of the PER1 register from 1 to 0 while the SNOOZE mode sequencer is operating.
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CHAPTER 29 SNOOZE MODE SEQUENCER (SMS)
29.3.2 Peripheral reset control register 1 (PRR1)
The PRR1 register is used to control resetting of the on-chip peripheral modules. Each bit in this register controls resetting and release from the reset state of the corresponding on-chip peripheral module. To place the SNOOZE mode sequencer in the reset state, be sure to set bit 6 (SMSRES) of this register to 1. The PRR1 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 29 - 3 Format of Peripheral Reset Control Register 1 (PRR1)
Address: After reset: R/W:
F00FBH 00H R/W
Symbol
<7>
<6>
<5>
<4>
3
PRR1 DACRES SMSRES CMPRES TML32RES
0
2
<1>
<0>
0
REMCRES CTSURES
SMSRES
Control resetting of the SNOOZE mode sequencer
0
The SNOOZE mode sequencer is released from the reset state.
1
The SNOOZE mode sequencer is in the reset state.
· The SFRs for use with the SNOOZE mode sequencer are initialized.
Note
The functions that are mounted depend on the product. For details on the PRR1 register, see the description in CHAPTER 24 RESET FUNCTION.
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29.3.3 Sequencer instruction registers p (SMSIp) (p = 0 to 31)
Each SMSIp register is a 16-bit register for holding a command to be handled by the SNOOZE mode sequencer. The commands are stored in the total of 32 registers from SMSI0 to SMSI31. The sequencer sequentially handles the commands in order from the SMSI0 register. The contents of each register are referred to as a sequencer code, which consists of an indicator of the processing, a first operand, a second operand, and an additional byte or nybble, the use of which depends on the sequencer code. For details on how the sequencer handles each form of processing, see 29.5 Commands for Use in Processing by the Sequencer. In addition, after executing processing specified by an SMSIp register, the sequencer executes the processing specified either by the next SMSIp register or by the SMSIp register at a branch destination. The SMSIp register currently in use can be confirmed by reading the SMSCV0 to SMSCV4 bits of the sequencer status register (SMSS). Table 29 - 1 shows the correspondences between the memory addresses of the SMSIp registers and values of the SMSCV0 to SMSCV4 bits. Table 29 - 2 lists the types of processing specified by the SMSIp registers.
The SMSIp registers can be set by a 16-bit memory manipulation instruction. The value of each SMSIp register is 0000H following a reset.
Figure 29 - 4 Format of Sequencer Instruction Registers p (SMSIp)
Address: After reset: R/W:
F0380H, F0381H (SMSI0) to F03BEH, F03BFH (SMSI31) 0000H R/W
Symbol
15
14
13
12
11
10
9
8
SMSIp
Sequencer code
First operand
7
6
5
4
3
2
1
0
Second operand
Additional byte
p = 0 to 31
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Table 29 - 1 Correspondences between the Memory Addresses of the SMSIp Registers and Values of the SMSCV0 to SMSCV4 Bits
SMSIp
Address
SMSCV[4:0]
SMSIp
Address
SMSCV[4:0]
SMSI15
F039EH, F039FH 01111B
SMSI31
F03BEH, F03BFH 11111B
SMSI14
F039CH, F039DH 01110B
SMSI30
F03BCH, F03BDH 11110B
SMSI13
F039AH, F039BH 01101B
SMSI29
F03BAH, F03BBH 11101B
SMSI12
F0398H, F0399H 01100B
SMSI28
F03B8H, F03B9H 11100B
SMSI11
F0396H, F0397H 01011B
SMSI27
F03B6H, F03B7H 11011B
SMSI10
F0394H, F0395H 01010B
SMSI26
F03B4H, F03B5H 11010B
SMSI9
F0392H, F0393H 01001B
SMSI25
F03B2H, F03B3H 11001B
SMSI8
F0390H, F0391H 01000B
SMSI24
F03B0H, F03B1H 11000B
SMSI7
F038EH, F038FH 00111B
SMSI23
F03AEH, F03AFH 10111B
SMSI6
F038CH, F038DH 00110B
SMSI22
F03ACH, F03ADH 10110B
SMSI5
F038AH, F038BH 00101B
SMSI21
F03AAH, F03ABH 10101B
SMSI4
F0388H, F0389H 00100B
SMSI20
F03A8H, F03A9H 10100B
SMSI3
F0386H, F0387H 00011B
SMSI19
F03A6H, F03A7H 10011B
SMSI2
F0384H, F0385H 00010B
SMSI18
F03A4H, F03A5H 10010B
SMSI1
F0382H, F0383H 00001B
SMSI17
F03A2H, F03A3H 10001B
SMSI0
F0380H, F0381H 00000B
SMSI16
F03A0H, F03A1H 10000B
Caution 1. Only set the SMSIp registers while the operation of the sequencer is stopped. Caution 2. No register follows the SMSI31 register once the processing it defines has finished. Therefore, set the SMSI31
register for processing for termination command or interrupt plus termination command to stop processing by the sequencer, or for branch processing so that the processing at the branch destination register is run.
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Table 29 - 2 Types of Processing Specified by the SMSIp Registers
Name of Processing
OperationNote 4
Sequencer Code
8-bit data transfer 1
[SMSGn + Byte] SMSGm
0000
8-bit data transfer 2
SMSGm [SMSGn + Byte]
0001
16-bit data transfer 1
[SMSGn + Byte] SMSGm
0010
16-bit data transfer2
SMSGm [SMSGn + Byte]
0011
1-bit data setting
[SMSGn + Byte].bit 1
0100
First Operand (4 Bits)
nth of SMSGn
Note 1
nth of SMSGn
Note 1
nth of SMSGn
Note 1
nth of SMSGn
Note 1
nth of SMSGn
Note 1
Second Operand Additional
(4 Bits)
Byte (4 Bits)
mth of SMSGmNote 1
ByteNote 2
mth of SMSGmNote 1
ByteNote 2
mth of SMSGmNote 1
ByteNote 2
mth of SMSGmNote 1
ByteNote 2
bitNote 2
ByteNote 2
1-bit data clearing
[SMSGn + Byte].bit 0
0101
nth of SMSGn
Note 1
bitNote 2
ByteNote 2
1-bit data transfer
SCY [SMSGn + Byte].bit
0110
nth of SMSGn
Note 1
bitNote 2
ByteNote 2
Word addition
Word subtraction
Word comparison
Logical shift right
Branch 1 (SCY = 1) Branch 2 (SCY = 0) Branch 3 (SZ = 1) Branch 4 (SZ = 0) Wait Conditional wait 1 (bit = 1)
Conditional wait 2 (bit = 0)
SMSGn, SCY SMSGn + SMSGm
SMSGn, SCY SMSGn - SMSGm
SMSGn - SMSGm
SCY SMSGn.0, SMSGm.15 0, SMSGn.m-1 SMSGn.m SMSS[4:0] SMSS[4:0] + jdisp8 if SCY = 1 SMSS[4:0] SMSS[4:0] + jdisp8 if SCY = 0 SMSS[4:0] SMSS[4:0] + jdisp8 if SZ = 1 SMSS[4:0] SMSS[4:0] + jdisp8 if SZ = 0 Holding processing pending for a certain period SMSS[4:0] SMSS[4:0] if [ SMSGn + Byte ].bit = 1 SMSS[4:0] SMSS[4:0] if [ SMSGn + Byte ].bit = 0
0111
0111
0111
0111
1000 1000 1000 1000 1001 1010
1011
nth of SMSGn
Note 1
mth of SMSGmNote 1
nth of SMSGn
Note 1
mth of SMSGmNote 1
nth of SMSGn
Note 1
nth of SMSGn
Note 1
mth of SMSGmNote 1
0000
$addr5Note 3
$addr5Note 3
$addr5Note 3
$addr5Note 3
IM1
nth of SMSGn
Note 1
BitNote 2
nth of SMSGn
Note 1
BitNote 2
0000
0001
0010
0011
0000 0001 0010 0011 IM2 ByteNote 2 ByteNote 2
Termination
SMSS[4:0] 0, Stopping the sequencer
1111
0000
0000
0000
Interrupt plus termination
SMSS[4:0] 0, Stopping the sequencer after issuing an interrupt
1111
0000
0000
0001
DTC activation
Output of a DTC activating source signal
1111
0000
0000
0010
Note 1. Note 2. Note 3.
Note 4.
Specify values in the range from 0 to 15 (from 0000B to 1111B) for n and m. Specify values in the range from 0 to 7 (from 0000B to 0111B) for the bytes. This is an 8-bit displacement value. Specify a relative address in the range from 0 to 31 (0000 0000B to 0001 1111B, 1111 1111B to 1110 0001B). For details on the terms, see 29.5 Commands for Use in Processing by the Sequencer.
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29.3.4 Sequencer general-purpose registers n (SMSGn) (n = 0 to 15)
Each SMSGn register is a 16-bit general-purpose register for use with the sequencer and is used for the storage of data, judgement values for use in calculations, source and destination addresses for data manipulation, and so on. Note that the SMSG0 and SMSG15 registers have the fixed values 0000H and FFFFH, respectively. The sequencer has direct access to the SMSGn registers for several types of processing. In such cases, use the suffix n in SMSGn as the internal data addresses to specify the desired SMSGn registers for the sequencer. The SMSG0 to SMSG15 registers can be read by a 16-bit memory manipulation instruction. The SMSG1 to SMSG14 registers can be set by a 16-bit memory manipulation instruction. The value of each of the SMSG1 to SMSG14 registers is 0000H following a reset. The SMSG0 and SMSG15 registers have the fixed values 0000H and FFFFH, respectively.
Figure 29 - 5 Format of Sequencer General-Purpose Registers n (SMSGn)
Address: After reset: R/W:
F03C0H, F03C1H 0000H R
Symbol
15
14
13
12
11
10
9
8
SMSG0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Address: After reset: R/W:
F03C2H, F03C3H (SMSG1) to F03DCH, F03DDH (SMSG14) 0000H R/W
Symbol
15
14
13
12
11
10
9
8
SMSGn
7
6
5
4
3
2
1
0
n = 1 to 14
Address: After reset: R/W:
F03DEH, F03DFH FFFFH R
Symbol
15
14
13
12
11
10
9
8
SMSG15
1
1
1
1
1
1
1
1
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
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Table 29 - 3 Correspondences between the SMSGn Registers, Memory Addresses, and the Internal Data Addresses for the Sequencer.
SMSGn
Addresses
Internal Data Addresses for the Sequencer
SMSG15
F03DEH, F03DFH
1111B
SMSG14
F03DCH, F03DDH
1110B
SMSG13
F03DAH, F03DBH
1101B
SMSG12
F03D8H, F03D9H
1100B
SMSG11
F03D6H, F03D7H
1011B
SMSG10
F03D4H, F03D5H
1010B
SMSG9
F03D2H, F03D3H
1001B
SMSG8
F03D0H, F03D1H
1000B
SMSG7
F03CEH, F03CFH
0111B
SMSG6
F03CCH, F03CDH
0110B
SMSG5
F03CAH, F03CBH
0101B
SMSG4
F03C8H, F03C9H
0100B
SMSG3
F03C6H, F03C7H
0011B
SMSG2
F03C4H, F03C5H
0010B
SMSG1
F03C2H, F03C3H
0001B
SMSG0
F03C0H, F03C1H
0000B
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29.3.5 Sequencer control register (SMSC)
The SMSC register controls operation of the SNOOZE mode sequencer. Specifically, this register is used for control over starting and stopping of operation of the sequencer and holding the activating trigger for the sequencer pending, and for setting the source clock for counting in waiting triggered by the wait commands and the trigger for starting operation of the sequencer. The SMSC register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 29 - 6 Format of Sequencer Control Register (SMSC) (1/2)
Address: After reset: R/W:
F03E0H 00H R/W
Symbol
<7>
<6>
<5>
<4>
3
2
1
0
SMSC SMSSTART SMSSTOP SMSTRGWAIT LONGWAIT SMSTRGSEL3 SMSTRGSEL2 SMSTRGSEL1 SMSTRGSEL0
SMSSTAR TNote 1
Control over operation of the SNOOZE mode sequencer
0
The sequencer is stopped.
Condition for setting to 0: Setting the SMSSTOP bit to 1
1
The sequencer is waiting for the selected activating trigger or operating.
Condition for setting to 1: Writing 1 to this bit
SMSSTOP
Notes 1, 2
Control over operation of the SNOOZE mode sequencer
0
--
1
Trigger for forcibly terminating processing by the sequencer
Terminates processing by the sequencer and forcibly places the sequencer in the stopped
state. Specifically, the sequencer is stopped on completion of the processing being handled at
the time the SMSSTOP bit is set to 1.
SMSTRGW
AIT
Control over holding the activating trigger pending
Note 3
0
Disables holding the activating trigger pending
1
Enables holding the activating trigger pending
On reception of the selected activating trigger, the trigger is held pending. Clearing the
SMSTRGWAIT bit to 0 enables the trigger being held pending, so the sequencer starts
operating.
Note 1. Note 2. Note 3.
Writing 0 to the SMSSTART and SMSSTOP bits has no effect. The SMSSTOP bit is always read as 0. Only set the SMSTRGWAIT bit to 1 while the value of the SMSSTART bit is 0, that is, while the sequencer is stopped.
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Figure 29 - 6 Format of Sequencer Control Register (SMSC) (2/2)
Address: After reset: R/W:
F03E0H 00H R/W
Symbol
<7>
<6>
<5>
<4>
3
2
1
0
SMSC SMSSTART SMSSTOP SMSTRGWAIT LONGWAIT SMSTRGSEL3 SMSTRGSEL2 SMSTRGSEL1 SMSTRGSEL0
LONGWAI T
Status flag indicating the source clock for counting for use with the wait command
0
Stops supply of the low-speed on-chip oscillator clock.
1
Enables supply of the low-speed on-chip oscillator clock.
SMSTRGS SMSTRGS SMSTRGS SMSTRGS Selected Activating Trigger for the SNOOZE Mode
EL3
EL2
EL1
EL0
SequencerNote 1
0
0
0
0
Interval detection interrupt (INTITL) from the 32-bit
interval timer
0
0
0
1
Pin input edge detection interrupt (INTP3)
0
0
1
0
UART0 reception transfer end interrupt (INTSR0)
0
0
1
1
CSI00 transfer end interrupt (INTCSI00)
0
1
0
0
A/D conversion end interrupt (INTAD)
0
1
0
1
ELCL output signal
0
1
1
0
UARTA0 reception transfer end interrupt
(INTUR0)Note 2
0
1
1
1
Timer channel 02 count or capture end interrupt
(INTTM02)
1
0
0
0
IICA0 communication end interrupt (INTIICA0)
1
0
0
1
Voltage detection interrupt (INTLVI)
1
0
1
0
Key return signal detection interrupt (INTKR)Note 3
Note 1.
Note 2. Note 3.
Only set the SMSTRGSEL3 to SMSTRGSEL0 bits to 1 while the value of the SMSSTART bit is 0, that is, while the sequencer is stopped. This is only selectable in products with 36 to 128 pins. This is only selectable in products with 40 to 128 pins.
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29.3.6 Sequencer status register (SMSS)
The SMSS register indicates the state of the sequencer. This register can be used to confirm whether the sequencer is operating or stopped, the values of the sequencer's zero and carry flags, and the number of the SMSIp register that holds the command currently being executed by the sequencer. The SMSS register can be read by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 29 - 7 Format of Sequencer Status Register (SMSS)
Address: After reset: R/W:
F03E1H 00H R
Symbol
<7>
6
SMSS SMSSTAT
SZ
5 SCY
4 SMSCV4
3 SMSCV3
2 SMSCV2
1 SMSCV1
0 SMSCV0
SMSSTAT
State of operation of the SNOOZE mode sequencer
0
The SNOOZE mode sequencer is stopped.
1
The SNOOZE mode sequencer is operating.
SZ
Zero flag of the SNOOZE mode sequencer
0
The result of the most recent operation by the sequencer was not 0.
1
The result of the most recent operation by the sequencer was 0.
SCY 0 1
Carry flag of the SNOOZE mode sequencer The operation most recent operation by the sequencer did not produce carrying or borrowing. The operation most recent operation by the sequencer produced carrying or borrowing.
SMSCV4
SMSCV3
SMSCV2 0 to 31
SMSCV1
SMSCV0
State of processing by the SNOOZE
mode sequencer
These bits indicate the number of the SMSIp register from which the sequencer is reading the command to be handled or has read the command that is currently being processed. Example: When the value of the SMSCV[4:0] bits is 3, the processing set up in the SMSI3 register is currently being read or its execution is in progress.
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29.4
Operations of the SNOOZE Mode Sequencer
29.4.1 Internal operations of the SNOOZE mode sequencer
Sequencing by the SNOOZE mode sequencer starts in response to the activating trigger specified by the SMSTRGSEL0 to SMSTRGSEL4 bits of the SMSC register. Following activation, the sequencer handles the processing specified by the SMSI0 register, and then handles the processing specified by the SMSIp register indicated by the SMSCV0 to SMSCV4 bits of the SMSS register. After execution of the processing for termination command or interrupt plus termination command, the sequencer has finished one round of processing and waits for another activating trigger. Moreover, setting the SMSSTOP bit of the SMSC register to 1 to generate a trigger for forcible termination leads to the sequencer being stopped. Figure 29 - 8 shows the flow of internal operations of the SNOOZE mode sequencer.
Figure 29 - 8 Flow of Internal Operations of the SNOOZE Mode Sequencer
Generation of the activating trigger
If the CPU has been placed in STOP mode, start the operating clock.
Handle the processing specified by SMSIp. The SMSCV[4:0] bits of the SMSS register indicate the
current value of p.
Forcible termination? Yes
Clear SMSC to 00H. Clear SMSS to 00H.
No
Is the current processing for termination command?
Yes
No
Is the current processing for interrupt plus termination command?
No
Yes Issue an INTSMSE interrupt.
Increment the value of the SMSCV[4:0] bits of SMSS or set it to the destination
address of a branch.
Clear the SMSSTAT bit of SMSS to 0B. Clear the SMSCV[4:0] bits of SMSS to
00000B.
If the CPU has been placed in STOP mode, stop the operating clock.
The sequencer is stopped.
The sequencer waits for another activating trigger.
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29.4.2 Memory space allocated to the sequencer
The registers of the SNOOZE mode sequencer are in the second SFR space as shown in Figure 29 - 9. The sequencer handles the 16-bit processing codes stored at even addresses in the range from F0380H to F03BFH as being at five-bit addresses from 0 to 31 (00000B to 11111B). The sequencer also has direct access to the 16-bit data for processing stored at even addresses in the range from F03C0H to F03DFH as being at four-bit addresses from 0 to 15 (0000B to 1111B).
Figure 29 - 9 Memory Space Allocated to the SNOOZE Mode Sequencer
F03E1H F03E0H F03DEH F03DCH
SMSS SMSC SMSG15 SMSG14
...
...
F03C4H F03C2H F03C0H F03BEH F03BCH F03BAH
SMSG2 SMSG1 SMSG0 SMSI31 SMSI30 SMSI29
...
...
F0386H F0384H F0382H F0380H
SMSI3 SMSI2 SMSI1 SMSI0
8 bits
16 bits
Sequencer status register Sequencer control register Sequencer general-purpose registers 0 to 15
Sequencer instruction registers 0 to 31
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Moreover, the sequencer also has indirect access with some limitationsNote to the memory space from F0000H to FFFFFH through use of the SMSGn registers.
Note
Access by the SNOOZE mode sequencer to the areas listed below is prohibited. · General-purpose register area · Mirror area · Data flash memory area · An internal RAM area that has been placed in shutdown mode by the setting of the memory power
reduction control register (PSMCR) · The stated internal RAM areas of the products listed below (if the tracing function of on-chip debugging is in
use) - R7F100GxG (x = A, B, C, E, F, G, J, L, M, and P): FC300H to FC6FFH - R7F100GxJ (x = A, B, C, E, F, G, J, L, M, P, and S): FA300H to FA6FFH - R7F100GxL, R7F100GxN (x = F, G, J, L, M, P, and S): F4300H to F46FFH · Area to which the monitor program for debugging is allocated (when on-chip debugging is in use) For details, see 34.4 Allocation of Memory Spaces to User Resources. · Sequencer instruction registers 0 o 31 (SMSI0 to SMSI31) · Sequencer control register (SMSC) · Sequencer status register (SMSS) · SMSEN bit of peripheral enable register 1 (PER1) · SMSRES bit of peripheral reset control register 1 (PRR1)
Figure 29 - 10 Memory Space to which the Sequencer Has Access
FFFFFH
SMSIp Sequencer code SMSGn SMSGm
byte
Target memory SMSGn + Byte
F0000H
Memory
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29.4.3 Sequencer flags
The sequencer has flags that are set or reset in response to the results of operations.
(a) Sequencer zero flag (SZ) The SZ flag is an internal flag of the sequencer. The flag is set to 1 when the result of addition, subtraction, or comparison is 0. Otherwise, the flag is cleared to 0. The flag is only for use in the internal processing by the sequencer. For details, see 29.5 Commands for Use in Processing by the Sequencer.
(b) Sequencer carry flag (SCY) The SCY flag reflects the state of addition or subtraction producing an overflow or underflow, the value of the shiftedout bit in logical shifting processing, or the result of 1-bit data transfer. The flag is only for use in the internal processing by the sequencer. For details, see 29.5 Commands for Use in Processing by the Sequencer.
The values of the SZ and SCY flags of the sequencer can be read from the corresponding bits of the SMSS register. See 29.3.6 Sequencer status register (SMSS).
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29.4.4 Procedures for running the SNOOZE mode sequencer
(1) Example of the initial settings, activation, and operation of the SNOOZE mode sequencer Figure 29 - 11 shows an example of a flow of processing from the initial settings until activation and the completion of processing by the SNOOZE mode sequencer.
Figure 29 - 11 Flow of Activating and Running the SNOOZE Mode Sequencer
Initial settings
Start of the initial settings
Set the SMSRES bit of PRR1 to 0.
Set the SMSEN bit of PER1 to 1.
Set the code for processing in the SMSIp area.
Set the initial values in the SMSGn area.
Set the SMS activating trigger in SMSC.
Set the SMSSTART bit of SMSC to 1.
Release the SNOOZE mode sequencer from the reset state.
Start supply of the clock signal to the SNOOZE mode sequencer.
Set the code for processing by the sequencer in SMSI0 to SMSI31.
Set data and memory addresses required for processing by the sequencer in SMSG1 to SMSG14. Note that the SMSG0 and SMSG15 registers have the fixed values 0000H and FFFFH, respectively. Select the single source to activate the sequencer.
Make the setting for the sequencer waiting for an activating trigger.
Waiting for the sequencer to start
Processing by the sequencer in progress
Completion of processing by the sequencer
Activating trigger
No
generated?
Yes
The sequencer waits for the activating trigger.
The sequencer handles processing.
The sequencer starts with the processing specified in SMSI0 following arrival of the activating trigger.
Selectable
Processing by the
sequencer is complete.
An INTSMSE interrupt is generated.Note
The interrupt plus termination command being the last to have been handled by the sequencer is followed by generation of an INTSMSE interrupt.
Return to waiting for the activating trigger
Note
If processing by the sequencer ends following the processing for termination command or setting of the trigger bit for forcible termination (the SMSSTOP bit in the SMSC register), an INTSMSE interrupt will not be generated. If processing by the sequencer ends for the latter reason (setting of the trigger bit for forcible termination), the SMSC register itself will be initialized. Therefore, to restart processing by the sequencer, make the initial settings of the SMSC register again (the SMSIp and SMSGn registers are not reset).
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(2) Example of a flow of stopping the SNOOZE mode sequencer Figure 29 - 12 shows an example of a flow of stopping the SNOOZE mode sequencer while it is operating.
Figure 29 - 12 Flow of Stopping the SNOOZE Mode Sequencer
Start of stopping the sequencer
Waiting for the end of the current processing by the
sequencer
Setting for stopping the sequencer
Selectable
No SMSSTAT = 0?
Yes
Set the SMSSTOP bit to 1.
Stopping the SNOOZE mode sequencer
Set the SMSEN bit of PER1 to 0.
Selectable Set the SMSRES bit of PRR1 to 1, and then set it to 0.
End of stopping the sequencer
Wait for the sequencer to finish the processing in progress.
Stop operation of the sequencer.
Stop supply of the clock signal to the SNOOZE mode sequencer. Make these settings if you wish to reset the registers and internal circuits of the SNOOZE mode sequencer.
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29.4.5 States of the SNOOZE mode sequencer
The SNOOZE mode sequencer has four states: the sequencer stopped state, the activating trigger waiting state, the activation pending state, and the sequencer operating state. Transitions between these states proceed according to settings of the registers and input of the activating trigger.
Sequencer stopped state The sequencer enters the stopped state immediately after it is released from the reset state or its operation is forcibly terminated by setting the SMSSTOP bit of the SMSC register to 1. Setting the SMSSTART bit of the SMSC register to 1 places the sequencer in the activating trigger waiting state.
Activating trigger waiting state The activating trigger waiting state is that in which the detection of the activating trigger for the sequencer is enabled by setting the SMSSTART bit of the SMSC register to 1 but the trigger has not yet arrived. Detection of the activating trigger specified by the SMSTRGSEL3 to SMSTRGSEL0 bits of the SMSC register in this state starts the sequencer operating by placing it in the operating state. Note that if the setting of the SMSTRGWAIT bit of the SMSC register is also 1, the sequencer will not start operating and enters the activation pending state. In addition, if operation of the sequencer is forcibly terminated by setting the SMSSTOP bit of the SMSC register to 1, the sequencer enters the sequencer stopped state.
Activation pending state The activation pending state is entered following detection of the activating trigger while the value of the SMSTRGWAIT bit of the SMSC register is 1. Clearing the SMSTRGWAIT bit to 0 in this state starts the sequencer operating by placing the sequencer in the sequencer operating state. If operation of the sequencer is forcibly terminated by setting the SMSSTOP bit of the SMSC register to 1, the sequencer enters the sequencer stopped state.
Sequencer operating state The sequencer operating state is that in which the sequencer is operating and is handling processing specified by the SMSIp registers. Executing the termination or interrupt plus termination command places the sequencer in the activating trigger waiting state. If operation of the sequencer is forcibly terminated by setting the SMSSTOP bit of the SMSC register to 1, the sequencer enters the sequencer stopped state.
The SMSSTART and SMSTRGWAIT bits of the SMSC register and the SMSSTAT bit of the SMSS register can be used to confirm the current state of the SNOOZE mode sequencer.
Table 29 - 4 Correspondence between the Bit Settings and States of the SNOOZE Mode Sequencer
SMSTRGWAIT
SMSSTAT
SMSSTART
State of the SNOOZE Mode Sequencer
0
0
0
Sequencer stopped state
0
0
1
Activating trigger waiting state
0
1
1
Sequencer operating state
1
0
0
Sequencer stopped state
1
0
1
Activating trigger waiting state
1
1
1
Setting prohibited (prohibited state)Note
Note
Enabling holding a trigger pending while the sequencer is in the operating state is prohibited.
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29.5
Commands for Use in Processing by the Sequencer
The sequencer can handle 21 types of processing. For details, see sections 29.5.1 to 29.5.21.
Terms used in the descriptions of the commands (29.5.1 to 29.5.21) are defined below.
· Equivalent CPU command: Assembler language instruction that leads to the same processing as the given command.
· Equivalent CPU operation: Processing expressed in symbolic form · $addr5: 5-bit relative address in 5 of 8 bits (-31 to 0 to 31) · jdisp8: 8-bit signed displacement value (0000 0000B to 0001 1111B, 1111 1111B to1110 0001B) · Number of clock cycles for processing: Number of cycles of the fCLK clock from the time the sequencer starts the
processing until the result of the processing is actually reflected · SMSIp: Sequencer instruction registers (p = 0 to 31) · SMSGn: Sequencer internal data address (n = 0 to 15) for sequencer general-purpose registers, which is stored as
the first operand of most commands · SMSGm: Sequencer internal data address (m = 0 to 15) for sequencer general-purpose registers, which is stored
as the second operand of most commands · Example of a statement: Example of a binary value to be entered in the SMSIp register · Sequencer code: Code that is to be entered in bits 15 to 12 of the SMSIp register and indicates the type of
processing · First operand: Code to be entered in bits 11 to 8 of the SMSIp register · Second operand: Code to be entered in bits 7 to 4 of the SMSIp register · Additional byte: Code to be entered in bits 3 to 0 of the SMSIp register
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29.5.1 8-bit data transfer 1
8-bit data transfer 1 is for transferring 8 bits of data. The value of the SMSGn register specified as the first operand and that of the additional byte are used to specify the address of the destination for transfer in memory. The sequencer transfers the 8 bits of data specified as the second operand in the SMSGm register to the above destination in memory. Set a value in the range from 0 to 7 (from 0000B to 0111B) as the additional byte. To specify an SFR as the destination for transfer, set the address of the SFR that can be manipulated in 8-bit units in the first operand and additional byte. The bit units with which each SFR can be manipulated are the same as those for the CPU. Note that the sequencer general-purpose registers n (n = 0 to 15) can be specified as destinations for transfer. Executing 8-bit data transfer 1 results in a value being stored in the 8 lower-order bits of the specified sequencer general-purpose register n (n = 0 to 15).
Sequencer code: Number of clock cycles for processing: Flags: Equivalent CPU command: Equivalent CPU operation:
0000B 3 cycles of fCLK The states of the SZ and SCY flags are retained. MOV [ SMSGn + Byte ], SMSGm [ SMSGn + Byte ] SMSGm
Symbol
15
14
13
12
11
10
9
8
SMSIp
0
0
0
0
First operand (SMSGn)
7
6
5
4
Second operand (SMSGm)
3
2
1
0
Additional byte (byte)
Example of a statement: 0000 0001 0111 0010 B The equivalent CPU command in this case is MOV [SMSG1+2H], SMSG7. In the case where SMSG1 = FE00H and SMSG7 = xx12H, the value 12H stored in the SMSG7 register will be stored at the address FFE02H.
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29.5.2 8-bit data transfer 2
8-bit data transfer 2 is for transferring 8 bits of data. The value of the SMSGn register specified as the first operand and that of the additional byte are used to specify the address of the source for transfer in memory. The sequencer stores the 8 bits of data at the source address for transfer in the SMSGm register specified as the second operand. Set a value in the range from 0 to 7 (from 0000B to 0111B) as the additional byte. To specify an SFR as the source for transfer, set the address of the SFR that can be manipulated in 8-bit units in the second operand and additional byte. The bit units with which each SFR can be manipulated are the same as those for the CPU. Note that the sequencer general-purpose registers n (n = 0 to 15) can be specified as sources for transfer. Executing 8-bit data transfer 2 results in reading of the value of the 8 lower-order bits of the specified sequencer general-purpose register n (n = 0 to 15).
Sequencer code: Number of clock cycles for processing: Flags: Equivalent CPU command: Equivalent CPU operation:
0001B 3 cycles of fCLK The states of the SZ and SCY flags are retained. MOV SMSGm, [ SMSGn + Byte ] SMSGm [ SMSGn + Byte ]
Symbol
15
14
13
12
11
10
9
8
SMSIp
0
0
0
1
First operand (SMSGn)
7
6
5
4
Second operand (SMSGm)
3
2
1
0
Additional byte (byte)
Example of a statement: 0001 0001 0111 0010 B The equivalent CPU command in this case is MOV SMSG7, [SMSG1+2H]. In the case where SMSG1 = FE00H and FFE02H = xx12H, the value 12H stored at the address FFE02H will be stored in the SMSG7 register.
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29.5.3 16-bit data transfer 1
16-bit data transfer 1 is for transferring 16 bits of data. The value of the SMSGn register specified as the first operand and that of the additional byte are used to specify the address of the destination for transfer in memory. The sequencer transfers the 16 bits of data specified as the second operand in the SMSGm register to the above destination in memory. Specify an even address as the destination for transfer in memory. If an odd address is specified, the LSB of the address is automatically changed to 0 before the data are transferred. Set a value in the range from 0 to 7 (from 0000B to 0111B) as the additional byte. To specify an SFR as the destination for transfer, set the address of the SFR that can be manipulated in 16-bit units in the first operand and additional byte. The bit units with which each SFR can be manipulated are the same as those for the CPU.
Sequencer code: Number of clock cycles for processing: Flags: Equivalent CPU command: Equivalent CPU operation:
0010B 3 cycles of fCLK The states of the SZ and SCY flags are retained. MOVW [ SMSGn + Byte ], SMSGm [ SMSGn + Byte ] SMSGm
Symbol
15
14
13
12
11
10
9
8
SMSIp
0
0
1
0
First operand (SMSGn)
7
6
5
4
Second operand (SMSGm)
3
2
1
0
Additional byte (byte)
Example of a statement: 0010 0001 0111 0010 B The equivalent CPU command in this case is MOVW [SMSG1+2H], SMSG7. In the case where SMSG1 = FE00H and SMSG7 = 1234H, the value 1234H stored in the SMSG7 register will be stored at the addresses FFE02H and FFE03H.
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29.5.4 16-bit data transfer 2
16-bit data transfer 2 is for transferring 16 bits of data. The value of the SMSGn register specified as the first operand and that of the additional byte are used to specify the address of the source for transfer in memory. The sequencer stores the 16 bits of data at the source address for transfer in the SMSGm register specified as the second operand. Specify an even address as the source for transfer in memory. If an odd address is specified, the LSB of the address is automatically changed to 0 before the data are transferred. Set a value in the range from 0 to 7 (from 0000B to 0111B) as the additional byte. To specify an SFR as the source for transfer, set the address of the SFR that can be manipulated in 16-bit units in the second operand and additional byte. The bit units with which each SFR can be manipulated are the same as those for the CPU.
Sequencer code: Number of clock cycles for processing: Flags: Equivalent CPU command: Equivalent CPU operation:
0011B 3 cycles of fCLK The states of the SZ and SCY flags are retained. MOV SMSGm, [ SMSGn + Byte ] SMSGm [ SMSGn + Byte ]
Symbol
15
14
13
12
11
10
9
8
SMSIp
0
0
1
1
First operand (SMSGn)
7
6
5
4
Second operand (SMSGm)
3
2
1
0
Additional byte (byte)
Example of a statement: 0011 0001 0111 0010 B The equivalent CPU command in this case is MOVW SMSG7, [SMSG1+2H]. In the case where SMSG1 = FE00H, and FFE02H and FFE03H = 1234H, the value 1234H stored at the addresses FFE02H and FFE03H will be stored in the SMSG7 register.
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29.5.5 1-bit data setting
1-bit data setting is for setting a specified bit among eight bits of data at a specified address to 1. The value of the SMSGn register specified as the first operand and that of the additional byte are used to specify the address in memory. The second operand is used to specify the number of the bit to be set to 1. Set values in the range from 0 to 7 (from 0000B to 0111B) in the second operand and additional byte. When an SFR is to be specified, set the address of the SFR that can be manipulated in 1-bit units and the bit number as the first operand, second operand, and additional byte. The bit units with which each SFR can be manipulated are the same as those for the CPU.
Sequencer code: Number of clock cycles for processing: Flags: Equivalent CPU command: Equivalent CPU operation:
0100B 4 cycles of fCLK The states of the SZ and SCY flags are retained. SET1 [ SMSGn + Byte ].bit [ SMSGn + Byte ].bit 1
Symbol
15
14
13
12
11
10
9
8
SMSIp
0
1
0
0
First operand (SMSGn)
7
6
5
4
Second operand (bit number)
3
2
1
0
Additional byte (byte)
Example of a statement: 0100 0001 0011 0010 B The equivalent CPU command in this case is SET1 [SMSG1+2H].3. In the case where SMSG1 = FE00H and FFE02H = 0000 0000B, bit 3 at the address FFE02H will be set to 1, making the value at the address FFE02H 0000 1000B.
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29.5.6 1-bit data clearing
1-bit data clearing is for clearing a specified bit among eight bits of data at a specified address to 0. The value of the SMSGn register specified as the first operand and that of the additional byte are used to specify the address in memory. The second operand is used to specify the number of the bit to be cleared to 0. Set values in the range from 0 to 7 (from 0000B to 0111B) in the second operand and additional byte. When an SFR is to be specified, set the address of the SFR that can be manipulated in 1-bit units and the bit number as the first operand, second operand, and additional byte. The bit units with which each SFR can be manipulated are the same as those for the CPU.
Sequencer code: Number of clock cycles for processing: Flags: Equivalent CPU command: Equivalent CPU operation:
0101B 4 cycles of fCLK The states of the SZ and SCY flags are retained. CLR1 [ SMSGn + Byte ].bit [ SMSGn + Byte ].bit 0
Symbol
15
14
13
12
11
10
9
8
SMSIp
0
1
0
1
First operand (SMSGn)
7
6
5
4
Second operand (bit number)
3
2
1
0
Additional byte (byte)
Example of a statement: 0101 0001 0011 0010 B The equivalent CPU command in this case is CLR1 [SMSG1+2H].3. In the case where SMSG1 = FE00H and FFE02H = 0000 1000B, bit 3 at the address FFE02H will be cleared to 0, making the value at the address FFE02H 0000 0000B.
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29.5.7 1-bit data transfer
1-bit data transfer is for transferring the value of a specified bit among eight bits of data at a specified address to the SCY flag. The value of the SMSGn register specified as the first operand and that of the additional byte are used to specify the address of the source for transfer in memory. The second operand is used to specify the bit whose value is to be transferred. Set values in the range from 0 to 7 (from 0000B to 0111B) in the second operand and additional byte. When an SFR is to be specified, set the address of the SFR that can be manipulated in 1-bit units and the bit number as the first operand, second operand, and additional byte. The bit units with which each SFR can be manipulated are the same as those for the CPU.
Sequencer code: Number of clock cycles for processing: Flags:
Equivalent CPU command: Equivalent CPU operation:
0110B 3 cycles of fCLK The state of the SZ flag is retained. The SCY flag reflects the result of the transfer. MOV1 SCY, [ SMSGn + Byte ].bit SCY [ SMSGn + Byte ].bit
Symbol
15
14
13
12
11
10
9
8
SMSIp
0
1
1
0
First operand (SMSGn)
7
6
5
4
Second operand (bit number)
3
2
1
0
Additional byte (byte)
Example of a statement: 0110 0001 0011 0010 B The equivalent CPU command in this case is MOV1 SCY, [SMSG1+2H].3. In the case where SMSG1 = FE00H and FFE02H = 0000 1000B, the value of bit 3 at the address FFE02H will be transferred to the SCY flag, so the SCY flag will be set to 1.
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29.5.8 Word addition
Word addition is for adding two 16-bit values. The values of the SMSGn and SMSGm registers that are specified as the first and second operands are added, and the result is stored in the SMSGn register specified as the first operand. If the result of addition that is stored in the SMSGn register is 0, the SZ flag is set to 1. Otherwise, the flag is cleared to 0. Also, if an arithmetic carry has been generated from bit 15, the SCY flag is set to 1. Otherwise, the flag is cleared to 0. Set the additional byte to 0000B.
Sequencer code: Number of clock cycles for processing: Flags: Equivalent CPU command: Equivalent CPU operation:
0111B (additional byte: 0000B) 1 cycle of fCLK The SZ and SCY flags reflect the result of the calculation. ADDW SMSGn, SMSGm SMSGn, SCY SMSGn + SMSGm
Symbol
15
14
13
12
11
10
9
8
SMSIp
0
1
1
1
First operand (SMSGn)
7
6
5
4
3
2
1
0
Second operand (SMSGm)
0
0
0
0
Example of a statement: 0111 0001 0011 0000 B The equivalent CPU command in this case is ADDW SMSG1, SMSG3. In the case where SMSG1 = FFF0H and SMSG3 = 0010H, the settings of the register and flags as the results of the addition will be as follows: SMSG1 = 0000H, SCY = 1, and SZ = 1.
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29.5.9 Word subtraction
Word subtraction is for subtracting two 16-bit values. The value of the SMSGm register specified as the second operand is subtracted from the value of the SMSGn register specified as the first operand, and then the resulting value is stored in the SMSGn register specified in the first operand. If the result of subtraction that is stored in the SMSGn register is 0, the SZ flag is set to 1. Otherwise, the flag is cleared to 0. Also, if an arithmetic borrow has been generated from bit 0, the SCY flag is set to 1. Otherwise, the flag is cleared to 0. Set the additional byte to 0001B.
Sequencer code: Number of clock cycles for processing: Flags: Equivalent CPU command: Equivalent CPU operation:
0111B (additional byte: 0001B) 1 cycle of fCLK The SZ and SCY flags reflect the result of the calculation. SUBW SMSGn, SMSGm SMSGn, SCY SMSGn - SMSGm
Symbol
15
14
13
12
11
10
9
8
SMSIp
0
1
1
1
First operand (SMSGn)
7
6
5
4
3
2
1
0
Second operand (SMSGm)
0
0
0
1
Example of a statement: 0111 0001 0011 0001 B The equivalent CPU command in this case is SUBW SMSG1, SMSG3. In the case where SMSG1 = 1234H and SMSG3 = 1200H, the settings of the register and flags as the results of the subtraction will be as follows: SMSG1 = 0034H, SCY = 0, and SZ = 0.
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29.5.10 Word comparison
Word comparison is for comparing two 16-bit values. The value of the SMSGm register specified as the second operand is subtracted from the value of the SMSGn register specified as the first operand. If the setting of the SMSGn register as the result of the subtraction is 0, the SZ flag is set to 1. Otherwise, the flag is cleared to 0. Also, if an arithmetic borrow has been generated from bit 0, the SCY flag is set to 1. Otherwise, the flag is cleared to 0. Set the additional byte to 0010B.
Sequencer code: Number of clock cycles for processing: Flags: Equivalent CPU command: Equivalent CPU operation:
0111B (additional byte: 0010B) 1 cycle of fCLK The SZ and SCY flags reflect the result of the calculation. CMPW SMSGn, SMSGm SMSGn - SMSGm
Symbol
15
14
13
12
11
10
9
8
SMSIp
0
1
1
1
First operand (SMSGn)
7
6
5
4
3
2
1
0
Second operand (SMSGm)
0
0
1
0
Example of a statement: 0111 0001 0011 0010 B The equivalent CPU command in this case is CMPW SMSG1, SMSG3. In the case where SMSG1 = 1234H and SMSG3 = 1200H, the settings of the flags as the results of the comparison will be as follows: SCY = 0 and SZ = 0.
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29.5.11 Logical shift right
Logical shift right is for shifting a 16-bit value by 1 bit to the right. The value of the SMSGn register specified as the first operand is shifted by 1 bit to the right. At this time, the MSB (bit 15) of the SMSGn register is set to 0 and the value of the LSB (bit 0) that is shifted out is stored in the SCY flag.
15 0
0 SCY
Set the additional byte to 0011B. Since the second operand is not used, set it to 0000B.
Sequencer code: Number of clock cycles for processing: Flags:
Equivalent CPU command: Equivalent CPU operation:
0111B (additional byte: 0011B) 1 cycle of fCLK The state of the SZ flag is retained. The SCY flag reflects the result of the calculation. SHRW SMSGn SCY SMSGn.0, SMSGn.m-1 SMSGn.m, SMSGn.15 0
Symbol
15
14
13
12
11
10
9
8
SMSIp
0
1
1
1
First operand (SMSGn)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
1
Example of a statement: 0111 0001 0000 0011 B The equivalent CPU command in this case is SHRW SMSG1. In the case where SMSG1 = AAF5H, the settings of the register and flag as the results of the logical shift will be as follows: SMSG1 = 557AH and SCY = 1.
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29.5.12 Branch 1 (SCY = 1)
Branch 1 is for processing to branch if SCY = 1. With SCY = 1, program control branches to the processing stored in the SMSIp register at the relative address specified as the first and second operands. If SCY = 0, processing proceeds to that set in the next SMSIp register. Set the additional byte to 0000B. Set values in the range from -31 to 31 as the first and second operands.
Sequencer code: Number of clock cycles for processing: Flags: Equivalent CPU command: Equivalent CPU operation:
1000B (additional byte: 0000B) 1 cycle of fCLK The states of the SZ and SCY flags are retained. BC $addr5 SMSCV[4:0] SMSCV[4:0] + jdisp8 if SCY = 1
Symbol
15
14
13
12
11
10
9
8
SMSIp
1
0
0
0
First and second operands ($addr5)
7
6
5
4
3
2
1
0
First and second operands ($addr5)
0
0
0
0
Example of a statement: 1000 0000 0101 0000 B The equivalent CPU command in this case is BC $05H. In the case where the value of the SMSCV[4:0] bits of the SMSS register is 03H, and SCY = 1, the value of the SMSCV[4:0] bits will be 08H, so processing will proceed to that stored in the SMSI8 register.
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CHAPTER 29 SNOOZE MODE SEQUENCER (SMS)
29.5.13 Branch 2 (SCY = 0)
Branch 2 is for processing to branch if SCY = 0. With SCY = 0, program control branches to the processing stored in the SMSIp register at the relative address specified as the first and second operands. If SCY = 1, processing proceeds to that set in the next SMSIp register. Set the additional byte to 0001B. Set values in the range from -31 to 31 as the first and second operands.
Sequencer code: Number of clock cycles for processing: Flags: Equivalent CPU command: Equivalent CPU operation:
1000B (additional byte: 0001B) 1 cycle of fCLK The states of the SZ and SCY flags are retained. BNC $addr5 SMSCV[4:0] SMSCV[4:0] + jdisp8 if SCY = 0
Symbol
15
14
13
12
11
10
9
8
SMSIp
1
0
0
0
First and second operands ($addr5)
7
6
5
4
3
2
1
0
First and second operands ($addr5)
0
0
0
1
Example of a statement: 1000 1111 1110 0001 B The equivalent CPU command in this case is BNC $0FEH In the case where the value of the SMSCV[4:0] bits of the SMSS register is 0EH, and SCY = 0, the value of the SMSCV[4:0] bits will be 0CH, so processing will proceed to that stored in the SMSI12 register.
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CHAPTER 29 SNOOZE MODE SEQUENCER (SMS)
29.5.14 Branch 3 (SZ = 1)
Branch 3 is for processing to branch if SZ = 1. With SZ = 1, program control branches to the processing stored in the SMSIp register at the relative address specified as the first and second operands. If SZ = 0, processing proceeds to that set in the next SMSIp register. Set the additional byte to 0010B. Set values in the range from -31 to 31 as the first and second operands.
Sequencer code: Number of clock cycles for processing: Flags: Equivalent CPU command: Equivalent CPU operation:
1000B (additional byte: 0010B) 1 cycle of fCLK The states of the SZ and SCY flags are retained. BZ $addr5 SMSCV[4:0] SMSCV[4:0] + jdisp8 if SZ = 1
Symbol
15
14
13
12
11
10
9
8
SMSIp
1
0
0
0
First and second operands ($addr5)
7
6
5
4
3
2
1
0
First and second operands ($addr5)
0
0
1
0
Example of a statement: 1000 0000 0101 0010 B The equivalent CPU command in this case is BZ $05H. In the case where the value of the SMSCV[4:0] bits of the SMSS register is 03H, and SZ = 1, the value of the SMSCV[4:0] bits will be 08H, so processing will proceed to that stored in the SMSI8 register.
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CHAPTER 29 SNOOZE MODE SEQUENCER (SMS)
29.5.15 Branch 4 (SZ = 0)
Branch 4 is for processing to branch if SZ = 0. With SZ = 0, program control branches to the processing stored in the SMSIp register at the relative address specified as the first and second operands. If SZ = 1, processing proceeds to that set in the next SMSIp register. Set the additional byte to 0011B. Set values in the range from -31 to 31 as the first and second operands.
Sequencer code: Number of clock cycles for processing: Flags: Equivalent CPU command: Equivalent CPU operation:
1000B (additional byte: 0011B) 1 cycle of fCLK The states of the SZ and SCY flags are retained. BNZ $addr5 SMSCV[4:0] SMSCV[4:0] + jdisp8 if SZ = 0
Symbol
15
14
13
12
11
10
9
8
SMSIp
1
0
0
0
First and second operands ($addr5)
7
6
5
4
3
2
1
0
First and second operands ($addr5)
0
0
1
1
Example of a statement: 1000 1111 1110 0011 B The equivalent CPU command in this case is BNZ $0FEH. In the case where the value of the SMSCV[4:0] bits of the SMSS register is 0EH, and SZ = 0, the value of the SMSCV[4:0] bits will be 0CH, so processing will proceed to that stored in the SMSI12 register.
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CHAPTER 29 SNOOZE MODE SEQUENCER (SMS)
29.5.16 Wait
The wait command holds processing pending for a certain period. Execution of processing is held pending for the number of cycles of fWAIT specified in the second operand by using the clock and division ratio specified as the first operand and additional byte. Use the first and second operands to select the source clock for counting of the wait time and the value to be counted as the wait period, and use the additional byte to select the clock for use in waiting, specifically, select the divisor for the frequency of the selected source clock. If the low-speed on-chip oscillator clock is to be used as the source clock for counting of the wait time, set the LONGWAIT bit of the SMSC register to 1 in advance.
Sequencer code: Number of clock cycles for processing: Flags: Equivalent CPU command: Equivalent CPU operation:
1001B See the description titled "(1) Number of clock cycles for use in waiting". The states of the SZ and SCY flags are retained. WAIT IM1, IM2 Holding processing pending for a certain period
Symbol
15
14
13
12
11
10
9
8
SMSIp
1
0
0
1
First and second operands (IM1)
7
6
5
4
First and second operands (IM1)
3
2
1
0
Additional byte (IM2)
IM1[7]
0 1
Selection of the Source Clock fSMS for Use in Waiting
fCLK fILNotes 1, 2
IM1[6:0] Selection of the Wait Time
0000000 0000001 0000010
· · · 1111110 1111111
128/fWAIT 1/fWAIT 2/fWAIT · · ·
126/fWAIT 127/fWAIT
IM2
0000 0001 0010 0011 0100
Selection of the Clock (fWAIT) for Use in Waiting
fSMS fSMS/2 fSMS/4 fSMS/8 fSMS/16
0101 0110 0111 Other than the above
fSMS/32 fSMS/64 fSMS/128 Settings prohibited
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CHAPTER 29 SNOOZE MODE SEQUENCER (SMS)
Example of a statement:
Example of the Setting of the SMSIp Register
Source Clock for Use in Waiting
Clock for Use in Waiting
Number to Count for Waiting
Wait Time in µs (typ.)
1001 0 0000001 0000
fCLK
fCLK
1
1001 0 0000000 0111
fCLK
fCLK/128
128
1001 0 1000000 0110
fCLK
fCLK/64
64
0.03125 512 128
1001 1 0000001 0000
fIL
fIL
1
1001 1 0000000 0111
fIL
fIL/128
128
1001 1 1100000 0101
fIL
fIL/32
96
30.51757813 500000 93750
Note 1. Note 2.
When the low-speed on-chip oscillator clock (fIL) is in use for the CPU/peripheral hardware clock frequency (fCLK), select fCLK (IM1[7] = 0) as the source clock fSMS for counting the wait time. When the low-speed on-chip oscillator clock (fIL) is to be used as the source clock for the timing of waiting by the SNOOZE mode sequencer, set peripheral enable register 0 (PER0) and peripheral enable register 1 (PER1) to 00H and 40H, respectively.
Remark fCLK: CPU/peripheral hardware clock frequency fIL: Low-speed on-chip oscillator clock frequency (32.768 kHz)
(1) Number of clock cycles for use in waiting The number of clock cycles for use in waiting depends on the setting of the wait command. Refer to values set for IM1 and IM2 to calculate the required processing time. Note that the wait processing requires time for synchronization before the counter for use in timing the wait starts operating and after the counter finishes operating. Refer to an example described below to calculate the time for synchronization. Before execution of the wait command: (1 cycle of fCLK) + (2Note cycles of the selected clock for use in waiting)
After execution of the wait command: 2Note cycles of fCLK
Note
This is the number of clock cycles for synchronization and will be no greater than 2. This time may also be extremely close to 1 cycle with some types of timing.
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CHAPTER 29 SNOOZE MODE SEQUENCER (SMS)
29.5.17 Conditional wait 1 (bit = 1)
In conditional wait 1, processing is repeatedly held pending as long as the value of a specified bit among eight bits of data at a specified address is 1. The value of the SMSGn register specified as the first operand and that of the additional byte are used to specify the address in memory. The second operand is used to specify the target bit for the condition. The sequencer reads the specified bit. If the setting is 1, the sequencer does not handle the succeeding processing but goes into wait processing. The sequencer repeats this as long as the value of the specified bit is 1. When reading from the specified bit returns 0, the sequencer handles the succeeding processing. Set a value in the range from 0 to 7 (from 0000B to 0111B) as the second operand. When an SFR is to be specified, set the address of the SFR that can be manipulated in 1-bit units and the bit number as the first operand, second operand, and additional byte. The bit units with which each SFR can be manipulated are the same as those for the CPU.
Sequencer code: Number of clock cycles for processing:
Flags: Equivalent CPU command: Equivalent CPU operation:
1010B See the description titled "(1) Number of clock cycles required for conditional wait 1". The states of the SZ and SCY flags are retained. WHILE1 [ SMSGn + Byte ].bit SMSS[4:0] SMSS[4:0] if [ SMSGn + Byte ].bit = 1
Symbol
15
14
13
12
11
10
9
8
SMSIp
1
0
1
0
First operand (SMSGn)
7
6
5
4
Second operand (bit number)
3
2
1
0
Additional byte (byte)
Example of a statement: 1010 0011 0101 0010 B The equivalent CPU command in this case is WHILE1 [SMSG3+2].5. In the case where SMSG3 = 02E8H, the sequencer holds processing pending as long as the value of bit 5 at address F02EAH is 1. When the value of the bit becomes 0, the sequencer handles the succeeding processing.
(1) Number of clock cycles required for conditional wait 1 In conditional wait 1 processing, access to the specified bit is repeated until its value becomes 0. Starting the processing requires one cycle of fCLK and each round of reference to the register bit and judgement requires two cycles of fCLK. For example, the time set up in the case where the fifth access to the bit for reference of the destination register returns 0 is calculated from the following formula. fCLK × 1 + (fCLK × 2) × 5 = fCLK × 11 Note that if attempted access to memory by the SNOOZE mode sequencer is in contention with access by the CPU or DTC, the SNOOZE mode sequencer may be placed in the pending state. Such cases also increase the number of clock cycles.
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CHAPTER 29 SNOOZE MODE SEQUENCER (SMS)
29.5.18 Conditional wait 2 (bit = 0)
In conditional wait 2, processing is repeatedly held pending as long as the value of a specified bit among eight bits of data at a specified address is 0. The value of the SMSGn register specified as the first operand and that of the additional byte are used to specify the address in memory. The second operand is used to specify the target bit for the condition. The sequencer reads the specified bit. If the setting is 0, the sequencer does not handle the succeeding processing but goes into wait processing. The sequencer repeats this as long as the value of the specified bit is 0. When reading from the specified bit returns 1, the sequencer handles the succeeding processing. Set a value in the range from 0 to 7 (from 0000B to 0111B) as the second operand. When an SFR is to be specified, set the address of the SFR that can be manipulated in 1-bit units and the bit number as the first operand, second operand, and additional byte. The bit units with which each SFR can be manipulated are the same as those for the CPU.
Sequencer code: Number of clock cycles for processing:
Flags: Equivalent CPU command: Equivalent CPU operation:
1011B See the description titled "(1) Number of clock cycles required for conditional wait 2". The states of the SZ and SCY flags are retained. WHILE0 [ SMSGn + Byte ].bit SMSS[4:0] SMSS[4:0] if [ SMSGn + Byte ].bit = 0
Symbol
15
14
13
12
11
10
9
8
SMSIp
1
0
1
1
First operand (SMSGn)
7
6
5
4
Second operand (bit number)
3
2
1
0
Additional byte (byte)
Example of a statement: 1011 0011 0101 0010 B The equivalent CPU command in this case is WHILE0 [SMSG3+2].5. In the case where SMSG3 = FFE0H, the sequencer holds processing pending as long as the value of bit 5 at address FFFE2H is 0. When the value of the bit becomes 1, the sequencer handles the succeeding processing.
(1) Number of clock cycles required for conditional wait 2 Since the number of clock cycles of waiting set up by conditional wait 2 is counted in the same way as described for conditional wait 1, refer to 29.5.17 (1) Number of clock cycles required for conditional wait 1.
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CHAPTER 29 SNOOZE MODE SEQUENCER (SMS)
29.5.19 Termination
The termination command stops the SNOOZE mode sequencer. Specifically, execution of the command stops the SNOOZE mode sequencer, clears the SMSSTAT and SMSCV[4:0] bits in the SMSS register to 0, and places the sequencer in the activating trigger waiting state. Set the additional byte to 0000B. Set all bits of the first and second operands to 0.
Sequencer code: Number of clock cycles for processing: Flags: Equivalent CPU command: Equivalent CPU operation:
1111B (additional byte: 0000B) 1 cycle of fCLK The states of the SZ and SCY flags are retained. FINISH SMSCV[4:0] 0, stopping the sequencer
Symbol
15
14
13
12
11
10
9
8
SMSIp
1
1
1
1
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Example of a statement: 1111 0000 0000 0000 B The equivalent CPU command in this case is FINISH. The termination command stops the sequencer, clears the SMSSTAT and SMSCV[4:0] bits of the SMSS register to 0, and places the sequencer in the activating trigger waiting state.
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CHAPTER 29 SNOOZE MODE SEQUENCER (SMS)
29.5.20 Interrupt plus termination
The interrupt plus termination command issues an interrupt signal and then stops the SNOOZE mode sequencer. Issuing the interrupt signal enables starting the CPU when it has been placed on standby. Specifically, execution of the command issues the interrupt signal, stops the SNOOZE mode sequencer, clears the SMSSTAT and SMSCV[4:0] bits in the SMSS register to 0, and places the sequencer in the activating trigger waiting state. Set the additional byte to 0001B. Set all bits of the first and second operands to 0.
Sequencer code: Number of clock cycles for processing: Flags: Equivalent CPU command: Equivalent CPU operation:
1111B (additional byte: 0001B) 1 cycle of fCLK The states of the SZ and SCY flags are retained. WAKEUP SMSS[4:0] 0, stopping the sequencer after issuing an interrupt
Symbol
15
14
13
12
11
10
9
8
SMSIp
1
1
1
1
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
Example of a statement: 1111 0000 0000 0001 B The equivalent CPU command in this case is WAKEUP. The interrupt plus termination command stops the sequencer after issuing an INTSMSE interrupt, clears the SMSSTAT and SMSCV[4:0] bits of the SMSS register to 0, and places the sequencer in the activating trigger waiting state.
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CHAPTER 29 SNOOZE MODE SEQUENCER (SMS)
29.5.21 DTC activation
The DTC activation command issues a DTC activating source signal so that DTC transfer proceeds. That is, execution of the command issues an activating source signal for the DTC. If the corresponding control settings for the DTC have been made in advance, the specified DTC transfer will proceed. Set the additional byte to 0010B. Set all bits of the first and second operands to 0.
Sequencer code: Number of clock cycles for processing: Flags: Equivalent CPU command: Equivalent CPU operation:
1111B (additional byte: 0010B) 1 cycle of fCLK The states of the SZ and SCY flags are retained. DTCTRG Output of a DTC activating source signal
Symbol
15
14
13
12
11
10
9
8
SMSIp
1
1
1
1
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
Example of a statement: 1111 0000 0000 0010 B The equivalent CPU command in this case is DTCTRG. The DTC activation command issues a DTC activating source signal. DTC transfer proceeds according to the DTC control settings. To hold processing by the sequencer pending until completion of DTC transfer, use the wait command to hold processing pending until the DTC has been started, and then use conditional wait 1 to hold the processing pending until the corresponding bit of DTC activation enable register i (DTCENi) (i = 0 to 4) has been set to 0.
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CHAPTER 29 SNOOZE MODE SEQUENCER (SMS)
29.6
Operation in Standby Modes
HALT mode
State
Operation of the SNOOZE Mode Sequencer Operation continues.Note 1
STOP mode SNOOZE mode
The activating trigger for the SNOOZE mode sequencer can be accepted.Note 3
Operation continues.Notes 2, 4, 5, 6
Note 1. Note 2. Note 3.
Note 4.
Note 5.
Note 6.
When the subsystem clock is selected as fCLK, operation is disabled if the RTCLPC bit of the OSMC register is 1. The SNOOZE mode can only be set when the high-speed on-chip oscillator clock or middle-speed on-chip oscillator clock is selected as fCLK. Detection of an SMS activating trigger in STOP mode places the chip in SNOOZE mode, making the SNOOZE mode sequencer capable of operation. The state of the chip returns to the STOP mode after the operations of the SMS are completed. Note that the sequencer does not have access to certain memory areas in SNOOZE mode. For details, see 29.4.2 Memory space allocated to the sequencer. When a transfer end interrupt from the CSIp in SNOOZE mode is being used as the activating trigger for the SNOOZE mode sequencer, use the interrupt plus termination command to release the chip from the SNOOZE mode and start processing by the CPU, or make the settings for reception by the CSIp (writing 1 to the STm0 bit, writing 0 to the SWCm bit, setting the SSCm register, and writing 1 to the SSm0 bit) again before the processing for termination. When a transfer end interrupt from the UARTq in SNOOZE mode is being used as the activating trigger for the SNOOZE mode sequencer, use the interrupt plus termination command to release the chip from the SNOOZE mode and start processing by the CPU, or make the settings for reception by the UARTq (writing 1 to the STm1 bit, writing 0 to the SWCm bit, setting the SSCm register, and writing 1 to the SSm1 bit) again before the processing for termination. When an A/D conversion end interrupt from the A/D converter in SNOOZE mode is being used as the activating trigger for the SNOOZE mode sequencer, use the interrupt plus termination command to release the chip from the SNOOZE mode and start processing by the CPU, or make the settings for the SNOOZE mode function of the A/D converter (writing 1 to the AWC bit after having written 0 to it) again before the processing for termination.
Remark
Products with 30 to 64 pins: p = 00; m = 0 Products with 80 to 128 pins: p = 00, 20; m = 0, 1
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CHAPTER 30 CAPACITIVE SENSING UNIT (CTSU2L)
CHAPTER 30 CAPACITIVE SENSING UNIT (CTSU2L)
The number of output channels of the capacitive sensing unit depends on the product.
ROM size
Pin count
Number of the CTSU2L output channels
30
2 (TS00, TS01)
32
3 (TS00 to
TS02)
36
5 (TS00 to
TS04)
64 to 128 Kbytes
40, 44
48
52
6 (TS00 to
TS05)
8 (TS00 to
TS07)
10 (TS00 to
TS09)
64
12 (TS00 to
TS11)
80
100
30 (TS00 to TS15, TS20 to TS33)
32 (TS00 to TS15, TS20 to TS35)
ROM size
Pin count
Number of the CTSU2L output channels
30
6 (TS00, TS01, TS20, TS21, TS26, TS27)
192 to 768 Kbytes
32
36
40
44
48
52
64
80
100, 128
7 (TS00 to
TS02, TS20, TS21, TS26, TS27)
11 (TS00 to
TS04, TS20 to TS23, TS26, TS27)
13 (TS00 to
TS05, TS20 to TS24, TS26, TS27)
14 (TS00 to
TS05, TS20 to TS27)
16 (TS00 to
TS07, TS20 to TS27)
20 (TS00 to
TS09, TS20 to TS29)
22 (TS00 to
TS11, TS20 to TS29)
30 (TS00 to
TS15, TS20 to TS33)
32 (TS00 to
TS15, TS20 to TS35)
The Capacitive Sensing Unit (CTSU2L) measures the electrostatic capacitance of the capacitive sensor. Changes in the electrostatic capacitance are determined by software, which enables the CTSU2L to detect whether a finger is in contact with the capacitive sensor. The electrode surface of the capacitive sensor is usually enclosed with an electrical conductor so that a finger does not come into direct contact with the electrode. As shown in Figure 30 - 1, electrostatic capacitance (parasitic capacitance) exists between the electrode and the surrounding conductors. Because the human body is an electrical conductor, when a finger is placed close to the electrode, the electrostatic capacitance value increases.
Figure 30 - 1 Increased Electrostatic Capacitance Because of the Presence of a Finger
Circuit board pattern
Circuit board pattern
Touchsensing microcontroller
Touch sensor
Touchsensing microcontroller
Touch sensor
Finger
Metal enclosure Ground
Metal enclosure Ground
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CHAPTER 30 CAPACITIVE SENSING UNIT (CTSU2L)
Electrostatic capacitance is detected by the self-capacitance and mutual capacitance methods. In the self-capacitance method, the CTSU detects electrostatic capacitance generated between a finger and a single electrode. In the mutual capacitance method, two electrodes are used; one electrode is used as a transmit electrode and the other electrode is used as a receive electrode. The CTSU detects a change in the electrostatic capacitance generated between these electrodes when a finger is placed close to them.
Figure 30 - 2 Self-capacitance Method and Mutual Capacitance Method
Self-capacitance method
Mutual capacitance method
Electrical conductor (panel)
Electrode Board
Touch sensor
Touch-sensing microcontroller
Touch-sensing microcontroller (transmission ) (reception)
Electrostatic capacitance is measured by counting clock signal cycles whose frequency changes according to the amount of charged or discharged current for a specified period. For details of the principles of measurement operation, see related application notes.
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CHAPTER 30 CAPACITIVE SENSING UNIT (CTSU2L)
<R> <R>
30.1
Overview
Table 30 - 1 lists the CTSU functions and Figure 30 - 3 shows a block diagram of the CTSU. Figure 30 - 4 shows the sensor drive pulse output clock configuration.
Table 30 - 1 CTSU Functions
Item
Configuration
CTSU2L operating voltage condition
VDD = 1.8 to 5.5 V
Operating clock
fCLK, fCLK/2, fCLK/4, or fCLK/8
Pins
Electrostatic capacitance
TSm (m = 00 to 15, 20 to 35) up to 32 channels
measurement
Connection pin to capacitor for TSCAP (10 nF) measurement secondary power We recommend connecting a 10-nF capacitor.
Measurement mode
Self-capacitance measurement Electrostatic capacitance is measured from the charged current that flows toward
mode
the electrode used in the self-capacitance method.
Mutual capacitance measurement mode
Electrostatic capacitance is measured from the charged current that flows toward the capacitance generated between the transmit and receive electrodes used in the mutual capacitance method.
DC current measurement mode Current from a measurement pin is measured.
Calibration mode
Characteristic correction of the current control oscillator for measurement
Noise prevention
Synchronous noise prevention, high-pass noise prevention Majority decision by multi-frequency measurement
Adjustment for each pin
Offset current adjustment function Sensor drive pulse frequency specification Measurement time specification
Measurement start conditions
Software trigger External trigger (ELCL)
Low-power function
SNOOZE function supported
Requests
Data transfer request
Channel measurement setting write request Measurement result read request
Interrupt request
Measurement end interrupt request
Transmission power switching of mutual capacitance method
The power for transmission in the mutual capacitance method can be switched among VDD (VCL), VCC (I/O port), and VCC (dedicated).
As shown in Figure 30 - 3, the CTSU consists of a status control block, a trigger control block, a clock control block, a channel control block, a port control block, a sensor drive pulse generator, a measurement block, an interrupt block, an IO block, a SNOOZE control block, and SFRs.
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RL78/G23 Figure 30 - 3 CTSU Block Diagram
CHAPTER 30 CAPACITIVE SENSING UNIT (CTSU2L)
Event input from the ELCL fCLK
fCLK/2 fCLK/22 fCLK/23
CTSU_CTSUWR CTSU_CTSURD CTSU_CTSUFN
Capacitive Sensing Unit (CTSU)
Trigger control block
Channel control block
Port control block
Pin control
Clock control block
Count source
SNOOZE control block
Status control
Sensor drive pulse generator
Sensor drive pulse
SUCLK
SUCLK oscillator
Operation enabled Offset control
Power supply
Offset current source
Interrupt block
Measurement block (counter measurement) · Sensor counter register
Sensor clock
Sensor oscillator
SFRs (control registers)
Port control
I/O port
TSn
Sensor IO
Power supply
Power supply selection
Dedicated IO
TSCAP
LPF
Data bus
Figure 30 - 4 Sensor Drive Pulse Output Clock Configuration
CTSUCRA.CLK[1:0]
CTSUSO.SDPA[7:0]
CTSUCRB.PRMODE[1:0] CTSUCRB.PRRATIO[3:0]
CTSUSO.SSDIV[3:0]
CTSUCRB.SOFF
fCLK fCLK/2 fCLK/22 fCLK/23
CTSU hardware
macro
Clock control block
Operating clock
Sensor drive
pulse basic
timing generation
Base clock
Phase shift
SUCLK
Sensor drive pulse (random pulse mode) generator
State Frequency clock
division
State control
Edge diffusion
Jitter sensor drive pulse
Base sensor drive pulse
Sensor drive pulse (high resolution pulse mode) generator
Frequency division
Sensor drive pulse (random pulse)
Sensor drive pulse (high resolution pulse)
CTSUCRA.STCLK[5:0]
CTSUCRB.SSCNT[1:0] CTSUCRB.SSMOD[2:0] CTSUTRIMA.SUADJD[7:0]
CTSUSUCLKx.SUADJx[7:0] CTSUSUCLKx.SUMULTIx[7:0] CTSUCRA.FCMODE CTSUMCHx.MCAx
CTSUSO.SDPA[7:0]
Table 30 - 2 External Pins Used in CTSU
Pin name
Input/output
TSm (m = 00 to 15, 20 to 35) Output
TSCAP
--
Function
Electrostatic capacitance measurement pin, transmit pin in the mutual capacitance method, active shield control pin, or current measurement pin
Connection pin to capacitor for measurement secondary power
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CHAPTER 30 CAPACITIVE SENSING UNIT (CTSU2L)
30.2
Registers to Control the Capacitive Sensing Unit
The following registers are used to control the capacitive sensing unit.
· Peripheral enable register 1 (PER1) · Peripheral reset control register 1 (PRR1) · CTSU control registers AL and AH (CTSUCRAL, CTSUCRAH) · CTSU control registers BL and BH (CTSUCRBL, CTSUCRBH) · CTSU measurement channel registers L and H (CTSUMCHL, CTSUMCHH) · CTSU channel enable control registers AL, AH, BL, and BH
(CTSUCHACAL, CTSUCHACAH, CTSUCHACBL, CTSUCHACBH) · CTSU channel transmit/receive control registers AL, AH, BL, and BH
(CTSUCHTRCAL, CTSUCHTRCAH, CTSUCHTRCBL, CTSUCHTRCBH) · CTSU status register L (CTSUSRL) · CTSU sensor offset registers 0 and 1 (CTSUSO0, CTSUSO1) · CTSU sensor counter registers L and H (CTSUSC, CTSUUC) · CTSU calibration registers L and H (CTSUDBGR0, CTSUDBGR1) · CTSU sensor unit clock control registers AL, AH, BL, and BH
(CTSUSUCLK0, CTSUSUCLK1, CTSUSUCLK2, CTSUSUCLK3) · CTSU trimming registers AL and AH (CTSUTRIM0, CTSUTRIM1) · CTSU trimming registers BL and BH (CTSUTRIM2, CTSUTRIM3)
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30.2.1 Peripheral enable register 1 (PER1)
This register is used to enable or disable the supply of a clock signal to various on-chip peripheral modules. Clock supply to an on-chip peripheral module that is not to be used can be stopped to decrease power consumption and noise. If the CTSU is to be used, be sure to set bit 0 (CTSUEN) of this register to 1. The PER1 register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 30 - 5 Format of Peripheral Enable Register 1 (PER1)
Address: After reset: R/W:
F00FAH 00H R/W
Symbol
<7>
PER1 DACEN
<6> SMSEN
<5> CMPEN
<4> TML32EN
<3> DTCEN
<2> UTAEN
<1> REMCEN
<0> CTSUEN
CTSUEN
Control of supply of an input clock to the CTSU
0
Stops supply of an input clock.
· The SFRs used by the CTSU cannot be written.
· When an SFR used by the CTSU is read, the value returned is 00H or 0000H.
1
Enables supply of an input clock.
· The SFRs used by the CTSU can be read and written.
30.2.2 Peripheral reset control register 1 (PRR1)
The PRR1 register is used to control resetting of the on-chip peripheral modules. Each bit in this register controls resetting and release from the reset state of the corresponding on-chip peripheral module. The PRR1 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Figure 30 - 6 Format of Peripheral Reset Control Register 1 (PRR1)
Address: After reset: R/W:
F00FBH 00H R/W
Symbol
<7>
PRR1 DACRES
<6>
<5>
<4>
<3>
SMSRES CMPRES TML32RES DTCRES
<2>
<1>
<0>
UTARES REMCRES CTSURES
CTSURES
Control resetting of the CTSU
0
The CTSU is released from the reset state.
The CTSU is in the reset state. 1
· The SFRs for use with the CTSU2L are initialized.
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30.2.3 CTSU control registers AL and AH (CTSUCRAL, CTSUCRAH)
The CTSUCRAL register can be accessed in 8-bit units (CTSUCR1 as upper part and CTSUCR0 as lower part). The CTSUCRAH register can be accessed in 8-bit units (CTSUCR3 as upper part and CTSUCR2 as lower part).
Figure 30 - 7 Format of CTSU Control Registers AL and AH (CTSUCRAL, CTSUCRAH)
Address: After reset: R/W:
F0500H, F0502H 0000H R/W
Symbol
15
14
13
12
11
10
9
8
CTSUCRAH DCBACK DCMODE
STCLK[5:0]
7 FCMODE
6 SDPSEL
Symbol CTSUCRAL
15
MD1
14
MD0
5
4
POSEL[1:0]
13
12
CLK[1:0]
3 LOAD1
2 LOAD0
1 ATUNE2
11
10
ATUNE1 ATUNE0
9
CSW
0 0
8
PON
7
6
5
4
3
2
1
0
TXVSEL TXVSEL2 PUMPON
INIT
0
SNZ
CAP
STRT
DCBACK
Current Measurement Feedback Select
0
Selects TSCAP-I/O.
1
Selects measurement pin.
This bit is valid only when DCMODE = 1 to switch the pin for feedback to measurement power.
VDC VREF
ON when CSW = 1
TSCAP
IDLE current OFF during measurement when LOAD0 = 1
ADC
ANI30
OFF during measurement when DCBACK = 1
High level is output without a pulse
when DCMODE = 1 Current
measurement
ON during measurement when DCBACK = 1
DCMODE
Current Measurement Mode Select
0
Normal mode
1
Current measurement mode
Measures current without switched capacitor operation. Outputs a fixed value to the measurement reception pin according to the IOC bit and stops the drive pulse. IOC = 0: High-level output IOC = 1: Low-level output
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STCLK[5:0]
STCLK Select
0
0
0
0
0
0
Peripheral clock divided by 2
0
0
0
0
0
1
Peripheral clock divided by 4
0
0
0
0
1
0
Peripheral clock divided by 6
0
0
0
0
1
1
Peripheral clock divided by 8
:
:
:
:
:
:
:
1
1
1
1
1
0
Peripheral clock divided by 126
1
1
1
1
1
1
Peripheral clock divided by 128
These bits set the division value for fCLK (after prescaler) to obtain STCLK. STCLK is related to measurement time and clock recovery cycle. The division value is determined by the following equation. Division value = (STCLK[5:0] + 1) × 2 (divided by 2 to 128)
Setting STCLK to 0.5 MHz (2 µs) is recommended.
FCMODE
Sensor unit clock (SUCLK) Select
0
SUCLK is used as frequency diffusion clock.
1
SUCLK is used as recovery clock for multi-clock measurement.
To use SUCLK as recovery clock, set the CTSUDBGR1.CCOCLK bit to 1.
· When the FCMODE bit is 0 (SUCLK used as frequency diffusion clock)
As specified in the CTSUTRIM1.SUADJD[7:0], CTSUCRBH.SSCNT[1:0], and CTSUCRBH.SSMOD[2:0], SUCLK is generated when the digital oscillator oscillates and the frequency is spectrum-diffused.
· When the FCMODE is 1 (SUCLK used as recovery clock for multi-clock measurement)
As specified in the CTSUSUCLK0, CTSUSUCLK1, CTSUSUCLK2, or CTSUSUCLK3 register, SUCLK is generated when the clock recovery control is performed. Before setting the FCMODE bit to 1, set the CTSUSUCLK0, CTSUSUCLK1, CTSUSUCLK2, or CTSUSUCLK3 register. The recovery is performed in status 0 (non-measurement state) for all selected clocks during measurement. The SUADJx bits in the CTSUSUCLK0, CTSUSUCLK1, CTSUSUCLK2, or CTSUSUCLK3 register are updated by recovery (x = 0 to 3). When the FCMODE bit is 1, do not change the CTSUSUCLK0, CTSUSUCLK1, CTSUSUCLK2, or CTSUSUCLK3 register setting.
<Relationship between SDPSEL and FCMODE>
SDPSEL 0 1
FCMODE 0 1
Other than above
Operation CTSU compatible setting Sensor unit clock (SUCLK) mode Used for multi-clock measurement
Setting prohibited
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SDPSEL
Sensor Drive Pulse Select
0
Random pulse mode (CTSU compatible setting)
fCLK divided by the settings of the CTSUCRAL.CLK[1:0] and CTSUSO1.SDPA[7:0] bits is used as the base clock, and the sensor drive pulse is obtained by phase-shifting the base clock using the random number generated according to the settings of the CTSUCRBL.PRMODE[1:0] and CTSUCRBL.PRRATIO[3:0] bits. It is also possible to apply jitter by the frequency diffusion clock.
1
Sensor unit clock (SUCLK) mode
The sensor drive pulse is obtained by applying frequency recovery based on fCLK to generate SUCLK and dividing it by the CTSUSO1.SDPA[7:0] setting.
The SDPSEL bit selects the sensor drive pulse.
POSEL[1:0]
Non-measured Pin Output Select
0
0
Low-level output (from the I/O port regardless of the TXVSEL and TXVSEL2
settings)
0
1
Hi-z (high impedance) output
1
0
Low-level output (by the TXVSEL and TXVSEL2 settings)
1
1
Same phase (transmission) pulse output (by the TXVSEL and TXVSEL2
settings)
The POSEL[1:0] bits select the non-measured pin output.
[Example] When measurement is performed by the self-capacitance method using the electrode shown below to enable the active shield function: · Shield pin: TS3
Set the transmit/receive control register to 1 to output a transmit pulse to use TS3 as a shield pin.
· Measurement pins: TS0 to TS2 Set the POSEL[1:0] bits to 11B. The same pulse as the shield pin is output from the non-measured pin.
TS3
TS0
TS1
TS2
LOAD[1:0]
Measurement Load Control
0
0
2.5-µA constant current load mode
0
1
No-load mode
1
0
20-µA constant current load mode
1
1
Resistive load mode (for calibration)
To place the measurement load in the resistive load mode, set these bits to 01B and then set them to 11B.
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<R>
ATUNE2
Analog Adjustment 2
0
Follows the ATUNE1 setting.
1
When ATUNE1 is 0: 20 µA (1/1)
When ATUNE1 is 1: 160 µA (1/8) current measurement mode
The ATUNE2 bit sets the current mirror ratio of the measurement power-supply current to the current control oscillator input current.
MD1
Measurement Mode Select 1
0
Self-capacitance method (single measurement)
When CHTRCx is set to 1 (transmission), the transmit pin outputs the first (same phase) pulse.
When multiple bits are set to 1, scan is performed.
When CHTRCx is set to all 0, measurement is performed without transmission.
1
Mutual capacitance method (double-measurement requiring CHTRCx setting)
When CHTRCx is set to all 0, scan fails without measurement.
The MD1 bit selects single measurement (assuming self-capacitance method) or double-measurement (assuming mutual capacitance method).
MD0
Measurement Mode Select 0
0
Single scan mode
1
Multi-scan mode
The MD0 bit selects single scan mode or multi-scan mode.
CLK[1:0]
Peripheral Operating Clock Select
0
0
fCLK
0
1
fCLK/2
1
0
fCLK/4
1
1
fCLK/8
The CLK[1:0] bits are used to divide the CPU/peripheral hardware clock (fCLK) using the prescaler.
ATUNE1
Analog Adjustment 1
0
80 µA (1/4)
1
40 µA (1/2)
The ATUNE1 bit sets the current mirror ratio of the measurement power-supply current to the current control
oscillator input current.
ATUNE0
Analog Adjustment 0
0
Measurement power-supply voltage = 1.5 V
This setting cannot be used if Vcc is less than 2.4 V.
1
Measurement power-supply voltage = 1.2 V
This bit is used to change voltage to suit the system's power supply specifications.
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<R>
CSW
Measurement Power Capacitor Connection
0
Turns off the external capacitance connection switch.
1
Turns on the external capacitance connection switch.
This bit controls charging of the LPF capacitance connected to the TSCAP pin by turning the capacitance
switch on or off. After the capacitance switch is turned on, wait for the specified time until the capacitance
connected to the TSCAP pin is charged, and then set STRT to 1 to start measurement. Before starting
measurement, use the I/O port to output a low level to the TSCAP pin, and discharge the LPF capacitance.
Set the CSW bit to 1 before setting the PON bit to 1.
When VCC < 4.5 V, set the PUMPON bit to 1 and then set the CSW bit to 1.
PON
Measurement Power On
0
Power off
1
Power on
The PON bit turns on the VDC for measurement to supply the power (1.5 V) for measurement.
When CSW is 0, do not set this bit to 1.
TXVSEL 0 1
VCC (I/O port) VDD (VCL)
Transmission Power Supply Select
TXVSEL2
Transmission Power Supply Select 2
0
Follows the TXVSEL setting.
1
VCC (dedicated)
PUMPON
Boost Circuit Control
0
Boost power off VCCX3 = VCC
1
Boost power on VCCX3 4.5 V
The PUMPON bit controls the boost power voltage (VCCX3).
When VCC is 4.5 V or lower, the boost power is required.
INIT
Control Block Initialization
0
--
1
Initializes the internal control registers.
To forcibly terminate operation, be sure to set the STRT bit to 0 and the INIT bit to 1 simultaneously. In this
case, operation stops and the internal control registers are initialized.
Do not set the STRT bit to 1 (CTSU operation start) and the INIT bit to 1 simultaneously.
The TXVSEL2 bit is read as 0.
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SNZ
SNOOZE Enable
0
Disables the SNOOZE function.
1
Enables the SNOOZE function.
The SNZ bit enables or disables the SNOOZE function when an external trigger is selected (CAP = 1).
Setting this bit to 1 drives the CTSU hardware macro into the suspended state to enable low-power
operation in the standby state.
<CTSU hardware macro state control>
PON 0 1 1 1 1 1
SNZ 0 0 1 1 1 1
CAP 0 -- 1 1 1 0
Other than above
STRT 0 -- 0 1 1 0
External trigger Hardware macro(VDC) state
--
Stopped
--
Operating
--
Suspended
None (waiting) Suspended
Provided (active) Operating
--
Software suspended
Setting prohibited
The SNZ bit enables SNOOZE operation. In the external trigger waiting state enabled by setting the STRT bit to 1, the CPU can enter STOP mode. When a falling edge of the external trigger is detected during STOP mode, the CTSU sends a clock request to the clock generating block and enters the SNOOZE state to start measurement. After the measurement end interrupt, clear this bit to 0 by software. The software suspended state in this table is used when the software of a system without SNOOZE function suspends the CTSU hardware macro to enable low-power operation. In this case, set the SNZ bit to 0 after the CPU returns to the previous state by an external interrupt, and then set the STRT bit to 1 to start measurement upon a software trigger.
CAP
Measurement Start Trigger Select
0
Software trigger
1
External trigger
The CAP bit specifies the measurement start condition.
For details, see the STRT bit explanation.
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STRT
Measurement Operation Start
0
Measurement stopped
1
Measurement operating
The STRT bit specifies whether to start or stop CTSU operation.
When CAP is 0, writing 1 to the STRT bit starts measurement. At the end of measurement, this bit is cleared
to 0 by hardware.
When CAP is 1, writing 1 to this bit drives the CTSU into the external trigger waiting state. Measurement
starts at the falling edge of the external trigger. After the measurement is complete, the CTSU waits for the
next external trigger and continues operation.
The following table shows the CTSU states.
<CTSU state>
STRT 0 0 1 1
CAP 0 1 0 1
CTSU state Stopped Stopped Measurement in progress Measurement in progress or waiting for an external triggerNote
Note The state can be read from the CTSUSR.STC[2:0] bits. Measurement in progress: CTSUSRL.STC[2:0] 000B
While waiting for an external trigger: CTSUSRL.STC[2:0] = 000B
If 1 is written to the STRT bit by software when the STRT bit is already set to 1, this writing is ignored and operation continues. To forcibly terminate operation by software when the STRT bit is set to 1, be sure to set the STRT bit to 0 and the INIT bit to 1 simultaneously.
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30.2.4 CTSU control registers BL and BH (CTSUCRBL, CTSUCRBH)
The CTSUCRBL register can be accessed in 8-bit units (CTSUSST as upper part and CTSUSDPRS as lower part). The CTSUCRBH register can be accessed in 8-bit units (CTSUDCLKC as upper part).
Figure 30 - 8 Format of CTSU Control Registers BL and BH (CTSUCRBL, CTSUCRBH)
Address: After reset: R/W:
F0504H, F0506H 0000H R/W
Symbol
15
14
13
12
11
10
9
8
CTSUCRBH
0
0
SSCNT[1:0]
0
SSMOD[2:0]
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Symbol
15
14
13
12
11
10
9
8
CTSUCRBL
SST[7:0]
7
6
5
4
3
2
1
0
PROFF
SOFF
PRMODE[1:0]
PRRATIO[3:0]
SSCNT[1:0]
SUCLK Diffusion Control
0
0
SSADJ + 0
0
1
SSADJ + 1
1
0
SSADJ + 2
1
1
SSADJ + 3
The SSCNT[1:0] bits adjust the diffusion clock frequency. When these bits are set to 11B, the CTSU compatible setting is employed.
SSMOD[2:0]
SUCLK Diffusion Mode Select
0
0
0
256 cycles
0
0
1
384 cycles
0
1
0
512 cycles
0
1
1
1024 cycles
1
1
1
No diffusion
Other than above
Setting prohibited
The SUCLK clock is used for the SSCG modulation of the CTSU. The SUCLK frequency need not be guaranteed. The SSMOD[2:0] and SSCNT[1:0] bits are used to determine the FM modulation frequency. The SSMOD[2:0] bits set the FM modulation cycle.
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<R>
SST[7:0]
Sensor Stabilization Wait Time Control
The SST[7:0] bits set the period from the start of sensor drive pulse supply until the TSCAP pin voltage
becomes stable.
<When CTSUCRAH.SDPSEL = 0>
The table below shows the stabilization time in units of base sensor drive pulse cycles.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
:
:
:
:
:
:
:
:
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
2 cycles 4 cycles 6 cycles 8 cycles
: 510 cycles 512 cycles
<When CTSUCRAH.SDPSEL = 1> The table below shows the stabilization time in units of STCLK cycles.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
:
:
:
:
:
:
:
:
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1 cycle 2 cycles 3 cycles 4 cycles
: 255 cycles 256 cycles
The TSCAP pin voltage is stabilized by supplying sensor drive pulses. The SST[7:0] value is related to the
number of cycles as shown below.
· When CTSUCRAH.SDPSEL = 0
The stabilization wait time is specified by the number of cycles of the base sensor drive pulse. Number of cycles = 2 × (value of these bits + 1) Set the stabilization wait time within the following range. Number of cycles set by CTSUCRBL.SST[7:0] (CTSUCRBL.PRRATIO[3:0] + 1)
· When CTSUCRAH.SDPSEL = 1
The stabilization wait time is specified by the number of STCLK cycles. Number of cycles = 1 × (value of these bits + 1)
PROFF
Pseudo-Random Number Disable Control
0
Pseudo-random number control is enabled.
1
Pseudo-random number control is disabled.
The PROFF bit disables the pseudo-random number control.
A value of 1 or 0 is output per cycle to generate pseudo-random numbers (1-bit random number generation).
When PROFF is 1, one cycle is added to the cycles specified by the PRMODE bits.
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SOFF
Jitter Disable Control
0
Applies jitter.
1
Does not apply jitter.
The SOFF bit sets whether to apply jitter to the sensor drive pulse to prevent synchronous noise. The output of the sensor drive pulse is selected from the base sensor drive pulse or the jittered sensor drive pulse.
PRMODE[1:0]
0
0
0
1
1
0
1
1
Pseudo-Random Number Generation Cycle 255 cycles (When PROFF = 1: 256 cycles) 63 cycles (When PROFF = 1: 64 cycles) 31 cycles (When PROFF = 1: 32 cycles) 3 cycles (When PROFF = 1: 4 cycles)
PRRATIO[3:0]
Phase Shift Frequency
The PRRATIO[3:0] bits specify the phase shift frequency of the base clock using a pseudo-random number.
These bits become a factor to determine the measurement period.
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30.2.5 CTSU measurement channel registers L and H (CTSUMCHL, CTSUMCHH)
The CTSUMCHL register can be accessed in 8-bit units (CTSUMCH1 as upper part and CTSUMCH0 as lower part). The CTSUMCHH register can be accessed in 8-bit units (CTSUMFAF as lower part).
Figure 30 - 9 Format of CTSU Measurement Channel Registers L and H (CTSUMCHL, CTSUMCHH)
Address: After reset: R/W:
F0508H, F050AH 0000H, 3F3FH R/W
Symbol
15
14
13
12
11
10
9
8
CTSUMCHH
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
MCA3
MCA2
MCA1
MCA0
Symbol
15
14
13
12
11
10
9
8
CTSUMCHL
0
0
MCH1[5:0]
7
6
5
4
3
2
1
0
0
0
MCH0[5:0]
MCAx
Multi-clock x Enable
0
Disabled
1
Enabled
The MCAx bit sets valid clock for measurement using SUCLK with two or more frequencies. For measurement using three clocks, set three bits out of the four bits (MCA3 to MCA0) to 1.
When making measurement using SUCLK with two or more frequencies, this bit enables or disables the target clock. When measurement starts with two or more MCAx bits enabled, valid channels are scanned in ascending order from MCA0. After a pin has been measured, if the next valid clock is present, the same pin is measured. If there is no valid clock, measurement shifts to the next pin. The SUCLK frequency is set by the CTSUSUCLK0, CTSUSUCLK1, CTSUSUCLK2, and CTSUSUCLK3 registers. The following shows the relationship between the MCAx bits and the CTSUSUCLK0 to CTSUSUCLK3 registers. · MCA0: Enables SUCLK set by the CTSUSUCLK0.SUMULTI0[7:0] and CTSUSUCLK0.SUADJ0[7:0] bits · MCA1: Enables SUCLK set by the CTSUSUCLK1.SUMULTI1[7:0] and CTSUSUCLK1.SUADJ1[7:0] bits · MCA2: Enables SUCLK set by the CTSUSUCLK2.SUMULTI2[7:0] and CTSUSUCLK2.SUADJ2[7:0] bits · MCA3: Enables SUCLK set by the CTSUSUCLK3.SUMULTI3[7:0] and CTSUSUCLK3.SUADJ3[7:0] bits
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<R>
MCH1[5:0]
Measurement Channel 1
· In single scan mode (CTSUCRAL.MD0 = 0), the MCH1[5:0] bits set the transmit channel to be measured. Do not set channels that are not to be measured using the CTSUCHACAH, CTSUCHACAL, CTSUCHACBH, or CTSUCHACBL register. If such channels are set, measurement is completed immediately after it starts.
· In multi-scan mode (CTSUCRAL.MD0 = 1), the MCH0[5:0] bits indicate the value of the transmit channel that is being measured, and writing to these bits has no effect (cleared at the beginning of measurement).
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
:
:
:
:
:
:
1
1
1
1
1
0
1
1
1
1
1
1
TS0 TS1 TS2 TS3
: TS62 TS63
Do not modify these bits during measurement (CTSUCRAL.STRT = 1). Otherwise, operation is not guaranteed. When measurement is stopped, these bits become 111111B.
MCH0[5:0]
Measurement Channel 0
· In single scan mode (CTSUCRAL.MD0 = 0), the MCH0[5:0] bits set the receive channel to be measured. Do not set channels that are not to be measured using the CTSUCHACAH, CTSUCHACAL, CTSUCHACBH, or CTSUCHACBL register. If such channels are set, measurement is completed immediately after it starts.
· In multi-scan mode (CTSUCRAL.MD0 = 1), the MCH1[5:0] bits indicate the value of the receive channel that is being measured, and writing to these bits has no effect (cleared at the beginning of measurement).
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
:
:
:
:
:
:
1
1
1
1
1
0
1
1
1
1
1
1
TS0 TS1 TS2 TS3
: TS62 TS63
Do not modify these bits during measurement (CTSUCRAL.STRT = 1). Otherwise, operation is not guaranteed. When measurement is stopped, these bits become 111111B.
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30.2.6
CTSU channel enable control registers AL, AH, BL, and BH (CTSUCHACAL, CTSUCHACAH, CTSUCHACBL, CTSUCHACBH)
The CTSUCHACAL register can be accessed in 8-bit units (CTSUCHAC1 as upper part and CTSUCHAC0 as lower part). The CTSUCHACAH register can be accessed in 8-bit units (CTSUCHAC3 as upper part and CTSUCHAC2 as lower part). The CTSUCHACBL register can be accessed in 8-bit units (CTSUCHAC5 as upper part and CTSUCHAC4 as lower part). The CTSUCHACBH register can be accessed in 8-bit units (CTSUCHAC7 as upper part and CTSUCHAC6 as lower part).
Figure 30 - 10 Format of CTSU Channel Enable Control Registers AL, AH, BL, and BH (CTSUCHACAL, CTSUCHACAH, CTSUCHACBL, CTSUCHACBH)
Address: After reset: R/W:
F050CH, F050EH, F0510H, F0512H 0000H, 0000H, 0000H, 0000H R/W
Symbol
CTSUCHACAH
15 CHAC31
14 CHAC30
13 CHAC29
12 CHAC28
11 CHAC27
10 CHAC26
9 CHAC25
8 CHAC24
7 CHAC23
6 CHAC22
5 CHAC21
4 CHAC20
3 CHAC19
2 CHAC18
1 CHAC17
0 CHAC16
Symbol
CTSUCHACAL
15 CHAC15
14 CHAC14
13 CHAC13
12 CHAC12
11 CHAC11
10 CHAC10
9 CHAC09
8 CHAC08
7 CHAC07
6 CHAC06
5 CHAC05
4 CHAC04
3 CHAC03
2 CHAC02
1 CHAC01
0 CHAC00
Symbol
CTSUCHACBH
15 CHAC63
14 CHAC62
13 CHAC61
12 CHAC60
11 CHAC59
10 CHAC58
9 CHAC57
8 CHAC56
7 CHAC55
6 CHAC54
5 CHAC53
4 CHAC52
3 CHAC51
2 CHAC50
1 CHAC49
0 CHAC48
Symbol
CTSUCHACBL
15 CHAC47
14 CHAC46
13 CHAC45
12 CHAC44
11 CHAC43
10 CHAC42
9 CHAC41
8 CHAC40
7 CHAC39
6 CHAC38
5 CHAC37
4 CHAC36
3 CHAC35
2 CHAC34
1 CHAC33
0 CHAC32
CHACx
Channel Enable Control
0
Do not measure pins.
1
Measure pins.
The CHACx bits set whether TSm pin measurement is required.
Caution 1. Caution 2.
CHAC63 to CHAC0 are used for setting measurement of TS63 to TS0 pins. Write 0 to unassigned bits. These bits are read as 0. Set the CHACx bits to 1 for transmit and receive pins whose electrostatic capacitance is to be measured.
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Caution 3. Set the CTSUCHACAH, CTCSUCHACAL, CTSUCHACBH, and CTSUCHACBL registers when CTSUCRAL.STRT is 0.
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30.2.7
CTSU channel transmit/receive control registers AL, AH, BL, and BH (CTSUCHTRCAL, CTSUCHTRCAH, CTSUCHTRCBL, CTSUCHTRCBH)
The CTSUCHTRCAL register can be accessed in 8-bit units (CTSUCHTRC1 as upper part and CTSUCHTRC0 as lower part). The CTSUCHTRCAH register can be accessed in 8-bit units (CTSUCHTRC3 as upper part and CTSUCHTRC2 as lower part). The CTSUCHTRCBL register can be accessed in 8-bit units (CTSUCHTRC5 as upper part and CTSUCHTRC4 as lower part). The CTSUCHTRCBH register can be accessed in 8-bit units (CTSUCHTRC7 as upper part and CTSUCHTRC6 as lower part).
Figure 30 - 11 Format of CTSU Channel Transmit/Receive Control Registers AL, AH, BL, and BH (CTSUCHTRCAL, CTSUCHTRCAH, CTSUCHTRCBL, CTSUCHTRCBH)
Address: After reset: R/W:
F0514H, F0516H, F0518H, F051AH 0000H, 0000H, 0000H, 0000H R/W
Symbol
15
14
13
12
11
10
9
8
CTSUCHTRCAH CHTRC31 CHTRC30 CHTRC29 CHTRC28 CHTRC27 CHTRC26 CHTRC25 CHTRC24
7
6
5
4
3
2
1
0
CHTRC23 CHTRC22 CHTRC21 CHTRC20 CHTRC19 CHTRC18 CHTRC17 CHTRC16
Symbol
15
14
13
12
11
10
9
8
CTSUCHTRCAL CHTRC15 CHTRC14 CHTRC13 CHTRC12 CHTRC11 CHTRC10 CHTRC09 CHTRC08
7
6
5
4
3
2
1
0
CHTRC07 CHTRC06 CHTRC05 CHTRC04 CHTRC03 CHTRC02 CHTRC01 CHTRC00
Symbol
15
14
13
12
11
10
9
8
CTSUCHTRCBH CHTRC63 CHTRC62 CHTRC61 CHTRC60 CHTRC59 CHTRC58 CHTRC57 CHTRC56
7
6
5
4
3
2
1
0
CHTRC55 CHTRC54 CHTRC53 CHTRC52 CHTRC51 CHTRC50 CHTRC49 CHTRC48
Symbol
15
14
13
12
11
10
9
8
CTSUCHTRCBL CHTRC47 CHTRC46 CHTRC45 CHTRC44 CHTRC43 CHTRC42 CHTRC41 CHTRC40
7
6
5
4
3
2
1
0
CHTRC39 CHTRC38 CHTRC37 CHTRC36 CHTRC35 CHTRC34 CHTRC33 CHTRC32
CHTRCx
Channel Transmit/Receive Control
0
Reception
1
Transmission
The CHTRCx bits assign the TSm pins to reception or transmission.
Caution 1. CHTRC63 to CHTRC0 are used for setting transmit/receive control of TS63 to TS0 pins. Write 0 to unassigned bits. These bits are read as 0.
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<R>
Caution 2. The CHTRCx bits assign the TSm pins to reception or transmission. When MD1 is set to 0, if one of these bits is set to 1 (transmission), the corresponding pin can be used for shield signal output. However, when setting as a shield output, do not set two or more bits to 1.
Caution 3. Set the CHTRCx bits to 1 for transmit and receive pins whose electrostatic capacitance is to be measured.
Caution 4. Set the CTSUCHTRCAH, CTSUCHTRCAL, CTSUCHTRCBH, and CTSUCHTRCBL registers when CTSUCRAL.STRT is 0.
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30.2.8 CTSU status register L (CTSUSRL)
The CTSUSRL register can be accessed in 8-bit units (CTSUST as upper part and CTSUST1 as lower part).
Figure 30 - 12 Format of CTSU Status Register L (CTSUSRL)
Address: After reset: R/W:
F051CH 0000H R/W
Symbol
15
14
13
12
11
CTSUSRL
PS
SUCKOVF SENSOVF DTSR
0
10
9
8
STC[2:0]
7
6
5
4
3
2
1
0
ICOMP0 ICOMP1 ICOMPRST
0
0
0
MFC[1:0]
PS
Mutual Capacitance Measurement Status
0
First measurement
1
Second measurement
The PS bit indicates the measurement status in double-measurement (CTSUCRAL.MD1 = 1).
<R>
This bit indicates whether the measurement is the first or second of double-measurement per channel. This bit is 0 when measurement is stopped or during single measurement (CTSUCRAL.MD1 = 0).
SUCKOVF
SUCLK Counter Overflow
0
No overflow occurred.
1
An overflow occurred.
The SUCKOVF bit indicates whether the SUCLK counter has overflowed. When an overflow occurs, the result of measurement is read from the CTSUUC.UC[15:0] bits as FFFFH. Even if an overflow occurs, measurement processing continues for the set period. Occurrence of an overflow generates no interrupt. Therefore, read the measurement result of each channel after measurement is complete (after a measurement end interrupt is generated) to check an overflowed channel.
This bit is cleared when 0 is written after 1 is read by software. This bit is also cleared by the CTSUCRAL.INIT bit.
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<R>
<R> <R>
SENSOVF
0
No overflow occurred.
1
An overflow occurred.
Sensor Counter Overflow
The SENSOVF bit indicates whether the sensor counter has overflowed. When an overflow occurs, the
result of measurement is read from the CTSUSC.SC[15:0] bits as FFFFH.
Even if an overflow occurs, measurement processing continues for the set period.
Occurrence of an overflow generates no interrupt. Therefore, read the measurement result of each channel
after measurement is complete (after a measurement end interrupt is generated) to check an overflowed
channel.
This bit is cleared when 0 is written after 1 is read by software. This bit is also cleared by the CTSUCRAL.INIT bit.
DTSR
Data Transfer Status
0
The measurement result has been read.
1
The measurement result has not been read.
The DTSR bit indicates whether the measurement result stored in the sensor counter has been read. This
bit is set to 1 on completion of measurement and is cleared to 0 when the CTSUSC register is read by
software or the DTC.
This bit is also cleared by the CTSUCRAL.INIT bit.
STC[2:0]
Measurement Status Counter
0
0
0
Status 0
0
0
1
Status 1
0
1
0
Status 2
0
1
1
Status 3
1
0
0
Status 4
1
0
1
Status 5
The STC[2:0] bits indicate the current measurement status.
ICOMP0
Reference Resistance Comparison Result
0
Normal
1
Abnormal TSCAP voltage
TSCAP voltage error flag
This bit is cleared to 0 when CTSUCRAL.PON is set to 0 or 1 is written to ICOMPRST.
When the TSCAP voltage becomes abnormal, the sensor counters at that time are all cleared to 0.
ICOMP1
Current Error
0
Normal
1
Abnormal current
Current error flag
This bit is cleared to 0 when CTSUCRAL.PON is set to 0 or 1 is written to ICOMPRST.
ICOMPRST
ICOMP0 and ICOMP1 Reset
Writing 1 to this bit resets the ICOMP1 and ICOMP0 flags.
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MFC[1:0]
Multi-clock Counter
0
0
Multi-clock 0
0
1
Multi-clock 1
1
0
Multi-clock 2
1
1
Multi-clock 3
The MFC[1:0] bits indicate the clock that is being measured during multi-clock measurement
(CTSUCRAH.FCMODE = 1).
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30.2.9 CTSU sensor offset registers 0 and 1 (CTSUSO0, CTSUSO1)
Figure 30 - 13 Format of CTSU Sensor Offset Registers 0 and 1 (CTSUSO0, CTSUSO1)
Address: After reset: R/W:
F0520H, F0522H 0000H, 0000H R/W
Symbol
15
14
13
12
11
10
9
8
CTSUSO1
SDPA[7:0]
7
6
5
4
3
2
SSDIV[3:0]
0
0
Symbol
15
14
13
12
11
10
CTSUSO0
SNUM[5:0]
1
0
SNUM[7:6]
9
8
SO[9:8]
<R>
7
6
5
4
3
2
1
0
SO[7:0]
SDPA[7:0]
Sensor Driving Pulse Divisor Setting
· When CTSUCRAH.SDPSEL = 0
The operating clock is divided to generate a base clock to be the source of sensor drive pulse. These bits are also available for setting the voltage stabilization time of the CTSU hardware macro.
0
0
0
0
0
0
0
0 Operating clock divided by 2Note
0
0
0
0
0
0
0
1 Operating clock divided by 4
0
0
0
0
0
0
1
0 Operating clock divided by 6
0
0
0
0
0
0
1
1 Operating clock divided by 8
:
:
:
:
:
:
:
:
:
1
1
1
1
1
1
1
0 Operating clock divided by 510
1
1
1
1
1
1
1
1 Operating clock divided by 512
· When CTSUCRAH.SDPSEL = 1 The SUCLK clock is divided to generate a sensor drive pulse.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
:
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0 SUCLK divided by 1
1 SUCLK divided by 2
0 SUCLK divided by 3
1 SUCLK divided by 4
:
:
0 SUCLK divided by 255
1 SUCLK divided by 256
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SSDIV[3:0]
Spectrum Diffusion Sampling Cycle Control
The SSDIV[3:0] bits are valid only when CTSUCRAH.SDPSEL is 0. Sampling cycle (divided by 1 to 16) can be set for the jitter application function.
0
0
0
0
Divided by 1
0
0
0
1
Divided by 2
:
:
:
:
:
1
1
1
0
Divided by 15
1
1
1
1
Divided by 16
The SSDIV[3:0] bits set the sampling cycle of the jitter application function. Set the sampling cycle to less than 1/4 of the sensor drive pulse cycle. Set these bits for the pin to be measured after an INTWR_N interrupt is generated.
SNUM[7:0]
Measurement Count Setting
· When CTSUCRAH.SDPSEL = 0
The measurement count is set. The SNUM[7:0] bits specify how many times the base unit determined by the CTSUCRBL.PRRATIO[3:0] and CTSUCRBL.PRMODE[1:0] bits is repeated during the measurement period. Measurement count = (SNUM[5:0] + 1) × 2 Set the SNUM[7: 6] bits to 00B.
· When CCTSUCRAH.SDPSEL = 1
The measurement time is set. Measurement time = (STCLK cycles × 8) × (value of SNUM[7:0] bits + 1)
Set these bits for the pin to be measured after an INTWR_N interrupt is generated.
SO[9:0]
Sensor Offset Adjustment
The SO[9:0] bits adjust the input current offset of the sensor ICO.
* The adjustment value varies with the CTSUCRAL.ATUNE[0] value.
Set these bits for the pin to be measured after an INTWR_N interrupt is generated.
Note
When jitter application is disabled (CTSUCRB.SOFF bit = 1) in the mutual capacitance method, setting of
SDPA[7:0] = 00000000B is prohibited.
After an INTWR_N interrupt is generated, write to the CTSUSO register, which causes a transition to Status 3. Therefore, when writing a value to the CTSUSO register, set all bits at a time.
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CHAPTER 30 CAPACITIVE SENSING UNIT (CTSU2L)
30.2.10 CTSU sensor counter registers L and H (CTSUSC, CTSUUC)
Figure 30 - 14 Format of CTSU Sensor Counter Registers L and H (CTSUSC, CTSUUC)
Address: After reset: R/W:
F0524H, F0526H 0000H, 0000H R
Symbol
15
14
13
12
11
10
9
8
CTSUUC
UC[15:8]
7
6
5
4
3
2
1
0
UC[7:0]
Symbol
15
14
13
12
11
10
9
8
CTSUSC
SC[15:8]
7
6
5
4
3
2
1
0
SC[7:0]
UC[15:0]
This register shows the count value of the clock (SUCLK × 2).
When an overflow occurs, this counter shows FFFFH.
SUCLK Counter
SC[15:0] This register shows the measurement result of the sensor counter. When an overflow occurs, this counter shows FFFFH.
Sensor Counter
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30.2.11 CTSU calibration registers L and H (CTSUDBGR0, CTSUDBGR1)
Figure 30 - 15 Format of CTSU Calibration Registers L and H (CTSUDBGR0, CTSUDBGR1)
Address: After reset: R/W:
F0528H, F052AH 0000H, 0000H R/W
Symbol CTSUDBGR1
15 TXREV
14
13
CCOCALIB CCOCLK
12
11
10
9
8
DACCLK SUCARRY SUMSEL DACCARRY DACMSEL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Symbol
15
14
13
12
11
10
9
8
CTSUDBGR0
0
0
0
0
DCOFF
0
IOC CNTRDSEL
7 TSOC
6 SUCLKEN
5
4
CLKSEL0[1:0]
3 DRV
2 TSOD
TXREV
Transmit Pin Inverted Output
0
The pulse output from the transmit pin is not inverted.
1
The pulse output from the transmit pin is inverted.
<Single measurement (CTSUCRAL.MD1 = 0)> 0: Same phase of receive pin 1: Reverse phase of receive pin <Double-measurement (CTSUCRAL.MD1 = 1)> 0: First: Same phase of receive pin; Second: Reverse phase of receive pin 1: First: Reverse phase of receive pin; Second: Same phase of receive pin
1
0
TEST[1:0]
Set this bit to 0 for normal measurement (setting to 1 is assumed for debugging).
CCOCALIB
CCO Calibration Mode Select
MODE circuit state 0: Normal mode LDO current SENS oscillator SSCNT current SSCG oscillator 1: Oscillator calibration mode SSCNT current SENS oscillator LDO current SSCG oscillator The oscillator calibration mode is used when the external current is compared with the current DAC to correct the oscillator characteristics by software.
CCOCLK
CCO Modulation Circuit Clock Select
0
The clock specified by the CTSUCRAL.CLK[1:0] bits
1
SUCLK
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<R> <R>
DACCLK
DAC Modulation Circuit Clock Select
0
The clock specified by the CTSUCRAL.CLK[1:0] bits
1
SUCLK
SUCARRY
CCO Carry Input (Usually Fixed to the Low Level)
0
A value of 32 is added to the input data.
SUMSEL
Current Oscillator Input Current Matrix Test
0
Normal operation
1
Current oscillator input current test mode
This bit controls the input current for the current oscillator.
DACCARRY
DAC Upper Current Source Carry Input (Usually Fixed to the Low Level)
0
A value of 64 is added to the input data.
DACMSEL
Current Offset DAC Current Matrix Test
0
Normal operation
1
Current offset DAC current test mode
This bit controls the current for the current offset DAC.
DCOFF
Down-Conversion Disable
0
Normal operation mode
1
Down-conversion disabled
The DCOFF bit disables conversion of the VDDSENS voltage (disables the Pch driver). The amplifier circuit of the converter operates as a comparator.
IOC
Transmit Pin Control
The IOC bit selects the output level from the TS pin when the CTSUDBGR1.TSOD bit or the CTSUCRAL.DCMODE bit is set to 1. <When CTSUDBGR1.TSOD = 1> 0: Low level is output from the TS pin. 1: High level is output from the TS pin. <When CTSUCRAL.DCMODE = 1> 0: High level is output from the TS pin. 1: Low level is output from the TS pin. When the CTSUDBGR1.TSOD and CTSUCRAL.DCMODE bits are 0, this bit is ignored.
CNTRDSEL
Sensor Counter Register Read Count Select
0
Transitions to the next state after single reading.
1
Transitions to the next state after reading twice.
TSOC
Calibration Setting 2
0
Electrostatic capacitance measurement mode
1
Calibration setting 2
The TSOC bit is used to set calibration of the CTSU. When measuring electrostatic capacitance, set this bit to 0.
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<R>
SUCLKEN
0
SUCLK is disabled.
1
SUCLK is enabled.
SUCLK Enable
CLKSEL0[1:0]
Observation Clock Select 0
0
0
Low level is always output.
0
1
Sensor ICO clock (divided by 8)
1
0
Setting prohibited
1
1
SUCLK (divided by 8)
The CLKSEL0[1:0] bits select the clock to be observed from the three clocks that the CTSU hardware macro outputs.
DRV
Calibration Setting 1
0
Electrostatic capacitance measurement mode
1
Calibration setting 1
The DRV bit is used to set calibration of the CTSU. When measuring electrostatic capacitance, set this bit to 0.
TSOD
TS Pin Fixed Output
0
Electrostatic capacitance measurement mode
1
TS pin fixed output (high- or low-level output)
The TSOD bit is used for calibration of the CTSU. When this bit is set to 1, the level specified by the CTSUDBGR0.IOC bit is output from the TS pin.
TEST[1:0]
Test Mode
0
0
Normal operation mode
0
1
Setting prohibited
1
0
Setting prohibited. Burn-in mode 1 (STRESS)
1
1
Setting prohibited
The TEST[1:0] bits control operating mode of the CTSU hardware macro.
· Burn-in mode 1 (STRESS) This mode is used to increase the reference voltage to stress the VDD system.
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CHAPTER 30 CAPACITIVE SENSING UNIT (CTSU2L)
30.2.12 CTSU sensor unit clock control registers AL, AH, BL, and BH (CTSUSUCLK0, CTSUSUCLK1, CTSUSUCLK2, CTSUSUCLK3)
Figure 30 - 16 Format of CTSU Sensor Unit Clock Control Registers AL, AH, BL, and BH (CTSUSUCLK0, CTSUSUCLK1, CTSUSUCLK2, CTSUSUCLK3)
Address: After reset: R/W:
F052CH, F052EH, F0530H, F0532H 0000H, 0000H, 0000H, 0000H R/W
Symbol
15
14
13
12
11
10
9
8
CTSUSUCLK1
SUMULTI1[7:0]
7
6
5
4
3
2
1
0
SUADJ1[7:0]
Symbol
15
14
13
12
11
10
9
8
CTSUSUCLK0
SUMULTI0[7:0]
7
6
5
4
3
2
1
0
SUADJ0[7:0]
Symbol
15
14
13
12
11
10
9
8
CTSUSUCLK3
SUMULTI3[7:0]
7
6
5
4
3
2
1
0
SUADJ3[7:0]
Symbol
15
14
13
12
11
10
9
8
CTSUSUCLK2
SUMULTI2[7:0]
7
6
5
4
3
2
1
0
SUADJ2[7:0]
SUMULTIx[7:0]
SUCLK Multiplication Rate Setting
The SUMULTIx[7:0] bits set the multiplication rate of STCLK (assuming 0.5 MHz (divided fCLK)) to generate SUCLK. STCLK is compared with SUCLK divided by this setting. Based on the comparison result, SUADJn is updated. The target clock frequency is 32 MHz to 80 MHz.
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
0
0
1
1
1
1
1
1
:
:
:
:
:
:
:
:
0
1
1
1
1
1
1
1
:
:
:
:
:
:
:
:
1
1
1
1
1
1
1
1
×1 :
× 64 :
× 128 :
× 256
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SUADJx[7:0]
SUCLK Frequency Adjustment
The SUADJx[7:0] bits set the initial value of the SUCLK frequency. The drift is adjusted and the SUADJx[7:0] value is updated by the clock recovery function. The output frequency varies from the set value in each MCU. The SUCLK frequency is adjusted based on the register set value as an initial value and the register value is updated by the clock recovery control.
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RL78/G23
CHAPTER 30 CAPACITIVE SENSING UNIT (CTSU2L)
30.2.13 CTSU trimming registers AL and AH (CTSUTRIM0, CTSUTRIM1)
The CTSUTRIM0 register can be accessed in 8-bit units (DACTRIM as upper part and RTRIM as lower part). The CTSUTRIM1 register can be accessed in 8-bit units (TRESULT4 as upper part and SUADJD as lower part).
Figure 30 - 17 Format of CTSU Trimming Registers AL and AH (CTSUTRIM0, CTSUTRIM1)
Address: After reset: R/W:
F0600H, F0602H 0000H, 0000H R/W
Symbol
15
14
13
12
11
10
9
8
CTSUTRIM1
TRESULT4[7:0]
7
6
5
4
3
2
1
0
SUADJD[7:0]
Symbol
15
14
13
12
11
10
9
8
CTSUTRIM0
DACTRIM[7:0]
7
6
5
4
3
2
1
0
RTRIM[7:0]
TRESULT4[7:0]
Test Result 4
The TRESULT4[7:0] bits store the coefficient of variation for the 120-k reference load resistance. These bits are the initial value set at the factory. Do not modify these bits.
SUADJD[7:0]
SUCLK Frequency Adjustment
The SUADJD[7:0] bits hold the initial value for generating approx. 64 MHz, which is set at the factory. When FCMODE is 0, this set value is input to the digital oscillator. Do not modify this initial value set at the factory.
DACTRIM[7:0]
Offset Current DAC Upper/Lower Matching Variation Adjustment
The DACTRIM[7:0] bits adjust the upper/lower matching variation (coefficient of the lower current source) of the offset current DAC. These bits hold the initial value set at the factory. Do not modify this value.
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
0
1
1
0
0
0
0
0
:
:
:
:
:
:
:
:
1
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
1
0
0
1
0
0
0
0
:
:
:
:
:
:
:
:
1
0
1
0
0
0
1
1
Other than above: Setting prohibited
× 0.0 :
× 0.875 :
× 1.0 :
× 1.125 :
× 1.273
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RL78/G23
CHAPTER 30 CAPACITIVE SENSING UNIT (CTSU2L)
RTRIM[7:0]
Reference Resistance Adjustment
The RTRIM[7:0] bits adjust the reference resistance value. These bits hold the initial value set at the factory. Do not modify this value..
RTRIM[7:0]
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
1
1
1
1
1
1
1
1
Resistance value Low : High
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RL78/G23
CHAPTER 30 CAPACITIVE SENSING UNIT (CTSU2L)
30.2.14 CTSU trimming registers BL and BH (CTSUTRIM2, CTSUTRIM3)
The CTSUTRIM2 register can be accessed in 8-bit units (TRESULT1 as upper part and TRESULT0 as lower part). The CTSUTRIM3 register can be accessed in 8-bit units (TRESULT3 as upper part and TRESULT2 as lower part).
Figure 30 - 18 Format of CTSU Trimming Registers BL and BH (CTSUTRIM2, CTSUTRIM3)
Address: After reset: R/W:
F0604H, F0606H 0000H, 0000H R/W
Symbol
15
14
13
12
11
10
9
8
CTSUTRIM3
TRESULT3[7:0]
7
6
5
4
3
2
1
0
TRESULT2[7:0]
Symbol
15
14
13
12
11
10
9
8
CTSUTRIM2
TRESULT1[7:0]
7
6
5
4
3
2
1
0
TRESULT0[7:0]
TRESULT3[7:0]
Test Result 3
The TRESULT3[7:0] bits store the coefficient of variation for the 60-k reference load resistance. These bits are the initial value set at the factory. Do not modify these bits.
TRESULT2[7:0]
Test Result 2
The TRESULT2[7:0] bits store the coefficient of variation for the 30-k reference load resistance. These bits are the initial value set at the factory. Do not modify these bits.
TRESULT1[7:0]
Test Result 1
The TRESULT1[7:0] bits store the coefficient of variation for the 15-k reference load resistance.
These bits are the initial value set at the factory. Do not modify these bits.
TRESULT0[7:0]
Test Result 0
The TRESULT0[7:0] bits store the coefficient of variation for the 7.5-k reference load resistance. These bits are the initial value set at the factory. Do not modify these bits.
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RL78/G23
CHAPTER 31 REGULATOR
CHAPTER 31 REGULATOR
31.1 Overview
The RL78/G23 incorporates a circuit for constant voltage operation. To stabilize the output voltage from the regulator, connect the REGC pin to VSS via a capacitor (0.47 to 1 µF). Use a capacitor with good characteristics, since it is for stabilizing the internal voltage.
REGC
VS S
Caution The length of the wiring within the broken lines in the above figure should be as short as possible.
The regulator outputs a 1.5-V voltage.
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RL78/G23
CHAPTER 32 OPTION BYTES
CHAPTER 32 OPTION BYTES
32.1
Functions of Option Bytes
Addresses 000C0H to 000C3H of the flash memory of the RL78/G23 form an option byte area. Option bytes consist of user option bytes (000C0H to 000C2H) and on-chip debug option byte (000C3H). Upon power application or resetting and starting, an option byte is automatically referenced and a specified function is set. When using the product, be sure to set the following functions by using the option bytes. For the bits to which no function is allocated, do not change their initial values. To use the boot swap operation during self-programming, 000C0H to 000C3H are replaced by 040C0H to 040C3H. Therefore, set the same values as 000C0H to 000C3H to 040C0H to 040C3H.
Caution The option bytes should always be set regardless of whether each function is used.
32.1.1 User option bytes (000C0H to 000C2H or 040C0H to 040C2H)
(1) 000C0H or 040C0H · Setting of watchdog timer operation Enabling or disabling of counter operation Enabling or stopping of counter operation in the HALT or STOP mode · Setting of overflow time of watchdog timer · Setting of window open period of watchdog timer · Setting of interval interrupt of watchdog timer Interval interrupt is used or not used
Caution
When boot swapping is to be used, 000C0H is replaced with 040C0H. Therefore, set the same value as the setting in 000C0H in 040C0H.
(2) 000C1H or 040C1H · Setting of LVD0 operation mode Reset mode Interrupt mode LVD0 off (by controlling the externally input reset signal on the RESET pin) · Setting of LVD0 detection level (VLVD0)
Caution 1. After power is supplied, the reset state must be retained until the operating voltage becomes in the range defined in 37.4 AC Characteristics. This is done by utilizing the voltage detection circuit or controlling the externally input reset signal. After the power supply is turned off, this LSI should be placed in the STOP mode, or placed in the reset state by utilizing the voltage detection circuit or controlling the externally input reset signal, before the voltage falls below the operating range. The range of operating voltage varies with the setting of the user option byte (000C2H or 040C2H).
Caution 2. When boot swapping is to be used, 000C1H is replaced with 040C1H. Therefore, set the same value as the setting in 000C1H in 040C1H.
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RL78/G23
CHAPTER 32 OPTION BYTES
(3) 000C2H or 040C2H · Setting of flash operation mode Make the setting depending on the main system clock frequency (fMAIN) and power supply voltage (VDD) to be used. LS (low-speed main) mode HS (high-speed main) mode LP (low-power main) mode · Setting of the frequency of the high-speed on-chip oscillator Select from 1 MHz to 32 MHz.
Caution
When boot swapping is to be used, 000C2H is replaced with 040C2H. Therefore, set the same value as the setting in 000C2H in 040C2H.
32.1.2 On-chip debug option byte (000C3H or 040C3H)
· Control of on-chip debug operation On-chip debug operation is disabled or enabled.
· Handling of data of flash memory in case of failure in on-chip debug security ID authentication Data of flash memory is erased or not erased in case of failure in on-chip debug security ID authentication.
Caution
When boot swapping is to be used, 000C3H is replaced with 040C3H. Therefore, set the same value as the setting in 000C3H in 040C3H.
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CHAPTER 32 OPTION BYTES
32.2
Format of User Option Bytes
Figure 32 - 1 Format of User Option Byte (000C0H or 040C0H)
Address:
000C0H or 040C0HNote 1
Symbol
7
WDTINT
6
5
WINDOW1 WINDOW0
4 WDTON
3 WDCS2
2 WDCS1
1 WDCS0
0 WDSTBYON
WDTINT 0 1
Use of interval interrupt of watchdog timer Interval interrupt is not used. Interval interrupt is generated when 75% of the overflow time + 1/2 fIL is reached.
WINDOW1 0 0 1 1
WINDOW0
Watchdog timer window open periodNote 2
0
Setting prohibited
1
50%
0
Setting prohibited
1
100%
WDTON 0 1
Operation control of watchdog timer counter Counter operation disabled (counting stopped after reset) Counter operation enabled (counting started after reset)
WDCS2
0 0 0 0 1 1 1 1
WDCS1
0 0 1 1 0 0 1 1
WDCS0
0 1 0 1 0 1 0 1
Watchdog timer overflow time (fIL = 37.683 kHz (max.))
27/fIL (3.39 ms) 28/fIL (6.79 ms) 29/fIL (13.58 ms) 210/fIL (27.17 ms) 212/fIL (108.69 ms) 214/fIL (434.78 ms) 215/fIL (869.56 ms) 217/fIL (3478.26 ms)
WDSTBYON
Operation control of watchdog timer counter (HALT/STOP mode)
0
Counter operation stopped in HALT/STOP modeNote 2
1
Counter operation enabled in HALT/STOP mode
Note 1. Note 2.
When boot swapping is to be used, 000C0H is replaced with 040C0H. Therefore, set the same value as the setting in 000C0H in 040C0H. The window open period is 100% when WDSTBYON = 0, regardless of the value of the WINDOW1 and WINDOW0 bits.
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RL78/G23
CHAPTER 32 OPTION BYTES
Figure 32 - 2 Format of User Option Byte (000C1H or 040C1H) (1/3)
Address:
000C1H or 040C1HNote
Symbol
7
6
5
4
3
2
1
LVD0EN LVD0SEL
1
1
1
LVD0V2 LVD0V1
· LVD0 setting (reset mode)
Detection Voltage
Option Byte Setting Value
VLVD0 Rising edge Falling edge
LVD0EN
Mode setting LVD0SEL
LVD0V2
LVD0V1
1.69 V
1.65 V
1
1
1
1
1.90 V
1.86 V
1
1
2.38 V
2.33 V
1
0
2.67 V
2.62 V
1
0
2.97 V
2.91 V
0
1
3.96 V
3.88 V
0
1
--
Settings other than the above are prohibited.
0 LVD0V0
LVD0V0 1 0 1 0 1 0
Note
When boot swapping is to be used, 000C1H is replaced with 040C1H. Therefore, set the same value as the setting in 000C1H in 040C1H.
Caution Be sure to set bits 5 to 3 to 1.
Remark 1. For details on the LVD0 circuit, see CHAPTER 26 VOLTAGE DETECTOR (LVD). Remark 2. The detection voltage is a typical value. For details, see 37.6.6 LVD circuit characteristics.
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RL78/G23
CHAPTER 32 OPTION BYTES
Figure 32 - 3 Format of User Option Byte (000C1H or 040C1H) (2/3)
Address:
000C1H or 040C1HNote
Symbol
7
6
5
4
3
2
1
LVD0EN LVD0SEL
1
1
1
LVD0V2 LVD0V1
· LVD0 setting (interrupt mode)
Detection Voltage
Option Byte Setting Value
VLVD0 Rising edge Falling edge
LVD0EN
Mode setting LVD0SEL
LVD0V2
LVD0V1
1.69 V
1.65 V
1
0
1
1
1.90 V
1.86 V
1
1
2.38 V
2.33 V
1
0
2.67 V
2.62 V
1
0
2.97 V
2.91 V
0
1
3.96 V
3.88 V
0
1
--
Settings other than the above are prohibited.
0 LVD0V0
LVD0V0 1 0 1 0 1 0
Note
When boot swapping is to be used, 000C1H is replaced with 040C1H. Therefore, set the same value as the setting in 000C1H in 040C1H.
Caution Be sure to set bits 5 to 3 to 1.
Remark 1. For details on the LVD0 circuit, see CHAPTER 26 VOLTAGE DETECTOR (LVD). Remark 2. The detection voltage is a typical value. For details, see 37.6.6 LVD circuit characteristics.
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RL78/G23
CHAPTER 32 OPTION BYTES
Figure 32 - 4 Format of User Option Byte (000C1H or 040C1H) (3/3)
Address:
000C1H or 040C1HNote
Symbol
7
6
5
4
3
2
1
LVD0EN LVD0SEL
1
1
1
LVD0V2 LVD0V1
· LVD0 off setting (external reset input from the RESET pin is used)
Detection Voltage
Option Byte Setting Value
VLVD0 Rising edge Falling edge
LVD0EN
Mode setting LVD0SEL
LVD0V2
LVD0V1
--
--
0
×
×
×
--
Settings other than the above are prohibited.
0 LVD0V0
LVD0V0 ×
Note
When boot swapping is to be used, 000C1H is replaced with 040C1H. Therefore, set the same value as the setting in 000C1H in 040C1H.
Caution 1. Be sure to set bits 5 to 3 to 1. Caution 2. After power is supplied, the reset state must be retained until the operating voltage becomes in the
range defined in 37.4 AC Characteristics. This is done by utilizing the voltage detection circuit or controlling the externally input reset signal. After the power supply is turned off, this LSI should be placed in the STOP mode, or placed in the reset state by utilizing the voltage detection circuit or controlling the externally input reset signal, before the voltage falls below the operating range. The range of operating voltage varies with the setting of the user option byte (000C2H or 040C2H).
Remark 1. ×: Don't care. Remark 2. For details on the LVD0 circuit, see CHAPTER 26 VOLTAGE DETECTOR (LVD). Remark 3. The detection voltage is a typical value. For details, see 37.6.6 LVD circuit characteristics.
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RL78/G23
CHAPTER 32 OPTION BYTES
Figure 32 - 5 Format of User Option Byte (000C2H or 040C2H)
Address:
000C2H or 040C2HNote
Symbol
7
6
5
CMODE1 CMODE0
1
4
3
2
1
0
0
FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0
Value of the Option Byte (000C2H)
CMODE1 CMODE0
Flash Operation Mode
0
1
LP (low-power main)
mode
1
0
LS (low-speed main)
mode
1
1
HS (high-speed main)
mode
Other than above
Setting prohibited
Operating Frequency Operating Voltage Range
Range
1 MHz to 2 MHz
1.6 V to 5.5 V
1 MHz to 2 MHz 1 MHz to 4 MHz (Rewriting of flash memory is not possible.) 1 MHz to 24 MHz 1 MHz to 2 MHz 1 MHz to 4 MHz (Rewriting of flash memory is not possible.) 1 MHz to 32 MHz
1.6 V to 5.5 V
1.8 V to 5.5 V 1.6 V to 5.5 V
1.8 V to 5.5 V
FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0
Frequency of the High-speed On-chip Oscillator Clock
1
0
0
0
32 MHz
0
0
0
0
24 MHz
1
0
0
1
16 MHz
0
0
0
1
12 MHz
1
0
1
0
8 MHz
0
0
1
0
6 MHz
1
0
1
1
4 MHz
0
0
1
1
3 MHz
1
1
0
0
2 MHz
1
1
0
1
1 MHz
Other than above
Setting prohibited
Note
When boot swapping is to be used, 000C2H is replaced with 040C2H. Therefore, set the same value as the setting in 000C2H in 040C2H.
Caution 1. Be sure to set bits 5 and 4 to 10B. Caution 2. The operating frequency range and operating voltage range vary depending on the flash operation
mode. For details, see 37.4 AC Characteristics.
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RL78/G23
CHAPTER 32 OPTION BYTES
32.3
Format of On-chip Debug Option Byte
The format of on-chip debug option byte is shown below.
Figure 32 - 6 Format of On-chip Debug Option Byte (000C3H or 040C3H)
Address:
000C3H or 040C3HNote
Symbol
7
6
5
4
3
2
1
0
OCDENSET
0
0
0
0
1
0
OCDERSD
OCDENSET OCDERSD
Control of on-chip debug operation
0
0
Disables on-chip debugging.
0
1
Setting prohibited
1
0
Enables on-chip debugging.
Erases data of flash memory in case of failures in authenticating on-chip debug
security ID.
1
1
Enables on-chip debugging.
Does not erase data of flash memory in case of failures in authenticating on-
chip debug security ID.
Note
When boot swapping is to be used, 000C3H is replaced with 040C3H. Therefore, set the same value as the setting in 000C3H in 040C3H.
Caution Only bits 7 and 0 (OCDENSET and OCDERSD) are specifiable. Be sure to set bits 6 to 1 to 000010B.
Remark
The use of on-chip debugging changes the values of bits 3 to 1. Accordingly, the values after such settings are made become undefined. However, note that when setting the option byte, be sure to set bits 3 to 1 to their default values (0, 1, and 0).
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RL78/G23
CHAPTER 32 OPTION BYTES
32.4
Setting of Option Bytes
The user option bytes and on-chip debug option byte can also be set by using linker options instead of statements in the source code. In such cases, the settings made by using linker options are given priority over the statements in the source code as shown below. An example of the statements in relation to the option byte settings in software is shown below.
.CSEG
OPT_BYTE
.DB
0x36
; Does not use the interval interrupt of the watchdog timer.
; Enables watchdog timer operation.
; The window open period of the watchdog timer is 50%.
; The overflow time of the watchdog timer is 210/fIL.
; Stops watchdog timer operation during HALT/STOP mode.
.DB
0xBF
; Selects VLVD0 as 1.69 V on rising edges and 1.65 V on falling edges.
; Select the interrupt mode as the LVD0 operation mode.
.DB
0x6D
; Select the LP (low-power main) mode as the flash operation mode and 1 MHz
; as the frequency of the high-speed on-chip oscillator clock.
.DB
0x85
; Enables on-chip debug operation, does not erase flash memory data when
; security ID authentication fails.
When boot swapping is to be used during self-programming, 000C0H to 000C3H are replaced with 040C0H to 040C3H. Therefore, set the same values as the settings in 000C0H to 000C3H in 040C0H to 040C3H as shown below.
OPT2 .CSEG
AT
0x040C0
.DB
0x36 ; Does not use the interval interrupt of the watchdog timer.
; Enables watchdog timer operation.
; The window open period of the watchdog timer is 50%.
; The overflow time of the watchdog timer is 210/fIL.
; Stops watchdog timer operation during HALT/STOP mode.
.DB
0xBF ; Selects VLVD0 as 1.69 V on rising edges and 1.65 V on falling edges.
; Select the interrupt mode as the LVD0 operation mode.
.DB
0x6D ; Select the LP (low-power main) mode as the flash operation mode and 1 MHz
; as the frequency of the high-speed on-chip oscillator clock.
.DB
0x85 ; Enables on-chip debug operation, does not erase flash memory data when
; security ID authentication fails.
Caution
To specify the option byte by using assembly language, use OPT_BYTE as the relocation attribute name of the CSEG pseudo instruction. To specify 040C0H to 040C3H for use as the option bytes in the case of boot swapping, use the relocation attribute AT to specify absolute addresses.
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RL78/G23
CHAPTER 33 FLASH MEMORY
CHAPTER 33 FLASH MEMORY
The RL78 microcontroller incorporates the flash memory to which a program can be written, erased, and overwritten while mounted on the board. The flash memory includes the "code flash memory", in which programs can be executed, and the "data flash memory", an area for storing data.
FFFFFH
FFF00H FFEFFH FFEE0H FFEDFH
Special function registers (SFRs) 256 bytes
General-purpose registers 32 bytes
RAM 12 to 48 Kbytes
Mirror area
F1000H F0FFFH F0800H F07FFH
F0000H EFFFFH
Data flash memory 8 Kbytes
Reserved
Extended special function registers (2nd SFRs) 2 Kbytes
Reserved
Code flash memory 96 to 768 Kbytes
00000H
The following methods for programming the flash memory are available. The code flash memory can be rewritten to through serial programming using a flash memory programmer or an external device (UART communication), or through self-programming.
· Serial Programming Using Flash Memory Programmer (see 33.1.) Data can be written to the flash memory on-board or off-board by using a dedicated flash memory programmer.
· Serial Programming Using External Device (that Incorporates UART) (see 33.2.) Data can be written to the flash memory on-board through UART communication with an external device (microcontroller or ASIC).
· Self-Programming (see 33.6.) The user application can execute self-programming of the code flash memory by using the flash self-programming code.
Caution
When rewriting the flash memory, stop the middle-speed on-chip oscillator (MIOEN = 0) and select the high-speed on-chip oscillator (MCM1 = 0) as the main on-chip oscillator clock (fOCO). Do not change the flash operation mode register (FLMODE).
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RL78/G23
CHAPTER 33 FLASH MEMORY
The data flash memory can be rewritten to by using the Renesas flash driver during user program execution
<R>
(background operation). For access and writing to the data flash memory, see 33.6 Self-Programming and 33.8 Data
Flash Memory.
The code flash memory and the data flash memory have a function to protect them from writing. For details, see 27.3.3
Flash memory guard function.
33.1
Serial Programming Using Flash Memory Programmer
The following dedicated flash memory programmer can be used to write data to the internal flash memory of the RL78 microcontroller.
· PG-FP6 · E2 or E2 Lite on-chip debugging emulator
Data can be written to the flash memory on-board or off-board, by using a dedicated flash memory programmer.
(1) On-board programming The contents of the flash memory can be rewritten after the RL78 microcontroller has been mounted on the target system. Mount a connector for the dedicated flash memory programmer on the target system.
(2) Off-board programming Data can be written to the flash memory with a dedicated program adapter before the RL78 microcontroller is mounted on the target system.
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RL78/G23
CHAPTER 33 FLASH MEMORY
Table 33 - 1 Wiring between RL78/G23 and Dedicated Flash Memory Programmer
Pin Configuration of Dedicated Flash Memory Programmer
Signal Name
E2 or E2 Lite On- I/O PG-FP6 Chip Debugging
Emulator
Pin Function
Pin Name
30-pin
LSSOP (300 mil)
32-pin
HWQFN (5 × 5) LQFP (7 × 7)
36-pin
WFLGA (4 × 4)
Pin No. 40-pin
44-pin
48-pin
52-pin
HWQFN (6 × 6)
LQFP (10 × 10)
LFQFP (7 × 7) HWQFN (7 × 7)
LQFP (10 × 10)
-- SI/RxD
TOOL0 --
I/O
Transmit/ TOOL0/
5
receive signal P40
I/O
1
F6
1
2
39
4
--
RESET
Output Reset signal RESET
6
2
E5
2
3
40
5
/RESET
--
Output
VCC
VDD
I/O
VDD voltage VDD
12
8
B6
10
11
48
13
generation/
power
monitoring
GND
--
Ground
VSS
11
7
C5
9
10
47
12
REGC
10
6
D5
8
Note
9
46
11
FLMD1
EMVDD
--
Driving power VDD
12
for TOOL0 pin
8
B6
10
11
48
13
Pin Configuration of Dedicated Flash Memory Programmer
Signal Name
E2 or E2 Lite On- I/O PG-FP6 Chip Debugging
Emulator
Pin Function
Pin Name
64-pin
LQFP (12 × 12) LFQFP (10 × 10)
64-pin
WFLGA (5 × 5)
--
TOOL0
I/O
Transmit/ TOOL0/
5
D6
receive signal P40
SI/RxD
--
I/O
--
RESET
Output Reset signal RESET
6
E7
/RESET
--
Output
VCC
VDD
I/O
VDD voltage VDD
15
B7
generation/
power
monitoring
GND
--
Ground
VSS
13
C7
EVSS
14
B8
REGC
12
D7
Note
FLMD1
EMVDD
--
Driving power EVDD
16
A8
for TOOL0 pin
Note
Connect the REGC pin to ground via a capacitor (0.47 to 1 µF).
Pin No. 80-pin 100-pin
100-pin
128-pin
LQFP (14 × 14) LFQFP (12 × 12)
LFQFP (14 × 14)
LQFP (14 × 20)
LFQFP (14 × 20)
9
12
89
22
10
13
90
26
19
22
99
35
17
20
97
33
18
21, 43
98, 20
34, 56
16
19
96
32
20
23, 53 100, 30 36, 57
Remark Pins that are not indicated in the above table can be left open when using the flash memory programmer for flash programming.
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33.1.1 Programming environment
The environment required for writing a program to the flash memory of the RL78 microcontroller is illustrated below.
Figure 33 - 1 Environment for Writing Program to Flash Memory
RS-232C USB
Host machine
PG-FP6
E2 or E2 Lite
Dedicated flash memory programmer
VDD EVDD Note VSS, EVSS Note
RESET TOOL0
(dedicated single-line UART)
Note
Only present in 64, 80, 100, and 128-pin products.
RL78 microcontroller
A host machine that controls the dedicated flash memory programmer is necessary. To interface between the dedicated flash memory programmer and the RL78 microcontroller, the TOOL0 pin is used for manipulation such as writing and erasure via a dedicated single-line UART.
33.1.2 Communication mode
Communication between the dedicated flash memory programmer and the RL78 microcontroller is established by serial communication using the TOOL0 pin via a dedicated single-line UART of the RL78 microcontroller.
Transfer rate: 1 Mbps, 500 kbps, 250 kbps, 115.2 kbps
Figure 33 - 2 Communication with Dedicated Flash Memory Programmer
PG-FP6 E2 or E2 Lite
Dedicated flash memory programmer
VDD N ote 1
EMVDD N ote 2 , FLMD1 Note 3
GND RESET Note 2, /RESET Note 3 TOOL0 Note 2 SI/RxD Note 3
VDD VDD/EVDD N ote 4
VSS/EVSS N ote 4 /REGC N ote 5
RESET TOOL0
RL78 microcontroller
Note 1. Note 2. Note 3. Note 4. Note 5.
The signal name for the PG-FP6 is VCC. When using E2 or E2 Lite on-chip debugging emulator. When using PG-FP6. Only present in 64, 80, 100, and 128-pin products. Connect the REGC pin to ground via a capacitor (0.47 to 1 µF).
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The dedicated flash memory programmer generates the following signals for the RL78 microcontroller. See the manual for the PG-FP6 or, E2 or E2 Lite on-chip debugging emulator for details.
Table 33 - 2 Pin Connection
PG-FP6
Dedicated Flash Memory Programmer
Signal Name
E2 or E2 Lite
I/O
On-Chip Debugging Emulator
Pin Function
VCC
VDD
I/O VDD voltage generation/power monitoring
GND
--
Ground
FLMD1
EMVDD
--
Driving power for TOOL0 pin
/RESET
--
Output
Reset signal
--
RESET
Output
--
TOOL0
I/O
Transmit/receive signal
SI/RxD
--
I/O
Transmit/receive signal
Note 1. Note 2.
Pins to be connected differ with the product. For details, see Table 33 - 1. Connect the REGC pin to ground via a capacitor (0.47 to 1 µF).
RL78 Microcontroller Pin Name Note 1
VDD VSS, EVSS, REGC Note 2
VDD, EVDD RESET
TOOL0
33.2
Serial Programming Using External Device (that Incorporates UART)
On-board data writing to the internal flash memory is possible by using the RL78 microcontroller and an external device
(a microcontroller or ASIC) connected to a UART.
<R>
On the development of flash memory programmer by user, refer to the RL78 Microcontrollers (RL78 Protocol C) Serial
Programming Edition Application Note (R01AN5756).
33.2.1 Programming environment
The environment required for writing a program to the flash memory of the RL78 microcontroller is illustrated below.
Figure 33 - 3 Environment for Writing Program to Flash Memory
Note
VDD, EVDD Note VSS, EVSS Note
RESET
External device
UART (TOOLTxD, TOOLRxD)
(such as microcontroller and ASIC)
TOOL0
Only present in 64, 80, 100, and 128-pin products.
RL78 microcontroller
Processing to write data to or delete data from the RL78 microcontroller by using an external device is performed onboard. Off-board writing is not possible.
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33.2.2 Communication mode
Communication between the external device and the RL78 microcontroller is established by serial communication using the TOOLTxD and TOOLRxD pins via the dedicated UART of the RL78 microcontroller.
Transfer rate: 1 Mbps, 500 kbps, 250 kbps, 115.2 kbps
Figure 33 - 4 Communication with External Device
VDD
GND
RESETOUT
External device (such as microcontroller and ASIC)
RxD TxD
PORT
Note 1. Note 2.
Only present in 64, 80, 100, and 128-pin products. Connect the REGC pin to ground via a capacitor (0.47 to 1 µF).
VDD/EVDD0 Note 1 VSS/EVSS0 Note 1/REGC Note 2
RESET
TOOLTxD
RL78 microcontroller
TOOLRxD
TOOL0
The external device generates the following signals for the RL78 microcontroller.
Table 33 - 3 Pin Connection
Signal Name
External Device I/O
Pin Function
VDD
I/O
VDD voltage generation/power monitoring
GND
--
Ground
RESETOUT
Output
Reset signal output
RxD
Input
Receive signal
TxD
Output
Transmit signal
PORT
Output
Mode signal
Note 1. Note 2.
Only present in 64, 80, 100, and 128-pin products. Connect the REGC pin to ground via a capacitor (0.47 to 1 µF).
RL78 Microcontroller Pin Name
VDD, EVDDNote 1 VSS, REGCNote 2, EVSSNote 1 RESET TOOLTxD TOOLRxD TOOL0
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33.3
Connection of Pins on Board
To write to the flash memory on board by using a flash memory programmer, mount a connector for the dedicated flash memory programmer on the target system. In addition, include a function for mode switching from normal operation to flash memory programming in the board design. Entry to flash memory programming mode places all pins that are not to be used in programming the flash memory in the same states as those immediately after a reset. If the given states do not suit the operation of external devices, apply appropriate handling to the pins.
Remark For details on flash memory programming mode, refer to 33.4.2 Flash memory programming mode.
33.3.1 P40/TOOL0 pin
In the flash memory programming mode, connect this pin to the dedicated flash memory programmer via an external 1k pull-up resistor. When this pin is used as the port pin, use that by the following method.
When used as an input pin: Input of the low level is prohibited for tHD period after external reset release. However, when this pin is used via a pull-down resistor, use a resistor with a value of 500 k or more.
When used as an output pin: When this pin is used via pull-down resistors, use the 500 k or more resistors.
Remark 1. tHD: This is the time over which the TOOL0 pin must be kept at the low level following the end of the external and internal resets for setting of the flash memory programming mode (see 37.10 Timing of Entry to Flash Memory Programming Modes).
Remark 2. The SAU and IICA pins are not used for communication between the RL78 microcontroller and dedicated flash memory programmer, because single-line UART (TOOL0 pin) is used.
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33.3.2 RESET pin
Signal conflict will occur if the reset signal of the dedicated flash memory programmer and external device are connected to the RESET pin that is connected to the reset signal generator on the board. To prevent this conflict, isolate the connection with the reset signal generator. The flash memory will not be correctly programmed if the reset signal is input from the user system while the flash memory programming mode is set. Do not input any signal other than the reset signal of the dedicated flash memory programmer and external device.
Figure 33 - 5 Signal Conflict (RESET Pin)
RL78 microcontroller
Input pin
Signal conflict
Dedicated flash memory programmer connection pin
Another device
Output pin
In the flash memory programming mode, a signal output by another device will conflict with the signal output by the dedicated flash memory programmer. Therefore, isolate the signal of another device.
33.3.3 Port pins
Entry to flash memory programming mode places all pins that are not to be used in programming the flash memory in the same states as those immediately after a reset. If the given states of the port pins do not suit the operation of external devices that are connected to individual port pins, apply appropriate handling to the pins such as connection to VDD or VSS via resistors.
33.3.4 REGC pin
Connect the REGC pin to GND via a capacitor having excellent characteristics (0.47 to 1 µF) in the same manner as during normal operation. Also, use a capacitor with good characteristics, since it is used to stabilize internal voltage.
33.3.5 X1 and X2 pins
Connect X1 and X2 in the same states as in the normal operation mode.
Remark In the flash memory programming mode, the high-speed on-chip oscillator clock (fIH) is used.
33.3.6 Power supply
To use the supply voltage output of the flash memory programmer, connect the VDD pin to VDDNote of the flash memory programmer, and the VSS pin to GND of the flash memory programmer. To use the on-board supply voltage, connect the power supply in the same manner as during normal operation. However, when writing to the flash memory by using the flash memory programmer and using the on-board supply voltage, be sure to connect the VDD and VSS pins to VDDNote and GND of the flash memory programmer to use the power monitor function by the flash memory programmer.
Note
The signal name for the PG-FP6 is VCC.
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33.4
Programming Method
33.4.1 Serial programming procedure
The following figure illustrates a flow for rewriting the code flash memory through serial programming.
Figure 33 - 6 Code Flash Memory Manipulation Procedure
Start
Controlling TOOL0 pin and RESET pin
Flash memory programming mode is set
Manipulate code flash memory
End?
No
Yes End
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33.4.2 Flash memory programming mode
To rewrite the contents of the code flash memory through serial programming, specify the flash memory programming mode. The following describes how to enter the flash memory programming mode.
<For serial programming by using the dedicated flash memory programmer> Connect the RL78 microcontroller to a dedicated flash memory programmer. Starting communications with the dedicated flash memory programmer automatically places the RL78 LSI chip in the flash memory programming mode.
<For serial programming by using an external device (UART communication)>
Set the TOOL0 pin to the low level, and then cancel the reset (see Table 33 - 4). After that, enter flash memory
<R>
programming mode according to steps <1> to <4> shown in Figure 33 - 7. For details, refer to the RL78
microcontrollers (RL78 Protocol C) Serial Programming Edition Application Note (R01AN5756).
Table 33 - 4 Relationship between the TOOL0 Pin and Operation Mode after Release from the Reset State
TOOL0
Operation Mode
EVDD
Normal operation mode
0 V
Flash memory programming mode
Figure 33 - 7 Entry to Flash Memory Programming Mode
<1> <2>
<3>
<4>
RESET
TOOL0
723 µs + tHD processing
time
1 byte of data specifying the mode
tSU
tSUINIT
<1> The low level is input to the TOOL0 pin. <2> The external reset is de-asserted (release from a POR or LVD reset must precede this). <3> The TOOL0 pin is set to the high level. <4> The bit rate setting is based on the UART reception.
Remark
tSUINIT: The section is the up to 100 ms from the end of the external reset within which specifying the initial
communications settings must be finished.
tSU:
This is the time from the TOOL0 pin being placed at the low level until the end of the external reset.
tHD:
This is the time over which the TOOL0 pin must be kept at the low level following the end of the external and
internal resets (excluding the processing time of the firmware to control the flash memory).
For details, see 37.10 Timing of Entry to Flash Memory Programming Modes.
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33.4.3 Selecting communication mode
The communication modes of the RL78 microcontroller are shown in the table below.
Table 33 - 5 Communication Modes
Communication Mode
Standard SettingNote 1
Pins Used
Port
SpeedNote 2
Frequency
Multiply Rate
Single-line UART
UART
115200 bps,
--
(when flash memory
250000 bps,
programmer is used, or when
500000 bps,
external device is used)
1 Mbps
--
TOOL0
Dedicated UART
UART
115200 bps,
--
(when external device is used)
250000 bps,
500000 bps,
1 Mbps
--
TOOLTxD,
TOOLRxD
Note 1. Note 2.
Selection items for Standard settings on GUI of the flash memory programmer. Because factors other than the baud rate error, such as the signal waveform slew, also affect UART communication, thoroughly evaluate the slew as well as the baud rate error.
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<R>
33.4.4 Communication commands
The RL78 microcontroller executes serial programming through the commands listed in Table 33 - 6. The signals sent from the dedicated flash memory programmer or external device to the RL78 microcontroller are called commands, and programming functions corresponding to the commands are executed. For details, refer to the RL78 Microcontrollers (RL78 Protocol C) Serial Programming Edition Application Note (R01AN5756).
Table 33 - 6 Flash Memory Control Commands
Classification
Command Name
Function
Verification
Verify
Compares the contents of a specified area of the flash memory with data transmitted from the programmer.
Erasure
Block Erase
Erases a specified area in the flash memory.
Blank checking
Block Blank Check
Checks if a specified block in the flash memory has been correctly erased
Writing
Programming
Writes data to a specified area in the flash memoryNote.
Getting information
Silicon Signature
Gets the RL78 microcontroller information (such as the device name, flash memory configuration, and programming firmware version).
Checksum
Gets the checksum data for a specified area.
Security
Security Set
Sets security information.
Security Get
Gets security information.
Security Release
Release setting of prohibition of writing.
Others
Reset
Used to detect the state of synchronization during communications.
Baud Rate Set
Sets baud rate when UART communication mode is selected.
Note
Confirm that no data have been written to the write area. If data in the area has not been erased, do not attempt further writing of data because data cannot be erased after the setting to prohibit block erasure has been made.
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Product information (such as device name and firmware version) can be obtained by executing the "Silicon Signature" command. Tables 33 - 7 and 33 - 8 show signature data list and example of signature data list.
Table 33 - 7 Signature Data List
Field name
Description
Number of bytes of transmit data
Device code
The serial number assigned to the device
3 bytes
Device name
Device name (ASCII code)
10 bytes
Code flash memory area end address End address of code flash memory area (Sent from the lower-order byte of the address. Example. 00000H to 1FFFFH (128 Kbytes) FFH, FFH, 01H)
3 bytes
Data flash memory area end address End address of data flash memory area (Sent from the lower-order byte of the address. Example. F1000H to F2FFFH (8 Kbytes) FFH, 2FH, 0FH)
3 bytes
Firmware version
Version information of firmware for programming (Sent from the byte equivalent to the highest-order digit of the version number. Example. Ver. 1.02 01H, 00H, 02H)
3 bytes
Table 33 - 8 Example of Signature Data List
Field name
Description
Device code Device name
RL78 protocol C R7F100GLG
Code flash memory area end address Code flash memory area 00000H to 1FFFFH (128 Kbytes)
Data flash memory area end address Data flash memory area F1000H to F2FFFH (8 Kbytes)
Firmware version
Ver. 1.02
Number of bytes of transmit data 3 bytes 10 bytes
3 bytes 3 bytes 3 bytes
Data (hexadecimal)
10 00 0A
52 = "R" 37 = "7" 46 = "F" 31 = "1" 30 = "0" 30 = "0" 47 = "G" 4C = "L" 47 = "G" 20 = " "
FF FF 1F
FF 2F 0F
01 00 02
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33.5
Processing Times for Commands When the Dedicated Flash Memory
Programmer Is in Use (Reference Values)
The following shows the processing time for each command (reference value) when PG-FP6 is used as a dedicated flash memory programmer.
Table 33 - 9 Processing Times for Commands When PG-FP6 Is in Use (Reference Values)
PG-FP6 Command
96 Kbytes
128 Kbytes
Code Flash Memory 192 Kbytes 256 Kbytes 384 Kbytes
512 Kbytes
768 Kbytes
Erasure
1.2 s
1.3 s
1.7 s
2.1 s
2.8 s
3.5 s
5 s
Writing
2.4 s
2.9 s
4 s
5.2 s
7.3 s
9.5 s
14.1 s
Verification
1.7 s
2.2 s
3 s
3.9 s
5.6 s
7.3 s
10.9 s
Writing after erasure
3.2 s
4 s
5.4 s
6.9 s
9.8 s
12.7 s
18.8 s
Remark
The command processing times (reference values) shown in the table are typical values under the following conditions. Port: TOOL0 (single-line UART) Speed: 1,000,000 bps
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33.6
Self-Programming
The RL78 microcontroller supports a self-programming function that can be used to rewrite the flash memory via a user program. Because this function allows a user application to rewrite the flash memory by using the flash selfprogramming code, it can be used to upgrade the program in the field.
Caution 1. Caution 2.
Caution 3.
Caution 4.
The self-programming function cannot be used when the CPU operates with the subsystem clock (fSUB). To prohibit an interrupt during self-programming, in the same way as in the normal operation mode, execute the flash self-programming code in the state where the IE flag is cleared to 0 by the DI instruction. To enable an interrupt, clear the interrupt mask flag to 0 to accept in the state where the IE flag is set to 1 by the EI instruction, and then execute the flash self-programming code. The high-speed on-chip oscillator should be kept operating during self-programming. If it is stopped, it should be made to operate again (HIOSTOP = 0), and the flash self-programming code should be reexecuted after 5 µs have elapsed. Stop the middle-speed on-chip oscillator (MIOEN = 0) and select the high-speed on-chip oscillator (MCM1 = 0) as the main on-chip oscillator clock (fOCO). When rewriting the flash memory, do not change the flash operation mode register (FLMODE).
<R>
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33.6.1 Self-programming procedure
<R>
The following figure illustrates a flow for rewriting the flash memory by using a flash self-programming code. For details
on registers for use during self-programming, see 33.6.2 Registers to control the flash memory.
Figure 33 - 8 Flow of Self-Programming (Rewriting Flash Memory)
Code flash memory control start Initialize flash environment. Flash shield window setting Erasure Writing Verification Get flash information. Set flash information. Close flash environment. End
Prohibit access to the flash memory. Prohibit transitions to STOP mode. Prohibit stopping of the clock.
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<R> 33.6.2 Registers to control the flash memory
The following registers are used to control the flash memory.
· Flash address pointer registers H and L (FLAPH, FLAPL) · Flash end address pointer registers H and L (FLSEDH, FLSEDL) · Flash write buffer registers H and L (FLWH, FLWL) · Flash protect command register (PFCMD) · Flash status register (PFS) · Flash programming mode control register (FLPMC) · Flash area selection register (FLARS) · Flash memory sequencer initial setting register (FSSET) · Flash memory sequencer control register (FSSQ) · Flash extra sequencer control register (FSSE) · Flash registers initialization register (FLRST) · Flash memory sequencer status registers H and L (FSASTH, FSASTL) · Flash security flag monitoring register (FLSEC) · Flash FSW monitoring register E (FLFSWE) · Flash FSW monitoring register S (FLFSWS) · Data flash control register (DFLCTL) · Interrupt vector jump enable register (VECTCTRL) · Interrupt vector change registers 0 and 1 (FLSIVC0, FLSIVC1)
CHAPTER 33 FLASH MEMORY
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Writing to the registers for controlling the flash memory is only possible under specified conditions. Table 33 - 10 shows the conditions that enables write access to the flash memory.
Table 33 - 10 Conditions That Enable Write Access to the Flash Memory
Register Name
Conditions for Write Access
Registers to be used during selfprogramming (writing to these registers is not possible while the flash memory sequencer is activated)
FLAPL, FLAPH FLSEDL, FLSEDH FLWL, FLWH FLARS
FSSET
Writing to these registers is possible when either of the following conditions is met while the value of the FLRST bit of the FLRST register is 0. · The value of the FLSPM bit of the FLPMC register is 1. · The value of the EEEMD bit of the FLPMC register is 1.
Writing to bits 4 to 0 of the FSSET register is possible when either of the following conditions is met. · The value of the FLSPM bit of the FLPMC register is 1. · The value of the EEEMD bit of the FLPMC register is 1.
FSSQ
Writing to bits 7 and 6 of the FSSET register is possible when either of the following conditions is met while the value of the BTPR bit of the FLSEC register is 1. · The value of the FLSPM bit of the FLPMC register is 1. · The value of the EEEMD bit of the FLPMC register is 1.
Writing to this register is possible when either of the following conditions is met while the value of the FLRST bit of the FLRST register is 0. · The value of the FLSPM bit of the FLPMC register is 1 and the value of
the FWEDIS bit of the FLPMC register is 0. · The value of the EEEMD bit of the FLPMC register is 1.
FSSE
* Writing to the SQST and FSSTP bits is always possible regardless of the state of the flash memory sequencer. For details, see 33.6.2.9 Flash memory sequencer control register (FSSQ).
Writing to this register is possible when the value of the FLRST bit of the FLRST register is 0, the value of the FLSPM bit of the FLPMC register is 1, and the value of the FWEDIS bit of the FLPMC register is 0.
FLPMC FLRST
* Writing to the ESQST bit is always possible regardless of the state of the flash memory sequencer. For detail, see 33.6.2.10 Flash extra sequencer control register (FSSE).
Writing to these registers is possible while the flash memory sequencer is stopped.
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33.6.2.1 Flash address pointer registers H and L (FLAPH, FLAPL)
The FLAPH and FLAPL registers specify the address where programming the flash memory is to start. The FLAPH and FLAPL registers can be set by 8-bit and 16-bit memory manipulation instructions, respectively. The values of the FLAPH and FLAPL registers are 00H and 0000H, respectively, under either of the following conditions. · Following a reset · The value of the FLRST bit of the FLRST register is 1.
Figure 33 - 9 Format of Flash Address Pointer Registers H and L (FLAPH, FLAPL)
Address: After reset: R/W:
F02C4H 00H R/W
Symbol
7
6
5
4
3
2
1
0
FLAPH
0
0
0
0
FLAP19 FLAP18 FLAP17 FLAP16
Address: After reset: R/W:
F02C2H 0000H R/W
Symbol
15
FLAPL FLAP15
14 FLAP14
13 FLAP13
12 FLAP12
11 FLAP11
10 FLAP10
9 FLAP9
8 FLAP8
7 FLAP7
6 FLAP6
5 FLAP5
4 FLAP4
3 FLAP3
2 FLAP2
1 FLAP1
0 FLAP0
Caution 1. Values read during the execution of a command for the extra area sequencer are undefined. Caution 2. The settings of the FLAP1 and FLAP0 bits are meaningless during programming of the code flash
memory. Caution 3. New values cannot be written to these registers while the flash memory sequencer is operating.
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33.6.2.2 Flash end address pointer registers H and L (FLSEDH, FLSEDL)
The FLSEDH and FLSEDL registers specify the address where programming of the flash memory is to end. The FLSEDH and FLSEDL registers can be set by 8-bit and 16-bit memory manipulation instructions, respectively. The values of the FLSEDH and FLSEDL registers are 00H and 0000H, respectively, under either of the following conditions. · Following a reset · The value of the FLRST bit of the FLRST register is 1.
Figure 33 - 10 Format of Flash End Address Pointer Registers H and L (FLSEDH, FLSEDL)
Address: After reset: R/W:
F02C8H 00H R/W
Symbol
7
6
5
4
3
2
1
0
FLSEDH
0
0
0
0
EWA19
EWA18
EWA17
EWA16
Address: After reset: R/W:
F02C6H 0000H R/W
Symbol FLSEDL
15 EWA15
14 EWA14
13 EWA13
12 EWA12
11 EWA11
10 EWA10
9 EWA9
8 EWA8
7 EWA7
6 EWA6
5 EWA5
4 EWA4
3 EWA3
2 EWA2
1 EWA1
0 EWA0
Caution 1. Values read during the execution of a command for the extra area sequencer are undefined. Caution 2. The settings of the EWA1 and EWA0 bits are meaningless during programming of the code flash
memory. Caution 3. New values cannot be written to these registers while the flash memory sequencer is operating.
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Table 33 - 11 Method of Setting the FLAP and FLSED Registers
Commands exclusively for use with the code/data flash memory
area sequencer
Settings of the FLAP and FLSED Registers
FSSQ
Writing
FLAPH, FLAPL: Address from which writing is to proceed FLSEDH, FLSEDL: All 0s
Blank checking
For one word:
Settings of FLAPH and FLAPL = settings of FLSEDH and FLSEDL
For two or more words: Settings of FLAPH and FLAPL < settings of FLSEDH and FLSEDL
Block erasureNote
Code flash memory
FLAPH, FLAPL:
Set the start address and 0s in the FLAP[19:11] bits and the FLAP[10:2] bits, respectively.
FLSEDH, FLSEDL: Set the end address and 1s in the EWA[19:11] bits and the EWA[10:2] bits, respectively.
Data flash memory
FLAPH, FLAPL:
Set the start address and 0s in the FLAP[19:8] bits and the FLAP[7:0] bits, respectively.
FLSEDH, FLSEDL: Set the end address and 1s in the EWA[19:8] bits and the EWA[7:0] bits, respectively.
FSSE
All commands
Settings of FLAPH and FLAPL: All 0s Settings of FLSEDH and FLSEDL: All 0s
Note
Set the FLAPH and FLAPL registers and the FLSEDH and FLSEDL registers so that the following condition is met. Combined settings of FLAPH and FLAPL combined settings of FLSEDH and FLSEDL
Caution 1. For products with 512 or more Kbytes of flash memory, consecutive execution of each of the blank check and block erase commands is not possible.
Caution 2. Consecutive execution for the code and data flash memory areas of each of the blank check, and block erase commands is not possible.
Caution 3. To program the code and data flash memory areas, set the FLSPM and EEEMD bits of the FLPMC register to 1, respectively.
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33.6.2.3 Flash write buffer registers H and L (FLWH, FLWL)
The FLWH and FLWL registers hold data to be written during programming of the flash memory. The FLWH and FLWL registers can be set by a 16-bit memory manipulation instruction. The value of each of the FLWH and FLWL registers is 0000H under any of the following conditions. · Following a reset · The value of the FLRST bit of the FLRST register is 1. · The flash memory sequencer has finished operating. Writing to these registers is not possible while the value of the FLRST bit is 1. Set data to be written to the data flash memory in the 8 lower-order bits of the FLWL register.
Figure 33 - 11 Format of Flash Write Buffer Registers H and L (FLWH, FLWL)
Address: After reset: R/W:
F02CEH 0000H R/W
Symbol FLWH
15 FLW31
14 FLW30
13 FLW29
12 FLW28
11 FLW27
10 FLW26
9 FLW25
8 FLW24
7 FLW23
6 FLW22
5 FLW21
4 FLW20
3 FLW19
2 FLW18
1 FLW17
0 FLW16
Address: After reset: R/W:
F02CCH 0000H R/W
Symbol FLWL
15 FLW15
14 FLW14
13 FLW13
12 FLW12
11 FLW11
10 FLW10
9 FLW9
8 FLW8
7 FLW7
6 FLW6
5 FLW5
4 FLW4
3 FLW3
2 FLW2
1 FLW1
0 FLW0
Caution 1. Reading from these registers is not possible while a sequencer command is being executed. Caution 2. When writing to the data flash memory, set 0s in the FLWH register and the bits of the FLWL register
other than the 8 lower-order bits. Caution 3. New values cannot be written to these registers while the flash memory sequencer is operating.
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33.6.2.4 Flash protect command register (PFCMD)
The PFCMD register protects the flash programming mode control register (FLPMC) against write access. Enabling write access to the FLPMC register requires the execution of a specific sequence for use with the flash memory sequencer. For details on the procedure for handling the specific sequence, see 33.6.3 Setting the flash memory control mode. The PFCMD register can be set by an 8-bit memory manipulation instruction.
Figure 33 - 12 Format of Flash Protect Command Register (PFCMD)
Address: After reset: R/W:
F00C0H Undefined W
Symbol PFCMD
7 REG7
6 REG6
5 REG5
4 REG4
3 REG3
2 REG2
1 REG1
0 REG0
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33.6.2.5 Flash status register (PFS)
The PFS register indicates whether or not a protection error has been generated. For details on the conditions for setting and clearing the FPRERR bit, see 33.6.3.1 Procedure for executing the specific sequence. The PFS register can be read by a 1-bit or 8-bit memory manipulation instruction.
Figure 33 - 13 Format of Flash Status Register (PFS)
Address: After reset: R/W:
F00C1H 00H R
Symbol
7
6
5
4
3
2
1
0
PFS
0
0
0
0
0
0
0
FPRERR
FPRERR
0
No error has occurred.
1
An error has occurred.
Protection error flag
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33.6.2.6 Flash programming mode control register (FLPMC)
The FLPMC register disables or enables writing to the flash memory and selects the programming mode. Enabling write access to the FLPMC register requires the execution of a specific sequence for use with the flash memory sequencer. For details on the procedure for handling the specific sequence, see 33.6.3 Setting the flash memory control mode. The FLPMC register can be set by an 8-bit memory manipulation instruction. The value of this register is 08H following a reset.
Figure 33 - 14 Format of Flash Programming Mode Control Register (FLPMC)
Address: After reset: R/W:
F02C0H 08H R/W
Symbol
7
6
5
4
3
2
1
0
FLPMC
0
0
0
EEEMD FWEDIS
0
FLSPM
0
EEEMD 0 1
Selection of the programming mode for the data flash memory Rewrite-disabled mode Programming mode
FWEDIS
Software control over enabling or disabling erasure and programming of the code flash memoryNote
0
Enables erasure and programming.
1
Disables erasure and programming.
FLSPM
Selection of the programming mode for the code flash memory
0
Rewrite-disabled mode
1
Programming mode
Note
Be sure to keep the value of this bit at 0 until erasure or programming of the code flash memory is completed.
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33.6.2.7 Flash area selection register (FLARS)
The FLARS register selects the area of the flash memory. The FLARS register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of the FLARS register is 00H under either of the following conditions. · Following a reset · The value of the FLRST bit of the FLRST register is 1.
Figure 33 - 15 Format of Flash Area Selection Register (FLARS)
Address: After reset: R/W:
F02C1H 00H R/W
Symbol
7
6
5
4
3
2
1
0
FLARS
0
0
0
0
0
0
0
EXA
EXA 0 1
User area Extra area
Selection of the area of flash memory
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33.6.2.8 Flash memory sequencer initial setting register (FSSET)
The FSSET register sets the operating frequency of the flash memory sequencer and makes the initial settings for boot swapping. The FSSET register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 33 - 16 Format of Flash Memory Sequencer Initial Setting Register (FSSET)
Address: After reset: R/W:
F00B6H 00H R/W
Symbol
7
6
5
FSSET TMSPMD TMBTSEL
0
4 FSET4
3 FSET3
2 FSET2
TMSPMD
Specification for boot swappingNote
0
Follows the information in the extra area.
1
Follows the setting of the TMBTSEL bit.
1 FSET1
0 FSET0
TMBTSEL
Setting for temporary boot swappingNote
0
Specifies boot cluster 0 as the boot area (boot swapping does not proceed).
1
Specifies boot cluster 1 as the boot area (boot swapping proceeds).
FSET[4:0]
Setting of the operating frequency of the flash memory sequencer
--
Set the operating frequency of the flash memory sequencer.
For the correspondence between the operating frequency of the flash memory sequencer and the setting of the FSET[4:0] bits, see Table 33 - 12.
Note
Setting the TMSPMD and TMBTSEL bits is not possible while boot protection is set (BTPR = 0).
Caution
Set the value corresponding to that obtained by rounding the CPU operating frequency up to the nearest whole number in the FSET[4:0] bits. For example, when the CPU operating frequency is 4.5 MHz, set the bits for 5 MHz. Note that frequencies that are not whole numbers, such as 1.5 MHz, are not available as CPU operating frequencies below 4 MHz.
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Table 33 - 12 Correspondence between the Operating Frequency of the Flash Memory Sequencer and the Setting of the FSET[4:0] Bits
Operating Frequency
(MHz)
Setting of the FSET[4:0] Bits
Operating Frequency
(MHz)
Setting of the FSET[4:0] Bits
Operating Frequency
(MHz)
Setting of the FSET[4:0] Bits
32
11111b
31
11110b
30
11101b
29
11100b
28
11011b
27
11010b
26
11001b
25
11000b
24
10111b
23
10110b
22
10101b
21
10100b
20
10011b
19
10010b
18
10001b
17
10000b
16
01111b
15
01110b
14
01101b
13
01100b
12
01011b
11
01010b
10
01001b
9
01000b
8
00111b
7
00110b
6
00101b
5
00100b
4
00011b
3
00010b
2
00001b
1
00000b
--
--
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33.6.2.9 Flash memory sequencer control register (FSSQ)
The FSSQ register specifies the commands to be used when the code/data flash memory area sequencer is activated. The FSSQ register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of the FSSQ register is 00H under either of the following conditions. · Following a reset · The value of the FLRST bit of the FLRST register is 1.
Figure 33 - 17 Format of Flash Memory Sequencer Control Register (FSSQ)
Address: After reset: R/W:
F02C5H 00H R/W
Symbol
7
6
5
FSSQ SQST
FSSTP
0
4
3
2
1
0
0
MDCH
SQMD2 SQMD1 SQMD0
SQST 0 1
Operation control of the code/data flash memory area sequencer The code/data flash memory area sequencer is stopped. The code/data flash memory area sequencer is started.
FSSTP 0 1
Forcible termination control of the code/data flash memory area sequencer The code/data flash memory area sequencer is not forcibly terminated. The code/data flash memory area sequencer is forcibly terminated.
SQMD[2:0] 01H
MDCH setting CF: 0 DF: 0
03H
CF: 0
DF: 1
04H
CF: 0
DF: 0
Other than above
Control of the code/data flash memory area sequencer
Write Writes data specified in the FLWH and FLWL registers to the address specified in the FLAPH and FLAPL registers. · Writing 1 word (4 bytes) of data to the code flash memory: Set the data in the
FLWH and FLWL registers. · Writing 1 byte of data to the data flash memory: Set the data in the FLW[7:0]
bits of the FLWL register. Blank check Executes blank checking of the range from the address specified in the FLAPH and FLAPL registers to the address specified in the FLSEDH and FLSEDL registers. The setting of the MDCH bit of the FSSQ register depends on the target flash memory area for blank checking. Blank checking of the code flash memory or data flash memory respectively requires setting the MDCH bit to 0 or 1 before running the check. Block erase Erases blocks in the range from the block start address specified in the FLAPL and FLAPH registers to the block end address specified in the FLSEDL and FLSEDH registers. Setting prohibited
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Caution Initialization by setting the FLRST bit to 1 is only enabled while the sequencer is stopped (both the SQEND and ESQEND bits of the FSASTH register have the setting 0).
Remark CF: For access to the code flash memory DF: For access to the data flash memory
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33.6.2.10 Flash extra sequencer control register (FSSE)
The FSSE register specifies the commands for use when the extra area sequencer is activated. The FSSE register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of the FSSE register is 00H under either of the following conditions. · Following a reset · The value of the FLRST bit of the FLRST register is 1.
Figure 33 - 18 Format of Flash Extra Sequencer Control Register (FSSE)
Address: After reset: R/W:
F00B7H 00H R/W
Symbol
7
6
5
4
3
2
1
0
FSSE ESQST
0
0
0
ESQMD3 ESQMD2 ESQMD1 ESQMD0
ESQST 0 1
Operation control of the extra area sequencer The extra area sequencer is stopped. The extra area sequencer is started.
ESQMD [3:0]
Control of the extra area sequencer
01H Write to the extra area (programming of the FSW-related data)
Writes data specified in the FLWH and FLWL registers. Sets up the FSW, FSW control, and
FSW protection flag. When the FSW protection flag has been set (FSPR = 0), this action
cannot be executed. Attempted execution leads to a sequencer error (setting the ESEQER bit
of the FSASTL register to 1).
06H Write to the extra area (programming of the read-prohibited area of software from a third party
and the protection flag)
Writes data specified in the FLWH and FLWL registers. Sets up the read-prohibited area of
software from a third party and the protection flag. When the protection flag has been set
(SWPR = 0), this action cannot be executed. Attempted execution leads to a sequencer error
(setting the ESEQER bit of the FSASTL register to 1).
07H Write to the extra area (programming of the security flags and boot area switching flag)
Writes data specified in the FLWH and FLWL registers. Sets up the security flags and boot
area switching flag. For the security flags, only changing the current state of each flag to
"disabled" is possible. If boot protection has been set (BTPR = 0), setting the boot area
switching flag is not possible.
Other than Setting prohibited
above
Caution 1. Initialization by setting the FLRST bit to 1 is only enabled while the sequencer is stopped (both the SQEND and ESQEND bits of the FSASTH register have the setting 0).
Caution 2. To write to the extra area, set the EXA bit of the FLARS register to 1 and set the data to be written in the FLWH and FLWL registers before activating the extra area sequencer.
Caution 3. Values read from the FLAPL, FLWH, FLWL, and FSSQ registers are undefined after activation of the extra area sequencer.
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33.6.2.11 Flash registers initialization register (FLRST)
The FLRST register initializes all registers related to the sequencer whether it is to be used with the extra area or code/data flash memory areas. The FLRST register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 33 - 19 Format of Flash Registers Initialization Register (FLRST)
Address: After reset: R/W:
F02C9H 00H R/W
Symbol
7
6
5
4
3
2
1
0
FLRST
0
0
0
0
0
0
0
FLRST
FLRST
Control of initializing the registersNote
0
The registers are not initialized.
1
The registers are initialized.
Note
For details on how to handle the FLRST register, see 33.6.4 Clearing the registers for use with the flash memory sequencer.
Caution The registers below are initialized with the use of this register. FLAPH, FLAPL, FLSEDH, FLSEDL, FLWH, FLWL, FLARS, FSSQ, FSSE
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33.6.2.12 Flash memory sequencer status registers H and L (FSASTH, FSASTL)
The FSASTH and FSASTL registers indicate the results of the respective operations of the flash memory sequencer when it has been used with the extra area or code/data flash memory areas. The FSASTH and FSASTL registers can be read by a 1-bit or 8-bit memory manipulation instruction.
Figure 33 - 20 Format of Flash Memory Sequencer Status Registers H and L (FSASTH, FSASTL)
Address: After reset: R/W:
F02CBH 00H R
Symbol
7
6
5
4
3
2
1
0
FSASTH ESQEND SQEND
0
0
0
0
0
0
Address: After reset: R/W:
F02CAH 00HNote R
Symbol
7
FSASTL MBTSEL
6 MOPEN
5 ESEQER
4 SEQER
3 BLER
2
1
0
0
WRER
ERER
Note
The initial value of the MBTSEL bit is undefined because it depends on the value of the BTFLG bit (boot area switching flag) stored in the extra area.
ESQEND
Status flag indicating whether the extra area sequencer is stopped
0
The extra area sequence is operating.
1
The extra area sequence is stopped.
<Clearing condition> The ESQST bit is cleared.
SQEND
Status flag indicating whether the code/data flash memory area sequencer is stopped
0
The code/data flash memory area sequencer is operating.
1
The code/data flash memory area sequencer is stopped.
<Clearing condition> The SQST bit is cleared.
MBTSEL
Boot flag monitoring bitNote
0
BTFLG = 1 (the boot program area is not swapped).
1
BTFLG = 0 (the boot program area is swapped).
MOPEN
Operation status flag of the code/data flash memory area sequencer
0
The code/data flash memory area sequencer is stopped.
1
The code/data flash memory area sequencer is operating.
<Clearing condition> The code/data flash memory area sequencer is stopped.
ESEQER
Error flag of the extra area sequencer
0
No error has occurred.
1
An error has occurred.
<Clearing condition> Next activation of the extra area sequencer
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SEQER
Error flag of the flash memory sequencer
0
No error has occurred.
1
An error has occurred.
<Clearing condition> Next activation of the flash memory sequencer
BLER
Error flag for the blank check command
0
No error has occurred.
1
An error has occurred.
<Clearing condition> Activation of the next command action
WRER
Error flag for the write command
0
No error has occurred.
1
An error has occurred.
<Clearing condition> Activation of the next command action Forcible termination of a command during writing leads to the values read being undefined.
ERER
Error flag for the block erase command
0
No error has occurred.
1
An error has occurred.
<Clearing condition> Next activation of the flash memory sequencer
Forcible termination of the command during block erasing leads to values read being undefined.
Note
This bit indicates the inverse of the value of the BTFLG bit (boot area switching flag) stored in the extra area.
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33.6.2.13 Flash security flag monitoring register (FLSEC)
The FLSEC register monitors the information on the security flags and boot area switching flag. The FLSEC register can be read by a 16-bit memory manipulation instruction.
Figure 33 - 21 Format of Flash Security Flag Monitoring Register (FLSEC)
Address: After reset: R/W:
F00B0H Undefined R
Symbol
15
14
13
12
11
10
9
8
FLSEC
0
0
0
WRPR
0
SEPR
BTPR
BTFLG
7
6
5
4
3
2
1
0
0
0
0
0
SWPR
0
1
0
WRPR 0 1
Writing is prohibited. Writing is enabled.
Write-prohibited flag
SEPR 0 1
Block erasure is prohibited. Block erasure is enabled.
Block erase-prohibited flag
BTPR 0 1
Boot area rewrite-prohibited flag Rewriting of the boot area is prohibited. Rewriting of the boot area is enabled.
BTFLG 0 1
The boot area is boot cluster 0. The boot area is boot cluster 1.
Boot area switching flag
SWPR 0 1
Software from a third party read-prohibited flag Reading software from a third party is prohibited. Reading software from a third party is enabled.
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33.6.2.14 Flash FSW monitoring register E (FLFSWE)
The FLFSWE register monitors the end block number specified for the flash shield area and whether the shield area is inside or outside the window range. After a reset or writing to the extra area, the values in the extra area are reflected in the FLFSWE register. For details on the flash shield window function, see 33.6.8 Flash shield window function. The FLFSWE register can be read by a 16-bit memory manipulation instruction.
Figure 33 - 22 Format of Flash FSW Monitoring Register E (FLFSWE)
Address: After reset: R/W:
F00B4H Undefined R
Symbol
15
14
13
12
11
10
FLFSWE FSWC
0
0
0
0
0
9
8
0
FSWE8
7 FSWE7
6 FSWE6
5 FSWE5
4 FSWE4
3 FSWE3
2 FSWE2
1 FSWE1
0 FSWE0
FSWE[8:0]
End block number specified for the flash shield area
--
End block number (end block number in the window range + 1)Note
FSWC
Setting of the shield area
0
The shield area is set inside the window range.
1
The shield area is set outside the window range.
Note
The setting during serial programming is different from this. For details, see Table 33 - 13.
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33.6.2.15 Flash FSW monitoring register S (FLFSWS)
The FLFSWS register monitors the start block number specified for the flash shield area and whether the FSW function is set to prohibit or enable rewriting. After a reset or writing to the extra area, the values in the extra area are reflected in the FLFSWS register. For details on the flash shield window function, see 33.6.8 Flash shield window function. The FLFSWS register can be read by a 16-bit memory manipulation instruction.
Figure 33 - 23 Format of Flash FSW Monitoring Register S (FLFSWS)
Address: After reset: R/W:
F00B2H Undefined R
Symbol
15
14
13
12
11
10
FLFSWS FSPR
0
0
0
0
0
9
8
0
FSWS8
7 FSWS7
6 FSWS6
5 FSWS5
4 FSWS4
3 FSWS3
2 FSWS2
1 FSWS1
0 FSWS0
FSWS[8:0]
Start block number specified for the flash shield area
--
Start block number (start block number in the window range)
FSPR 0 1
FSW Setting The FSW function is set to prohibit rewriting. The FSW function is set to enable rewriting.
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33.6.2.16 Data flash control register (DFLCTL)
The DFLCTL register enables or disables access to the data flash memory. The DFLCTL register can be set by a 1-bit or 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 33 - 24 Format of Data Flash Control Register (DFLCTL)
Address: After reset: R/W:
F0090H 00H R/W
Symbol
7
6
5
4
3
2
1
DFLCTL
0
0
0
0
0
0
0
DFLEN 0 1
Data flash access control Access to the data flash memory is disabled. Access to the data flash memory is enabled.
<0> DFLEN
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33.6.2.17 Interrupt vector jump enable register (VECTCTRL)
The VECTCTRL register specifies the destination address of the jump in response to any interrupt which occurs during self-programming. The VECTCTRL register can be set by an 8-bit memory manipulation instruction. The value of this register is 00H following a reset.
Figure 33 - 25 Format of Interrupt Vector Jump Enable Register (VECTCTRL)
Address: After reset: R/W:
F00FFH 00H R/W
Symbol
7
6
5
4
3
2
1
0
VECTCTRL
0
0
0
0
0
0
0
VECTCTRL
VECTCTR L
Setting the interrupt branch destinations
0
Interrupt vector addresses in the ROM
1
Specified addresses in the RAMNote
Note
A destination address in the RAM is specified by the FLSIVC1 and FLSIVC0 registers. For details, see 33.6.2.18 Interrupt vector change registers 0 and 1 (FLSIVC0, FLSIVC1).
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33.6.2.18 Interrupt vector change registers 0 and 1 (FLSIVC0, FLSIVC1)
The FLSIVC0 and FLSIVC1 registers specify the destination address of the jump in response to any interrupt which occurs during self-programming. For details on how to handle an interrupt during self-programming, see 33.6.9 Interrupts in code flash programming mode. The FLSIVC0 and FLSIVC1 registers can be set by a 16-bit memory manipulation instruction. The values of the FLSIVC0 and FLSIVC1 registers are 0000H and 000FH, respectively, following a reset.
Figure 33 - 26 Format of Interrupt Vector Changer Registers 0 and 1 (FLSIVC0, FLSIVC1)
Address: After reset: R/W:
F0480H, F0481H 0000H R/W
Symbol
15
FLSIVC0 FLSIV15
14 FLSIV14
13 FLSIV13
12 FLSIV12
11 FLSIV11
10 FLSIV10
9 FLSIV9
8 FLSIV8
7 FLSIV7
6 FLSIV6
5 FLSIV5
4 FLSIV4
3 FLSIV3
2 FLSIV2
1 FLSIV1
0 FLSIV0
Address: After reset: R/W:
F0482H, F0483H 000FH R/W
Symbol
15
14
13
12
11
10
9
8
FLSIVC1
0
0
0
0
0
0
0
0
7 0 Caution
6
5
4
3
2
1
0
0
0
0
FLSIV19 FLSIV18 FLSIV17 FLSIV16
Set the values of the 4 higher-order bits and 16 lower-order bits of the branch destination address in the FLSIVC1 and FLSIVC0 registers, respectively.
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<R> 33.6.3 Setting the flash memory control mode
Execution of the specific sequence for use with the flash memory sequencer enables setting the flash memory control mode to the states where the code or data flash memory area or neither of them can be rewritten.
State where the code flash memory (and extra area) can be rewritten: Code flash programming mode State where the data flash memory can be rewritten: Data flash programming mode State where the flash memory (and extra area) cannot be rewritten: Rewrite-disabled mode
Caution
For handling of the extra area or data flash memory area, follow the procedure while access to the data flash memory is enabled (the value of the DFLEN bit of the DFLCTL register is 1).
33.6.3.1 Procedure for executing the specific sequence
Writing the required values to the flash programming mode control register (FLPMC register) by following steps 1 to 4 below enables the transitions to each of the flash memory control modes. <1> Write A5H to the PFCMD register. <2> Write the value to be set to the FLPMC register. <3> Write the inverse of the value to be set to the FLPMC register. <4> Write the value to be set to the FLPMC register.
· The specific sequence can only be executed while the value of the FLRST bit of the FLRST register is 0 and the flash memory sequencer is stopped.
· If writing to any other memory area or register is attempted in the intervals between steps 1 to 4 during execution of the specific sequence, a protection error occurs, writing to the specified register does not proceed, and the FPRERR flag of the flash status register (PFS) is set to 1. The FPRERR flag is cleared following a reset or when execution of the specific sequence is re-started.
33.6.3.2 Procedure for entry to the code flash programming mode
The procedure for entry to the code flash programming mode is given below. <1> Write A5H to the PFCMD register. <2> Write 02H to the FLPMC register (EEEMD = 0, FWEDIS = 0, FLSPM = 1). <3> Write FDH to the FLPMC register (inverse of 02H). <4> Write 02H to the FLPMC register (EEEMD = 0, FWEDIS = 0, FLSPM = 1).
33.6.3.3 Procedure for entry to the data flash programming mode
The procedure for entry to the data flash programming mode is given below. <1> Write A5H to the PFCMD register. <2> Write 10H to the FLPMC register (EEEMD = 1, FWEDIS = 0, FLSPM = 0). <3> Write EFH to the FLPMC register (inverse of 10H). <4> Write 10H to the FLPMC register (EEEMD = 1, FWEDIS = 0, FLSPM = 0).
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33.6.3.4 Procedure for entry to the rewrite-disabled mode
After executing the procedure for entry to the rewrite-disabled mode from the code flash programming mode or data flash programming mode and waiting for tMSNote, reading from the target flash memory for the programming mode before the mode transition becomes possible.
Note
tMS: 10 µs (mode setup time)
(1) When the interrupt vector has not been changed to addresses in the RAM The procedure for the transition in cases where branch destinations in response to interrupts are interrupt vector addresses in the ROM is given below. <1> Write A5H to the PFCMD register. <2> Write 08H to the FLPMC register (EEEMD = 0, FWEDIS = 1, FLSPM = 0). <3> Write F7H to the FLPMC register (inverse of 08H). <4> Write 08H to the FLPMC register (EEEMD = 0, FWEDIS = 1, FLSPM = 0). <5> Reading from the target flash memory area becomes possible after waiting for tMS.
(2) When the interrupt vectors have been changed to addresses in the RAM The procedure for the transition in cases where branch destinations in response to interrupts are changed to specified addresses in the RAM is given below. <1> Write A5H to the PFCMD register. <2> Write 00H to the FLPMC register (EEEMD = 0, FWEDIS = 0, FLSPM = 0). <3> Write FFH to the FLPMC register (inverse of 00H). <4> Write 00H to the FLPMC register (EEEMD = 0, FWEDIS = 0, FLSPM = 0). <5> Reading from the target flash memory area becomes possible after waiting for tMS.
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<R> 33.6.4 Clearing the registers for use with the flash memory sequencer
The following registers can be cleared by setting the FLRST bit of the flash registers initialization register (FLRST) to 1. Target registers: FLAPH, FLAPL, FLSEDH, FLSEDL, FLWH, FLWL, FLARS, FSSQ, FSSE
The procedure for clearing the target registers is given below. <1> Set the FLRST bit. <2> Use software code to wait for at least one cycle of the CPU operating clock. <3> Clear the FLRST bit.
<R> 33.6.5 Setting the operating frequency of the flash memory sequencer
Set the value corresponding to the operating frequency of the CPU (1 MHz to 32 MHz) in the FSET[4:0] bits of the flash memory sequencer initial setting register (FSSET). When making the setting, round the CPU operating frequency value up to the nearest whole number. (Example: When the CPU operating frequency is 4.5 MHz, set the bits for 5 MHz.)
How to set the operating frequency of the flash memory sequencer is described below. <1> Enter the code flash programming mode or data flash programming mode.
For the procedures for entry to each of these flash programming modes, see 33.6.3.1 Procedure for executing the specific sequence, 33.6.3.2 Procedure for entry to the code flash programming mode, and 33.6.3.3 Procedure for entry to the data flash programming mode. <2> After reading from the flash memory sequencer initial setting register (FSSET), set the TMSPMD and TMBTSEL bits to the same values as those read from the FSSET register and the FSET[4:0] bits to the value corresponding to the CPU operating frequency, respectively.
Caution
When using the flash memory sequencer to rewrite the code or data flash memory or the extra area, set the value corresponding to the CPU operating frequency in the FSET[4:0] bits of the FSSET register before proceeding. Note that if rewriting of any of these areas is attempted while the value corresponding to the CPU operating frequency is not correct, operation is undefined and written data are not guaranteed. Even if the values in the flash memory are as expected immediately after rewriting, retaining the values for any specified period is not guaranteed.
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<R> 33.6.6 Commands for use with the flash memory sequencer in the respective areas
33.6.6.1 Overview
The flash memory sequencer serves as a code/data flash memory area sequencer or an extra area sequencer. In the former role, it is used to rewrite the code flash memory area or data flash memory area, while in the latter role it is used to rewrite the extra area. To rewrite a given area, execute the corresponding commands for use with the sequencer.
33.6.6.2 Selecting the area to be rewritten
Use the flash area selection register (FLARS) to select the user area or extra area for rewriting to the code/data flash memory area or extra area, respectively.
33.6.6.3 Commands for use with the code/data flash memory area sequencer
Use the commands that are exclusively for use with the code/data flash memory area sequencer to rewrite the code or data flash memory area. Issuing a command requires entering the target command number in the SQMD[2:0] bits of the flash memory sequencer control register (FSSQ) and setting the SQST bit after or at the same time as that. Do not set the SQST bit before the SQMD[2:0] bits. For the commands exclusively for use with the code/data flash memory area sequencer, see 33.6.2.9 Flash memory sequencer control register (FSSQ).
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33.6.6.4 Operations for rewriting the code flash memory area
To rewrite the code flash memory area, enter the code flash programming mode and then execute commands for use with the code/data flash memory area sequencer. Before starting to execute a command, set the data required for execution, such as specifying an address, addresses, or data, in the corresponding registers.
Units for block erasure and for writing in rewriting of the code flash memory area
Unit for blocks to be erased: 2 Kbytes
Unit for writing:
1 word (4 bytes)
<Handling the commands> The commands to be used are for writing to and for block erasure and blank checking of the code flash memory area. · Enter the code flash programming mode. For the procedure for entry to the code flash programming mode, see
33.6.3.1 Procedure for executing the specific sequence and 33.6.3.2 Procedure for entry to the code flash programming mode. · FLARS register = 00H (EXA bit = 0): Setting to select the user (not extra) area · Set the specified data in the corresponding registers before executing the individual commands.
(1) Block erasure FLAPH and FLAPL registers: Block start address in the code flash memory (example: 0x002000) FLSEDH and FLSEDL registers: Block end address in the code flash memory (example: 0x0027FF)
(2) Writing: As writing proceeds in one-word (four-byte) units, set the address bits to a multiple of four; that is, set the two lower-order bits to 00B. FLAPH and FLAPL registers: Start address in the target flash memory area (example: 0x002000) FLSEDH and FLSEDL registers: Set all bits to 0 or do not set them (example: 0x000000). FLWH and FLWL registers: One-word (four-byte) values to be written
(3) Blank checking: As blank checking proceeds in one-word (four-byte) units, set the address bits to a multiple of four; that is, set the two lower-order bits to 00B. FLAPH and FLAPL registers: Start address in the target flash memory area (example: 0x002000) FLSEDH and FLSEDL registers: End address in the target flash memory area (example: 0x0027FF) * When blank checking is only to be applied to one word (four bytes), set the FLSEDH and FLSEDL registers to the same values as those in the FLAPH and FLAPL registers.
· After issuing a command for use with the code/data flash memory area sequencer, wait for the completion of its execution. For details on the procedure for waiting for the completion of command execution, see the section titled "Procedure for checking the completion of commands for use with the code/data flash memory area sequencer" in 33.6.6.9 Procedures for checking completion of the commands for use with the flash memory sequencer in the respective areas.
· Processing after executing a command When command processing is to continue: The same command with the target registers set to updated values or a rewrite command for any other area in the code flash memory can be executed with the state remaining in code flash programming mode. When command processing has been completed: Switch to the rewrite-disabled mode. For the procedure for switching to the rewrite-disabled mode, see 33.6.3.1 Procedure for executing the specific sequence and 33.6.3.4 Procedure for entry to the rewrite-disabled mode.
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33.6.6.5 Operations for rewriting the data flash memory area
To rewrite the data flash memory area, enter the data flash programming mode and then execute commands for use with the code/data flash memory area sequencer. Before starting to execute a command, set the data required for execution, such as specifying an address, addresses, or data, in the corresponding registers.
Units for block erasure and for writing in rewriting of the data flash memory area
Unit for blocks to be erased: 256 bytes
Unit for writing:
1 byte
<Handling the commands> The commands to be used are for writing to and for block erasure and blank checking of the data flash memory area. · Enter the data flash programming mode. For the procedure for entry to the data flash programming mode, see 33.6.3.1
Procedure for executing the specific sequence and 33.6.3.3 Procedure for entry to the data flash programming mode. · FLARS register = 00H (EXA bit = 0): Setting to select the user (not extra) area · Set the specified data in the corresponding registers before executing the individual commands.
(1) Block erasure FLAPH and FLAPL registers: Block start address in the data flash memory (example: 0x0F1100) FLSEDH and FLSEDL registers: Block end address in the data flash memory (example: 0x0F11FF)
(2) Writing: 1 byte FLAPH and FLAPL registers: Start address in the target flash memory area (example: 0x0F1101) FLSEDH and FLSEDL registers: Set all bits to 0 or do not set them (example: 0x000000). FLWH and FLWL registers: Set a value to be written in the range from 0x00000000 to 0x000000FF, since only the FLW7 to FLW0 bits are valid.
(3) Blank checking: FLAPH and FLAPL registers: Start address in the target flash memory area (example: 0x0F1100) FLSEDH and FLSEDL registers: End address in the target flash memory area (example: 0x0F11FF) * When blank checking is only to be applied to one byte, set the FLSEDH and FLSEDL registers to the same values as those in the FLAPH and FLAPL registers.
· After issuing a command for use with the code/data flash memory area sequencer, wait for the completion of its execution. For details on the procedure for waiting for the completion of command execution, see the section titled "Procedure for checking the completion of commands for use with the code/data flash memory area sequencer" in 33.6.6.9 Procedures for checking completion of the commands for use with the flash memory sequencer in the respective areas.
· Processing after executing a command When command processing is to continue: The same command with the target registers set to updated values or a rewrite command for any other area in the data flash memory can be executed with the state remaining in data flash programming mode. When command processing has been completed: Switch to the rewrite-disabled mode. For the procedure for switching to the rewrite-disabled mode, see 33.6.3.1 Procedure for executing the specific sequence and 33.6.3.4 Procedure for entry to the rewrite-disabled mode.
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33.6.6.6 Commands for use with the extra area sequencer
To rewrite the extra area, enter the code flash programming mode and then use commands that are exclusively for use with the extra area sequencer. Issuing a command requires entering the target command number in the ESQMD[3:0] bits of the flash extra sequencer control register (FSSE) and setting the ESQST bit after or at the same time as that. Do not set the ESQST bit before the ESQMD[3:0] bits.
33.6.6.7 Operations for rewriting the extra area
To rewrite the extra area, enter the code flash programming mode and then execute commands for use with the extra area sequencer. Before starting to execute a command, set the data required for execution in the corresponding registers.
Unit for writing in rewriting of the extra area Unit for writing: 1 word (4 bytes) * No erasure command is available, so a unit is not specified.
<Handling the commands> The target commands are for writing data to the extra area. · Enter the code flash programming mode. For the procedure for entry to the code flash programming mode, see
33.6.3.1 Procedure for executing the specific sequence and 33.6.3.2 Procedure for entry to the code flash programming mode. · FLARS register = 01H (EXA bit = 1): Setting to select the extra (not user) area · Before executing a command, set a one-word (four-byte) value in the FLWH and FLWL registers. Specifically, set the value to be written to the target extra area data EX bits 31 to 0 in the FLW[31:0] bits of the FLWH and FLWL registers. · Specifying a command determines the area to which data are to be written. Enter the target command number in the ESQMD[3:0] bits of the FSSE register and also set the ESQST bit of the same register to 1.
(1) For programming of the FSW-related data: 81H (2) For programming of the read-prohibited area of software from a third party and the protection flag: 86H (3) For programming of the security flags and boot area switching flag: 87H
· After issuing a command for use with the extra area sequencer, wait for the completion of its execution. For details on the procedure for waiting for the completion of command execution, see the section titled "Procedure for checking the completion of commands for use with the extra area sequencer" in 33.6.6.9 Procedures for checking completion of the commands for use with the flash memory sequencer in the respective areas.
· Processing after executing a command When command processing is to continue: The same command with the target registers set to updated values or a rewrite command for any other area in the extra area can be executed with the state remaining in code flash programming mode. When command processing has been completed: Switch to the rewrite-disabled mode. For the procedure for switching to the rewrite-disabled mode, see 33.6.3.1 Procedure for executing the specific sequence and 33.6.3.4 Procedure for entry to the rewrite-disabled mode.
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33.6.6.8 Data to be set for the commands for use with the extra area sequencer
Writing to the extra area proceeds per word (four bytes), including values that are not to be changed. Before executing a command, set the value to be set in the extra area data EX bits 31 to 0 for each target command to be executed in the FLW[31:0] bits of the FLWH and FLWL registers.
(1) Programming of the FSW-related data Set the value to be set in the extra area data EX bits 31 to 0 shown below in the FLW31 to FLW0 bits of the FLWH and FLWL registers.
EX bit 31 FSWC
EX bit 30 0
EX bit 29 0
EX bit 28 0
EX bit 27 0
EX bit 26 0
EX bit 25 0
EX bit 24 FSWE8
EX bit 23 FSWE7
EX bit 22 FSWE6
EX bit 21 FSWE5
EX bit 20 FSWE4
EX bit 19 FSWE3
EX bit 18 FSWE2
EX bit 17 FSWE1
EX bit 16 FSWE0
EX bit 15 FSPR
EX bit 14 0
EX bit 13 0
EX bit 12 0
EX bit 11 0
EX bit 10 0
EX bit 9 0
EX bit 8 FSWS8
EX bit 7 FSWS7
EX bit 6 FSWS6
EX bit 5 FSWS5
EX bit 4 FSWS4
EX bit 3 FSWS3
EX bit 2 FSWS2
EX bit 1 FSWS1
EX bit 0 FSWS0
The value to be set in the FSWE8 to FSWE0 bits (bits 24 to 16) is the end block number (end block number in the
window range + 1).
The value to be set in the FSWC bit (bit 31) is for FSW mode control.
FSWC = 0/1 (at shipment): Respectively select shielding of the area inside the window range or outside the window range
The value to be set in FSWS8 to FSWS0 bits (bits 8 to 0) is the start block number (start block number in the window
range).
The value to be set in the FSPR bit (bit 15) is for making the FSW setting to prohibit rewriting.
FSPR = 0/1 (at shipment): FSW is set to prohibit rewriting/FSW is set to enable rewriting.
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(2) Programming of the read-prohibited area of software from a third party and the protection flag Set the value to be set in the extra area data EX bits 31 to 0 shown below in the FLW31 to FLW0 bits of the FLWH and FLWL registers.
EX bit 31 SWPR
EX bit 30 --
EX bit 29 --
EX bit 28 --
EX bit 27 --
EX bit 26 --
EX bit 25 --
EX bit 24 UPAddr8
EX bit 23 UPAddr7
EX bit 22 UPAddr6
EX bit 21 UPAddr5
EX bit 20 UPAddr4
EX bit 19 UPAddr3
EX bit 18 UPAddr2
EX bit 17 UPAddr1
EX bit 16 UPAddr0
EX bit 15 --
EX bit 14 --
EX bit 13 --
EX bit 12 --
EX bit 11 --
EX bit 10 --
EX bit 9 --
EX bit 8 LOWAddr8
EX bit 7 EX bit 6 EX bit 5 EX bit 4 EX bit 3 EX bit 2 EX bit 1 EX bit 0 LOWAddr7 LOWAddr6 LOWAddr5 LOWAddr4 LOWAddr3 LOWAddr2 LOWAddr1 LOWAddr0
The value to be set in the UPAddr8 to UPAddr0 (bits 24 to 16) is the number of the end block in the read-prohibited area of software from a third party.
The value to be set in the LOWAddr8 to LOWAddr0 (bits 8 to 0) is the number of the start block in the read-prohibited area of software from a third party.
The value to be set in the SWPR bit (bit 31) controls the prohibition of rewriting in the read-prohibited area of software
from a third party. SWPR = 0/1 (at shipment): Rewriting in the read-prohibited area is prohibited/rewriting in the read-prohibited area is enabled.
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(3) Programming of the security flags and boot area switching flag Set the value to be set in the extra area data EX bits 31 to 0 shown below in the FLW31 to FLW0 bits of the FLWH and FLWL registers.
EX bit 31 1
EX bit 30 1
EX bit 29 1
EX bit 28 1
EX bit 27 1
EX bit 26 1
EX bit 25 1
EX bit 24 1
EX bit 23 1
EX bit 22 1
EX bit 21 1
EX bit 20 1
EX bit 19 1
EX bit 18 1
EX bit 17 1
EX bit 16 1
EX bit 15 1
EX bit 14 1
EX bit 13 1
EX bit 12 WRPR
EX bit 11 1
EX bit 10 SEPR
EX bit 9 BTPR
EX bit 8 BTFLG
EX bit 7 1
EX bit 6 1
EX bit 5 1
EX bit 4 1
EX bit 3 1
EX bit 2 1
EX bit 1 1
EX bit 0 1
The value to be set in the WRPR bit (bit 12) controls the prohibition of writing in serial programming mode.
WRPR = 0/1 (at shipment): Writing in serial programming mode is prohibited/writing in serial programming mode is enabled.
The value to be set in the SEPR bit (bit 10) controls the prohibition of block erasure in serial programming mode.
SEPR = 0/1 (at shipment): Block erasure in serial programming mode is prohibited/block erasure in serial programming mode is enabled.
The value to be set in the BTPR bit (bit 9) controls the prohibition of rewriting in the boot area through serial
programming and self-programming. BTPR = 0/1 (at shipment): Rewriting in the boot area is prohibited/rewriting in the boot area is enabled.
The value to be set in the BTFLG bit (bit 8) is for control of the boot cluster to be set as the boot area when TMSPMD =
0; that is, boot swapping follows the information in the extra area (the BTFLG setting). BTFLG = 0/1 (at shipment): The boot area is boot cluster 1/the boot area is boot cluster 0.
Caution 1. When changing the value of the BTFLG bit, set all other bits to 1. Caution 2. When changing the values of security flags other than BTFLG to 0 (prohibition), read the register first
and set the BTFLG bit to the same value as was read, and set the other bits to 1. Caution 3. When setting the WRPR bit to 0 (prohibition), the WRPR bit can only be set to 1 (enabling) by
executing the chip erase command in serial programming mode. Note that if either of the prohibition settings listed below is made, executing the chip erase command in serial programming mode is not possible. · SEPR = 0 (Block erasure is prohibited.) · BTPR = 0 (Rewriting of the boot area is prohibited.)
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33.6.6.9 Procedures for checking completion of the commands for use with the flash memory sequencer in the respective areas
Completion of an activated command for use with the flash memory sequencer requires the execution of the specific procedure for checking completion described below.
· Procedure for checking the completion of commands for use with the code/data flash memory area sequencer <Procedure for checking completion> (1) Wait until the SQEND flag of the FSASTH register is set after activating a command for use with the code/data
flash memory area sequencer. (2) Clear the SQST bit of the FSSQ register after confirming that the value of the SQEND flag of the FSASTH register
is 1. (3) Wait until the SQEND flag of the FSASTH register is cleared, at which point the procedure is completed.
· Procedure for checking the completion of commands for use with the extra area sequencer <Procedure for checking completion> (1) Wait until the ESQEND flag of the FSASTH register is set after activating a command for use with the extra area
sequencer. (2) Clear the ESQST bit of the FSSE register after confirming that the value of the ESQEND flag of the FSASTH
register is 1. (3) Wait until the ESQEND flag of the FSASTH register is cleared, at which point the procedure is completed.
33.6.6.10 Procedure for forcibly terminating a command for use with the code/data flash memory area sequencer
If an abnormal state arises during the execution of a command for use with the code/data flash memory area sequencer, forcibly terminating the command is possible. Note that forcibly terminating a command for use with the extra area sequencer while it is in progress is not possible.
<Procedure for forcible termination> (1) Set the FSSTP bit of the FSSQ register to 1 between activating a command in step 1 and clearing the SQST bit of
the FSSQ register in step 2 in the section titled "Procedure for checking the completion of commands for use with the code/data flash memory area sequencer" in 33.6.6.9 Procedures for checking completion of the commands for use with the flash memory sequencer in the respective areas. This forcibly terminates the command for use with the code/data flash memory area sequencer which was activated. (2) Clear the SQST and FSSTP bits of the FSSQ register after confirming that the value of the SQEND flag of the FSASTH register is 1. (3) Wait until the SQEND flag of the FSASTH register is automatically cleared, at which point the procedure is completed.
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33.6.7 Boot swap function
If rewriting in the boot area through self-programming failed by temporary power failure or other reasons, restarting a program by resetting or overwriting is disabled due to data destruction in the boot area. The boot swap function is used to avoid this problem. Before erasing boot cluster 0Note, which is a boot program area, through self-programming, write a new boot program to boot cluster 1 in advance. When the program has been correctly written to boot cluster 1, swap this boot cluster 1 and boot cluster 0 by using the set information function of the firmware of the RL78 microcontroller, so that boot cluster 1 is used as a boot area. After that, erase or write the original boot program area, boot cluster 0. As a result, even if a power failure occurs while the area is being rewritten, the program is executed correctly because it is booted from boot cluster 1 to be swapped when the program is reset and started next.
Note
A boot cluster is a 4-Kbyte area and boot clusters 0 and 1 are swapped by the boot swap function.
Figure 33 - 27 Boot Swap Function
XXXXXH User program
Self-programming to boot cluster 1
User program
Execution of boot swapping by firmware
User program
Self-programming to boot cluster 0
User program
08000H
User program
04000H
Boot program
(boot cluster 0)
00000H
Boot
New boot program (boot cluster 1)
Boot program (boot cluster 0)
Boot
Boot program (boot cluster 0)
New boot program (boot cluster 1) Boot
New user program (boot cluster 0)
New boot program (boot cluster 1) Boot
In the example of the above figure, the boot areas before and after boot swapping are as follows. Boot cluster 0: Boot area before boot swapping Boot cluster 1: Boot area after boot swapping
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RL78/G23 Figure 33 - 28 Example of Executing Boot Swapping
CHAPTER 33 FLASH MEMORY
Block number
Boot cluster 1
Boot cluster 0
15 User program 14 User program
9 User program 8 User program 04000H 7 Boot program 6 Boot program
1 Boot program 0 Boot program 00000H
Booting from boot cluster 0
...
Erasing block 8 15 User program 14 User program
9 User program 8 7 Boot program 6 Boot program
1 Boot program 0 Boot program
Erasing block 9 15 User program 14 User program
9 8 7 Boot program 6 Boot program
1 Boot program 0 Boot program
...
Erasing block 14 15 User program 14
9 8 7 Boot program 6 Boot program
1 Boot program 0 Boot program
Writing blocks 8 to 15 15 New boot program 14 New boot program
9 New boot program 8 New boot program 7 Boot program 6 Boot program
1 Boot program 0 Boot program
Erasing block 14 15 Boot program 14
9 8 7 New boot program 6 New boot program
1 New boot program 0 New boot program
Boot swapping 15 Boot program 14 Boot program
9 Boot program 8 Boot program 04000H 7 New boot program 6 New boot program
1 New boot program 0 New boot program 00000H
Booted by boot cluster 1
Erasing block 8 15 Boot program 14 Boot program
9 Boot program 8 7 New boot program 6 New boot program
1 New boot program 0 New boot program
Erasing block 15 15 14
9 8 7 New boot program 6 New boot program
1 New boot program 0 New boot program
Writing blocks 8 to 15 15 New user program 14 New user program
9 New user program 8 New user program 04000H 7 New boot program 6 New boot program
1 New boot program 0 New boot program 00000H
Erasing block 15 15 14
9 8 7 Boot program 6 Boot program
1 Boot program 0 Boot program
Erasing block 9 15 Boot program 14 Boot program
9 8 7 New boot program 6 New boot program
1 New boot program 0 New boot program
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<R> 33.6.8 Flash shield window function
The flash shield window function is provided as one of the security functions for use with self-programming. It disables writing to and erasing of areas selected as being either inside or outside the range specified as the window. This function is only effective for self-programming. The window range can be set by specifying the start and end blocks. The window range can be set or changed during both serial programming and self-programming. Writing to and erasing of areas selected as being either inside or outside the range specified as the window are disabled during self-programming. During serial programming, however, areas selected as being both inside and outside the range specified as the window can be written and erased.
<R> Figure 33 - 29 Flash Shield Window Setting Example (Target Devices: R7F100GLG, Start Block Number in the Window Range: 04H, End Block Number in the Window Range: 06H, FSWC: 1)
Flash memory area
1FFFFH
Flash shield range
Block 3FH Block 3EH
03800H
037FFH
Block 06H
(end block in the window range)
Window range
Block 05H
Block 04H
02000H (start block in the window range)
01FFFH
Block 03H
Flash shield range
Block 02H Block 01H
00000H
Block 00H
Available methods for writing Serial programming: Yes Self-programming: No
Serial programming: Yes Self-programming: Yes
Serial programming: Yes Self-programming: No
Caution 1. If the rewrite-prohibited area of the boot cluster 0 overlaps with the flash shield window range, prohibition to rewrite the boot cluster 0 takes priority.
Caution 2. The flash shield window can only be used for the code flash memory (and is not supported for the data flash memory).
<R>
Table 33 - 13 Relationship between Flash Shield Window Function Setting/Change Methods and Commands
Programming Condition
Window Range Setting/Change Method
Command to be Executed
Block erase
Write
Self-programming
Specify the start block number (the start block number in Block erasure is only
the window range) and the end block number (the end possible either inside or
block number in the window range + 1) by the flash self- outside the window
programming code.
range.
Writing is only possible either inside or outside the window range.
Serial programming
Specify the start block number (the start block number in the window range) and the end block number (the end block number in the window range) on GUI of dedicated flash memory programmer, etc.
Block erasure is possible both inside and outside the window range.
Writing is possible both inside and outside the window range.
Remark See 33.7 Security Settings to prohibit writing/erasure during serial programming.
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CHAPTER 33 FLASH MEMORY
<R> 33.6.9 Interrupts in code flash programming mode
33.6.9.1 Overview
When an interrupt occurs, reference to the interrupt vector in the ROM proceeds, and execution branches to the interrupt processing that is allocated in the up to 64-Kbyte ROM space in accord with the address in the interrupt vector (16 bits), from which the interrupt processing is executed. However, in code flash programming mode, where the code flash memory and extra area can be rewritten, referring to the ROM is not possible. As a result, the interrupt processing cannot be executed in this way. Note that even when referring to the ROM is not possible, the interrupt processing can be executed by changing the branch destinations of the interrupts. Specifically, changing the branch destinations of all interrupts to specified addresses in the RAM enables the execution of interrupt processing from the RAM instead of by using the interrupt vector and interrupt processing in the ROM.
33.6.9.2 Operation to change the branch destinations of the interrupts
To change the branch destinations of the interrupts, set the interrupt vector change registers 1, 0 (FLSIVC1, FLSIVC0) and interrupt vector jump enable register (VECTCTRL) so that execution branches to an address in the RAM following an interrupt. This enables execution of the interrupt processing from the RAM without reference to the interrupt vector in the ROM, even when an interrupt occurs in code flash programming mode. The FLSIVC1 and FLSIVC0 registers are used to specify the branch destination address in response to interrupts which occur during rewriting of the code flash memory or extra area. Set the values of the 16 lower-order bits and 4 higherorder bits of the branch destination address in the FLSIVC0 and FLSIVC1 registers, respectively.
Settings for control of the branch destination of interrupts that occur during self-programming are as follows.
For branching to vector addresses in the ROM: VECTCTRL = 0 or FWEDIS of FLPMC = 1
For branching to a RAM address:
VECTCTRL = 1 (with FWEDIS of FLPMC = 0)
Caution 1. The user must determine the type of interrupt by checking the interrupt flags. Therefore, the interrupt flags are not automatically cleared after the VECTCTRL register has been set.
Caution 2. A changed interrupt branch destination in the ROM is not specifiable. Caution 3. The change to the interrupt branch destination made by the VECTCTRL register is only effective
during self-programming. Caution 4. Disable interrupts while changing the interrupt branch destination to an address in the RAM.
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CHAPTER 33 FLASH MEMORY
33.6.9.3 Operation to change the interrupt branch destination
To specify interrupt processing from the RAM, update the FLSIVC1, FLSIVC0, and VECTCTRL registers while the value of the FWEDIS bit of the flash programming mode control register (FLPMC) is 0. Execute the specific sequence for use with the flash memory sequencer to handle the FWEDIS bit of the FLPMC register, and set the FLSIVC1, FLSIVC0, and VECTCTRL registers. The interrupt branch destination is thus changed to an address in RAM.
(1) When changing the interrupt branch destinations to an address in RAM The following operation is for changing all interrupt branch destinations to a specified address in the RAM.
<Handling for change> · Save the setting for enabling or disabling interrupts that was in place before starting this procedure and make the
setting to disable interrupts. · Execute the specific sequence and set the FWEDIS bit of the FLPMC register to 0.
<1> Write A5H to the PFCMD register. <2> Write 00H to the FLPMC register (EEEMD = 0, FWEDIS = 0, FLSPM = 0). <3> Write FFH to the FLPMC register (inverse of 00H). <4> Write 00H to the FLPMC register (EEEMD = 0, FWEDIS = 0, FLSPM = 0). · Specify an address in RAM in the FLSIVC1 and FLSIVC0 registers. · Set the VECTCTRL register to 01H to set the RAM address as the branch destination for interrupts. · Restore the saved setting for enabling or disabling interrupts.
Caution 1. Retain the value 0 in the FWEDIS bit as long as interrupt processing from the RAM remains specified. Caution 2. Do not set the interrupt branch destination in the saddr space at addresses from FFE20H to FFEFFH. Caution 3. When instructions are being executed from the RAM area and RAM parity error resets are enabled
(RPERDIS = 0), initialize the RAM area where data access is to proceed + 10 bytes.
(2) When returning the interrupt branch destinations from the RAM address to the vectors in the ROM The following operation is for returning the interrupt branch destinations to the addresses indicated by the interrupt vectors in the ROM (default state).
<Handling for returning to the ROM interrupt vectors> · Save the setting for enabling or disabling interrupts that was in place before starting this procedure and make the
setting to disable interrupts. · Execute the specific sequence and set the FWEDIS bit of the FLPMC register to 1.
<1> Write A5H to the PFCMD register. <2> Write 08H to the FLPMC register (EEEMD = 0, FWEDIS = 1, FLSPM = 0). <3> Write F7H to the FLPMC register (inverse of 08H). <4> Write 08H to the FLPMC register (EEEMD = 0, FWEDIS = 1, FLSPM = 0). · Set the VECTCTRL register to 00H to set the vector addresses in the ROM as the interrupt branch destinations. · Restore the saved setting for enabling or disabling interrupts.
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CHAPTER 33 FLASH MEMORY
<R> 33.6.10 Example of executing the commands to rewrite the flash memory areas
33.6.10.1 Example of executing the commands to rewrite the code flash memory area
Figure 33 - 30 shows the flow of executing the commands to rewrite the code flash memory area.
Figure 33 - 30 Flow of Executing the Commands to Rewrite the Code Flash Memory Area
Start
Copy the code for rewrite processing to the RAM.
Jump to a RAM address.
(Change the interrupt branch destinations.)
This step is only required when the interrupt branch destinations are to be changed to the RAM.: · 33.6.9.3 Operation to change the interrupt branch destination
Enter the code flash programming mode.
Execute a command for use with the code/data flash memory area sequencer.
· 33.6.3.2 Procedure for entry to the code flash programming mode
· 33.6.5 Setting the operating frequency of the flash memory sequencer
· 33.6.6.4 Operations for rewriting the code flash memory area
Wait until execution of the command for use with the code/data flash memory area sequencer is completed.
Yes Is command execution to continue?
No
Enter the rewrite-disabled mode.
· 33.6.6.9 Procedures for checking completion of the commands for use with the flash memory sequencer in the respective areas
· 33.6.3.4 Procedure for entry to the rewrite-disabled mode
Jump to a ROM address.
To user processing
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CHAPTER 33 FLASH MEMORY
33.6.10.2 Example of executing the commands to rewrite the data flash memory area
Figure 33 - 31 shows the flow of executing the commands to rewrite the data flash memory area.
Figure 33 - 31 Flow of Executing the Commands to Rewrite the Data Flash Memory Area
Start
Enable the data flash memory. DFLEN = 1
Enter the data flash programming mode.
Execute a command for use with the code/data flash memory area sequencer.
Wait until execution of the command for use with the code/data flash memory area sequencer is completed.
Yes Is command execution to continue? No
Enter the rewrite-disabled mode.
· 33.6.3.3 Procedure for entry to the data flash programming mode
· 33.6.5 Setting the operating frequency of the flash memory sequencer
· 33.6.6.5 Operations for rewriting the data flash memory area
· 33.6.6.9 Procedures for checking completion of the commands for use with the flash memory sequencer in the respective areas
· Procedure for checking the completion of commands for use with the code/data flash memory area sequencer
· 33.6.3.4 Procedure for entry to the rewrite-disabled mode
To user processing
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CHAPTER 33 FLASH MEMORY
33.6.10.3 Example of executing the commands to rewrite the extra area
Figure 33 - 32 shows the flow of executing the commands to rewrite the extra area.
Figure 33 - 32 Flow of Executing the Commands to Rewrite the Extra Area
Start
Enable the data flash memory. DFLEN = 1
Enter the code flash programming mode.
· 33.6.3.2 Procedure for entry to the code flash programming mode
· 33.6.5 Setting the operating frequency of the flash memory sequencer
Execute a command for use with the extra area sequencer.
Wait until execution of the command for use with the extra area sequencer is completed.
Yes
Is command execution to continue?
No
Enter the rewrite-disabled mode.
· 33.6.6.7 Operations for rewriting the extra area
· 33.6.6.9 Procedures for checking completion of the commands for use with the flash memory sequencer in the respective areas
· Procedure for checking the completion of commands for use with the extra area sequencer
· 33.6.3.4 Procedure for entry to the rewrite-disabled mode
To user processing
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CHAPTER 33 FLASH MEMORY
<R> 33.6.11 Notes on self-programming
(1) Rewriting the code flash memory or extra area To rewrite the code flash memory or extra area, place the code or values in the RAM.
(2) Precondition for manipulating the data flash memory area Before manipulating the data flash memory area, set the DFLEN bit of the data flash control register (DFLCTL) to 1 (enabling access to the data flash memory).
(3) Execution of programs during rewriting of the flash memory The flash memory sequencer is used to control rewriting of the flash memory during self-programming. In the flash memory control modes where rewriting of the flash memory is enabled, reference to the flash memory to be manipulated is not possible.
· In code flash programming mode, reference to the code flash memory is not possible. Accordingly, in code flash programming mode, copy the user program that is to be executed from the ROM (code flash memory) and its data for reference to the RAM in advance so that the program can be executed and reference to the data in the RAM is possible.
· In data flash programming mode, reference to the data flash memory is not possible. Accordingly, in data flash programming mode, copy data that are for reference to the RAM in advance so that reference to the data in the RAM is possible.
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CHAPTER 33 FLASH MEMORY
33.7
Security Settings
The RL78 microcontroller supports a security function that prohibits rewriting the user program written to the internal flash memory, so that the program cannot be changed by an unauthorized person. The operations shown below can be performed using the security set command.
· Disabling block erasure Execution of the block erase command for a specific block in the code flash memory is prohibited during serial programming. However, blocks can be erased by means of self-programming.
· Disabling writing Execution of the write command for entire blocks in the code flash memory is prohibited during serial programming. However, blocks can be written by means of self-programming. After the setting to prohibit writing has been made, releasing the setting by the security release command is enabled by a reset.
· Disabling rewriting boot cluster 0 Execution of the block erase command and write command on boot cluster 0 (00000H to 00FFFH) in the code flash memory is prohibited by this setting.
The block erase, write commands, and rewriting boot cluster 0 are enabled by the default setting when the flash memory is shipped. Security can be set by serial programming and self-programming. Each security setting can be used in combination. Table 33 - 14 shows the relationship between the erase and write commands when the RL78 microcontroller security function is enabled.
Caution The security function of the dedicated flash programmer does not support self-programming.
Remark
To prohibit writing and erasure during self-programming, use the flash shield window function (see 33.6.8 Flash shield window function for detail).
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Table 33 - 14 Relationship between Enabling the Security Function and Commands
(1) During serial programming
Valid Security Prohibition of block erasure
Block Erase Blocks cannot be erased.
Command to be Executed Write
Data can be written.Note
Prohibition of writing
Blocks can be erased.
Data cannot be written.
Prohibition of rewriting boot cluster 0 Boot cluster 0 cannot be erased.
Boot cluster 0 cannot be written.
Note
Confirm that no data have been written to the write area. If data in the area has not been erased, do not attempt further writing of data because data cannot be erased after the setting to prohibit block erasure has been made.
(2) During self-programming
Valid Security
Block Erase
Command to be Executed
Write
Prohibition of block erasure
Blocks can be erased.
Data can be written.
Prohibition of writing
Prohibition of rewriting boot cluster 0 Boot cluster 0 cannot be erased.
Boot cluster 0 cannot be written.
Remark To prohibit writing and erasure during self-programming, use the flash shield window function (see 33.6.8 Flash shield window function for detail).
Table 33 - 15 Setting Security in Each Programming Mode
(1) During serial programming
Security
Security Setting
Disabling the Security Setting
Prohibition of block erasure Prohibition of writing
Set via GUI of dedicated flash memory programmer, etc.
Disabling the setting is not possible.
Set via GUI of dedicated flash memory programmer, etc.
Prohibition of rewriting boot cluster 0
Disabling the setting is not possible.
Caution The setting to prohibit writing can only be released when the settings to prohibit erasing blocks and rewriting boot cluster 0 are not made and the code and data flash memory areas are blank.
(2) During self-programming
Security Prohibition of block erasure Prohibition of writing
Security Setting Set by using flash self-programming code.
Prohibition of rewriting boot cluster 0
Disabling the Security Setting
Disabling the setting is not possible.
Disabling the setting is not possible during self-programming (set via GUI of dedicated flash memory programmer, etc. during serial programming).
Disabling the setting is not possible.
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CHAPTER 33 FLASH MEMORY
33.8
Data Flash Memory
33.8.1 Overview of the data flash memory
An overview of the data flash memory is provided below.
· The user program can rewrite the data flash memory by using the Renesas flash driver. For details, refer to RL78 Family Renesas Flash Driver RL78 Type01 User's Manual (R20UT4830EJ).
· The data flash memory can also be rewritten to through serial programming using the dedicated flash memory programmer or an external device.
· The data flash memory can be erased in 1-block (256-byte) units. · The data flash memory can be accessed only in 8-bit units. · The data flash memory can be directly read by CPU instructions. · Instructions can be executed from the code flash memory while rewriting the data flash memory (that is,
background operation (BGO) is supported). · The data flash memory area is exclusively to be used for data, so executing instructions from the data flash
memory is prohibited. · Accessing the data flash memory is prohibited while rewriting the code flash memory (during self-programming). · Manipulating the DFLCTL register is prohibited while rewriting the data flash memory. · Transition to the STOP mode is prohibited while rewriting the data flash memory.
Caution 1. The data flash memory is stopped after a reset is canceled. The data flash control register (DFLCTL) must be set up in order to use the data flash memory.
Caution 2. The high-speed on-chip oscillator should be kept operating during rewriting of the data flash area. If it is stopped, it should be made to operate again (HIOSTOP = 0), and the Renesas flash driver should be re-executed after 5 µs have elapsed.
Remark For rewriting the code flash memory via a user program, see 33.6 Self-Programming.
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CHAPTER 33 FLASH MEMORY
33.8.2 Procedure for accessing the data flash memory
The data flash memory is stopped after release from a reset. For access to this memory, follow the procedure below to make the required initial setting.
<1> Set 1 in bit 0 (DFLEN) of the data flash control register (DFLCTL). <2> Wait for the setup time by using a software timer, etc.
The setup time depends on the operating mode of the flash memory in terms of the main clock selection. <Setup time for each operating mode of the flash memory>
· HS (high-speed main) mode: 250 ns · LS (low-speed main) mode: 250 ns · LP (low-power main) mode: 0 ns <3> After the wait, the data flash memory can be accessed.
Caution 1. Accessing the data flash memory is prohibited during the setup time. Caution 2. Transition to the STOP mode is prohibited during the setup time. To enter the STOP mode during the
setup time, clear DFLEN to 0 and then execute the STOP instruction. Caution 3. The high-speed on-chip oscillator should be kept operating during rewriting of the data flash area. If it
is stopped, it should be made to operate again (HIOSTOP = 0), and the Renesas flash driver should be re-executed after 5 µs have elapsed.
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CHAPTER 34 ON-CHIP DEBUGGING
CHAPTER 34 ON-CHIP DEBUGGING
34.1
Connection between the E2 or E2 Lite On-chip Debugging Emulator and
RL78/G23
On-chip debugging is handled by connecting the RL78 microcontroller and host machine through the E2 or E2 Lite onchip debugging emulator. Pins VDD, RESET, TOOL0, and VSS are used for connection to the emulator. Serial communications are handled through the TOOL0 pin as a single-line UART connection.
Caution
RL78 microcontrollers have on-chip debugging functionality for use in the development and evaluation of user systems. Do not use on-chip debugging with products designated as part of mass production, because using this function may cause the guaranteed number of times the flash memory is rewriting to be exceeded, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when on-chip debugging is used with products designated as part of mass production.
Figure 34 - 1 Example of Connection between the E2 or E2 Lite On-Chip Debugging Emulator and RL78/G23
E2 or E2 Lite target connector
VDD
EMVDD
GND GND GND
VDD EVDD
TOOL0 Reset_out Reset_out
Reset_in
10 k Note 1
VDD EVDD
RL78/G23 VDD
EVDD0, EVDD1
EVDD 1 k
VDD 1 k Note 2
VSS, EVSS0, EVSS1
TOOL0 RESET Reset circuit Reset signal
Note 1. Note 2.
The connection shown as a broken line is not required for serial programming. If the reset circuit on the target system does not have a buffer so the reset signal is only generated through resistors and capacitors, this pull-up resistor is not required.
Caution This circuit diagram is an example where the reset signal is output from an N-channel open-drain buffer with an output resistance no greater than 100 .
Remark
Pins EVDD0, EVDD1, EVSS0, and EVSS1 are not present in some products. In such cases, use the VDD and VSS pins as the alternative.
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CHAPTER 34 ON-CHIP DEBUGGING
34.2
Connection between the External Device that Incorporates UART and RL78/G23
On-board communications between an external device (a microcontroller or ASIC) that is connected to the RL78 microcontroller via a UART and the host machine is possible. Pins VDD, RESET, TOOL0, VSS, TOOLTxD, and TOOLRxD are used for the communications. Communications between the external device and the RL78 microcontroller is established by serial communication using the TOOLTxD and TOOLRxD pins via the dedicated UART of the RL78 microcontroller.
VDD
GND RESETOUT
External device (such as microcontroller
and ASIC )
RxD TxD PORT
VD
D
/EV
N ot e D D0
1
VS
S/EV
S
N ot e S0
1/REGCN
ot
e
2
RESET
TOOLTxD TOOLRxDNote 3
RL78 microcontroller
TOOL0
Note 1. Note 2. Note 3.
This pin is only present in the 64-pin, 80-pin, 100-pin and 128-pin products. Connect the REGC pin to the ground via a capacitor (0.47 to 1 µF). Set the port pin with which TOOLRxD is multiplexed as an input.
34.3
Security ID Codes for On-Chip Debugging
To protect against third parties reading the contents of memory, the RL78 microcontroller has on-chip debugging control bits in the flash memory at 000C3H (see CHAPTER 32 OPTION BYTES), and an area to hold the security ID code for on-chip debugging in the range from 000C4H to 000CDH. When boot swapping is to be used in self-programming, 000C3H and the range from 000C4H to 000CDH are respectively replaced with 040C3H and the range from 040C4H to 040CDH. Therefore, set the same value as the settings in 000C3H and the range from 000C4H to 000CDH in 040C3H and the range from 040C4H to 040CDH.
Table 34 - 1 On-Chip Debug Security ID
Address
Security ID Code for On-Chip Debugging
000C4H to 000CDH
Any 10-byte ID code Note
040C4H to 040CDH
Note
The setting FFFFFFFFFFFFFFFFFFFFH is not allowed.
34.4
Allocation of Memory Spaces to User Resources
Allocation of memory spaces to user resources is required before communications between the RL78 microcontroller and E2 or E2 Lite on-chip debugging emulator, and on-chip debugging, can proceed. If you are using an assembler or compiler from Renesas Electronics, you can use linker options to allocate the memory spaces.
(1) Allocation of memory spaces to the user program The shaded areas in Figure 34 - 2 are reserved for the monitor program for debugging, and user programs and data cannot be allocated to these areas. When using on-chip debugging, ensure that nothing is allocated to these areas so that they can be secured for on-chip debugging. Also ensure that the contents of these areas are not modified by the user program.
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CHAPTER 34 ON-CHIP DEBUGGING
Figure 34 - 2 Memory Spaces Allocated for Use by the Monitor Program for Debugging
Code flash memory
Note 1
Usage prohibited (512 bytes or
256 bytes Note 2)
Internal RAM SFR area
Stack area for debugging (4 bytes) Note 4
Internal RAM area
Code flash area
Mirror area
: Area used for on-chip debugging
000D8H
000CEH
000C4H 000C3H
00002H 00000H
Debug monitor area (10 bytes)
Security ID area (10 bytes)
Debug monitor area (2 bytes) Note 3
On-chip debug option byte area (1 byte)
Note 1. The address depends on the products as shown below. Products
R7F100GxF (x = A to C, E to G, J, L) R7F100GxG (x = A to C, E to G, J, L, M, P) R7F100GxH (x = A to C, E to G, J, L, M, P) R7F100GxJ (x = A to C, E to G, J, L, M, P, S) R7F100GxK (x = F, G, J, L, M, P, S) R7F100GxL (x = F, G, J, L, M, P, S) R7F100GxN (x = F, G, J, L, M, P, S)
Address of Note 1 17FFFH 1FFFFH 2FFFFH 3FFFFH 5FFFFH 7FFFFH BFFFFH
Note 2.
Note 3. Note 4.
When the realtime RAM monitor (RRM) and dynamic memory modification (DMM) are not to be used, the size of this area is 256 bytes. During debugging, the reset vector is relocated to the address of the monitor program. Since this area is allocated immediately below the portion of the main stack area that is currently in use, the address range of this area depends on the amount of the stack in use other than for debugging. Accordingly, four additional bytes are required for the entire stack area. In the case of self-programming, this is a 12-byte area, so 12 additional bytes are required.
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CHAPTER 35 BCD CORRECTION CIRCUIT
CHAPTER 35 BCD CORRECTION CIRCUIT
35.1 BCD Correction Circuit Function
The result of addition/subtraction of the BCD (binary-coded decimal) code and BCD code can be obtained as BCD code with this circuit. The decimal correction operation result is obtained by performing addition/subtraction having the A register as the operand and then adding/subtracting the BCD correction result register (BCDADJ).
35.2 Register to Control the BCD Correction Circuit
The following register is used to control the BCD correction circuit.
· BCD correction result register (BCDADJ)
35.2.1 BCD correction result register (BCDADJ)
The BCDADJ register stores correction values for obtaining the add/subtract result as BCD code through add/subtract instructions using the A register as the operand. The value read from the BCDADJ register varies depending on the value of the A register when it is read and those of the CY and AC flags. The BCDADJ register is read by an 8-bit memory manipulation instruction. Reset input sets this register to undefined.
Figure 35 - 1 Format of BCD Correction Result Register (BCDADJ)
Address: After reset: R/W:
F00FEH Undefined R
Symbol
7
6
5
4
3
2
1
0
BCDADJ
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CHAPTER 35 BCD CORRECTION CIRCUIT
35.3 BCD Correction Circuit Operation
The basic operation of the BCD correction circuit is as follows.
(1) Addition: Obtaining the result of the binary addition of BCD values and BCD values as a BCD value <1> The BCD code value to which addition is performed is stored in the A register. <2> By adding the value of the A register and the second operand (value of one more BCD code to be added) as are in binary, the binary operation result is stored in the A register and the correction value is stored in the BCD correction result register (BCDADJ). <3> Decimal correction is performed by adding in binary the values of the A register (addition result in binary) and the BCDADJ register (correction value), and the correction result is stored in the A register and CY flag.
Caution
The value read from the BCDADJ register varies depending on the value of the A register when it is read and those of the CY and AC flags. Therefore, execute the instruction <3> after the instruction <2> instead of executing any other instructions. To perform BCD correction in the interrupt enabled state, saving and restoring the A register is required within the interrupt function. PSW (CY flag and AC flag) is restored by the RETI instruction.
Examples are shown below.
Example 1: 99 + 89 = 188
MOV ADD ADD
Instruction A, #99H ; <1> A, #89H ; <2> A, !BCDADJ ; <3>
A Register 99H 22H 88H
CY Flag -- 1 1
AC Flag -- 1 0
BCDADJ Register -- 66H --
Example 2: 85 + 15 = 100
MOV ADD ADD
Instruction A, #85H ; <1> A, #15H ; <2> A, !BCDADJ ; <3>
A Register 85H 9AH 00H
CY Flag -- 0 1
AC Flag -- 0 1
BCDADJ Register -- 66H --
Example 3: 80 + 80 = 160
MOV ADD ADD
Instruction A, #80H ; <1> A, #80H ; <2> A, !BCDADJ ; <3>
A Register 80H 00H 60H
CY Flag -- 1 1
AC Flag -- 0 0
BCDADJ Register -- 60H --
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CHAPTER 35 BCD CORRECTION CIRCUIT
(2) Subtraction: Obtaining the result of the binary subtraction of BCD values and BCD values as a BCD value <1> The BCD code value from which subtraction is performed is stored in the A register. <2> By subtracting the value of the second operand (value of BCD code to be subtracted) from the A register as is in binary, the calculation result in binary is stored in the A register, and the correction value is stored in the BCD correction result register (BCDADJ). <3> Decimal correction is performed by subtracting the value of the BCDADJ register (correction value) from the A register (subtraction result in binary) in binary, and the correction result is stored in the A register and CY flag.
Caution
The value read from the BCDADJ register varies depending on the value of the A register when it is read and those of the CY and AC flags. Therefore, execute the instruction <3> after the instruction <2> instead of executing any other instructions. To perform BCD correction in the interrupt enabled state, saving and restoring the A register is required within the interrupt function. PSW (CY flag and AC flag) is restored by the RETI instruction.
An example is shown below.
Example: 91 - 52 = 39
MOV SUB SUB
Instruction A, #91H ; <1> A, #52H ; <2> A, !BCDADJ ; <3>
A Register 91H 3FH 39H
CY Flag -- 0 0
AC Flag -- 1 0
BCDADJ Register -- 06H --
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CHAPTER 36 INSTRUCTION SET
CHAPTER 36 INSTRUCTION SET
This chapter lists the instructions in the RL78 microcontroller instruction set. For details of each operation and operation code, refer to the separate document RL78 Family User's Manual Software (R01US0015).
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CHAPTER 36 INSTRUCTION SET
36.1
Conventions Used in Operation List
36.1.1 Operand identifiers and specification methods
Operands are described in the "Operand" column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more description methods, select one of them. Alphabetic letters in capitals and the symbols, #, !, !!, $, $!, [ ], and ES: are keywords and are described as they are. Each symbol has the following meaning.
· #: Immediate data specification · !: 16-bit absolute address specification · !!: 20-bit absolute address specification · $: 8-bit relative address specification · $!: 16-bit relative address specification · [ ]: Indirect address specification · ES: Extension address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe the #, !, !!, $, $!, [ ], and ES: symbols. For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for description.
Table 36 - 1 Operand Identifiers and Specification Methods
Identifier
Description Method
r rp sfr sfrp
saddr saddrp
addr20 addr16 addr5
word byte bit RBn
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special-function register symbol (SFR symbol) FFF00H to FFFFFH Special-function register symbols (16-bit manipulatable SFR symbol. Even addresses only Note) FFF00H to FFFFFH
FFE20H to FFF1FH Immediate data or labels FFE20H to FF1FH Immediate data or labels (even addresses only Note)
00000H to FFFFFH Immediate data or labels 0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions Note) 0080H to 00BFH Immediate data or labels (even addresses only)
16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label
RB0 to RB3
Note
Bit 0 = 0 when an odd address is specified.
Remark
The special function registers can be described to operand sfr as symbols. See Table 3 - 7 List of Special Function Registers (SFRs) for the symbols of the special function registers. The extended special function registers can be described to operand !addr16 as symbols. See Table 3 - 8 List of Extended Special Function Registers (2nd SFRs) for the symbols of the extended special function registers.
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36.1.2 Description of operation column
The operation when the instruction is executed is shown in the "Operation" column using the following symbols.
Table 36 - 2 Symbols in "Operation" Column
Symbol
Function
A
A register; 8-bit accumulator
X
X register
B
B register
C
C register
D
D register
E
E register
H
H register
L
L register
ES
ES register
CS
CS register
AX
AX register pair; 16-bit accumulator
BC
BC register pair
DE
DE register pair
HL
HL register pair
PC
Program counter
SP
Stack pointer
PSW
Program status word
CY
Carry flag
AC
Auxiliary carry flag
Z
Zero flag
RBS
Register bank select flag
IE
Interrupt request enable flag
()
Memory contents indicated by address or register contents in parentheses
XH, XL XS, XH, XL
16-bit registers: XH = higher 8 bits, XL = lower 8 bits 20-bit registers: XS = (bits 19 to 16), XH = (bits 15 to 8), XL = (bits 7 to 0)
Logical product (AND)
Logical sum (OR)
Exclusive logical sum (exclusive OR)
--
Inverted data
addr5
16-bit immediate data (even addresses only in 0080H to 00BFH)
addr16
16-bit immediate data
addr20
20-bit immediate data
jdisp8
Signed 8-bit data (displacement value)
jdisp16
Signed 16-bit data (displacement value)
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36.1.3 Description of flag operation column
The change of the flag value when the instruction is executed is shown in the "Flag" column using the following symbols.
Table 36 - 3 Symbols in "Flag" Column
Symbol
(Blank) 0 1 × R
Unchanged Cleared to 0 Set to 1 Set/cleared according to the result Previously saved value is restored
Change of Flag Value
36.1.4 PREFIX instruction
Instructions with "ES:" have a PREFIX operation code as a prefix to extend the accessible data area to the 1 MB space (00000H to FFFFFH), by adding the ES register value to the 64 KB space from F0000H to FFFFFH. When a PREFIX operation code is attached as a prefix to the target instruction, only one instruction immediately after the PREFIX operation code is executed as the addresses with the ES register value added. A interrupt and DTC transfer are not acknowledged between a PREFIX instruction code and the instruction immediately after.
Table 36 - 4 Use Example of PREFIX Operation Code
Instruction
MOV !addr16, #byte MOV ES:!addr16, #byte MOV A, [HL] MOV A, ES: [HL]
1 CFH 11H 8BH 11H
2
CFH -- 8BH
!addr16
Opcode 3
-- --
!addr16
4 #byte
-- --
Caution Set the ES register value with MOV ES, A, etc., before executing the PREFIX instruction.
5 -- #byte -- --
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36.2
Operation List
Table 36 - 5 Operation List (1/18)
Instruction Mnemonic Group
Operands
8-bit data transfer
MOV
r, #byte
PSW, #byte
CS, #byte
ES, #byte
!addr16, #byte
ES:!addr16, #byte
saddr, #byte
sfr, #byte
[DE+byte], #byte
ES:[DE+byte], #byte
[HL+byte], #byte
ES:[HL+byte], #byte
[SP+byte], #byte
word[B], #byte
ES:word[B], #byte
word[C], #byte
ES:word[C], #byte
word[BC], #byte
ES:word[BC], #byte
A, r
Note 3
r, A
Note 3
A, PSW
PSW, A
A, CS
CS, A
A, ES
ES, A
A, !addr16
A, ES:!addr16
!addr16, A
ES:!addr16, A
A, saddr
saddr, A
Clocks Bytes
Note 1 Note 2
Operation
2
1
-- r byte
3
3
-- PSW byte
3
1
-- CS byte
2
1
-- ES byte
4
1
-- (addr16) byte
5
2
-- (ES, addr16) byte
3
1
-- (saddr) byte
3
1
-- sfr byte
3
1
-- (DE + byte) byte
4
2
-- ((ES, DE) + byte) byte
3
1
-- (HL + byte) byte
4
2
-- ((ES, HL) + byte) byte
3
1
-- (SP + byte) byte
4
1
-- (B + word) byte
5
2
-- ((ES, B) + word) byte
4
1
-- (C+word) byte
5
2
-- ((ES, C) + word) byte
4
1
-- (BC+word) byte
5
2
-- ((ES, BC) + word) byte
1
1
-- Ar
1
1
-- rA
2
1
-- A PSW
2
3
-- PSW A
2
1
-- A CS
2
1
-- CS A
2
1
-- A ES
2
1
-- ES A
3
1
4 A (addr16)
4
2
5 A (ES, addr16)
3
1
-- (addr16) A
4
2
-- (ES, addr16) A
2
1
-- A (saddr)
2
1
-- (saddr) A
Flag Z AC CY ×××
×××
Note 1. Note 2. Note 3.
Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. Number of CPU clocks (fCLK) when the code flash memory is accessed, or when the data flash memory is accessed by an 8-bit instruction. Except r = A
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
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Table 36 - 6 Operation List (2/18)
Instruction Mnemonic Group
Operands
8-bit data transfer
MOV
A, sfr sfr, A A, [DE] [DE], A A, ES:[DE] ES:[DE], A A, [HL] [HL], A A, ES:[HL] ES:[HL], A A, [DE+byte] [DE+byte], A A, ES:[DE+byte] ES:[DE+byte], A A, [HL+byte] [HL+byte], A A, ES:[HL+byte] ES:[HL+byte], A A, [SP+byte] [SP+byte], A A, word[B] word[B], A A, ES:word[B] ES:word[B], A A, word[C] word[C], A A, ES:word[C] ES:word[C], A A, word[BC] word[BC], A A, ES:word[BC] ES:word[BC], A
Clocks Bytes
Note 1 Note 2
Operation
2
1
-- A sfr
2
1
-- sfr A
1
1
4 A (DE)
1
1
-- (DE) A
2
2
5 A (ES, DE)
2
2
-- (ES, DE) A
1
1
4 A (HL)
1
1
-- (HL) A
2
2
5 A (ES, HL)
2
2
-- (ES, HL) A
2
1
4 A (DE + byte)
2
1
-- (DE + byte) A
3
2
5 A ((ES, DE) + byte)
3
2
-- ((ES, DE) + byte A
2
1
4 A (HL + byte)
2
1
-- (HL + byte) A
3
2
5 A ((ES, HL) + byte)
3
2
-- ((ES, HL) + byte) A
2
1
-- A (SP + byte)
2
1
-- (SP + byte) A
3
1
4 A (B + word)
3
1
-- (B + word) A
4
2
5 A ((ES, B) + word)
4
2
-- ((ES, B) + word) A
3
1
4 A (C + word)
3
1
-- (C + word) A
4
2
5 A ((ES, C) + word)
4
2
-- ((ES, C) + word) A
3
1
4 A (BC + word)
3
1
-- (BC + word) A
4
2
5 A ((ES, BC) + word)
4
2
-- ((ES, BC) + word) A
Flag Z AC CY
Note 1. Note 2.
Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. Number of CPU clocks (fCLK) when the code flash memory is accessed, or when the data flash memory is accessed by an 8-bit instruction.
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
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Table 36 - 7 Operation List (3/18)
Instruction Mnemonic Group
Operands
8-bit data transfer
MOV
XCH
A, [HL+B]
[HL+B], A
A, ES:[HL+B]
ES:[HL+B], A
A, [HL+C]
[HL+C], A
A, ES:[HL+C]
ES:[HL+C], A
X, !addr16
X, ES:!addr16
X, saddr
B, !addr16
B, ES:!addr16
B, saddr
C, !addr16
C, ES:!addr16
C, saddr
ES, saddr
A, r
Note 3
A, !addr16 A, ES:!addr16 A, saddr A, sfr A, [DE] A, ES:[DE] A, [HL] A, ES:[HL] A, [DE+byte] A, ES:[DE+byte] A, [HL+byte] A, ES:[HL+byte]
Bytes
Clocks Note 1 Note 2
Operation
2
1
4 A (HL + B)
2
1
-- (HL + B) A
3
2
5 A ((ES, HL) + B)
3
2
-- ((ES, HL) + B) A
2
1
4 A (HL + C)
2
1
-- (HL + C) A
3
2
5 A ((ES, HL) + C)
3
2
-- ((ES, HL) + C) A
3
1
4 X (addr16)
4
2
5 X (ES, addr16)
2
1
-- X (saddr)
3
1
4 B (addr16)
4
2
5 B (ES, addr16)
2
1
-- B (saddr)
3
1
4 C (addr16)
4
2
5 C (ES, addr16)
2
1
-- C (saddr)
3
1
-- ES (saddr)
1 (r = X)
2 (other
1
than r = X)
A r --
4
2
-- A (addr16)
5
3
-- A (ES, addr16)
3
2
-- A (saddr)
3
2
-- A sfr
2
2
-- A (DE)
3
3
-- A (ES, DE)
2
2
-- A (HL)
3
3
-- A (ES, HL)
3
2
-- A (DE + byte)
4
3
-- A ((ES, DE) + byte)
3
2
-- A (HL + byte)
4
3
-- A ((ES, HL) + byte)
Flag Z AC CY
Note 1. Note 2. Note 3.
Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. Number of CPU clocks (fCLK) when the code flash memory is accessed, or when the data flash memory is accessed by an 8-bit instruction. Except r = A
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
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Table 36 - 8 Operation List (4/18)
Instruction Mnemonic Group
Operands
8-bit data transfer
XCH
ONEB
CLRB
MOVS
16-bit data MOVW transfer
A, [HL+B] A, ES:[HL+B] A, [HL+C] A, ES:[HL+C] A X B C !addr16 ES:!addr16 saddr A X B C !addr16 ES:!addr16 saddr [HL+byte], X ES:[HL+byte], X rp, #word saddrp, #word sfrp, #word AX, rp Note 3 rp, AX Note 3 AX, !addr16 !addr16, AX AX, ES:!addr16 ES:!addr16, AX AX, saddrp saddrp, AX AX, sfrp sfrp, AX
Clocks Bytes
Note 1 Note 2
Operation
2
2
-- A (HL + B)
3
3
-- A ((ES, HL) + B)
2
2
-- A (HL + C)
3
3
-- A ((ES, HL) + C)
1
1
-- A 01H
1
1
-- X 01H
1
1
-- B 01H
1
1
-- C 01H
3
1
-- (addr16) 01H
4
2
-- (ES, addr16) 01H
2
1
-- (saddr) 01H
1
1
-- A 00H
1
1
-- X 00H
1
1
-- B 00H
1
1
-- C 00H
3
1
-- (addr16) 00H
4
2
-- (ES,addr16) 00H
2
1
-- (saddr) 00H
3
1
-- (HL + byte) X
4
2
-- (ES, HL + byte) X
3
1
-- rp word
4
1
-- (saddrp) word
4
1
-- sfrp word
1
1
-- AX rp
1
1
-- rp AX
3
1
4 AX (addr16)
3
1
-- (addr16) AX
4
2
5 AX (ES, addr16)
4
2
-- (ES, addr16) AX
2
1
-- AX (saddrp)
2
1
-- (saddrp) AX
2
1
-- AX sfrp
2
1
-- sfrp AX
Flag Z AC CY
×
×
×
×
Note 1. Note 2. Note 3.
Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. Number of CPU clocks (fCLK) when the code flash memory is accessed, or when the data flash memory is accessed by an 8-bit instruction. Except rp = AX
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
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Table 36 - 9 Operation List (5/18)
Instruction Mnemonic Group
Operands
16-bit data MOVW transfer
AX, [DE] [DE], AX AX, ES:[DE] ES:[DE], AX AX, [HL] [HL], AX AX, ES:[HL] ES:[HL], AX AX, [DE+byte] [DE+byte], AX AX, ES:[DE+byte] ES:[DE+byte], AX AX, [HL+byte] [HL+byte], AX AX, ES:[HL+byte] ES:[HL+byte], AX AX, [SP+byte] [SP+byte], AX AX, word[B] word[B], AX AX, ES:word[B] ES:word[B], AX AX, word[C] word[C], AX AX, ES:word[C] ES:word[C], AX AX, word[BC] word[BC], AX AX, ES:word[BC] ES:word[BC], AX
Clocks Bytes
Note 1 Note 2
Operation
1
1
4 AX (DE)
1
1
-- (DE) AX
2
2
5 AX (ES, DE)
2
2
-- (ES, DE) AX
1
1
4 AX (HL)
1
1
-- (HL) AX
2
2
5 AX (ES, HL)
2
2
-- (ES, HL) AX
2
1
4 AX (DE + byte)
2
1
-- (DE + byte) AX
3
2
5 AX ((ES, DE) + byte)
3
2
-- ((ES, DE) + byte) AX
2
1
4 AX (HL + byte)
2
1
-- (HL + byte) AX
3
2
5 AX ((ES, HL) + byte)
3
2
-- ((ES, HL) + byte) AX
2
1
-- AX (SP + byte)
2
1
-- (SP + byte) AX
3
1
4 AX (B + word)
3
1
-- (B + word) AX
4
2
5 AX ((ES, B) + word)
4
2
-- ((ES, B) + word) AX
3
1
4 AX (C + word)
3
1
-- (C + word) AX
4
2
5 AX ((ES, C) + word)
4
2
-- ((ES, C) + word) AX
3
1
4 AX (BC + word)
3
1
-- (BC + word) AX
4
2
5 AX ((ES, BC) + word)
4
2
-- ((ES, BC) + word) AX
Flag Z AC CY
Note 1. Note 2.
Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. Number of CPU clocks (fCLK) when the code flash memory is accessed, or when the data flash memory is accessed by an 8-bit instruction.
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
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Table 36 - 10 Operation List (6/18)
Instruction Mnemonic Group
Operands
16-bit data MOVW transfer
XCHW ONEW
BC, !addr16 BC, ES:!addr16 DE, !addr16 DE, ES:!addr16 HL, !addr16 HL, ES:!addr16 BC, saddrp DE, saddrp HL, saddrp AX, rp Note 3 AX
Clocks Bytes
Note 1 Note 2
Operation
3
1
4 BC (addr16)
4
2
5 BC (ES, addr16)
3
1
4 DE (addr16)
4
2
5 DE (ES, addr16)
3
1
4 HL (addr16)
4
2
5 HL (ES, addr16)
2
1
-- BC (saddrp)
2
1
-- DE (saddrp)
2
1
-- HL (saddrp)
1
1
-- AX rp
1
1
-- AX 0001H
Flag Z AC CY
BC
1
1
-- BC 0001H
CLRW
AX
1
1
-- AX 0000H
BC
1
1
-- BC 0000H
8-bit operation
ADD
A, #byte
saddr, #byte
A, r
Note 4
r, A
A, !addr16
A, ES:!addr16
A, saddr
A, [HL]
A, ES:[HL]
A, [HL+byte]
A, ES:[HL+byte]
A, [HL+B]
A, ES:[HL+B]
A, [HL+C]
A, ES:[HL+C]
2
1
-- A, CY A + byte
3
2
-- (saddr), CY (saddr) + byte
2
1
-- A, CY A + r
2
1
-- r, CY r + A
3
1
4 A, CY A + (addr16)
4
2
5 A, CY A + (ES, addr16)
2
1
-- A, C A + (saddr)
1
1
4 A, CY A + (HL)
2
2
5 A,CY A + (ES, HL)
2
1
4 A, CY A + (HL + byte)
3
2
5 A,CY A + ((ES, HL) + byte)
2
1
4 A, CY A + (HL + B)
3
2
5 A,CY A + ((ES, HL) + B)
2
1
4 A, CY A + (HL + C)
3
2
5 A,CY A + ((ES, HL) + C)
××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ×××
Note 1.
Note 2.
Note 3. Note 4.
Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. Number of CPU clocks (fCLK) when the code flash memory is accessed, or when the data flash memory is accessed by an 8-bit instruction. Except rp = AX Except r = A
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
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Table 36 - 11 Operation List (7/18)
Instruction Mnemonic Group
Operands
8-bit operation
ADDC
SUB
A, #byte
saddr, #byte
A, rv Note 3
r, A
A, !addr16
A, ES:!addr16
A, saddr
A, [HL]
A, ES:[HL]
A, [HL+byte]
A, ES:[HL+byte]
A, [HL+B]
A, ES:[HL+B]
A, [HL+C]
A, ES:[HL+C]
A, #byte
saddr, #byte
A, r
Note 3
r, A
A, !addr16
A, ES:!addr16
A, saddr
A, [HL]
A, ES:[HL]
A, [HL+byte]
A, ES:[HL+byte]
A, [HL+B]
A, ES:[HL+B]
A, [HL+C]
A, ES:[HL+C]
Clocks Bytes
Note 1 Note 2
Operation
2
1
-- A, CY A + byte + CY
3
2
-- (saddr), CY (saddr) + byte + CY
2
1
-- A, CY A + r + CY
2
1
-- r, CY r + A + CY
3
1
4 A, CY A + (addr16) + CY
4
2
5 A, CY A + (ES, addr16) + CY
2
1
-- A, CY A + (saddr) + CY
1
1
4 A, CY A + (HL) + CY
2
2
5 A,CY A + (ES, HL) + CY
2
1
4 A, CY A + (HL + byte) + CY
3
2
5 A,CY A + ((ES, HL) + byte) + CY
2
1
4 A, CY A + (HL + B) + CY
3
2
5 A,CY A + ((ES, HL) + B) + CY
2
1
4 A, CY A + (HL + C) + CY
3
2
5 A,CY A + ((ES, HL) + C) + CY
2
1
-- A, CY A - byte
3
2
-- (saddr), CY (saddr) - byte
2
1
-- A, CY A - r
2
1
-- r, CY r - A
3
1
4 A, CY A - (addr16)
4
2
5 A, CY A - (ES, addr16)
2
1
-- A, CY A - (saddr)
1
1
4 A, CY A - (HL)
2
2
5 A,CY A - (ES, HL)
2
1
4 A, CY A - (HL + byte)
3
2
5 A,CY A - ((ES, HL) + byte)
2
1
4 A, CY A - (HL + B)
3
2
5 A,CY A - ((ES, HL) + B)
2
1
4 A, CY A - (HL + C)
3
2
5 A,CY A - ((ES, HL) + C)
Flag Z AC CY ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ×××
Note 1. Note 2. Note 3.
Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. Number of CPU clocks (fCLK) when the code flash memory is accessed, or when the data flash memory is accessed by an 8-bit instruction. Except r = A
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
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Table 36 - 12 Operation List (8/18)
Instruction Mnemonic Group
Operands
8-bit operation
SUBC
AND
A, #byte
saddr, #byte
A, r
Note 3
r, A
A, !addr16
A, ES:!addr16
A, saddr
A, [HL]
A, ES:[HL]
A, [HL+byte]
A, ES:[HL+byte]
A, [HL+B]
A, ES:[HL+B]
A, [HL+C]
A, ES:[HL+C]
A, #byte
saddr, #byte
A, r
Note 3
r, A
A, !addr16
A, ES:!addr16
A, saddr
A, [HL]
A, ES:[HL]
A, [HL+byte]
A, ES:[HL+byte]
A, [HL+B]
A, ES:[HL+B]
A, [HL+C]
A, ES:[HL+C]
Clocks Bytes
Note 1 Note 2
Operation
2
1
-- A, CY A - byte - CY
3
2
-- (saddr), CY (saddr) - byte - CY
2
1
-- A, CY A - r - CY
2
1
-- r, CY r - A - CY
3
1
4 A, CY A - (addr16) - CY
4
2
5 A, CY A - (ES, addr16) - CY
2
1
-- A, CY A - (saddr) - CY
1
1
4 A, CY A - (HL) - CY
2
2
5 A,CY A - (ES, HL) - CY
2
1
4 A, CY A - (HL + byte) - CY
3
2
5 A,CY A - ((ES, HL) + byte) - CY
2
1
4 A, CY A - (HL + B) - CY
3
2
5 A,CY A - ((ES, HL) + B) - CY
2
1
4 A, CY A - (HL + C) - CY
3
2
5 A, CY A - ((ES:HL) + C) - CY
2
1
-- A A byte
3
2
-- (saddr) (saddr) byte
2
1
-- AAr
2
1
-- RrA
3
1
4 A A (addr16)
4
2
5 A A (ES:addr16)
2
1
-- A A (saddr)
1
1
4 A A (HL)
2
2
5 A A (ES:HL)
2
1
4 A A (HL + byte)
3
2
5 A A ((ES:HL) + byte)
2
1
4 A A (HL + B)
3
2
5 A A ((ES:HL) + B)
2
1
4 A A (HL + C)
3
2
5 A A ((ES:HL) + C)
Flag Z AC CY ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× × × × × × × × × × × × × × × ×
Note 1. Note 2. Note 3.
Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. Number of CPU clocks (fCLK) when the code flash memory is accessed, or when the data flash memory is accessed by an 8-bit instruction. Except r = A
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
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Table 36 - 13 Operation List (9/18)
Instruction Mnemonic Group
Operands
8-bit
OR
operation
XOR
A, #byte
saddr, #byte
A, r
Note 3
r, A
A, !addr16
A, ES:!addr16
A, saddr
A, [HL]
A, ES:[HL]
A, [HL+byte]
A, ES:[HL+byte]
A, [HL+B]
A, ES:[HL+B]
A, [HL+C]
A, ES:[HL+C]
A, #byte
saddr, #byte
A, r
Note 3
r, A
A, !addr16
A, ES:!addr16
A, saddr
A, [HL]
A, ES:[HL]
A, [HL+byte]
A, ES:[HL+byte]
A, [HL+B]
A, ES:[HL+B]
A, [HL+C]
A, ES:[HL+C]
Clocks Bytes
Note 1 Note 2
Operation
2
1
-- A A byte
3
2
-- (saddr) (saddr) byte
2
1
-- AAr
2
1
-- rrA
3
1
4 A A (addr16)
4
2
5 A A (ES:addr16)
2
1
-- A A (saddr)
1
1
4 A A (HL)
2
2
5 A A (ES:HL)
2
1
4 A A (HL + byte)
3
2
5 A A ((ES:HL) + byte)
2
1
4 A A (HL + B)
3
2
5 A A ((ES:HL) + B)
2
1
4 A A (HL + C)
3
2
5 A A ((ES:HL) + C)
2
1
-- A A byte
3
2
-- (saddr) (saddr) byte
2
1
-- AAr
2
1
-- rrA
3
1
4 A A (addr16)
4
2
5 A A (ES:addr16)
2
1
-- A A (saddr)
1
1
4 A A (HL)
2
2
5 A A (ES:HL)
2
1
4 A A (HL + byte)
3
2
5 A A ((ES:HL) + byte)
2
1
4 A A (HL + B)
3
2
5 A A ((ES:HL) + B)
2
1
4 A A (HL + C)
3
2
5 A A ((ES:HL) + C)
Flag Z AC CY × × × × × × × × × × × × × × × × × × × × × × × × × × × × × ×
Note 1. Note 2. Note 3.
Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. Number of CPU clocks (fCLK) when the code flash memory is accessed, or when the data flash memory is accessed by an 8-bit instruction. Except r = A
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
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Table 36 - 14 Operation List (10/18)
Instruction Mnemonic Group
Operands
8-bit operation
CMP
CMP0 CMPS
A, #byte
!addr16, #byte
ES:!addr16, #byte
saddr, #byte
A, r
Note 3
r, A
A, !addr16
A, ES:!addr16
A, saddr
A, [HL]
A, ES:[HL]
A, [HL+byte]
A, ES:[HL+byte]
A, [HL+B]
A, ES:[HL+B]
A, [HL+C]
A, ES:[HL+C]
A
X
B
C
!addr16
ES:!addr16
saddr
X, [HL+byte]
X, ES:[HL+byte]
Clocks Bytes
Note 1 Note 2
Operation
2
1
-- A - byte
4
1
4 (addr16) - byte
5
2
5 (ES:addr16) - byte
3
1
-- (saddr) - byte
2
1
-- A-r
2
1
-- r-A
3
1
4 A - (addr16)
4
2
5 A - (ES:addr16)
2
1
-- A - (saddr)
1
1
4 A - (HL)
2
2
5 A - (ES:HL)
2
1
4 A - (HL + byte)
3
2
5 A - ((ES:HL) + byte)
2
1
4 A - (HL + B)
3
2
5 A - ((ES:HL) + B)
2
1
4 A - (HL + C)
3
2
5 A - ((ES:HL) + C)
1
1
-- A - 00H
1
1
-- X - 00H
1
1
-- B - 00H
1
1
-- C - 00H
3
1
4 (addr16) - 00H
4
2
5 (ES:addr16) - 00H
2
1
-- (saddr) - 00H
3
1
4 X - (HL + byte)
4
2
5 X - ((ES:HL) + byte)
Flag Z AC CY ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ×00 ×00 ×00 ×00 ×00 ×00 ×00 ××× ×××
Note 1. Note 2. Note 3.
Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. Number of CPU clocks (fCLK) when the code flash memory is accessed, or when the data flash memory is accessed by an 8-bit instruction. Except r = A
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
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Table 36 - 15 Operation List (11/18)
Instruction Mnemonic Group
Operands
16-bit operation
ADDW
SUBW CMPW
AX, #word AX, AX AX, BC AX, DE AX, HL AX, !addr16 AX, ES:!addr16 AX, saddrp AX, [HL+byte] AX, ES: [HL+byte] AX, #word AX, BC AX, DE AX, HL AX, !addr16 AX, ES:!addr16 AX, saddrp AX, [HL+byte] AX, ES: [HL+byte] AX, #word AX, BC AX, DE AX, HL AX, !addr16 AX, ES:!addr16 AX, saddrp AX, [HL+byte] AX, ES: [HL+byte]
Clocks Bytes
Note 1 Note 2
Operation
3
1
-- AX, CY AX + word
1
1
-- AX, CY AX + AX
1
1
-- AX, CY AX + BC
1
1
-- AX, CY AX + DE
1
1
-- AX, CY AX + HL
3
1
4 AX, CY AX + (addr16)
4
2
5 AX, CY AX + (ES:addr16)
2
1
-- AX, CY AX + (saddrp)
3
1
4 AX, CY AX + (HL + byte)
4
2
5 AX, CY AX + ((ES:HL) + byte)
3
1
-- AX, CY AX - word
1
1
-- AX, CY AX - BC
1
1
-- AX, CY AX - DE
1
1
-- AX, CY AX - HL
3
1
4 AX, CY AX - (addr16)
4
2
5 AX, CY AX - (ES:addr16)
2
1
-- AX, CY AX - (saddrp)
3
1
4 AX, CY AX - (HL + byte)
4
2
5 AX, CY AX - ((ES:HL) + byte)
3
1
-- AX - word
1
1
-- AX - BC
1
1
-- AX - DE
1
1
-- AX - HL
3
1
4 AX - (addr16)
4
2
5 AX - (ES:addr16)
2
1
-- AX - (saddrp)
3
1
4 AX - (HL + byte)
4
2
5 AX - ((ES:HL) + byte)
Flag Z AC CY ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ×××
Note 1. Note 2.
Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. Number of CPU clocks (fCLK) when the code flash memory is accessed, or when the data flash memory is accessed by an 8-bit instruction.
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
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Table 36 - 16 Operation List (12/18)
Instruction Mnemonic Group
Operands
Multiply,
MULU
X
Divide, Multiply & accumulate
MULHU MULH
DIVHU
DIVWU
MACHU MACH
Clocks Bytes
Note 1 Note 2
Operation
1
1
-- AX A × X
3
2
-- BCAX AX × BC (unsigned)
3
2
-- BCAX AX × BC (signed)
AX (quotient), DE (remainder)
3
9
-- AX ÷ DE (unsigned)
3
17
-- BCAX (quotient), HLDE (remainder)
BCAX ÷ HLDE (unsigned)
3
3
-- MACR MACR + AX × BC (unsigned)
3
3
-- MACR MACR + AX × BC(signed)
Flag Z AC CY
×× ××
Note 1. Note 2.
Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. Number of CPU clocks (fCLK) when the code flash memory is accessed, or when the data flash memory is accessed by an 8-bit instruction.
Caution
Disable interrupts when executing the DIVHU or DIVWU instruction in an interrupt servicing routine. Alternatively, unless they are executed in the RAM area, note that execution of a DIVHU or DIVWU instruction is possible even with interrupts enabled as long as a NOP instruction is added immediately after the DIVHU or DIVWU instruction in the assembly language source code. The following compilers automatically add a NOP instruction immediately after any DIVHU or DIVWU instruction output during the build process. - V. 1.01.00 and later versions of CC-RL (Renesas Electronics compiler), for both C and assembly language
source code
- V. 1.71 and later versions of the CA78K0R (Renesas Electronics compiler), for both C and assembly language source code
- Service pack 1.40.3 and later versions of the EWRL78 (IAR compiler), for C language source code - LLVM RL78 (CyberTHOR compiler), for both C and C++ language source code - GNURL78 (CyberTHOR compiler), for both C and C++ language source code
Remark 1. Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Remark 2. MACR indicates the multiplication and accumulation register (MACRH, MACRL).
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Table 36 - 17 Operation List (13/18)
Instruction Mnemonic Group
Operands
Increment/ INC decrement
DEC
INCW
DECW
Shift
SHR SHRW SHL
SHLW
SAR SARW
r !addr16 ES:!addr16 saddr [HL+byte] ES: [HL+byte] r !addr16 ES:!addr16 saddr [HL+byte] ES: [HL+byte] rp !addr16 ES:!addr16 saddrp [HL+byte] ES: [HL+byte] rp !addr16 ES:!addr16 saddrp [HL+byte] ES: [HL+byte] A, cnt AX, cnt A, cnt B, cnt C, cnt AX, cnt BC, cnt A, cnt AX, cnt
Clocks Bytes
Note 1 Note 2
Operation
1
1
-- rr+1
3
2
-- (addr16) (addr16) + 1
4
3
-- (ES, addr16) (ES, addr16) + 1
2
2
-- (saddr) (saddr) + 1
3
2
-- (HL + byte) (HL + byte) + 1
4
3
-- ((ES:HL) + byte) ((ES:HL) + byte) + 1
1
1
-- rr-1
3
2
-- (addr16) (addr16) - 1
4
3
-- (ES, addr16) (ES, addr16) - 1
2
2
-- (saddr) (saddr) - 1
3
2
-- (HL + byte) (HL + byte) - 1
4
3
-- ((ES:HL) + byte) ((ES:HL) + byte) - 1
1
1
-- rp rp + 1
3
2
-- (addr16) (addr16) + 1
4
3
-- (ES, addr16) (ES, addr16) + 1
2
2
-- (saddrp) (saddrp) + 1
3
2
-- (HL + byte) (HL + byte) + 1
4
3
-- ((ES:HL) + byte) ((ES:HL) + byte) + 1
1
1
-- rp rp - 1
3
2
-- (addr16) (addr16) - 1
4
3
-- (ES, addr16) (ES, addr16) - 1
2
2
-- (saddrp) (saddrp) - 1
3
2
-- (HL + byte) (HL + byte) - 1
4
3
-- ((ES:HL) + byte) ((ES:HL) + byte) - 1
2
1
-- (CY A0, Am - 1 Am, A7 0) × cnt
2
1
-- (CY AX0, AXm - 1 AXm, AX15 0) × cnt
2
1
-- (CY A7, Am Am - 1, A0 0) × cnt
2
1
-- (CY B7, Bm Bm - 1, B0 0) × cnt
2
1
-- (CY C7, Cm Cm - 1, C0 0) × cnt
2
1
-- (CY AX15, AXm AXm - 1, AX0 0) × cnt
2
1
-- (CY BC15, BCm BCm - 1, BC0 0) × cnt
2
1
-- (CY A0, Am - 1 Am, A7 A7) × cnt
2
1
-- (CY AX0, AXm - 1 AXm, AX15 AX15) × cnt
Flag Z AC CY ×× ×× ×× ×× ×× ×× ×× ×× ×× ×× ×× ××
× × × × × × × × ×
Note 1. Note 2.
Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. Number of CPU clocks (fCLK) when the code flash memory is accessed, or when the data flash memory is accessed by an 8-bit instruction.
Remark 1. Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Remark 2. cnt indicates the bit shift count.
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Table 36 - 18 Operation List (14/18)
Instruction Mnemonic Group
Operands
Rotate
ROR ROL RORC ROLC ROLWC
Bit
MOV1
manipulate
AND1 OR1
A, 1 A, 1 A, 1 A, 1 AX,1 BC,1 CY, A.bit A.bit, CY CY, PSW.bit PSW.bit, CY CY, saddr.bit saddr.bit, CY CY, sfr.bit sfr.bit, CY CY,[HL].bit [HL].bit, CY CY, ES:[HL].bit ES:[HL].bit, CY CY, A.bit CY, PSW.bit CY, saddr.bit CY, sfr.bit CY,[HL].bit CY, ES:[HL].bit CY, A.bit CY, PSW.bit CY, saddr.bit CY, sfr.bit CY, [HL].bit CY, ES:[HL].bit
Clocks Bytes
Note 1 Note 2
Operation
2
1
-- (CY, A7 A0, Am - 1 Am) × 1
2
1
-- (CY, A0 A7, Am + 1 Am) × 1
2
1
-- (CY A0, A7 CY, Am - 1 Am) × 1
2
1
-- (CY A7, A0 CY, Am + 1 Am) × 1
2
1
-- (CY AX15, AX0 CY, AXm + 1 AXm) × 1
2
1
-- (CY BC15, BC0 CY, BCm + 1 BCm) × 1
2
1
-- CY A.bit
2
1
-- A.bit CY
3
1
-- CY PSW.bit
3
4
-- PSW.bit CY
3
1
-- CY (saddr).bit
3
2
-- (saddr).bit CY
3
1
-- CY sfr.bit
3
2
-- sfr.bit CY
2
1
4 CY (HL).bit
2
2
-- (HL).bit CY
3
2
5 CY (ES, HL).bit
3
3
-- (ES, HL).bit CY
2
1
-- CY CY A.bit
3
1
-- CY CY PSW.bit
3
1
-- CY CY (saddr).bit
3
1
-- CY CY sfr.bit
2
1
4 CY CY (HL).bit
3
2
5 CY CY (ES, HL).bit
2
1
-- CY CY A.bit
3
1
-- CY CY PSW.bit
3
1
-- CY CY (saddr).bit
3
1
-- CY CY sfr.bit
2
1
4 CY CY (HL).bit
3
2
5 CY CY (ES, HL).bit
Flag Z AC CY
× × × × × × ×
× ××
×
×
×
×
× × × × × × × × × × × ×
Note 1. Note 2.
Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. Number of CPU clocks (fCLK) when the code flash memory is accessed, or when the data flash memory is accessed by an 8-bit instruction.
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
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Table 36 - 19 Operation List (15/18)
Instruction Mnemonic Group
Operands
Bit
XOR1
manipulate
SET1
CLR1
SET1 CLR1 NOT1
CY, A.bit CY, PSW.bit CY, saddr.bit CY, sfr.bit CY, [HL].bit CY, ES:[HL].bit A.bit PSW.bit !addr16.bit ES:!addr16.bit saddr.bit sfr.bit [HL].bit ES:[HL].bit A.bit PSW.bit !addr16.bit ES:!addr16.bit saddr.bit sfr.bit [HL].bit ES:[HL].bit CY CY CY
Clocks Bytes
Note 1 Note 2
Operation
2
1
-- CY CY A.bit
3
1
-- CY CY PSW.bit
3
1
-- CY CY (saddr).bit
3
1
-- CY CY sfr.bit
2
1
4 CY CY (HL).bit
3
2
5 CY CY (ES, HL).bit
2
1
-- A.bit 1
3
4
-- PSW.bit 1
4
2
-- (addr16).bit 1
5
3
-- (ES, addr16).bit 1
3
2
-- (saddr).bit 1
3
2
-- sfr.bit 1
2
2
-- (HL).bit 1
3
3
-- (ES, HL).bit 1
2
1
-- A.bit 0
3
4
-- PSW.bit 0
4
2
-- (addr16).bit 0
5
3
-- (ES, addr16).bit 0
3
2
-- (saddr.bit) 0
3
2
-- sfr.bit 0
2
2
-- (HL).bit 0
3
3
-- (ES, HL).bit 0
2
1
-- CY 1
2
1
-- CY 0
2
1
-- CY CY
Flag Z AC CY
× × × × × × ×××
×××
1 0 ×
Note 1. Note 2.
Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed Number of CPU clocks (fCLK) when the code flash memory is accessed, or when the data flash memory is accessed by an 8-bit instruction.
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
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Table 36 - 20 Operation List (16/18)
Instruction Mnemonic Group
Operands
Call/return CALL
rp
$!addr20
!addr16
!!addr20
CALLT
[addr5]
BRK
--
RET
--
RETI
--
RETB
--
Clocks Bytes
Note 1 Note 2
Operation
2
3
-- (SP - 2) (PC + 2)S, (SP - 3) (PC + 2)H,
(SP - 4) (PC + 2)L, PC CS, rp,
SP SP - 4
3
3
-- (SP - 2) (PC + 3)S, (SP - 3) (PC + 3)H,
(SP - 4) (PC + 3)L, PC PC + 3 + jdisp16,
SP SP - 4
3
3
-- (SP - 2) (PC + 3)S, (SP - 3) (PC + 3)H,
(SP - 4) (PC + 3)L, PC 0000, addr16,
SP SP - 4
4
3
-- (SP - 2) (PC + 4)S, (SP - 3) (PC + 4)H,
(SP - 4) (PC + 4)L, PC addr20,
SP SP - 4
2
5
-- (SP - 2) (PC + 2)S, (SP - 3) (PC + 2)H,
(SP - 4) (PC + 2)L , PCS 0000,
PCH (0000, addr5 + 1),
PCL (0000, addr5),
SP SP - 4
2
5
-- (SP - 1) PSW, (SP - 2) (PC + 2)S,
(SP - 3) (PC + 2)H, (SP - 4) (PC + 2)L,
PCS 0000,
PCH (0007FH), PCL (0007EH),
SP SP - 4, IE 0
1
6
-- PCL (SP), PCH (SP + 1),
PCS (SP + 2), SP SP + 4
2
6
-- PCL (SP), PCH (SP + 1),
PCS (SP + 2), PSW (SP + 3),
SP SP + 4
2
6
-- PCL (SP), PCH (SP + 1),
PCS (SP + 2), PSW (SP + 3),
SP SP + 4
Flag Z AC CY
RRR RRR
Note 1. Note 2.
Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. Number of CPU clocks (fCLK) when the code flash memory is accessed, or when the data flash memory is accessed by an 8-bit instruction.
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
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CHAPTER 36 INSTRUCTION SET
Table 36 - 21 Operation List (17/18)
Instruction Group
Mnemonic
Operands
Stack manipulate
PUSH
PSW rp
POP MOVW
Unconditional branch
ADDW SUBW BR
Conditional branch
BC BNC BZ BNZ BH BNH BT
PSW rp SP, #word SP, AX AX, SP HL, SP BC, SP DE, SP SP, #byte SP, #byte AX $addr20 $!addr20 !addr16 !!addr20 $addr20 $addr20 $addr20 $addr20 $addr20 $addr20 saddr.bit, $addr20 sfr.bit, $addr20 A.bit, $addr20 PSW.bit, $addr20 [HL].bit, $addr20 ES:[HL].bit, $addr20
Bytes
2
1
2 1 4 2 2 3 3 3 2 2 2 2 3 3 4 2 2 2 2 3 3 4 4 3 4 3 4
Clocks Note 1 Note 2
Operation
1
--
(SP - 1) PSW, (SP - 2) 00H, SP SP - 2
1
-- (SP - 1) rpH, (SP - 2) rpL,
SP SP - 2
3
-- PSW (SP + 1), SP SP + 2
1
-- rpL (SP), rpH (SP + 1), SP SP + 2
1
-- SP word
1
-- SP AX
1
-- AX SP
1
-- HL SP
1
-- BC SP
1
-- DE SP
1
-- SP SP + byte
1
-- SP SP - byte
3
-- PC CS, AX
3
-- PC PC + 2 + jdisp8
3
-- PC PC + 3 + jdisp16
3
-- PC 0000, addr16
3
-- PC addr20
2/4 Note 3
-- PC PC + 2 + jdisp8 if CY = 1
2/4 Note 3
-- PC PC + 2 + jdisp8 if CY = 0
2/4 Note 3
-- PC PC + 2 + jdisp8 if Z = 1
2/4 Note 3
-- PC PC + 2 + jdisp8 if Z = 0
2/4 Note 3
-- PC PC + 3 + jdisp8 if (Z CY) = 0
2/4 Note 3
-- PC PC + 3 + jdisp8 if (Z CY) = 1
3/5 Note 3
-- PC PC + 4 + jdisp8 if (saddr).bit = 1
3/5 Note 3 3/5 Note 3
-- PC PC + 4 + jdisp8 if sfr.bit = 1 -- PC PC + 3 + jdisp8 if A.bit = 1
3/5 Note 3
-- PC PC + 4 + jdisp8 if PSW.bit = 1
3/5 Note 3 4/6 Note 3
6/7 PC PC + 3 + jdisp8 if (HL).bit = 1 7/8 PC PC + 4 + jdisp8 if (ES, HL).bit = 1
Flag Z AC CY
RRR
Note 1. Note 2. Note 3.
Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. Number of CPU clocks (fCLK) when the code flash memory is accessed, or when the data flash memory is accessed by an 8-bit instruction. This indicates the number of clocks "when condition is not met/when condition is met".
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
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RL78/G23
CHAPTER 36 INSTRUCTION SET
Table 36 - 22 Operation List (18/18)
Instruction Group
Mnemonic
Operands
Conditional BF branch
BTCLR
saddr.bit, $addr20 sfr.bit, $addr20 A.bit, $addr20 PSW.bit, $addr20 [HL].bit, $addr20 ES:[HL].bit, $addr20 saddr.bit, $addr20
sfr.bit, $addr20
A.bit, $addr20
PSW.bit, $addr20
[HL].bit, $addr20
ES:[HL].bit, $addr20
Conditional SKC
--
skip
SKNC
--
SKZ
--
SKNZ
--
SKH
--
SKNH
--
CPU control SEL Note 4 RBn
NOP
--
EI
--
DI
--
HALT
--
STOP
--
Bytes
4 4 3 4 3 4 4
4
3
4
3
4 2 2 2 2 2 2 2 1 3 3 2 2
Clocks Note 1 Note 2
Operation
3/5 Note 3
-- PC PC + 4 + jdisp8 if (saddr).bit = 0
3/5 Note 3
-- PC PC + 4 + jdisp8 if sfr.bit = 0
3/5 Note 3
-- PC PC + 3 + jdisp8 if A.bit = 0
3/5 Note 3
-- PC PC + 4 + jdisp8 if PSW.bit = 0
3/5 Note 3
6/7 PC PC + 3 + jdisp8 if (HL).bit = 0
4/6 Note 3
7/8 PC PC + 4 + jdisp8 if (ES, HL).bit = 0
3/5 Note 3
PC PC + 4 + jdisp8 if (saddr).bit = 1 --
then reset (saddr).bit
3/5 Note 3
PC PC + 4 + jdisp8 if sfr.bit = 1 -- then reset sfr.bit
3/5 Note 3
-- PC PC + 3 + jdisp8 if A.bit = 1 then reset A.bit
3/5 Note 3
PC PC + 4 + jdisp8 if PSW.bit = 1 --
then reset PSW.bit
3/5 Note 3
PC PC + 3 + jdisp8 if (HL).bit = 1 -- then reset (HL).bit
4/6 Note 3
PC PC + 4 + jdisp8 if (ES, HL).bit = 1 --
then reset (ES, HL).bit
1
-- Next instruction skip if CY = 1
1
-- Next instruction skip if CY = 0
1
-- Next instruction skip if Z = 1
1
-- Next instruction skip if Z = 0
1
-- Next instruction skip if (Z CY) = 0
1
-- Next instruction skip if (Z CY) = 1
1
-- RBS[1:0] n
1
-- No Operation
4
-- IE 1 (Enable Interrupt)
4
-- IE 0 (Disable Interrupt)
3
-- Set HALT Mode
3
-- Set STOP Mode
Flag Z AC CY
×××
Note 1.
Note 2.
Note 3. Note 4.
Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. Number of CPU clocks (fCLK) when the code flash memory is accessed, or when the data flash memory is accessed by an 8-bit instruction. This indicates the number of clocks "when condition is not met/when condition is met". n indicates the number of register banks (n = 0 to 3)
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
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RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
37.1
Absolute Maximum Ratings
Absolute Maximum Ratings
(1/2)
Item
Symbols
Conditions
Ratings
Unit
Supply voltage
VDD
-0.5 to +6.5
V
EVDD0, EVDD1 EVDD0 = EVDD1
-0.5 to +6.5
V
EVSS0, EVSS1 EVSS0 = EVSS1
-0.5 to +0.3
V
REGC pin input voltage VIREGC
REGC
-0.3 to +2.1
V
and -0.3 to VDD + 0.3Note 1
Input voltage
VI1
P00 to P07, P10 to P17, P30 to P37,
-0.3 to EVDD0 + 0.3
V
P40 to P47, P50 to P57, P64 to P67,
and -0.3 to VDD + 0.3Note 2
P70 to P77, P80 to P87, P90 to P97,
P100 to P106, P110 to P117, P120,
P125 to P127, P140 to P147
VI2
P60 to P63 (N-ch open-drain)
-0.3 to +6.5
V
VI3
P20 to P27, P121 to P124, P137,
-0.3 to VDD + 0.3Note 2
V
P150 to P156, EXCLK, EXCLKS, RESET
Output voltage
VO1
P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147
-0.3 to EVDD0 + 0.3
V
and -0.3 to VDD + 0.3Note 2
VO2
P20 to P27, P150 to P156
-0.3 to VDD + 0.3Note 2
V
Analog input voltage
VAI1
ANI16 to ANI26
-0.3 to EVDD0 + 0.3
V
and -0.3 to AVREFP + 0.3
Notes 2, 3
VAI2
ANI0 to ANI14
-0.3 to VDD + 0.3
V
and -0.3 to AVREFP + 0.3
Notes 2, 3
Note 1.
Note 2. Note 3.
Connect the REGC pin to VSS via a capacitor (0.47 to 1 µF). The listed value is the absolute maximum rating of the REGC pin. Only use the capacitor connection. Do not apply a specific voltage to this pin. This voltage must be no higher than 6.5 V. The voltage on a pin in use for A/D conversion must not exceed AVREFP + 0.3.
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Remark 1. The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified.
Remark 2. AVREFP refers to the positive reference voltage of the A/D converter. Remark 3. The reference voltage is VSS.
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RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
Absolute Maximum Ratings
(2/2)
Item
Symbols
Conditions
Ratings
Unit
High-level output current IOH1
Per pin
P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147
-40
mA
Total of all pins -170 mA
P00 to P04, P07, P32 to P37, P40 to P47, P102 to P106, P120, P125 to P127, P130, P140 to P145
-70
mA
P05, P06, P10 to P17, P30, P31, P50 to P57,
-100
mA
P64 to P67, P70 to P77, P80 to P87,
P90 to P97, P100, P101, P110 to P117, P146,
P147
IOH2
Per pin
P20 to P27, P121 to P124, P150 to P156
-0.5
mA
Total of all pins
-2
mA
Low-level output current IOL1
Per pin
P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147
40Note
mA
Total of all pins 170 mA
P00 to P04, P07, P32 to P37, P40 to P47, P102 to P106, P120, P125 to P127, P130, P140 to P145
70
mA
P05, P06, P10 to P17, P30, P31, P50 to P57,
100
mA
P60 to P67, P70 to P77, P80 to P87,
P90 to P97, P100, P101, P110 to P117, P146,
P147
IOL2
Per pin
P20 to P27, P121 to P124, P150 to P156
1
mA
Total of all pins
5
mA
Ambient operating
TA
In normal operation mode
temperature
In flash memory programming mode
-40 to +105
C
Storage temperature
Tstg
-65 to +150
C
Note
The rating for the following port pins is 80 mA when IOL1 = 40.0 mA is specified by the 40-mA port output control register (PTDC). - Pins P04, P10, and P120 of the 64- to 100-pin package products with 384- to 768-Kbyte flash ROM - Pin P110 of the 100-pin package products with 384- to 768-Kbyte flash ROM - Pins P17, P51, and P70 of the 30- to 52-pin package products
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified.
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RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
37.2
Characteristics of the Oscillators
37.2.1 Characteristics of the X1 and XT1 oscillators
<R>
(TA = -40 to +105°C, 1.6 V VDD 5.5 V, VSS = 0 V)
Item
Resonator
Conditions
Min.
Typ.
Max. Unit
X1 clock oscillation allowable input Ceramic resonator/
cycle time Note
crystal resonator
0.05
1
µs
XT1 clock oscillation frequency (fXT)Note
Crystal resonator
32.768
kHz
Note
The listed time and frequency indicate permissible ranges of the oscillator. For actual applications, request evaluation by the manufacturer of the oscillator circuit mounted on a board so you can use appropriate values. Refer to AC Characteristics for instruction execution time.
Caution
Since the CPU is started by the high-speed on-chip oscillator clock after release from the reset state, the user should use the oscillation stabilization time counter status register (OSTC) to check the X1 clock oscillation stabilization time. Specify the values for the oscillation stabilization time in the OSTC register and the oscillation stabilization time select register (OSTS) after having sufficiently evaluated the oscillation stabilization time with the resonator to be used.
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
37.2.2 Characteristics of the On-chip Oscillators
<R> <R>
(TA = -40 to +105°C, 1.6 V VDD 5.5 V, VSS = 0 V)
Item
Symbol
Conditions
Min. Typ. Max. Unit
High-speed on-chip
fIH
oscillator clock frequency
1
32
MHz
High-speed on-chip oscillator clock frequency accuracyNote 1
HIPREC = 1 +85 to +105°C 1.8 V VDD 5.5 V -2.0 1.6 V VDD 5.5 V -6.0
-20 to +85°C 1.8 V VDD 5.5 V -1.0
+2.0
%
+6.0
%
+1.0
%
1.6 V VDD 5.5 V -5.0
+5.0
%
-40 to -20°C 1.8 V VDD 5.5 V -1.5
+1.5
%
1.6 V VDD 5.5 V -5.5
+5.5
%
HIPREC = 0Note 4
-15
0
%
High-speed on-chip oscillator clock correction resolution
0.05
%
Middle-speed on-chip
fIM
oscillator clock
frequencyNote 2
1
4
MHz
Middle-speed on-chip oscillator clock frequency accuracyNote 1
-12
+12
%
Middle-speed on-chip oscillator clock correction resolution
0.15
%
Middle-speed on-chip oscillator frequency temperature coefficient
±0.17
Note 3
%/°C
Low-speed on-chip
fIL
oscillator clock
frequencyNote 2
32.768
kHz
Low-speed on-chip oscillator clock frequency accuracyNote 1
-15
+15
%
Low-speed on-chip oscillator clock correction resolution
0.3
%
Low-speed on-chip oscillator frequency temperature coefficient
±0.21
Note 3
%/°C
Note 1. Note 2.
Note 3. Note 4.
The accuracy values were obtained in testing of this product. The listed values only indicate the characteristics of the oscillators. Refer to AC Characteristics for instruction execution time. Guaranteed by characterization results. The listed condition applies when the setting of the FRQSEL3 bit is 1.
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
37.3
DC Characteristics
37.3.1 Pin characteristics
(TA = -40 to +105°C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Item
Symbol
Conditions
Min.
Allowable high-level output current Note 1
IOH1 Per pin for P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147
1.6 V EVDD0 5.5 V
Total of P00 to P04, P07, P32 to P37, P40 to P47, P102 to P106, P120, P125 to P127, P130, P140 to P145 (when duty 70%Note 3)
4.0 V EVDD0 5.5 V
2.7 V EVDD0 < 4.0 V 1.8 V EVDD0 < 2.7 V 1.6 V EVDD0 < 1.8 V
Total of P05, P06, P10 to P17, P30, P31, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100, P101, P110 to P117, P146, P147 (when duty 70%Note 3)
4.0 V EVDD0 5.5 V
2.7 V EVDD0 < 4.0 V 1.8 V EVDD0 < 2.7 V 1.6 V EVDD0 < 1.8 V
Total of all pins (when duty 70%Note 3)
1.6 V EVDD0 5.5 V
IOH2 Per pin for P20 to P27, P121, P122, P150 to P156
4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V
(1/7)
Typ. Max. Unit -10.0 mA
Note 2
-55.0 mA
Note 4
-10.0 mA -5.0 mA -2.5 mA -80.0 mA
Note 5
-19.0 mA -10.0 mA -5.0 mA -135.0 mA
Note 6
-3.0 mA
Note 2
-1.0 mA
Note 2
1.8 V VDD < 2.7 V
-1.0 mA
Note 2
1.6 V VDD < 1.8 V
-0.5 mA
Note 2
Note 1. Note 2. Note 3.
Note 4.
Total of all pins (when duty 70%Note 3)
4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V
-20.0 mA -10.0 mA
1.8 V VDD < 2.7 V
-5.0 mA
1.6 V VDD < 1.8 V
-5.0 mA
Device operation is guaranteed at the listed currents even if current is flowing from the EVDD0, EVDD1, or VDD pin to an output pin. The combination of these and other pins must also not exceed the value for maximum total current. The listed currents apply when the duty cycle is no greater than 70%. Use the following formula to calculate the output current when the duty cycle is greater than 70%, where n is the duty cycle. · Total output current from the listed pins = (IOH 0.7)/(n 0.01)
Example when n = 80% and IOH = -10.0 mA Total output current from the listed pins = (-10.0 0.7)/(80 0.01) -8.7 mA Note that the duty cycle has no effect on the current that is allowed to flow into a single pin. A current higher than the absolute maximum rating must not flow into a single pin. The maximum value is -30 mA in the products for industrial applications (R7F100Gxx3xxxC) with an ambient operating temperature range of 85°C to 105°C.
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
Note 5. Note 6.
The maximum value is -50 mA in the products for industrial applications (R7F100Gxx3xxxC) with an ambient operating temperature range of 85°C to 105°C. The maximum values are respectively -100 mA and -60 mA in the products for industrial applications (R7F100Gxx3xxxC) with an ambient operating temperature range of -40°C to 85°C and of 85°C to 105°C.
Caution The following pins are not capable of the output of high-level signals in the N-ch open-drain mode. P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55, P71, P74, P80 to P82, P96, and P142 to P144
Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified.
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(TA = -40 to +105°C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
(2/7)
Item
Symbol
Conditions
Min.
Typ.
Max. Unit
Allowable low-level output currentNote 1
IOL1 Per pin for P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147
20.0 mA
Notes 2, 3
Per pin for P60 to P63
15.0 mA
Note 2
Total of P00 to P04, P07, P32 to P37, P40 to P47, P102 to P106, P120, P125 to P127, P130, P140 to P145 (when duty 70%Note 4)
4.0 V EVDD0 5.5 V
2.7 V EVDD0 < 4.0 V 1.8 V EVDD0 < 2.7 V 1.6 V EVDD0 < 1.8 V
70.0 mA
Note 5
15.0 mA
9.0
mA
4.5
mA
Total of P05, P06, P10 to P17, P30, P31, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100, P101, P110 to P117, P146, P147 (when duty 70%Note 4)
4.0 V EVDD0 5.5 V
2.7 V EVDD0 < 4.0 V 1.8 V EVDD0 < 2.7 V 1.6 V EVDD0 < 1.8 V
80.0 mA
Note 5
35.0 mA 20.0 mA 10.0 mA
Total of all pins (when duty 70%Note 4)
150.0 mA
Note 6
IOL2 Per pin for P20 to P27, P121, P122, P150 to P156
4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V
8.5Note 2 mA 1.5Note 2 mA
1.8 V VDD < 2.7 V
0.6Note 2 mA
1.6 V VDD < 1.8 V
0.4Note 2 mA
Total of all pins (when duty 70%Note 4)
4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V
20
mA
20
mA
1.8 V VDD < 2.7 V
15
mA
1.6 V VDD < 1.8 V
10
mA
Note 1. Note 2. Note 3.
Note 4.
Note 5.
Device operation is guaranteed at the listed currents even if current is flowing from an output pin to the EVSS0, EVSS1, or VSS pin. The combination of these and other pins must also not exceed the value for maximum total current. The maximum rating for the following port pins is 40 mA when IOL1 = 40.0 mA is specified by the 40-mA port output control register (PTDC). - Pins P04, P10, and P120 of the 64- to 100-pin package products with 384- to 768-Kbyte flash ROM - Pin P101 of the 100-pin package products with 384- to 768-Kbyte flash ROM - Pins P17, P51, and P70 of the 30- to 52-pin package products The listed currents apply when the duty cycle is no greater than 70%. Use the following formula to calculate the output current when the duty cycle is greater than 70%, where n is the duty cycle. · Total output current from the listed pins = (IOL 0.7)/(n 0.01)
Example when n = 80% and IOL = 10.0 mA Total output current from the listed pins = (10.0 0.7)/(80 0.01) 8.7 mA Note that the duty cycle has no effect on the current that is allowed to flow into a single pin. A current higher than the absolute maximum rating must not flow into a single pin. The maximum value is 40 mA in the products for industrial applications (R7F100Gxx3xxxC) with an ambient operating temperature range of 85°C to 105°C.
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
Note 6.
The maximum value is 80 mA in the products for industrial applications (R7F100Gxx3xxxC) with an ambient operating temperature range of 85°C to 105°C.
Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified.
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(TA = -40 to +105°C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
(3/7)
Item
Symbol
Conditions
Min.
Typ. Max.
Unit
Input voltage, high
VIH1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147
Normal input buffer
0.8 EVDD0
EVDD0
V
VIH2 P01, P03, P04, P10, P11,
TTL input buffer
2.2
P13 to P17, P43, P44,
4.0 V EVDD0 5.5 V
P53 to P55, P80, P81, P142,
P143
TTL input buffer
2.0
3.3 V EVDD0 < 4.0 V
EVDD0
V
EVDD0
V
TTL input buffer
1.5
1.6 V EVDD0 < 3.3 V
EVDD0
V
VIH3 P20 to P27, P150 to P156
0.7 VDD
VDD
V
VIH4 P60 to P63
0.7 EVDD0
6.0
V
VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET
0.8 VDD
VDD
V
Input voltage, low
VIL1 P00 to P07, P10 to P17,
Normal input buffer
0
P30 to P37, P40 to P47,
P50 to P57, P64 to P67,
P70 to P77, P80 to P87,
P90 to P97, P100 to P106,
P110 to P117, P120,
P125 to P127, P140 to P147
0.2 EVDD0 V
VIL2 P01, P03, P04, P10, P11,
TTL input buffer
0
P13 to P17, P43, P44,
4.0 V EVDD0 5.5 V
P53 to P55, P80, P81, P142,
P143
TTL input buffer
0
3.3 V EVDD0 < 4.0 V
0.8
V
0.5
V
TTL input buffer
0
1.6 V EVDD0 < 3.3 V
0.32
V
VIL3 P20 to P27, P150 to P156
0
0.3 VDD
V
VIL4
P60 to P63
0
0.3 EVDD0 V
VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET
0
0.2 VDD
V
Caution The maximum value of VIH of pins P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55, P71, P74, P80 to P82, P96, and P142 to P144 is EVDD0, even in the N-ch open-drain mode.
Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified.
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RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(TA = -40 to +105°C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
(4/7)
Item
Symbol
Conditions
Min.
Typ.
Max. Unit
Output voltage, high VOH1 P00 to P07, P10 to P17,
4.0 V EVDD0 5.5 V, EVDD0
V
P30 to P37, P40 to P47,
IOH1 = -10.0 mA
- 1.5
P50 to P57, P64 to P67,
P70 to P77, P80 to P87,
4.0 V EVDD0 5.5 V, EVDD0
V
P90 to P97, P100 to P106,
IOH1 = -3.0 mA
- 0.7
P110 to P117, P120,
2.7 V EVDD0 5.5 V, EVDD0
V
P125 to P127, P130,
IOH1 = -2.0 mA
- 0.6
P140 to P147
1.8 V EVDD0 5.5 V, EVDD0
V
IOH1 = -1.5 mA
- 0.5
1.6 V EVDD0 < 5.5 V, EVDD0
V
IOH1 = -1.0 mA
- 0.5
VOH2 P20 to P27, P121, P122,
4.0 V VDD 5.5 V,
VDD
V
P150 to P156
IOH2 = -3.0 mA
- 0.7
2.7 V VDD < 4.0 V,
VDD
V
IOH2 = -1.0 mA
- 0.5
1.8 V VDD < 2.7 V,
VDD
V
IOH2 = -1.0 mA
- 0.5
1.6 V VDD < 1.8 V,
VDD
V
IOH2 = -0.5 mA
- 0.5
Caution P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55, P71, P74, P80 to P82, P96, and P142 to P144 do not output high-level signals in the N-ch open-drain mode.
Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified.
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RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(TA = -40 to +105°C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
(5/7)
Item
Symbol
Conditions
Min. Typ. Max. Unit
Output voltage, low VOL1
P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147
4.0 V EVDD0 5.5 V 4.0 V EVDD0 5.5 V 2.7 V EVDD0 5.5 V
IOL1 = 20.0 mA IOL1 = 40.0 mANote IOL1 = 8.5 mA IOL1 = 17.0 mANote IOL1 = 3.0 mA IOL1 = 6.0 mANote
1.3 V 1.3 V 0.7 V 0.7 V 0.6 V 0.6 V
2.7 V EVDD0 5.5 V
IOL1 = 1.5 mA IOL1 = 3.0 mANote
0.4 V 0.4 V
1.8 V EVDD0 5.5 V IOL1 = 0.6 mA
0.4 V
IOL1 = 1.2 mANote
0.4 V
1.6 V EVDD0 5.5 V IOL1 = 0.3 mA
0.4 V
IOL1 = 0.6 mANote
0.4 V
VOL2
P20 to P27, P121, P122, P150 to P156
4.0 V VDD 5.5 V, IOL2 = 8.5 mA 2.7 V VDD < 4.0 V, IOL2 = 1.5 mA
0.7 V 0.5 V
1.8 V VDD < 2.7 V, IOL2 = 0.6 mA
0.4 V
1.6 V VDD < 1.8 V, IOL2 = 0.4 mA
0.4 V
VOL3 P60 to P63
4.0 V EVDD0 5.5 V, IOL3 = 15.0 mA
2.0 V
4.0 V EVDD0 5.5 V, IOL3 = 5.0 mA
0.4 V
2.7 V EVDD0 5.5 V, IOL3 = 3.0 mA
0.4 V
1.8 V EVDD0 5.5 V, IOL3 = 2.0 mA
0.4 V
1.6 V EVDD0 5.5 V, IOL3 = 1.0 mA
0.4 V
Note
This setting applies to the following port pins. - Pins P04, P10, and P120 of the 64- to 100-pin package products with 384- to 768-Kbyte flash ROM - Pin P101 of the 100-pin package products with 384- to 768-Kbyte flash ROM - Pins P17, P51, and P70 of the 30- to 52-pin package products
Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified.
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RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(TA = -40 to +105°C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
(6/7)
Item
Symbol
Conditions
Min. Typ. Max. Unit
Output currentNote
CCDIOL P16, P17, P50, P51 CCSm = 01H 4.0 V EVDD0 5.5 V
P60 to P63
2.7 V EVDD0 < 4.0 V
1.0 1.8 2.6 mA 0.8 1.5 2.3 mA
CCSm = 02H 4.0 V EVDD0 5.5 V
3.0 4.9 6.5 mA
3.0 V EVDD0 < 4.0 V
2.7 4.3 5.9 mA
CCSm = 03H 4.0 V EVDD0 5.5 V
6.6 10.0 13.2 mA
3.3 V EVDD0 < 4.0 V
6.0 9.1 12.1 mA
P60 to P63
CCSm = 04H 4.0 V EVDD0 5.5 V
10.2 15.0 19.8 mA
3.3 V EVDD0 < 4.0 V
9.4 13.8 18.2 mA
Note
The listed currents apply when the output current control function is enabled.
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RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(TA = -40 to +105°C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
(7/7)
Item
Symbol
Conditions
Min. Typ. Max. Unit
Input leakage current, ILIH1 high
P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147
VI = EVDD0
0.5 µA
ILIH2
P20 to P27, P137, P150 to P156, RESET
VI = VDD
0.5 µA
ILIH3
P121 to P124
VI = VDD
(X1, X2, XT1, XT2, EXCLK, EXCLKS)
0.5 µA
Input leakage current, ILIL1 low
P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147
VI = EVSS0
0.5 µA
ILIL2 P20 to P27, P137, P150 to P156, RESET
VI = VSS
0.5 µA
ILIL3
P121 to P124
VI = VSS
(X1, X2, XT1, XT2, EXCLK, EXCLKS)
0.5 µA
On-chip pll-up resistance
RU
P00 to P07, P10 to P17, P30 to P37, VI = EVSS0, In input port
10 20 100 k
P40 to P47, P50 to P57, P64 to P67,
P70 to P77, P80 to P87, P90 to P97,
P100 to P106, P110 to P117,
P120 to P122, P125 to P127,
P140 to P147
Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified.
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RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
37.3.2 Supply current characteristics
(1) 30- to 64-pin package products with 96- to 128-Kbyte flash ROM
<R>
(TA = -40 to +105°C, 1.6 V EVDD0 VDD 5.5 V, VSS = EVSS0 = 0 V)
(1/4)
Item Symbol
Conditions
Min. Typ. Max. Unit
Supply current
Note 1
IDD1
Operating HS
mode
(high-speed main)
mode
fIH = 32 MHzNote 2
Basic
VDD = 5.0 V
operation VDD = 1.8 V
Normal VDD = 5.0 V operation
VDD = 1.8 V
1.4 -- mA 1.4 -- 3.1 5.1 mA 3.1 5.1
LS (low-speed main) mode
fIH = 24 MHzNote 2 fIH = 16 MHzNote 2
Normal VDD = 5.0 V operation
VDD = 1.8 V
Normal VDD = 5.0 V operation
VDD = 1.8 V
2.3 3.9 mA 2.3 3.9 1.7 2.8 mA 1.7 2.8
fIM = 4 MHzNote 3
Normal VDD = 5.0 V operation
VDD = 1.6 V
0.4 0.7 mA 0.4 0.7
LP (low-power main) mode
fIM = 2 MHzNote 3 fIM = 1 MHzNote 3
Normal VDD = 5.0 V operation
VDD = 1.6 V
Normal VDD = 5.0 V operation
VDD = 1.6 V
206 332 µA
205 331
115 181 µA
114 180
HS (high-speed main) mode
fMX = 20 MHzNote 4, Square wave input
Normal VDD = 5.0 V operation
VDD = 1.8 V
1.9 3.2 mA 1.9 3.2
LS (low-speed main) mode
fMX = 20 MHzNote 4, Square wave input
Normal VDD = 5.0 V operation
VDD = 1.8 V
fMX = 20 MHzNote 4, Normal VDD = 5.0 V Resonator connection operation
VDD = 1.8 V
1.8 3.0 mA 1.8 3.0 2.0 3.3 mA 2.0 3.2
fMX = 10 MHzNote 4, Square wave input
Normal VDD = 5.0 V operation
VDD = 1.8 V
0.9 1.6 mA 0.9 1.6
fMX = 10 MHzNote 4, Normal VDD = 5.0 V Resonator connection operation
VDD = 1.8 V
1.0 1.7 mA 1.0 1.7
fMX = 8 MHzNote 4, Square wave input
Normal VDD = 5.0 V operation
VDD = 1.8 V
0.8 1.3 mA 0.8 1.3
fMX = 8 MHzNote 4,
Normal VDD = 5.0 V
Resonator connection operation VDD = 1.8 V
0.9 1.4 mA 0.9 1.4
Note 1.
Note 2. Note 3. Note 4.
The listed currents are the total currents flowing into VDD and EVDD0, including the input leakage currents flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The currents in the Max. column include the peripheral operation current, but do not include those flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pulldown resistors, and those flowing while the data flash memory is being rewritten. The listed currents apply when the high-speed system clock, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock are stopped. The listed currents apply when the high-speed on-chip oscillator, high-speed system clock, low-speed on-chip oscillator, and subsystem clock are stopped. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock are stopped.
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RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
Remark 1. fIH: High-speed on-chip oscillator clock frequency Remark 2. fIM: Middle-speed on-chip oscillator clock frequency Remark 3. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 4. The typical value for the ambient operating temperature (TA) is 25°C unless otherwise specified.
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RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(1) 30- to 64-pin package products with 96- to 128-Kbyte flash ROM
<R>
(TA = -40 to +105°C, 1.6 V EVDD0 VDD 5.5 V, VSS = EVSS0 = 0 V)
(2/4)
Item Symbol
Conditions
Min. Typ. Max. Unit
Supply IDD1 current
Note 1
Operating mode
Subsystem clock operation mode
fSUB = 32.768 kHzNote 2, Low-speed on-chip oscillator operation
Normal operation
TA = -40°C TA = +25°C TA = +50°C
3.7 6.3 µA 4.1 6.8 4.4 9.7
TA = +70°C
5.1 15.0
TA = +85°C
6.0 23.4
TA = +105°C
8.7 42.5
fSUB = 32.768 kHzNote 3, Normal TA = -40°C
Square wave input
operation TA = +25°C
3.3 5.6 µA 3.5 5.7
TA = +50°C
3.7 8.4
TA = +70°C
4.3 13.5
TA = +85°C
5.2 21.3
TA = +105°C
7.6 38.7
fSUB = 32.768 kHzNote 3, Normal TA = -40°C
Resonator connection
operation TA = +25°C
3.3 5.2 µA 3.6 5.5
TA = +50°C
3.8 7.9
TA = +70°C
4.4 13.5
TA = +85°C
5.3 21.1
TA = +105°C
7.9 38.9
Note 1. Note 2. Note 3.
The listed currents are the total currents flowing into VDD and EVDD0, including the input leakage currents flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The currents in the Max. column include the peripheral operation current, but do not include those flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pulldown resistors, and those flowing while the data flash memory is being rewritten. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. They do not include the current flowing into the RTC, 32-bit interval timer, and watchdog timer. The listed currents apply when the high-speed on-chip oscillator, high-speed system clock, middle-speed on-chip oscillator, and low-speed on-chip oscillator are stopped, and the low power consumption oscillation 3 is specified (AMPHS1, AMPHS0 = 1, 1). They do not include the currents flowing into the RTC, 32-bit interval timer, and watchdog timer.
Remark 1. fIL: Low-speed on-chip oscillator clock frequency Remark 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
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RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(1) 30- to 64-pin package products with 96- to 128-Kbyte flash ROM
<R>
(TA = -40 to +105°C, 1.6 V EVDD0 VDD 5.5 V, VSS = EVSS0 = 0 V)
(3/4)
Item
Symbol
Conditions
Min. Typ. Max. Unit
Supply
IDD2
currentNote 1 Note 2
HALT mode
HS (high-speed main) mode
fIH = 32 MHzNote 3
VDD = 5.0 V VDD = 1.8 V
0.58 1.98 mA 0.58 1.98
LS (low-speed main) mode
fIH = 24 MHzNote 3 fIH = 16 MHzNote 3
VDD = 5.0 V VDD = 1.8 V VDD = 5.0 V
0.48 1.54 mA 0.48 1.54 0.48 1.23 mA
VDD = 1.8 V
0.48 1.23
fIM = 4 MHzNote 4
VDD = 5.0 V
0.09 0.27 mA
VDD = 1.6 V
0.09 0.27
LP (low-power main) mode
fIM = 2 MHzNote 4 fIM = 1 MHzNote 4
VDD = 5.0 V VDD = 1.6 V VDD = 5.0 V
34 121 µA
34 121
29
75
µA
VDD = 1.6 V
29
75
HS (high-speed main) mode
fMX = 20 MHzNote 5, Square wave input
VDD = 5.0 V VDD = 1.8 V
0.23 1.07 mA 0.20 1.04
LS (low-speed main) mode
fMX = 20 MHzNote 5, Square wave input
VDD = 5.0 V VDD = 1.8 V
fMX = 20 MHzNote 5, VDD = 5.0 V Resonator connection
VDD = 1.8 V
0.23 1.07 mA 0.20 1.04 0.41 1.29 mA 0.41 1.29
fMX = 10 MHzNote 5, Square wave input
VDD = 5.0 V VDD = 1.8 V
0.14 0.57 mA 0.12 0.55
fMX = 10 MHzNote 5, VDD = 5.0 V Resonator connection
VDD = 1.8 V
0.24 0.69 mA 0.24 0.69
fMX = 8 MHzNote 5, Square wave input
VDD = 5.0 V VDD = 1.8 V
0.12 0.47 mA 0.10 0.45
fMX = 8 MHzNote 5,
VDD = 5.0 V
Resonator connection VDD = 1.8 V
0.21 0.58 mA 0.21 0.58
Note 1.
Note 2. Note 3. Note 4. Note 5.
The listed currents are the total currents flowing into VDD and EVDD0, including the input leakage currents flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The currents in the Max. column include the peripheral operation current, but do not include those flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pulldown resistors, and those flowing while the data flash memory is being rewritten. The listed currents apply when the HALT instruction has been fetched from the flash memory for execution. The listed currents apply when the high-speed system clock, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock are stopped. The listed currents apply when the high-speed on-chip oscillator, high-speed system clock, low-speed on-chip oscillator, and subsystem clock are stopped. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock are stopped.
Remark 1. fIH: High-speed on-chip oscillator clock frequency Remark 2. fIM: Middle-speed on-chip oscillator clock frequency Remark 3. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 4. The typical value for the ambient operating temperature (TA) is 25°C unless otherwise specified.
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RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(1) 30- to 64-pin package products with 96- to 128-Kbyte flash ROM
<R>
(TA = -40 to +105°C, 1.6 V EVDD0 VDD 5.5 V, VSS = EVSS0 = 0 V)
Item Symbol
Conditions
Min.
Supply current
Note 1
IDD2
Note 2
HALT mode
Subsystem clock operation mode
fSUB = 32.768 kHzNote 3, Low-speed on-chip oscillator operation
TA = -40°C TA = +25°C TA = +50°C
TA = +70°C
TA = +85°C
TA = +105°C
fSUB = 32.768 kHz, Square wave input Note 4
TA = -40°C TA = +25°C
TA = +50°C
TA = +70°C
TA = +85°C
TA = +105°C
fSUB = 32.768 kHz,
TA = -40°C
Resonator connection Note 5 TA = +25°C
TA = +50°C
TA = +70°C
TA = +85°C
TA = +105°C
IDD3
STOP mode RAMSDS = 0Note 6
TA = -40°C
TA = +25°C
TA = +50°C
TA = +70°C
TA = +85°C
TA = +105°C
RAMSDS = 1Note 7
TA = -40°C
TA = +25°C
TA = +50°C
TA = +70°C
TA = +85°C
TA = +105°C
RAMSDS = 1, 128-Hz realtime clock operationNote 8
TA = -40°C TA = +25°C
TA = +50°C
TA = +70°C
TA = +85°C
TA = +105°C
(4/4)
Typ. Max. Unit
0.85 2.94 µA
1.08 3.25
1.30 5.95
1.72 11.05
2.40 19.17
4.32 37.31
0.22 2.01 µA
0.29 1.90
0.44 4.46
0.80 9.36
1.44 17.53
3.24 35.11
0.23 2.06 µA
0.34 2.24
0.51 4.91
0.88 9.93
1.52 18.11
3.37 36.04
0.15 1.45 µA
0.23 1.45
0.45
4
0.9
9
1.6
17
4
35
0.14 1.45 µA
0.21 1.45
0.4 3.5
0.8 8.5
1.4
15
3.2
30
0.22 1.53 µA
0.32 1.56
0.52 3.62
0.93 8.63
1.54 15.14
3.34 30.14
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
Note 1.
Note 2. Note 3. Note 4. Note 5.
Note 6.
Note 7. Note 8.
The listed currents are the total currents flowing into VDD and EVDD0, including the input leakage currents flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The currents in the Max. column include the peripheral operation current, but do not include those flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pulldown resistors, and those flowing while the data flash memory is being rewritten. The listed currents apply when the HALT instruction has been fetched from the flash memory for execution. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. They include the currents flowing into the RTC, but do not include those into the 32-bit interval timer and watchdog timer. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and low-speed on-chip oscillator are stopped. They include the currents flowing into the RTC, but do not include those into the 32-bit interval timer and watchdog timer. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and low-speed on-chip oscillator are stopped, and the setting of RTCLPC is 1, and the low power consumption oscillation 3 is specified (AMPHS1, AMPHS0 = 1, 1). They include the currents flowing into the RTC, but do not include those into the 32-bit interval timer and watchdog timer. The listed currents with this setting allow retention of the contents of the entire RAM area. The listed currents apply when the low-speed on-chip oscillator and subsystem clock oscillation are stopped. They do not include the current flowing into the RTC, 32-bit interval timer, and watchdog timer. For the current for operation of the subsystem clock in the STOP mode, refer to that in the HALT mode. The listed currents with this setting allow retention of the contents of a specified 4-Kbyte area of the RAM. The listed currents apply when the low-speed on-chip oscillator and subsystem clock oscillation are stopped. They do not include the currents flowing into the RTC, 32-bit interval timer, and watchdog timer. The listed currents with this setting allow retention of the contents of a specified 4-Kbyte area of the RAM. The listed currents apply when the low-speed on-chip oscillator is stopped, the setting of RTCLPC is 1, and the low power consumption oscillation 3 is specified (AMPHS1, AMPHS0 = 1, 1). They do not include the currents flowing into the RTC, 32-bit interval timer, and watchdog timer.
Remark 1. fIL: Low-speed on-chip oscillator clock frequency Remark 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(2) Peripheral Functions (Common to all products)
<R>
(TA = -40 to +105°C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Item
Symbol
Conditions
High-speed on-chip oscillator operating current
IFIHNote 1
HIPREC = 1 HIPREC = 0
Middle-speed on-chip oscillator operating current
IFIMNote 1
Low-speed on-chip oscillator operating current
IFILNote 1
RTC operating current
IRTC
Notes 1, 2, 3
fRTCCLK = 32.768 kHz fRTCCLK = 128 Hz
32-bit interval timer operating current
IIT
Notes 1, 2, 4
Watchdog timer operating IWDT
current
Notes 1, 2, 5
fIL = 32.768 kHz (typ.)
A/D converter operating current
IADC
Notes 1, 6
When conversion at maximum speed
Normal mode, AVREFP = VDD = 5.0 V Low voltage mode, AVREFP = VDD = 3.0 V
AVREFP current
IADREFNote 7 AVREFP = 5.0 V
A/D converter internal
IADREFNote 1
reference voltage current
Temperature sensor operating current
ITMPSNote 1
D/A converter operating current
IDACNotes 1, 8 Per channel
Comparator operating current
ICMPNotes 1, 9
LVD operating current
ILVD0
Notes 1, 10
ILVD1
Notes 1, 10
Self-programming operating current
IFSPNotes 1, 11
Data flash rewrite operating current
IBGO
Notes 1, 12
Snooze mode sequencer ISMS
operating current
Notes 1, 13
fIH = 32 MHz fIL = 32.768 kHz
SNOOZE operating current
ISNOZNote 1
ADC to be in The ADC is shifting from the STOP mode
use
to the SNOOZE mode.Note 14
The ADC is operating in the low-voltage mode. AVREFP = VDD = 3.0 V
SPI (CSI)/UART to be in use
Remote control signal
IREM
receiver operating current Notes 1, 15
Low-speed peripheral clock supply current
ISXP
Notes 1, 16
RTCLPC = 0
Min. Typ. Max. Unit 380 -- µA 240 -- µA 20 -- µA
0.3 -- µA
0.005 -- µA 0.002 -- µA 0.04 -- µA
0.32 -- µA
0.95 1.6 mA 0.5 0.75 mA
52 -- µA 114 -- µA
110 -- µA
150 -- µA
6
-- µA
0.02 -- µA 0.02 -- µA 2.5 12.2 mA
2.5 12.2 mA
1.1 -- mA 1.2 -- µA 0.6 0.81 mA
1.2 1.56
0.7 0.92 0.03 -- µA
0.22 -- µA
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
<R>
<R> <R> <R> <R>
(TA = -40 to +105°C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Item
Symbol
Conditions
Min. Typ. Max. Unit
Output current control operating current
ICCDA
Notes 1, 17
The setting of the CCDE register is not 00H.
100 -- µA
Note 1. Note 2. Note 3.
Note 4.
Note 5. Note 6. Note 7. Note 8.
Note 9. Note 10. Note 11. Note 12. Note 13.
Note 14. Note 15.
Note 16. Note 17. Note 18.
ICCDP
Notes 1, 18
Per single output current control port
Setting of the low-level output current: Hi-Z
Setting of the low-level output current: 2 to 15 mA
30 -- µA 200 -- µA
This current flows into VDD. The listed currents apply when the high-speed on-chip oscillator, middle-speed on-chip oscillator, and high-speed system clock are stopped. This current flows into the realtime clock (RTC). It does not include the operating current of the low-speed on-chip oscillator or the XT1 oscillator. The supply current of the RL78 microcontrollers is the sum of either IDD1 or IDD2, and IRTC, when the realtime clock is operating or in the HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be included in the supply current. IDD2 in the subsystem clock operation mode includes the operating current of the realtime clock. This current only flows to the 32-bit interval timer. It does not include the operating current of the low-speed on-chip oscillator or the XT1 oscillator. The supply current of the RL78 microcontrollers is the sum of either IDD1 or IDD2, and IIT, when the 32-bit interval timer is operating or in the HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be included in the supply current. This current only flows to the watchdog timer. It includes the operating current of the low-speed on-chip oscillator. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer is operating. This current only flows to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IADC when the A/D converter is operating or in the HALT mode. This current flows into AVREFP. This current only flows to the D/A converter. The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IDAC, when the D/A converter is operating or in the HALT mode. This current only flows to the comparator. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ICMP when the comparator is in operation. This current only flows to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ILVD when the LVD circuit is in operation. This current only flows during self programming. This current only flows while the data flash memory is being rewritten. This current only flows into the snooze mode sequencer. Note that the operating current of the low-speed on-chip oscillator and the XT1 oscillator are not included. The supply current of the RL78 microcontrollers is the sum of either IDD1 or IDD2, and ISMS, when the snooze mode sequencer is operating or in the HALT mode. For shift time to the SNOOZE mode, see 18.3.13 SNOOZE Mode Function. This current flows into the remote control signal receiver. It does not include the operating current of the low-speed on-chip oscillator or the XT1 oscillator. The supply current of the RL78 microcontrollers is the sum of either IDD1 or IDD2, and IIT, when the remote control signal receiver is operating or in the HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be included in the supply current. This current is added to the supply current in the HALT mode when the setting of RTCLPC is 0 in the STOP mode, or when the setting of RTCLPC is 0 with the sub-system clock (fSUB) selected as the CPU clock. This current is added to the supply current when the output voltage control port is set. This current does not include the current flowing into the I/O port pins.
Remark 1. fIL: Low-speed on-chip oscillator clock frequency Remark 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 3. fCLK: CPU/peripheral hardware clock frequency Remark 4. The typical value for the ambient operating temperature (TA) is 25°C unless otherwise specified.
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
37.4
AC Characteristics
<R>
(TA = -40 to +105°C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Item
Symbol
Conditions
Min. Typ.
Instruction cycle (minimum instruction execution time)
TCY Main system clock HS
1.8 V VDD 5.5 V 0.03125
(fMAIN) operation
(high-speed main) mode
1.6 V VDD 1.8 V
0.25
LS (low-speed main) mode
1.8 V VDD 5.5 V 1.6 V VDD 1.8 V
0.04167 0.25
LP
1.6 V VDD 5.5 V
0.5
(low-power main)
mode
Subsystem clock (fSUB) operation
1.8 V VDD 5.5 V 26.041 30.5
In the self programming mode
HS (high-speed main) mode
1.8 V VDD 5.5 V 1.6 V VDD 1.8 V
0.03125 0.5
LS (low-speed main) mode
1.8 V VDD 5.5 V 1.6 V VDD 1.8 V
0.04167 0.5
External system clock fEX
1.8 V VDD 5.5 V
1.0
frequency
1.6 V VDD < 1.8 V
1.0
fEXS
32
External system clock input high-level width, low-level width
tEXH, tEXL
1.8 V VDD 5.5 V 1.6 V VDD < 1.8 V
tEXHS, tEXLS
15 120 13.7
TI00 to TI07, TI10 to TI17 tTIH, input high-level width, tTIL low-level width
1/fMCK + 10
TO00 to TO07, TO10 to fTO TO17 output frequency
HS (high-speed main) mode LS (low-speed main) mode
4.0 V EVDD0 5.5 V 2.7 V EVDD0 < 4.0 V
1.8 V EVDD0 < 2.7 V
1.6 V EVDD0 < 1.8 V
LP (low-power main) mode
1.6 V EVDD0 5.5 V
PCLBUZ0, PCLBUZ1 output frequency
fPCL HS (high-speed main) mode LS (low-speed main) mode
4.0 V EVDD0 5.5 V 2.7 V EVDD0 < 4.0 V
1.8 V EVDD0 < 2.7 V
1.6 V EVDD0 < 1.8 V
LP (low-power main) mode
1.6 V EVDD0 < 1.8 V
Interrupt input high-level fINTH,
width, low-level width
fINTL
INTP0 INTP1 to INTP11
1.6 V VDD 5.5 V
1
1.6 V EVDD0 5.5 V
1
Key interrupt input low- fKRH, KR0 to KR7
level width
fKRL
1.8 V EVDD0 5.5 V 250
1.6 V EVDD0 < 1.8 V
1
RESET low-level width fRSL
10
Max. Unit
1
µs
1
µs
1
µs
1
µs
1
µs
31.3 µs
1
µs
1
µs
1
µs
1
µs
20.0 MHz 4.0 MHz 38.4 kHz
ns ns µs
nsNote
16 MHz 8 MHz 4 MHz 2 MHz 2 MHz 16 MHz 8 MHz 4 MHz 2 MHz 2 MHz
µs µs ns µs µs
(Note and Remark are listed on the next page.)
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
Note
The following conditions are required for low voltage interface when EVDD0 < VDD. 1.8 V EVDD0 < 2.7 V: 125 ns min. 1.6 V EVDD0 < 1.8 V: 250 ns min.
Remark
fMCK: Timer array unit operating clock frequency (To set this operating clock, use the CKSmn0 and CKSmn1 bits of the timer mode register mn (TMRmn) (m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3).)
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
Minimum Instruction Execution Time during Main System Clock Operation TCY vs VDD (HS (high-speed main) mode)
10
Cycle time TCY [µs]
1.0 0.5 0.25
0.1 0.05 0.03125
0.01 0
1.0 2.0 3.0 4.0 5.0 6.0
1.6 1.8
5.5
Supply voltage VDD [V]
In normal operation During self programming
TCY vs VDD (LS (low-speed main) mode)
10
Cycle time TCY [µs]
1.0 0.5 0.25
0.1 0.05 0.04167
In normal operation During self programming
0.01 0
1.0 2.0 3.0 4.0 5.0 6.0
1.6 1.8
5.5
Supply voltage VDD [V]
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
TCY vs VDD (LP (low-power main) mode)
10
Cycle time TCY [µs]
1.0 In normal operation
0.5
0.1 0.05
0.01 0
1.0 2.0 3.0 4.0 5.0 6.0
1.6
5.5
Supply voltage VDD [V]
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RL78/G23 AC Timing Test Points
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
VIH/VOH VIL/VOL
Test points
VIH/VOH VIL/VOL
External System Clock Timing
EXCLK/EXCLKS
tEXL/ tEXLS
1/fEX/ 1/fEXS
tEXH/ tEXHS
TI/TO Timing
TI00 to TI07, TI10 to TI17 TO00 to TO07, TO10 to TO17
tTIL
tTIH
1/fTO
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RL78/G23 Interrupt Request Input Timing
INTP0 to INTP11
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
tINTL
tINTH
Key Interrupt Input Timing KR0 to KR7
tKRL
tKRH
RESET Input Timing
tRSL RESET
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
37.5
Characteristics of the Peripheral Functions
AC Timing Test Points
VIH/VOH VIL/VOL
Test points
VIH/VOH VIL/VOL
37.5.1 Serial array unit
(1) In UART communications with devices operating at same voltage levels
<R>
(TA = -40 to +105°C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Item
Symbol
Conditions
HS (High-Speed Main)
Mode
Min.
Max.
LS (Low-Speed Main)
Mode
Min.
Max.
LP (Low-Power Main)
Mode
Min.
Max.
Transfer rate
Note 1
1.6 V EVDD0 5.5 V
fMCK/6
Note 2
fMCK/6
Note 2
fMCK/6
Theoretical value of the
5.3
4
0.33
maximum transfer rate
fMCK = fCLKNote 3
Note 1. Note 2.
Note 3.
The transfer rate in the SNOOZE mode is within the range from 4800 to 9600 bps. The following conditions are required for low voltage interface when EVDD0 < VDD. 2.4 V EVDD0 < 2.7 V: 2.6 Mbps max. 1.8 V EVDD0 < 2.4 V: 1.3 Mbps max. 1.6 V EVDD0 < 1.8 V: 0.6 Mbps max. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are as follows. HS (high-speed main) mode: 32 MHz (1.8 V VDD 5.5 V)
4 MHz (1.6 V VDD 5.5 V) LS (low-speed main) mode: 24 MHz (1.8 V VDD 5.5 V)
4 MHz (1.6 V VDD 5.5 V) LP (low-power main) mode: 2 MHz (1.6 V VDD 5.5 V)
Unit bps Mbps
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg).
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RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
Connection in the UART communications with devices operating at same voltage levels
TxDq
RL78 microcontroller
RxDq
Rx User device
Tx
Bit width in the UART communications when interfacing devices operate at the same voltage level (reference)
TxDq RxDq
1/Transfer rate High-/low-bit width Baud rate error tolerance
Remark 1. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14) Remark 2. fMCK: Serial array unit operation clock frequency
(To set this operating clock, set the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13).)
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(2) In SPI (CSI) communications in the master mode with devices operating at same voltage levels with the internal SCKp clock (the ratings below are only applicable to CSI00)
<R>
(TA = -40 to +85°C, 2.7 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Item
Symbol
Conditions
HS
LS
LP
(High-Speed Main) (Low-Speed Main) (Low-Power Main)
Mode
Mode
Mode
Unit
Min. Max. Min. Max. Min. Max.
SCKp cycle time tKCY1 tKCY1 2/fCLK 4.0 V EVDD0 5.5 V 62.5
83.3
1000
ns
2.7 V EVDD0 5.5 V 83.3
125
1000
ns
SCKp high-/ low-level width
tKH1, tKL1
4.0 V EVDD0 5.5 V
tKCY1/2 - 7
tKCY1/2 - 10
tKCY1/2
ns
- 50
2.7 V EVDD0 5.5 V
tKCY1/2 - 10
tKCY1/2 - 15
tKCY1/2
ns
- 50
SIp setup time (to SCKp)Note 1
tSIK1
4.0 V EVDD0 5.5 V 2.7 V EVDD0 5.5 V
23
33
110
ns
33
50
110
ns
SIp hold time (from SCKp)
Note 1
tKSI1 2.7 V EVDD0 5.5 V
10
10
10
ns
Delay time from SCKp to SOp outputNote 2
tKSO1 C = 20 pFNote 3
10
10
10 ns
Note 1.
Note 2. Note 3.
The setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The setting for the SIp setup time becomes "to SCKp" and that for the SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The setting for the delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using the port input mode register g (PIMg) and the port output mode register g (POMg).
Remark 1. The listed times are only valid when the peripheral I/O redirect function of CSI00 is not in use. Remark 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 1) Remark 3. fMCK: Serial array unit operation clock frequency
(To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number (mn = 00).)
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(3) In SPI (CSI) communications in the master mode with devices operating at same voltage levels with the internal SCKp clock
<R>
(TA = -40 to +105°C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Item
Symbol
Conditions
HS
LS
LP
(High-Speed Main) (Low-Speed Main) (Low-Power Main)
Mode
Mode
Mode
Unit
Min. Max. Min. Max. Min. Max.
SCKp cycle time tKCY1 tKCY1 4/fCLK 2.7 V EVDD0 5.5 V
125
166
2000
ns
2.4 V EVDD0 5.5 V
250
250
2000
ns
1.8 V EVDD0 5.5 V
500
500
2000
ns
1.6 V EVDD0 5.5 V 1000
1000
2000
ns
SCKp high-/ low-level width
tKH1, tKL1
4.0 V EVDD0 5.5 V
tKCY1/2 - 12
tKCY1/2 - 21
tKCY1/2
ns
- 50
2.7 V EVDD0 5.5 V
tKCY1/2 - 18
tKCY1/2 - 25
tKCY1/2
ns
- 50
2.4 V EVDD0 5.5 V
tKCY1/2 - 38
tKCY1/2 - 38
tKCY1/2
ns
- 50
1.8 V EVDD0 5.5 V
tKCY1/2 - 50
tKCY1/2 - 50
tKCY1/2
ns
- 50
1.6 V EVDD0 5.5 V
tKCY1/2 - 100
tKCY1/2 - 100
tKCY1/2
ns
- 100
SIp setup time
tSIK1
(to SCKp)Note 1
4.0 V EVDD0 5.5 V 2.7 V EVDD0 5.5 V
44
54
110
ns
44
54
110
ns
2.4 V EVDD0 5.5 V
75
75
110
ns
1.8 V EVDD0 5.5 V
110
110
110
ns
1.6 V EVDD0 5.5 V
220
220
220
ns
SIp hold time (from SCKp)
Note 1
tKSI1 1.6 V EVDD0 5.5 V
19
19
19
ns
Delay time from SCKp to SOp outputNote 2
tKSO1
1.6 V EVDD0 5.5 V C = 30 pFNote 3
25
25
25 ns
Note 1.
Note 2. Note 3.
This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The setting for the SIp setup time becomes "to SCKp" and that for the SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The setting for the delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using the port input mode register g (PIMg) and the port output mode register g (POMg).
Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM and POM numbers (g = 0, 1, 4, 5, 8, 14)
Remark 2. fMCK: Serial array unit operation clock frequency (To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number = 00 to 03, 10 to 13).)
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(4) In SPI (CSI) communications in the slave mode with devices operating at same voltage levels with the SCKp external clock
(TA = -40 to +105°C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
(1/2)
Item
Symbol
Conditions
HS
LS
LP
(High-Speed Main) (Low-Speed Main) (Low-Power Main)
Mode
Mode
Mode
Unit
Min. Max. Min. Max. Min. Max.
SCKp cycle time tKCY2
Note 4
4.0 V EVDD0 5.5 V 20 MHz < fMCK fMCK 20 MHz
8/fMCK 6/fMCK
8/fMCK 6/fMCK
--
ns
6/fMCK
ns
2.7 V EVDD0 5.5 V 16 MHz < fMCK
8/fMCK
8/fMCK
--
ns
fMCK 16 MHz
6/fMCK
6/fMCK
6/fMCK
ns
2.4 V EVDD0 5.5 V
6/fMCK and 500
6/fMCK
6/fMCK
ns
and 500
and 500
1.8 V EVDD0 5.5 V
6/fMCK and 750
6/fMCK
6/fMCK
ns
and 750
and 750
1.6 V EVDD0 5.5 V
6/fMCK
6/fMCK
6/fMCK
ns
and 1500
and 1500
and 1500
SCKp high-/ low-level width
tKH2, tKL2
4.0 V EVDD0 5.5 V 2.7 V EVDD0 5.5 V
tKCY2/2 - 7
tKCY2/2 - 7
tKCY2/2 - 7
ns
tKCY2/2 - 8
tKCY2/2 - 8
tKCY2/2 - 8
ns
1.8 V EVDD0 5.5 V
tKCY2/2 - 18
tKCY2/2 - 18
tKCY2/2
ns
- 18
1.6 V EVDD0 5.5 V
tKCY2/2 - 66
tKCY2/2 - 66
tKCY2/2
ns
- 66
(Notes, Caution, and Remarks are listed on the next page.)
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(4) In SPI (CSI) communications in the slave mode with devices operating at same voltage levels with the SCKp external clock
(TA = -40 to +105°C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
(2/2)
Item
Symbol
Conditions
HS
LS
LP
(High-Speed Main) (Low-Speed Main) (Low-Power Main)
Mode
Mode
Mode
Unit
Min.
Max.
Min.
Max.
Min.
Max.
SIp setup time
tSIK2 2.7 V EVDD0 5.5 V
1/fMCK
1/fMCK
1/fMCK
ns
(to SCKp)Note 1
+ 20
+ 30
+ 30
1.8 V EVDD0 5.5 V
1/fMCK
1/fMCK
1/fMCK
ns
+ 30
+ 30
+ 30
1.6 V EVDD0 5.5 V
1/fMCK
1/fMCK
1/fMCK
ns
+ 40
+ 40
+ 40
SIp hold time
tKSI2 1.8 V EVDD0 5.5 V
1/fMCK
1/fMCK
1/fMCK
ns
(from SCKp)Note 1
+ 31
+ 31
+ 31
1.6 V EVDD0 5.5 V
1/fMCK
1/fMCK
1/fMCK
ns
+ 250
+ 250
+ 250
Delay time from
tKSO2
SCKp to SOp output
Note 2
C = 30 pF 2.7 V EVDD0 5.5 V
Note 3
2.4 V EVDD0 5.5 V
2/fMCK + 44
2/fMCK + 75
2/fMCK + 110
2/fMCK + 110
2/fMCK ns + 110
2/fMCK ns + 110
1.8 V EVDD0 5.5 V
2/fMCK + 110
2/fMCK + 110
2/fMCK ns + 110
1.6 V EVDD0 5.5 V
2/fMCK + 220
2/fMCK + 220
2/fMCK ns + 220
Note 1.
Note 2. Note 3. Note 4.
This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The setting for the SIp setup time becomes "to SCKp" and that for the SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The setting for the delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. C is the load capacitance of the SOp output line. Transfer rate in the SNOOZE mode is 1 Mbps at the maximum.
Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using the port input mode register g (PIMg) and the port output mode register g (POMg).
Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM and POM numbers (g = 0, 1, 4, 5, 8, 14)
Remark 2. fMCK: Serial array unit operation clock frequency (To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number = 00 to 03, 10 to 13).)
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
Connection in the SPI (CSI) communications with devices operating at same voltage levels
SCKp
RL78 microcontroller
SIp
SOp
SCK SO User device SI
Timing of serial transfer in the SPI (CSI) communications with devices operating at same voltage levels when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1
tKL1, 2
tKCY1, 2
tKH1, 2
SCKp SIp
tSIK1, 2
tKSI1, 2
tKSO1, 2
Input data
SOp
Output data
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
Timing of serial transfer in the SPI (CSI) communications with devices operating at same voltage levels when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0
tKH1, 2
tKCY1, 2
tKL1, 2
SCKp SIp
tSIK1, 2
tKSI1, 2
tKSO1, 2
Input data
SOp
Output data
Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31) Remark 2. m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(5) In simplified I2C communications with devices operating at same voltage levels
<R>
(TA = -40 to +105°C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
(1/2)
HS
LS
LP
(High-Speed Main) (Low-Speed Main) (Low-Power Main)
Item
Symbol
Conditions
Mode
Mode
Mode
Unit
Min.
Max.
Min.
Max.
Min.
Max.
SCLr clock frequency fSCL
2.7 V EVDD0 5.5 V, Cb = 50 pF, Rb = 2.7 k
1000
Note 1
1000
Note 1
400Note 1 kHz
1.8 V EVDD0 5.5 V, Cb = 100 pF, Rb = 3 k
400Note 1
400Note 1
400Note 1 kHz
1.8 V EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 k
300Note 1
300Note 1
300Note 1 kHz
1.6 V EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 k
250Note 1
250Note 1
250Note 1 kHz
Hold time when SCLr tLOW 2.7 V EVDD0 5.5 V,
475
is low
Cb = 50 pF, Rb = 2.7 k
475
1150
ns
1.8 V EVDD0 5.5 V,
1150
1150
1150
ns
Cb = 100 pF, Rb = 3 k
1.8 V EVDD0 < 2.7 V,
1550
1550
1550
ns
Cb = 100 pF, Rb = 5 k
1.6 V EVDD0 < 1.8 V,
1850
1850
1850
ns
Cb = 100 pF, Rb = 5 k
Hold time when SCLr tHIGH 2.7 V EVDD0 5.5 V,
475
is high
Cb = 50 pF, Rb = 2.7 k
475
1150
ns
1.8 V EVDD0 5.5 V,
1150
1150
1150
ns
Cb = 100 pF, Rb = 3 k
1.8 V EVDD0 < 2.7 V,
1550
1550
1550
ns
Cb = 100 pF, Rb = 5 k
1.6 V EVDD0 < 1.8 V,
1850
1850
1850
ns
Cb = 100 pF, Rb = 5 k
(Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.)
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(5) In simplified I2C communications with devices operating at same voltage levels
<R>
(TA = -40 to +105°C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
HS
LS
(High-Speed Main) (Low-Speed Main)
Item
Symbol
Conditions
Mode
Mode
Min.
Max.
Min.
Max.
Data setup time (reception)
tSU:DAT 2.7 V EVDD0 5.5 V, Cb = 50 pF, Rb = 2.7 k
1/fMCK + 85
Note 2
1/fMCK + 85
Note 2
1.8 V EVDD0 5.5 V, Cb = 100 pF, Rb = 3 k
1/fMCK + 145
Note 2
1/fMCK + 145
Note 2
1.8 V EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 k
1/fMCK + 230
Note 2
1/fMCK + 230
Note 2
1.6 V EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 k
1/fMCK + 290
Note 2
1/fMCK + 290
Note 2
Data hold time (transmission)
tHD:DAT 2.7 V EVDD0 5.5 V,
0
305
0
305
Cb = 50 pF, Rb = 2.7 k
1.8 V EVDD0 5.5 V,
0
355
0
355
Cb = 100 pF, Rb = 3 k
1.8 V EVDD0 < 2.7 V,
0
405
0
405
Cb = 100 pF, Rb = 5 k
1.6 V EVDD0 < 1.8 V,
0
405
0
405
Cb = 100 pF, Rb = 5 k
Note 1. Note 2.
The listed times must be no greater than fMCK/4. Set fMCK so that it will not exceed the hold time when SCLr is low or high.
(2/2)
LP
(Low-Power Main)
Mode
Unit
Min.
Max.
1/fMCK
ns
+ 145
Note 2
1/fMCK
ns
+ 145
Note 2
1/fMCK
ns
+ 230
Note 2
1/fMCK
ns
+ 290
Note 2
0
305 ns
0
355 ns
0
405 ns
0
405 ns
Caution
Select the normal input buffer and the N-ch open drain output (VDD tolerance (when 30- to 52-pin products)/EVDD tolerance (when 64- to 128-pin products)) mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h (POMh).
(Remarks are listed on the next page.)
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
Connection in the simplified I2C communications with devices operating at same voltage levels
SDAr
RL78 microcontroller
SCLr
VDD Rb
SDA User device
SCL
Timing of serial transfer in the simplified I2C communications with devices operating at same voltage levels
tLOW
1/fSCL
tHIGH
SCLr
SDAr
tHD:DAT
tSU:DAT
Remark 1. Rb[]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance Remark 2. r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), g: PIM number (g = 0, 1, 4, 5, 8, 14), h: POM number (g = 0, 1, 4, 5, 7 to
9, 14) Remark 3. fMCK: Serial array unit operation clock frequency
(To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number = 00 to 03, 10 to 13).)
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(6) In UART communications with devices operating at different voltage levels (1.8 V, 2.5 V, 3 V)
<R>
(TA = -40 to +105°C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Item Symbol
Conditions
HS (High-Speed Main)
Mode
Min.
Max.
LS (Low-Speed Main)
Mode
Min.
Max.
Transfer rate
Reception 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V
fMCK/6
Note 1
fMCK/6
Note 1
Theoretical value of
5.3
4
the maximum transfer
rate
fMCK = fCLKNote 4
2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V
fMCK/6
Note 1
fMCK/6
Note 1
Theoretical value of
5.3
4
the maximum transfer
rate
fMCK = fCLKNote 4
1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V
fMCK/6
Notes 1, 2, 3
fMCK/6
Notes 1, 2
Theoretical value of
5.3
4
the maximum transfer
rate
fMCK = fCLKNote 4
Note 1. Note 2. Note 3.
Note 4.
Transfer rate in the SNOOZE mode is within the range from 4800 to 9600 bps. Use this rate with EVDD0 Vb. The following conditions are required for low voltage interface when EVDD0 < VDD. 2.4 V EVDD0 < 2.7 V: 2.6 Mbps (max.) 1.8 V EVDD0 < 2.4 V: 1.3 Mbps (max.) The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 32 MHz (1.8 V VDD 5.5 V)
4 MHz (1.6 V VDD 5.5 V) LS (low-speed main) mode: 24 MHz (1.8 V VDD 5.5 V)
4 MHz (1.6 V VDD 5.5 V) LP (low-power main) mode: 2 MHz (1.6 V VDD 5.5 V)
(1/2)
LP
(Low-Power Main)
Mode
Unit
Min.
Max.
fMCK/6 bps
Note 1
0.33 Mbps
fMCK/6 bps
Note 1
0.33 Mbps
fMCK/6 bps
Notes 1, 2
0.33 Mbps
Caution
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (when 30- to 52-pin products)/EVDD tolerance (when 64- to 128-pin products)) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
Remark 1. Vb[V]: Communication line voltage Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14) Remark 3. fMCK: Serial array unit operation clock frequency
(To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number = 00 to 03, 10 to 13).) Remark 4. Communications by using UART2 with devices operating at different voltage levels are not possible when the setting of bit 1 (PIOR1) of the peripheral I/O redirection register (PIOR) is 1.
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(6) In UART communications with devices operating at different voltage levels (1.8 V, 2.5 V, 3 V)
(TA = -40 to +105°C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
(2/2)
Item
Transfer rate
Symbol
Conditions
Transmission 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V
Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 1.4 k, Vb = 2.7 V
2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V
Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 2.7 k, Vb = 2.3 V
1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V
HS (High-Speed Main)
Mode
Min.
Max.
Note 1
2.8Note 2
Note 3
1.2Note 4
Notes 5, 6
LS (Low-Speed Main)
Mode
Min.
Max.
Note 1
2.8Note 2
Note 3
1.2Note 4
Notes 5, 6
LP
(Low-Power Main)
Mode
Unit
Min.
Max.
Note 1 bps
2.8Note 2 Mbps
Note 3 bps 1.2Note 4 Mbps
Notes 5, 6 bps
Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 5.5 k, Vb = 1.6 V
0.43
Note 7
0.43
Note 7
0.43 Mbps
Note 7
Note 1.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V
Maximum transfer rate =
1 {-Cb Rb In (1 - 2.2 )} 3
Vb
[bps]
Note 2.
Baud rate error (theoretical value) =
1
- {-Cb Rb In (1 - 2.2 )}
Transfer rate 2
Vb
100 [%]
(
1
Transfer rate
) Num ber of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
This rate is calculated as an example when the conditions described in the "Conditions" column are met. See Note 1 above to calculate the maximum transfer rate under conditions of the customer.
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
Note 3.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V
1
Maximum transfer rate = {-Cb Rb In (1 - 2.0 )} 3 Vb
[bps]
Baud rate error (theoretical value) =
1
- {-Cb Rb In (1 - 2.0 )}
Transfer rate 2
Vb
100 [%]
(
1
Transfer rate
) Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
Note 4.
Note 5. Note 6.
This rate is calculated as an example when the conditions described in the "Conditions" column are met. See Note 3 above to calculate the maximum transfer rate under conditions of the customer. Use this rate with EVDD0 Vb. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V
1
Maximum transfer rate = {-Cb Rb In (1 - 1.5 )} 3 Vb
[bps]
Note 7.
Baud rate error (theoretical value) =
1
- {-Cb Rb In (1 - 1.5 )}
Transfer rate 2
Vb
100 [%]
(
1
) Number of transferred bits
Transfer rate
* This value is the theoretical value of the relative difference between the transmission and reception sides.
This rate is calculated as an example when the conditions described in the "Conditions" column are met. Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer.
Caution
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (when 30- to 52-pin products)/EVDD tolerance (when 64- to 128-pin products)) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
In UART communications with devices operating at different voltage levels
TxDq
RL78 microcontroller
RxDq
Vb Rb
Rx User device
Tx
Bit width in the UART communications with devices operating at different voltage levels (reference)
1/Transfer rate Low-bit width High-bit width Baud rate error tolerance
TxDq
RxDq
1/Transfer rate High-/Low-bit width Baud rate error tolerance
Remark 1. Rb[]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage
Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14) Remark 3. fMCK: Serial array unit operation clock frequency
(To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number = 00 to 03, 10 to 13).) Remark 4. Communications by using UART2 with devices operating at different voltage levels are not possible when the setting of bit 1 (PIOR1) of the peripheral I/O redirection register (PIOR) is 1.
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(7) In SPI (CSI) communications in the master mode with devices operating at different voltage levels (2.5 V or 3 V) with the internal SCKp clock (the ratings below are only applicable to CSI00)
<R>
(TA = -40 to +105°C, 2.7 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
(1/2)
Item
Symbol
Conditions
HS
LS
LP
(High-Speed Main) (Low-Speed Main) (Low-Power Main)
Mode
Mode
Mode
Unit
Min. Max. Min. Max. Min. Max.
SCKp cycle time
tKCY1
tKCY1 2/fCLK
4.0 V EVDD0 5.5
200
V, 2.7 V Vb 4.0 V,
Cb = 20 pF,
Rb = 1.4 k
200
2300
ns
2.7 V EVDD0 < 4.0
300
V, 2.3 V Vb 2.7 V,
Cb = 20 pF,
Rb = 2.7 k
300
2300
ns
SCKp high-level tKH1 4.0 V EVDD0 5.5 V,
width
2.7 V Vb 4.0 V,
Cb = 20 pF, Rb = 1.4 k
tKCY1/2
tKCY1/2
tKCY1/2
ns
- 50
- 50
- 50
2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k
tKCY1/2
tKCY1/2
tKCY1/2
ns
- 120
- 120
- 120
SCKp low-level
tKL1
4.0 V EVDD0 5.5 V,
width
2.7 V Vb 4.0 V,
Cb = 20 pF, Rb = 1.4 k
tKCY1/2
tKCY1/2
tKCY1/2
ns
- 7
- 7
- 50
2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k
tKCY1/2
tKCY1/2
tKCY1/2
ns
- 10
- 10
- 50
SIp setup time
tSIK1 4.0 V EVDD0 5.5 V,
58
(to SCKp)Note 1
2.7 V Vb 4.0 V,
Cb = 20 pF, Rb = 1.4 k
58
479
ns
2.7 V EVDD0 < 4.0 V,
121
121
479
ns
2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
SIp hold time
tKSI1 4.0 V EVDD0 5.5 V,
10
(from SCKp)Note 1
2.7 V Vb 4.0 V,
Cb = 20 pF, Rb = 1.4 k
10
10
ns
2.7 V EVDD0 < 4.0 V,
10
10
10
ns
2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
Delay time from SCKp to SOp outputNote 1
tKSO1
4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k
60
60
60 ns
2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k
130
130
130 ns
(Notes, Caution, and Remarks are listed on the next page.)
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(7) In SPI (CSI) communications in the master mode with devices operating at different voltage levels (2.5 V or 3 V) with the internal SCKp clock (the ratings below are only applicable to CSI00)
<R>
(TA = -40 to +105°C, 2.7 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
HS
LS
(High-Speed Main) (Low-Speed Main)
Item
Symbol
Conditions
Mode
Mode
Min.
Max.
Min.
Max.
SIp setup time
tSIK1 4.0 V EVDD0 5.5 V,
23
23
(to SCKp)Note 2
2.7 V Vb 4.0 V,
Cb = 20 pF, Rb = 1.4 k
2.7 V EVDD0 < 4.0 V,
33
33
2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
SIp hold time
tKSI1 4.0 V EVDD0 5.5 V,
10
10
(from SCKp)Note 2
2.7 V Vb 4.0 V,
Cb = 20 pF, Rb = 1.4 k
2.7 V EVDD0 < 4.0 V,
10
10
2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
Delay time from SCKp tKSO1 4.0 V EVDD0 5.5 V,
10
10
to SOp outputNote 2
2.7 V Vb 4.0 V,
Cb = 20 pF, Rb = 1.4 k
2.7 V EVDD0 < 4.0 V,
10
10
2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
Note 1. Note 2.
This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. This setting applies when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
LP (Low-Power Main)
Mode
Min.
Max.
110
110
10
10
10
10
(2/2)
Unit ns ns ns ns ns ns
Caution
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (when 30- to 52-pin products)/EVDD tolerance (when 64- to 128-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
Remark 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 1) Remark 3. fMCK: Serial array unit operation clock frequency
(To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number = 00).) Remark 4. The listed times are only valid when the peripheral I/O redirect function of CSI00 is not in use.
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(8) In SPI (CSI) communications in the master mode with devices operating at different voltage levels (1.8 V, 2.5 V, or 3 V) with the internal SCKp clock
<R>
(TA = -40 to +105°C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
(1/3)
Item
Symbol
Conditions
HS
LS
LP
(High-Speed Main) (Low-Speed Main) (Low-Power Main)
Mode
Mode
Mode
Unit
Min.
Max.
Min. Max. Min. Max.
SCKp cycle time
tKCY1 tKCY1 4.0 V EVDD0 5.5 V,
300
4/fCLK 2.7 V Vb 4.0 V,
Cb = 30 pF,
Rb = 1.4 k
300
2300
ns
2.7 V EVDD0 < 4.0 V, 500 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k
500
2300
ns
1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 VNote, Cb = 30 pF, Rb = 5.5 k
1150
1150
2300
ns
SCKp high-level width tKH1
4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k
tKCY1/2 - 75
tKCY1/2
tKCY1/2
ns
- 75
- 75
2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k
tKCY1/2 - 170
tKCY1/2
tKCY1/2
ns
- 170
- 170
1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 VNote, Cb = 30 pF, Rb = 5.5 k
tKCY1/2 - 458
tKCY1/2
tKCY1/2
ns
- 458
- 458
SCKp low-level width tKL1
4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k
tKCY1/2 - 12
tKCY1/2
tKCY1/2
ns
- 12
- 50
2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k
tKCY1/2 - 18
tKCY1/2
tKCY1/2
ns
- 18
- 50
1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 VNote, Cb = 30 pF, Rb = 5.5 k
tKCY1/2 - 50
tKCY1/2
tKCY1/2
ns
- 50
- 50
Note
Use this setting with EVDD0 Vb.
Caution
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (when 30- to 52-pin products)/EVDD tolerance (when 64- to 128-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed two pages after the next page.)
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 1418 of 1478
RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(8) In SPI (CSI) communications in the master mode with devices operating at different voltage levels (1.8 V, 2.5 V, or 3 V) with the internal SCKp clock
<R>
(TA = -40 to +105°C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
HS
LS
(High-Speed Main) (Low-Speed Main)
Item
Symbol
Conditions
Mode
Mode
Min.
Max.
Min.
Max.
SIp setup time
tSIK1 4.0 V EVDD0 5.5 V,
81
81
(to SCKp)Note 1
2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
2.7 V EVDD0 < 4.0 V,
177
177
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
1.8 V EVDD0 < 3.3 V,
479
479
1.6 V Vb 2.0 VNote 2,
Cb = 30 pF, Rb = 5.5 k
SIp hold time
tKSI1 4.0 V EVDD0 5.5 V,
19
19
(from SCKp)Note 1
2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
2.7 V EVDD0 < 4.0 V,
19
19
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
1.8 V EVDD0 < 3.3 V,
19
19
1.6 V Vb 2.0 VNote 2,
Cb = 30 pF, Rb = 5.5 k
Delay time from SCKp tKSO1 4.0 V EVDD0 5.5 V,
100
100
to SOp outputNote 1
2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
2.7 V EVDD0 < 4.0 V,
195
195
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
1.8 V EVDD0 < 3.3 V,
483
483
1.6 V Vb 2.0 VNote 2,
Cb = 30 pF, Rb = 5.5 k
Note 1. Note 2.
This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. Use this setting with EVDD0 Vb.
LP (Low-Power Main)
Mode
Min.
Max.
479
479
479
19
19
19
100
195
483
(2/3)
Unit ns ns ns ns ns ns ns ns ns
Caution
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (when 30- to 52-pin products)/EVDD tolerance (when 64- to 128-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the page after the next page.)
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Page 1419 of 1478
RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(8) In SPI (CSI) communications in the master mode with devices operating at different voltage levels (1.8 V, 2.5 V, or 3 V) with the internal SCKp clock
<R>
(TA = -40 to +105°C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
HS
LS
(High-Speed Main) (Low-Speed Main)
Item
Symbol
Conditions
Mode
Mode
Min.
Max.
Min.
Max.
SIp setup time
tSIK1 4.0 V EVDD0 5.5 V,
44
44
(to SCKp)Note 1
2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
2.7 V EVDD0 < 4.0 V,
44
44
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
1.8 V EVDD0 < 3.3 V,
110
110
1.6 V Vb 2.0 VNote 2,
Cb = 30 pF, Rb = 5.5 k
SIp hold time
tKSI1 4.0 V EVDD0 5.5 V,
19
19
(from SCKp)Note 1
2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
2.7 V EVDD0 < 4.0 V,
19
19
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
1.8 V EVDD0 < 3.3 V,
19
19
1.6 V Vb 2.0 VNote 2,
Cb = 30 pF, Rb = 5.5 k
Delay time from SCKp tKSO1 4.0 V EVDD0 5.5 V,
25
25
to SOp outputNote 1
2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
2.7 V EVDD0 < 4.0 V,
25
25
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
1.8 V EVDD0 < 3.3 V,
25
25
1.6 V Vb 2.0 VNote 2,
Cb = 30 pF, Rb = 5.5 k
Note 1. Note 2.
This setting applies when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Use this setting with EVDD0 Vb.
LP (Low-Power Main)
Mode
Min.
Max.
110
110
110
19
19
19
25
25
25
(3/3)
Unit ns ns ns ns ns ns ns ns ns
Caution
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (when 30- to 52-pin products)/EVDD tolerance (when 64- to 128-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 1420 of 1478
RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
Connection in the SPI (CSI) communications with devices operating at different voltage levels
<Master>
SCKp
RL78 microcontroller
SIp
SOp
Vb
Vb
Rb
Rb
SCK
SO User device
SI
Remark 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14)
Remark 3. fMCK: Serial array unit operation clock frequency (To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number = 00).)
Remark 4. Communications by using CSI01 of 48-, 52-, and 64-pin products, and CSI11 and CSI21 with devices operating at different voltage levels are not possible. Use other CSI channels to handle such communications.
Timing of serial transfer in the SPI (CSI) communications in the master mode with devices operating at different voltage levels when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1
tKL1
tKCY1
tKH1
SCKp
tSIK1
tKSI1
SIp
Input data
tKSO1
SOp
Output data
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RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
Timing of serial transfer in the SPI (CSI) communications in the master mode with devices operating at different voltage levels when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0
tKH1
tKCY1 tKL1
SCKp
tSIK1
tKSI1
SIp
Input data
tKSO1
SOp
Output data
Remark 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14)
Remark 2. Communications by using CSI01 of 48-, 52-, and 64-pin products, and CSI11 and CSI21 with devices operating at different voltage levels are not possible. Use other CSI channels to handle such communications.
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RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(9) In SPI (CSI) communications in the slave mode with devices operating at different voltage levels (1.8 V, 2.5 V, or 3 V) with the external SCKp clock
<R>
(TA = -40 to +105°C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
(1/2)
Item Symbol
Conditions
HS
LS
LP
(High-Speed Main) (Low-Speed Main) (Low-Power Main)
Mode
Mode
Mode
Unit
Min. Max. Min. Max. Min. Max.
SCKp cycle time
Note 1
tKCY2
4.0 V EVDD0 5.5 V, 24 MHz < fMCK
14/fMCK
2.7 V Vb 4.0 V
20 MHz < fMCK 24 MHz 12/fMCK
8 MHz < fMCK 20 MHz 10/fMCK
-- 12/fMCK 10/fMCK
--
ns
--
ns
--
ns
4 MHz < fMCK 8 MHz
8/fMCK
8/fMCK
--
ns
fMCK 4 MHz
6/fMCK
6/fMCK
10/fMCK
ns
2.7 V EVDD0 < 4.0 V, 24 MHz < fMCK
20/fMCK
2.3 V Vb 2.7 V,
20 MHz < fMCK 24 MHz 16/fMCK
-- 16/fMCK
--
ns
--
ns
16 MHz < fMCK 20 MHz 14/fMCK
14/fMCK
--
ns
8 MHz < fMCK 16 MHz 12/fMCK
12/fMCK
--
ns
4 MHz < fMCK 8 MHz
8/fMCK
8/fMCK
--
ns
fMCK 4 MHz
6/fMCK
6/fMCK
10/fMCK
ns
1.8 V EVDD0 < 3.3 V, 24 MHz < fMCK
1.6 V Vb 2.0 V
Note 2
20 MHz < fMCK 24 MHz
16 MHz < fMCK 20 MHz
48/fMCK 36/fMCK 32/fMCK
-- 36/fMCK 32/fMCK
--
ns
--
ns
--
ns
8 MHz < fMCK 16 MHz 26/fMCK
26/fMCK
--
ns
4 MHz < fMCK 8 MHz 16/fMCK
16/fMCK
--
ns
fMCK 4 MHz
10/fMCK
10/fMCK
10/fMCK
ns
(Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.)
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RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(9) In SPI (CSI) communications in the slave mode with devices operating at different voltage levels (1.8 V, 2.5 V, or 3 V) with the external SCKp clock
<R>
(TA = -40 to +105°C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
(2/2)
HS
LS
LP
(High-Speed Main) (Low-Speed Main) (Low-Power Main)
Item
Symbol
Conditions
Mode
Mode
Mode
Unit
Min.
Max.
Min.
Max.
Min.
Max.
SCKp high-/low-level tKH2, 4.0 V EVDD0 5.5 V,
tKCY2/2
tKCY2/2
tKCY2/2
ns
width
tKL2
2.7 V Vb 4.0 V
- 12
- 12
- 50
2.7 V EVDD0 < 4.0 V,
tKCY2/2
tKCY2/2
tKCY2/2
ns
2.3 V Vb 2.7 V
- 18
- 18
- 50
1.8 V EVDD0 < 3.3 V,
tKCY2/2
tKCY2/2
tKCY2/2
ns
1.6 V Vb 2.0 VNote 2
- 50
- 50
- 50
SIp setup time
tSIK2 4.0 V EVDD0 5.5 V,
1/fMCK
1/fMCK
1/fMCK
ns
(to SCKp)Note 3
2.7 V Vb 4.0 V
+ 20
+ 20
+ 30
2.7 V EVDD0 < 4.0 V,
1/fMCK
1/fMCK
1/fMCK
ns
2.3 V Vb 2.7 V
+ 20
+ 20
+ 30
1.8 V EVDD0 < 3.3 V,
1/fMCK
1/fMCK
1/fMCK
ns
1.6 V Vb 2.0 VNote 2
+ 30
+ 30
+ 30
SIp hold time (from SCKp)Note 3
tKSI2
1/fMCK
1/fMCK
1/fMCK
ns
+ 31
+ 31
+ 31
Delay time from SCKp tKSO2 to SOp outputNote 4
4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k
2/fMCK + 120
2/fMCK + 120
2/fMCK ns + 573
2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k
2/fMCK + 214
2/fMCK + 214
2/fMCK ns + 573
1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 VNote 2, Cb = 30 pF, Rb = 5.5 k
2/fMCK + 573
2/fMCK + 573
2/fMCK ns + 573
Note 1. Note 2. Note 3.
Note 4.
Transfer rate in the SNOOZE mode: 1 Mbps (max.) Use this setting with EVDD0 Vb. This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" and SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. This setting applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (for the 30- to 52-pin products)/EVDD tolerance (for the 64- to 128-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 1424 of 1478
RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
Connection in the SPI (CSI) communications with devices operating at different voltage levels
<Slave>
SCKp
RL78 microcontroller
SIp
SOp
Vb Rb
SCK SO User device SI
Remark 1. Rb[]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14)
Remark 3. fMCK: Serial array unit operation clock frequency (To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number = 00, 01, 02, 10, 12 and 13).)
Remark 4. Communications by using CSI01 of 48-, 52-, and 64-pin products, and CSI11 and CSI21 with devices operating at different voltage levels are not possible. Use other CSI channels to handle such communications.
Timing of serial transfer in the SPI (CSI) communications in the slave mode with devices operating at different voltage levels when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1
tKCY2
tKL2
tKH2
SCKp SIp
tSIK2
tKSI2
tKSO2
Input data
SOp
Output data
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RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
Timing of serial transfer in the SPI (CSI) communications in the slave mode with devices operating at different voltage levels when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0
tKH2
tKCY2 tKL2
SCKp SIp
tSIK2
tKSI2
tKSO2
Input data
SOp
Output data
Remark 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14)
Remark 2. Communications by using CSI01 of 48-, 52-, and 64-pin products, and CSI11 and CSI21 with devices operating at different voltage levels are not possible. Use other CSI channels to handle such communications.
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RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(10) Simplified I2C communications with devices operating at different voltage levels (1.8 V, 2.5 V, or 3 V)
<R>
(TA = -40 to +105°C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
(1/2)
HS
LS
LP
(High-Speed Main) (Low-Speed Main) (Low-Power Main)
Item
Symbol
Conditions
Mode
Mode
Mode
Unit
Min. Max. Min. Max. Min. Max.
SCLr clock frequency fSCL 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k
1000
Note 1
1000
Note 1
300 kHz
Note 1
2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k
1000
Note 1
1000
Note 1
300 kHz
Note 1
4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k
400
Note 1
400
Note 1
300 kHz
Note 1
2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k
400
Note 1
400
Note 1
300 kHz
Note 1
1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 VNote 2, Cb = 100 pF, Rb = 5.5 k
300
Note 1
300
Note 1
300 kHz
Note 1
Hold time when SCLr is tLOW 4.0 V EVDD0 5.5 V,
475
low
2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
475
1550
ns
2.7 V EVDD0 < 4.0 V,
475
2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
475
1550
ns
4.0 V EVDD0 5.5 V,
1150
1550
1550
ns
2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
2.7 V EVDD0 < 4.0 V,
1150
1550
1550
ns
2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
1.8 V EVDD0 < 3.3 V,
1550
1550
1550
ns
1.6 V Vb 2.0 VNote 2,
Cb = 100 pF, Rb = 5.5 k
Hold time when SCLr is tHIGH 4.0 V EVDD0 5.5 V,
245
245
610
ns
high
2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
2.7 V EVDD0 < 4.0 V,
200
200
610
ns
2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
4.0 V EVDD0 5.5 V,
675
675
610
ns
2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
2.7 V EVDD0 < 4.0 V,
600
600
610
ns
2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
1.8 V EVDD0 < 3.3 V,
610
610
610
ns
1.6 V Vb 2.0 VNote 2,
Cb = 100 pF, Rb = 5.5 k
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(10) Simplified I2C communications with devices operating at different voltage levels (1.8 V, 2.5 V, and 3 V)
<R>
(TA = -40 to +105°C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
HS
LS
(High-Speed Main) (Low-Speed Main)
Item
Symbol
Conditions
Mode
Mode
Min.
Max.
Min.
Max.
Data setup time (reception)
tSU:DAT 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k
1/fMCK + 135
Note 3
1/fMCK + 135
Note 3
2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k
1/fMCK + 135
Note 3
1/fMCK + 135
Note 3
4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k
1/fMCK + 190
Note 3
1/fMCK + 190
Note 3
2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k
1/fMCK + 190
Note 3
1/fMCK + 190
Note 3
1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 VNote 2, Cb = 100 pF, Rb = 5.5 k
1/fMCK + 190
Note 3
1/fMCK + 190
Note 3
Data hold time (transmission)
tHD:DAT 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k
0
305
0
305
2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k
0
305
0
305
4.0 V EVDD0 5.5 V,
0
355
0
355
2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
2.7 V EVDD0 < 4.0 V,
0
355
0
355
2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
1.8 V EVDD0 < 3.3 V,
0
405
0
405
1.6 V Vb 2.0 VNote 2,
Cb = 100 pF, Rb = 5.5 k
Note 1. Note 2. Note 3.
The listed times must be no greater than fMCK/4. Use this setting with EVDD0 Vb. Set fMCK so that it will not exceed the hold time when SCLr is low or high.
LP (Low-Power Main)
Mode
Min.
Max.
1/fMCK + 190
Note 3
1/fMCK + 190
Note 3
1/fMCK + 190
Note 3
1/fMCK + 190
Note 3
1/fMCK + 190
Note 3
0
305
0
305
0
355
0
355
0
405
(2/2)
Unit ns ns ns ns ns ns ns ns ns ns
Caution
Select the TTL input buffer and the N-ch open drain output (VDD tolerance (for the 30- to 52-pin products)/EVDD tolerance (for the 64- to 128-pin products)) mode for the SDAr pin and the N-ch open drain output (VDD tolerance (for the 30- to 52-pin products)/EVDD tolerance (for the 64- to 128-pin products)) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
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RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
Connection in the I2C communications with devices operating at different voltage levels
SDAr
RL78 microcontroller
SCLr
Vb
Vb
Rb
Rb
SDA
User device
SCL
Timing of serial transfer in the simplified I2C communications with devices operating at different voltage levels
tLOW
1/fSCL
tHIGH
SCLr
SDAr
tHD:DAT
tSU:DAT
Remark 1. Rb[]: Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage
Remark 2. r: IIC number (r = 00, 01, 10, 20, 30, 31), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14) Remark 3. fMCK: Serial array unit operation clock frequency
(To set this operating clock, use the CKSmn bit in the serial mode register mn (SMRmn) (m: Unit number, n: Channel number = 00, 01, 02, 10, 12 and 13).)
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
37.5.2 Serial interface UARTA
(TA = -40 to +105°C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Transfer rate
200
0
19200
bps
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remark g: PIM number (g = 3, 4, 7, 8), h: POM number (h = 3, 4, 7, 8, 12)
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RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
37.5.3 Serial interface IICA
(1) I2C standard mode
(TA = -40 to +105°C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Item
Symbol
Conditions
Min.
Typ.
Max. Unit
SCLA0 clock frequency
fSCL
Standard mode: fCLK 1 MHz
0
100
kHz
Setup time of restart condition
tSU:STA
4.7
µs
Hold timeNote 1
tHD:STA
4.0
µs
Hold time when SCLA0 is low
tLOW
4.7
µs
Hold time when SCLA0 is high
tHIGH
4.0
µs
Data setup time (reception)
tSU:DAT
250
ns
Data hold time (transmission)Note 2
tHD:DAT
0
3.45
µs
Setup time of stop condition
tSU:STO
4.0
µs
Bus-free time
tBUF
4.7
µs
Note 1. Note 2.
The first clock pulse is generated after this period when the start or restart condition is detected. The maximum value of tHD:DAT applies to normal transfer. The clock stretching will be inserted on reception of an acknowledgment (ACK) signal.
Caution The listed frequency and times apply even when bit 2 (PIOR2) in the peripheral I/O redirection register (PIOR) is 1. In such cases, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination.
Remark The maximum value of communication line capacitance (Cb) and communication line pull-up resistor (Rb) are as follows. Cb = 400 pF, Rb = 2.7 k
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(2) I2C fast mode
(TA = -40 to +105°C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Item
Symbol
Conditions
Min.
Typ.
Max. Unit
SCLA0 clock frequency
fSCL
Fast mode: fCLK 3.5 MHz
0
1.8 V EVDD0 5.5 V
400
kHz
Setup time of restart condition
tSU:STA
1.8 V EVDD0 5.5 V
0.6
µs
Hold timeNote 1
tHD:STA
1.8 V EVDD0 5.5 V
0.6
µs
Hold time when SCLA0 is low
tLOW
1.8 V EVDD0 5.5 V
1.3
µs
Hold time when SCLA0 is high
tHIGH
1.8 V EVDD0 5.5 V
0.6
µs
Data setup time (reception) Data hold time (transmission)Note 2
tSU:DAT tHD:DAT
1.8 V EVDD0 5.5 V 1.8 V EVDD0 5.5 V
100
ns
0
0.9
µs
Setup time of stop condition
tSU:STO
1.8 V EVDD0 5.5 V
0.6
µs
Bus-free time
tBUF
1.8 V EVDD0 5.5 V
1.3
µs
Note 1. Note 2.
The first clock pulse is generated after this period when the start or restart condition is detected. The maximum value of tHD:DAT applies to normal transfer. The clock stretching will be inserted on reception of an acknowledgment (ACK) signal.
Caution The values in the above table apply even when bit 2 (PIOR2) in the peripheral I/O redirection register (PIOR) is 1. In such cases, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination.
Remark The maximum value of communication line capacitance (Cb) and communication line pull-up resistor (Rb) are as follows. Cb = 320 pF, Rb = 1.1 k
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(3) I2C fast mode plus
(TA = -40 to +105°C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Item
Symbol
Conditions
Min.
Typ.
Max. Unit
SCLA0 clock frequency
fSCL
Fast mode plus: fCLK 10 MHz
0
2.7 V EVDD0 5.5 V
1000 kHz
Setup time of restart condition
tSU:STA
2.7 V EVDD0 5.5 V
0.26
µs
Hold timeNote 1
tHD:STA
2.7 V EVDD0 5.5 V
0.26
µs
Hold time when SCLA0 is low
tLOW
2.7 V EVDD0 5.5 V
0.5
µs
Hold time when SCLA0 is high
tHIGH
2.7 V EVDD0 5.5 V
0.26
µs
Data setup time (reception) Data hold time (transmission)Note 2
tSU:DAT tHD:DAT
2.7 V EVDD0 5.5 V 2.7 V EVDD0 5.5 V
50
ns
0
0.45
µs
Setup time of stop condition
tSU:STO
2.7 V EVDD0 5.5 V
0.26
µs
Bus-free time
tBUF
2.7 V EVDD0 5.5 V
0.5
µs
Note 1. Note 2.
The first clock pulse is generated after this period when the start or restart condition is detected. The maximum value of tHD:DAT applies to normal transfer. The clock stretching will be inserted on reception of an acknowledgment (ACK) signal.
Caution The values in the above table apply even when bit 2 (PIOR2) in the peripheral I/O redirection register (PIOR) is 1. In such cases, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination.
Remark The maximum value of communication line capacitance (Cb) and communication line pull-up resistor (Rb) are as follows. Cb = 120 pF, Rb = 1.1 k
IICA serial transfer timing
SCLAn
tLOW tR
tHD:DAT tHD:STA
SDAAn
tBUF
Stop
Start
condition condition
Remark n = 0, 1
tHIGH tF tSU:DAT
tSU:STA
tHD:STA
Restart condition
tSU:STO
Stop condition
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RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
37.6
Analog Characteristics
37.6.1 A/D converter characteristics
<R>
(1) Normal modes 1 and 2
(TA = -40 to +105°C, 2.4 V AVREFP VDD 5.5 V, VSS = 0 V,
reference voltage (+) = AVREFP (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM (ADREFM = 1),
target pins: ANI2 to ANI14, internal reference voltage, and temperature sensor output voltage)
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Resolution
RES
8
12
Bit
Conversion clock Overall errorNotes 1, 3, 4, 5
fAD AINL
4.5 V AVREFP = VDD 5.5 V 2.7 V AVREFP = VDD 5.5 V
1
32
MHz
±7.5
LSB
±9.0
LSB
Conversion timeNote 6
tCONV
2.4 V AVREFP = VDD 5.5 V 4.5 V AVREFP = VDD 5.5 V 2.7 V AVREFP = VDD 5.5 V
±9.0
LSB
2.0
µs
2.0
µs
Zero-scale errorNotes 1, 2, 3, 4, 5 EZS
2.4 V AVREFP = VDD 5.5 V 4.5 V AVREFP = VDD 5.5 V 2.7 V AVREFP = VDD 5.5 V
2.0
µs
±0.17 %FSR
±0.21 %FSR
Full-scale errorNotes 1, 2, 3, 4, 5 EFS
2.4 V AVREFP = VDD 5.5 V 4.5 V AVREFP = VDD 5.5 V 2.7 V AVREFP = VDD 5.5 V
±0.21 ±0.17 ±0.21
%FSR %FSR %FSR
Integral linearity errorNotes 1, 4, 5 ILE
2.4 V AVREFP = VDD 5.5 V 4.5 V AVREFP = VDD 5.5 V 2.7 V AVREFP = VDD 5.5 V
±0.21 ±3.0 ±3.0
%FSR LSB LSB
Differential linearity errorNote 1 DLE
2.4 V AVREFP = VDD 5.5 V 4.5 V AVREFP = VDD 5.5 V 2.7 V AVREFP = VDD 5.5 V
±3.0
LSB
±1.0
LSB
±1.0
LSB
2.4 V AVREFP = VDD 5.5 V
±1.0
LSB
Analog input voltage
VAIN
0
AVREFP
V
Note 1. Note 2. Note 3. Note 4.
Note 5.
Note 6.
This value does not include the quantization error (±1/2 LSB). This value is indicated as a ratio (%FSR) to the full-scale value. When pins ANI16 to ANI31 are selected as the target pins for conversion, the maximum values are as follows. Overall error: Add ±3 LSB to the maximum value. Zero-scale/full-scale error: Add ±0.04%FSR to the maximum value. When reference voltage (+) = VDD and reference voltage (-) = VSS, the maximum values are as follows. Overall error: Add ±10 LSB to the maximum value. Zero-scale/full-scale error: Add ±0.25%FSR to the maximum value. Integral linearity error: Add ±4 LSB to the maximum value. When AVREFP < VDD, the maximum values are as follows. Overall error/zero-scale error/full-scale error: Add (±0.75 LSB × (VDD voltage (V) - AVREFP voltage (V)) to the maximum
value. Integral linearity error: Add (±0.2 LSB × (VDD voltage (V) - AVREFP voltage (V)) to the maximum value. When the internal reference voltage or the temperature sensor output voltage is selected as the target for conversion, the sampling time must be at least 5 µs. Accordingly, use standard mode 2 with the longer sampling time.
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RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
<R>
(2) Low-voltage modes 1 and 2
(TA = -40 to +105°C, 1.6 V AVREFP VDD 5.5 V, VSS = 0 V,
reference voltage (+) = AVREFP (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM (ADREFM = 1),
target pins ANI2 to ANI14, internal reference voltage, and temperature sensor output voltage)
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Resolution
RES
8
12
Bit
Conversion clock Overall errorNotes 1, 3, 4, 5
fAD AINL
2.7 V AVREFP = VDD 5.5 V 2.4 V AVREFP = VDD 5.5 V
1
24
MHz
±9
LSB
±9
LSB
1.8 V AVREFP = VDD 5.5 V
±11.5
LSB
Conversion timeNote 6
tCONV
1.6 V AVREFP = VDD 5.5 V 2.7 V AVREFP = VDD 5.5 V 2.4 V AVREFP = VDD 5.5 V
±12.0
LSB
3.33
µs
5.0
µs
1.8 V AVREFP = VDD 5.5 V
10.0
µs
Zero-scale errorNotes 1, 2, 3, 4, 5 EZS
1.6 V AVREFP = VDD 5.5 V 2.7 V AVREFP = VDD 5.5 V 2.4 V AVREFP = VDD 5.5 V
20.0
µs
±0.21 %FSR
±0.21 %FSR
1.8 V AVREFP = VDD 5.5 V
±0.27 %FSR
Full-scale errorNotes 1, 2, 3, 4, 5 EFS
1.6 V AVREFP = VDD 5.5 V 2.7 V AVREFP = VDD 5.5 V 2.4 V AVREFP = VDD 5.5 V
±0.28 ±0.21 ±0.21
%FSR %FSR %FSR
1.8 V AVREFP = VDD 5.5 V
±0.27 %FSR
Integral linearity errorNotes 1, 4, 5 ILE
1.6 V AVREFP = VDD 5.5 V 2.7 V AVREFP = VDD 5.5 V 2.4 V AVREFP = VDD 5.5 V
±0.28 ±4.0 ±4.0
%FSR LSB LSB
1.8 V AVREFP = VDD 5.5 V
±4.5
LSB
Differential linearity errorNote 1 DLE
1.6 V AVREFP = VDD 5.5 V 2.7 V AVREFP = VDD 5.5 V 2.4 V AVREFP = VDD 5.5 V
±4.5
LSB
±1.5
LSB
±1.5
LSB
1.8 V AVREFP = VDD 5.5 V
±2.0
LSB
1.6 V AVREFP = VDD 5.5 V
±2.0
LSB
Analog input voltage
VAIN
0
AVREFP
V
Note 1. Note 2. Note 3.
Note 4.
Note 5.
This value does not include the quantization error (±1/2 LSB). This value is indicated as a ratio (%FSR) to the full-scale value. When pins ANI16 to ANI31 are selected as the target pins for conversion, the maximum values are as follows. Overall error: Add ±3 LSB to the maximum value. Zero-scale/full-scale error: Add ±0.04%FSR to the maximum value. When reference voltage (+) = VDD and reference voltage (-) = VSS, the maximum values are as follows. Overall error: Add ±10 LSB to the maximum value. Zero-scale/full-scale error: Add ±0.25%FSR to the maximum value. Integral linearity error: Add ±4 LSB to the maximum value. When AVREFP < VDD, the maximum values are as follows. Overall error/zero-scale error/full-scale error: Add (±0.75 LSB × (VDD voltage (V) - AVREFP voltage (V)) to the maximum
value. Integral linearity error: Add (±0.2 LSB × (VDD voltage (V) - AVREFP voltage (V)) to the maximum value.
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
Note 6.
When the internal reference voltage or the temperature sensor output voltage is selected as the target for conversion, the sampling time must be at least 5 µs. Accordingly, use standard mode 2 with the longer sampling time, and use the conversion clock (fAD) of no more than 16 MHz.
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
<R>
(3) When the internal reference voltage is selected as reference voltage (+)
(TA = -40 to +105°C, 1.8 V VDD 5.5 V, VSS = 0 V, low-voltage modes 1 and 2,
reference voltage (+) = internal reference voltage (ADREFP1 = 1, ADREFP0 = 0),
reference voltage (-) = AVREFM (ADREFM = 1)
Item
Symbol
Conditions
Min.
Resolution
RES
Conversion clock
fAD
8-bit resolution
1.6 V VDD 5.5 V
1
Zero-scale errorNotes 1, 2
EZS
8-bit resolution
1.6 V VDD 5.5 V
Integral linearity errorNote 1 ILE
8-bit resolution
1.6 V VDD 5.5 V
Differential linearity errorNote 1 DLE 8-bit resolution
1.6 V VDD 5.5 V
Analog input voltage
VAIN
0
<R>
Note 1. Note 2. Note 3. Note 4.
This value does not include the quantization error (±1/2 LSB). This value is indicated as a ratio (%FSR) to the full-scale value. Refer to 37.6.2 Temperature sensor/internal reference voltage characteristics. When reference voltage (-) is selected as VSS, the maximum values are as follows. Zero-scale error: Add ±0.35%FSR to the maximum value. Integral linearity error: Add ±0.5 LSB to the maximum value.
Typ. 8
±1.0
Max.
2 ±0.6 ±2.0
VBGR
Note 3
Unit Bit MHz %FSR LSB LSB V
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RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
37.6.2 Temperature sensor/internal reference voltage characteristics
(TA = -40 to +105°C, 1.8 V VDD 5.5 V, VSS = 0 V)
Item
Symbol
Conditions
Min.
Typ.
Temperature sensor output VTMPS25 Setting ADS register = 80H, TA = +25°C
1.05
voltage
Internal reference voltage VBGR
Setting ADS register = 81H
1.42
1.48
Temperature coefficient
FVTMPS Temperature dependency of the temperature
-3.3
sensor voltage
Operation stabilization wait tAMP
5
time
Max. 1.54
Unit V
V mV/°C
µs
37.6.3 D/A converter characteristics
(TA = -40 to +105°C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Resolution
RES
8
Bit
Overall error
AINL
Rload = 8 M
1.8 V VDD 5.5 V
±2.5
LSB
Rload = 4 M
1.8 V VDD 5.5 V
±2.5
LSB
Settling time
tSET
Cload = 20 pF
2.7 V VDD 5.5 V
3
µs
1.6 V VDD 5.5 V
6
µs
37.6.4 Comparator characteristics
(TA = -40 to +105°C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Item
Symbol
Conditions
Min.
Input voltage range IVREF
Input to the IVREF0 and IVREF1 pins
0
C0LVL = 0, C1LVL = 0
Input to the IVREF0 and IVREF1 pins
1.4
C0LVL = 1, C1LVL = 1
IVCMP
Input to the IVCMP0 and IVCMP1 pins
-0.3
Output delay
td
VDD = 3.0 V,
High-speed mode
Input slew rate > 1 V/µs
Low-speed mode
Offset voltage
--
High-speed mode
Low-speed mode
Operation stabilization tCMP
30
wait time
Internal reference
VBGR2
1.4
voltage
Typ.
Max.
Unit
VDD - 1.4
V
VDD
V
VDD + 0.3
V
1.5
µs
3.0
µs
50
mV
40
mV
µs
1.6
V
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RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
37.6.5 POR circuit characteristics
(TA = -40 to +105°C, VSS = 0 V)
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Detection voltage Minimum pulse widthNote
VPOR, VPDR TPW
1.43
1.50
1.57
V
300
µs
Note
This width is the minimum time required for a POR reset when VDD falls below VPDR. This width is also the
minimum time required for a POR reset from when VDD falls below 0.7 V to when VDD exceeds VPOR in the
STOP mode or while the main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in
the clock operation status control register (CSC).
Supply voltage (VDD)
TPW
VPOR
VPDR or 0.7 V
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
37.6.6 LVD circuit characteristics
(1) LVD0 Detection Voltage in the Reset Mode and Interrupt Mode
<R> (TA = -40 to +105°C, VPDR VDD 5.5 V, VSS = 0 V)
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Detection
Supply voltage level VLVD00 The power supply voltage is rising. 3.84
3.96
4.08
V
voltage
The power supply voltage is falling. 3.76
3.88
4.00
V
VLVD01 The power supply voltage is rising. 2.88
2.97
3.06
V
The power supply voltage is falling. 2.82
2.91
3.00
V
VLVD02 The power supply voltage is rising. 2.59
2.67
2.75
V
The power supply voltage is falling. 2.54
2.62
2.70
V
VLVD03 The power supply voltage is rising. 2.31
2.38
2.45
V
The power supply voltage is falling. 2.26
2.33
2.40
V
VLVD04 The power supply voltage is rising. 1.84
1.90
1.95
V
The power supply voltage is falling. 1.80
1.86
1.91
V
VLVD05 The power supply voltage is rising. 1.64
1.69
1.74
V
The power supply voltage is falling. 1.60
1.65
1.70
V
Minimum pulse width
tLW
500
µs
Detection delay time
500
µs
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CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
(2) LVD1 Detection Voltage of Reset Mode and Interrupt Mode
<R> (TA = -40 to +105°C, VPDR VDD 5.5 V, VSS = 0 V)
Item
Symbol
Conditions
Min.
Detection voltage
Supply voltage level VLVD10
The power supply voltage is rising. 4.08 The power supply voltage is falling. 4.00
VLVD11
The power supply voltage is rising. 3.88
The power supply voltage is falling. 3.80
VLVD12
The power supply voltage is rising. 3.68
The power supply voltage is falling. 3.60
VLVD13
The power supply voltage is rising. 3.48
The power supply voltage is falling. 3.40
VLVD14
The power supply voltage is rising. 3.28
The power supply voltage is falling. 3.20
VLVD15
The power supply voltage is rising. 3.07
The power supply voltage is falling. 3.00
VLVD16
The power supply voltage is rising. 2.91
The power supply voltage is falling. 2.85
VLVD17
The power supply voltage is rising. 2.76
The power supply voltage is falling. 2.70
VLVD18
The power supply voltage is rising. 2.61
The power supply voltage is falling. 2.55
VLVD19
The power supply voltage is rising. 2.45
The power supply voltage is falling. 2.40
VLVD110 The power supply voltage is rising. 2.35
The power supply voltage is falling. 2.30
VLVD111 The power supply voltage is rising. 2.25
The power supply voltage is falling. 2.20
VLVD112 The power supply voltage is rising. 2.15
The power supply voltage is falling. 2.10
VLVD113 The power supply voltage is rising. 2.05
The power supply voltage is falling. 2.00
VLVD114 The power supply voltage is rising. 1.94
The power supply voltage is falling. 1.90
VLVD115
Note
The power supply voltage is rising. The power supply voltage is falling.
1.84 1.80
VLVD116
Note
The power supply voltage is rising. The power supply voltage is falling.
1.74 1.70
VLVD117
Note
The power supply voltage is rising. The power supply voltage is falling.
1.64 1.60
Minimum pulse width
tLW
500
<R>
Detection delay time
Note
This setting can only be used when LVD0 is disabled.
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Typ.
Max.
Unit
4.16
4.24
V
4.08
4.16
V
3.96
4.04
V
3.88
3.96
V
3.75
3.82
V
3.67
3.74
V
3.55
3.62
V
3.49
3.54
V
3.35
3.42
V
3.27
3.34
V
3.13
3.19
V
3.06
3.12
V
2.97
3.03
V
2.91
2.97
V
2.815
2.87
V
2.755
2.81
V
2.66
2.71
V
2.60
2.65
V
2.50
2.55
V
2.45
2.50
V
2.40
2.45
V
2.35
2.40
V
2.295
2.34
V
2.25
2.29
V
2.195
2.24
V
2.145
2.19
V
2.09
2.13
V
2.04
2.08
V
1.98
2.02
V
1.94
1.98
V
1.875
1.91
V
1.835
1.87
V
1.775
1.81
V
1.735
1.77
V
1.67
1.70
V
1.63
1.66
V
µs
500
µs
Page 1441 of 1478
RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
37.6.7 Power supply voltage rising slope characteristics
(TA = -40 to +105°C, VSS = 0 V)
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Power supply voltage rising slope
SVDD
54
V/ms
Caution Make sure to keep the internal reset state by the LVD0 circuit or an external reset until VDD reaches the operating voltage range shown in AC characteristics.
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 1442 of 1478
RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
37.7
RAM Data Retention Characteristics
(TA = -40 to +105°C, VSS = 0V)
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Data retention supply voltage VDDDR
1.43Note
5.5
V
Note
This voltage depends on the POR detection voltage. When the voltage drops, the data in RAM are retained until a POR is applied, but are not retained following a POR.
VDD
STOP instruction execution Standby release signal (interrupt request)
STOP mode RAM data retention
VDDDR
Operation mode
37.8
Flash Memory Programming Characteristics
(TA = -40 to +105°C, 1.6 V VDD 5.5 V, VSS = 0 V)
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
CPU/peripheral hardware clock frequency Number of code flash rewritesNotes 1, 2, 3
Number of data flash rewritesNotes 1, 2, 3
fCLK
1
32
MHz
Cerwr
Retained for 20 years TA = 85°C
1,000
Times
Retained for 1 year TA = 25°C
1,000,000
Retained for 5 years TA = 85°C
100,000
Retained for 20 years TA = 85°C
10,000
Note 1. Note 2. Note 3.
1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. The listed numbers of times apply when using flash memory programmer and Renesas Electronics self programming library. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation.
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 1443 of 1478
RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
<R>
(1) Code flash memory
(TA = -40 to +105°C, 1.6 V VDD 5.5 V, VSS = 0 V)
Item
Symbol
fCLK = 1 MHz Min. Typ. Max.
fCLK = 2 MHz, 3 MHz 4 MHz fCLK < 8 MHz 8 MHz fCLK < 32 MHz
fCLK = 32 MHz
Unit
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Programming 4 bytes tP4 time
-- 74.7 656.5 -- 51.0 464.6 -- 41.7 384.8 -- 37.1 346.2 -- 34.2 321.9 µs
Erasure time 2 Kbytes tE2K
-- 10.4 312.2 -- 7.7 258.5 -- 6.4 231.8 -- 5.8 218.4 -- 5.6 214.4 ms
Blank checking 4 bytes tBC4 time
2 Kbytes tBC2K
-- -- 38.4 -- -- 19.2 -- -- 13.1 -- -- 10.2 -- -- 8.3 µs -- -- 2618.9 -- -- 1309.5 -- -- 658.3 -- -- 332.8 -- -- 234.1 µs
Time taken to forcibly stop tSED the erasure
-- -- 18.0 -- -- 14.0 -- -- 12.0 -- -- 11.0 -- -- 10.3 µs
Security setting time
tAWSSAS -- 18.2 526.2 -- 14.4 469.2 -- 12.5 441.1 -- 11.6 427.1 -- 11.3 422.6 ms
Time until programming -- starts following cancellation of the STOP instruction
20 --
--
20 --
--
20 --
--
20 --
--
20 --
-- µs
Caution The listed values do not include the time until the operations of the flash memory start following execution of an instruction by software.
<R>
(2) Data flash memory
(TA = -40 to +105°C, 1.6 V VDD 5.5 V, VSS = 0 V)
Item
Symbol
fCLK = 1 MHz Min. Typ. Max.
fCLK = 2 MHz, 3 MHz 4 MHz fCLK < 8 MHz 8 MHz fCLK < 32 MHz
fCLK = 32 MHz
Unit
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Programming 1 byte tP4 time
-- 74.7 656.5 -- 51.0 464.6 -- 41.7 384.8 -- 37.1 346.2 -- 34.2 321.9 µs
Erasure time 256
tE2K
bytes
-- 7.8 259.2 -- 6.4 232.0 -- 5.8 218.5 -- 5.5 211.8 -- 5.4 209.7 ms
Blank checking time
1 byte
256 bytes
tBC4 tBC2K
-- -- 38.4 -- -- 19.2 -- -- 13.1 -- -- 10.2 -- -- 8.3 µs -- -- 1326.1 -- -- 663.1 -- -- 335.1 -- -- 171.2 -- -- 121.0 µs
Time taken to forcibly stop tSED the erasure
-- -- 18.0 -- -- 14.0 -- -- 12.0 -- -- 11.0 -- -- 10.3 µs
Time until programming -- starts following cancellation of the STOP instruction
20 --
--
20 --
--
20 --
--
20 --
--
20 --
-- µs
Time until reading starts -- following setting DFLEN to 1
0.25 --
-- 0.25 --
-- 0.25 --
-- 0.25 --
-- 0.25 --
-- ns
Caution The listed values do not include the time until the operations of the flash memory start following execution of an instruction by software.
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 1444 of 1478
RL78/G23
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
37.9
Dedicated Flash Memory Programmer Communication (UART)
(TA = -40 to +105°C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Item
Symbol
Conditions
Min.
Transfer rate
During serial programming
115,200
Typ.
Max.
Unit
1,000,000 bps
37.10 Timing of Entry to Flash Memory Programming Modes
(TA = -40 to +105°C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Item
Symbol
Conditions
Min. Typ. Max. Unit
Time to complete the communication for the tSUINIT initial setting after the external reset is released
POR and LVD reset must be released before the external reset is released.
100 ms
Time to release the external reset after the tSU
POR and LVD reset must be released
10
µs
TOOL0 pin is set to the low level
before the external reset is released.
Time to hold the TOOL0 pin at the low level tHD
POR and LVD reset must be released
1
ms
after the external reset is released
before the external reset is released.
(the processing time of the firmware to
control the flash memory is not included)
<1> <2>
<3>
<4>
RESET
TOOL0
723 µs + tHD processing
time
1-byte data for setting mode
. . .
tSU
tSUINIT
<1> The low level is input to the TOOL0 pin. <2> The external reset is released. Note that the POR and LVD reset must be released before the external reset is released. <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting.
Remark
tSUINIT: The time during which the communications for the initial setting must be completed within 100 ms after the external reset is released.
tSU: Time to release the external reset after the TOOL0 pin is set to the low level tHD: Time to hold the TOOL0 pin at the low level after the external reset is released. It does not include the processing time
of the firmware to control the flash memory.
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 1445 of 1478
RL78/G23
CHAPTER 38 PACKAGE DRAWINGS
CHAPTER 38 PACKAGE DRAWINGS
38.1
30-Pin Products
R7F100GAF3CSP, R7F100GAG3CSP, R7F100GAH3CSP, R7F100GAJ3CSP R7F100GAF2DSP, R7F100GAG2DSP, R7F100GAH2DSP, R7F100GAJ2DSP
JEITA Package Code P-LSSOP30-0300-0.65
RENESAS Code PLSP0030JB-B
Previous Code S30MC-65-5A4-3
MASS (TYP.) [g] 0.18
30
16
detail of lead end F
G
T
1
15
A
P L
E
U
S
C
NS
B
D
MM
K
NOTE
Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition.
H
I
J
ITEM A B C
D
E F G H I J K L M N
P
T U
MILLIMETERS
9.85p0.15
0.45 MAX.
0.65 (T.P.)
0.24
00..0087
0.1p0.05
1.3p0.1
1.2
8.1p0.2
6.1p0.2
1.0p0.2
0.17p0.03
0.5
0.13
0.10
3o
5o
3o
0.25
0.6p0.15
2012 Renesas Electronics Corporation. All rights reserved.
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 1446 of 1478
RL78/G23
CHAPTER 38 PACKAGE DRAWINGS
38.2
32-Pin Products
R7F100GBF3CNP, R7F100GBG3CNP, R7F100GBH3CNP, R7F100GBJ3CNP R7F100GBF2DNP, R7F100GBG2DNP, R7F100GBH2DNP, R7F100GBJ2DNP
JEITA Package code P-HWQFN032-5x5-0.50
RENESAS code PWQN0032KE-A
MASS(TYP.)[g] 0.06
2X aaa C
24
25
17 16
D
INDEX AREA (D/2 X E/2)
2X
32
9
aaa C
1
8
B
E
A
ccc C
A (A3) A1
32X
e
eee C
E2
1
fff C A B
32
D2
25
24
L(32X)
C
SEATING PLANE
b(32X)
bbb C A B
ddd C
Reference Symbol
fff C A B A
8
A1
A3 9
b
D
E
e
L
K
16
D2
E2 17
aaa
K(32X)
bbb
ccc
ddd
eee
fff
Dimension in Millimeters
Min. Nom. Max.
0.80
0.00
0.02
0.05
0.203 REF.
0.18
0.25
0.30
5.00 BSC
5.00 BSC
0.50 BSC
0.35
0.40
0.45
0.20
3.15
3.20
3.25
3.15
3.20
3.25
0.15
0.10
0.10
0.05
0.08
0.10
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 1447 of 1478
RL78/G23
CHAPTER 38 PACKAGE DRAWINGS
R7F100GBF3CFP, R7F100GBG3CFP, R7F100GBH3CFP, R7F100GBJ3CFP R7F100GBF2DFP, R7F100GBG2DFP, R7F100GBH2DFP, R7F100GBJ2DFP
JEITA Package Code P-LQFP32-7x7-0.80
HD 2D
RENESAS Code PLQP0032GB-A
Previous Code P32GA-80-GBT-1
MASS (TYP.) [g] 0.2
24
17
25
16
detail of lead end
32 1
1
E HE
9 8
c
L
e
3
b
xM
A A2
y
A1
NOTE 1.Dimensions " 1" and " 2" do not include mold flash. 2.Dimension " 3" does not include trim offset.
ITEM D E HD HE A A1 A2 b c
L e x y
(UNIT:mm) DIMENSIONS
7.00±0.10 7.00±0.10 9.00±0.20 9.00±0.20 1.70 MAX. 0.10±0.10 1.40 0.37±0.05 0.145 ±0.055 0.50±0.20 0° to 8° 0.80 0.20 0.10
2012 Renesas Electronics Corporation. All rights reserved.
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 1448 of 1478
RL78/G23
CHAPTER 38 PACKAGE DRAWINGS
38.3
36-Pin Products
R7F100GCF3CLA, R7F100GCG3CLA, R7F100GCH3CLA, R7F100GCJ3CLA R7F100GCF2DLA, R7F100GCG2DLA, R7F100GCH2DLA, R7F100GCJ2DLA
Contact a Renesas Electronics sales office for details.
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 1449 of 1478
RL78/G23
CHAPTER 38 PACKAGE DRAWINGS
38.4
40-Pin Products
R7F100GEF3CNP, R7F100GEG3CNP, R7F100GEH3CNP, R7F100GEJ3CNP R7F100GEF2DNP, R7F100GEG2DNP, R7F100GEH2DNP, R7F100GEJ2DNP
Contact a Renesas Electronics sales office for details.
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 1450 of 1478
RL78/G23
CHAPTER 38 PACKAGE DRAWINGS
38.5
44-Pin Products
R7F100GFF3CFP, R7F100GFG3CFP, R7F100GFH3CFP, R7F100GFJ3CFP R7F100GFK3CFP, R7F100GFL3CFP R7F100GFN3CFP R7F100GFF2DFP, R7F100GFG2DFP, R7F100GFH2DFP, R7F100GFJ2DFP R7F100GFK2DFP, R7F100GFL2DFP R7F100GFN2DFP
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 1451 of 1478
RL78/G23
CHAPTER 38 PACKAGE DRAWINGS
38.6
48-Pin Products
R7F100GGF3CFB, R7F100GGG3CFB, R7F100GGH3CFB, R7F100GGJ3CFB R7F100GGK3CFB, R7F100GGL3CFB, R7F100GGN3CFB R7F100GGF2DFB, R7F100GGG2DFB, R7F100GGH2DFB, R7F100GGJ2DFB R7F100GGK2DFB, R7F100GGL2DFB, R7F100GGN2CFB
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 1452 of 1478
RL78/G23
CHAPTER 38 PACKAGE DRAWINGS
R7F100GGF3CNP, R7F100GGG3CNP, R7F100GGH3CNP, R7F100GGJ3CNP R7F100GGK3CNP, R7F100GGL3CNP, R7F100GGN3CNP R7F100GGF2DNP, R7F100GGG2DNP, R7F100GGH2DNP, R7F100GGJ2DNP R7F100GGK2DNP, R7F100GGL2DNP, R7F100GGN2CNP
Contact a Renesas Electronics sales office for details.
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 1453 of 1478
RL78/G23
CHAPTER 38 PACKAGE DRAWINGS
38.7
52-Pin Products
R7F100GJF3CFA, R7F100GJG3CFA, R7F100GJH3CFA, R7F100GJJ3CFA R7F100GJK3CFA, R7F100GJL3CFA, R7F100GJN3CFA R7F100GJF2DFA, R7F100GJG2DFA, R7F100GJH2DFA, R7F100GJJ2DFA R7F100GJK2DFA, R7F100GJL2DFA, R7F100GJN2DFA
JEITA Package Code P-LQFP52-10x10-0.65
RENESAS Code PLQP0052JA-A
Previous Code P52GB-65-GBS-1
MASS (TYP.) [g] 0.3
HD
2
D
39 40
27 26
detail of lead end
1
E HE
c
L
52 1
14 13
e
3
b
xM
A A2
y
A1
NOTE 1.Dimensions " 1" and " 2" do not include mold flash. 2.Dimension " 3" does not include trim offset.
ITEM D E HD HE A A1 A2 b c
L e x y
(UNIT:mm) DIMENSIONS
10.00±0.10 10.00±0.10 12.00±0.20 12.00±0.20 1.70 MAX. 0.10±0.05 1.40 0.32±0.05
0.145 ±0.055
0.50±0.15 0° to 8° 0.65 0.13 0.10
2012 Renesas Electronics Corporation. All rights reserved.
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 1454 of 1478
RL78/G23
CHAPTER 38 PACKAGE DRAWINGS
38.8
64-Pin Products
R7F100GLF3CFA, R7F100GLG3CFA, R7F100GLH3CFA, R7F100GLJ3CFA R7F100GLK3CFA, R7F100GLL3CFA, R7F100GLN3CFA R7F100GLF2DFA, R7F100GLG2DFA, R7F100GLH2DFA, R7F100GLJ2DFA R7F100GLK2DFA, R7F100GLL2DFA, R7F100GLN2DFA
JEITA Package Code P-LQFP64-12x12-0.65
RENESAS Code PLQP0064JA-A
Previous Code P64GK-65-UET-2
MASS (TYP.) [g] 0.51
HD D
48 49
33 32
detail of lead end
A3 c
E HE
Q
L
Lp
L1
64 1
ZE ZD
17 16
e
b
xM S
yS
NOTE Each lead centerline is located within 0.13 mm of its true position at maximum material condition.
A A2
A1
(UNIT:mm)
ITEM DIMENSIONS
D
12.00p0.20
E
12.00p0.20
HD
14.00p0.20
HE
14.00p0.20
A
1.60 MAX.
A1
0.10p0.05
A2
1.40p0.05
A3
0.25
b
0.32
0.08
0.07
c
0.145
0.055
0.045
L
0.50
S
Lp
0.60p0.15
L1
1.00p0.20
Q
3o
5o
3o
e
0.65
x
0.13
y
0.10
ZD
1.125
ZE
1.125
2012 Renesas Electronics Corporation. All rights reserved.
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 1455 of 1478
RL78/G23
CHAPTER 38 PACKAGE DRAWINGS
R7F100GLF3CFB, R7F100GLG3CFB, R7F100GLH3CFB, R7F100GLJ3CFB, R7F100GLK3CFB, R7F100GLL3CFB, R7F100GLN3CFB R7F100GLF2DFB, R7F100GLG2DFB, R7F100GLH2DFB, R7F100GLJ2DFB, R7F100GLK2DFB, R7F100GLL2DFB, R7F100GLN2DFB
JEITA Package Code P-LFQFP64-10x10-0.50
48 49
HD *1 D
RENESAS Code PLQP0064KB-C
33 32
Previous Code --
MASS (Typ) [g] 0.3
Unit: mm
*2 E HE
64 S
1 Index area
NOTE 3
17
16
NOTE 4
F
yS e
*3 bp
M
0.25 c T
A2
A
A1
Lp L1 Detail F
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
Reference Dimensions in millimeters
Symbol Min Nom Max
D
9.9 10.0 10.1
E
9.9 10.0 10.1
A2
1.4
HD 11.8 12.0 12.2
HE 11.8 12.0 12.2
A
1.7
A1 0.05 0.15
bp 0.15 0.20 0.27
c 0.09 0.20
T
0q 3.5q 8q
e
0.5
x
0.08
y
0.08
Lp 0.45 0.6 0.75
L1
1.0
© 2015 Renesas Electronics Corporation. All rights reserved.
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 1456 of 1478
RL78/G23
CHAPTER 38 PACKAGE DRAWINGS
R7F100GLF3CLA, R7F100GLG3CLA, R7F100GLH3CLA, R7F100GLJ3CLA, R7F100GLK3CLA, R7F100GLL3CLA, R7F100GLN3CLA R7F100GLF2DLA, R7F100GLG2DLA, R7F100GLH2DLA, R7F100GLJ2DLA, R7F100GLK2DLA, R7F100GLL2DLA, R7F100GLN2DLA
Contact a Renesas Electronics sales office for details.
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 1457 of 1478
RL78/G23
CHAPTER 38 PACKAGE DRAWINGS
38.9
80-Pin Products
R7F100GMG3CFA, R7F100GMH3CFA, R7F100GMJ3CFA, R7F100GMK3CFA, R7F100GML3CFA, R7F100GMN3CFA R7F100GMG2DFA, R7F100GMH2DFA, R7F100GM2DFA, R7F100GMK2DFA, R7F100GML2DFA, R7F100GMN2DFA
JEITA Package Code P-LQFP80-14x14-0.65
HD *1 D 60
61
RENESAS Code PLQP0080JA-B
41 40
Previous Code --
MASS (Typ) [g] 0.6
Unit: mm
*2 E
HE
80 1
Index area NOTE 3
S
yS e
A2
A
A1
Lp L1 Detail F
0.25 c T
21
20 *3 bp
NOTE 4
F
M
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
Reference Dimensions in millimeters
Symbol Min Nom Max
D 13.9 14.0 14.1
E 13.9 14.0 14.1
A2
1.4
HD 15.8 16.0 16.2
HE 15.8 16.0 16.2
A
1.7
A1 0.05 0.15
bp 0.22 0.30 0.38
c 0.09 0.20
T
0q 3.5q 8q
e
0.65
x
0.13
y
0.10
Lp 0.45 0.6 0.75
L1
1.0
© 2016 Renesas Electronics Corporation. All rights reserved.
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 1458 of 1478
RL78/G23
CHAPTER 38 PACKAGE DRAWINGS
R7F100GMG3CFB, R7F100GMH3CFB, R7F100GMJ3CFB, R7F100GMK3CFB, R7F100GML3CFB, R7F100GMN3CFB R7F100GMG2DFB, R7F100GMH2DFB, R7F100GM2DFB, R7F100GMK2DFB, R7F100GML2DFB, R7F100GMN2DFB
JEITA Package Code P-LFQFP80-12x12-0.50
HD *1 D 60
61
RENESAS Code PLQP0080KB-B
41
40
Previous Code --
MASS (Typ) [g] 0.5
Unit: mm
*2 E
HE
A
A1
A2
80 1 Index area
NOTE 3
S
yS e
Lp L1 Detail F
0.25 c T
21
20 *3
bp
NOTE 4
F
M
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
Reference Dimensions in millimeters
Symbol Min Nom Max
D 11.9 12.0 12.1
E 11.9 12.0 12.1
A2
1.4
HD 13.8 14.0 14.2
HE 13.8 14.0 14.2
A
1.7
A1 0.05 0.15
bp 0.15 0.20 0.27
c 0.09 0.20
T
0q 3.5q 8q
e
0.5
x
0.08
y
0.08
Lp 0.45 0.6 0.75
L1
1.0
© 2017 Renesas Electronics Corporation. All rights reserved.
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 1459 of 1478
RL78/G23
CHAPTER 38 PACKAGE DRAWINGS
38.10 100-Pin Products
R7F100GPG3CFB, R7F100GPH3CFB, R7F100GPJ3CFB, R7F100GPK3CFB, R7F100GPL3CFB, R7F100GPN3CFB R7F100GPG2DFB, R7F100GPH2DFB, R7F100GPJ2DFB, R7F100GPK2DFB, R7F100GPL2DFB, R7F100GPN2DFB
JEITA Package Code P-LFQFP100-14x14-0.50
HD *1 D 75
76
RENESAS Code PLQP0100KB-B
51 50
Previous Code --
MASS (Typ) [g] 0.6
Unit: mm
*2 E HE
100 1
S
Index area NOTE 3
yS e
A2
A
A1
Lp L1 Detail F
0.25 c T
26
25
NOTE 4
F
*3 bp
M
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
Reference Dimensions in millimeters
Symbol Min Nom Max
D 13.9 14.0 14.1
E 13.9 14.0 14.1
A2
1.4
HD 15.8 16.0 16.2
HE 15.8 16.0 16.2
A
1.7
A1 0.05 0.15
bp 0.15 0.20 0.27
c 0.09 0.20
T
0q 3.5q 8q
e
0.5
x
0.08
y
0.08
Lp 0.45 0.6 0.75
L1
1.0
© 2015 Renesas Electronics Corporation. All rights reserved.
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 1460 of 1478
RL78/G23
CHAPTER 38 PACKAGE DRAWINGS
R7F100GPG3CFA, R7F100GPH3CFA, R7F100GPJ3CFA, R7F100GPK3CFA, R7F100GPL3CFA, R7F100GPN3CFA R7F100GPG2DFA, R7F100GPH2DFA, R7F100GPJ2DFA, R7F100GPK2DFA, R7F100GPL2DFA, R7F100GPN2DFA
JEITA Package Code P-LQFP100-14x20-0.65
RENESAS Code PLQP0100JC-A
Previous Code P100GF-65-GBN-1
MASS (TYP.) [g] 0.92
80 81
B
HD D
A
51 50
E HE
100 1
ZE ZD
S
b x M S AB
31 30
e
A A2
yS
A1
detail of lead end A3
c
L Lp L1
ITEM D E HD HE A A1 A2 A3 b
c L Lp L1
e x y ZD ZE
(UNIT:mm)
DIMENSIONS 20.00 0.20
14.00 0.20
22.00 0.20
16.00 0.20
1.60 MAX.
0.10 0.05
1.40 0.05
0.25
0.32
0.08 0.07
0.145
0.055 0.045
0.50
0.60 0.15
1.00 0.20
3
5 3
0.65
0.13
0.10
0.575
0.825
2012 Renesas Electronics Corporation. All rights reserved.
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 1461 of 1478
RL78/G23
CHAPTER 38 PACKAGE DRAWINGS
38.11 128-Pin Products
R7F100GSJ3CFB, R7F100GSK3CFB, R7F100GSL3CFB, R7F100GSN3CFB R7F100GSJ2DFB, R7F100GSK2DFB, R7F100GSL2DFB, R7F100GSN2DFB
JEITA Package Code P-LFQFP128-14x20-0.50
RENESAS Code PLQP0128KD-A
Previous Code P128GF-50-GBP-1
MASS (TYP.) [g] 0.92
102 103
HD D
A
65 64
detail of lead end A3
c
B E HE
128 1
ZE ZD
S
b x M S AB yS
39 38
e
A A2
A1
Q L
Lp
L1
ITEM D E HD HE A A1 A2 A3 b
c
L Lp L1
Q e x y ZD ZE
(UNIT:mm)
DIMENSIONS 20.00p0.20
14.00p0.20
22.00p0.20
16.00p0.20
1.60 MAX.
0.10p0.05
1.40p0.05
0.25
0.22 p0.05
0.145
0.055
0.045
0.50
0.60p0.15
1.00p0.20
3o
5o
3o
0.50
0.08
0.08
0.75
0.75
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
2012 Renesas Electronics Corporation. All rights reserved.
Page 1462 of 1478
RL78/G23
APPENDIX A REVISION HISTORY
APPENDIX A REVISION HISTORY
A.1
Major Revisions in This Edition
(1/4)
Page
Description
Classification
Overall
--
"CSI" was modified to "SPI (CSI)".
(c)
--
"Wait" was modified to "clock stretch".
(c)
CHAPTER 1 OUTLINE
p.2
1.1 Features: Note was added.
(c)
p.3
1.1 Features: The description was added.
(c)
p.5
Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G23 was modified.
(d)
p.6 to p.8
Table 1 - 1 List of Ordering Part Numbers: Tables were modified and notes 2 and 3 were added.
(d), (c)
CHAPTER 4 PORT FUNCTIONS
p.198
Figure 4 - 12 Format of Output Current Control Enable Register (CCDE): Caution 2 was modified.
(b)
p.205
4.4.5 Handling different potential (1.8 V, 2.5 V, or 3 V) by using I/O buffers, (1) Setting procedure
(c)
when using input pins of UART0 to UART3, UARTA0, UARTA1, CSI00, CSI01, CSI10, CSI20,
CSI30, and CSI31 functions in the TTL input buffer mode: Note was added.
p.216, p.220
Table 4 - 7 Examples of Register and Output Latch Settings for Alternate Functions (30-Pin to 64-
(a)
Pin Products with 96-Kbyte or 128-Kbyte Flash Memory) was modified.
p.232, p.236
Table 4 - 8 Examples of Register and Output Latch Settings for Alternate Functions (Products with
(a)
192-Kbyte to 768-Kbyte Flash Memory and 80-Pin and 100-Pin Products with 128-Kbyte Flash
Memory) was modified.
CHAPTER 6 CLOCK GENERATOR
p.264
Figure 6 - 1 Block Diagram of Clock Generator: Figure and remark were modified.
(a)
CHAPTER 8 REALTIME CLOCK (RTC)
p.456
Figure 8 - 19 Procedure for Starting the Realtime Clock Operation was modified.
(a)
CHAPTER 12 A/D CONVERTER (ADC)
p.591
Table 12 - 4 Resistance and Capacitance Values of Equivalent Circuit (Reference Values) was
(b)
modified.
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
p.617
CHAPTER 15 SERIAL ARRAY UNIT (SAU): Note was added.
(c)
p.623
Figure 15 - 1 Block Diagram of Serial Array Unit 0 was modified.
(a)
p.653
15.3.15 Serial standby control register m (SSCm): Caution was modified.
(b)
p.751
15.6.3 SNOOZE Mode Function: Caution 2 was modified.
(b)
CHAPTER 17 SERIAL INTERFACE UARTA (UARTA)
p.889
Figure 17 - 1 Block Diagram of UARTAn was modified.
(a)
p.895 Remark
Figure 17 - 5 Format of Operation Mode Setting Register 0 (ASIMAn0): Caution 4 was modified.
(c)
"Classification" in the above table classifies revisions as follows.
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note, (d): Addition/change of package, part number, or management division, (e): Addition/change of related documents
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RL78/G23
APPENDIX A REVISION HISTORY
(2/4)
Page
Description
Classification
CHAPTER 25 POWER-ON-RESET CIRCUIT (POR)
p.1140, p.1141 Figure 25 - 2 Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage
(b)
Detector: Note 3 was modified.
CHAPTER 26 VOLTAGE DETECTOR (LVD)
p.1142
26.1 Functions of Voltage Detector: The description was modified.
(c)
p.1143
Figure 26 - 1 Block Diagram of LVD0 was modified.
(c)
p.1143
Figure 26 - 2 Block Diagram of LVD1 was modified.
(c)
p.1144
26.3.1 Voltage detection register (LVIM): The description was modified.
(c)
p.1144
Figure 26 - 3 Format of Voltage Detection Register (LVIM): Note 1 was modified.
(c)
p.1146, p.1147 Figure 26 - 5 Format of Voltage Detection Level Register (LVIS): Figure and note 2 were modified
(c)
and notes 3 and 4 were added.
p.1148
26.4.1 When used as reset mode: The descriptions were modified.
(c)
p.1149
Figure 26 - 6 Timing of LVD0 Internal Reset Signal Generation was modified.
(c)
p.1150
Figure 26 - 7 Timing of LVD1 Internal Reset Signal Generation: Figure and remark were modified.
(c)
p.1152
Figure 26 - 8 Timing of LVD0 Interrupt Signal Generation was modified.
(c)
p.1153
Figure 26 - 9 Timing of LVD1 Interrupt Signal Generation: Figure and remark were modified.
(c)
p.1156
26.5 Points for Caution when the Voltage Detector is to be Used: (5) was added.
(c)
CHAPTER 27 SAFETY FUNCTIONS
p.1171
Figure 27 - 13 Format of Invalid Memory Access Detection Control Register (IAWCTL) was
(b)
modified.
CHAPTER 30 CAPACITIVE SENSING UNIT (CTSU2L)
p.1238
Table 30 - 1 CTSU Functions was modified.
(c)
p.1245, p.1246 Figure 30 - 7 Format of CTSU Control Register AL/AH (CTSUCRAL/CTSUCRAH) was modified.
(c)
p.1250
Figure 30 - 8 Format of CTSU Control Register BL/BH (CTSUCRBL/CTSUCRBH) was modified.
(c)
p.1253
Figure 30 - 9 Format of CTSU Measurement Channel Register L/H (CTSUMCHL/CTSUMCHH) was
(c)
modified.
p.1257
Figure 30 - 11 Format of CTSU Channel Transmit/Receive Control Register AL/AH/BL/BH
(c)
(CTSUCHTRCAL/CTSUCHTRCAH/CTSUCHTRCBL/CTSUCHTRCBH): Caution 4 was modified.
p.1258, p.1259 Figure 30 - 12 Format of CTSU Status Register L (CTSUSRL) was modified.
(c)
p.1261
Figure 30 - 13 Format of CTSU Sensor Offset Register 0/1 (CTSUSO0/CTSUSO1) was modified.
(c)
p.1265, p.1266 Figure 30 - 15 Format of CTSU Calibration Register L/H (CTSUDBGR0/CTSUDBGR1) was
(b)
modified.
CHAPTER 33 FLASH MEMORY
p.1283
CHAPTER 33 FLASH MEMORY: The descriptions were modified.
(c)
p.1286
33.2 Serial Programming Using External Device (that Incorporates UART): The descriptions were
(c)
modified.
p.1291
33.4.2 Flash memory programming mode: The descriptions were modified.
(c)
p.1293
33.4.4 Communication commands: The descriptions were modified.
(c)
p.1296
33.6 Self-Programming: Remark was deleted.
(c)
p.1297 Remark
33.6.1 Self-programming procedure: The descriptions were modified.
(c)
"Classification" in the above table classifies revisions as follows.
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note, (d): Addition/change of package, part number, or management division, (e): Addition/change of related documents
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APPENDIX A REVISION HISTORY
(3/4)
Page
Description
Classification
p.1298
33.6.2 Registers to control the flash memory was added.
(c)
p.1322
33.6.3 Setting the flash memory control mode was added.
(c)
p.1324
33.6.4 Clearing the registers for use with the flash memory sequencer was added.
(c)
p.1324
33.6.5 Setting the operating frequency of the flash memory sequencer was added.
(c)
p.1325
33.6.6 Commands for use with the flash memory sequencer in the respective areas was added.
(c)
p.1335
33.6.8 Flash shield window function was modified.
(c)
p.1335
Figure 33 - 29 Flash Shield Window Setting Example (Target Devices: R7F100GLG, Start Block
(c)
Number in the Window Range: 04H, End Block Number in the Window Range: 06H, FSWC: 1) was
modified.
p.1335
Table 33 - 13 Relationship between Flash Shield Window Function Setting/Change Methods and
(c)
Commands was modified.
p.1336
33.6.9 Interrupts in code flash programming mode was added.
(c)
p.1338
33.6.10 Example of executing the commands to rewrite the flash memory areas was added.
(c)
p.1341
33.6.11 Notes on self-programming was added.
(c)
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C
p.1376
37.2.1 Characteristics of the X1 and XT1 oscillators: Note 1 was modified.
(c)
p.1377
37.2.2 Characteristics of the On-chip Oscillators and Note 1 were modified.
(b), (c)
p.1387,
37.3.2 Supply current characteristics (1) 30- to 64-pin package products with 96- to 128-Kbyte flash
(b)
p.1389 to p.1392 ROM was modified.
p.1387
37.3.2 Supply current characteristics (2) Peripheral Functions (Common to all products) was
(b)
modified.
p.1394
37.3.2 Supply current characteristics (2) Peripheral Functions (Common to all products): Notes 15,
(b)
16, 17, and 18 were added.
p.1395
37.4 AC Characteristics was modified.
(b)
p.1401
37.5.1 Serial array unit (1) In UART communications with devices operating at same voltage levels:
(b)
Note 1 was modified.
p.1403
37.5.1 Serial array unit (2) In SPI (CSI) communications in the master mode with devices operating
(b)
at same voltage levels with the internal SCKp clock (the ratings below are only applicable to CSI00)
was modified.
p.1404
37.5.1 Serial array unit (3) In SPI (CSI) communications in the master mode with devices operating
(b)
at same voltage levels with the internal SCKp clock was modified.
p.1409, p.1410 37.5.1 Serial array unit (5) In simplified I2C communications with devices operating at same voltage
(b)
levels was modified.
p.1412
37.5.1 Serial array unit (6) In UART communications with devices operating at different voltage
(b)
levels (1.8 V, 2.5 V, 3 V): Note 1 was modified.
p.1416, p.1417 37.5.1 Serial array unit (7) In SPI (CSI) communications in the master mode with devices operating
(b)
at different voltage levels (2.5 V or 3 V) with the internal SCKp clock (the ratings below are only
applicable to CSI00) was modified.
p.1418 to p.1420 37.5.1 Serial array unit (8) In SPI (CSI) communications in the master mode with devices operating
(b)
at different voltage levels (2.5 V or 3 V) with the internal SCKp clock (the ratings below are only
applicable to CSI00) was modified.
p.1423, p.1424 37.5.1 Serial array unit (9) In SPI (CSI) communications in the slave mode with devices operating at
(b)
different voltage levels (1.8 V, 2.5 V, or 3 V) with the external SCKp clock was modified.
p.1427, p.1428 37.5.1 Serial array unit (10) Simplified I2C communications with devices operating at different
(b)
voltage levels (1.8 V, 2.5 V, or 3 V) was modified.
Remark
"Classification" in the above table classifies revisions as follows.
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note, (d): Addition/change of package, part number, or management division, (e): Addition/change of related documents
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APPENDIX A REVISION HISTORY
(4/4)
Page
Description
Classification
p.1461
37.6.1 A/D converter characteristics (1) Normal modes 1 and 2 were modified.
(b)
p.1463
37.6.1 A/D converter characteristics (2) Low-voltage modes 1 and 2 were modified.
(b)
p.1465
37.6.1 A/D converter characteristics (3) When the internal reference voltage is selected as
(b)
reference voltage (+) was modified.
p.1434
37.6.1 A/D converter characteristics (4) When reference voltage (+) = Internal reference voltage
(b)
(ADREFP1 = 1, ADREFP0 = 0), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pin:
ANI0, ANI2 to ANI14, ANI16 to ANI26 was deleted.
p.1468
37.6.6 LVD circuit characteristics (1) LVD0 Detection Voltage in the Reset Mode and Interrupt Mode
(c)
was modified.
p.1435, p.1436 37.6.6 LVD circuit characteristics (2) LVD1 Detection Voltage of Reset Mode and Interrupt Mode and
(c)
Note were modified.
p.1444
37.8 Flash Memory Programming Characteristics (1) Code flash memory was added.
(b)
p.1444 Remark
37.8 Flash Memory Programming Characteristics (2) Data flash memory was added.
(b)
"Classification" in the above table classifies revisions as follows.
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note, (d): Addition/change of package, part number, or management division, (e): Addition/change of related documents
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RL78/G23
APPENDIX A REVISION HISTORY
A.2
Revision History of Preceding Editions
Here is the revision history of the preceding editions. Chapter indicates the chapter of each edition.
(1/12)
Edition
Description
Chapter
Rev.0.50 First Edition issued.
Throughout
Rev.0.80 The name of a connection pin to a capacitor TCAP was modified to TSCAP.
Overall
"E20 emulator" was deleted.
1.1 Features: The descriptions were modified.
CHAPTER 1 OUTLINE
Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G23 was modified.
Table 1 - 1 List of Ordering Part Numbers was modified.
1.3.3 36-pin products: The figure was modified.
1.3.6 48-pin products: The figure was modified.
1.3.9 80-pin products: Cautions 1 to 3 were modified and Remark 3 was added.
1.3.10 100-pin products: Cautions 1 to 3 were modified and Remarks 1 to 3 were added.
1.3.11 128-pin products: Cautions 1 to 3 were modified and Remarks 1 to 3 were added.
1.6 Outline of Functions: The descriptions were modified and Notes 6 and 7 were added.
Figure 2 - 5 Pin Block Diagram for Pin Type 4-3-5 was modified. Figure 2 - 6 Pin Block Diagram for Pin Type 4-33-1 was modified.
CHAPTER 2 PIN FUNCTIONS
Figure 2 - 7 Pin Block Diagram for Pin Type 4-35-1 was modified.
Figure 2 - 8 Pin Block Diagram for Pin Type 4-37-1 was modified.
Figure 3 - 1 Memory Map (R7F100GxF (x = A, B, C, E, F, G, J, L)): Note 2 was modified.
Figure 3 - 2 Memory Map (R7F100GxG (x = A, B, C, E, F, G, J, L, M, P)): Note 2 was modified.
CHAPTER 3 CPU ARCHITECTURE
Figure 3 - 3 Memory Map (R7F100GxH (x = A, B, C, E, F, G, J, L, M, P)): Note 2 was modified.
Figure 3 - 4 Memory Map (R7F100GxJ (x = A, B, C, E, F, G, J, L, M, P, S)): Note 2 was modified.
Figure 3 - 5 Memory Map (R7F100GxK (x = F, G, J, L, M, P, S)): Note 2 was modified.
Figure 3 - 6 Memory Map (R7F100GxL (x = F, G, J, L, M, P, S)): Note 2 was modified.
Figure 3 - 7 Memory Map (R7F100GxN (x = F, G, J, L, M, P, S)): Note 2 was modified.
Table 3 - 5 Vector Table was modified.
3.1.1 Internal program memory space: (2), (3), and (4) were modified.
Figure 3 - 8 Format of Configuration of Processor Mode Control Register (PMC) was modified.
Figure 3 - 9 Correspondence Between Data Memory and Addressing was modified.
Table 3 - 7 List of Special Function Registers (SFRs): Note 2 was added.
Table 3 - 8 List of Extended Special Function Registers (2nd SFRs): The register name was modified.
Table 4 - 1 Port Configuration was modified. 4.3 Registers Controlling Port Function: The description was modified.
CHAPTER 4 PORT FUNCTIONS
4.3.12 Output current control enable register (CCDE): The descriptions were modified.
4.3.13 Output current select registers (CCSx): The descriptions were modified.
4.3.14 40-mA port output control register (PTDC): The title and descriptions were modified.
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APPENDIX A REVISION HISTORY
(2/12)
Edition
Description
Chapter
Rev.0.80 Figure 4 - 14 Format of 40-mA Port Output Control Register (PTDC): The title was modified.
CHAPTER 4 PORT FUNCTIONS
4.3.15 Port function output enable registers (PFOEx): The descriptions were modified.
4.4.5 Handling different potential (1.8 V, 2.5 V, or 3 V) by using I/O buffers: The descriptions in (1) were modified.
4.4.5 Handling different potential (1.8 V, 2.5 V, or 3 V) by using I/O buffers: The descriptions in (2) were modified.
4.5.4 Examples of register settings for port and alternate functions was added.
5.4 Transition between Flash Operation Modes: The descriptions were modified. Figure 5 - 4 State Transitions between Flash Operation Modes was modified.
CHAPTER 5 OPERATION STATE CONTROL
5.5.2 Details of LS (low-speed main) mode: The descriptions and Note were modified.
Figure 5 - 6 Operating Range in LS Mode is modified.
5.5.3 Details of LP (low-power main) mode: The descriptions were modified.
The description in (1) Main system clock in 6.1 Functions of Clock Generator was modified. CHAPTER 6 CLOCK
Figure 6 - 1 Block Diagram of Clock Generator was modified.
GENERATOR
The description, note 3, caution 6, and caution 7 in Figure 6 - 2 Format of Clock Operation Mode Control Register (CMC) were modified.
Caution 5 in Figure 6 - 4 Format of Clock Operation Status Control Register (CSC) was modified.
The description and note in Figure 6 - 7 Format of Peripheral Enable Register 0 (PER0) were modified.
The description and note in Figure 6 - 8 Format of Peripheral Enable Register 1 (PER1) were modified.
The description and note 7 in Figure 6 - 9 Format of Subsystem Clock Supply Mode Control Register (OSMC) were modified.
The description in 6.3.12 High-speed on-chip oscillator trimming register (HIOTRM) was modified.
The description in 6.3.13 Middle-speed on-chip oscillator trimming register (MIOTRM) was modified.
The description in 6.3.14 Low-speed on-chip oscillator trimming register (LIOTRM) was modified.
The description in 6.4.1 X1 oscillator was modified.
The caution in Figure 6 - 19 Examples of External Circuits for the XT1 Oscillator was modified.
Table 6 - 2 Examples of Transitions of the CPU Clock and SFR Settings was modified.
A note was added to Figure 7 - 11 Format of Peripheral Enable Register 0 (PER0).
CHAPTER 7 TIMER ARRAY UNIT (TAU)
Figure 8 - 1 Block Diagram of the Realtime Clock was modified.
Figure 8 - 3 Format of Subsystem Clock Supply Mode Control Register (OSMC) was modified and Notes 1 and 2 were added.
CHAPTER 8 REALTIME CLOCK (RTC)
Figure 8 - 4 Format of Realtime Clock Control Register 0 (RTCC0): Note was modified, and Caution 3 was added.
Figure 9 - 2 Format of Peripheral Enable Register 1 (PER1) was modified. The description in 9.2.6 Interval timer capture register 000 (ITLCAP000) was modified.
CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
The description in 9.2.7 Interval timer capture register 00 (ITLCAP00) was modified.
R01UH0896EJ0100 Rev.1.00 Apr 13, 2021
Page 1468 of 1478
RL78/G23
APPENDIX A REVISION HISTORY
Edition
Description
Rev.0.80 The description in 9.2.10 Interval timer frequency division register 0 (ITLFDIV00) was modified.
A caution and remark were added to 9.2.13 Interval timer status register (ITLS0).
The description in 9.3.2 Capture mode settings was modified.
The description in 9.3.3 Timer operation was modified.
Figure 10 - 2 Format of Clock Output Select Register n (CKSn) was modified.
Figure 12 - 2 Format of Peripheral Enable Register 0 (PER0): Note 3 was added. Figure 12 - 5 Timing Chart When A/D Voltage Comparator Is Used: Note 1 was modified. Figure 12 - 7 Format of A/D Converter Mode Register 1 (ADM1) was modified. Figure 12 - 37 Setting up Software Trigger Wait Mode was modified. Figure 12 - 41 Flowchart for Setting up SNOOZE Mode (Software Trigger) was modified. Figure 13 - 2 Format of Peripheral Enable Register 1 (PER1): Note was added.
Figure 14 - 2 Format of Peripheral Enable Register 1 (PER1): Note was added.
Figure 15 - 5 Format of Peripheral Enable Register 0 (PER0): Note 2 was added.
16.1 Functions of Serial Interface IICA (3): The descriptions were modified. Figure 16 - 5 Format of Peripheral Enable Register 0 (PER0) was modified. Figure 17 - 1 Block Diagram of UARTAn was modified. 17.2 Register Descriptions: Remark was modified. Figure 17 - 2 Format of Peripheral Enable Register 1 (PER1): The descriptions and Note were modified. 17.2.8 Status clear trigger register (ASCTAn) (n = 0, 1): The descriptions were modified. Figure 17 - 13 Flowchart of Communication Procedure: Caution was modified. Figure 18 - 2 Format of Peripheral Enable Register 1 (PER1): Note was added. Figure 18 - 5 Format of Function Select Register 1 (REMCON1) was modified. Figure 18 - 7 Format of Interrupt Control Register (REMINT) was modified. Figure 18 - 8 Format of Compare Control Register (REMCPC) was modified. Figure 18 - 20 Format of Receive Bit Count Register (REMRBIT) was modified. Figure 18 - 25 Example of Flowchart for Initial Settings of REMC was modified. 18.3.4.1 When using fSXL as the REMC operating clock: The descriptions were modified. 18.3.5 RIN0 Input: The descriptions were modified. 18.3.9 Compare Function: The descriptions were modified. Table 18 - 6 Interrupt Modes and Transition from SNOOZE Mode was modified. Figure 18 - 44 Example of Flowchart for Setting up SNOOZE Mode was modified. 18.4.5 Reading Registers: The descriptions were modified. Figure 19 - 5 Format of Peripheral Enable Register 1 (PER1): Note was added.
(3/12)
Chapter CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER (PCLBUZ) CHAPTER 12 A/D CONVERTER (ADC)
CHAPTER 13 D/A CONVERTER (DAC) CHAPTER 14 COMPARATOR (CMP) CHAPTER 15 SERIAL ARRAY UNIT (SAU) CHAPTER 16 SERIAL INTERFACE IICA (IICA) CHAPTER 17 SERIAL INTERFACE UARTA (UARTA)
CHAPTER 18 REMOTE CONTROL SIGNAL RECEIVER (REMC)
CHAPTER 19 DATA TRANSFER CONTROLLER (DTC)
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RL78/G23
APPENDIX A REVISION HISTORY
(4/12)
Edition
Description
Chapter
Rev.0.80 Figure 20 - 2 Block Diagram of Logic Cell Block L1 was modified. Figure 20 - 3 Block Diagram of Logic Cell Block L2 was modified. Figure 20 - 4 Block Diagram of Logic Cell Block L3 was modified.
CHAPTER 20 LOGIC AND EVENT LINK CONTROLLER (ELCL)
The description and caution 2 in Figure 20 - 5 Format of Input Signal Select Registers n (ELISELn) (n = 0 to 11) were modified.
Caution 2 in Figure 20 - 6 Format of Event Link L1 Signal Select Registers n (ELL1SELn) (n = 0 to 3) was modified.
Caution 2 in Figure 20 - 7 Format of Event Link L1 Signal Select Registers n (ELL1SELn) (n = 4, 5) was modified.
Caution 2 in Figure 20 - 8 Format of Event Link L1 Signal Select Register 6 (ELL1SEL6) was modified.
The description and caution 2 in Figure 20 - 9 Format of Logic Cell Block L1 Control Register (ELL1CTL) were modified.
Caution 3 in Figure 20 - 10 Format of Event Link L1 Output Select Registers n (ELL1LNKn) (n = 0 to 3) was modified.
Caution 3 in Figure 20 - 11 Format of Event Link L1 Output Select Registers n (ELL1LNKn) (n = 4, 5) was modified.
Caution 2 in Figure 20 - 12 Format of Event Link L1 Output Select Register 6 (ELL1LNK6) was modified.
Caution 2 in Figure 20 - 13 Format of Event Link L2 Signal Select Registers n (ELL2SELn) (n = 0 to 3) was modified.
Caution 2 in Figure 20 - 14 Format of Event Link L2 Signal Select Registers n (ELL2SELn) (n = 4, 5) was modified.
Caution 2 in Figure 20 - 15 Format of Event Link L2 Signal Select Register 6 (ELL2SEL6) was modified.
The description and caution 2 in Figure 20 - 16 Format of Logic Cell Block L2 Control Register (ELL2CTL) were modified.
Caution 3 in Figure 20 - 17 Format of Event Link L2 Output Select Registers n (ELL2LNKn) (n = 0 to 3) was modified.
Caution 3 in Figure 20 - 18 Format of Event Link L2 Output Select Registers n (ELL2LNKn) (n = 4, 5) was modified.
Caution 2 in Figure 20 - 19 Format of Event Link L2 Output Select Register 6 (ELL2LNK6) was modified.
Caution 2 in Figure 20 - 20 Format of Event Link L3 Signal Select Registers n (ELL3SELn) (n = 0 to 3) was modified.
Caution 2 in Figure 20 - 21 Format of Event Link L3 Signal Select Registers n (ELL3SELn) (n = 4, 5) was modified.
Caution 2 in Figure 20 - 22 Format of Event Link L3 Signal Select Register 6 (ELL3SEL6) was modified.
The description and caution 2 in Figure 20 - 23 Format of Logic Cell Block L3 Control Register (ELL3CTL) were modified.
Caution 3 in Figure 20 - 24 Format of Event Link L3 Output Select Registers n (ELL3LNKn) (n = 0 to 3) was modified.
Caution 3 in Figure 20 - 25 Format of Event Link L3 Output Select Registers n (ELL3LNKn) (n = 4, 5) was modified.
Caution 2 in Figure 20 - 26 Format of Event Link L3 Output Select Register 6 (ELL3LNK6) was modified.
The description in 20.4 ELCL Operation was modified.
Point to note (4) was added to 20.6 Usage Notes.
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Description
Chapter
Rev.0.80 Table 21 - 2 Flags Corresponding to Interrupt Request Sources (4/5): Notes 1 and 2 were CHAPTER 21 INTERRUPT
added.
FUNCTIONS
Table 23 - 1 Operating Statuses in HALT Mode (1) was modified. Table 23 - 2 Operating Statuses in HALT Mode (2) was modified.
CHAPTER 23 STANDBY FUNCTION
Table 23 - 3 Operating Statuses in STOP Mode was modified.
Table 23 - 4 Operating Statuses in SNOOZE Mode was modified.
Figure 27 - 16 Format of Guard Register of IAWCTL Register (GIAWCTL) was modified.
CHAPTER 27 SAFETY FUNCTIONS
Figure 29 - 8 Flow of Internal Operations of the SNOOZE Mode Sequencer was modified. CHAPTER 29 SNOOZE
The description in 29.5.13 Branch 2 (SCY = 0) was modified.
MODE SEQUENCER (SMS)
The description in 29.5.14 Branch 3 (SZ = 1) was modified.
The description in 29.5.15 Branch 4 (SZ = 0) was modified.
The description in 29.5.16 Wait was modified.
CHAPTER 30 CAPACITIVE SENSING UNIT (CTSU2L): The descriptions were modified. Table 30 - 1 CTSU Functions was modified.
CHAPTER 30 CAPACITIVE SENSING UNIT (CTSU2L)
Figure 30 - 3 CTSU Block Diagram was modified.
Table 30 - 2 External Pins Used in CTSU was modified.
30.3 Operation was deleted.
30.4 Usage Notes was deleted.
Figure 33 - 9 Boot Swap Function was modified.
CHAPTER 33 FLASH MEMORY
37.1 Absolute Maximum Ratings was modified. 37.2.1 X1, XT1 oscillator characteristics was modified. 37.3.1 Pin characteristics (2/7): Note 3 was modified.
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +85°C (TARGET)
37.3.2 Supply current characteristics (1) 30- to 64-pin package products with 96- to 128-KB ROM (2/4): Note 3 was modified.
37.3.2 Supply current characteristics (1) 30- to 64-pin package products with 96- to 128-KB ROM (4/4): Notes 4, 5, and 8 were modified.
37.3.2 Supply current characteristics (2) 30- to 80-pin package products with 192- to 256-KB flash ROM (2/4): Note 3 was modified.
37.3.2 Supply current characteristics (2) 30- to 80-pin package products with 192- to 256-KB flash ROM (4/4): Notes 5 and 8 were modified.
37.3.2 Supply current characteristics (3) 44- to 80-pin package products with 384- to 768-KB flash ROM, and 100- and 128-pin products (2/4): Note 3 was modified.
37.3.2 Supply current characteristics (3) 44- to 80-pin package products with 384- to 768-KB flash ROM, and 100- and 128-pin products (4/4): Notes 5 and 8 were modified.
37.4 AC Characteristics was modified.
37.5.3 Serial interface IICA (1) was modified.
37.5.3 Serial interface IICA (2) was modified.
37.5.3 Serial interface IICA (3) was modified.
37.6.3 D/A converter characteristics was modified.
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APPENDIX A REVISION HISTORY
(6/12)
Edition
Description
Chapter
Rev.0.80 37.6.4 Comparator characteristics was modified.
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +85°C (TARGET)
Rev.0.90 Table 1 - 1 List of Ordering Part Numbers was modified.
CHAPTER 1 OUTLINE
1.6 Outline of Functions: Tables were modified.
Table 3 - 7 List of Special Function Registers (SFRs) was modified. Table 3 - 8 List of Extended Special Function Registers (2nd SFRs) was modified.
CHAPTER 3 CPU ARCHITECTURE
Figure 4 - 12 Format of Output Current Control Enable Register (CCDE): Figure was modified and caution was added.
CHAPTER 4 PORT FUNCTIONS
4.3.14 40-mA port output control register (PTDC): The descriptions were modified.
Figure 4 - 14 Format of 40-mA Port Output Control Register (PTDC) was modified.
Figure 4 - 15 Format of Port Function Output Enable Register 0 (PFOE0) was modified.
Figure 4 - 16 Format of Port Function Output Enable Register 1 (PFOE1) was modified.
Table 4 - 5 Concept of Basic Settings: Table and note 1 were modified.
4.5.2 Register settings for alternate function whose output function is not used: The descriptions were modified.
Table 4 - 7 Examples of Register and Output Latch Settings for Alternate Functions (30-Pin to 64-Pin Products with 96-Kbyte or 128-Kbyte Flash Memory) was modified.
Table 4 - 8 Examples of Register and Output Latch Settings for Alternate Functions (Products with 192-Kbyte to 768-Kbyte Flash Memory and 80-Pin and 100-Pin Products with 128-Kbyte Flash Memory) was modified.
Table 5 - 2 Features of Each Flash Operation Mode: Note was modified.
CHAPTER 5 OPERATION STATE CONTROL
Figure 6 - 1 Block Diagram of Clock Generator: Figure and remark were modified.
Figure 6 - 7 Format of Peripheral Enable Register 0 (PER0): Figure was modified and note was deleted.
CHAPTER 6 CLOCK GENERATOR
Figure 6 - 8 Format of Peripheral Enable Register 1 (PER1): Figure was modified and note was deleted.
Figure 6 - 9 Format of Subsystem Clock Supply Mode Control Register (OSMC): Figure and notes 2 to 4 were modified.
6.3.8 Subsystem clock select register (CKSEL): The descriptions were modified.
Figure 6 - 10 Format of Subsystem Clock Select Register (CKSEL): Figure and note were modified.
6.5 Operations of the Clock Generator: The descriptions were modified.
Table 6 - 2 Examples of Transitions of the CPU Clock and SFR Settings was modified.
Figure 7 - 11 Format of Peripheral Enable Register 0 (PER0) was modified. Figure 7 - 12 Format of Peripheral Reset Control Register 0 (PRR0) was modified.
CHAPTER 7 TIMER ARRAY UNIT (TAU)
Figure 7 - 19 Format of Timer Input Select Register 0 (TIS0) was modified.
7.10.2 Point for caution when a timer output is to be used as an event input for the ELCL: The descriptions were modified.
Figure 8 - 3 Format of Subsystem Clock Supply Mode Control Register (OSMC): Figure, CHAPTER 8 REALTIME
note 1, and caution were modified.
CLOCK (RTC)
9.1 Overview: The descriptions were modified.
Table 9 - 1 Specifications of 32-Bit Interval Timer Operations: Table and remark were modified.
CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
Figure 9 - 1 Block Diagram of 32-Bit Interval Timer: Figure and note were modified.
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Edition
Description
Chapter
Rev.0.90
Table 9 - 2 List of Registers was modified.
Figure 9 - 2 Format of Peripheral Enable Register 1 (PER1): Figure was modified and note was deleted.
CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
Figure 9 - 3 Format of Peripheral Reset Control Register 1 (PRR1) was modified.
9.2.4 Interval timer compare registers 0mn (ITLCMP0mn) (mn = 00, 01, 12, 13): Title and descriptions were modified.
Figure 9 - 4 Format of Interval Timer Compare Registers 0mn (ITLCMP0mn) was modified.
9.2.5 Interval timer compare registers 0n (ITLCMP0n) (n = 0, 1): The descriptions were modified.
Figure 9 - 5 Format of Interval Timer Compare Registers 0n (ITLCMP0n) was modified.
9.2.6 Interval timer capture register 00 (ITLCAP00): The descriptions were modified.
Figure 9 - 6 Format of Interval Timer Capture Register 00 (ITLCAP00) was modified.
Figure 9 - 7 Format of Interval Timer Control Register (ITLCTL0): Figure and notes were modified.
Figure 9 - 8 Format of Interval Timer Clock Select Register 0 (ITLCSEL0): Figure and remark were modified.
9.2.9 Interval timer frequency division register 0 (ITLFDIV00): The descriptions were modified.
Figure 9 - 9 Format of Interval Timer Frequency Division Register 0 (ITLFDIV00): Figure and notes 1 and 2 were modified.
9.2.10 Interval timer frequency division register 1 (ITLFDIV01): The descriptions were modified.
Figure 9 - 10 Format of Interval Timer Frequency Division Register 1 (ITLFDIV01): Figure and notes 1 and 2 were modified.
Figure 9 - 11 Format of Interval Timer Capture Control Register 0 (ITLCC0): Figure was modified and note 7 was added.
9.2.12 Interval timer status register (ITLS0): The descriptions were modified.
Table 9 - 3 Conditions for Setting the Interrupt Status Flags in Each Timer Mode was modified.
9.2.13 Interval timer match detection mask register (ITLMKF0): The descriptions were modified.
Table 9 - 4 Registers and Settings Used in 8-Bit Counter Mode: Table and remark were modified.
Table 9 - 5 Registers and Settings Used in 16-Bit Counter Mode was modified.
Table 9 - 6 Registers and Settings Used in 32-Bit Counter Mode was modified.
Table 9 - 7 Registers and Settings Used in 16-Bit Capture Mode: Caution was added.
9.3.3 Timer operation: The descriptions were modified.
Figure 9 - 14 Example of Timer Operation: Figure and remark were modified.
9.3.4 Capture operation: The descriptions were modified.
Figure 9 - 15 Example of Capture Operation: Figure and remark were modified.
Table 9 - 8 Interrupt Sources in 8-Bit, 16-Bit, and 32-Bit Counter Modes was modified.
Figure 9 - 16 Procedure for Starting the 32-Bit Interval Timer was modified.
Figure 9 - 17 Procedure for Stopping the 32-Bit Interval Timer was modified.
Figure 9 - 18 Procedure for Changing the Operating Mode of the 32-Bit Interval Timer was modified.
Figure 9 - 19 Procedure for Resetting the 32-Bit Interval Timer was modified.
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APPENDIX A REVISION HISTORY
(8/12)
Edition
Description
Chapter
Rev.0.90 Figure 9 - 20 Procedure for Starting Event Input from the ELCL was modified. Figure 9 - 21 Procedure for Stopping Event Input from the ELCL was modified.
CHAPTER 9 32-BIT INTERVAL TIMER (TML32)
10.1 Functions of Clock Output/Buzzer Output Controller: Caution was modified.
Figure 10 - 1 Block Diagram of Clock Output/Buzzer Output Controller was modified.
Figure 10 - 2 Format of Clock Output Select Register n (CKSn): Figure, caution 3, and remark 2 were modified.
CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER (PCLBUZ)
12.3 Registers Controlling A/D Converter: The descriptions were modified. Figure 12 - 2 Format of Peripheral Enable Register 0 (PER0) was modified.
CHAPTER 12 A/D CONVERTER (ADC)
Figure 12 - 3 Format of Peripheral Reset Control Register 0 (PRR0) was modified.
Table 12 - 3 A/D Conversion Time Selection was modified.
Figure 12 - 8 Format of A/D Converter Mode Register 2 (ADM2) was modified.
12.8.2 A/D conversion by inputting a hardware trigger: The descriptions were modified and caution was added.
12.10 Points for Caution when the A/D Converter is to be Used: The descriptions were modified.
Figure 12 - 52 Analog Input Pin Connection was modified.
CHAPTER 13 D/A CONVERTER (DAC): The descriptions were modified. Figure 13 - 1 Block Diagram of D/A Converter was modified.
CHAPTER 13 D/A CONVERTER (DAC)
Figure 13 - 2 Format of Peripheral Enable Register 1 (PER1): Figure was modified and note was deleted.
Figure 13 - 3 Format of Peripheral Reset Control Register 1 (PRR1) was modified.
13.4.2 Operation in realtime output mode: The descriptions were modified.
Figure 13 - 6 Timing for Outputting D/A Conversion Value was modified.
13.5 Points for Caution when the D/A Converter is to be Used: (8) was deleted.
Figure 14 - 1 Comparator Block Diagram was modified.
Figure 14 - 2 Format of Peripheral Enable Register 1 (PER1): Figure was modified and note was deleted.
CHAPTER 14 COMPARATOR (CMP)
Figure 14 - 3 Format of Peripheral Reset Control Register 1 (PRR1): Figure was modified and caution 2 was added.
Figure 14 - 4 Format of Comparator Mode Setting Register (COMPMDR): Note 3 was added.
Figure 15 - 1 Block Diagram of Serial Array Unit 0 was modified. Figure 15 - 2 Block Diagram of Serial Array Unit 1 was modified.
CHAPTER 15 SERIAL ARRAY UNIT (SAU)
Figure 15 - 5 Format of Peripheral Enable Register 0 (PER0) was modified.
Figure 15 - 6 Format of Peripheral Reset Control Register 0 (PRR0) was modified.
Figure 15 - 22 Format of Input Switch Control Register (ISC): Figure was modified and notes 1 to 4 were added.
15.5.9 Procedure for Processing Errors that Occurred During 3-wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) Communication: The descriptions were modified.
Figure 16 - 5 Format of Peripheral Enable Register 0 (PER0) was modified. Figure 16 - 6 Format of Peripheral Reset Control Register 0 (PRR0) was modified.
CHAPTER 16 SERIAL INTERFACE IICA (IICA)
Figure 16 - 7 Format of IICA Control Register n0 (IICCTLn0): Note 2 was modified.
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APPENDIX A REVISION HISTORY
(9/12)
Edition
Description
Chapter
Rev.0.90 Figure 17 - 1 Block Diagram of UARTAn: Figure and remark were modified.
Figure 17 - 2 Format of Peripheral Enable Register 1 (PER1): Figure was modified and note was deleted.
CHAPTER 17 SERIAL INTERFACE UARTA (UARTA)
17.2.9 UARTA clock select register 0 (UTA0CK): The descriptions were modified.
Figure 17 - 10 Format of UARTA0 Clock Select Register (UTA0CK): Figure and remark were modified.
17.2.10 UARTA clock select register 1 (UTA1CK): The descriptions were modified.
Figure 17 - 11 Format of UARTA1 Clock Select Register (UTA1CK): Figure and remark were modified.
17.3.2 UART Mode, (4) Normal transmission: The descriptions were modified.
Table 17 - 8 Set Data of Baud Rate Generator was modified.
17.4.3 Point for Caution when Selecting the UARTAn Operation Clock (fUTAn): The descriptions were modified.
Table 18 - 1 Specifications of Remote Control Signal Receiver: Table and note 2 were modified.
Figure 18 - 1 Block Diagram of Remote Control Signal Receiver was modified.
CHAPTER 18 REMOTE CONTROL SIGNAL RECEIVER (REMC)
Figure 18 - 2 Format of Peripheral Enable Register 1 (PER1): Figure was modified and note was deleted.
Figure 18 - 3 Format of Peripheral Reset Control Register 1 (PRR1) was modified.
Figure 18 - 5 Format of Function Select Register 1 (REMCON1) was modified.
Figure 18 - 19 Format of Receiver Standby Control Register (REMSTC) was modified.
18.3.4 Operating Clock: The descriptions were modified.
Figure 18 - 28 RIN0 Internal Input Signal Generation Configuration was modified.
18.3.5 RIN0 Input: The descriptions were modified.
18.3.12 Interrupts: The descriptions were modified.
18.3.13 SNOOZE Mode Function: The descriptions and remark were modified.
Figure 18 - 44 Example of Flowchart for Setting up SNOOZE Mode was modified.
18.4.1 Register Access when Starting Operation of the Remote Control Signal Receiver: Title was modified.
18.4.2 Timing of Changing the Register Values: Title was modified.
18.4.4 Changing the Operating Clock: Title was modified.
Figure 19 - 5 Format of Peripheral Enable Register 1 (PER1): Note was deleted.
CHAPTER 19 DATA
TRANSFER CONTROLLER 19.5.8 Operation in standby mode: The descriptions were modified and note 1 was added. (DTC)
Table 20 - 1 Connections in Logic Cell Block L1: Note 2 was modified. Table 20 - 2 Connections in Logic Cell Block L2: Note 2 was modified. Table 20 - 3 Connections in Logic Cell Block L3: Note 2 was modified.
CHAPTER 20 LOGIC AND EVENT LINK CONTROLLER (ELCL)
Figure 20 - 5 Format of Input Signal Select Registers n (ELISELn) (n = 0 to 11): Notes 3 and 4 and caution 2 were modified.
Figure 20 - 6 Format of Event Link L1 Signal Select Registers n (ELL1SELn) (n = 0 to 3): Caution 2 was modified.
Figure 20 - 7 Format of Event Link L1 Signal Select Registers n (ELL1SELn) (n = 4, 5): Caution 2 was modified.
Figure 20 - 8 Format of Event Link L1 Signal Select Register 6 (ELL1SEL6): Caution 2 was modified.
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Edition
Description
Chapter
Rev.0.90
Figure 20 - 9 Format of Logic Cell Block L1 Control Register (ELL1CTL): Caution 2 was modified.
Figure 20 - 10 Format of Event Link L1 Output Select Registers n (ELL1LNKn) (n = 0 to 3): Caution 3 was modified.
CHAPTER 20 LOGIC AND EVENT LINK CONTROLLER (ELCL)
Figure 20 - 11 Format of Event Link L1 Output Select Registers n (ELL1LNKn) (n = 4, 5): Caution 3 was modified.
Figure 20 - 12 Format of Event Link L1 Output Select Register 6 (ELL1LNK6): Caution 2 was modified.
Figure 20 - 13 Format of Event Link L2 Signal Select Registers n (ELL2SELn) (n = 0 to 3): Caution 2 was modified.
Figure 20 - 14 Format of Event Link L2 Signal Select Registers n (ELL2SELn) (n = 4, 5): Caution 2 was modified.
Figure 20 - 15 Format of Event Link L2 Signal Select Register 6 (ELL2SEL6): Caution 2 was modified.
Figure 20 - 16 Format of Logic Cell Block L2 Control Register (ELL2CTL): Caution 2 was modified.
Figure 20 - 17 Format of Event Link L2 Output Select Registers n (ELL2LNKn) (n = 0 to 3): Caution 3 was modified.
Figure 20 - 18 Format of Event Link L2 Output Select Registers n (ELL2LNKn) (n = 4, 5): Caution 3 was modified.
Figure 20 - 19 Format of Event Link L2 Output Select Register 6 (ELL2LNK6): Caution 2 was modified.
Figure 20 - 20 Format of Event Link L3 Signal Select Registers n (ELL3SELn) (n = 0 to 3): Caution 2 was modified.
Figure 20 - 21 Format of Event Link L3 Signal Select Registers n (ELL3SELn) (n = 4, 5): Caution 2 was modified.
Figure 20 - 22 Format of Event Link L3 Signal Select Register 6 (ELL3SEL6): Caution 2 was modified.
Figure 20 - 23 Format of Logic Cell Block L3 Control Register (ELL3CTL): Caution 2 was modified.
Figure 20 - 24 Format of Event Link L3 Output Select Registers n (ELL3LNKn) (n = 0 to 3): Caution 3 was modified.
Figure 20 - 25 Format of Event Link L3 Output Select Registers n (ELL3LNKn) (n = 4, 5): Caution 3 was modified.
Figure 20 - 26 Format of Event Link L3 Output Select Register 6 (ELL3LNK6): Caution 2 was modified.
Figure 20 - 27 Format of Output Signal Select Registers n (ELOSELn) (n = 0 to 7) was modified.
Figure 20 - 28 Format of Output Signal Enable Register (ELOENCTL): Note was modified.
Table 20 - 5 Bits in Output Signal Enable Register and Event-Receiving Peripheral Functions: Table was modified and note 4 was added.
20.6 Points for Caution when the ELCL is to be Used: (1) and (3) were modified.
23.1 Standby Function: Caution 2 was modified. 23.2.2 Memory power reduction control register (PSMCR): The descriptions were added.
CHAPTER 23 STANDBY FUNCTION
Table 23 - 1 Operating Statuses in HALT Mode (1) was modified.
Table 23 - 2 Operating Statuses in HALT Mode (2) was modified.
Table 23 - 3 Operating Statuses in STOP Mode: Table and remark 1 were modified.
Table 23 - 4 Operating Statuses in SNOOZE Mode: Table and remark 1 were modified.
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Edition
Description
Chapter
Rev.0.90 Figure 24 - 7 Format of Peripheral Reset Control Register 0 (PRR0) was modified. Figure 24 - 8 Format of Peripheral Reset Control Register 1 (PRR1) was modified.
CHAPTER 24 RESET FUNCTION
25.1 Functions of Power-on-reset Circuit: The descriptions were modified.
Figure 25 - 2 Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector: Caution was modified.
CHAPTER 25 POWER-ONRESET CIRCUIT (POR)
Figure 25 - 2 Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector: Remark 2 was modified.
26.1 Functions of Voltage Detector: The descriptions were modified.
Figure 26 - 3 Format of Voltage Detection Register (LVIM): Figure was modified and note 4 was added.
CHAPTER 26 VOLTAGE DETECTOR (LVD)
Figure 26 - 5 Format of Voltage Detection Level Register (LVIS): Figure and notes 1 and 2 were modified.
26.4.1 When used as reset mode: The descriptions were modified.
Figure 26 - 7 Timing of LVD1 Internal Reset Signal Generation was added.
26.4.2 When used as interrupt mode: The descriptions were modified.
Figure 26 - 9 Timing of LVD1 Interrupt Signal Generation was added.
Figure 27 - 23 Format of UART Loopback Select Register (ULBS) was modified.
CHAPTER 27 SAFETY FUNCTIONS
Figure 29 - 2 Format of Peripheral Enable Register 1 (PER1): Figure was modified and note was deleted.
CHAPTER 29 SNOOZE MODE SEQUENCER (SMS)
Figure 29 - 3 Format of Peripheral Reset Control Register 1 (PRR1) was modified.
Table 29 - 3 Types of Processing Specified by the SMSIp Registers: Note 3 was modified.
29.5 Commands for Use in Processing by the Sequencer: The descriptions were modified.
29.5.1 8-bit data transfer 1: The descriptions were modified.
29.5.2 8-bit data transfer 2: The descriptions were modified.
29.5.3 16-bit data transfer 1: The descriptions were modified.
29.5.4 16-bit data transfer 2: The descriptions were modified.
29.5.5 1-bit data setting: The descriptions were modified.
29.5.6 1-bit data clearing: The descriptions were modified.
29.5.7 1-bit data transfer: The descriptions were modified.
29.5.12 Branch 1 (SCY = 1): The descriptions were modified.
29.5.13 Branch 2 (SCY = 0): The descriptions were modified.
29.5.14 Branch 3 (SZ = 1): The descriptions were modified.
29.5.15 Branch 4 (SZ = 0): The descriptions were modified.
29.5.16 Wait: The descriptions and note 1 were modified.
29.5.17 Conditional wait 1 (bit = 1): The descriptions were modified.
29.5.18 Conditional wait 2 (bit = 0): The descriptions were modified.
29.5.19 Termination: The descriptions were modified.
29.5.20 Interrupt plus termination: The descriptions were modified.
29.6 Operation in Standby Modes: The descriptions were modified and note 1 was added.
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APPENDIX A REVISION HISTORY
(12/12)
Edition
Description
Chapter
Rev.0.90 30.2 Registers Controlling CTSU: The descriptions were modified.
Figure 30 - 5 Format of Peripheral Enable Register 1 (PER1): Figure was modified and note was deleted.
CHAPTER 30 CAPACITIVE SENSING UNIT (CTSU2L)
Figure 30 - 6 Format of Peripheral Reset Control Register 1 (PRR1) was modified.
30.2.10 CTSU sensor counter register L/H (CTSUSC/CTSUUC): Title was modified.
Figure 30 - 14 Format of CTSU Sensor Counter Register L/H (CTSUSC/CTSUUC): Title was modified.
30.2.13 CTSU trimming register AL/AH (CTSUTRIM0/CTSUTRIM1): Title and the descriptions were modified.
Figure 30 - 17 Format of CTSU Trimming Register AL/AH (CTSUTRIM0/CTSUTRIM1): Title was modified.
30.2.14 CTSU trimming register BL/BH (CTSUTRIM2/CTSUTRIM3) was added.
Figure 32 - 2 Format of User Option Byte (000C1H or 040C1H) was modified. Figure 32 - 3 Format of User Option Byte (000C1H or 040C1H) was modified.
CHAPTER 32 OPTION BYTES
34.2 Connection between the External Device that Incorporates UART and RL78/G23: Note 3 was added.
CHAPTER 34 ON-CHIP DEBUGGING
Table 36 - 16 Operation List: Caution was modified.
CHAPTER 36 INSTRUCTION SET
37.2.1 Characteristics of the X1 and XT1 oscillators was modified.
37.2.2 Characteristics of the on-chip oscillators was modified.
37.3.2 Supply current characteristics, (1) 30- to 64-pin package products with 96- to 128Kbyte flash ROM (1/4): Note 2 was modified.
CHAPTER 37 ELECTRICAL CHARACTERISTICS TA = -40 to +105°C (TARGET)
37.3.2 Supply current characteristics, (1) 30- to 64-pin package products with 96- to 128Kbyte flash ROM (2/4): Note 3 was modified.
37.3.2 Supply current characteristics, (2) Peripheral Functions (Common to all products) was modified.
37.4 AC Characteristics was modified.
37.6.4 Comparator characteristics was modified.
37.6.6 LVD circuit characteristics, (1) LVD0 Detection Voltage in the Reset Mode and Interrupt Mode was modified.
37.6.6 LVD circuit characteristics, (2) LVD1 Detection Voltage of Reset Mode and Interrupt Mode was modified and Note was added.
37.6.7 Power supply voltage rising slope characteristics: Note was modified.
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Colophon
RL78/G23 User's Manual: Hardware
Publication Date: Rev.0.50 May 28, 2020 Rev.1.00 Apr 13, 2021
Published by:
Renesas Electronics Corporation
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RL78/G23
R01UH0896EJ0100
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