User Manual for ST models including: UM3247 Industrial Digital Output Expansion Board, UM3247, Industrial Digital Output Expansion Board, Digital Output Expansion Board, Output Expansion Board, Expansion Board, Board
Getting started with the X-NUCLEO-OUT17A1 industrial digital output expansion board for STM32 Nucleo - User manual
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DocumentDocumentUM3247
User manual
Getting started with the X-NUCLEO-OUT17A1 industrial digital output expansion board for STM32 Nucleo
Introduction
The X-NUCLEO-OUT17A1 is an industrial digital output expansion board for STM32 Nucleo. It provides a powerful and flexible environment for the evaluation of the driving and diagnostic capabilities of the IPS8200HQ-1 octal high-side, smart power, solidstate relay in a digital output module connected to 1.0 A industrial loads.
The X-NUCLEO-OUT17A1 interfaces with the microcontroller on the STM32 Nucleo via STISO620 and STISO621 and Arduino® UNO R3 connectors.
The user can select which driving mode controls the IPS8200HQ-1: parallel (SEL2 = L by JP21 = open) or SPI (SEL2 = H by JP21 = closed).
In the case of SPI selection, the user can select the communication protocol between 8 bits (SEL1 = L by JP22 = open) or 16 bits (SEL1 = H by JP22 = closed).
The VCC supply pin of the IPS8200HQ-1 is provided by the connector CN1, while the loads (driven by the eight output channels of the IPS8200HQ-1) can be connected between the connectors CN2, CN3, CN4, CN12, and the pin 2 of the connector CN1.
The on-board digital isolators (STISO620 and STISO621) feature the 2.8k VRMS (4k VPK) galvanic isolation between the two application sides: logic and process sides.
The logic side is the application side of the MCU and it is supplied by the VISO_L rail (3.3 or 5.0 V). VISO_L can be supplied by an external power supply connected to CN13 or, alternatively by the pin 4 (SW1 = close 1-2) or pin 5 (SW1 = close 2-3) of CN6.
The process side is the application side of the industrial loads and it is supplied by the VCC and VISO_P rails. The VISO_P (3.3 or 5.0 V) is usually supplied by the VREG rail (JP31 = closed) that can be generated by the step-down embedded in the IPS8200HQ-1 (SW17 = close 1-2, JP20 = closed, JP15 = closed and JP28 = close 2-4 (VREG = 3.3 V) or JP28 = 1-3 (VREG = 5.0 V)).
Alternatively, VREG can be provided by an external power supply connected to CN14 (SW17 = close 2-3, JP20 = open, JP15 = open).
In parallel driving mode (active with the default jumper and switch settings) the application board can work even without any Nucleo board: in this case, the user must provide the process side voltage (usually 24 V) by the CN1 and the VISO_L (usually 3.3 V) by the CN13. The INX signals, available on CN5[1, 2, 3], CN8[4] and CN9[3, 5, 7, 8], drives on/off the correspondent OUTX connected to the loads on the process side.
The INX pins can be driven low/high swinging between 0V and VISO_L. The activation of each OUTX (OUT1... OUT8) can be monitored by the green LEDs DOX (DO1... DO8).
The activation of the three diagnostic pins (TWARN, PGOOD, FAULT) can be visualized on the correspondent red LEDs (D11, D12, D13, respectively) or monitored by an oscilloscope on TP6, TP7, and TP5.
Note: Although the pins CN8[5], CN5[9], CN5[10] are connected to the nets FAULT_L, PGOOD_L and TWARN_L, these pins cannot correctly report the status of the corresponding signals on the process side (FAULT, PGOOD, and TWARN) due to routing mistake on the same side.
The SPI driving mode can be set by changing the default configuration (JP21 = close; SW4, SW5, SW6, SW7, SW9, SW10, SW11, SW12, SW13, SW14, SW15, and SW20 = close 2-3, SW18 = close 1-2). The SPI-8bits is the default mode (JP22 = open), while the SPI-16bits mode can be activated by JP22 = close.
In SPI driving mode it is also possible to activate the MCU freeze detection feature by setting SW3 = close 2-3.
The expansion board can be connected to either a NUCLEO-F401RE or a NUCLEO-G431RB development board. In this case the companion firmware X-CUBE-IPS detects the selected configuration (GPIO, SPI-8bits, SPI-16bits) by reading the signals SEL2_L and SEL1 from CN8[1] and CN8[6]. The activation of the MCU freeze feature is detected by WDEN(in) on CN9[4].
It is also possible to evaluate a system composed of a X-NUCLEO-OUT17A1 stacked on other expansion boards. In fact, SPI driving mode allows the daisy-chaining communication with another X-NUCLEO-OUT17A1 stacked through the Arduino connectors: the two stacked boards must be configured with SW6, SW18 = close 2-3 on one board, and SW6, SW18 = close 1-2 on the other board.
UM3247 - Rev 2 - April 2024 For further information contact your local STMicroelectronics sales office.
www.st.com
Figure 1. X-NUCLEO-OUT17A1 expansion board
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Getting started
1
Getting started
1.1
Overview
The X-NUCLEO-OUT17A1 embeds the IPS8200HQ-1 intelligent power switch (IPS), which features serial/parallel selectable interface on-chip, 8-bit and 16-bit SPI interface for IC command and control diagnostic, Power Good diagnostic, IC warning temperature detection, overcurrent and overtemperature protection for safe output loads control.
The board is designed to meet the application requirements for the galvanic isolation between the user and power interfaces.
An optical isolation satisfies this requirement. The isolation is implemented through three dual channel digital isolators with 2 0 channel directionality (U3, U11, U12) for the input signals forward to the device, and four dual channel digital isolators with 1 1 channel directionality (U4, U6, U7, U10) for the diagnostic feedback signals of the device and the daisy chaining service lines.
The expansion board features:
·
Based on the IPS8200HQ-1 octal high-side switch, which features:
Operating range 10.5 to 36 V
Operating output current 1.0 A
Low power dissipation (RON(MAX) = 200 m)
Undervoltage lock-out
Selectable driving modes parallel or 5 MHz SPI (8 or 16 bits)
Embedded step-down converter
4x2 LED matrix for efficient status indication
MCU freeze detection
Fast decay for inductive loads
Overload and overtemperature protections
Loss of ground protection
Junction Overtemperature and parity check diagnostic pin (FAULT)
Case overtemperature diagnostic pin (TWARN)
Supply voltage Level diagnostic pin (PGOOD)
QFN48L 8x6 mm package
·
Application board voltage operating range: 12 to 33 V
·
Extended voltage operating range (J9 open) up to 36 V
·
Operating current: up to 1.0 A per channel
·
Blue LED showing SPI mode selection
·
Yellow LED showing SPI mode 16-bits selection
·
Red LED for FAULT diagnostic pin (JP12 closed)
·
Red LED for PGOOD diagnostic pin (JP13 closed)
·
Red LED for TWARN diagnostic pin (JP27 closed)
·
4 kVPK galvanic isolation guaranteed by STISO620 and STISO621
·
Supply rail reverse polarity protection
·
Compatible with STM32 Nucleo development boards
·
Equipped with Arduino® UNO R3 connectors
·
RoHS and China RoHS compliant
·
CE certified
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1.2
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Getting started
Board configuration
A set of jumpers and switches is available to configure the board. Table 1 shows the configurations to be used respectively for Parallel 8 Channels Mode, SPI 8 Channels Mode and Daisy Chain Mode.
Table 1. X-NUCLEO-OUT17A1
Jumpers/Switches
Parallel 8 Ch
SW1, SW3, SW17
Closed 1-2
JP1, JP2, JP3, JP4, JP5, JP6, JP7, JP8, JP9, JP12, JP13, JP15, JP20, JP23, JP24, JP25, JP27, JP31
Closed
JP10, JP14, JP16, JP17, JP18, JP19 Open
JP11
Not mounted
JP28
Closed 2-4
JP29, JP30
Closed 1-2, 3-4, 5-6, 7-8
SW4, SW5, SW7, SW9, SW10, SW11, SW12, SW13, SW14, SW15
Closed 1-2
SW6
Closed 1-2
SW18 SW20 JP21 JP22
Open Closed 1-2 Open Open
SPI 8 Ch Closed 1-2
Daisy Chain Closed 1-2
Closed
Closed
Open Not mounted Closed 2-4
Closed 1-2, 3-4, 5-6, 7-8
Open Not mounted Closed 2-4
Closed 1-2, 3-4, 5-6, 7-8
Closed 2-3
Closed 2-3
Closed 2-3
Board 0: Closed 2-3 Board 1: Closed 1-2
Closed 1-2
Board 0: Closed 2-3 Board 1: Closed 1-2
Closed 2-3
Closed 2-3
Closed
Closed
Open (SEL1 L, SPI 8bits)
Open (SEL1 L, SPI 8bits)
Closed (SEL1 H, SPI 16 bits) Closed (SEL1 H, SPI 16 bits)
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Getting started
1.3
Digital section
The digital section is associated with the STM32 interface and the digital supply voltage to and from the XNUCLEO-OUT17A1 expansion board.
Figure 2. X-NUCLEO-OUT17A1 expansion board: digital interface section
The dotted green line indicates the whole digital interface section. The pink rectangles identify the Arduino® UNO R3 connectors and the yellow ones identify STISO620 and STISO621 digital isolators.
The four Arduino® UNO R3 connectors:
·
allow the expansion board to communicate with the STM32 Nucleo development microcontroller board
accessing the STM32 peripheral and GPIO resources;
·
provide the digital supply voltage between the STM32 Nucleo development board and the X-NUCLEO-
OUT17A1 expansion board, in either direction.
The five digital isolators (STISO620 and STISO621) provide 4 kVPK galvanic isolation between logic and process sides of the expansion board.
Usually, the STM32 Nucleo development board supplies the expansion board by a 3.3 V or 5.0 V generated by the USB.
Alternatively, it is possible to supply the STM32 Nucleo development board from the expansion board. In this case, an external supply voltage (7-12 V) should be connected to the CN11 connector (not mounted by default) on the expansion board and the ground loop should be closed by mounting D2 (enabling the reverse polarity protection) or by closing JP11 (without reverse polarity).
To supply the VIN voltage rail, it is necessary to:
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Getting started
·
close the JP5 jumper between pins 2 and 3 and open the JP1 jumper on the NUCLEO-F401RE;
·
open the JP5 jumper between pins 1 and 2 and close the JP5 jumper between pins 3 and 4 on the
NUCLEO-G431RB.
Logic side is then supplied by the VISO_L rail (3.3 V or 5.0 V). VISO_L can be supplied by an external power supply connected to CN13 (SW1 open) or, alternatively by the pin 4 (SW1 = close 1-2) or pin 5 (SW1 = close 2-3) of CN6.
The user can select which driving mode controls the IPS8200HQ-1: parallel (SEL2 = L by JP21 = open) or SPI (SEL2 = H by JP21 = closed). In the case of SPI selection, the user can select the communication protocol between 8 bits (SEL1 = L by JP22 = open) or 16 bits (SEL1 = H by JP22 = closed).
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Getting started
1.4
Power section
The power section involves the power supply voltage (CN1, pin 1 for VCC, pin 2 for GND), the load connection (eight loads can be connected between each pin of CN2, CN3, CN4, and CN12 and pin 2 of CN1), EMC protections (U2), and supply reverse polarity protection (D1).
Figure 3. X-NUCLEO-OUT17A1 expansion board: power section
1. IPS8200HQ-1 2. Output and power supply connector 3. Output channels - green LEDs 4. FAULT (diagnostic pin) red LED 5. PGOOD (diagnostic pin) red LED 6. TWARN (diagnostic pin) red LED 7. SEL2 H (SPI) blue LED 8. SEL1 H (16 bits SPI data width) yellow LED
The process side is supplied by the VCC and VISO_P rails. The VISO_P (3.3 or 5.0 V) is usually supplied by the VREG rail (JP31 = closed) that can be generated by the step-down embedded in the IPS8200HQ-1 (SW17 = close 1-2, JP20 = closed, JP15 = closed and JP28 = close 2-4 (VREG = 3.3 V) or JP28 = 1-3 (VREG = 5.0 V)). Alternatively, VREG can be provided by an external power supply connected to CN14 (SW17 = close 2-3, JP20 = open, JP15 = open).
For EMC:
·
the SMC30J30CA transient voltage suppressor (U2), enabled by closing J9, is placed between VCC and
GND tracks to protect the IPS8200HQ-1 against surge discharge on the supply rail path up to ±1 kV/2
coupling;
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Getting started
·
in the common mode surge testing, two single-layer capacitors (C11 and C12 - not included) must be
soldered at the predisposed locations;
·
the IPS8200HQ-1 output stages do not require additional EMC protections with respect to the
IEC61000-4-2, IEC61000-4-3, IEC61000-4-4, IEC61000-4-5, IEC61000-4-8 standards.
The EMC performance of the X-NUCLEO-OUT17A1 is detailed below:
·
for emission (when the DC input port of the board is powered by an AC-DC, DC-DC or battery with a cable
that does not exceed a three-meter length), compliance with standards:
EN IEC 61000-6-3:2021
EN 55032:2015 +A1:2020
·
for immunity, compliance with standards:
EN IEC 61000-6-1:2019
EN 55035:2017 +A11:2020
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Getting started
1.5
Hardware requirements
The X-NUCLEO-OUT17A1 expansion board is designed to be used with the NUCLEO-F401RE or NUCLEOG431RB STM32 Nucleo development boards.
To function correctly, the X-NUCLEO-OUT17A1 must be plugged onto the matching Arduino® UNO R3 connector pins on the STM32 Nucleo board as shown below.
Figure 4. X-NUCLEO-OUT17A1 and STM32 Nucleo stack
1.6
System requirements
To use the STM32 Nucleo development boards with the X-NUCLEO-OUT17A1 expansion board, you need:
·
a Windows PC/laptop (Windows 7 or above)
·
a type A to mini-B USB cable to connect the STM32 Nucleo board to the PC when using a NUCLEO-
F401RE development board
·
a type A to micro-B USB cable to connect the STM32 Nucleo board to the PC when using a NUCLEO-
G431RB development board
·
the X-CUBE-IPS firmware and software package installed on your PC/laptop
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Getting started
1.7
Board setup
Step 1. Connect the mini-USB or micro-USB cable to your PC to use the X-NUCLEO-OUT17A1 with NUCLEOF401RE or NUCLEO-G431RB development board
Step 2.
Download the proper firmware (.bin) onto the STM32 Nucleo development board microcontroller through STM32 ST-LINK utility, STM32CubeProgrammer, and according with the information detailed in the table below. The X-NUCLEO-OUT17A1 can be used to control the IPS8200HQ device in three different operating modes available for the user in three different example projects: Parallel_8_Channels (one board configured in parallel 8 channels mode, direct pin input interface), SPI_8_Channels (one board configured in SPI 8 channels mode, SPI input interface) and DaisyChain (two stacked boards properly configured in Daisy chain mode, SPI input interface with daisy chaining). The binary files provided with the X-CUBE-IPS software package enable the user to choose the preferred control mode by selecting the binary file contained in the proper example project Binary folder, as reported in the following table
Table 2. Nucleo development boards binary files
Nucleo board
Binary path
Projects\STM32F401RE-Nucleo\Examples\OUT17A1\DaisyChain\Binary\DaisyChain.bin
Projects\STM32F401RENUCLEO-F401RE Nucleo\Examples\OUT17A1\Parallel_8_Channels\Binary\Parallel_8_Channels.bin
Projects\STM32F401RENucleo\Examples\OUT17A1\SPI_8_Channels\Binary\SPI_8_Channels.bin
Projects\STM32G431RB-Nucleo\Examples\OUT17A1\DaisyChain\Binary\DaisyChain.bin
Projects\STM32G431RBNUCLEO-G431RB Nucleo\Examples\OUT17A1\Parallel_8_Channels\Binary\Parallel_8_Channels.bin
Projects\STM32G431RBNucleo\Examples\OUT17A1\SPI_8_Channels\Binary\SPI_8_Channels.bin
Note:
Additional details on each operating mode configuration are available inside the X-CUBE-IPS software package as reported in the below table:
Board configuration DaisyChain Parallel_8_Channels SPI_8_Channels
Table 3. Additional information on board configuration
Readme file Examples\OUT17A1\DaisyChain\readme.html Examples\OUT17A1\Parallel_8_Channels\readme.html Examples\OUT17A1\SPI_8_Channels\readme.html
Step 3. Step 4. Step 5. Step 6. Step 7.
Connect the IPS8200HQ-1 device supply voltage via CN1 (see Section 1.4: Power section). Provide the digital supply voltage (see Section 1.3: Digital section). Connect the load on the output connector (see Section 1.4: Power section). Reset the example sequence by pushing the black button on the STM32 Nucleo board. Push the blue button on the STM32 Nucleo board to choose among the examples provided in the default firmware package.
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UM3247 - Rev 2
2
Schematic diagrams
CN7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
SSQ-119-04-L-D N.M.
Figure 5. X-NUCLEO-OUT17A1 circuit schematic (1 of 3)
Morpho connectors (not mounted)
CN10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
SSQ-119-04-L-D N.M.
2
1
VCC
+ C9 N.M
47uF
C10 2.2uF
2
1
Analog supply 1 0 - 36 V
U2 C11
4700pF TP1 N.M. 5001 EARTH
SMC30J30CA
JP10 def aul t open
JP9 def aul t cl osed
C12 4700pF
N.M.
D1
STPS1H100A
OUT1 OUT2
OUT3 OUT4
OUT5 OUT6
OUT7 OUT8
1
CN1
2
691214110002
2 1
CN2
2 1
CN3
2 1
CN4
2 1
CN12
CN6
1 2 3 4 5 6 7 8
3v3 5v0
I OREF NRST 3V3 5V
VIN
SSQ-108-04-F-S
R55
220k
DEFAULT FAULT_L DEFAULT PGOOD_L
DEFAULT SPI_CLK DEFAULT SPI_MISO DEFAULT SPI_MOSI DEFAULT IN7/SPI_SS DEFAULT IN1 DEFAULT IN2/WDEN
VISO_L
SW3 3 2 1
def aul t : Cl ose 1- 2
R21 0
WDEN(in)
CN8 1 PA0 2 PA1 3 PA4 4 PB0 5 PC1 6 PC0
R120 R119 R118 R117 R116 R115
100 SEL2_L 100 OUT_EN 100 WD 100 IN5/DAISY_CHAIN 100 TWARN_L 100 SEL1
DEFAULT DEFAULT DEFAULT DEFAULT/ Al t er nat e use DEFAULT DEFAULT
DEFAULT IN3 DEFAULT IN4 DEFAULT IN6 DEFAULT WDEN(in) DEFAULT IN8
R108
100
R107
100
R106
100
R105
100
R104
100
R103
100
R102
100
R101
100
R60 220k
R51 220k
R52 220k
R53 220k
R54 220k
R56 220k
R57 220k
R58 220k
R114
100
R113
100
R111
100
R110
100
R109
100
C
SSQ-106-04-F-S
R37 R36
A
A
D18
D19
C
LED YELLOW
Arduino connectors
150 SEL2_L
150 SEL1
IN1 IN2/WDEN IN3 IN4
IN1 IN2/WDEN IN3 IN4
IN5/DAISY_CHAIN
IN6
IN6
IN7/SPI_SS
IN8
IN8
SPI_MISO SPI_MOSI SPI_CLK
OUT_EN
WD
SPI_MISO SPI_MOSI SPI_CLK
FAULT_L TWARN_L PGOOD_L
OUT_EN IN5/DAISY_CHAIN
WD
IN7/SPI_SS
CN5 PB8 10 PB9 9 AVDD 8
7 PA5 6 PA6 5 PA7 4 PB6 3 PC7 2 PA9 1
CN9 PA8 8 PB10 7 PB4 6 PB5 5 PB3 4 PA10 3 PA2 2 PA3 1 SSQ-108-04-F-S FAULT_L TWARN_L PGOOD_L
SSQ-110-04-F-S
VISO_L
C49 2.2uF
External logic side supply (3.3 or 5.0 V)
U9 ESDA15P60-1U1M
D15
BAT48JFILM JP16
default open
CN13
2 1
Alternate Nucleo supply 7 - 12 V
VIN
(7 - 12 V Nucleo supply open)
U5 ESDA15P60-1U1M N.M
CN11
2 1
D2 N.M.
BAT48JFILM
JP11
N.M.
LED BLUE
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Schematic diagrams
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UM3247 - Rev 2
VISO_L
VISO_L
SEL2_L SEL1
C35 100nF
8 VDD2 7 RXA 6 RXB 5 GND2
U12 VDD1 1
TXA 2 TXB 3 GND1 4
STISO620
C36 100nF
R59 220k
Figure 6. X-NUCLEO-OUT17A1 circuit schematic (2 of 3)
SEL2
VISO_P R22 270
JP22 Def aul t = Open. Cl ose t o set SEL1 = H ( = 16 bi t ) when SPI Mode i s sel ect ed by SEL2 = H.
VISO_P JP31
VREG
def aul t = cl ose
3v3
5v0
SW 1
def aul t :
cl ose 1- 2
3 2 1
VISO_L
IN1 IN2/W DEN
C37 100nF
U11 1 VDD1 2 TXA 3 TXB 4 GND1
STISO620
VDD2 8 RXA 7 RXB 6
GND2 5
VISO_L
TW ARN_L
C41 100nF
IN5/DAISY_CHAIN SPI_MOSI
SW 6 1 2 3
def aul t : cl ose 1- 2
U4 1 VDD1 2 RX1 3 TX1 4 GND1
STISO621
VISO_P
C38 100nF
R11 270
R33 C33
10k 100pF
SW 20 3 2 1
def aul t = cl ose 1- 2
SEL1/IN1
R12 270
R32
C32
10k
100pF
JP25 def aul t = cl ose
W D_EN/IN2
VISO_P
VDD2 8 TX2 7 RX2 6
GND2 5
C42 100nF
TW ARN
SW 14
3
R2
2
1
R7
R27
def aul t :
10k
cl ose 1- 2
100 270
C29
C21
100pF 4.7pF
SW 15 3 2 1
SDI/IN5
def aul t : cl ose 1- 2
IN3
SW 4 1
2
3
OUT_EN def aul t : cl ose 1- 2
IN4
SW 5 1
2
3
WD
def aul t :
cl ose 1- 2
VISO_L
C39 100nF
U3 1 VDD1 2 TXA 3 TXB 4 GND1
STISO620
VDD2 8 RXA 7 RXB 6
GND2 5
VISO_L
FAULT_L
IN6 SPI_CLK
SW 7 1 2 3
def aul t : cl ose 1- 2
C43 100nF
U10
1 VDD1
2 RX1
3 TX1
4 GND1
STISO621
VDD2 8 TX2 7 RX2 6
GND2 5
PGOOD_L IN7/SPI_SS
VISO_L
C45 100nF
U6
1 VDD1
2 RX1
3 TX1
4 GND1
STISO621
VDD2 8 TX2 7 RX2 6
GND2 5
VISO_P
C46 100nF
SW 9
3
R4
2
1
R10
R29
def aul t :
10k
cl ose 1- 2
PGOOD
100 270
C27
C23
100pF 4.7pF
SW 10 3 2 1
def aul t : cl ose 1- 2
SS/IN7
SPI_MISO IN5/DAISY_CHAIN
SW 18
1
2
3
IN8
def aul t : ALL OPEN
VISO_L
C47
U7
100nF 1 VDD1
2 RX1
3 TX1
4 GND1
STISO621
VDD2 8 TX2 7 RX2 6
GND2 5
C40 100nF
WD = H JP19 def aul t = open
VREG OUT_EN = H JP18 def aul t = open R13 270
R25 10k
R14 270
C31 100pF
R26
C30
10k
100pF
VISO_P
JP24
OUT_EN/IN3
def aul t = cl ose
JP23 def aul t = cl ose
W D/IN4
VISO_P
C44 100nF
FAULT
SW 12
3
R3
100
2
1
R8
270
R28 def aul t : 10k cl ose 1- 2
C28
C22
100pF 4.7pF
SW 13 3 2 1
CLK/IN6
def aul t : cl ose 1- 2
VISO_P
C48 100nF
R1 R9
R34
R30
10k
10k
100 270
C26 100pF
C24 3.3pF
SW 11 3 2 1
SDO/IN8
def aul t : cl ose 1- 2
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Schematic diagrams
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UM3247 - Rev 2
VCC R5 8k
JP14 def aul t : open
C13 0.1uF
Figure 7. X-NUCLEO-OUT17A1 circuit schematic (3 of 3)
R20
0
VREG
def aul t : open
JP21
VREG
External VREG supply (3.3 or 5.0 V)
U8 ESDA15P60-1U1M
D16
CN14
2 1
R31
C34
10k 100pF
BAT48JFILM
JP17
def aul t open
C
C
C
C
C
C
SEL2 SEL1/IN1
R6 270
WD_EN/IN2 OUT_EN/IN3 WD/IN4 SDI/IN5 CLK/IN6 SS/IN7 SDO/IN8 VREG
VREG
JP27
JP12
JP13
Def aul t = Def aul t = Def aul t =
cl osed cl osed cl osed
C15 0.1uF
R15
R16
R17
470
470
470
TWARN
JP29
FAULT PGOOD
def aul t = cl ose 1- 2 cl ose 3- 4 cl ose 5- 6 cl ose 7- 8
8
7
6
5
4
3
2
1
R38 150
COL0
COL1
DCVDD
R39
VREF
150 C16 C18 10nF 10nF
TP4 5001
1
3
5
7
JP30 def aul t = cl ose 1- 2 cl ose 3- 4 cl ose 5- 6 cl ose 7- 8
2
4
6
8
A
A
A
A
A
A
A
A
A
A
A
D11 RED
D13 RED
D12 RED
DO7 DO5 DO3 DO1 DO8 DO6 DO4 DO2
ROW0 ROW1
11 12 13 14 15 16 17 18 19 20 21 22 23 24
WD_EN/IN2 OUT_EN/IN3 WD/IN4 SDI/IN5 CLK/IN6 xSS/IN7 SDO/IN8 VREG COL0 COL1 DCVDD VREF ROW0 ROW1
ROW2 ROW3
25 26
TP8 5001
C
C
C
C
C
ROW2 ROW3
PGOOD FAULT TWARN
SEL1/IN1 SEL2
10 9
37 GND
Exp-VCC 49
32 33 34
xPGOOD xFAULT xTWARN
U1 IPS8200HQ-1
OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8
48 47 46 45 44 43 42 41
BOOT PHASE
39 38
FB 36
BOOT PHASE
FB
TP2 5001 TP3
5001
JP1
C1
def aul t = cl ose
JP2
C2
def aul t = cl ose
JP3
C3
def aul t = cl ose
JP4
C4
def aul t = cl ose
JP5
C5
def aul t = cl ose
JP6
C6
def aul t = cl ose
JP7
C7
def aul t = cl ose
JP8
C8
def aul t = cl ose
10nF
OUT1 10nF
OUT2 10nF
OUT3 10nF
OUT4 10nF
OUT5 10nF
OUT6 10nF
OUT7 10nF
OUT8
BOOT C14 22nF
PHASE
JP20
Def aul t =
cl osed
C25
D14
100pF
STPS1L60A
L1
1
2
JP15
VREG
100uH
def aul t = cl ose
R35
10k
R42 1k47
SW17
1
C19 10nF
FB 2
C17
3
DCVDD
JP28
4.7uF
1
2
def aul t = cl ose 1- 2
3
4
( 1- 2 => DCDC on)
( 2- 3 => DCDC of f )
R41
R40
def aul t = cl ose 2- 4
2k37 cl ose 2- 4 => 3v3
33k
cl ose 1- 3 => 5v0
TP5 5001
TP6 5001
TP7 5001
UM3247
Schematic diagrams
page 13/25
UM3247
Bill of materials
3
Bill of materials
Item 1 2 3 4 5 6 7 8 9 10
11 12 13
14 15
Q.ty 11 2 1 0 1 1 0 3 1 10
14 1 7
0 1
Table 4. X-NUCLEO-OUT17A1 bill of materials
Ref. C1 C2 C3 C4 C5 C6 C7 C8 C16 C18 C19
C13 C15
C14
C11 C12
C17
C10
C9
C21 C22 C23
C24
C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48
C49
CN1 CN2 CN3 CN4 CN11 CN12 CN13 CN14
CN11
CN5
Part/value
Description Manufacturer
Order code
10nF 0603 (1608 Metric) 50V 10%
CAP CER 10000PF 50V X7R 0603
Wurth Electronics Inc.
885382206002
0.1uF 0805 (2012 Metric) 100V 10%
CAP CER 0.1UF 100V X7R 0805
Wurth Electronics Inc.
885012207128
22nF 0603 50V 10%
Wurth Electronics Inc.
885382206003
4700pF 1825 (4564 Metric) 3000V (3kV) 10%
CAP CER 4700PF 3KV X7R 1825 (not assembled)
Vishay Vitramon HV1825Y472KXHATHV
4.7uF 0805 10V 10%
CAP CER 4.7UF 10V X7R 0805
Wurth Electronics Inc.
885012207025
2.2uF 1210 (3225 Metric) 100V 10%
CAP CER 2.2UF 100V X7R 1210
Wurth Electronics Inc.
885382209002
47uF (N.M.) Radial, Can 100V 20%
CAP 47 UF 20% 100 V (not assembled)
Wurth Electronics Inc.
860040875002
4.7pF 0603 10V 10%
CAP CER 4.7PF 10V COG 0603
Wurth Electronics Inc.
885012006001
3.3pF 0603 50V 10%
CAP CER 3.3PF 50V COG 0603
Wurth Electronics Inc.
885012006048
100pF 0603 25V 10%
CAP CER 100PF 25V X7R 0603
Wurth Electronics Inc.
885012206028
100nF 0603 10V 10%
CAP CER 0.1UF 10V X7R 0603
Wurth Electronics Inc.
885012206020
2.2uF 0603 10V 10%
CAP CER 2.2UF 10V X7R 0603
Wurth Electronics Inc.
885012206027
691214110002 7.4X7 pitch 3.5
TERM BLK 2POS SIDE ENT 3.5MM PCB
Wurth Electronics Inc.
691214110002
691214110002 7.4X7 pitch 3.5
TERM BLK 2POS SIDE ENT 3.5MM PCB (not assembled)
Wurth Electronics Inc.
691214110002
10 ways, 1 row
CONN RCPT 10POS 0.1 GOLD PCB
SAMTEC 4UCON
ESQ-110-14-T-S 17896
UM3247 - Rev 2
page 14/25
UM3247
Bill of materials
Item 16 17 18 19 20 21 22 23
24 25 26
27
28
Q.ty 2 0 1 8 1 3 1 2
0 1 1
26
0
Ref. CN6 CN9
CN7 CN10
CN8 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8
D1
D11 D12 D13
D14
D15 D16
D2
D18
D19 JP1 JP2 JP3 JP4 JP5 JP6 JP7 JP8 JP9 JP10 JP12 JP13 JP14 JP15 JP16 JP17 JP18 JP19 JP20 JP21 JP22 JP23 JP24 JP25 JP27 JP31
JP11
Part/value
Description Manufacturer
8 ways, 1row
CONN RCPT 8POS 0.1 GOLD PCB
SAMTEC 4UCON
CONN RCPT 38POS 0.1 GOLD PCB (not assembled)
Samtec Inc.
6 ways, 1 row
CONN RCPT 6POS 0.1 GOLD PCB
SAMTEC 4UCON
150060VS7500 LED GREEN 0 0603 (1608 CLEAR 0603 Metric) 20mA SMD
Wurth Electronics Inc.
STPS1H100A DO-214AC, SMA SMA Flat Notch 1A
DIODE SCHOTTKY 100V 1A SMA
ST
RED 0603 (1608 Metric) 20mA
LED RED CLEAR 0603 SMD
Wurth Electronics Inc.
STPS1L60A DO-214AC, SMA 1A
STMicroelectron ics
ST
BAT48JFILM
SC-76,
DIODE
SOD-323 750mV @
SCHOTTKY 40V 350MA
ST
200mA 350mA SOD323
(DC)
BAT48JFILM SC-76, SOD-323 750mV @ 200mA 350mA (DC)
DIODE SCHOTTKY 40V 350MA SOD323 (not assembled)
ST
BLUE 0402 20mA
LED LIGHT BLUE 0402 SMD
Wurth Electronics Inc.
YELLOW 0402 20mA
LED LIGHT YELLOW 0402 SMD
Wurth Electronics Inc.
JUMPER-con2strip-male
JUMPERCONN HEADER .100 STR 2POS
Wurth Electronics Inc.
JUMPER-con2strip-male
JUMPERCONN HEADER .100 STR 2POS (not assembled)
Wurth Electronics Inc.
Order code ESQ-108-14-T-S 15782 SSQ-119-04-L-D ESQ-106-04-T-S 15781 150060VS75000 STPS1H100A 150060RS75000 STPS1L60A BAT48JFILM
BAT48JFILM 150040BS73220 150040YS73220
61300211121
61300211121
UM3247 - Rev 2
page 15/25
UM3247
Bill of materials
Item 29 30 31 32 33 34 35 36 37 38 39 40 41
42
43 44
Q.ty 1 2 1 24 1 10 3 2 11 4 1 1 1
16
8 1
Ref.
Part/value
Description Manufacturer
Order code
JP28
con4-2x2-stripmale
CONN HEADER .100 DUAL STR 4POS
Wurth Electronics Inc.
61300421121
JP29 JP30
con8-2x4-stripmale
CONN HEADER .100 DUAL STR 8POS
Wurth Electronics Inc.
61300821121
L1
100uH
INDUCTOR
indm1030x1030 100UH 1A
x300l180x460 470MOHM
Wurth Electronics Inc.
744065101
R1 to R4 R101 to R111, R113 to R120
100 0603 (1608 Metric) 0.1W, 1/10W 1%
RES SMD 100 OHM 1% 1/10W Yageo 0603
RC0603FR-07100RP
R5
8k 0603 0.1W, 1/10W
RES SMD 8k OHM 1% 1/10W 0603
Vishay
PLTU0603U8001LST5
R6 to R14, R22
270 0603 0.1W, 1/10W
RES SMD 270 OHM 1% 1/10W Vishay 0603
CRCW0603270RJNECC
R15 R16 R17
470 0603 0.1W, 1/10W
RES SMD 470 OHM 1% 1/10W Vishay 0603
CRCW0603470RJNEBC
R20 R21
0 0603 0.1W, 1/10W
RES SMD 0 OHM 1% 1/10W Yageo 0603
RC0603JR-070RL
R25 to R35
10k 0603 0.1W, 1/10W
RES SMD 10k OHM 1% 1/10W Bourns 0603
CR0603-JW-103ELF
R36 R37 R38 R39
150 0603 0.1W, 1/10W
RES SMD 150 OHM 1% 1/10W Bourns 0603
CR0603-FX-1500ELF
R40
33k 0603 0.1W, 1/10W
RES SMD 33k OHM 1% 1/10W Bourns 0603
CR0603-JW-333ELF
R41
2.37k 0603 0.1W, 1/10W
RES SMD 2.37k OHM 1% 1/10W Bourns 0603
CR0603-FX-2371ELF
R42
1.47k 0603 0.1W, 1/10W
RES SMD 1.47k OHM 1% 1/10W Bourns 0603
CR0603-FX-1471ELF
SW1 SW3 SW4 SW5 SW6 SW7 SW9 SW10 SW11 SW12 SW13 SW14 SW15 SW17 SW18 SW20
con3-strip-male
CONN HEADER .100 STR 3POS
Wurth Electronics Inc.
61300311121
TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8
5001 0.100" Dia x 0.180" L (2.54mm x 4.57mm)
TEST POINT PC MINI .040"D BLACK
Keystone Electronics
5001
U1
IPS8200HQ-1 QFN48L 8x6 mm (opt A)
8 channel/1.0A high side driver
ST
IPS8200HQ-1
UM3247 - Rev 2
page 16/25
UM3247
Bill of materials
Item 45 46 47 48 49 50 51
Q.ty 3 4 2 0 1 55 10
Ref. U3 U11 U12
U4 U6 U7 U10
U8 U9
U5
U2
No Reference R51 R52 R53 R54 R55 R56 R57 R58 R59 R60
Part/value
Description Manufacturer
Order code
STISO620 SOIC8P127_49 0X600X175L83 X42N
Digital Isolator 2ch unidirectional
ST
STISO620
STISO621 SOIC8P127_49 0X600X175L83 X42N
Digital Isolator 2ch bidirectional
ST
STISO621
ESDA15P60-1U 1M 2-UDFN
TVS DIODE 13.2V 22.7V 1610
ST
ESDA15P60-1U1M
TVS DIODE
ESDA15P60-1U 13.2V 22.7V
1M 2-UDFN
1610 (not
ST
assembled)
ESDA15P60-1U1M
SMC30J30CA, TVS DIODE
DO-214AB,
33.3V 48.7V
ST
SMC
SMC, 3 kW
SMC30J30CA
jumper close 2.54mm jumper close 2.54mm
jumper close 2.54mm
Wurth Electronics Inc.
60900213421
220k 0603 0.1W, 1/10W
RES SMD 220k OHM 1% 1/10W ANY 0603
ANY
UM3247 - Rev 2
page 17/25
UM3247
Board versions
4
Board versions
Table 5. X-NUCLEO-OUT17A1 versions
PCB version
Schematic diagrams
Bill of materials
X$NUCLEO-OUT17A1 (1) X$NUCLEO-OUT17A1 schematic diagrams
X$NUCLEO-OUT17A1 bill of materials
1. This code identifies the X-NUCLEO-OUT17A1 evaluation board first version. It is printed on the board PCB.
UM3247 - Rev 2
page 18/25
UM3247
Regulatory compliance information
5
Regulatory compliance information
Notice for US Federal Communication Commission (FCC)
For evaluation only; not FCC approved for resale FCC NOTICE - This kit is designed to allow: (1) Product developers to evaluate electronic components, circuitry, or software associated with the kit to determine whether to incorporate such items in a finished product and (2) Software developers to write software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference. Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter 3.1.2.
Notice for Innovation, Science and Economic Development Canada (ISED)
For evaluation purposes only. This kit generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to Industry Canada (IC) rules. À des fins d'évaluation uniquement. Ce kit génère, utilise et peut émettre de l'énergie radiofréquence et n'a pas été testé pour sa conformité aux limites des appareils informatiques conformément aux règles d'Industrie Canada (IC).
Notice for the European Union
This device is in conformity with the essential requirements of the Directive 2014/30/EU (EMC) and of the Directive 2015/863/EU (RoHS).
Notice for the United Kingdom
This device is in compliance with the UK Electromagnetic Compatibility Regulations 2016 (UK S.I. 2016 No. 1091) and with the Restriction of the Use of Certain Hazardous Substances in Electrical and Electronic Equipment Regulations 2012 (UK S.I. 2012 No. 3032).
UM3247 - Rev 2
page 19/25
UM3247
References
6
References
Freely available on www.st.com:
·
IPS8200HQ-1 datasheet
·
UM3035: "Getting started with X-CUBE-IPS industrial digital output software for STM32 Nucleo"
·
NUCLEO-F401RE documentation
·
NUCLEO-G431RB documentation
UM3247 - Rev 2
page 20/25
Revision history
Date 14-Nov-2023 24-Apr-2024
UM3247
Table 6. Document revision history
Revision 1 2
Changes Initial release. Updated Introduction and Section 1.2: Board configuration.
UM3247 - Rev 2
page 21/25
UM3247
Contents
Contents
1 Getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Board configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 Digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.5 Hardware requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.6 System requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.7 Board setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Schematic diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3 Bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4 Board versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 5 Regulatory compliance information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 6 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
UM3247 - Rev 2
page 22/25
UM3247
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6.
X-NUCLEO-OUT17A1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Nucleo development boards binary files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Additional information on board configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 X-NUCLEO-OUT17A1 bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 X-NUCLEO-OUT17A1 versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
UM3247 - Rev 2
page 23/25
UM3247
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7.
X-NUCLEO-OUT17A1 expansion board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 X-NUCLEO-OUT17A1 expansion board: digital interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 X-NUCLEO-OUT17A1 expansion board: power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 X-NUCLEO-OUT17A1 and STM32 Nucleo stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 X-NUCLEO-OUT17A1 circuit schematic (1 of 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 X-NUCLEO-OUT17A1 circuit schematic (2 of 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 X-NUCLEO-OUT17A1 circuit schematic (3 of 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
UM3247 - Rev 2
page 24/25
UM3247
IMPORTANT NOTICE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2024 STMicroelectronics All rights reserved
UM3247 - Rev 2
page 25/25