OS02N10 2-Megapixel Product Brief

Low-Power, Enhanced Performance 2MP Image Sensor for Security Surveillance Cameras

The OSO2N10 is a 2-megapixel (MP) frontside illumination (FSI) image sensor. It features an optimized defective pixel correction (DPC) algorithm designed for higher sensitivity, improved performance, and increased reliability in IP and HD analog security cameras, including professional surveillance and outdoor home security cameras. The OSO2N10 supports an always-on mode for low-power capability.

The OSO2N10 utilizes a 2.5-micron pixel based on OMNIVISION's OmniPixel®3-HS technology. This cost-effective solution leverages FSI technology for true-to-life color reproduction in both bright and dark conditions. The optimized DPC algorithm enhances sensor quality and reliability by providing real-time correction of defective pixels that may occur throughout the sensor's lifecycle, particularly in harsh operating conditions. The OSO2N10 supports a resolution of 1920 x 1080 at 30 frames per second and is compatible with MIPI and DVP interfaces.

For more information, visit www.ovt.com.

Ordering Information

OS02N10-A44A-001A-Z (color, lead-free) 44-pin CSP

Applications

Security surveillance systems
IP cameras
HD analog cameras

Technical Specifications

Active Array Size: 1928 x 1088
Maximum Image Transfer Rate: Full-size: 1920H x 1080V @ 30 fps; Always-on mode: 480H x 270V @ 1 fps / 3 fps
Power Supply: Analog: 2.8V; I/O: 1.8V / 2.8V; Core: 1.5V
Power Requirements: Active: 100 mW
Output Interfaces: 10-bit 2-lane MIPI / 10-bit DVP
Temperature Range: Operating: -30°C to +85°C junction temperature; Stable: 0°C to +60°C junction temperature
Output Formats: 10-bit RGB RAW / 8-bit RGB RAW for AO mode
Lens Size: 1/3.27"
Lens Chief Ray Angle: 15° linear
Shutter: Rolling
Pixel Size: 2.5 µm x 2.5 µm
Image Area: 4820 µm x 2720 µm

Product Features

Programmable Controls: Frame rate, mirror and flip, cropping, windowing
Supports 2x2 color binning function
Supports output formats: 8-bit/10-bit RAW RGB
SCCB control interface for register programming
Supports MIPI 2-lane serial output interface
Supports DVP 8-bit/10-bit output interface
Operates at 1920H x 1080V @ 30 fps in 10-bit mode, or always-on mode 480H x 270V @ 1 fps / 3 fps in 8-bit mode
Supports automatic black level calibration
Supports multi-camera synchronous function
Supports dynamic defective pixel correction
32 bytes OTP integrated (1 byte for OSC, 20 bytes for product information, 11 bytes reserved for customer)

Functional Block Diagram

The functional block diagram illustrates the OSO2N10 image sensor architecture. It comprises an image sensor core, an image sensor processor, and an image output interface. The image sensor core includes the image array, column sample/hold, amplifier (AMP), and analog-to-digital converter (ADC). A gain control mechanism is integrated within the core. The image sensor processor (ISP) handles image processing. The image output interface includes a FIFO buffer and MIPI/DVP output. Control signals such as ECLK, EVSYNC, PCLK, VSYNC, HSYNC, and XSHUTDN are managed by timing generator and system control logic, which interfaces with a control register bank via an SCCB interface. Output data streams, including MCP/MCN, MDPO/MDNO, MDP1/MDN1, and D[9:0], are provided through the MIPI/DVP interface.

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