Owner's Manual for MIPOT models including: 32001506AUS, 32001506BUS, 32001506CUS, 32001506DUS, 32001506FUS, MiP Series Wireless Protocol Modules, MiP Series, Wireless Protocol Modules, Protocol Modules, Modules

Enrico Stulin

32001506-US Datasheet rev1.0

Mipot MIP 2AQJP-MIP 2AQJPMIP mip


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Wireless Protocol Modules MiP Series ­ Data Sheet
Wireless Protocol Modules MiP Series 32001506xUS Family
Stand Alone LoRaTM Modem with MCU
Datasheet

Overview
The 32001506xUS is a family of transceivers operating in the 915 MHz SRD Band optimized for very long range, low power applications, suitable for LPWA networks. Based on LoRa® RF Technology, it provides ultra-long range spread spectrum communication and high interference immunity.
Thanks to its small LGA form factor (11.3 x 8.9 mm only) and its low current consumption, this module allows the implementation of highly integrated low power (battery operated) solutions for Internet of Things (IoT) applications, security systems, sensor networks, metering, smart buildings, agriculture, supply chain.
The 32001506xUS family features a dual core microcontroller in which one is dedicated to the radio stack and the ARM Cortex M4 is free for the customer application firmware.
The available radio stacks support a wide range of applications as the wM-Bus standard (32001506AUS), or accelerating the development of a LoRaWAN application (32001506BUS) using the LoRa modulation, or performing a local star network using the LoRa Mipot stack (32001506CUS). Using the LoRa Modem stack (32001506DUS), it is easy to create point-topoint applications or build a more complex custom stack. The 32001506FUS contains all the forementioned stack allowing to switch between them at runtime.

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Wireless Protocol Modules MiP Series ­ Data Sheet
Contents
1. Product Features........................................................................................................ 3 2. Mechanical Dimensions ............................................................................................. 4 3. Pin Definition............................................................................................................. 5 4. Firmware development .............................................................................................. 7
4.1. Overview...................................................................................................................... 7 4.2. Memory organization .................................................................................................. 7
4.2.1. Available memory for 32001506AUS ................................................................... 7 4.2.2. Available memory for 32001506BUS ................................................................... 7 4.2.3. Available memory for 32001506CUS ................................................................... 8 4.2.4. Available memory for 32001506DUS ................................................................... 8 4.2.5. Available memory for 32001506FUS ................................................................... 8 4.3. Reserved Pins............................................................................................................... 8 5. Hardware integration................................................................................................. 9 5.1. Decoupling capacitors ................................................................................................. 9 5.2. Layout guidelines ......................................................................................................... 9 6. Electrical Characteristics............................................................................................. 9 6.1. Absolute Maximum Ratings......................................................................................... 9 6.2. Operating Condition .................................................................................................. 10 6.2.1. GENERAL ELECTRICAL CHARACTERISTICS @ 25 °C............................................. 10 6.2.2. RECEIVER ELECTRICAL CHARACTERISTICS @ 25 °C ............................................ 10 6.2.3. TRANSMITTER ELECTRICAL CHARACTERISTICS @ 25 °C..................................... 11 7. Temperature Range Curves .......................................................................................12 8. Exposure assessment ................................................................................................12 9. Antenna details.........................................................................................................13 10. Application Notes .....................................................................................................13 11. Ordering Information ................................................................................................14 12. Regulatory Approvals................................................................................................14 13. Revision History ........................................................................................................15

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Wireless Protocol Modules MiP Series ­ Data Sheet

1. Product Features

Mechanical highlights:
 Extremely compact dimensions  LGA pattern
Low power characteristics:
 Sleep current consumption 2.2 µA  11 mA in RX mode
Memories:
 196 kB Flash memory  32 kB RAM  512 B OTP
(One Time Programmable) memory

RF performances:
 -135 dBm Sensitivity @LoRa®  +20 dBm Output power
Additional features:
 ARM Cortex-M4 CPU  Preloaded radio library  Internal communication channel
with the radio peripheral  Based on STM32WL55J
Multiple Stacks available:
 wM-Bus (32001506AUS)  LoRaWAN (32001506BUS)  LoRa Mipot (32001506CUS)  LoRa Modem (32001506DUS)  LoRa Multistack (32001506FUS)

Emission designator:
LoRa® DTS: 500KF1D LoRa® FHSS: 125KFXD
Regulatory compliance:
 USA FCC Rules and Regulations CFR 47, Part 15, Subpart B (10-1-20 Edition)  USA FCC Part 15.247 (10-1-20 Edition): Operation within the bands 902 - 928 MHz,
2400 -2483.5 MHz, and 5725 - 5850 MHz.  USA FCC Part 15.209 (10-1-20 Edition): Radiated emission limits; general
requirements.  USA FCC 47 CFR Part 2.1091 Radiofrequency radiation exposure evaluation: mobile
devices.  ANSI C63.10-2013: American National Standard for Testing Unlicensed Wireless
Devices.  CANADA ICES-003 Issue 7 (October 2020)  CANADA RSS-247 Issue 2 (February 2017).  CANADA RSS-Gen Issue 5 amendment 1 (March 2019).  CANADA ISED RSS-102 Issue 5 (2015-03) ­ Radio Frequency Exposure Compliance
of Radiocommunication Apparatus (All Frequency Bands)

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2. Mechanical Dimensions

Wireless Protocol Modules MiP Series ­ Data Sheet

Note: Dimension in mm. General tolerance ±0.1mm. The tolerance is not cumulative.

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3. Pin Definition

Wireless Protocol Modules MiP Series ­ Data Sheet Top View

Bottom View

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Wireless Protocol Modules MiP Series ­ Data Sheet

32001506DUS LGA PAD
A1 A2 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 C1 C2 C3 C4 C5 C6 C7 C9

STM32WL BGA BALL
PA6 PA5 PA4 PC0 PC1 PB5 PB8 PB9 VDD PA7 PC6 PA2 PA3 PB6 PB7 PA15 VDDA VDD PH3-BOOT0 PA8 PA1 GND PA0 PB4 VREF+ GND

32001506DUS LGA PAD
D1 D2 D3 D4 D5 D6 D7 D8 D9 E1 E2 E4 E6 E7 E9 F1 F2 F9 G1 G2 G3 G5 G6 G7 G8 G9

STM32WL BGA BALL
GND PB10 PB11 GND PB14 PA10 VBAT PB13 PC2 GND GND PB1 PB2 PA12 PC3 ANT GND PB12 GND GND GND NRST SWDIO SWCLK SWO PA9

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4. Firmware development
4.1. Overview
The 32001506xUS family module is based on the STM32WL55J and embeds the necessary circuitry for the RF subsystem in the 868 MHz band. The MCU employs an asymmetrical dual core CPU comprised of an ARM Cortex-M4 and an ARM Cortex-M0+. The Cortex-M0+ core is reserved for the RF stack while the user code runs on the Cortex-M4. The communication between the cores is done using the Inter-Processor Communication Controller (IPCC). The RF stack is preloaded in the module and uses the same set of commands of the host-based version. For details about the MCU, please refer to STM32WL55J data sheet (DS13293) and reference manual (RM0453).
4.2. Memory organization
The memory available for the user code depend on the model because of different memory requirements of the different stacks, and is shown in the following tables.

4.2.1. Available memory for 32001506AUS

Start address End Address

Length

0x0800 0000

0x08031FFF

204800

0x2000 0000

0x2000 7FFF

32768

0x2000 8000

0x2000 83FF

1024

0x1FFF 7200

0x1FFF 73FF

512

Description
User Flash Memory User RAM IPCC RAM User OTP Memory

4.2.2. Available memory for 32001506BUS

Start address End Address

Length

0x0800 0000

0x08029FFF

172032

0x2000 0000

0x2000 7FFF

32768

0x2000 8000

0x2000 83FF

1024

0x1FFF 7200

0x1FFF 73FF

512

Description
User Flash Memory User RAM IPCC RAM User OTP Memory

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Wireless Protocol Modules MiP Series ­ Data Sheet

4.2.3. Available memory for 32001506CUS

Start address End Address

Length

0x0800 0000

0x0802C7FF

182272

0x2000 0000

0x2000 7FFF

32768

0x2000 8000

0x2000 83FF

1024

0x1FFF 7200

0x1FFF 73FF

512

Description
User Flash Memory User RAM IPCC RAM User OTP Memory

4.2.4. Available memory for 32001506DUS

Start address End Address

Length

0x0800 0000

0x0802 FFFF

196608

0x2000 0000

0x2000 7FFF

32768

0x2000 8000

0x2000 83FF

1024

0x1FFF 7200

0x1FFF 73FF

512

Description
User Flash Memory User RAM IPCC RAM User OTP Memory

4.2.5. Available memory for 32001506FUS

Start address End Address

Length

0x0800 0000

0x08021FFF

139264

0x2000 0000

0x2000 7FFF

32768

0x2000 8000

0x2000 83FF

1024

0x1FFF 7200

0x1FFF 73FF

512

Description
User Flash Memory User RAM IPCC RAM User OTP Memory

4.3. Reserved Pins

Some Pins of the STM32WL55J are reserved for internal use, so those are not available for the user application and must be not modified in any way.

· PA11 · PC4 · PC13

· PB0 · PC5 · PC15

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Wireless Protocol Modules MiP Series ­ Data Sheet
5. Hardware integration
5.1. Decoupling capacitors
Each power supply pin must be decoupled with capacitors with the values suggested in the figure.

5.2. Layout guidelines
For better noise rejection, put the decoupling capacitors as close as possible to the power pins of the module, giving precedence to the low value ones.
The trace connecting to the RF pin must have an impedance of 50 . For better performance, connect the GND pads around the RF pin without thermals.

6. Electrical Characteristics
6.1. Absolute Maximum Ratings Parameter
Supply Voltage (VDD) Radio Frequency Input Level, pin F1 Voltage Standing Wave Radio (VSWR) at RF Input, ANT, pad F1 I/O Pin voltage Storage Temperature Operating Temperature

Max.
3.9 0 10:1 VDD + 0.3 -40 ÷ 100 -40 ÷ 85

Unit
V dBm
V °C °C

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Wireless Protocol Modules MiP Series ­ Data Sheet

6.2. Operating Condition
Note: All RF parameters measured with input (pad F1, ANT) connected to a 50  impedance signal source or load.

6.2.1. GENERAL ELECTRICAL CHARACTERISTICS @ 25 °C

Parameter

Min. Typ. Max. Unit

Supply Voltage (VDD)

1.9

3.0

3.6

V

VDDA

0

-

3.6

V

VBAT

1.55

-

3.6

V

VIN

-0.3

-

VDD+0.3 V

Sleep DC Current

-

2.2

3.0

µA

Data Rate 2-FSK

-

-

48 kbit/s

Data Rate LoRa®

0.98

-

21.9 kbit/s

Notes

6.2.2. RECEIVER ELECTRICAL CHARACTERISTICS @ 25 °C

Parameter

Min. Typ. Max.

DC Current Drain

-

-

11

Operating Frequency

902.0

-

928.0

Channel Frequency Precision

-

±15

-

Sensitivity, 2-FSK

-

-115

-

Sensitivity, LoRa®

-

-135

-

Spurious radiated level

-

-

-57

Output Logic Low

GND

-

0.05

Output Logic High

VDD - 0.2 -

VDD

Unit
mA MHz kHz dBm dBm dBm
V V

Notes
6
2,3,5 2,4,5

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6.2.3. TRANSMITTER ELECTRICAL CHARACTERISTICS @ 25 °C

Parameter

Min. Typ. Max.

Current Drain (CW @20 dBm)

-

138

Operating frequency

902.0

-

Occupied Bandwidth LoRa® DTS

500

-

Occupied Bandwidth LoRa® FHSS

-

125

Operating Channel Width LoRa®

-

600

Operating Channel Width LoRa® FHSS

-

200

Maximum Output power (50  load) -

20

RF Output Impedance

-

50

Input Logic Low

GND

-

Input Logic High

VDD - 0.2 -

928.0
-
0.05 VDD

Unit
mA MHz kHz kHz kHz kHz
dBm  V V

Notes
1,2
8 8 1,2,7

Notes: 1) VDD = 3.6 V.
2) All RF parameters measured with input (pin F1, ANT) connected to 50  impedance signal source or load.
3) Pseudo random code NRZ, 2-FSK BER (bit error rate) = 0.1 % or better, 2-level FSK modulation without pre-filtering, Bit Rate = 4.8 kbit/s, frequency deviation = 5 kHz, filter bandwidth = 20 kHz.
4) LoRa® PER (packet error rate) = 1 %, packet of 64 bytes, preamble of 8 bytes, error correction code CR = 4/5, CRC on payload enabled, no reduced encoding, no implicit header.
5) Sensitivities given using highest LNA gain step.
6) Power consumption measured with -140 dBm signal and AGC ON.
7) In order not to exceed the maximum power permitted by the FCC PART 15 regulation, choose an appropriate antenna system and power supply.
8) Single hop OBW and OCW.

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7. Temperature Range Curves
Note: All RF parameters measured with input (pad F1) connected to a 50  impedance signal source or load.

Current mA

TX Current Drain vs. Temperature (CW mode)
130.0 125.0 120.0 115.0 110.0 105.0 100.0
95.0 90.0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 85
°C

Output TX Power vs. Temperature (CW mode)

21.0

20.5

20.0

19.5

19.0

18.5

18.0

17.5

17.0

16.5

16.0 -40 -30 -20 -10 0

10 20 30 40 50 60 70 85

°C

VDD = 2.1 V VDD = 3.0 V VDD = 3.6 V
VDD = 2.1 V VDD = 3.0 V VDD = 3.6 V

Power dBm

8. Exposure assessment
A conservative evaluation distance of 20 cm has been used to perform the assessment. The Maximum Gain to meet FCC Radiofrequency radiation exposure limits is:

Technology/Mode LoRa

Band
ISM (USA)

Frequency (MHz)
902 - 928

Distance (cm)
20

FCC General Population Limit
(mW/cm2)
0.60

Maximum Gain to comply with RF Exposure Limits (dBi)
16.10

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9. Antenna details
To perform the assessments the following antenna has been used as reference:

Antenna model Parameters Standards Band (MHz)
Frequency (MHz) Return Loss (dB)
VSWR Efficiency (%) Peak Gain (dBi) Average Gain (dB) Impedance () Polarization Radiation Pattern Max. Input Power (W)

868 863 - 870
 -7.8 2.4:1 66.1 2.7 -1.8

2J0B15 ­ C885G 868/915 MHz ISM Antenna ZigBee, ISM, SIGFOX, LoRa
50 Linear Omni-Directional
25

915 902 ­ 928
-8.0
2.4:1 75.2 3.3 -1.2

10. Application Notes

Title
Command Reference Manual Command Reference Manual Command Reference Manual Command Reference Manual Command Reference Manual
Manufacturing Process Information for LGA MiP Series Modules
STM32WL55J data sheet
STM32WL55J reference manual

Description
Description of commands for the wM-Bus stack
Description of commands for the LoRaWAN stack
Description of commands for the LoRa Mipot stack
Description of commands for the LoRa Modem stack
Description of commands for the multi-stack module
Packaging information, Tape& Reel Specification, Reflow soldering information
Overview of the MCU and its peripherals
Detailed description of the MCU and its peripherals

Doc
32001506AUS_Com_Ref 32001506BUS_Com_Ref 32001506CUS_Com_Ref 32001506DUS_Com_Ref 32001506FUS_Com_Ref
AN_MNF002
DS13293 (from ST) RM0453 (from ST)

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Wireless Protocol Modules MiP Series ­ Data Sheet

11. Ordering Information

Title
32001506AUS 32001506BUS 32001506CUS 32001506DUS 32001506FUS

Description
MiP-Wm-2C256N-US MiP-Lw-2C256N-US MiP-LoMi-2C256N-US MiP-LoMo-2C256N-US MiP-LwMo-2C256N-US

DoC
United States United States United States United States United States

12. Regulatory Approvals

Models: 32001506AUS, 32001506BUS, 32001506CUS, 32001506DUS, 32001506FUS

U.S. FCC ID: 2AQJP-MIP
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.

CANADA IC: 28566-MIP HVIN: 32M01514

PMN: HMN:

32001506AUS, 32001506BUS, 32001506CUS, 32001506DUS, 32001506FUS -

32M01514 HVIN:
FVIN: -

Doc
DoI

Title
32001505BUS_DoI

Description
Declaration of Identity

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Wireless Protocol Modules MiP Series ­ Data Sheet

13. Revision History

Revision Date

0.0

20.09.2022 Draft

Description

0.1

23.11.2022 Added 32001506AUS module references

1.0

03.11.2023

Added regulatory approvals labels, exposure assessment and antenna details

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References

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