User Guide for Atmel models including: ATF1502AS-ASL, ATF1504AS-ASL, ATF1508ASV-ASVL, ATF15xx-DK3-U Development Kit, ATF15xx-DK3-U, Development Kit, Kit

ATF15xx-DK3-U Development Kit - This document describes in detail the ATF15xx-DK3-U CPLD Development/Programmer Board, Adapter Boards and JTAG ISP download cable.

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Atmel-8961-CPLD-ATF15xx-DK3-U-Development-Kit-UserGuide
ATF15xx-DK3-U
CPLD Development/Programmer Kit
USER GUIDE

Introduction
The Atmel® ATF15xx-DK3-U Complex Programmable Logic Device (CPLD) Development/Programmer Kit is a complete development system and an In-System Programming (ISP) programmer for the Atmel ATF15xx Family of industry standard pin compatible CPLDs with Logic Doubling® features. This kit provides designers a very quick and easy way to develop prototypes and evaluate new designs with an ATF15xx ISP CPLD. The ATF15xx Family of ISP CPLDs includes the Atmel ATF15xxAS, ATF15xxASL, ATF15xxASV, and ATF15xxASVL CPLDs. With the availability of the different socket adapter boards to support most of the package types(1) offered in the ATF15xx Family of ISP CPLDs, this kit can be used as an ISP programmer to program the ATF15xx ISP CPLDs in most of the available package types(1) through the industry standard JTAG interface (IEEE 1149.1).

Kit Contents
 CPLD Development/Programmer Board (ATF15xx-DK3)  44-pin TQFP Socket Adapter Board (ATF15xxDK3-SAA44)(2)  ATF15xx USB-based JTAG ISP Download Cable (ATDH1150USB or ATDH1150USB-K)  Two Atmel 44-pin TQFP Sample Devices

Device Support

The ATF15xx-DK3-U CPLD Development/Programmer Kit supports the following devices in all currently available Atmel speed grades and packages (except the 100-PQFP):

 ATF1502AS/ASL  ATF1504AS/ASL  ATF1508ASV/ASVL

 ATF1502ASV  ATF1504ASV/ASVL  ATF1508AS/ASL

1. The socket adapter board is not offered for the 100-pin PQFP. 2. Only the 44-pin TQFP Socket Adapter Board is included in this kit. Other socket adapter boards are sold separately. See
"Hardware Description" section for more information on socket adapter board ordering codes.
Atmel-8961A-CPLD-ATF15xx-DK3-U-Development-Kit-UserGuide_072015

Table of Contents
Kit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
CPLD Development/Programmer Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Logic Doubling CPLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ATF15xx ISP Download Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 PLD Development Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
CPLD Development/Programmer Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7-segment Displays with Selectable Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 LEDs with Selectable Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Push-button Switches with Selectable Jumpers for I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Push-button Switches with Selectable Jumpers for GCLR and OE1 Pins . . . . . . . . . . . . . . . . . . . . . 9 2MHz Oscillator and Clock Selection Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VCCIO and VCCINT Voltage Selection Jumpers and LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ICCIO and ICCINT Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power Supply Switch and Power LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power Supply Jack and Power Supply Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 JTAG ISP Connector and TDO Selection Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Socket Adapter Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Atmel ATF15xx ISP Download Cable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
References and Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Atmel ProChip Designer Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Atmel WinCUPL Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Atmel ATMISP Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Atmel POF2JED Conversion Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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Kit Features

CPLD Development/Programmer Board
 10-pin JTAG-ISP Port  Regulated Power Supply Circuits for 9VDC Power Source  Selectable 5V, 3.3V, 2.5V, or 1.8V I/O Voltage Supply  Selectable 1.8V, 3.3V, or 5.0V Core Voltage Supply  44-pin TQFP Socket Adapter Board  Headers for I/O Pins of the ATF15xx Device  2MHz Crystal Oscillator  Four 7-segment LED Displays  Eight Individual LEDs  Eight Push-button Switches  Global Clear and Output Enable Push-button Switches  Current Measurement Jumpers
Logic Doubling CPLDs
 ATF15xx ISP CPLD with Logic Doubling Architecture
ATF15xx ISP Download Cable
 5V, 3.3V, 2.5V, or 1.8V ISP Download Cable for the Universal Serial Bus (USB) port of a PC There are two versions of the ATF15xx USB ISP Download Cable; ATDH1150USB and ATDH1150USB-K. They are built by two different vendors but have identical circuit design, and the Atmel Ordering Code is ATDH1150USB. The ATDH1150USB-K is built by Kanda (www.kanda.com) and it can be directly purchased from Kanda. More details are available online at www.atmel.com/tools/ATDH1150USB.aspx.
PLD Development Software
The Atmel PLD development software tools are available online for PLD designer's use of the ATF15xx ISP CPLDs. Please reference the Overview document, "PLD Design Software Overview" available at: http://www.atmel.com/images/atmel-3629-pld-design-software-overview.pdf

System Requirements
The minimum hardware and software required to program an ATF15xx ISP CPLD device designed using the Atmel ProChip Designer Software on the CPLD Development/Programmer Board through the Atmel ATMISP (ATF15xx CPLD ISP Software) are:
 x86 or x64 Microprocessor-based Computer  Windows XP® or Windows 7  128-MByte RAM  500-MByte Free Hard Disk Space  Windows-supported Mouse  Available USB 1.1 / 2.0 / 3.0 Port  9VDC Power Supply with 500mA of Supply Current  SVGA Monitor (800 x 600 Resolution)

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Ordering Information

Atmel Part Number ATF15xx-DK3-U

Description
CPLD Development/Programmer Kit (includes the ATF15xxDK3-SAA44(1) and ATDH1150USB or ATDH1150USB-K)

ATF15xxDK3-SAA100

100-pin TQFP Socket Adapter Board for DK3 Board

ATF15xxDK3-SAJ44

44-pin PLCC Socket Adapter Board for DK3 Board

ATF15xxDK3-SAJ84

84-pin PLCC Socket Adapter Board for DK3 Board

ATF15xxDK3-SAA44(1)

44-pin TQFP Socket Adapter Board for DK3 Board

Note:

1. Only the 44-pin TQFP Socket Adapter Board is included in this kit. Other socket adapter boards are sold separately. See "Hardware Description" section for more information on socket adapter board ordering codes.

Hardware Description

CPLD Development/Programmer Board

The CPLD Development/Programmer and Socket Adapter Boards shown in the below figure contain features that are useful for developing, prototyping, or evaluating ATF15xx CPLD designs. Features that make this a very versatile starter/development kit and an ISP programmer for the ATF15xx family of JTAG-ISP CPLDs include:

 Push-button Switches  LEDs  7-segment Displays  2MHz Crystal Oscillator

 5V, 3.3V, 2.5V, or 1.8V VCCIO Selector  1.8V, 3.3V, or 5.0V VCCINT Selector  JTAG ISP Port
 Socket Adapters

Figure 1.

CPLD Development/Programmer Kit with 44-pin TQFP Socket Adapter Board
Voltage VccIO GCLR GOE Regulators Selector Switch Switch

VccIO LED VCCINT Selector
VccINT LED Power LED Clock Selector
Power Switch Oscillator
Power Supply Jack Power Supply Header JTAG Cascade Jumper
JTAG ISP Header

7-Segment Displays IccIO Jumper IccINT Jumper ATF15xxDK3-SAA44 Socket Adapter Board
User I/O Pin Headers
Device Socket LEDs Push-Button Switches

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7-segment Displays with Selectable Jumpers
The CPLD Development/Programmer Board contains four 7-segment displays which allow the observation of the ATF15xx CPLD outputs. These four displays are labeled as DSP1, DSP2, DSP3, and DSP4. The 7-segment displays have common anode LEDs with the common anode lines connected to the VCCIO (I/O supply voltage for the CPLD) through a series of resistors with selectable jumpers labeled as JPDSP1, JPDSP2, JPDSP3, and JPDSP4. These jumpers can be removed to disable the displays by unconnecting the VCCIO to the displays. Individual cathode lines are connected to the I/O pins of the ATF15xx CPLD on the CPLD Development/Programmer Kit. To turn on a particular segment, including the DOT of a display, the corresponding ATF15xx I/O pin connected to this LED segment must be in a logic low state with the corresponding selectable jumper set; therefore, the outputs of the ATF15xx device will require configuration for active-low outputs in the design file. The displays work best at 2.5V VCCIO or higher.
Each segment of each display is hard-wired to one specific I/O pin of the ATF15xx device. For the higher pin count devices (100-pin and larger), all seven segments and the DOT segments of the four displays are connected to the I/O pins; however, for the lower pin count devices, only a subset of the displays, first and fourth displays, are connected to the ATF15xx device's I/O pins. Tables 1 and 2 show the 7-segment display package connections to the ATF15xx device. The circuit schematic of the displays and jumpers is shown in the figure below.
Figure 2. Circuit Diagram of 7-segment Display and Jumpers

DOT1 DOT2 DOT3 DOT4

RDOT1

RDOT2

RDOT3

RDOT4

VccIO
JPDSP1 JPLED1
DSP1

JPDSP2 JPLED2
DSP2

JPDSP3 JPLED3
DSP3

JPDSP4 JPLED4
DSP4

Vc1 Vc2 DOT Vc1 Vc2 DOT Vc1 Vc2 DOT Vc1 Vc2 DOT

a

f

b g

ec d

a

f

b g

ec d

a

f

b g

ec d

a

f

b g

ec d

a b c d e f g

a b c d e f g

a b c d e f g

a b c d e f g

RDSP41 RDSP43 RDSP45 RDSP47

RDSP31 RDSP33 RDSP35 RDSP37

RDSP21 RDSP23 RDSP25 RDSP27

RDSP11 RDSP13 RDSP15 RDSP17

RDSP42 RDSP44 RDSP46

RDSP32 RDSP34 RDSP36

RDSP22 RDSP24 RDSP26

RDSP12 RDSP14 RDSP16

D4A D4B D4C D4D D4E D4F D4G

D3A D3B D3C D3D D3E D3F D3G

D2A D2B D2C D2D D2E D2F D2G

D1A D1B D1C D1D D1E D1F D1G

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Table 1. ATF15xx 44-pin Connections to 7-segment Displays

44-pin TQFP

DSP/Segment PLD Pin DSP/Segment PLD Pin

1/A

27

3/A

NC

1/B

33

3/B

NC

1/C

30

3/C

NC

1/D

21

3/D

NC

1/E

18

3/E

NC

1/F

23

3/F

NC

1/G

20

3/G

NC

1/DOT

31

3/DOT

NC

2/A

NC

4/A

3

2/B

NC

4/B

10

2/C

NC

4/C

6

2/D

NC

4/D

43

2/E

NC

4/E

35

2/F

NC

4/F

42

2/G

NC

4/G

34

2/DOT

NC

4/DOT

11

44-pin PLCC

DSP/Segment PLD Pin DSP/Segment PLD Pin

1/A

33

3/A

NC

1/B

39

3/B

NC

1/C

36

3/C

NC

1/D

27

3/D

NC

1/E

24

3/E

NC

1/F

29

3/F

NC

1/G

26

3/G

NC

1/DOT

37

3/DOT

NC

2/A

NC

4/A

9

2/B

NC

4/B

16

2/C

NC

4/C

12

2/D

NC

4/D

5

2/E

NC

4/E

41

2/F

NC

4/F

4

2/G

NC

4/G

40

2/DOT

NC

4/DOT

17

Table 2. ATF15xx 84-pin and 100-pin Connections to 7-segment Displays

84-pin PLCC

DSP/Segment PLD Pin DSP/Segment PLD Pin

1/A

68

3/A

22

1/B

74

3/B

28

1/C

70

3/C

25

1/D

63

3/D

21

1/E

58

3/E

16

1/F

65

3/F

17

1/G

61

3/G

12

1/DOT

73

3/DOT

29

2/A

52

4/A

5

2/B

57

4/B

10

2/C

55

4/C

8

2/D

48

4/D

79

2/E

41

4/E

76

2/F

50

4/F

77

2/G

45

4/G

75

2/DOT

56

4/DOT

11

100-pin TQFP

DSP/Segment PLD Pin DSP/Segment PLD Pin

1/A

67

3/A

13

1/B

71

3/B

19

1/C

69

3/C

16

1/D

61

3/D

8

1/E

57

3/E

83

1/F

64

3/F

6

1/G

60

3/G

92

1/DOT

75

3/DOT

20

2/A

52

4/A

100

2/B

54

4/B

94

2/C

47

4/C

97

2/D

41

4/D

81

2/E

46

4/E

76

2/F

40

4/F

80

2/G

45

4/G

79

2/DOT

56

4/DOT

93

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LEDs with Selectable Jumpers
The CPLD Development/Programmer Board has eight individual LEDs, which allow designers to display the output signals from the user I/Os of the ATF15xx devices. These eight LEDs are labeled LED1 to LED8 on the CPLD Development/Programmer Board. The cathode of each LED is connected to Ground (GND) through a series resistor, while the anode of each LED is connected to a user I/O pin of the CPLD through the JPL1/2/3/4/5/6/7/8 selectable jumper. These jumpers can be removed to disable the LEDs by unconnecting the anodes of the LEDs to the I/O pins of the CPLD. The figure below illustrates the circuit diagram of the LEDs with the selection jumpers.
To turn on a particular LED, the corresponding ATF15xx I/O pin connected to the LED must be in a logic high state with the corresponding jumper set; therefore, the outputs of the ATF15xx device will need to be configured as active high outputs. The LEDs work best at 2.5V VCCIO or higher. The lower pin count devices (44-pin) only have four I/Os connected to LED1/2/3/4. For the higher pin-count devices (100-pin and larger), all eight LEDs are connected to the I/Os of the device. Table 3 shows the different package connections of the CPLD I/Os to the LEDs.
Figure 3. Circuit Diagram of the LEDs and Jumpers

RL1

RL2

RL3

RL4

330

330

330

330

RL5

RL6

RL7

RL8

330

330

330

330

LED1 GREEN

LED2 GREEN

LED3 GREEN

LED4 GREEN

LED5 GREEN

LED6 GREEN

LED7 GREEN

LED8 GREEN

JPL1 SIP2

JPL2 SIP2

JPL3 SIP2

JPL4 SIP2

JPL5 SIP2

JPL6 SIP2

JPL7 SIP2

JPL8 SIP2

LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8

Table 3. ATF15xx Connections to LEDs

44-pin TQFP

LED PLD Pin

LED1

28

LED2

25

LED3

22

LED4

19

44-pin PLCC

LED PLD Pin

LED1

34

LED2

31

LED3

28

LED4

25

84-pin PLCC

LED PLD Pin

LED1

69

LED2

67

LED3

64

LED4

60

LED5

27

LED6

24

LED7

18

LED8

15

100-pin TQFP

LED PLD Pin

LED1

68

LED2

65

LED3

63

LED4

58

LED5

17

LED6

14

LED7

10

LED8

9

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Push-button Switches with Selectable Jumpers for I/O Pins
The CPLD Development/Programmer Board contains eight push-button switches, which are connected to the I/O pins of the CPLD. The switches send input logic signals to the user I/O pins of the ATF15xx device. These switches are labeled SW1 to SW8 on the CPLD Development/Programmer Board. One end of each input push-button switch is connected to VCCIO, while the other end of each push-button switch is connected to a pull-down resistor and then connected to the specific I/O pin of the CPLD through the JPS1/2/3/4/5/6/7/8 selectable jumper.
If any one of these switches is pressed and the corresponding jumper is set, the specific I/O pin of the device will be driven to a logic high state by the output of switch circuit. Since each push-button switch is also connected to a pull-down resistor, the input will have a logic low state if the switch is not pressed with the corresponding jumper set. If the push-button jumper is not set, the corresponding pin will be treated as an unconnected pin. Figure 4 is a circuit diagram of the push-button switch and selectable jumper. Table 4 shows the connections of these eight push-button switches to the CPLD I/O pins in the different package types.
Figure 4. Circuit Diagram of the Push-button Switches and Jumpers for the I/O Pins

SW1

R19 1K

JPS1

R29

SIP2

1K

VCCIO

C13 0.001uF

SW1

Table 4. ATF15xx Connections to the I/O Pin Switches

44-pin TQFP

Push Button PLD Pin

SW1

15

SW2

14

SW3

13

SW4

12

SW5

8

SW6

5

SW7

2

SW8

44

44-pin PLCC

Push Button PLD Pin

SW1

21

SW2

20

SW3

19

SW4

18

SW5

14

SW6

11

SW7

8

SW8

6

84-pin PLCC

Push Button PLD Pin

SW1

54

SW2

51

SW3

49

SW4

44

SW5

9

SW6

6

SW7

4

SW8

80

100-pin TQFP

Push Button PLD Pin

SW1

48

SW2

36

SW3

44

SW4

37

SW5

96

SW6

98

SW7

84

SW8

99

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Push-button Switches with Selectable Jumpers for GCLR and OE1 Pins
The CPLD Development/Programmer Board contains two push-button switches for the Global Clear (GCLR) and Output Enable (OE1) pins of the CPLD. The switches control the logic states of the OE1 and GCLR inputs of the ATF15xx devices. These switches are labeled SW-GCLR and SW-GOE1 on the board. One end of the SW-GCLR input push-button switch is connected to GND. The other end of the push-button switch is connected to a pull-up resistor to VCCIO, and then connected to the GCLR dedicated input pin of the ATF15xx device. It is intended to be used as an active-low reset signal to reset the registers in the ATF15xx device with the JPGCLR selectable jumper set. Similarly, one end of the SW-GOE1 input push-button switch is connected to GND. The other end of the push-button switch is connected to a pull-up resistor to VCCIO, and then connected to the OE1 dedicated input pin of the ATF15xx device. It is intended to be used as an active-low output enable signal to control the enabling/disabling of the tri-state output buffers in the ATF15xx with the JPGOE selectable jumper set. Figure 5 is the circuit diagram of the push-button switches and the jumpers for the GCLR and OE1 pins.
If any of these push-button switches is pressed and the corresponding jumper is set, the specific I/O of the CPLD will be driven to a logic low state. Since each push-button is also connected to a pull-up resistor, the corresponding CPLD input will have a logic high state if the push-button switch is not pressed with the corresponding selectable jumper set. If the selectable jumper is not set, the corresponding dedicated input pin of the CPLD can be considered a No Connect (NC) pin. Table 5 shows the pin numbers of the GCLR and OE1 dedicated input pins of the ATF15xx devices in all available package types.
Figure 5. Circuit Diagram of Push-button Switches and Selectable Jumpers for GCLR and OE1
VccIO

GCLR R37 1K

R15 1K
JPGCLR

R16 1K

JPGOE

R38

1K

GOE

C7 0.001uF

SW-GCLR SW-GCLR

SW-GOE SW-GOE

C8 0.001uF

Table 5. Pin Numbers of GCLR and OE1

44-pin TQFP

44-pin PLCC

GCLR

39

1

OE1

38

44

84-pin PLCC 1 84

100-pin TQFP 89 88

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2MHz Oscillator and Clock Selection Jumper The Clock Selection Jumper labeled JP-GCLK on the CPLD Development/Programmer Board is a two-position jumper that allows the users to select which GCLK dedicated input pin (either GCLK1 or GCLK2) of the ATF15xx device should be connected to the output of the 2MHz oscillator. In addition, the jumper can be removed to allow an external clock source to be connected to GCLK1 and/or GCLK2 of the ATF15xx device. Figure 6 is an illustration of the circuit diagram of the oscillator and selection jumper. Table 6 shows the pin numbers for the GCLK1 and GCLK2 dedicated input pins of the ATF15xx device in all the different available package types.
If GCLK1 jumper is set, the jumper will be located toward the side of the board. On the other hand, if GCLK2 jumper is set, the jumper will be located toward the middle of the board.
Figure 6. Circuit Diagram of Oscillator and Clock Selection Jumper
JPGCLK

1 2 3

GCLK2
R17 1K

GCLK1
R18 1K R39 100

C21 0.1uF

VccOSC

OSC

1

4

2

3

2MHZ

Table 6. Pin Numbers of GCLK1 and GCLK2

44-pin TQFP

44-pin PLCC

GCLK1

37

43

GCLK2

40

2

84-pin PLCC 83 2

100-pin TQFP 87 90

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VCCIO and VCCINT Voltage Selection Jumpers and LEDs The VCCIO and VCCINT Voltage Selection Jumpers, labeled VCCIO Selector and VCCINT Selector respectively on ATF15xx-DK3 Development/Programming Kit, allow the selection of the I/O supply voltage level (VCCIO) and core supply voltage level (VCCINT) that are used for the target CPLD on the kit. Once these jumpers are set correctly, the LEDs (labeled VCCINT LED and VCCIO LED) will turn on; however, at lower supply voltage levels (i.e. 2.5V or lower), the LEDs might be very dim.
 For ATF15xxAS/ASL (5.0V) CPLDs, both the VCCIO Selector and VCCINT Selector jumpers must be set to 5.0V.
 For ATF15xxASV/ASVL (3.3V) CPLDs, both the VCCIO Selector and VCCINT Selector Jumpers must be set to 3.3V only.
The power of the CPLD Development/Programmer Kit must be turned OFF when changing the position of the VCCIO or VCCINT Voltage Selection Jumper (VCCIO Selector or VCCINT Selector).
ICCIO and ICCINT Jumpers The ICCIO and ICCINT jumpers can be removed and used as ICC measurement points. When the jumpers are removed, current meters can be connected to the posts to measure the current consumption of the target CPLD. When users are not using these jumpers to measure the current, these jumpers must be set in order for the kit and CPLD to operate.
Voltage Regulators
Two voltage regulators, labeled VR1 and VR2, are used to independently generate and regulate the VCCINT and VCCIO voltages from the 9VDC power supply. For details, please see the ATF15xx-DK3 kit schematic, Figure 11.
Power Supply Switch and Power LED
The Power Supply Switch, labeled POWER SWITCH, can be switched to the on or off position, which is used to turn on or off the power of the ATF15xx-DK3 board respectively. It allows the 9VDC voltage at the Power Supply Jack to pass to the voltage regulators when it is in the on position. When the Power Supply Switch is turned on, the Power LED (labeled POWER LED) will light up to indicate that the ATF15xx-DK3 Kit is supplied with power.
Power Supply Jack and Power Supply Header
The ATF15xx-DK3 board contains two different types of power supply connectors labeled JPower and JP Power. Either one of these power supply connectors can be used to connect a 9VDC power source to the kit. The first power connector labeled JPower, is a barrel power jack with a 2.1mm diameter post, and it mates to a 2.1mm (inner diameter) x 5.5mm (outer diameter) female plug. The second power supply header labeled JP Power, is a 4-pin male 0.100" header with 0.025" square posts. The availability of these two types of power connectors allows the users to choose the type of power supply equipment to use for ATF15xx-DK3 Development/Programmer Kit.
Only one of these two power supply connectors should be powered with a 9VDC source but not both at the same time.

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JTAG ISP Connector and TDO Selection Jumper
The JTAG ISP Connector labeled JTAG-IN, is used to connect the ATF15xx JTAG port pins (TCK, TDI, TMS, and TDO) through the ISP download cable to the parallel printer (LPT) port of a PC for JTAG ISP programming of the ATF15xx device. Polarized connectors are used on the ATF15xx-DK3 and ISP Download Cable to minimize connection problems. The PIN1 label at the bottom of the JTAG ISP connector indicates the pin 1 position of the 10-pin header and further reduces the chance of connecting the ISP Download Cable incorrectly.
To the left of the JTAG-IN connector, there are two columns of vias, and they are labeled JTAG-OUT. They are intended to allow the users to create a JTAG daisy chain to perform JTAG operations to multiple devices. Users will need to solder the same type of connector as the one used for JTAG-IN into the JTAG-OUT position in order to utilize this available feature.
To create a JTAG daisy chain using multiple ATF15xx-DK3 boards, the TDO Selection Jumper, labeled JP-TDO, must be set to the appropriate position. For all the devices in the daisy chain except the last device, this jumper must be set to the TO NEXT DEVICE position. For the last device in the chain, this jumper must be set to the TO ISP CABLE position. When this jumper is in the TO NEXT DEVICE position, the TDO of that particular JTAG device will be connected to the TDI of the next JTAG device in the chain. When this jumper is in the TO ISP CABLE position, the TDO of that device will be connected to the TDO of the JTAG 10-pin connector, which will allow the TDO signal of the that device in the chain to be transmitted back to the host PC with the ISP software. The figure below is a circuit diagram of the JTAG connectors and the JP-TDO jumper. The table below lists the pin numbers of the four JTAG pins for the ATF15xx device in all the available packages.
For a single device setup, the position of the JP-TDO jumper must be set to TO ISP CABLE.

Figure 7. Circuit Diagram of the JTAG ISP Connectors and TDO Jumper

VCCIO

VCCIO

JTAG-IN

1

2

3

4

5

6

7

8

9

10

R11 R12 R13 R14 4.7K 4.7K 4.7K 10K

JTAG-OUT

1

2

3

4

5

6

7

8

9

10

TCK TMS TDI

JP-TDO
3 2 1

TDO

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Table 7. Pin Numbers of JTAG Port Signals

TDI TDO TMS TCK

44-pin TQFP 1 32 7 26

44-pin PLCC 7 38 13 32

84-pin PLCC 14 71 23 62

100-pin TQFP 4 73 15 62

The ISP algorithm is controlled by the ATMISP software, which is running on the PC. The four JTAG signals are generated and buffered by the ISP download cable before going into the ATF15xx device on the CPLD Development/Programmer board. The 10-pin JTAG Port Header pinout on the CPLD Development/Programmer board is shown in Figure 8, and the dimensions of this 10-pin male JTAG header are shown in Figure 9.

Figure 8. 10-pin JTAG Port Header Pinout

10-Pin JTAG Port Header (Top View)

GND 10

NC 8

NC 6

VCC

4

GND 2

9 TDI 7 NC 5 TMS 3 TDO 1 TCK

Figure 9. 10-pin Male Header Dimensions

Top View

0.100

0.100

Side View 0.025 Sq.

All dimensions are in inches.

0.235

The 10-pin JTAG Port Header pinout is compatible with the ATDH1150USB and ATDH1150USB-K USB based ISP cables as well as the ATDH1150PC/VPC and ByteBlaster/MV/II LPT port based ISP cables. ATMISP v6.7 supports both the USB and LPT port based ISP cables while ATMISP v7.x and later only supports the USB port based ISP cables.

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Socket Adapter Board
The ATF15xx-DK3 CPLD Development/Programmer Socket Adapter Boards (ATF15xxDK3-XXXXX) are circuit boards that interface with the ATF15xx-DK3 CPLD Development/Programmer Board. They are used in conjunction with the ATF15xx-DK3 CPLD Development/Programmer Board to evaluate or program ATF15xx ISP CPLD devices in different package types. There are four Socket Adapter Boards available for the ATF15xx-DK3 covering the 44-TQFP, 44-PLCC, 84-PLCC, and 100-TQFP package types in the ATF15xx family of CPLDs. Each socket adapter board contains a socket for the ATF15xx device and has male headers on the bottom side, labeled JP1 and JP2. The headers on the bottom side mate with the female headers on the ATF15xx-DK3 board, labeled JP4 and JP3. The four 7-segment displays, push-button switches, JTAG port signals, oscillator, VCCINT, VCCIO, and GND on the CPLD Development/Programmer Board are connected to the ATF15xx device on the Socket Adapter Board through these two sets of connectors. On the top of the 44-TQFP socket adapter, there are four 10-pin connectors with the same dimensions as the JTAG ISP connector. The pins of these four connectors are connected to the input and I/O pins (except the four JTAG pins) of the target CPLD device. They can be used to connect to an oscilloscope or logic analyzer to capture the activities of the input and I/O pins of the CPLD. They also can be used to connect the input and I/O pins of the CPLD to other external boards or devices for system level evaluation or testing.
Atmel ATF15xx ISP Download Cable
The ATF15xx USB ISP Download Cable connects the USB port of the PC to the 10-pin JTAG header on the CPLD Development/Programmer Board or a custom circuit board. This ISP cable also acts as a buffer to buffer the JTAG signals for the JTAG devices on the target circuit board. The status LED on the ATF15xx USB ISP Download Cable indicates whether the communication between the PC and the target JTAG devices and the JTAG operation are successful or not. This ISP cable contains a standard B USB connector, which is connected to the USB port of a PC. The 10-pin female plug connects to the 10-pin male JTAG header on the ISP circuit board. The red color stripe on the ribbon cable indicates the orientation of pin 1 of the female plug. The 10-pin male JTAG header on the CPLD Development/Programmer Board is polarized to prevent users from inserting the female plug in the wrong orientation. The CPLD Development/Programmer kits includes the ATF15xx USB ISP Download Cable (ATDH1150USB or ATDH1150USB-K); however, other supported ISP cables can also be used. The ATDH1150VPC, ATDH1150USB, ByteBlasterMV, and ByteBlasterII cables can be used for the ATF15xx/ASL (5V) and ATF15xxASV/ASVL (3.3V) devices, while the older ATDH1150PC and the ByteBlaster cables can be used for the ATF15xxAS/ASL (5V) only. Figure 10 illustrates the 10-pin female header pinout for the ATF15xx ISP Download Cable. The 10-pin male header pinout on the PC board (if used for ISP) must match this pinout.
Figure 10. ATF15xx ISP Download Cable 10-pin Female Header Pinout Color Stripe
13 5 79
2 4 6 8 10
Note: The circuit board must supply VCC and GND to the CPLD ISP Cable through the 10-pin male header.
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DOT1 DOT2 DOT3 DOT4

Schematic Diagrams
Figure 11. ATF15xx-D3 Development/Programmer Kit Schematic Diagram

VCCINT GND D1B D1C D1A D1F D1D D1G D1E
TCK D2B D2A D2C D2F D2D D2G D2E GND VCCIO

JP3

1

2

3

4

5

6

7

8

9 10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

35 36

37 38

39 40

GND GND DOT1 LED1 LED2 LED3 TDO LED4
DOT2 SW1 SW2 SW3 SW4
GND GND

GND GND GOE GCLR GCLK2 GCLK1
SW8 SW7 SW6 SW5 DOT4
LED8 LED7 LED6 LED5
DOT3 GND GND

JP4

1

2

3

4

5

6

7

8

9 10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

35 36

37 38

39 40

VCCINT GND D4G D4E D4F D4D TDI D4A D4C D4B TMS D3G D3E D3F D3D D3A D3C D3B GND VCCIO

RDOT1

RDOT2

RDOT3

RDOT4

VccIO
JPDSP1 JPLED1
DSP1

a

f

b g

ec d

JPDSP2 JPLED2
DSP2

a

f

b g

ec d

JPDSP3 JPLED3
DSP3

a

f

b g

ec d

JPDSP4 JPLED4
DSP4

a

f

b g

ec d

Vc1 Vc2 DOT Vc1 Vc2 DOT Vc1 Vc2 DOT Vc1 Vc2 DOT

LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8

RL1

RL2

RL3

RL4

330

330

330

330

RL5

RL6

RL7

RL8

330

330

330

330

LED1 GREEN

LED2 GREEN

LED3 GREEN

LED4 GREEN

LED5 GREEN

LED6 GREEN

LED7 GREEN

LED8 GREEN

JPL1

JPL2

JPL3

JPL4

SIP2

SIP2

SIP2

SIP2

JPL5

JPL6

JPL7

JPL8

SIP2

SIP2

SIP2

SIP2

a b c d e f g

a b c d e f g

a b c d e f g

a b c d e f g

RDSP47

RDSP45

RDSP43

RDSP41

RDSP37

RDSP35

RDSP33

RDSP31

RDSP27

RDSP25

RDSP23

RDSP21

RDSP17

RDSP15

RDSP13

RDSP11

D4F RDSP46

D4D RDSP44

D4B RDSP42

D3F RDSP36

D3D RDSP34

D3B RDSP32

D2F RDSP26

D2D RDSP24

D2B RDSP22

D1F RDSP16

D1D RDSP14

D1B RDSP12

D4G

D4E

D4C

D4A

D3G

D3E

D3C

D3A

D2G

D2E

D2C

D2A

D1G

D1E

D1C

D1A

R19

R21

R23

1K

1K

1K

SW1

JPS1

R29

SW2 SW1

JPS2

R31

SW3 SW2

JPS3

R33

SW3

SIP2

1K

SIP2

1K

SIP2

1K

VCCIO

C13 0.001uF

VCCIO

C15 0.001uF

VCCIO

C17 0.001uF

R20

1K

SW5

JPS5

R30

SW6 SW5

SIP2

1K

R22

1K

JPS6

R32

SW7 SW6

SIP2

1K

R24 1K

JPS7

R34

SW7

SIP2

1K

VCCIO

C14 0.001uF

VCCIO

C16 0.001uF

VCCIO

C18 0.001uF

R25

1K

SW4

JPS4

R35

SW4

SIP2

1K

VCCIO

C19 0.001uF

R26

1K

SW8

JPS8

R36

SW8

SIP2

1K

VCCIO

C20 0.001uF

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9V DC Center Positive JPower
9VDC 500mA

1 2 3 4 1 ADJ

JP JP Power

VccIN

VR1 LM317 3 Vin

D4

D1

POWER SWITCH

+Vout

2
C3 R2 0.1uF C4 510
10uF

R3 240

1N4001

R28 1K

C1

C2

100uF 0.1uF

R4

JPIO18

270

1.8V(BE)

JP1 VccIO IccIO
D2
R1 1K

GCLR R37 1K

VccIO

R15 R16

1K

1K

JPGCLR

JPGOE

R38

GOE

1K

VccIO

VccINT

R5 330 JPIO25 2.5V(BE)
R6 JPIO33 680 3.3V(ASV/BE)

C7 0.001uF

SW-GCLR SW-GCLR

SW-GOE SW-GOE

C8 0.001uF

C9

C10

C12 C11

0.1uF 0.1uF 0.1uF 0.1uF

JPIO50 5V(AS)

MARK BIGATMEL ATMEL

1 ADJ 1 2 3
1 ADJ

VR2 LM317 VCCIN 3 Vin
JPINT18 1.8V(BE)

+Vout

2

JP2 VccINT IccINT

VR3 LM317 VCCIN 3 Vin

C5

R7

0.1uF

C6

510 10uF

D3

R8 240
R27 1K
R9 620

R10 680 JPINT33 3.3V(ASV)

+Vout

2

C22

R40

0.1uF

510

VccOSC
C23 10uF

R41 820

JTAG-IN

1

2

3

4

5

6

7

8

9 10

JPINT50 5.0(AS)

JPGCLK

GCLK2
R17 1K

GCLK1
R18 1K R39 100

VccOSC OSC

C21

1

4

0.1uF

2

3

2MHZ

JTAG-OUT

1

2

3

4

5

6

7

8

9 10

VccIO

VccIO
R11 R12 R13 R14 4.7K 4.7K 4.7K 10K

TCK TMS TDI

JP-TDO

3 2

TDO

1

15

Figure 12. 44-pin TQFP Socket Adapter Board Schematic Diagram
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PIN38 PIN39 PIN40 PIN37 PIN44 PIN2 PIN5 PIN8 PIN11

GND GND GOE GCLR GCLK2 GCLK1
SW8 SW7 SW6 SW5 DOT4
LED8 LED7 LED6 LED5
DOT3 GND GND

JP1

1

2

3

4

5

6

7

8

9 10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

35 36

37 38

39 40

VCCINT GND D4G D4E D4F D4D TDI D4A D4C D4B TMS D3G D3E D3F D3D D3A D3C D3B GND VCCIO

PIN34 PIN35 PIN42 PIN43
PIN3 PIN6 PIN10

PIN2 PIN5 PIN8 PIN11

JL

1

2

3

4

5

6

7

8

9 10

PIN3 PIN6 PIN10

TDI PIN2 PIN3 GND PIN5 PIN6 TMS PIN8 VCCIO PIN10 PIN11

PIN34 PIN37 PIN39 PIN42 PIN44

JT

1

2

3

4

5

6

7

8

9 10

PIN35 PIN38 PIN40 PIN43

PIN33 PIN30 PIN27 PIN23 PIN21 PIN20 PIN18

PIN44 PIN43 PIN42 VCCINT PIN40 PIN39 PIN38 PIN37 GND PIN35 PIN34

44 43 42 41 40 39 38 37 36 35 34

U1

I/O I/O I/O VCC I/OE2/GCLK2 GCLR OE1 GCLK1 GND GCLK3 I/O

1 2 3 4 5 6 7 8 9 10 11

TDI

I/O

I/O

GND

I/O

I/O TMS

ATMEL TQFP44

I/O

VCC

I/O

I/O

I/O TDO
I/O I/O VCC I/O I/O TCK I/O GND I/O

33 32 31 30 29 28 27 26 25 24 23

PIN33 TDO PIN31 PIN30 VCCIO PIN28 PIN27 TCK PIN25 GND PIN23

I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O

TQFP44

VCCINT GND D1B D1C D1A D1F D1D D1G D1E
TCK D2B D2A D2C D2F D2D D2G D2E GND VCCIO

JP2

1

2

3

4

5

6

7

8

9 10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

35 36

37 38

39 40

GND GND DOT1
LED1
LED2
LED3
TDO LED4

PIN31 PIN28 PIN25 PIN22
PIN19

DOT2 SW1 SW2 SW3 SW4
GND GND

PIN15 PIN14 PIN13 PIN12

PIN33 PIN30 PIN27 PIN23

JR

1

2

3

4

5

6

7

8

9 10

PIN31 PIN28 PIN25

22

21

20

19

18

VCCINT 17

GND 16

15

14

13

12

PIN22

PIN21

PIN20

PIN19

PIN18

PIN15

PIN14

PIN13

PIN12

VCCIO

VCCINT

c1

c2

c3

c4

0.1uF 0.1uF 0.1uF 0.1uF

PIN12 PIN14 PIN18 PIN20 PIN22

JB

1

2

3

4

5

6

7

8

9 10

PIN13 PIN15 PIN19 PIN21

Figure 13. 44-pin PLCC Socket Adapter Board Schematic Diagram

PIN44 PIN1 PIN2 PIN43 PIN6 PIN8 PIN11 PIN14 PIN17

GND GND GOE GCLR GCLK2 GCLK1
SW8 SW7 SW6 SW5 DOT4
LED8 LED7 LED6 LED5
DOT3 GND GND

JP1

1

2

3

4

5

6

7

8

9 10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

35 36

37 38

39 40

VCCINT GND D4G D4E D4F D4D TDI D4A D4C D4B TMS D3G D3E D3F D3D D3A D3C D3B GND VCCIO

PIN40 PIN41 PIN4 PIN5
PIN9 PIN12 PIN16

PIN40 PIN43 PIN1 PIN4 PIN6

JT

1

2

3

4

5

6

7

8

9 10

PIN41 PIN44 PIN2 PIN5

PIN39 PIN36 PIN33 PIN29 PIN27 PIN26 PIN24

VCCINT GND D1B D1C D1A D1F D1D D1G D1E
TCK D2B D2A D2C D2F D2D D2G D2E GND VCCIO

JP2

1

2

3

4

5

6

7

8

9 10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

35 36

37 38

39 40

GND GND DOT1
LED1
LED2
LED3
TDO LED4

PIN37 PIN34 PIN31 PIN28
PIN25

DOT2 SW1 SW2 SW3 SW4
GND GND

PIN21 PIN20 PIN19 PIN18

GND

VCCINT

40 PIN40

41 PIN41

43 PIN43

44 PIN44

1 PIN1

2 PIN2

4 PIN4

5 PIN5

6 PIN6

42

3

PIN8 PIN11 PIN14 PIN17

JL

1

2

3

4

5

6

7

8

9 10

PIN9 PIN12 PIN16

TDI

7

PIN8 8

PIN9 9

GND

10

PIN11 11

PIN12 12

TMS

13

PIN14 14

VCCIO

15

PIN16 16

PIN17 17

I/O I/O I/O VCC I/OE2/GCLK2 GCLR OE1 GCLK1 GND GCLK3 I/O

TDI

I/O

I/O

GND

I/O

I/O TMS

ATMEL PLCC44

I/O

VCC

I/O

I/O

U1

I/O TDO
I/O I/O VCC I/O I/O TCK I/O GND I/O

39 38 37 36 35 34 33 32 31 30 29

PIN39 TDO
PIN37 PIN36
VCCIO PIN34 PIN33
TCK PIN31
GND PIN29

I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O

PLCC44

PIN29 PIN33 PIN36 PIN39

JR

1

2

3

4

5

6

7

8

9 10

PIN31 PIN34 PIN37

PIN18 18 PIN19 19 PIN20 20 PIN21 21 GND 22 VCCINT 23 PIN24 24 PIN25 25 PIN26 26 PIN27 27 PIN28 28

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VCCIO

VCCINT

c1

c2

c3

c4

0.1uF 0.1uF 0.1uF 0.1uF

PIN18 PIN20 PIN24 PIN26 PIN28

JB

1

2

3

4

5

6

7

8

9 10

PIN19 PIN21 PIN25 PIN27

17

Figure 14. 84-pin PLCC Socket Adapter Board Schematic Diagram
18 ATF15xx-DK3-U Development/Programmer Kit [USER GUIDE]
Atmel-8961A-CPLD-ATF15xx-DK3-U-Development-Kit-UserGuide_072015

PIN84 PIN1 PIN2 PIN83
PIN80 PIN4 PIN6 PIN9 PIN11
PIN15 PIN18 PIN24 PIN27
PIN29

GND GND GOE GCLR GCLK2 GCLK1
SW8 SW7 SW6 SW5 DOT4
LED8 LED7 LED6 LED5
DOT3 GND GND

JP1

1

2

3

4

5

6

7

8

9 10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

35 36

37 38

ID3C940 40

PIN12 PIN15 PIN18 PIN24 PIN27 PIN25 PIN29 PIN31

JP4

1

2

3

4

5

6

7

8

9 10

11 12

13 14

15 16

17 18

JPLEFT

VCCINT GND D4G D4E D4F D4D TDI D4A D4C D4B TMS D3G D3E D3F D3D D3A D3C D3B GND VCCIO

PIN75 PIN76 PIN77 PIN79
PIN5 PIN8 PIN10
PIN12 PIN16 PIN17 PIN21 PIN22 PIN25 PIN28

PIN20 PIN16 PIN17 PIN21 PIN22 PIN28 PIN30

PIN12 VCCIO TDI PIN15 PIN16 PIN17 PIN18 GND PIN20 PIN21 PIN22 TMS PIN24 PIN25 VCCIO PIN27 PIN28 PIN29 PIN30 PIN31 GND

PIN11 PIN9 PIN6 PIN4 PIN1 PIN83 PIN80 PIN77 PIN75

JP3

1

2

3

4

5

6

7

8

9 10

11 12

13 14

15 16

17 18

JPTOP

PIN10 PIN8 PIN5 PIN2 PIN84 PIN81 PIN79 PIN76

MARK1 SMALLATMEL

PIN11 PIN10 PIN9 PIN8 GND PIN6 PIN5 PIN4 VCCINT PIN2 PIN1 PIN84 PIN83 GND PIN81 PIN80 PIN79 VCCIO PIN77 PIN76 PIN75

11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75

12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

I/O VCC_IO I/O / TDI I/O I/O I/O I/O GND I/O I/O I/O I/O / TMS I/O I/O VCC_IO I/O I/O I/O I/O I/O GND

I/O I/O I/O I/O GND I/O I/O I/O VCC_INT INPUT/OE2/GCLK2 INPUT/GCLRn INPUT/OE1 INPUT/GCLK1 GND I/O I/O I/O VCC_IO I/O I/O I/O

ATMEL 84PLCC

U1

I/O I/O GND I/O / TDO I/O I/O I/O I/O VCC_IO I/O I/O I/O I/O / TCK I/O I/O GND I/O I/O I/O I/O I/O

74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54

PIN74 PIN73 GND TDO PIN70 PIN69 PIN68 PIN67 VCCIO PIN65 PIN64 PIN63 TCK PIN61 PIN60 GND PIN58 PIN57 PIN56 PIN55 PIN54

PIN74 PIN70 PIN68 PIN65 PIN63 PIN61 PIN58
PIN57 PIN52 PIN55 PIN50 PIN48 PIN45 PIN41

VCCINT GND D1B D1C D1A D1F D1D D1G D1E
TCK D2B D2A D2C D2F D2D D2G D2E GND VCCIO

JP2

1

2

3

4

5

6

7

8

9 10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

35 36

37 38

39 40

IDC40

PIN73 PIN69 PIN67 PIN64 PIN61 PIN58 PIN57 PIN55

JP5

1

2

3

4

5

6

7

8

9 10

11 12

13 14

15 16

17 18

JPBOTTOM

I/O I/O I/O I/O I/O VCC_IO I/O I/O I/O GND VCC_INT I/O I/O I/O GND I/O I/O I/O I/O I/O VCC_IO

VCCIO

C1

C2

C3

C5

C7

C8

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

GND GND DOT1 LED1 LED2 LED3 TDO LED4
DOT2 SW1 SW2 SW3 SW4 GND GND
PIN74 PIN70 PIN68 PIN65 PIN63 PIN60 PIN56 PIN54

PIN73 PIN69 PIN67 PIN64
PIN60
PIN56 PIN54 PIN51 PIN49 PIN44

PIN33 33 PIN34 34 PIN35 35 PIN36 36 PIN37 37 VCCIO 38 PIN39 39 PIN40 40 PIN41 41 GND 42 VCCINT 43 PIN44 44 PIN45 45 PIN46 46 GND 47 PIN48 48 PIN49 49 PIN50 50 PIN51 51 PIN52 52 VCCIO 53

PIN33 PIN35 PIN37 PIN40 PIN44 PIN46 PIN49 PIN51

JP6

1

2

3

4

5

6

7

8

9 10

11 12

13 14

15 16

17 18

JPBOTTOM

PIN34 PIN36 PIN39 PIN41 PIN45 PIN48 PIN50 PIN52

VCCINT

C4

C6

0.1uF 0.1uF

VCCIO

GND

VCCINT

GND

76 PIN76

77 PIN77

78 PIN78

79 PIN79

80 PIN80

81 PIN81

83 PIN83

84 PIN84

85 PIN85

87 PIN87

88 PIN88

89 PIN89

90 PIN90

92 PIN92

93 PIN93

94 PIN94

96 PIN96

97 PIN97

98 PIN98

99 PIN99

100 PIN100

Figure 15. 100-pin TQFP Socket Adapter Board Schematic Diagram

PIN88 PIN89 PIN90 PIN87 PIN99 PIN84 PIN98 PIN96 PIN93
PIN9 PIN10 PIN14 PIN17
PIN20

GND GND GOE GCLR GCLK2 GCLK1
SW8 SW7 SW6 SW5 DOT4
LED8 LED7 LED6 LED5
DOT3 GND GND

JP1

1

2

3

4

5

6

7

8

9 10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

35 36

37 38

39 40

VCCINT GND D4G D4E D4F D4D TDI D4A D4C D4B TMS D3G D3E D3F D3D D3A D3C D3B GND VCCIO

PIN79 PIN76 PIN80 PIN81
PIN100 PIN97 PIN94
PIN92 PIN83 PIN6 PIN8 PIN13 PIN16 PIN19

PIN76 PIN79 PIN84 PIN85 PIN87 PIN89 PIN93 PIN96 PIN98 PIN99

JT

1

2

3

4

5

6

7

8

9 10

11 12

13 14

15 16

17 18

19 20

21 22

HEADER 11X2

PIN78 PIN77 PIN80 PIN81 PIN83 PIN90 PIN88 PIN92 PIN94 PIN97 PIN100

PIN71 PIN69 PIN67 PIN64 PIN61 PIN60 PIN57
PIN54 PIN52 PIN47 PIN40 PIN41 PIN45 PIN46

VCCINT GND D1B D1C D1A D1F D1D D1G D1E
TCK D2B D2A D2C D2F D2D D2G D2E GND VCCIO

JP2

1

2

3

4

5

6

7

8

9 10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

35 36

37 38

39 40

GND GND DOT1
LED1
LED2
LED3
TDO LED4

PIN75 PIN68 PIN65 PIN63
PIN58

DOT2 SW1 SW2 SW3 SW4
GND GND

PIN56 PIN48 PIN36 PIN44 PIN37

82

86

91

95

ATF15xx-DK3-U Development/Programmer Kit [USER GUIDE]

Atmel-8961A-CPLD-ATF15xx-DK3-U-Development-Kit-UserGuide_072015

PIN5 PIN2 PIN9 PIN6 PIN8 PIN13 PIN16 PIN19 PIN10 PIN12

JL

1

2

3

4

5

6

7

8

9 10

11 12

13 14

15 16

17 18

19 20

21 22

HEADER 11X2

PIN1 PIN7 PIN14 PIN17 PIN20 PIN22 PIN23 PIN25 PIN24 PIN21

PIN1 PIN2 VCCIO TDI PIN5 PIN6 PIN7 PIN8 PIN9 PIN10 GND PIN12 PIN13 PIN14 TMS PIN16 PIN17 VCCIO PIN19 PIN20 PIN21 PIN22 PIN23 PIN24 PIN25

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

I/On I/On VCCIO TDI I/On I/O I/On I/O I/O I/O GND I/O I/O I/O TMS I/O I/O VCCIO I/O I/O I/O I/On I/O I/On I/O

VCCIO

C7

C8 C1

C2

C3

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

VCCINT

C11 C12 C5

C6 C9

C10

0.2uF 0.2uF 0.01uF 0.01uF 0.1uF 0.1uF

3 2

PIN39

1

ATMEL TQFP100
VCCINT CON3
J1

GND PIN27 PIN28 PIN29 PIN30 PIN31 PIN32 PIN33
VCCIO PIN35 PIN36 PIN37
GND PIN39
PIN40 PIN41 PIN42 GND PIN44 PIN45 PIN46 PIN47 PIN48 PIN49 PIN50

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

GND I/On I/On I/O I/O I/O I/O I/O VCCIO I/O I/O I/O GND VCCINT I/O I/O I/O GND I/O I/O I/O I/O I/O I/On I/On

I/O I/O I/O I/O I/O GND I/O I/O I/O VCCINT GCLK2 GCLR OE1 GCLK1 GND I/O GCLK3 I/O I/O VCCIO I/O I/O I/On I/O I/On I/O

U1

I/O GND TDO I/On
I/O I/On I/O I/O I/O VCCIO I/O I/O I/O TCK I/O I/O GND I/O I/O I/O I/On I/O I/On I/O VCCIO

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

PIN75 GND TDO
PIN72 PIN71 PIN70 PIN69 PIN68 PIN67
VCCIO PIN65 PIN64 PIN63
TCK PIN61 PIN60
GND PIN58 PIN57 PIN56 PIN55 PIN54 PIN53 PIN52 VCCIO

TQFP100

PIN53 PIN55 PIN57 PIN60 PIN63 PIN65 PIN68 PIN71 PIN72

JR

21 22

19 20

17 18

15 16

13 14

11 12

9 10

7

8

5

6

3

4

1

2

HEADER 11X2

PIN52 PIN56 PIN54 PIN58 PIN61 PIN64 PIN67 PIN69 PIN70 PIN75

PIN31 PIN27 PIN30 PIN33 PIN36 PIN40 PIN42 PIN45 PIN48 PIN46

JB

1

2

3

4

5

6

7

8

9 10

11 12

13 14

15 16

17 18

19 20

21 22

HEADER 11X2

PIN28 PIN29 PIN32 PIN35 PIN37 PIN41 PIN44 PIN47 PIN50 PIN49

19

References and Support

For additional PLD design software references and support, documentation such as help files, tutorials, application notes/briefs, and user guides are available at www.atmel.com.

Atmel ProChip Designer Software

Table 8. ProChip Designer References and Support

ProChip Designer Help Tutorials Known Problems and Solutions Website

From the main ProChip window menu... Select Help > Prochip Designer Help. Select Help > Tutorials. Select Help > Review KPS. www.atmel.com/tools/PROCHIPDESIGNERV5_0.aspx

Atmel WinCUPL Software

Table 9. WinCUPL References and Support

WinCUPL Help CUPL Programmers Reference Guide Tutorials Known Problems and Solutions Website

From the main WinCUPL window menu... Select Help > Contents. Select Help > CUPL Programmers Reference. Select Help > Atmel Info > Tutorial1.pdf. Select Help > Atmel Info > CUPL_BUG.pdf. www.atmel.com/tools/WINCUPL.aspx

Atmel ATMISP Software

Table 10. ATMISP References and Support

ATMISP Help Files Tutorials Known Problems and Solutions Website

From the main ATMISP window menu... Select Help > ATMISP Help. Select Help > Quick Start Tutorial. Using the Windows Explorer browser, locate the ATMISP folder and open the readme.txt file with an ASCII text editor. www.atmel.com/tools/ATMISP.aspx

Atmel POF2JED Conversion Software

Table 11. POF2JED References and Support

POF2JED

From the main POF2JED window menu...

ATF15xx Conversion Application Brief Select Help > Conversion Options.

20 ATF15xx-DK3-U Development/Programmer Kit [USER GUIDE]
Atmel-8961A-CPLD-ATF15xx-DK3-U-Development-Kit-UserGuide_072015

Technical Support

For technical support on any Atmel PLD related issues, contact the Atmel PLD Applications Group at:

Email

pld@atmel.com

Hotline

(+1)(408) 436-4333

Online Support Form www.atmel.com/design-support/

Revision History

Revision 8961A

Date 07/2015

Description Initial document release.

ATF15xx-DK3-U Development/Programmer Kit [USER GUIDE]

21

Atmel-8961A-CPLD-ATF15xx-DK3-U-Development-Kit-UserGuide_072015

XXXXXX

Atmel Corporation

1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311

F: (+1)(408) 436.4200

| www.atmel.com

© 2015 Atmel Corporation. / Rev.: Atmel-8961A-CPLD-ATF15xx-DK3-U-Development-Kit-UserGuide_072015.
Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Windows® is a registered trademark of Microsoft Corporation in U.S. and or other countries. Other terms and product names may be trademarks of others.

DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in connection with any applications where the failure of such products would reasonably be expected to result in significant personal injury or death ("Safety-Critical Applications") without an Atmel officer's specific written consent. Safety-Critical Applications include, without limitation, life support devices and systems, equipment or systems for the operation of nuclear facilities and weapons systems. Atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by Atmel as military-grade. Atmel products are not designed nor intended for use in automotive applications unless specifically designated by Atmel as automotive-grade.



References

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