RZ/T2H and RZ/N2H Groups PCB Design Guide for LPDDR4

Overview

This guide outlines PCB design methods that align with verification requirements specified in the "RZ/T2H and RZ/N2H Groups PCB verification guide for LPDDR4" (R01AN7260EJ****). Renesas offers a fully verified LPDDR4 reference design, whose PCB structure and topologies are referenced herein. While the reference design's PCB layout can be copied, all verification items from the guide must still be confirmed through SI and PDN simulations.

The following documents are relevant to these LSI. Always refer to the latest versions. Document numbers ending in '****' indicate version information. Latest versions are available on the Renesas Electronics website.

Reference Documents

Notice and General Precautions

Notice: Renesas Electronics disclaims liability for losses or damages arising from the use of information or circuits provided, patent/copyright infringements, or unauthorized modification/reverse engineering of products. Products are classified into "Standard" and "High Quality" grades for specific applications. Renesas products are not authorized for use in systems that pose a direct threat to human life or cause serious property damage unless explicitly designated for such use. Users are responsible for ensuring product safety, compliance with laws and regulations (e.g., RoHS), and obtaining necessary third-party licenses.

General Precautions for Microprocessing Unit and Microcontroller Unit Products:

• Electrostatic Discharge (ESD): Take measures to prevent static electricity generation and dissipation. Use anti-static containers, grounding straps, and avoid touching devices with bare hands.
• Power-on Processing: Device states are indeterminate upon power supply until reset is complete. Ensure proper reset signal application.
• Input during Power-off: Do not input signals or power to devices that are powered off to prevent malfunction or degradation.
• Unused Pins: Handle unused pins according to manual guidelines to prevent noise induction and false signal recognition.
• Clock Signals: Ensure clock signals stabilize after reset before releasing the reset line. Stabilize clock signals before switching during program execution.
• Voltage Application Waveform: Prevent waveform distortion and chattering noise at input pins to avoid malfunctions.
• Reserved Addresses: Access to reserved addresses is prohibited as operation is not guaranteed.
• Product Differences: Verify system compatibility when changing to products with different part numbers, as electrical characteristics may vary.

Basic Information

PCB Structure

This guide focuses on an 8-layer board with through-hole vias. The layer assignments, signal/power (GND) distribution, and thickness for each layer are detailed below.

Diagram: PCB Structure

The 8-layer stack-up includes:

• L1: Cu 0.042mm (Signal / VDD / GND)
• L2: Cu 0.035mm (GND)
• L3: Cu 0.035mm (Signal)
• L4: Cu 0.035mm (None)
• L5: Cu 0.035mm (None)
• L6: Cu 0.035mm (VDD)
• L7: Cu 0.035mm (GND)
• L8: Cu 0.042mm (Signal / VDD / GND)

Additional layers include Solder Resist (S.R) at 0.03mm and Prepreg (P.P) at 0.08mm and 0.21mm. The total thickness is 1.2344mm. The base material is FR-4. Dielectric properties (relative permittivity / loss tangent) are provided for Solder Resist and Prepreg layers at 1GHz.

Design Rules

Key design specifications include:

• VIA Specifications:
• VIA Diameter: 0.25mm
• Surface Land Diameter: 0.5mm
• Internal Layer Land Diameter: 0.5mm
• Internal Layer Clearance Diameter: 0.7mm
• VIA Center - VIA Center (LSI): 0.8mm
• VIA Land - VIA Land (LSI): 0.3mm
• VIA Center - VIA Center (DRAM): 0.65mm
• VIA Land - VIA Land (DRAM): 0.15mm
• Minimum Trace Width: 0.1mm
• Minimum Space:
• Wiring - Wiring: 0.1mm
• Wiring - VIA: 0.1mm
• Wiring - BGA land: 0.1mm
• VIA - BGA land: 0.1mm
• Wiring - BGA resist: 0.05mm

Diagram: VIA Specifications: Illustrates VIA dimensions, land diameters, and clearance.

Diagram: BGA land diameter (PAD dimension): Shows BGA land and S.R. aperture dimensions for LSI (0.4mm land, 0.5mm aperture) and DRAM (0.3mm land, 0.4mm aperture), along with trace clearances.

Net Swap

Some external pins are swappable without requiring register settings, managed by the DDR parameter generation tool (gen_tool). Detailed information on external pin swizzling can be found in the "RZ/T2H and RZ/N2H Groups User's Manual: Hardware, 57.4.1 External Pin Swizzling" (R01UH1039EJ****).

Example of Swizzling for RZ/T2H

The following tables show examples of pin swizzling supported by the reference design PCB layout data for RZ/T2H.

Table 3.1: Example of Swizzling for RZ/T2H (1 of 3)

Table 3.1: Example of Swizzling for RZ/T2H (2 of 3)

Table 3.1: Example of Swizzling for RZ/T2H (3 of 3)

Common Guidelines

Component Placement

Diagram: Component placement assumptions: This diagram illustrates placement assumptions for a 2-RANK configuration, showing the LSI (U1) and DRAM (M1) placed on Layer 1 (L1). Lines indicate different signal types: Clock signals, DQ Strobe signals, DATA signals, Command & Address signals, Control signals, and Reset signal connecting the LSI and DRAM.

IO Power Supply Layout Guideline

The IO power supply (DDR_VDDQ) should be implemented as a plane on Layer 6 (L6), sufficiently large to cover all signal traces and DRAM. For optimal layout, place one VIA for every one or two PADs of the IO power supply near the LSI. Capacitors should be placed per number of VIAs. Use GND PADs near DDR_VDDQ and place VIAs for GND following the same rule. To minimize current return path inductance, capacitors should be placed with the shortest possible traces to the IO power supply and GND. Layout verification should include PDN analysis to ensure compliance with specifications.

Diagram: IO Power supply layout near the LSI: This schematic shows the arrangement of PADs, VIAs, Signal traces, GND connections, and DDR_VDDQ connections. It suggests placing capacitors (Cap) close to the DDR_VDDQ and GND connections.

Topology

For detailed skew information between wires for each signal, refer to "RZ/T2H and RZ/N2H Groups PCB verification guide for LPDDR4, 4.1.1 Skew restrictions" (R01AN7260EJ****). The PCB configuration of the reference design is presented below.

System Configuration:

• System RANK: Dual
• LPDDR4 SDRAM: 64GB
• Target Device: MT53E2G32D4DE-046 AIT:C (Z42N QDP)
• PCB: 8layers / One to One / Top mounting

Diagram: PCB configuration: A block diagram illustrating the connection between LPDDR4 and RZ/T2H, showing signal groups (DQ/DQS, CA/CS/CKE, CLK) and the Quad Die.

The following tables detail recommended IO settings, based on a 2-RANK DRAM model from the reference design.

Table 5.1: Recommended IO Setting

5.1.1 CLK Topology

Diagram: CLK topology: Illustrates the CLK signal path from LSI to DRAM on Layer 1 (L1). It shows trace lengths (a0, a0#) and specifies an odd mode impedance (Zodd) of 40Ω ±10%. Key design points include ensuring equal length for CLK pairs (a0=a0#) and maintaining at least 0.25mm spacing from other signal traces. SI simulation is mandatory.

5.1.2 CA Topology

Diagram: CA topology: Depicts the Address and Command (CA) signal paths from LSI to DRAM across layers L1, L3, and L8. Signals are single-ended with an impedance (Z0) of 50Ω ±10%. Trace lengths are indicated (a0 to c2). Design requires equal length for related signals and adherence to specified impedance. SI simulation is mandatory.

5.1.3 CTRL Topology

Diagram: CTRL topology: Shows the Control signal paths from LSI to DRAM across layers L1, L3, and L8. These signals are single-ended with an impedance (Z0) of 50Ω ±10%. Trace lengths are denoted (a0 to c3). Design considerations include equal trace lengths for pairs and proper spacing. SI simulation is mandatory.

5.1.4 RESET Topology

Diagram: RESET topology: Illustrates the RESET signal path from LSI to DRAM across layers L1 and L3. The signal is single-ended with an impedance (Z0) of 50Ω ±10%. Trace lengths are indicated (a0 to a2). Adherence to the specified topology and SI simulation is required.

5.1.5 DQS/DQ Topology

Diagram: DQS topology: Depicts the DQS/DQS# signal paths from LSI to DRAM across layers L1, L8. These differential traces require an impedance (Zodd) of 40Ω ±10%. Design requires equal length for DQS pairs (a0=a0#) and a minimum spacing of 0.25mm. SI simulation is mandatory.

Diagram: DQ topology: Illustrates the DQ and DM signal paths from LSI to DRAM across layers L1, L3, L8. These single-ended signals require an impedance (Z0) of 45Ω ±10%. Design considerations include proper trace lengths and spacing. SI simulation is mandatory.

Handling of Other Pins

Specific handling instructions for certain pins:

• DDR_ZN: A 120Ω (±1%) external resistor must be connected between DDR_ZN and VSS (GND).
• DDR_DTEST, DDR_ATEST: Keep these pins open.

Revision History

Colophon

Publication Date: Rev.0.70 Mar 26, 2024; Rev.1.00 Sep 30, 2024

Published by: Renesas Electronics Corporation