Product Document
Published by ams OSRAM Group
Application Note
AN001050
TMD3719 Flicker Detection
Built-in Flicker Function
v1-00 · 2022-Aug-04
Content Guide
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TMD3719 Flicker Detection Content Guide
1
Introduction ................................... 3 4
1.1
Flicker Detection Registers .......................... 3 5
2
Flicker Detection Modes ............. 13
2.1
On-Chip Mode ............................................ 13
2.2
Data Sampling Mode .................................. 15
3
Summary / Results ...................... 17
Revision Information ................... 18 Legal Information......................... 19
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TMD3719 Flicker Detection Introduction
1 Introduction
The TMD3719 features ambient light and color (RGB) sensing, proximity and flicker detection.
The device integrates direct detection of ambient light flicker for 4 selectable frequency bins. There are two flicker detection modes; On-chip mode and data sampling mode. During the data sampling mode, the flicker detection engine can buffer data in a FIFO for calculating other flicker frequencies externally.
In this document, the registers necessary to configure and the usage of both modes will be discussed.
1.1
Flicker Detection Registers
The TMD3719 registers necessary to make the flicker function work are summarized in this section. These registers can also be found in the datasheet.
The values of all registers and fields that are listed as reserved or are not listed, must not be changed at any time.
1.1.1
FD_CFG0 Register (Address 0x40)
Figure 1: FD_CFG0
Addr: 0x40
Bit
Field
7:5
Reserved
4:3
FD_SAMPLES
2
Reserved
1:0
FD_TIME
FD_CFG0
Reset 000
Type
00
R/W
0
00
R/W
Bit Description
Flicker Detection Number of Samples
VALUE
SAMPLES
0 (default)
128
1
256
2
512
3
1024(1)
Flicker Detection Time VALUE 0
1 (default)
TIME 50 ms 100 ms
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TMD3719 Flicker Detection Introduction
Addr: 0x40
FD_CFG0
Bit
Field
Reset
Type
Bit Description 2
3
200 ms
User Defined by FD_SAMPLE_TIME and
FD_SAMPLES
(1) If FD_MODE = 1 (register 0x82 [6]) then the number of samples changes from 1024 to unlimited.
1.1.2
FD_CFG5 Register (Address 0x45)
Figure 2: FD_CFG5 Register
Addr: 0x45
Bit
Bit Name
FD_CFG5 Default
7:0
FD_CHANNEL_DISABLE(1) 0xFE
Access Bit Description
Flicker Detection Channel
R/W
Disable. Selects which channels to be used for
flicker detection.
(1) Select which modulator channels should be connected/used by the on_chip flicker engine. Note that the bitstreams are added before the engine evaluates the data. The register bits are one hot encoded where bit 0 means modulator 0, and so on.
1.1.3
FD_CFG7 Register (Address 0x47)
Figure 3: FD_CFG7 Register
Addr: 0x47
Bit
Bit Name
7:2
Reserved
FD_CFG7 Default 000000
1:0
FD_SAMPLE_TIME_H
01
Access Bit Description
Flicker Detection Sample
Time High. These bits are
R/W
the high byte of the 10 bits
used for setting the flicker
detection integration time.
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TMD3719 Flicker Detection Introduction
1.1.4
FD_CFG7 Register (Address 0x48)
Figure 4: FD_CFG8 Register
Addr: 0x48
Bit
Bit Name
7:2
Reserved
FD_CFG8 Default 000000
1:0
FD_SAMPLE_TIME_L
01
Access Bit Description
Flicker Detection Sample
Time Low. This register is
R/W
the low byte of the 10 bits
used for setting the flicker
detection integration time.
1.1.5
ENABLE Register (Address 0x80)
Figure 5: ENABLE Register
Addr: 0x80 Bit Bit Name 7 Reserved 6 FDEN 5 Reserved 4 AEN 3 PEN 2:1 Reserved
0 PON
ENABLE Default 0 0 0 0 0 00
0
Access R/W R/W R/W
R/W
Bit Description
Flicker Detection Enable. Writing a 1 activates flicker detection. Writing a 0 disables flicker detection.
ALS Enable. Writing a 1 enables ALS/Color. Writing a 0 disables ALS/Color. Proximity Enable. Writing a 1 enables proximity. Writing a 0 disables proximity.
Power ON. When asserted, the internal oscillator is activated, allowing timers and ADC channels to operate. Writing a 0 disables the oscillator and clears PEN and AEN. Only set this bit after all other registers have been initialized by the host.
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1.1.6
MEAS_MODE1 Register (Address 0x82)
Figure 6: MEAS_MODE1 Register
Addr: 0x82
Bit
Bit Name
7
Reserved
6
FD_MODE
5:3
Reserved
2:0
FIFO_MODE
MEAS_MODE1
Default 0
Access
0
R/W
000
R/W
0
R/W
Bit Description
Flicker Detection Mode. Writing a 0 will set the FD to onchip mode and writing a 1 will set the FD to data sampling mode.
FIFO Mode VALUE 0 1 2 3 4 5 7
MODE Off
32-bit 16-bit ALS 16-bit FD
8-bit FD Reserved
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TMD3719 Flicker Detection Introduction
1.1.7
MOD_GAIN_0_1 Register (Address 0x89)
Figure 7: MOD_GAIN_0_1 Register
Addr: 0x89
Bit
Bit Name
7:4
MOD_GAIN1
3:0
MOD_GAIN0
MOD_GAIN_0_1
Default 0000
0000
Access Bit Description
Modulator One Gain
VALUE
GAIN
0
2x
1
4x
2
8x
3
16x
4
32x
R/W
5
64x
6
128x
7
256x
8
512x
9
1024x
10
2048x
11
4096x
12 15
Reserved
Modulator Zero Gain
VALUE
GAIN
0
2x
1
4x
2
8x
3
16x
4
32x
R/W
5
64x
6
128x
7
256x
8
512x
9
1024x
10
2048x
11
4096x
12 15
Reserved
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1.1.8
MOD_GAIN_2_3 Register (Address 0x8A)
Figure 8: MOD_GAIN_2_3 Register
Addr: 0x8A
Bit
Bit Name
7:4
MOD_GAIN3
3:0
MOD_GAIN2
MOD_GAIN_2_3
Default 0000
0000
Access Bit Description
Modulator Three Gain
VALUE
GAIN
0
2x
1
4x
2
8x
3
16x
4
32x
R/W
5
64x
6
128x
7
256x
8
512x
9
1024x
10
2048x
11
4096x
12 15
Reserved
Modulator Two Gain
VALUE
GAIN
0
2x
1
4x
2
8x
3
16x
4
32x
R/W
5
64x
6
128x
7
256x
8
512x
9
1024x
10
2048x
11
4096x
12 15
Reserved
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1.1.9
MOD_GAIN_4_5 Register (Address 0x8B)
Figure 9: MOD_GAIN_4_5 Register
Addr: 0x8B
Bit
Bit Name
7:4
MOD_GAIN5
3:0
MOD_GAIN4
MOD_GAIN_4_5
Default 0000
0000
Access Bit Description
Modulator Five Gain
VALUE
GAIN
0
2x
1
4x
2
8x
3
16x
4
32x
R/W
5
64x
6
128x
7
256x
8
512x
9
1024x
10
2048x
11
4096x
12 15
Reserved
Modulator Four Gain
VALUE
GAIN
0
2x
1
4x
2
8x
3
16x
4
32x
R/W
5
64x
6
128x
7
256x
8
512x
9
1024x
10
2048x
11
4096x
12 15
Reserved
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1.1.10
MOD_GAIN_6_7 Register (Address 0x8C)
Figure 10: MOD_GAIN_6_7 Register
Addr: 0x8C
Bit
Bit Name
7:4
MOD_GAIN7
3:0
MOD_GAIN6
MOD_GAIN_6_7
Default 0000
0000
Access Bit Description
Modulator Seven Gain
VALUE
GAIN
0
2x
1
4x
2
8x
3
16x
4
32x
R/W
5
64x
6
128x
7
256x
8
512x
9
1024x
10
2048x
11
4096x
12 15
Reserved
Modulator Six Gain
VALUE
GAIN
0
2x
1
4x
2
8x
3
16x
4
32x
R/W
5
64x
6
128x
7
256x
8
512x
9
1024x
10
2048x
11
4096x
12 15
Reserved
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TMD3719 Flicker Detection Introduction
1.1.11
CONTROL Register (Address 0xF6)
Figure 11: CONTROL Register
Addr: 0xF6 Bit Bit Name 7:3 Reserved 2 ALS_MANUAL_AZ
1 FIFO_CLR 0 CLEAR_SAI_ACTIVE
CONTROL
Default 00000 0
0 0
Access Bit Description
ALS Manual Autozero. Starts a
R/W
manual autozero of the ALS engines. Set AEN = 0 before starting a manual
autozero for it to work.
R/W
FIFO Buffer Clear. Clears all FIFO data, FINT, FIFO_OV, and FIFO_LVL.
Clear Sleep-After-Interrupt Active.
R/W
Clears SAI_ACTIVE, ends sleep, and
restarts device operation.
1.1.12
FIFO_MAP2 Register (Address 0xFA)
Figure 12: FIFO_MAP2 Register
Addr: 0xFA
FIFO_MAP2
Bit Bit Name 7:5 Reserved
Default 000
4 FIFO_WRITE_FD_RESULTS 0
3 FIFO_WRITE_FD_DATA
0
2 FIFO_WRITE_PDATAR
0
1 FIFO_WRITE_PDATA1
0
0 FIFO_WRITE_PDATA0
0
Access Bit Description
FIFO Write Flicker Detection Result.
R/W
If asserted, flicker detection on-chip calculation result is written to the
FIFO buffer.
FIFO Write Flicker Detection Data. If
R/W
asserted, flicker detection data is
written to the FIFO buffer.
FIFO Write Proximity Ratio Data. If
R/W
asserted, proximity ratio data is
written to the FIFO buffer.
FIFO Write Proximity One Data. If
R/W
asserted, proximity one data is written
to the FIFO buffer.
FIFO Write Proximity Zero Data. If
R/W
asserted, proximity zero data is
written to the FIFO buffer.
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1.1.13
FIFO_STATUS Register (Address 0xFB)
Figure 13: FIFO_STATUS Register
Addr: 0xFB Bit Bit Name 7 FIFO_OV
6:0 FIFO_LVL
FIFO_STATUS
Default 0 0000000
Access R R
Bit Description
FIFO Buffer Overflow. Indicates that the FIFO buffer overflowed and information has been lost. Bit is automatically cleared when the FIFO is read.
FIFO Buffer Level. Indicates the number of entries (each are 4 bytes) available in the FIFO buffer waiting for readout. The FIFO level can be between 0 (empty) and 64 (full).
1.1.14
FIFO Buffer Data Register (Address 0xFC 0xFF)
Figure 14: FIFO Buffer Data Register
Addr
0xFC 0xFD 0xFE 0xFF
Name Type FDATA R
Description FIFO buffer data
7 6 5 4 3 2 1 0 Reset
00000000 00000000 00000000 00000000
0x00 0x00 0x00 0x00
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TMD3719 Flicker Detection Flicker Detection Modes
2 Flicker Detection Modes
2.1
On-Chip Mode
Flicker function can be activated by the flicker enable bit in register 0x80 bit 6 (MEAS_MODE1.FDEN). Writing a 1 activates flicker detection. Writing a 0 disables flicker detection.
The time to measure for flicker is set by using register FD_CFG0.FD_TIME (0x40 bits [1:0]). The sampling time can be set to 50/100/200 milliseconds for a frequency bin resolution of 20/10/5 Hz, respectively. Also, a user defined FD_TIME can be defined by FD_SAMPLE_TIME in registers FD_CFG7 (0x47 bits [7:0]) and FD_CFG8 (0x48 [1:0]) in combination with FD_SAMPLES of register FD_CFG0 (0x40 bits [4:3]).
When setting register FD_CFG0.FD_TIME (0x40 bits [1:0]) to one of the preset sampling times, registers FD_CFG7 (0x47) and FD_CFG8 (0x48) are set with a preset value for sample time. These preset values are shown in Figure 15.
Registers FD_CFG7 (0x47) and FD_CFG8 (0x48) combine to make a 10-bit value.
Figure 15: Flicker Sampling Time Configurations
Value
0 1 2 3
FD_TIME(3) 0x40 bits [1:0]
50 ms(1) 100 ms(1) 200 ms(1) User defined
FD_SAMPLES 0x40 bits [4:3]
128 128 128 1024(2)
FD_SAMPLE_TIME 0x47 & 0x48
143 287 575 User Defined
(1) When selecting 50 ms/100 ms/200 ms, register FD_SAMPLES gets overwritten with 128. (2) Unlimited, if FD_MODE = 1, FIFO_WRITE_FD_DATA = 1, and FIFO_MODE > 0 else 1024. (3) FD_TIME = FD_SAMPLES * (FD_SAMPLE_TIME + 1) * modclk; modclk = 2.71 µs.
For example: FD_CFG0 (0x40) = 0x01(default) - This selects FD_TIME as 100 ms. Therefore, FD_SAMPLES = 128 and FD_SAMPLE_TIME = 287.
The on-chip flicker function uses the Goertzel Algorithm embedded in the device.
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Figure 16: TMD3719 GUI
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TMD3719 Flicker Detection Flicker Detection Modes
Figure 17: Explanation of Fields in the Above GUI Image
Index 1
2 3 4 7 8
Description
Time to measure flicker
Number of samples to be measured for flicker
Integration time for flicker
Coefficients input to algorithm to decode bin distances Results from the algorithm
Register(s) [bits]
Comments
0x40 [1:0]
0x40 [4:3] 0x47 [1:0], 0x48 [7:0] 0x41[4:0], 0x42[4:0], 0x43[4:0], 0x44[4:0]
200 ms, 100 ms (Default), 50 ms, user defined(1)
128 (Default), 256, 512, 1024 (Unlimited(2))
Must not be changed with FDEN = 1 and PON = 1
Inputs to the on-chip algorithm. 200 ms: 5 Hz to 160 Hz, 5 Hz steps 100 ms: 10 Hz to 320 Hz, 10 Hz steps 50 ms: 20 Hz to 640 Hz, 20 Hz steps
(1) Can be used to select different combinations using number of samples (0x40 [4:3]) and sample time (0x47, 0x48). (2) If fd_mode = 1, fifo_write_fd_data = 1, and fifo_mode > 0 else 1024.
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TMD3719 Flicker Detection Flicker Detection Modes
2.2
Data Sampling Mode
This section gives guidance on configuring flicker for 16-bit sampling mode and accessing flicker detection data from the FIFO.
This section shows an example of a specific flicker configuration. Adjustment to the configuration could be made for a different application.
FIFO access can be read out with single reads starting at FDATA0 (0xFC). 4 consecutive I2C addresses have to be read to get a full data set.
Upon reading FDATA3 (0xFF), then reading FDATA0 again (I2C address wrap around) it automatically decreases the FIFO_STATUS.FIFO_LVL (0xFB).
If reading beyond the end of the FIFO, data will return 0x00. There is no under-run flag, this is not as error condition.
2.2.1
Configuring Flicker Detection:
1. Configure ENABLE (0x80) = 0x01 (Enable PON). 2. Configure FD_CFG0 (0x40) = 0x02 (FD_TIME = 200 ms, FD_SAMPLES = 128). 3. Configure MOD_GAIN
MOD_GAIN_0_1 (0x89) = 0x02 (8x) MOD_GAIN_2_3 (0x8A) = 0x02 (8x) MOD_GAIN_4_5 (0x8B) = 0x02 (8x) MOD_GAIN_6_7 (0x8C) = 0x02 (8x) 4. Configure FD_CFG5 (0x45) = 0x00 (All flicker channels active). 5. Configure MEAS_MODE1 (0x82) = 0x43 - (FD_MODE = sampling mode, FIFO_MODE = 16 bits).
6. Configure FIFO_MAP2 (0xFA) = 0x08 (Write data to FIFO).
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TMD3719 Flicker Detection Flicker Detection Modes
2.2.2
Clearing the FIFO:
1. Read ENABLE register (0x80) contents and save it to a variable `A'. 2. Set ENABLE register (0x80) to 0x1, only PON is enabled. 3. Read CONTROL register (0xF6) and save it to a variable `B'. 4. Set variable `B' bit 1 (FIFO_CLR) to 1, leave other bits same. 5. Write `B' back to CONTROL register (0xF6). 6. Write variable `A' to ENABLE register (0x80) to recover the original state. 7. Configure ENABLE (0x80) = 0x41 (PON = 1, FDEN=1).
2.2.3
Polling Flicker Data
1. Read FIFO_STATUS (0xFB). 2. Check FIFO_OV (0xFB [7]) FIFO buffer overflow, if flag is set information has been lost. 3. Check FIFO_LVL (0xFB [6:0]) FIFO level, indicates number of entries available. 4. If FIFO_OV = 1 then; 5. Clear FIFO. 6. Delay 50 ms. 7. If FIFO_LVL is not 0 then; 8. Poll FIFO buffer data FDATA (0xFC, 0xFD, 0xFE, 0xFF).
Polling of the FIFO should be done such that the FIFO does not overflow. FIFO capacity is 256 bytes, the highest FIFO level is 256/4 = 64.
If 200 ms is selected for FD_TIME, FD_SAMPLES would be equal to 128 and while sampling the FIFO at 200 ms. The FIFO would more than likely overflow creating loss of data since 128 samples (256 bytes) is the full depth of the FIFO.
If the FIFO sampling frequency was reduced to 100 ms, the number of samples would be 64 (128 bytes), which is only half of the FIFO size then you will not have FIFO overflow. Therefore, to calculate the appropriate sample time, determine what will fill half of the FIFO or at most 2/3 of the FIFO and use that time as the sampling period.
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TMD3719 Flicker Detection Summary / Results
3 Summary / Results
There are two modes for configuring the flicker function in this device, on-chip and data sampling. Onchip flicker detection uses an embedded algorithm and data sampling uses FIFO to access data.
ams OSRAM provides a robust flicker detection functionality in many devices, the primary application for the flicker detection function would be flicker-immune camera operation. These efforts can make it easier to minimize flicker-induced problems.
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4 Revision Information
TMD3719 Flicker Detection Revision Information
Changes from previous version to current revision v1-00 Initial production version
Page
Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
Correction of typographical errors is not explicitly mentioned.
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TMD3719 Flicker Detection Legal Information
5 Legal Information
Copyrights & Disclaimer
Copyright ams-OSRAM AG, Tobelbader Strasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.
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