MCX A13, A14x, MCX A15x Arm Cortex -M33-Based Microcontrollers | NXP Semiconductors
27 нояб. 2024 г. — Features. • Arm Cortex-M33 48MHz(A14x) or 96MHz(A15x) with 396 CoreMark. (4.12 CoreMark/MHz). • Up to 1MB Flash, 128KB SRAM, up to 8 KB SRAM with ECC.
MCXA156, A155, A154, A146, A145, A144 Data Sheet Arm® Cortex®-M33 48MHz or 96MHz 32-bit MCU, up to 1MB Flash Rev. 5 -- July 2024 Data Sheet: Technical Data MCXA14x MCXA15x Features · Arm Cortex-M33 48MHz(A14x) or 96MHz(A15x) with 396 CoreMark (4.12 CoreMark/MHz) · Up to 1MB Flash, 128KB SRAM, up to 8 KB SRAM with ECC · All RAM can be retained down to Deep Power Down mode · -40 °C to 125 °C temperature range · Down to 64 A/MHz Active current, 32.26 A Deep Sleep current, 8.2 A Power Down current, 412 nA Deep Power Down current LQFP100 14 x 14 x 1.4 mm, 0.5mm LFBGA64 5 x 5 x 1.2 mm,0.5mm VFBGA112 7 x 7x 0.86mm, 0.5mm Core · Arm 32-bit Cortex-M33 CPU, with FPU and DSP extension instruction set, no TrustZone, no MPU Memories · Single-bank Flash: Up to 1024 KB Flash with ECC (support one bit correction and two bits detection) · Cache Engine with 4 KB RAM · Up to 128 KB RAM, configurable as up to 8KB RAM with ECC (support one bit correction and two bits detection) · All RAM can be retained down to Deep Power Down mode · 16 KB ROM Security · 128-bit Universal Unique Identifier (UUID) per device in accordance with IETF's RFC4122 version5 specification · Device lifecycle management · Flash read/write/execute permission protect by MBC and lockable · Implicit-protected Flash Region (IFR) · Security Monitoring: -- Code Watchdog for code flow integrity checking -- GLIKEY enhances protection against attacks to gain unauthorized access to sensitive registers Low-Power Performance · Active -- 64 A/MHz in Active Mode (executing while(1) from flash, 3.3 V@25 °C) · Deep Sleep -- 32.26 A, 7.1 s wake-up (3.3 V@25 °C) · Power Down -- 8.2 A, 16.6 s wake-up (RAM X0/X1 and RAM A0 retained, 3.3 V@25 °C) NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. NXP Semiconductors Deep Power Down -- 412 nA, 1.44 ms wake-up (wake timer disabled, reset pin enabled, all SRAM off, 3.3 V@25 °C) System and Clocks · 192 MHz free-running oscillator (FRO192M) · 12 MHz free-running oscillator (FRO12M) · 16 KHz free-running oscillator (FRO16K) · Up to 50 MHz crystal oscillator · Hardware and Software Watchdogs · Asynchronous DMA modules (8-channels) Communication Interfaces for Connectivity · 4x LPI2C, 2x LPSPI, 5x LPUART · 1x I3C · USB Full-speed (Device) with on-chip FS PHY · 1x FlexCAN with FD · FlexIO Advanced Motor Control · Up to 2x FlexPWM each with 3 sub-modules, providing 12 complementary outputs of PWM (no Nanoedge module) · Up to 2x Quadrature Decoder (eQDC) · 2x AOI (AND/OR/Invert) module support up to 4 output trigger Analog · 2x 16-bit ADC -- Up to 3.2 Msps in 16-bit mode, and 4 Msps in 12-bit -- Up to 32 ADC Input channels (depending on the package) -- One integrated temperature sensor per ADC · 1x 12-bit DAC · Two Low power Comparators (LPCMP) with 8 input pins and 8-bit DAC as internal reference -- 1x LPCMP is functional down to Deep Power Down mode · 1x OpAmp with PGA Timers · Five 32-bit standard general-purpose asynchronous timers/counters, which support up to four capture inputs and four compare outputs, PWM mode, and external count input. Specific timer events can be selected to generate DMA requests. · Low power timer · Frequency measurement timer · Windowed watchdog timer · Wake timer · Micro-tick timer (UTICK) · OS event timer General-purpose input/output Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 2 / 88 NXP Semiconductors · Up to 82 GPIOs · Up to eight 20 mA IO · 50 MHz IO on P1, P3 and P4 · Up to 19-pin wake-up sources function down to Deep Power Down mode · Support 1.71 V~3.6 V IO supply range · Support 1.2V independent IO supply on P3 port Power Management · Integrated voltage regulator -- Core LDO, other LDOs · Operating range: 1.71 V to 3.6 V · IOs: 1.71 V-3.6 V full-performance Target Applications Industrial · Energy Storage and Management System · Smart Metering · Factory Automation · Industrial HMI · Mobile Robotics Ecosystem · Motion Control and Robotics · Motor Drives · Brushless DC Motor (BLDC) Control · Permanent Magnet Synchronous Motor (PMSM) Smart Home · Home Control Panel · Major Home Appliances · Robotic Appliance · Smart Speaker · Soundbar · Gaming Accessories · Smart Lighting · Smart Power Socket and Light Switch Table 1. Ordering Information Part Number Marking Core Flash (KB) Speed (MHz) SRAM (KB) GPIOs MCXA144VLL MCXA144VLL 48 256 MCXA144VMP MCXA144VMP 48 256 64 81 64 50 Table continues on the next page... Pin Count Package 100 LQFP 64 LFBGA Packing Tray Tray Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 3 / 88 NXP Semiconductors Table 1. Ordering Information (continued) Part Number Marking MCXA144VPJ MCXA145VLL MCXA145VMP MCXA145VPJ MCXA146VLL MCXA146VMP MCXA146VPJ MCXA154VLL MCXA154VMP MCXA154VPJ MCXA155VLL MCXA155VMP MCXA155VPJ MCXA156VLL MCXA156VMP MCXA156VPJ MCXA144VPJ MCXA145VLL MCXA145VMP MCXA145VPJ MCXA146VLL MCXA146VMP MCXA146VPJ MCXA154VLL MCXA154VMP MCXA154VPJ MCXA155VLL MCXA155VMP MCXA155VPJ MCXA156VLL MCXA156VMP MCXA156VPJ Core Flash (KB) Speed (MHz) 48 256 48 512 48 512 48 512 48 1024 48 1024 48 1024 96 256 96 256 96 256 96 512 96 512 96 512 96 1024 96 1024 96 1024 SRAM (KB) 64 96 96 96 128 128 128 64 64 64 96 96 96 128 128 128 GPIOs Pin Count Package Packing 82 112 VFBGA Tray 81 100 LQFP Tray 50 64 LFBGA Tray 82 112 VFBGA Tray 81 100 LQFP Tray 50 64 LFBGA Tray 82 112 VFBGA Tray 81 100 LQFP Tray 50 64 LFBGA Tray 82 112 VFBGA Tray 81 100 LQFP Tray 50 64 LFBGA Tray 82 112 VFBGA Tray 81 100 LQFP Tray 50 64 LFBGA Tray 82 112 VFBGA Tray Table 2. Device Revision Number Device Mask Set Number 0P29K DIE_ID 0x0059DAA0 JTAG ID Register[PRN] 0x0726702B Table 3. Related Resources Type Description Resource Fact Sheet The Fact Sheet gives overview of the product key features and its MCXA1xxFS uses. Reference Manual The Reference Manual contains a comprehensive description of the MCXAP100M96FS6RM structure and function (operation) of a device. Data Sheet The Data Sheet includes electrical characteristics and signal connections. This document Chip Errata The chip mask set Errata provides additional or corrective information for a particular device mask set. MCXA156_P29K Package drawing Package dimensions are provided in package drawings. · LQFP100: 98ASS23308W · LFBGA64: 98ASA02085D Table continues on the next page... Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 4 / 88 NXP Semiconductors Table 3. Related Resources (continued) Type Description Software development kit MCUXpresso SDK. An open source software development kit (SDK) built specifically for your processor and evaluation board selections. Resource · VFBGA112: 98ASA02081D http://www.nxp.com/mcuxpresso Analog 2x 16 bit ADC 1x OpAmp w/ PGA 1x 12-bit DAC 2x LPCMP Temp sensor Advanced motor control 2x FlexPWM 2x eQDC (Quadrature decoder) 2x AOI (AND/OR invert) Security Security monitoring (intrusion detection) Lifecycle management Access control (memory and debug) Core Arm® Cortex® - M33 48/96 MHz with FPU, SIMD Memories Up to 1 MB flash w/4 KB cache Up to 128 KB SRAM (8 KB w/ECC) 16 KB ROM w/boot loader System Power management (POR/LVD/HVD, LDO) Clock generation Low-power internal clock (16 KHz, 12 MHz, 192 MHz) External XTAL (8-50 MHz) DMA Peripheral input multiplexing (INPUTMUX) Connectivity 4x LPI2C 5x LPUART 2x LPSPI Full-speed USB w/PHY 1x I3C 1x CAN-FD HMI FlexIO Timers 5x 32-bit timers Wake timer Frequency measurement timer Windowed watchdog timer Low-power timer Micro-tick timer OS event timer Figure 1. Block Diagram Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 5 / 88 NXP Semiconductors ARM Cortex M33 without TZ, MPU, w/ FPU SIMD 48 MHz 1.0 V 96 MHz 1.1 V DMA0 USB - FS Code System SRAMX 1 LPCAC M0 M1 M2 M3 P0 Multilayer AHB matrix P1 P3 P0 P2 ROM 16 KB MBC FMC FMU Flash 1 MB SRAM X 0 8 KB SRAM X 1 4 KB SRAM X0 Alias LPCAC SRAM A0 8 KB w/ ECC SRAM A1 16 KB SRAM A2 8 KB SRAM A3 32 KB SRAM B0 32 KB SRAM B1 16 KB SRAM B2 8 KB SRAM X0 Alias SRAM X0 Clocks, Power control, LDOs, System functions PoR LVD/HVD FRO SOSC CRC DMA3 0 CH0~7 FMC(NPX) LPI2C0~3 LPUART0~4 USB FS PHY FlexIO ERM FlexPWM 0~1 1:x wraper eQDC0/1 OpAmp 0 AIPS bridge 0 APB bridge 0 Debug mailbox Code WDG DMA3 0 MBC FMU SCG-lite LPS PI 0 ~1 USB FS CAN0 EIM AOI0 0~1 ADC 0 ADC 1 Po r t0 ~4 12 bit DAC 0 CMC SPC WUU Wake Timer LPTMR 0 VBAT OS_Event_Timer LPCMP0 LPCMP1 SYSCON Windowed WDG0 CTIMER 0~4 Micro-Tick timer Frequency measurement Peripheral input mux I3C0 GPIO 0~4 VSYS domain VDD_CORE domain Figure 2. Bus Architecture Can be accessed when remap is enabled Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 6 / 88 Contents 1 2 2.1 2.2 2.3 2.4 2.5 3 3.1 3.2 3.2.1 3.2.2 3.2.2.1 3.2.3 3.2.4 3.2.4.1 3.2.5 3.2.6 3.2.7 3.2.8 3.2.9 3.3 3.3.1 3.3.2 3.3.2.1 3.4 3.4.1 3.4.2 4 4.1 4.1.1 4.1.2 4.1.3 4.2 4.2.1 4.2.1.1 4.2.1.2 4.2.1.3 4.2.2 4.2.3 4.2.4 4.3 4.3.1 4.3.1.1 4.3.1.2 Feature Comparison ..........................................9 Ratings............................................................. 11 Thermal handling ratings.............................. 11 Moisture handling ratings..............................11 ESD handling ratings.................................... 11 Voltage and current maximum ratings.......... 12 Required Power-On-Reset (POR) Sequencing ...................................................................... 12 General.............................................................12 AC electrical characteristics.......................... 12 Nonswitching electrical specifications........... 13 Voltage and current operating requirement.. 13 HVD, LVD, and POR operating requirements ...................................................................... 14 VDD supply HVD, LVD, and POR Operating Requirements................................................14 Voltage and current operating behaviors...... 15 On-chip regulator electrical specifications.... 16 LDO_CORE electrical specifications.............16 Power mode transition operating behaviors..16 Power consumption operating behaviors......17 EMC radiated emissions operating behaviors ...................................................................... 20 Designing with radiated emissions in mind... 20 Capacitance attributes.................................. 20 Switching specifications................................ 21 Device clock specs....................................... 21 General switching specifications...................21 General switching specifications...................21 Thermal specifications ................................. 24 Thermal operating requirements...................24 Thermal attributes......................................... 24 Peripheral operating requirements and behaviors ......................................................................... 24 Core modules ...............................................24 Debug trace operating behaviors..................24 JTAG Debug Interface Timing...................... 25 Serial Wire Debug (SWD) Timing................. 27 Clock modules ............................................. 29 Reference Oscillator Specification................ 29 System Crystal Oscillator Specification........ 29 System Oscillator Crystal Specifications.......30 System Oscillator Crystal Specifications ......30 FRO-192M specifications..............................31 FRO-12M specifications................................32 FRO16K specifications................................. 32 Memories and memory interfaces ................32 Flash electrical specifications ...................... 32 Timing specifications ....................................32 Flash high voltage current behavior..............34 4.3.1.3 4.4 4.4.1 4.4.1.1 4.4.1.2 4.4.1.3 4.4.2 4.4.2.1 4.4.2.2 4.4.3 4.4.4 4.4.5 4.5 4.6 4.6.1 4.6.2 4.6.2.1 4.6.2.2 4.6.3 4.6.4 4.6.5 4.6.6 4.6.7 4.6.8 4.6.9 4.7 4.7.1 5 5.1 6 6.1 6.2 6.3 7 7.1 8 8.1 8.2 8.3 8.4 8.4.1 9 9.1 Flash reliability specifications........................34 Analog ..........................................................35 ADC electrical specifications.........................35 ADC operating conditions............................. 35 I/O mux resistance table............................... 36 ADC electrical characteristics....................... 37 12-bit DAC electrical characteristics............. 41 12-bit DAC operating requirements.............. 41 12-bit DAC operating behaviors....................41 Comparator and 8-bit DAC electrical specifications................................................ 44 OpAmp electrical specifications.................... 47 PGA electrical specifications.........................48 Timers........................................................... 49 Communication Interfaces ........................... 49 LPUART........................................................ 49 LPSPI switching specifications .................... 49 LPSPI master mode timing........................... 49 LPSPI slave mode timing..............................51 LPI2C timing................................................. 54 I2C 1 Mbps timing......................................... 56 I2C HS mode timing......................................57 I3C Push-Pull Timing Parameters for SDR Mode............................................................. 57 USB Full-speed device electrical specifications ...................................................................... 60 FlexCAN........................................................61 Flexible I/O controller (FLEXIO) electrical specifications................................................ 61 Human Machine Interface (HMI) modules ... 61 General Purpose Input/Output (GPIO)..........61 Package dimensions ....................................... 61 Obtaining package dimensions.....................61 Pinout .............................................................. 61 MCXA156, A155, A154, A146, A145, A144 Signal Multiplexing and Pin Assignments..... 61 MCXA156, A155, A154, A146, A145, A144 Pinout diagram..............................................78 Recommended connection for unused analog and digital pins.............................................. 78 Ordering parts.................................................. 79 Determining valid orderable parts................. 79 Part identification..............................................79 Description.................................................... 80 Part number format....................................... 80 Example........................................................ 80 Small package marking.................................81 Package marking information....................... 81 Terminology and guidelines............................. 81 Definitions..................................................... 81 9.2 Examples...................................................... 82 9.6 Specification Test Methods...........................83 9.3 Typical-value conditions................................82 10 Revision History............................................... 84 9.4 Relationship between ratings and operating Chapter Legal information..............................................85 requirements................................................. 83 9.5 Guidelines for ratings and operating requirements................................................. 83 NXP Semiconductors 1 Feature Comparison Feature Comparison Table 4. Feature Comparison MCXA146 MCXA145 MCXA144 MCXA156 MCXA155 MCXA154 Core Platform Core Cortex-M33 Cache 48 MHz 48 MHz 48 MHz 96 MHz 4 kB 96 MHz 96 MHz DMA 8 Channels Wakeup unit (WUU) Yes Peripheral input Yes multiplexing (INPUTMUX) Clock Fast internal reference clock FRO192M 48 MHz 48 MHz 48 MHz 192 MHz 192 MHz 192 MHz Slow internal reference clock FRO12M 12 MHz Low power internal reference clock FRO16K 16.384 KHz System oscillator with external crystal (SOSC) 8-50 MHz Memory Flash 1024 kB 512 kB 256 kB 1024 kB 512 kB 256 kB SRAM 128 kB including 8 kB with ECC 96 kB including 8 kB with ECC 64 kB including 8 kB with ECC 128 kB including 8 kB with ECC 96 kB including 8 kB with ECC 64 kB including 8 kB with ECC Error injection module Yes (EIM) Error recording module Yes (ERM) Security Lifecycle management Yes (LC) Read out protection Yes (ROP) Memory block checker Yes (MBC) GLIKEY Yes UUID 128-bit Code watchdog (CDOG) 1 Cyclic redundancy check 1 (CRC) Table continues on the next page... Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 9 / 88 NXP Semiconductors Feature Comparison Table 4. Feature Comparison (continued) MCXA146 MCXA145 MCXA144 MCXA156 MCXA155 MCXA154 Communic LPUART 5 ation Interfaces LPSPI 2 LPI2C 4 I3C 1 USB FS Device 1 FlexCAN1 1 1 1 1x CAN FD 1x CAN FD 1x CAN FD Flexible I/O (FlexIO) 1 Analog Low power comparator 2 (LPCMP) ADC 2 DAC 0 0 0 1 1 1 OPAMP 0 0 0 1 1 1 Motor FlexPWM 2 1 1 1 2 2 2 Control AND/OR INVERT (AOI) 2 Quadrature decoder 1 1 1 2 2 2 (eQDC)3 Timer 32-bit timer (CTimer) 5 Low power timer (LPTMR) 1 Micro-tick timer (UTICK) 1 OS event timer 1 Windowed watchdog timer 1 (WWDT) Frequency measurement 1 (FREQME) Wake timer IO Independent IO supply 4 5V tolerant IO 5 High drive IO (20 mA) 6 50 MHz IO 7 1 VDD_P3 2 Up to 8 Up to 21 Packages VFBGA112 (PJ) 82 8 LQFP100 (LL) 81 LFBGA64 (MP) 50 Temperature Range -40 °C to 125 °C 1. Flexible data rate (CAN FD) is available on MCXA156/A155/A154 2. FlexPWM0 is available on MCXA146/A145/A144. There`re 3 sub-modules for each FlexPWM module. 3. eQDC0 is available on MCXA146/A145/A144. Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 10 / 88 NXP Semiconductors 4. Support 1.2V IO power supply. 5. P3_27, P3_28 are 5V tolerant IOs. 6. P1_8,P1_9,P1_30,P1_31,P3_1,P3_0,P0_16,P0_17 are High Drive IOs. 7. 50 MHz IOs are located on P1, P3, P4 ports. 8. Show the package types and GPIO numbers 2 Ratings Ratings 2.1 Thermal handling ratings Table 5. Thermal handling ratings Symbol TSTG TSDR Description Min Typ Max Unit Condition Storage temperature 1 55 -- 150 °C -- Solder temperature, lead-free 2 -- -- 260 °C -- 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 2.2 Moisture handling ratings Table 6. Moisture handling ratings Symbol MSL Description Moisture sensitivity level 1 Min Typ Max Unit Condition -- -- 3 -- -- 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 2.3 ESD handling ratings Table 7. ESD handling ratings Description Electrostatic discharge voltage, human body model Electrostatic discharge voltage, charged-device model Electrostatic discharge voltage, charged device model (corner pins) Rating +/-2000 +/-500 +/-750 Unit V V V Notes 1 2 2 Latch-up immunity level (Class II at 125 °C Immunity Level A -- 3 junction temperature) 1. Determined according to ANSI/ESDA/JEDEC Standard JS-001-2023, For Electrostatic Discharge Sensitivity Testing, Human Body Model (HBM) - Device Level. 2. Determined according to ANSI/ESDA/JEDEC Standard JS-002-2022, For Electrostatic Discharge Sensitivity Testing, Charged Device Model (CDM) - Device Level. 3. Determined according JEDEC Standard JESD78F, IC Latch-Up Test. Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 11 / 88 NXP Semiconductors General 2.4 Voltage and current maximum ratings Table 8. Voltage and current maximum ratings Symbol VDD Description Min Typ Max Unit Supply voltage for Port 0, Port -0.3 -- 3.63 V -- 1, Port 2 VDD_P3 VDD_ANA VDD_USB VUSB0_Dx VDIO Supply Voltage for Port 3 -0.3 -- Supply voltage for ADC -0.3 -- Supply voltage for USB analog -0.3 -- USB0_DP and USB0_DM input -0.3 -- voltage Digital input voltage -0.3 -- VDIO_5VTOL Digital input voltage for 5V -0.3 -- tolerant I/O pins VAIO IDD ID Analog input voltageAnalog pins -0.3 -- are defined as pins that do not have an associated general- purpose I/O port function. 1 Digital supply current 2 -- -- Maximum current single pin limit -25 -- (digital output pins) 3.63 V -- 3.63 V -- 3.63 V -- 3.63 V -- VDD + 0. V -- 3 min(VDD V -- + 3.6V, 5.5V) VDD_ V -- ANA + 0. 3 100 mA -- 25 mA -- 1. Analog pins are defined as pins that do not have an associated general-purpose I/O port function. 2. This limit is per supply pin. It includes all power pins, including VDD, VDD_P3, VDD_ANA, VDD_USB. Condition 2.5 Required Power-On-Reset (POR) Sequencing · VDD and VDD_ANA must be same voltage 3 General 3.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 12 / 88 NXP Semiconductors General Low VIH Input Signal Midpoint1 Fall Time VIL High Rise Time The midpoint is VIL + (VIH - VIL) / 2 Figure 3. Input signal measurement reference 80% 50% 20% 3.2 Nonswitching electrical specifications 3.2.1 Voltage and current operating requirement Table 9. Voltage and current operating requirement Symbol Description Min Typ VDD Supply Voltage for IO, LDO, 1.71 -- Flash, and LPCMP VDD_P3 Supply voltage for Port 3 1.14 -- VDD_P3 Supply Voltage for Port 3 1.71 -- VDD_ANA Supply voltage for ADC VDD - 0. -- 1 VSS - VSS_ANA VSS-to-VSS_ANA differential -0.1 -- voltage VDD_USB Supply voltage for USB analog 3.0 -- VIH Input high voltage 0.7 × -- VDD VIH_5VTOL Input high voltage of 5V tolerant 0.7 × -- IO VDD VIL Input low voltage -- -- VIL_5VTOL VHYS VHYS_5VTOL IICIO Input low voltage of 5 V tolerant -- -- IO Input hysteresis 0.1 × -- VDD Input hysteresis of 5 V tolerant 0.1 × -- IO VDD IO pin DC injection current -- -3 -- per pin 1 Max 3.6 Unit V 1.32 V 3.6 V VDD + 0. V 1 0.1 V 3.6 V -- V -- V 0.3 × V VDD 0.3 × V VDD -- V -- V -- mA Table continues on the next page... Condition -- 1.2V Normal condition -- -- -- 1.71 V VDD 3.6 V 1.71 V VDD 3.6 V 1.71 V VDD 3.6 V 1.71 V VDD 3.6 V -- -- VIN < VSS-0.3 V (negative current injection) Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 13 / 88 NXP Semiconductors General Table 9. Voltage and current operating requirement (continued) Symbol IICIO IICcont IICcont VODPU Description IO pin DC injection current -- per pin 1 Min -- Contiguous pin DC injection -25 current --regional limit, includes sum of negative injection currents of 16 contiguous pins Contiguous pin DC injection -- current --regional limit, includes sum of negative injection currents of 16 contiguous pins Open drain pullup voltage level 2 VDD Typ -- -- -- -- Max 3 -- 25 VDD Unit mA mA mA V Condition VIN > VDD+0.3 V (positive current injection) Negative current injection Positive current injection -- 1. All I/O pins are internally clamped to VSS and VDD through an ESD protection diode. If VIN is greater than VDD_MIN(=VSS-0.3 V) or is less than VDD_MAX(=VDD+ 0.3 V), then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed, then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R = (-0.3 - VIN)/(-IICIOmin). The positive injection current limiting resistor is calculated as R=(VIN-VDD_MAX)/IICIOmax. The actual resistor should be an order of magnitude higher to tolerate transient voltages 2. Open drain outputs must be pulled to whichever supply voltage corresponds to that IO, VDD as appropriate. 3.2.2 HVD, LVD, and POR operating requirements The device includes low-voltage detection (LVD) and high-voltage detection (HVD) power supervisor circuits for following power supplies: · VDD 3.2.2.1 VDD supply HVD, LVD, and POR Operating Requirements Table 10. VDD supply HVD, LVD, and POR Operating Requirements Symbol Description Min Typ Max Unit Condition VHVDH_VDD VDD Rising high-voltage detect 3.730 3.810 3.890 V -- threshold (HVD assertion) VHVDH_HYS_VDD VDD High-voltage inhibit reset/ -- 38 -- mV -- recover hysteresis VLVDH_VDD VDD Falling low-voltage detect 2.567 2.619 2.673 V -- threshold (LVD assertion) - high range VLVDH_HYS_VDD VDD Low-voltage inhibit reset/ -- 27 -- mV -- recover hysteresis - high range VLVDL_VDD VDD Falling low-voltage detect 1.618 1.651 1.684 V -- threshold (LVD assertion) - low range VLVDL_HYS_VDD VDD Low-voltage inhibit reset/ -- 16 -- mV -- recover hysteresis - low range Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 14 / 88 NXP Semiconductors 3.2.3 Voltage and current operating behaviors Table 11. Voltage and current operating behaviors Symbol Description Min Typ Max VOH Output high voltage -- Normal VDD 0. -- -- drive strength 1 5 VOH Output high voltage -- Normal VDD 0. -- -- drive strength 1 5 VOH Output high voltage -- Normal VDD - -- -- drive strength 1 0.5 VOH Output high voltage -- High VDD 0. -- -- drive strength 1,2 5 VOH Output high voltage -- High VDD 0. -- -- drive strength 1,2 5 VOH Output high voltage -- High VDD - -- -- drive strength 1,2 0.5 IOHT Output high current total for all -- -- 100 ports VOL Output low voltage -- Normal -- -- 0.5 drive strength 1,3 VOL Output low voltage -- Normal -- -- 0.5 drive strength 1,3 VOL Output low voltage -- Normal -- -- 0.5 drive strength 1,3 VOL Output low voltage -- High drive -- -- 0.5 strength 1,2,3 VOL Output low voltage -- High drive -- -- 0.5 strength 1,2,3 VOL Output low voltage -- High drive -- -- 0.5 strength 1,2,3 IOLT Output low current total for all -- -- 100 ports IIN Input leakage current (per pin) -- 0.02 1 for full temperature range 4 IIN Input leakage current (per pin) -- 0.001 0.025 at 25 °C 4 IIN Input leakage current (total all -- 0.025 41 pins) for full temperature range 4 IOZ Hi-Z (off-state) leakage current -- 0.02 1 (per pin) RPU Internal pullup resistors 33 50 75 Table continues on the next page... Unit V V V V V V mA V V V V V V mA A A A A k General Condition 2.7 V VDD 3.6 V, IOH = 4 mA 1.71 V VDD < 2.7 V, IOH = 2.5 mA 1.14 V VDD < 1.32 V, IOH = 0.5 mA 2.7 V VDD 3.6 V, IOH = 6 mA 1.71 V VDD < 2.7 V, IOH = 3.75 mA 1.14 V VDD < 1.32 V, IOH = 0.75 mA -- 2.7 V VDD 3.6 V, IOL = 4 mA 1.71 V VDD < 2.7 V, IOL = 2.5 mA 1.14 V VDD < 1.32 V, IOL = 0.5 mA 2.7 V VDD 3.6 V, IOL = 6 mA 1.71 V VDD < 2.7 V, IOL = 3.75 mA 1.14 V VDD < 1.32 V, IOL = 0.75 mA -- -- -- -- -- -- Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 15 / 88 NXP Semiconductors General Table 11. Voltage and current operating behaviors (continued) Symbol RPU (I3C) Description Internal pullup resistors 5 Min Typ Max Unit (VDD - 1.75 -- 0.27 V)/3 mA k -- RPD Internal pulldown resistors 33 50 75 k -- RHPU High-resistance pullup option 0.67 -- (PCRx[PV] = 1) 6 1.5 M -- RHPD High-resistance pulldown option 0.67 -- (PCRx[PV] = 1) 6 1.5 M -- VBG Bandgap voltage reference 0.98 1.0 1.02 V -- voltage 1. For the HD pads, when setting DSE1=1, the IOH/IOL are four times higher at the same VOH/VOL. 2. RESET_B pins are always configured in high drive mode 3. Open drain outputs must be pulled to VDD 4. Measured at VDD = 3.6 V. 5. Only I3C pins support this option 6. Only RST pins support this option. Condition 3.2.4 On-chip regulator electrical specifications 3.2.4.1 LDO_CORE electrical specifications Table 12. LDO_CORE electrical specifications Symbol Description VDD LDO_CORE input supply voltage ILOAD ILOAD LDO_CORE max load current LDO_CORE max load current IDD LDO_CORE current consumption IDD LDO_CORE current consumption IINRUSH LDO_CORE inrush current Min 1.71 -- -- -- -- -- Typ -- -- -- -- -- -- Max 3.6 16 2 250 500 10 Unit V mA mA A nA mA Condition -- Normal drive strength Low drive strength Normal drive strength Low drive strength -- 3.2.5 Power mode transition operating behaviors All specifications in the following table assume this clock configuration: · CPU clock = 48 MHz · AHB clock = 48 MHz · Clock source = FIRC Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 16 / 88 NXP Semiconductors General Table 13. Power mode transition operating behaviors Symbol Description Min Typ Max Unit Condition tPOR tSLEEP tDSLEEP tPWDN After a POR event, amount -- of time to execution of the first instruction (measured from the point where VDD reach 1.8V) across the operating temperature range of the chip. 1,2 Sleep Active 1,2,3,4 -- Deep Sleep Active 1,2,3,4 -- Power Down Active 1,2,3,5 -- 2.34 2.43 ms -- 0.23 0.27 s -- 7.1 8.4 s -- 16.6 19.9 s -- tDPWDN Deep Power Down Active 1,2,3,4 -- 1.44 1.52 ms -- 1. Max value is mean+3 × sigma of tested values at the worst case of ambient temperature range and VDD 1.71 V to 3.6 V. Max values are based on characterization but not covered by test limits in production. 2. Typical value is the average of values tested at Temperature=25 and VDD=3.3 V 3. WFE used for Low Power mode entry 4. SPC->LPWKUP_DELAY[LPWKUP_DELAY] = 0x00 and the Core voltage level is configured for the same level in Active and Low Power mode (SPC->ACTIVE_CFG[CORELDO_VDD_LVL]=SPC->LP_CFG[CORELDO_VDD_LVL]= 01b). 5. SPC->LPWKUP_DELAY[LPWKUP_DELAY] = 0x5B and the Core voltage level is configured as different level for Active mode, (SPC->ACTIVE_CFG[CORELDO_VDD_LVL] = 01b for Active mode, SPC->LP_CFG[CORELDO_VDD_LVL] = 00b for Low Power mode) 3.2.6 Power consumption operating behaviors When calculating the total MCU current consumption the following considerations should be made: · Specifications below only include power for the MCU itself including VDD, VDD_ANA, VDD_P3. · VDD_USB current draw are not included · On top of the device's IDD current consumption, external loads applied to pins of the device need to be considered Symbol Description Condition 1 Typ Unit IDD_ACT_MD_1 2 1. CPU_CLK = 48 MHz from FRO192M; VDD_CORE 25 °C 3.06 mA = 1.0 V from LDO_CORE normal drive. 105 °C 3.62 mA 2. All peripheral clocks disabled; Flash is configured to 125 °C 4.17 mA LP mode; Cache enabled. 3. While(1) loop executing from internal flash. IDD_ACT_MD_2 1. CPU_CLK = 48 MHz from FRO192M; VDD_CORE 25 °C 3.31 mA = 1.0 V from LDO_CORE normal drive. 105 °C 3.90 mA 2. All peripheral clocks enabled; Cache enabled. 125 °C 4.47 mA 3. While(1) loop executing from internal flash. IDD_ACT_MD_CM_1 1. CPU_CLK = 48 MHz from FRO192M; VDD_CORE 25 °C 3.40 mA = 1.0 V from LDO_CORE normal drive. Table continues on the next page... Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 17 / 88 NXP Semiconductors Table continued from the previous page... 105 °C 3.95 2. All peripheral clocks disabled; Flash is configured to LP mode; Cache enabled. 125 °C 4.48 3. CoreMark executing from internal flash. IDD_ACT_MD_CM_2 1. CPU_CLK = 48 MHz from FRO192M; VDD_CORE 25 °C 3.66 = 1.0 V from LDO_CORE normal drive. 105 °C 4.23 2. All peripheral clocks enabled; Cache enabled. 125 °C 4.79 IDD_ACT_SD_1 3. CoreMark executing from internal flash. 1. CPU_CLK = 96 MHz from FRO192M; VDD_CORE 25 °C 6.40 = 1.1 V from LDO_CORE normal drive. 105 °C 7.11 2. All peripheral clocks disabled; Cache enabled. 125 °C 7.76 IDD_ACT_SD_2 3. While(1) loop executing from internal flash. 1. CPU_CLK = 96 MHz from FRO192M, FRO192M 25 °C 7.45 output is 192MHz; VDD_CORE = 1.1 V from LDO_CORE normal drive. 105 °C 8.16 2. All peripheral clocks enabled; Cache enabled. 125 °C 8.82 IDD_ACT_SD_CM_1 3. While(1) loop executing from internal flash. 1. CPU_CLK = 96 MHz from FRO192M; VDD_CORE 25 °C 7.09 = 1.1 V from LDO_CORE normal drive. 105 °C 7.72 2. All peripheral clocks disabled; Cache enabled. 125 °C 8.40 IDD_ACT_SD_CM_2 3. CoreMark executing from internal flash. 1. CPU_CLK = 96 MHz from FRO192M, FRO192M 25 °C 8.13 output is 192MHz; VDD_CORE = 1.1 V from LDO_CORE normal drive. 105 °C 8.79 2. All peripheral clocks enabled; Cache enabled. 125 °C 9.42 IDD_SLEEP_SD IDD_SLEEP_MD_1 3. CoreMark executing from internal flash. 1. CPU_CLK = OFF, SYSTEM_CLK = 96 MHz from 25 °C 3.34 FRO192M; VDD_CORE = 1.1 V from LDO_CORE normal drive. 105 °C 4.05 2. All peripheral clocks disabled. 125 °C 4.70 1. CPU_CLK = OFF, SYSTEM_CLK = 48 MHz from 25 °C 1.81 FRO192M; VDD_CORE = 1.0 V from LDO_CORE normal drive. 105 °C 2.39 2. All peripheral clocks disabled. 125 °C 2.93 Table continues on the next page... Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 General mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA 18 / 88 NXP Semiconductors Table continued from the previous page... IDD_SLEEP_MD_2 1. CPU_CLK = OFF, SYSTEM_CLK = 12 MHz from FRO12M; VDD_CORE = 1.0 V from LDO_CORE low drive. IDD_DEEP_SLEEP_SD 2. All peripheral clocks disabled. 1. CPU_CLK = SYSTEM_CLK = OFF; VDD_CORE = 1.1 V from LDO_CORE normal drive. 2. Core domain in Deep Sleep; FRO12M disabled. IDD_DEEP_SLEEP_MD_1 1. CPU_CLK = SYSTEM_CLK = OFF; VDD_CORE = 1.0 V from LDO_CORE low drive. 2. Core domain in Deep Sleep; FRO12M disabled. IDD_DEEP_SLEEP_MD_2 1. CPU_CLK = SYSTEM_CLK = OFF; VDD_CORE = 1.0 V from LDO_CORE low drive. IDD_POWER_DOWN_1 2. Core domain in Deep Sleep; FRO12M enabled. 1. CPU_CLK = SYSTEM_CLK = OFF; VDD_CORE = retention voltage from LDO_CORE low drive. IDD_POWER_DOWN_2 2. Core domain in Power Down(Lowest power mode can retain all registers); All RAM retained; FRO16K disabled. 1. CPU_CLK = SYSTEM_CLK = OFF; VDD_CORE = retention voltage from LDO_CORE low drive. IDD_DEEP_POWER_DO WN_1 2. Core domain in Power Down(Lowest power mode can retain all registers); RAM X0/X1 and RAM A0 retained; FRO16K disabled. 1. CPU_CLK = SYSTEM_CLK = OFF; LDO_CORE is powered off. IDD_DEEP_POWER_DO WN_2 2. Core domain in Deep Power Down; All RAM OFF; FRO16K disabled; Wakeup timer disabled. 1. CPU_CLK = SYSTEM_CLK = OFF; LDO_CORE is powered off. IDD_DEEP_POWER_DO WN_3 2. Core domain in Deep Power Down; All RAM OFF; FRO16K enabled; Wakeup timer enabled. 1. CPU_CLK = SYSTEM_CLK = OFF; LDO_CORE is powered off. IDD_DEEP_POWER_DO WN_4 2. Core domain in Deep Power Down; All RAM retained; FRO16K enabled; Wakeup timer enabled. 1. CPU_CLK = SYSTEM_CLK = OFF; LDO_CORE is powered off. 25 °C 105 °C 125 °C 25 °C 105 °C 125 °C 25 °C 105 °C 125 °C 25 °C 105 °C 125 °C 25 °C 105 °C 125 °C 25 °C 105 °C 125 °C 25 °C 105 °C 125 °C 25 °C 105 °C 125 °C 25 °C 105 °C 125 °C 25 °C Table continues on the next page... 0.43 0.99 1.55 257.98 781.14 1286.88 32.26 470.82 916.19 104.53 542.00 988.01 9.47 257.00 520.08 8.20 222.28 443.17 0.41 5.62 12.88 0.60 5.83 13.08 2.19 47.39 105.34 1.57 Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 General mA mA mA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA 19 / 88 NXP Semiconductors General Table continued from the previous page... 105 °C 29.84 µA 2. Core domain in Deep Power Down; RAM X0/X1 and RAM A0~A3 retained; FRO16K enabled; Wakeup 125 °C 66.33 µA timer enabled. IDD_DEEP_POWER_DO 1. CPU_CLK = SYSTEM_CLK = OFF; LDO_CORE is 25 °C 0.93 µA WN_5 powered off. 105 °C 12.71 µA 2. Core domain in Deep Power Down; RAM X0/X1 and 125 °C 28.28 µA RAM A0 retained; FRO16K enabled; Wakeup timer enabled. IDD_DEEP_POWER_DO 1. CPU_CLK = SYSTEM_CLK = OFF; LDO_CORE is 25 °C 0.79 µA WN_6 powered off. 105 °C 8.86 µA 2. Core domain in Deep Power Down; RAM A0 125 °C 19.80 µA retained; FRO16K enabled; Wakeup timer enabled. IDD_DEEP_POWER_DO 1. CPU_CLK = SYSTEM_CLK = OFF; LDO_CORE is 25 °C 0.82 µA WN_7 powered off. 105 °C 9.88 µA 2. Core domain in Deep Power Down; RAM X0/X1 125 °C 22.00 µA retained; FRO16K enabled; Wakeup timer enabled. 1. Ambient temperature 2. SD standard drive, core voltage is 1.1V. MD middle drive, core voltage is 1.0V 3.2.7 EMC radiated emissions operating behaviors EMC measurements to IC-level IEC standards are available from NXP on request. 3.2.8 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to nxp.com. 2. Perform a keyword search for "EMC design". 3.2.9 Capacitance attributes Table 14. Capacitance attributes Symbol Description Min Typ Max Unit Condition CIN_A Input capacitance: analog pins -- -- 7 pF -- CIN_D Input capacitance: digital pins -- -- 7 pF -- Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 20 / 88 NXP Semiconductors 3.3 Switching specifications 3.3.1 Device clock specs Table 15. Device clock specs Symbol Description fCPU CPU clock (CPU_CLK) Min -- fSYSTEM SYSTEM clock (SYSTEM_CLK) -- fSLOW Slow clock (SLOW_CLK) -- fCPU CPU clock (CPU_CLK) -- fSYSTEM SYSTEM clock (SYSTEM_CLK) -- fSLOW Slow clock (SLOW_CLK) -- Typ -- -- -- -- -- -- Max 96 96 24 48 48 12 Unit MHz MHz MHz MHz MHz MHz General Condition Standard drive (SD) mode VDD_CORE = 1. 1 V Standard drive (SD) mode VDD_CORE = 1. 1 V Standard drive (SD) mode VDD_CORE = 1. 1 V Middle drive (MD) mode VDD_CORE = 1. 0 V Middle drive (MD) mode VDD_CORE = 1. 0 V Middle drive (MD) mode VDD_CORE = 1. 0 V 3.3.2 General switching specifications These general-purpose specifications apply to all signals configured for GPIO, LPUART, LPI2C, LPI3C, LPSPI functions. 3.3.2.1 General switching specifications NOTE Refer to attached pinout spreadsheet. Table 16. General switching specifications Symbol Description Min Typ Max -- GPIO pin interrupt pulse width 1.5 -- -- (digital glitch filter disabled) -- Synchronous path 1 -- GPIO pin interrupt pulse width 150 -- -- (digital glitch filter disabled, analog filter enabled) -- Asynchronous path -- GPIO pin interrupt pulse width 50 -- -- (digital glitch filter disabled, analog filter disabled) -- Asynchronous path Table continues on the next page... Unit Condition SYSTEM The synchronous and clock asynchronous timing cycles must be met. ns -- ns -- Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 21 / 88 NXP Semiconductors General Table 16. General switching specifications (continued) Symbol Description Min -- External RST pin interrupt pulse 330 width -- Asynchronous path 2 Typ -- Max -- -- GPIO pin interrupt pulse width 16 -- -- -- Asynchronous path 2 -- Port rise/fall time for slow I/O 1 -- 7 pins 3,4 -- Port rise/fall time for slow I/O 3.5 -- 15 pins 3,4 -- Port rise/fall time for slow I/O 1 -- 7 pins 3,4 -- Port rise/fall time for slow I/O 9 -- 45 pins 3,4 -- Port rise/fall time for slow I/O 3.5 -- 25 pins 3,4 -- Port rise/fall time for slow I/O 1 -- 7 pins, 5V Tolerant 3,4 -- Port rise/fall time for slow I/O 3.5 -- 15 pins, 5V Tolerant 3,4 -- Port rise/fall time for slow I/O 1 -- 7 pins, 5V Tolerant 3,4 -- Port rise/fall time for slow I/O 3.5 -- 25 pins, 5V Tolerant 3,4 -- Port rise/fall time for slow I/O 3.5 -- 14 pins 3,4 -- Port rise/fall time for medium I/O 0.8 -- 4 pins 5,6 -- Port rise/fall time for medium I/O 1 -- 7 pins 5,6 Table continues on the next page... Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Condition This is the shortest pulse that is guaranteed to be recognized. -- 2.7 VDD 3.6 V, Fast slew rate (SRE = 0; DSE = 0) 2.7 VDD 3.6 V, Slow slew rate (SRE = 1; DSE = 0) 1.71 VDD < 2.7 V, Fast slew rate (SRE = 0; DSE = 1) 1.14 VDD < 1.32 V, Slow slew rate (SRE = 1; DSE = 1) 1.71 VDD < 2.7 V, Slow slew rate (SRE = 1; DSE = 1) 2.7 VDD 3.6 V, Fast slew rate (SRE = 0; DSE = 0) 2.7 VDD 3.6 V, Slow slew rate (SRE = 1; DSE = 0) 1.71 VDD < 2.7 V, Fast slew rate (SRE = 0; DSE = 1) 1.71 VDD < 2.7 V, Fast slew rate (SRE = 1; DSE = 1) 1.14 VDD < 1.32 V, Fast slew rate (SRE = 0; DSE = 1) 2.7 VDD 3.6 V, Fast slew rate (SRE = 0; DSE = 0) 2.7 VDD 3.6 V, Slow slew rate (SRE = 1; DSE = 0) Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 22 / 88 NXP Semiconductors General Table 16. General switching specifications (continued) Symbol -- -- -- -- -- -- -- -- -- -- -- Description Min Port rise/fall time for medium I/O 0.8 pins 5,6 Port rise/fall time for medium I/O 1 pins 5,6 HD pins 7 2.2 Port rise/fall time for HD pins 7 1 Port rise/fall time for HD pins 7 3.5 Port rise/fall time for HD pins 7 3.5 Port rise/fall time for HD pins 7 9 Port rise/fall time for HD pins 7 1 Port rise/fall time for HD pins 7 3.5 RST pins 4 3 RST pins 4 3.6 Typ -- -- -- -- -- -- -- -- -- -- -- Max 4 7 7 7 15 14 45 7 25 8 20 Unit ns ns ns ns ns ns ns ns ns ns ns Condition 1.71 VDD < 2.7 V, Fast slew rate (SRE = 0; DSE = 1) 1.71 VDD < 2.7 V, Slow slew rate (SRE = 1; DSE = 1) 2.7 VDD 3.6 V, Normal drive, fast slew rate (SRE = 0; DSE = 0) 2.7 VDD 3.6 V, Normal drive (DSE = 0), fast slew rate (SRE = 0) 2.7 VDD 3.6 V, Normal drive (DSE =0), slow slew rate (SRE = 1) 1.14 VDD < 1.32 V, Fast slew rate (SRE = 0; DSE = 1 or 3) 1.14 VDD < 1.32 V, Slow slew rate (SRE = 1; DSE = 1 or 3) 1.71 VDD < 2.7 V, High drive (DSE=1), Fast slew rate (SRE = 0) 1.71 VDD < 2.7 V, High drive (DSE =1), Slow slew rate (SRE=1) 2.7 VDD 3.6 V 1.71 VDD < 2.7 V 1. The synchronous and asynchronous timing must be met. 2. This is the shortest pulse that is guaranteed to be recognized 3. For the HD I/O pins, setting DSE1 = 1 will support the same rise/fall time at 4x the load capacitance. For the 5VTOL I/O pins, setting DSE1=1 will support the same fall time at 2x the load capacitance, but the rise time will increase due to the increased loading 4. Load is 25 pF. 5. Assumes default values in CALIB1 and CALIB0 in PORTS 6. 25 pF lumped load 7. Load is 25 pF for DSE=0. Load is 100 pF for DSE=2 or DSE=3. Drive strength and slew rate are configured using PORTx_PCRn[DSE1], PORTx_PCRn[DSE], and PORTx_PCRn[SRE]. Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 23 / 88 NXP Semiconductors 3.4 Thermal specifications Peripheral operating requirements and behaviors 3.4.1 Thermal operating requirements Table 17. Thermal operating requirements Symbol TA TJ Description Ambient temperature 1 Die junction temperature 2,3,4 Min -40 -- Typ Max Unit 25 125 °C -- -- 125 °C -- Condition 1. The device may operate at maximum TA rating as long as TJ maximum of 125 °C is not exceeded. The simplest method to determine TJ is: TJ = TA + RJA*chip power dissipation. 2. Operating at maximum conditions for extended periods may affect device reliability. Refer to Product Lifetime Usage Estimates application note (AN14194) 3. The device operating specification is not guaranteed beyond 125 °C TJ. 4. The maximum operating requirement applies to all chapters unless otherwise specifically stated. 3.4.2 Thermal attributes Table 18. Thermal attributes Rating Board Type1 Symbol Junction to Ambient Thermal Resistance 2 Junction-to-Top of Package Thermal Characterization Parameter 2 Junction to Case Top Thermal Resistance 3 JESD51-9, 2s2p JESD51-9, 2s2p NA RJA JT RJC 64 LFBGA 51.1 100 LQFP 52.7 112 VFBGA 53.0 Unit °C/W 8.4 6.0 4.8 °C/W 46.9 24.0 13.1 °C/W 1. Thermal test board meets JEDEC specification for this package (JESD51-9) 2. Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is solely for a thermal performance comparison of one package to another in a standardized specified environment. It is not meant to predict the performance of a package in an application-specific environment 3. Junction-to-Case top thermal resistance determined using an isothermal cold plate. 4 Peripheral operating requirements and behaviors 4.1 Core modules 4.1.1 Debug trace operating behaviors Table 19. Debug trace operating behaviors Symbol -- Description Frequency of operation Min -- Typ -- Max 36 -- Frequency of operation -- -- 25 T1 Clock period 27.78 -- -- T1 Clock period 40 -- -- Table continues on the next page... Unit MHz MHz ns ns Condition SD mode MD mode SD mode MD mode Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 24 / 88 NXP Semiconductors Peripheral operating requirements and behaviors Table 19. Debug trace operating behaviors (continued) Symbol Description Min Typ Max Unit Condition T2 Low pulse width 2 -- -- ns -- T3 High pulse width 2 -- -- ns -- T4 Clock and data rise time -- -- 3 ns -- T5 Clock and data fall time -- -- 3 ns -- T6 Data setup 1.5 -- -- ns -- T7 Data hold 1.0 -- -- ns -- TRACE_CLK T4 T5 T3 T2 T1 Figure 4. TRACE_CLKOUT specifications TRACE_CLK T6 T7 TRACE_DATA[3:0] Figure 5. Trace data specifications 4.1.2 JTAG Debug Interface Timing The following table gives the JTAG specifications in debug interface mode. Table 20. JTAG Debug Interface Timing Symbol Description Min Typ -- Operating voltage 1.71 -- J1 TCLK frequency of operation -- -- Max 3.6 25 J1 TCLK frequency of operation -- -- 12.5 J1 TCLK frequency of operation -- -- 25 Table continues on the next page... Unit V MHz MHz -- Condition -- Boundary Scan (SD mode) Boundary Scan (MD mode) JTAG-DP/TAP (SD mode) Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 25 / 88 NXP Semiconductors Peripheral operating requirements and behaviors Table 20. JTAG Debug Interface Timing (continued) Symbol Description J1 TCLK frequency of operation Min -- Typ -- J2 TCLK cycle period 1000/J1 -- J3 TCLK clock pulse width J2/2 -- J4 TCLK rise and fall times -- -- J5 Boundary scan input data setup 8 -- time to TCLK rise J5 Boundary scan input data setup 16 -- time to TCLK rise J6 Boundary scan input data hold -1 -- time after TCLK rise J6 Boundary scan input data hold -1 -- time after TCLK rise J7 TCLK low to boundary scan -- -- output data valid J7 TCLK low to boundary scan -- -- output data valid J8 TCLK low to boundary scan -- -- output high-Z J8 TCLK low to boundary scan -- -- output high-Z J9 JTAG-DP/TAP TMS, TDI input 8 -- data setup time to TCLK rise J9 JTAG-DP/TAP TMS, TDI input 16 -- data setup time to TCLK rise J10 JTAG-DP/TAP TMS, TDI input 1 -- data hold time after TCLK rise J10 JTAG-DP/TAP TMS, TDI input 1 -- data hold time after TCLK rise J11 TCLK low to JTAG-DP/TAP -- -- TDO data valid J11 TCLK low to JTAG-DP/TAP -- -- TDO data valid J12 TCLK low to JTAG-DP/TAP -- -- TDO high-Z J12 TCLK low to JTAG-DP/TAP -- -- TDO high-Z Max 12.5 -- -- 3 -- -- -- -- 18 38 18 38 -- -- -- -- 18 38 18 38 Unit -- ns ns ns ns ns ns ns ns -- ns -- ns -- ns -- -- ns ns -- Condition JTAG-DP/TAP (MD mode) -- -- -- SD mode MD mode SD mode MD mode SD mode MD mode SD mode MD mode SD mode MD mode SD mode MD mode SD mode MD mode SD mode MD mode TDOC represents the TDO bit frame of the scan packet in compact JTAG 2-wire mode. Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 26 / 88 NXP Semiconductors JTAG_TCLK J2 J3 J3 J4 J4 Figure 6. Test clock input timing Peripheral operating requirements and behaviors JTAG_TCLK JTAG_TDI/TMS JTAG_TDO JTAG_TDO Figure 7. Boundary scan (JTAG) timing J5 J6 Input data valid J7 Output data valid J8 JTAG_TCLK JTAG_TDI/TMS JTAG_TDO JTAG_TDO J9 J10 Input data valid J11 Output data valid J12 Figure 8. JTAG-DP/TAP timing 4.1.3 Serial Wire Debug (SWD) Timing The following table gives the Serial Wire Debug specifications for the device. Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 27 / 88 NXP Semiconductors Peripheral operating requirements and behaviors Table 21. Serial Wire Debug (SWD) Timing Symbol Description Min Typ -- Operating voltage 1.71 -- S1 SWD_CLK frequency of -- -- operation S1 SWD_CLK frequency of -- -- operation S2 SWD_CLK cycle period 1000/S1 -- S2 SWD_CLK cycle period 1000/S1 -- S3 SWD_CLK clock pulse width 20 -- S3 SWD_CLK clock pulse width 25 -- S4 SWD_CLK rise and fall times -- -- S5 SWD_DIO input data setup time 10 -- to SWD_CLK rise S5 SWD_DIO input data setup time 12.5 -- to SWD_CLK rise S6 SWD_DIO input data hold time 0 -- after SWD_CLK rise S6 SWD_DIO input data hold time 0 -- after SWD_CLK rise S7 SWD_CLK high to SWD_DIO -- -- data valid S7 SWD_CLK high to SWD_DIO -- -- data valid S8 SWD_CLK high to SWD_DIO 25 -- high-Z S8 SWD_CLK high to SWD_DIO 30 -- high-Z Max 3.6 25 20 -- -- -- -- 3 -- -- -- -- 25 30 -- -- Unit V MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns Condition -- SD mode MD mode SD mode MD mode SD mode MD mode -- SD mode MD mode SD mode MD mode SD mode MD mode SD mode MD mode SWD_CLK S2 S3 S3 S4 S4 Figure 9. Serial Wire clock input timing Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 28 / 88 NXP Semiconductors Peripheral operating requirements and behaviors SWD_CLK SWD_DIO S7 SWD_DIO S8 SWD_DIO Figure 10. Serial Wire data timing S5 S6 Input data valid Output data valid 4.2 Clock modules 4.2.1 Reference Oscillator Specification This chip is designed to meet targeted specifications with a ±40 ppm frequency error over the life of the part, which includes the temperature, mechanical, and aging excursions. The table below shows typical specifications for the Crystal Oscillator. 4.2.1.1 System Crystal Oscillator Specification Table 22. System Crystal Oscillator Specification Symbol fosc Tol Jitosc Vpp fec Description Crystal Frequency Frequency tolerance Jitter Peak-to-peak amplitude of oscillation 1 Externally provided input clock frequency 2 Min 8 -- -- -- 0 Typ -- ±10 70 0.6 -- Max 50 ±40 -- -- 50 Unit MHz ppm -- V MHz Condition -- -- Period jitter (RMS) -- -- tDC_EXTAL External clock duty cycle 45 50 55 % -- Vec Externally provided input clock Refer to -- -- -- -- amplitude 2 VIH and VIL specificat ion 1. When a crystal is being used with the oscillator, the EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 2. This specification is for an externally supplied clock driven to EXTAL and does not apply to any other clock input. Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 29 / 88 NXP Semiconductors Peripheral operating requirements and behaviors 4.2.1.2 System Oscillator Crystal Specifications. Table 23. System Oscillator Crystal Specifications. Symbol CP ESR Cpara Cpara Cm Lm tstart IOSC IOSC Description Min Shunt Capacitance -- Crystal equivalent series -- resistance 1 Parasitic capacitance of EXTAL -- Parasitic capacitance of XTAL -- Motional capacitance Cm 2.05 Motional inductance Lm 7.7 Crystal start-up time 2 -- Current consumption -- Current consumption -- Typ 1 20 -- -- 2.05 -- 350 270 1 Max 2 50 8 10 2.665 -- 500 -- 465 Unit pF pF pF fF mH s A -- Condition -- -- -- -- -- -- -- Normal mode Sleep mode 1. Maximum crystal equivalent series resistance for 16 MHz is 80 ohms with 2 pF shunt capacitance. 2. Dependent on crystal specifications, proper PC board layout procedures must be followed to achieve specifications Lm Cm Rm Cp Cload Figure 11. Crystal Electrical Block Diagram 4.2.1.3 System Oscillator Crystal Specifications Table 24. System Oscillator Crystal Specifications. Freq Crystal (MHz) Rm(ohms) Cp(pF) Cload(pF) Cm(pF) Lm(mH) Typical startup (µs)1 8 100 5.00 18.0 0.008 49.47 1240 16 80 2.00 8.00 0.008 12.37 215 16 200 1.00 8.00 0.008 12.37 186 25 60 3.00 11.0 0.008 5.07 224 25 60 2.00 10.0 0.008 5.07 128 25 100 1.00 8.00 0.008 5.07 73.6 32 60 3.00 9.00 0.008 3.09 233 Table continues on the next page... Typical Current consumpti on (µA)1 Drive level (µW) min max 168 24 34 168.3 16 22 200.4 31 46 245.6 70 93 232.5 61 80 232.7 62 82 269.6 71 95 Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 30 / 88 NXP Semiconductors Peripheral operating requirements and behaviors Table 24. System Oscillator Crystal Specifications. (continued) 32 60 2.00 8.00 0.008 3.09 116 253.2 59 80 32 100 1.00 8.00 0.008 3.09 52.4 289.3 91 123 40 50 2.00 8.00 0.008 1.98 80.4 296.9 73 99 40 60 3.00 9.00 0.008 1.98 162 333.2 99 135 48 50 2.00 8.00 0.008 1.37 73.1 359.6 104 140 48 60 3.00 9.00 0.008 1.37 155 407.9 138 188 1. This is based on simulation 4.2.2 FRO-192M specifications Table 25. FRO-192M specifications Symbol Description Min ffro192m FRO-192M frequency (nominal) -- ffro192m Frequency deviation (Ta = 0 °C -- 85 °C) ffro192m Frequency deviation (Ta = 40 -- °C 125 °C) ffro192m Frequency deviation (Ta = 40 -- °C 125 °C) tstartup Start-up time -- tstartup Start-up time -- fos jitper jitper jitcyc Ifro192m_vdd1p8 Ifro192m_vddlv Frequency overshoot during -- startup Period jitter RMS 1 -- Accumulated jitter over 10K -- cycles 1 Cycle to cycle jitter 1 -- Current consumption for vdd1p8 -- Current consumption for vddlv -- 1. Tested at 96 MHz Typ 192 -- -- -- 2 -- -- 70 800 100 70 35 Max -- ±1.5 ±3 ±0.25 -- 20 2 -- -- -- -- -- Unit MHz % % % s s % ps ps ps A A Condition -- Open loop Open loop Closed loop (using accurate clock source as reference) Oscillation time with initial accuracy of -20 % to +2 % of enable signal assertion Oscillation time within +/- 2 % from enable signal assertion -- -- -- -- -- -- Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 31 / 88 NXP Semiconductors 4.2.3 FRO-12M specifications Table 26. FRO-12M specifications Symbol Description ffro12m FRO-12M frequency (nominal) ffro12m Frequency deviation ffro12m Frequency deviation Min -- -- -- tstartup fos Ifro12m Start-up time -- Frequency overshoot during -- startup Current consumption -- Typ 12 -- -- 5 10 7 Peripheral operating requirements and behaviors Max -- ±3 ±0.6 -- 20 Unit MHz % % s % Condition -- open loop closed loop (using accurate clock source as reference) -- -- -- µA -- 4.2.4 FRO16K specifications Table 27. FRO16K specifications Symbol Description ffro16k FRO16K frequency (nominal) ffro16k Frequency deviation over 40 °C to 125 °C Ta TRIMstep Trimming step tstartup Start-up time Ifro16k Current consumption Min -- -- -- -- -- Typ 16.384 -- 1.5 310 50 Max -- ±6 -- -- -- Unit kHz % % s nA Condition -- open loop -- -- -- 4.3 Memories and memory interfaces 4.3.1 Flash electrical specifications This section describes the electrical characteristics of the flash memory module. 4.3.1.1 Timing specifications The following command times assume a flash bus clock frequency of 24 MHz. Command times will be increased by up to 10 s at 24 MHz if the module is exiting Sleep mode when the command is launched. The time to abort a command is not included in the following table. 4.3.1.1.1 Flash command time specifications Table 28. Flash command time specifications Symbol Description Min Typ Max Unit Condition trd1all256k Read 1s All execution time (256 -- -- 1700 µs -- KB) trd1all512k Read 1s All execution time (512 -- -- 3200 µs -- KB) Table continues on the next page... Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 32 / 88 NXP Semiconductors Peripheral operating requirements and behaviors Table 28. Flash command time specifications (continued) Symbol Description Min Typ Max Unit Condition trd1all1MB Read 1s All execution time (1 -- -- 6200 µs -- MB) trd1blk256k Read 1s Block execution time -- -- 1500 µs -- (256 KB) trd1blk512k Read 1s Block execution time -- -- 3050 µs -- (512KB) trd1blk1MB Read 1s Block execution time -- -- 6000 µs -- (1MB) trd1scr Read 1s Sector execution time -- -- 50 µs -- (8 KB) 1 trd1pg Read 1s Page execution time -- -- 4.4 µs -- (128 B) 1 trd1pglv Read 1s Page at low voltage -- -- 5.8 µs -- execution time (128 B) trd1phr Read 1s Phrase execution time -- -- 3.8 µs -- (16B) 1 trd1phrlv trdmisr8k Read 1s Phrase at low voltage -- -- 4.8 µs -- execution time (16 B) Read into MISR (8 KB) 1 -- -- 50 µs -- trdmisr256k Read into MISR (256 KB) -- -- 1500 µs -- trdmisr512k trdmisr1M Read into MISR (512 KB) -- -- 3050 µs -- Read into MISR (1 MB) 1 -- -- 6000 µs -- trd1iscr Read 1s IFR Sector execution -- -- 50 µs -- time (8 KB) 1 trd1ipg Read 1s IFR Page execution -- -- 4.4 µs -- time (128 B) 1 trd1ipglv Read 1s IFR Page at low -- -- 5.8 µs -- voltage execution time (128 B) trd1iphr Read 1s IFR Phrase execution -- -- 3.8 µs -- time (16 B) 1 trd1iphrlv Read 1s IFR Phrase at low -- -- 4.8 µs -- voltage execution time (16 B) trdimisr8k Read IFR into MISR (8 KB) 1 -- -- 50 µs -- trdimisrk32k Read IFR into MISR (32 KB) 1 -- -- 190 µs -- tpgmpg_initial Program Page execution time at -- 450 600 µs -- < 1k cycles (128 B) 2 tpgmpg_lifetime Program Page execution time at -- 450 750 µs -- < 1k cycles (128 B) Table continues on the next page... Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 33 / 88 NXP Semiconductors Peripheral operating requirements and behaviors Table 28. Flash command time specifications (continued) Symbol Description Min Typ Max Unit Condition tpgmphr_initial Program Phrase execution time -- 135 180 µs -- at > 1k cycles (16 B) 2 tpgmphr_lifetime Program Phrase execution time -- 135 225 µs -- at > 1k cycles (16 B) tersall256k Erase All execution time (256 KB) -- -- 800 ms -- tersall512k Erase All execution time (512 KB) -- -- 1500 ms -- tersall1M Erase All execution time (1 MB) -- -- 2800 ms -- tmasers256k Mass Erase execution time ( via -- -- 800 ms -- sideband) (256 KB) tmasers512k Mass Erase execution time ( via -- -- 1500 ms -- sideband) (512 KB) tmasers1M Mass Erase execution time ( via -- -- 2800 ms -- sideband) (1 MB) terrscr Erase Sector execution time (8 -- 2 KB) 2 22 ms -- tersall128k Erase All execution time (128 -- -- 400 ms -- KB) 1. Time to abort the command may significantly impact the time to execute the command. 2. Measured from the time FSTAT[PERDY] is cleared. 4.3.1.2 Flash high voltage current behavior Table 29. Flash high voltage current behavior Symbol IDD_IO_PGM IDD_IO_ERS Description Min Typ Max Unit Condition Average current adder to -- -- 6 VDD during flash programming operation 1 mA -- Average current adder to VDD -- -- 4 during flash erase operation 1 mA -- 1. See the Power Management chapter in the reference manual for the specific VDD voltage supply powering the flash array. 4.3.1.3 Flash reliability specifications. Table 30. Flash reliability specifications. Symbol Description Min Typ Max tnvmretp10k nnvmcycscr Data retention after up to 10 K cycles Sector cycling endurance 1 10 10 K 50 -- 500 K -- Table continues on the next page... Unit years cycles Condition Program Flash Program Flash Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 34 / 88 NXP Semiconductors Peripheral operating requirements and behaviors Table 30. Flash reliability specifications. (continued) Symbol Tnvmretp1k Tnvmretp100k Description Min Data retention after up to 1 K 20 cycles Data retention after up to 100 K 5 cycles Typ 100 50 Max -- -- Unit years years Condition Program Flash Program Flash Nnvmcyc256k Sector cycling endurance for 100 K 500 K -- 256 KB 2 Cycles Program Flash 1. Sector cycling endurance represents the number of Program/Erase cycles on a single sector at -40°C Tj 125°C. 2. For devices with a single flash block, sectors must be located within the last 256 KB of the flash main memory. For devices with two flash blocks, sectors must be located within the last 256 KB of each flash main memory but must not total more than 256 KB per device. NOTE Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25°C use profile. 4.4 Analog 4.4.1 ADC electrical specifications ADC operating conditions apply when the ADC is used in differential mode. All other ADC channels meet the 12-bit single-ended accuracy specifications. 4.4.1.1 ADC operating conditions Table 31. ADC operating conditions Symbol Description Min Typ Max Unit VDDAD Supply voltage 1.71 -- 3.6 V VSSAD VDD VSS VREFH VREFL VADIN Ground voltage -- 1 -- 1 Reference Voltage High 2 Reference Voltage Low 3 Input Voltage 3,4,5 -0.1 0 0.1 V -0.1 0 0.1 V 0.1 0 0.1 V 0.99 VDDAD VDDAD V VSSAD VSSAD VSSAD V VREFL -- VREFH V FADCK ADC conversion clock frequency 6 -- 24 MHz FADCK ADC conversion clock frequency 6 -- 60 MHz FADCK ADC conversion clock frequency 6 -- 64 MHz RAS Analog source resistance -- -- 5 k (external) 6 Table continues on the next page... Condition -- -- -- -- -- -- -- Low-power mode, PWRSEL=0 Normal Mode, 16b, PWRSEL=1 Normal Mode, 12b , PWRSEL=1 -- Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 35 / 88 NXP Semiconductors Peripheral operating requirements and behaviors Table 31. ADC operating conditions (continued) Symbol Description Min Typ Max Unit Condition RADIN Input Resistance ADC channels -- -- 1.65 k VDDAD 1.71 V 7:0 7,8 RADIN Input Resistance ADC channels -- -- 1.525 k VDDAD 2.1 V 7:0 7,8 RADIN Input Resistance ADC channels -- 7:0 7,8 0.925 1.35 k VDDAD 2.5 V CADIN Input Capacitance -- 1.92 2.4 pF -- 1. DC potential difference 2. Minimum VDDAD/VREFH is 2.4 V in high-speed mode 3. For devices that do not have a dedicated VREFL and VSS_ANA pins, VREFL and VSS_ANA are tied to VSS internally. 4. ADC selected inputs and unselected dedicated inputs must not exceed VDD_ANA during an ADC conversion. Unselected muxed inputs may exceed VDD_ANA but must not exceed the IO supply associated with the inputs (VDD) when a conversion is in progress. If an ADC input may exceed these levels, then a minimum of 1 K series resistance must be used between the source and the ADC input pin. 5. If VREFH is less than VDD_ANA, then voltage inputs greater than VREFH but less than VDD_ANA are allowed but result in a full-scale conversion result 6. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. 7. If the input come through a mux in the IO pad, add the IO Mux Resistance Adder value to the resistance for the channel type 8. There are several types of ADC inputs. To see which channels correspond to which type of ADC inputs, see channel index map in reference manual 4.4.1.2 I/O mux resistance table Table 32. I/O mux resistance table Symbol Description RIOMUX I/O MUX Resistance RIOMUX I/O MUX Resistance RIOMUX I/O MUX Resistance Min -- -- -- Typ -- -- 0.35 Max 5.35 1 0.66 Unit k k k Condition VDD 1.71v VDD 2.1v VDD 2.5 v Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 36 / 88 NXP Semiconductors Peripheral operating requirements and behaviors Figure 12. ADC input impedance equivalency diagram 4.4.1.3 ADC electrical characteristics Table 33. ADC electrical characteristics Symbol -- Description Supply current 1 Min -- Typ 7 Max -- IDDAD IDDAD Supply current 1 Supply current 1 -- 60 -- -- 200 -- IDDAD Supply current 1 -- 230 -- IDDAD Supply current 1 -- 550 -- Table continues on the next page... Unit -- µA µA µA µA Condition PWREN=0, Conversions triggered at 10 kS/s PWREN=1, No Conversions Low-power mode, 6 MHz Clock, PWRSEL=0 Low-power mode, 24 MHz clock, PWRSEL=0 Normal Mode, 60 MHz, PWRSEL=1 Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 37 / 88 NXP Semiconductors Peripheral operating requirements and behaviors Table 33. ADC electrical characteristics (continued) Symbol Description IDDAD Supply cuurent Min -- Typ 625 Max -- IDDTS CSMP Fconv Fconv TSMP_REQ Temp Sensor Supply Current -- 50 ADC Sample cycles 2 3.5 -- ADC conversion rate 3 -- -- ADC conversion rate 4 -- -- Required Sample Time 5 -- -- -- 131.5 4.0 3.0 -- TSMP TSMP TSMP TSMPINT DNL INL ZSE FSE TUE ENOB16 ENOB16 ENOB16 Sample Time 6 145.8 Sample Time 7 58.3 Sample Time 8 54.7 Internal channel sample 2.0 time inputs 9 Differential non-linearity 10,11 -- Integral non-linearity 10,11 -- Zero-scale error (V_ADIN = V_ -- REFL) 10,11 Full-scale error (V_ADIN = V_ -- REFH) 10,11 Total Unadjusted Error 10,11 -- Effective number of bits, 16b -- Mode, 1 kHz input 11,12 TSMP_R -- EQ TSMP_R -- EQ TSMP_R -- EQ -- -- ±1 -- ±1 -- ±1 -- ±2 -- ±3 -- 14.1 -- Effective number of bits, 16b -- Mode, 1 kHz input 11,12 13.2 -- Effective number of bits, 16b -- Mode, 1 kHz input 12.6 -- Table continues on the next page... Unit µA µA cycles MS/s MS/s ns ns Condition High Speed Mode, 60 MHz Clock, PWRSEL=1, HS=1 Temperature Sensor Adder Low-power mode and High speed mode 12b mode, (HS=1) 16b mode, (HS=1) Use equation based on RAS, RIOMUX, RADIN, CADIN, RAS, CAS, CP and desired accuracy (B) Low-power mode ns High-speed 16b mode ns High-speed 12b mode µs -- 12b LSB -- 12b LSB -- 12b LSB -- 12b LSB -- 12b LSB -- bits 23.4 kS/s (FADCK = 60 MHz, HS =1, AVGS=0111) bits 187 kS/s (FADCK = 60 MHz, HS=1, AVGS =0100) bits 750 kS/s (FADCK = 60 MHz, HS=1, AVGS =0010) Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 38 / 88 NXP Semiconductors Peripheral operating requirements and behaviors Table 33. ADC electrical characteristics (continued) Symbol ENOB16 ENOB12 ENOB12 SNDR16 Description Effective number of bits, 16b Mode, 1 kHz input Min -- Effective number of bits, 12b -- Mode, 1 kHz input 11,12 Effective number of bits, 12b -- Mode, 1 kHz input 11,12 Signal-to-noise plus distortion, -- 16b Mode, 1 kHz input 11,12 Typ 12.0 11.5 11.0 86.6 Max -- -- -- -- Unit bits bits bits dB Condition 3.0 MS/s (FADCK = 60 MHz, HS=1, AVGS =0000) 1.0 MS/s (FADCK = 64 MHz, HS =1, AVGS=0010) 4.0 MS/s (FADCK = 64 MHz, HS =1,AVGS=0000) 23.4 kS/s (FADCK=60 MHz, HS=1, AVGS=0111) SNDR16 Signal-to-noise plus distortion, -- 16b Mode, 1 kHz input 11,12 81.2 -- dB 187.5 kS/s (FADCK=60 MHz, HS=1, AVGS=0100) SNDR16 SNDR16 SNDR12 SNDR12 SFDR Signal-to-noise plus distortion, -- 16b Mode, 1 kHz input 11,12 Signal-to-noise plus distortion, -- 16b Mode, 1 kHz input Signal-to-noise plus distortion, -- 12b Mode, 1 kHz input 11,12 Signal-to-noise plus distortion, -- 12b Mode, 1 kHz input 11,12 Spurious free dynamic -- range 11,12 77.6 -- 74 -- 71.0 -- 68.0 -- 88.0 -- dB 750 kS/s (FADCK=60MHz, HS=1, AVGS=0010) dB 3.0 MS/s (FADCK=60 MHz, HS=1, AVGS=0000) dB 1.0 MS/s (FADCK=64 MHz, HS=1, AVGS=0010) dB 4.0 MS/s (FADCK=64 MHz, HS=1, AVGS=0000) dB 12b/16b Mode, 1kHz input, AVGS =0010 SFDR Tsu E_TS E_TS A B Spurious free dynamic -- range 11,12 Start-up time 13 5 Temperature sensor error 14 -- Temperature sensor error 14 -- Temp Sensor Slope Constant 15 -- Temp Sensor Offset Constant 15 -- Temp Sensor Bandgap -- Constant 15 82.0 -- -- -- ±1 ±3 ±2 ±4 738 -- 287.5 -- 10.06 -- dB 12b/16b Mode, 1kHz input, AVGS =0000 µs -- °C Tj=-40 to 105 °C °C Tj=-40 to 125 °C °C -- °C -- °C -- 1. The ADC supply current depends on the ADC conversion clock speed, conversion rate, and power mode. Typical value show is at 6 MHz, 24 MHz, and 48 MHz. For lowest power operation, PWRSEL should be set to 00. 2. Must meet minimum TSMP requirement 3. fADCK=64 MHz (HS Mode) Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 39 / 88 NXP Semiconductors Peripheral operating requirements and behaviors 4. fADCK=60 MHz (HS Mode) 5. Required sample time is dictated by external components RAS, CAS, internal components RADIN, CADIN, CP, and desired sample accuracy in bits (B). Calculate it with formula: TSMP_REQ = B*In(2)*[RAS*(CAS+CP)+ (RAS + RIOMUX + RADIN)* CADIN(typ). RIOMUX=0 unless the ADC input channel goes through an analog mux in the IO" 6. Min based on 3.5 cycles 7. Min based on 3.5 cycles @ 60 MHz 8. Min based on 3.5 cycles @ 64 MHz 9. Internal channel inputs are those that do not come from external source (temperature sensor, bandgap). 10. 1 LSB = (VREFH - VREFL)/2N (N=14 bits), for 16- bit specifications, multiply by 4. 11. All accuracy numbers assume that the ADC is calibrated with VREFH=VDD_ANA and using a high- speed- dedicated input channel. Typical values assume VDD_ANA = 3.0 V, Temp = 25 °C, fADCK = 24 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 12. Dynamic results assume Fin=1 kHz sinewave, no averaging unless otherwise specified 13. Delay required if PWREN=0 14. The temperature sensor can be calibrated to a +/- 1 % precision after board assembly by using a 3-temperature calibration flow with accurate ± 0.15 % temperature chamber 15. T(°C) = A*[°(Vbe8 - Vbe1)/(Vbe8 + (Vbe8 - Vbe1))] - B where Vbe1 is the first value stored to FIFO as a result of the temperature sensor channel conversion, Vbe8 is the second value stored to FIFO as a result of the temperature sensor channel conversion, A is the slope factor, B is the offset factor, is the bandgap coefficient Set the power-up delay (PUDLY) according to the ADC start-up time if PWREN=0. Ilkg = leakage current (Refer to pin leakage specification in the voltage and current operating behaviours of packaged device) 14.5 ENOB 14 Typical ENOB vs AVGS (16b Mode) 13.5 13 12.5 12 0000 0001 0010 Figure 13. ENOB vs ADC (16b HS Mode) 0011 0100 0101 0110 0111 AVGS aaa-052761 Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 40 / 88 NXP Semiconductors 14.5 ENOB 14 Peripheral operating requirements and behaviors Typical ENOB vs ADC sample rate (16b HS=1) 13.5 13 12.5 12 0.012 0.023 Figure 14. ENOB vs ADC sample rate 0.047 0.094 0.188 0.375 0.750 1.500 3.000 Fs (MS/s) aaa-052762 4.4.2 12-bit DAC electrical characteristics 4.4.2.1 12-bit DAC operating requirements Table 34. 12-bit DAC operating requirements Symbol VDD_ANA VDACR CL IL DAC_c_rate Description Supply voltage Reference Voltage 1 Output load capacitance 2 Output load current 3 DAC conversion rate Min Typ Max Unit Condition 1.71 -- 3.6 V -- 0.97 -- VDD_AN V -- A -- 50 100 pF -- -1 -- 1 mA -- -- -- 1 MSPS -- 1. The DAC reference can be selected to be VDD_ANA or VREFH or VREFO PAD, keep VDD_ANA be the highest voltage. 2. A small load capacitance (50 pF) can improve the bandwidth performance of the DAC. 3. Sink or source current availability 4.4.2.2 12-bit DAC operating behaviors Table 35. 12-bit DAC operating behaviors Symbol Description Min Typ Max IDD_DAC Supply Current -- 300 500 IDD_DAC Supply Current -- 100 150 IDD_DAC Supply Current -- 10 -- tDAC Full-scale settling time (0x100 to -- 0xF00) 1 2.5 3 Table continues on the next page... Unit µA µA nA µs Condition Normal mode Low-power mode Disabled Normal mode Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 41 / 88 NXP Semiconductors Peripheral operating requirements and behaviors Table 35. 12-bit DAC operating behaviors (continued) Symbol Description Min Typ Max Unit Condition tDAC Full-scale settling time (0x100 to -- 5 6 µs Low-power mode 0xF00) 1 tccDAC Code-to-code settling time -- (0xBF8 to 0xC08) 1 0.7 1 µs -- Vdacoutl DAC output voltage range low -- -- 100 mV -- -- high-speed mode, no load, DAC set to 0x000 Vdacouth INL DNL EOFFSET EG EG DAC output voltage range high -- high-speed mode, no load, DAC set to 0xFFF Integral non-linearity error 2 Differential non-linearity error 3 Offset error 4 Gain error 4 Gain error 4 VDACR100 -- -- -- -- -- -- -- -- ± 0.4 ± 0.3 ± 0.1 VDACR mV -- ±3 ±1 ± 0.8 ± 0.6 ± 0.3 LSB LSB %FSR %FSR %FSR -- -- -- VDACR < 2.1 V VDACR > 2.1 V PSRR Power supply rejection ratio, -- 70 -- dB -- VDD_ANA 2.4 V TCO Temperature coefficient offset -- -- -- µV/C -- voltage at middle scale 5 TEO Temperature coefficient offset -- 30 -- µV/C -- error TGE Temperature coefficient gain -- 10 -- PPM/C -- error ROP Output resistance (load = 10 -- 200 -- -- k) SR Slew rate 100 h ->F00 h or F00 -- 3.6 -- V/µs -- h ->100 h SR Slew rate 100 h ->F00 h or F00 -- 0.5 -- V/µs -- h ->100 h CT DAC to DAC crosstalk 6 -- -- -80 dB -- TPU Power-up time -- 2.5 -- µs -- 1. Settling within ±1 LSB measured with a 47 pF load. 2. The INL is measured for 0 + 100 mV to VDACR -100 mV 3. The DNL is measured for 0 + 100 mV to VDACR -100 mV 4. Calculated by a best fit curve from VSS_ANA + 100 mV to VDACR - 100 mV 5. VDD_ANA = 3.0 V, reference select set for VDD_ANA (DACx_CO:DACRFS = 1), high- power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device. 6. If two DACs are used and share same VREFH Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 42 / 88 NXP Semiconductors Peripheral operating requirements and behaviors 8 6 4 2 DAC12 INL (LSB) 0 -2 -4 -6 -8 0 500 1000 1500 2000 2500 3000 3500 4000 Digital Code Figure 15. Typical INL error vs. digital code Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 43 / 88 NXP Semiconductors Peripheral operating requirements and behaviors 1.499 1.4985 DAC12 Mid Level Code Voltage 1.498 1.4975 1.497 1.4965 1.496 -40 25 55 85 105 125 Temperature °C Figure 16. Offset at half scale vs. temperature 4.4.3 Comparator and 8-bit DAC electrical specifications Table 36. Comparator and 8-bit DAC electrical specifications Symbol Description Min Typ VDD Supply voltage 1.71 -- VREFH 8-bit DAC reference voltage 0.97 -- high IDD_CMP Supply current -- 200 Max 3.6 VDD -- IDD_CMP Supply current -- 10 -- IDD_CMP Supply current -- 400 -- VAIN VAIO Analog input voltage VSS -- VDD Analog input offset voltage -- -- 20 Table continues on the next page... Unit V V A A nA V mV Condition -- -- High speed mode (EN=1, HPMD=1) Normal mode (EN=1, HPMD=0, NPMD=0) Low-power mode (EN=1, HPMD=0, NPMD=1) -- High speed mode Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 44 / 88 NXP Semiconductors Peripheral operating requirements and behaviors Table 36. Comparator and 8-bit DAC electrical specifications (continued) Symbol VAIO VAIO VH VH VH VH VCMPOh VCMPOl tD tD tD tD tinit IDAC8b IDAC8b INL DNL Description Min Typ Analog input offset voltage -- -- Analog input offset voltage -- -- Analog comparator hysteresis 1 -- 0 Analog comparator hysteresis 1 -- 10 Analog comparator hysteresis 1 -- 20 Analog comparator hysteresis 1 -- 30 Output high VDD - 0. -- 2 Output low -- -- Propagation delay 2 -- -- Propagation delay 2 -- -- Propagation delay 2 -- -- Propagation delay 2 -- -- Analog comparator initialization -- -- delay 3 8-bit DAC current adder (enabled) -- 10 8-bit DAC current consumption -- 1 8-bit DAC integral non-linearity 4 -1 -- 8-bit DAC differential non- -1 -- linearity Max 20 40 -- -- -- -- -- 0.2 25 50 600 5 40 -- -- +1.0 +1.0 Unit mV mV mV mV mV mV V V ns ns ns s s A µA LSB LSB Condition Normal mode Low-power mode CR0[HYSTCTR] = 00 CR0[HYSTCTR] = 01 CR0[HYSTCTR] = 10 CR0[HYSTCTR] = 11 -- -- High speed mode, 100 mV overdrive, power > 1.71V High speed mode, 30 mV overdrive, power > 1.71V Normal mode, 30 mV overdrive, power > 1. 71V Low-power mode, 30 mV overdrive, power > 1.71V -- High power mode (EN=1, PMODE=1) Low power mode (EN=1, PMODE=0) Low/High power mode, supply power > 1.71V Low/High power mode, power > 1.71V 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD_ANA0.6 V. 2. Overdrive does not include input offset voltage or hysteresis. The propagation delay is defined as the time delay between the change of the voltage on input pin and the output change of the comparator analog part 3. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 4. 1 LSB = Vreference/256 Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 45 / 88 NXP Semiconductors Peripheral operating requirements and behaviors Figure 17. Typical hysteresis vs. Vin level (VDD = 3.3 V, HPMD = 1) Figure 18. Typical hysteresis vs. Vin level (VDD = 3.3 V, HPMD = 0, NPMD = 0) Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 46 / 88 NXP Semiconductors Peripheral operating requirements and behaviors Figure 19. Typical hysteresis vs Vin level (VDD =3.3 V, HPMD = 0, NPMD = 1) 4.4.4 OpAmp electrical specifications Table 37. OpAmp electrical specifications Symbol Description Min Typ Max Unit Condition VDD_ANA Operating Voltage 1.71 3 3.6 V -- ISUPPLY1 Supply Current (IOUT=0 mA -- high-speed mode) 450 -- µA -- ISUPPLY2 Supply Current (IOUT=0 mA -- high-speed mode) 120 -- µA -- VOS Input Offset Voltage -5 -- 5 mV -- VOS Input Offset Voltage Temperature Coefficient -- 5 -- µV/C -- VCML Input Common Mode Voltage 0 -- -- V -- Low VCMH Input Common Mode Voltage -- -- VDD_AN V -- High A PSRR Power Supply Rejection Ration -- 80 -- dB -- @ DC SRh Slew Rate positive (VIN=1 V, -- 6 -- V/µs -- high- speed mode) Table continues on the next page... Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 47 / 88 NXP Semiconductors Peripheral operating requirements and behaviors Table 37. OpAmp electrical specifications (continued) Symbol Description Min SRl Slew Rate positive (VIN=1 V, -- low- speed mode) GBWh Unity Gain Bandwidth (high- -- speed mode) GBWl Unity Gain Bandwidth (low- -- speed mode) AV DC Open Loop Voltage Gain -- CL Load Capacitance Driving -- Capability RL Load resistance (low-power 3 K mode) PM Phase Margin -- Vn Voltage noise density @1 kHz -- (high-speed mode) Vo Output swing 0.2 Tsettle Cin T_start Settling time (high-speed mode -- invert gain=4 input=10 mV with +/-730 V settling accuracy) Input Capacitance -- Startup Time high-speed -- mode buffer with input 1 V) Typ 1 6 1 110 -- -- 60 100 -- 1 5 5 Max Unit -- V/µs -- -- MHz -- -- MHz -- -- dB -- 20 pF -- -- -- -- deg -- -- nv/sqrtHz -- VDD_AN V -- A-0.2 -- µs -- -- pF -- -- µs -- Condition 4.4.5 PGA electrical specifications NOTE Gain is PGA mode gain and gain is 2.4.8 Table 38. PGA electrical specifications Symbol Description Error gain PGA gain accuracy -- PGA bandwidth -- PGA bandwidth -- PGA bandwidth -- PGA bandwidth Min -- -- -- -- -- Typ Max ±1 -- 6/ -- (gain+1) 32/ -- (gain+1) 6/ -- (gain+1) 32/ -- (gain+1) Unit % MHz MHz MHz MHz Condition -- Inverting mode, gain = 1, 2, 4 Inverting mode, gain = 8, 16, 33, 64 Non-inverting mode, gain = 1, 2, 4 Non-inverting mode, gain = 8, 16, 33, 64 Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 48 / 88 NXP Semiconductors 4.5 Timers See General switching specifications. Peripheral operating requirements and behaviors 4.6 Communication Interfaces 4.6.1 LPUART The Low Power Universal Asynchronous Receiver / Transmitter (LPUART) provides an asynchronous serial bus with master and slave operations, can reach to 24Mbps maximum transfer rate, based on characterization but not covered by test limits in production. See General switching specifications. 4.6.2 LPSPI switching specifications The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic SPI timing modes. 4.6.2.1 LPSPI master mode timing Table 39. LPSPI master mode timing Symbol LP1 Description Frequency of operation 1 Min -- Typ -- Max -- LP1 LPSPI0 ~ LPSPI1 medium -- -- 48 speed pad LP1 LPSPI0 ~ LPSPI1 slow speed -- -- 24 pad LP1 LPSPI0 ~ LPSPI1 medium -- -- 24 speed pad LP1 LPSPI0 ~ LPSPI1 slow speed -- -- 24 pad LP2 SPSCK period 1000/LP1 -- -- LP3 Enable lead time 2 1/2 -- -- LP4 Enable lag time 2 1/2 -- -- LP5 Clock (SPSCK) high or low time tSCK/2-3 -- tSCK/2 LP6 Data setup time (inputs) -- -- -- LP6 LPSPI0 ~ LPSPI1 medium 7.2 -- -- speed pad LP6 LPSPI0 ~ LPSPI1 slow speed 14.4 -- -- pad LP6 LPSPI0 ~ LPSPI1 medium 14.4 -- -- speed pad LP6 LPSPI0 ~ LPSPI1 slow speed 14.4 -- -- pad LP7 Data hold time (inputs) -- -- -- Table continues on the next page... Unit MHz MHz MHz MHz MHz ns tperiph tperiph ns ns ns ns ns ns ns Condition -- Master in SD mode Master in SD mode Master in MD mode Master in MD mode -- -- -- -- -- Master in SD mode Master in SD mode Master in MD mode Master in MD mode -- Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 49 / 88 NXP Semiconductors Peripheral operating requirements and behaviors Table 39. LPSPI master mode timing (continued) Symbol Description LP7 LPSPI0 ~ LPSPI1 medium speed pad LP7 LPSPI0 ~ LPSPI1 slow speed pad LP7 LPSPI0 ~ LPSPI1 medium speed pad LP7 LPSPI0 ~ LPSPI1 slow speed pad LP8 Data valid (after SPSCK edge) LP8 LPSPI0 ~ LPSPI1 medium speed pad LP8 LPSPI0 ~ LPSPI1 slow speed pad LP8 LPSPI0 ~ LPSPI1 medium speed pad LP8 LPSPI0 ~ LPSPI1 slow speed pad LP9 Data hold time (outputs) LP9 LPSPI0 ~ LPSPI1 medium speed pad LP9 LPSPI0 ~ LPSPI1 slow speed pad LP9 LPSPI0 ~ LPSPI1 medium speed pad LP9 LPSPI0 ~ LPSPI1 slow speed pad Min 0 0 0 0 -- -- -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- 7.2 14.4 14.4 14.4 -- -1 -1 -1 -1 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Condition Master in SD mode Master in SD mode Master in MD mode Master in MD mode -- Master in SD mode Master in SD mode Master in MD mode Master in MD mode -- Master in SD mode Master in SD mode Master in MD mode Master in MD mode 1. The frequency of operation is also limited to a minimum of fperiph/2048 and a max of fperiph/2, where fperiph is the LPSPI peripheral functional clock. 2. tperiph = 1/fperiph Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 50 / 88 NXP Semiconductors Peripheral operating requirements and behaviors PCS (OUTPUT) SCK (CPOL=0) (OUTPUT) LP3 LP2 LP5 LP5 SCK (CPOL=1) (OUTPUT) SIN (INPUT) SOUT (OUTPUT) LP6 LP7 MSB IN2 MSB OUT2 BIT 6 . . . 1 LP8 BIT 6 . . . 1 1. If configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 20. LPSPI master mode timing (CPHA = 0) LP4 LSB IN LP9 LSB OUT PCS (OUTPUT) SCK (CPOL=0) (OUTPUT) SCK (CPOL=1) (OUTPUT) SIN (INPUT) LP2 LP3 LP5 LP5 LP6 LP7 MSB IN2 LP8 SOUT (OUTPUT) PORT DATA MASTER MSB OUT2 BIT 6 . . . 1 LP9 BIT 6 . . . 1 1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 21. LPSPI master mode timing (CPHA = 1) LP4 LSB IN MASTER LSB OUT PORT DATA 4.6.2.2 LPSPI slave mode timing Table 40. LPSPI slave mode timing Symbol Description Min Typ Max LP1 Frequency of operation in OD -- -- -- mode 1 LP1 lpspi0~lpspi1 medium speed -- -- 24 pad 1 Table continues on the next page... Unit -- MHz Condition -- Slave Tx in SD mode Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 51 / 88 NXP Semiconductors Peripheral operating requirements and behaviors Table 40. LPSPI slave mode timing (continued) Symbol LP1 Description Min lpspi0~lpspi1 slow speed pad 1 -- Typ -- Max 12 Unit MHz LP1 lpspi0~lpspi1 medium speed -- -- 48 MHz pad 1 LP1 lpspi0~lpspi1 slow speed pad -- -- 24 MHz LP1 lpspi0~lpspi1 medium speed -- -- 12 MHz pad LP1 lpspi0~lpspi1 slow speed pad -- -- 12 MHz LP1 lpspi0~lpspi1 medium speed -- -- 12 MHz pad LP1 lpspi0~lpspi1 slow speed pad -- -- 12 MHz LP2 SPSCK period 4 x -- tperiph 2048 x ns tperiph LP3 Enable lead time 2 1 -- -- tperiph LP4 Enable lag time 2 1 -- -- tperiph LP5 Clock (SPSCK) high or low time tSPSCK/ -- tSPSCK/ ns 2 - 5 2 LP6 Data setup time (inputs) -- -- -- ns LP6 lpspi0~lpspi1 medium speed 3.6 -- -- ns pad LP6 lpspi0~lpspi1 slow speed pad 7.2 -- -- ns LP6 lpspi0~lpspi1 medium speed 14.4 -- -- ns pad LP6 lpspi0~lpspi1 slow speed pad 14.4 -- -- ns LP7 Data hold time (inputs) -- -- -- ns LP7 lpspi0~lpspi1 medium speed 0 -- -- ns pad LP7 lpspi0~lpspi1 slow speed pad 0 -- -- ns LP7 lpspi0~lpspi1 medium speed 0 -- -- ns pad LP7 lpspi0~lpspi1 slow speed pad 0 -- -- ns LP8 Slave access time 2,3 -- -- tperiph ns LP9 Slave MISO disable time 2,4 -- -- tperiph ns LP10 Data valid (after SPSCK edge) -- -- -- ns LP10 lpspi0~lpspi1 medium speed -- -- 15.6 ns pad LP10 lpspi0~lpspi1 slow speed pad -- -- 31.2 ns Table continues on the next page... Condition Slave Tx in SD mode Slave Rx in SD mode Slave Rx in SD mode Slave Tx in MD mode Slave Tx in MD mode Slave Rx in MD mode Slave Rx in MD mode -- -- -- -- -- Slave Rx in SD mode Slave Rx in SD mode Slave Rx in MD mode Slave Rx in MD mode -- Slave Rx in SD mode Slave Rx in SD mode Slave Rx in MD mode Slave Rx in MD mode -- -- -- Slave Tx in SD mode Slave Tx in SD mode Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 52 / 88 NXP Semiconductors Peripheral operating requirements and behaviors Table 40. LPSPI slave mode timing (continued) Symbol Description LP10 lpspi0~lpspi1 medium speed pad LP10 lpspi0~lpspi1 slow speed pad LP11 Data hold time (outputs) LP11 lpspi0~lpspi1 medium speed pad LP11 lpspi0~lpspi1 slow speed pad LP11 lpspi0~lpspi1 medium speed pad LP11 lpspi0~lpspi1 slow speed pad Min -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- Max 31.2 31.2 -- -1 -1 -1 -1 Unit ns ns ns ns ns ns ns Condition Slave Tx in MD mode Slave Tx in MD mode -- Slave Tx in SD mode Slave Tx in SD mode Slave Tx in MD mode Slave Tx in MD mode 1. The frequency of operation is also limited to a minimum of fperiph/2048 and a max of fperiph/4, where fperiph is the LPSPI peripheral functional clock. 2. tperiph = 1/fperiph 3. Time to data active from high-impedance state 4. Hold time to high-impedance state PCS (INPUT) SCK (CPOL=0) (INPUT) SCK (CPOL=1) (INPUT) LP2 LP3 LP5 LP5 LP8 SOUT (OUTPUT) see note SLAVE MSB LP6 LP7 SIN (INPUT) MSB IN NOTE: Not defined LP10 BIT 6 . . . 1 BIT 6 . . . 1 Figure 22. LPSPI slave mode timing (CPHA = 0) LP4 LP11 LP11 SLAVE LSB OUT LP9 SEE NOTE LSB IN Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 53 / 88 NXP Semiconductors Peripheral operating requirements and behaviors PCS (INPUT) SCK (CPOL=0) (INPUT) SCK (CPOL=1) (INPUT) SOUT (OUTPUT) SIN (INPUT) LP2 LP3 LP5 LP5 see note LP10 SLAVE MSB OUT LP8 LP6 LP7 MSB IN NOTE: Not defined Figure 23. LPSPI slave mode timing (CPHA = 1) LP11 BIT 6 . . . 1 BIT 6 . . . 1 LP4 LP9 SLAVE LSB OUT LSB IN 4.6.3 LPI2C timing Table 41. LPI2C timing Symbol Description Min Typ Max Unit Condition fSCL SCL Clock Frequency in 0 -- 100 kHz -- standard mode fSCL SCL Clock Frequency in fast 0 mode -- 400 kHz -- tHD; STA Hold time (repeated) START 4 condition. After this period, the first clock pulse is generated in standard mode -- -- µs -- tHD; STA Hold time (repeated) START 0.6 -- -- µs -- condition. After this period, the first clock pulse is generated in fast mode tLOW LOW period of the SCL clock in 4.7 -- -- µs -- standard mode tLOW LOW period of the SCL clock in 1.25 -- -- µs -- fast mode tHIGH HIGH period of the SCL clock in 4 standard mode -- -- µs -- tHIGH HIGH period of the SCL clock in 0.6 -- -- µs -- fast mode tSU; STA Set-up time for a repeated 4.7 -- -- µs -- START condition in standard mode Table continues on the next page... Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 54 / 88 NXP Semiconductors Peripheral operating requirements and behaviors Table 41. LPI2C timing (continued) Symbol Description Min Typ Max Unit Condition tSU; STA Set-up time for a repeated 0.6 -- -- µs -- START condition in fast mode tHD; DAT Data hold time for I2C bus 0 devices in standard mode 1,2 -- 3.45 µs -- tHD; DAT Data hold time for I2C bus devic 0 es in fast mode 1,3 -- 0.9 µs -- tSU; DAT Data set-up time in standard 250 -- -- ns -- mode 4 tSU; DAT Data setup time in fast mode 2,5 100A -- -- ns -- tr Rise time of SDA and SCL -- -- 1000 ns -- signals in standard mode 6 tr Rise time of SDA and SCL sign 20 +0. -- 300 ns -- als in fast mode 6 1Cb tf Fall time of SDA and SCL -- -- 300 ns -- signals in standard mode 5 tf Fall time of SDA and SCL signal 20 +0. -- 300 ns -- s in fast mode 5 1Cb tSU; STO Set-up time for STOP condition 4 in standard mode -- -- µs -- tSU; STO Set- 0.6 -- -- µs -- up time for STOP condition in f ast mode tBUF Bus free time between STOP 4.7 -- -- µs -- and START condition in standard mode tBUF Bus free time between STOP an 1.3 -- -- µs -- d START condition in fast mode tSP Pulse width of spikes that must N/A -- N/A ns -- be suppressed by the input filter in standard mode tSP Pulse width of spikes that must 0 -- 50 ns -- be suppressed by the input filter in fast mode 1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL lines. 2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal 3. Input signal Slew = 10 ns and Output Load = 50 pF 4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty. 5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released. Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 55 / 88 NXP Semiconductors 6. Cb = total capacitance of the one bus line in pF. Peripheral operating requirements and behaviors 4.6.4 I2C 1 Mbps timing Table 42. I2C 1 Mbps timing Symbol fSCL tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT Description Min Typ Max Unit Condition SCL Clock Frequency 0 -- 1 MHz -- Hold time (repeated) START 0.26 -- -- µs -- condition. After this period, the first clock pulse is generated. LOW period of the SCL clock 0.5 -- -- µs -- HIGH period of the SCL clock 0.26 -- -- µs -- Set-up time for a repeated 0.26 -- -- µs -- START condition Data hold time for I2C bus 0 devices -- -- µs -- Data set-up time 50 -- -- ns -- tr tf tSU; STO tBUF Rise time of SDA and SCL 20 +0. -- 120 ns -- signals 1 1Cb Fall time of SDA and SCL 20 +0. -- 120 ns -- signals 1 1Cb Set-up time for STOP condition 0.26 -- -- µs -- Bus free time between STOP 0.5 -- -- µs -- and START condition tSP Pulse width of spikes that must 0 -- 50 ns -- be suppressed by the input filter 1. Cb = total capacitance of the one bus line in pF for maximum value SDA tf tLOW tr tSU; DAT tf SCL S HD; STA tHD; DAT tHIGH tSU; STA Figure 24. Timing definition for devices on the I2C bus SR tHD; STA tSP tr tBUF tSU; STO P S Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 56 / 88 NXP Semiconductors Peripheral operating requirements and behaviors 4.6.5 I2C HS mode timing Table 43. I2C HS mode timing Symbol fSCL tHD; STA tLOW tHIGH Description Min Typ Max Unit Condition SCL Clock Frequency 0 -- 3.4 MHz -- Hold time (repeated) START 0.26 -- -- µs -- condition. After this period, the first clock pulse is generated. LOW period of the SCL clock 0.5 -- -- µs -- High period of the SCL clock 0.26 -- -- µs -- tSU; STA tHD; DAT tSU; DAT tr Set-up time for a repeated 0.26 -- -- µs -- START condition Data hold time for I2C bus 0 devices 1 -- -- µs -- Data setup time 34 -- -- ns -- Rise time of SDA and SCL 20 -- 120 ns -- signals 2 +0.1Cb tf tSU; STO tBUF tSP Fall time of SDA and SCL 20 -- 120 ns -- signals 2 +0.1Cb Setup time for STOP condition 0.26 -- -- µs -- Bus free time between STOP 0.5 -- -- µs -- and START condition Pulse width of spikes that must 0 be suppressed by the input filter -- 50 ns -- 1. A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time in maximum value. 2. Cb = total capacitance of the one bus line in pF. The max Cb value is 50 pF. Applicable for maximum value. NOTE Only PTB4/5, PTA18/19, PTC0/1, PTC4/5 pin can support Fast+ (3 MHz) mode. 4.6.6 I3C Push-Pull Timing Parameters for SDR Mode I3C interface is not supported on GPIO-Standard-plus pad type for 5 V operation. Measurements are with maximum output load of 30 pf, input transition of 1 ns. GPIO-Standard-plus pad configured with DSE = 1'b1 and GPIO-Medium pad with DSE = 1'b1 and SRE = 1'b1. SCL, SDA and PUR combination should be of same pad type. For e.g. I3C medium Data Pads to be used with I3C Medium Clock and PUR Pads Only. I3C Standard plus Data Pads to be used with I3C standard plus Clock and PUR pads only. Table 44. I3C Push-Pull Timing Parameters for SDR Mode Symbol fSCL tDIG_L Description SCL Clock Frequency SCL Clock Low Period 1,2 Min 0.01 32 Typ 12.5 -- Max 12.9 -- Unit MHz ns Condition FSCL = 1 / (tDIG_L + tDIG_H) -- Table continues on the next page... Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 57 / 88 NXP Semiconductors Peripheral operating requirements and behaviors Table 44. I3C Push-Pull Timing Parameters for SDR Mode (continued) Symbol tDIG_H tSCO tCR tCF tHD_PP tSU_PP Description SCL Clock High Period 2 Clock in to Data Out for Slave 3,4 SCL Clock Rise Time 5 Min 32 -- -- SCL Clock Fall Time 5 -- SDA Signal Data Hold in Push- 0 Pull Mode, Slave 6 SDA Signal Data Setup in Push- 3 Pull Mode Typ -- -- -- -- -- -- Max -- 12 Unit ns ns 150e06 * ns 1 / fSCL (capped at 60) 150e06 * ns 1 / fSCL (capped at 60) -- -- N/A ns Condition -- -- -- -- Applicable for slave and master loopback modes Applicable for slave and master loopback modes. 1. As both edges are used, the hold time needs to be satisfied for the respective edges; i.e., tCF + 3 for falling edge clocks, and tCR + 3 for rising edge clocks. 2. tDIG_L and tDIG_H are the clock Low and High periods as seen at the receiver end of the I3C Bus using VIL and VIH (see Figure 30) 3. Devices with more than 12ns of tSCO delay shall set the limitation bit in the BCR, and shall support the GETMXDS CCC to allow the Master to read this value and adjust computations accordingly. For purposes of system design and test conformance, this parameter should be considered together with pad delay, bus capacitance, propagation delay, and clock triggering points. 4. Pad delay based on 90 / 4 mA driver and 50 pF load. Note that Master may be a Slave in a multi-Master system, and thus shall also adhere to this requirement 5. The clock maximum rise/fall time is capped at 60 ns. For lower frequency rise and fall the maximum value is limited at 60 ns, and is not dependent upon the clock frequency. 6. tHD_PP is a Hold time parameter for Push-Pull Mode that has a different value for Master mode vs. Slave mode. In SDR Mode the Hold time parameter is referred to as tHD_SDR. Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 58 / 88 NXP Semiconductors Peripheral operating requirements and behaviors Sr tfDA trDA tHD_DAT SDA tSU_STA tHD_STA tSU_DAT tfCL trCL SCL tHIGH tLOW tLOW tHIGH Sr P tSU_STO 0.7 x VDD 0.3 x VDD 0.7 x VDD 0.3 x VDD = Open Drain With Weak Pullup Figure 25. Legacy mode timing = High Speed Active Push-Pull Drive 0.7 x VDD tHIGH tCF tLOW 0.3 x VDD tCR Figure 26. tDIG_H and tDIG_L tDIG_H tDIG_L Figure 27. Master out timing SDA SCL tHD_PP tSU_PP tCF tCR 0.7 x VDD 0.3 x VDD 0.7 x VDD 0.3 x VDD Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 59 / 88 NXP Semiconductors Peripheral operating requirements and behaviors Figure 28. Slave out timing SDA tSCO tSU_PP SCL tCF tCR 0.7 x VDD 0.3 x VDD 0.7 x VDD 0.3 x VDD SDA 0.7 x VDD 0.3 x VDD SCL Figure 29. Master SDR timing tSU_PP 0.7 x VDD 0.3 x VDD tHD_SDR 4.6.7 USB Full-speed device electrical specifications This section describes the USB0 port Full Speed/Low Speed transceiver. The USB0 (FS/LS Transceiver) meets the electrical compliance requirements defined in the Universal Serial Bus Revision 2.0 Specification with the amendments below. · USB ENGINEERING CHANGE NOTICE -- Title: 5 V Short Circuit Withstand Requirement Change -- Applies to: Universal Serial Bus Specification, Revision 2.0 · Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000 · USB ENGINEERING CHANGE NOTICE -- Title: Pull-up/Pull-down resistors -- Applies to: Universal Serial Bus Specification, Revision 2.0 · USB ENGINEERING CHANGE NOTICE -- Title: Suspend Current Limit Changes -- Applies to: Universal Serial Bus Specification, Revision 2.0 Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 60 / 88 NXP Semiconductors Package dimensions This SoC does not have a dedicated pin to monitor the state of the USB VBUS signal. Please refer to the USBFS chapter in the Reference Manual for methods which can be used for VBUS Session_Valid detection with either a P4-12/ALT1 pin using an external resistive divider. 4.6.8 FlexCAN See General switching specifications. 4.6.9 Flexible I/O controller (FLEXIO) electrical specifications The following table shows FlexIO timing specifications. Table 45. Flexible I/O controller (FLEXIO) electrical specifications Symbol Description Min Typ Max Unit Condition tODS Output delay skew between any 0 two FlexIO_Dx pins configured as outputs that toggle on same internal clock cycle -- 8 ns -- tIDS Input delay skew between any 0 -- 8 ns -- two FlexIO_Dx pins configured as inputs that are sampled on the same internal clock cycle 4.7 Human Machine Interface (HMI) modules 4.7.1 General Purpose Input/Output (GPIO) See General switching specifications. 5 Package dimensions 5.1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to nxp.com and perform a keyword search for the drawing's document number: If you want the drawing for this package LQFP100 LFBGA64 VFBGA112 6 Pinout Then use this document number 98ASS23308W 98ASA02085D 98ASA02081D 6.1 MCXA156, A155, A154, A146, A145, A144 Signal Multiplexing and Pin Assignments The signal multiplexing and pin assignments are provided in an Excel file attached to this document: 1. Click the paperclip symbol on the left side of the PDF window. Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 61 / 88 NXP Semiconductors 2. Double-click on the Excel file to open it. 3. Select the "Pinout" tab. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. However the pinout table is as given below Table 46. Pinout Pin Name A14xA15x BGA112 A14xA15x LQFP100 A14xA15x BGA64 Pinmux Assignment Pad Settings P1_8 A1 1 B2 ALT0 - P1_8 IO Supply - VDD ALT1 - FREQME_CLK_IN0 Pad type - HD+I3C ALT2 - LPUART1_RXD Default - DIS ALT3 - LPI2C2_SDA ALT4 - CT_INP8 ALT5 - CT0_MAT2 ALT6 - FLEXIO0_D16 ALT10 - I3C0_SDA P1_9 B1 2 C2 ALT0 - P1_9 IO Supply - VDD ALT1 - FREQME_CLK_IN1 Pad type - HD ALT2 - LPUART1_TXD Default - DIS ALT3 - LPI2C2_SCL ALT4 - CT_INP9 ALT5 - CT0_MAT3 ALT6 - FLEXIO0_D17 ALT10 - I3C0_SCL P1_10 C3 3 D2 ALT0 - P1_10 IO Supply - VDD ALT2 - LPUART1_RTS_B Pad type - SLOW ALT3 - LPI2C2_SDAS Default - DIS ALT4 - CT2_MAT0 ALT6 - FLEXIO0_D18 ALT11 - CAN0_TXD P1_11 D3 4 D1 ALT0 - P1_11 IO Supply - VDD ALT1 - TRIG_OUT2 Pad type - SLOW ALT2 - LPUART1_CTS_B Default - DIS ALT3 - LPI2C2_SCLS ALT4 - CT2_MAT1 ALT6 - FLEXIO0_D19 ALT10 - I3C0_PUR ALT11 - CAN0_RXD P1_12 D2 5 -- ALT0 - P1_12 IO Supply - VDD Table continues on the next page... Pinout Alternate Functions ISP - I2C_SDA VDD SYS - WUU0_IN10 ISP - I2C_SCL ANALOG - ADC1_A8 ANALOG - ADC1_A9 VDD SYS - WUU0_IN11 ANALOG - ADC1_A10 Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 62 / 88 NXP Semiconductors Table 46. Pinout (continued) Pin Name A14xA15x BGA112 A14xA15x LQFP100 P1_13 D1 6 P1_14 E4 7 P1_15 F4 8 P1_29 F3 9 P1_30 F1 10 P1_31 F2 11 A14xA15x BGA64 Pinmux Assignment Pad Settings ALT2 - LPI2C1_SDA ALT3 - LPUART2_RXD ALT4 - CT2_MAT2 ALT6 - FLEXIO0_D20 ALT11 - CAN0_RXD Pad type - SLOW Default - DIS -- ALT0 - P1_13 IO Supply - VDD ALT1 - TRIG_IN3 Pad type - SLOW ALT2 - LPI2C1_SCL Default - DIS ALT3 - LPUART2_TXD ALT4 - CT2_MAT3 ALT6 - FLEXIO0_D21 ALT11 - CAN0_TXD -- ALT0 - P1_14 IO Supply - VDD ALT2 - LPI2C1_SCLS Pad type - SLOW ALT3 - LPUART2_RTS_B Default - DIS ALT4 - CT_INP10 ALT5 - CT3_MAT0 ALT6 - FLEXIO0_D22 -- ALT0 - P1_15 IO Supply - VDD ALT2 - LPI2C1_SDAS Pad type - SLOW ALT3 - LPUART2_CTS_B Default - DIS ALT4 - CT_INP11 ALT5 - CT3_MAT1 ALT6 - FLEXIO0_D23 E1 ALT0 - P1_29 IO Supply - VDD ALT1 - RESET_B Pad type - RST ALT2 - SPC_LPREQ Default - ALT1 E2 ALT0 - P1_30 IO Supply - VDD ALT1 - TRIG_OUT3 Pad type - HD+I3C ALT3 - LPI2C0_SDA Default - DIS ALT4 - CT_INP16 ALT6 - FLEXIO0_D30 ALT10 - I3C0_SDA F2 ALT0 - P1_31 IO Supply - VDD ALT1 - TRIG_IN4 Pad type - HD Table continues on the next page... Pinout Alternate Functions VDD SYS - WUU0_IN12 ANALOG - ADC1_A11 ANALOG - ADC1_A12 ANALOG - ADC1_A13 VDD SYS - RESET_B ANALOG - XTAL48M ANALOG - EXTAL48M Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 63 / 88 NXP Semiconductors Table 46. Pinout (continued) Pin Name A14xA15x BGA112 A14xA15x LQFP100 VSS VSS VREFL VREFH VDD_ANA VDD P4_2 D4,D10,F7,G2,G6, 12 G8,K4,K10,M12 D4,D10,F7,G2,G6, 12 G8,K4,K10,M12 H7 12 H6 13 J5 14 E5,F6,H8,J9 15 H1 16 P4_3 H3 17 P4_4 J3 18 P4_5 K3 19 A14xA15x BGA64 Pinmux Assignment ALT3 - LPI2C0_SCL ALT4 - CT_INP17 ALT6 - FLEXIO0_D31 ALT10 - I3C0_SCL D4,D5,D6,E6,F5,F 6 D4,D5,D6,E6,F5,F 6 E4 F4 E3 G3 -- ALT0 - P4_2 ALT1 - CLKOUT ALT2 - LPI2C2_SDAS ALT3 - LPUART3_RXD ALT4 - CT4_MAT0 ALT5 - PWM0_A2 ALT6 - FLEXIO0_D10 -- ALT0 - P4_3 ALT2 - LPI2C2_SCL ALT3 - LPUART4_TXD ALT4 - CT4_MAT1 ALT5 - PWM0_B2 ALT6 - FLEXIO0_D11 -- ALT0 - P4_4 ALT2 - LPI2C2_SDA ALT3 - LPUART4_RXD ALT4 - CT4_MAT2 ALT5 - PWM0_A1 ALT6 - FLEXIO0_D12 -- ALT0 - P4_5 ALT1 - TRIG_OUT3 ALT2 - LPI2C2_SCLS ALT3 - LPUART3_TXD Table continues on the next page... Pad Settings Default - DIS IO Supply - VDD IO Supply - VDD IO Supply - VDD IO Supply - VDD IO Supply - VDD IO Supply - VDD IO Supply - VDD Pad type - MED Default - DIS IO Supply - VDD Pad type - MED Default - DIS IO Supply - VDD Pad type - MED Default - DIS IO Supply - VDD Pad type - MED Default - DIS Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 Pinout Alternate Functions VDD SYS - WUU0_IN16 VDD SYS - WUU0_IN17 64 / 88 NXP Semiconductors Table 46. Pinout (continued) Pin Name A14xA15x BGA112 A14xA15x LQFP100 P4_6 K1 20 P4_7 K2 21 P2_0 L2 22 P2_1 M2 23 P2_2 M1 24 A14xA15x BGA64 Pinmux Assignment Pad Settings ALT4 - CT4_MAT3 ALT5 - PWM0_B1 ALT6 - FLEXIO0_D13 -- ALT0 - P4_6 IO Supply - VDD ALT1 - TRIG_IN4 Pad type - MED ALT2 - LPI2C2_HREQ Default - DIS ALT3 - LPUART3_CTS_B ALT4 - CT_INP6 ALT5 - PWM0_A0 ALT6 - FLEXIO0_D14 -- ALT0 - P4_7 IO Supply - VDD ALT1 - TRIG_IN5 Pad type - MED ALT3 - LPUART3_RTS_B Default - DIS ALT4 - CT_INP7 ALT5 - PWM0_B0 ALT6 - FLEXIO0_D15 G2 ALT0 - P2_0 IO Supply - VDD ALT1 - TRIG_IN6 Pad type - SLOW ALT2 - LPUART0_RXD Default - DIS ALT3 - LPUART4_CTS_B ALT4 - CT_INP16 ALT5 - CT2_MAT0 ALT6 - FLEXIO0_D8 G1 ALT0 - P2_1 IO Supply - VDD ALT1 - TRIG_IN7 Pad type - SLOW ALT2 - LPUART0_TXD Default - DIS ALT3 - LPUART4_RTS_B ALT4 - CT_INP17 ALT5 - CT2_MAT1 ALT6 - FLEXIO0_D9 H1 ALT0 - P2_2 IO Supply - VDD ALT1 - TRIG_IN6 Pad type - SLOW ALT2 - LPUART0_RTS_B Default - DIS ALT3 - LPUART2_TXD ALT4 - CT_INP12 ALT5 - CT2_MAT2 Table continues on the next page... Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 Pinout Alternate Functions ANALOG - ADC0_A0 VDD SYS - WUU0_IN18 ANALOG - ADC0_A1 ANALOG - ADC0_A4/ CMP0_IN0/DAC0_OUT 65 / 88 NXP Semiconductors Table 46. Pinout (continued) Pin Name A14xA15x BGA112 A14xA15x LQFP100 P2_3 N1 25 P2_4 N2 26 P2_5 L3 27 P2_6 M4 28 P2_7 N4 29 P2_7 N4 29 P2_10 L4 30 A14xA15x BGA64 Pinmux Assignment Pad Settings ALT6 - FLEXIO0_D10 J1 ALT0 - P2_3 IO Supply - VDD ALT1 - TRIG_IN7 Pad type - SLOW ALT2 - LPUART0_CTS_B Default - DIS ALT3 - LPUART2_RXD ALT4 - CT_INP13 ALT5 - CT2_MAT3 ALT6 - FLEXIO0_D11 J2 ALT0 - P2_4 IO Supply - VDD ALT3 - LPUART2_CTS_B Pad type - SLOW ALT4 - CT_INP14 Default - DIS ALT5 - CT1_MAT0 ALT6 - FLEXIO0_D12 H2 ALT0 - P2_5 IO Supply - VDD ALT3 - LPUART2_RTS_B Pad type - SLOW ALT4 - CT_INP15 Default - DIS ALT5 - CT1_MAT1 ALT6 - FLEXIO0_D13 H3 ALT0 - P2_6 IO Supply - VDD ALT1 - TRIG_OUT4 Pad type - SLOW ALT2 - LPSPI1_PCS1 Default - DIS ALT3 - LPUART4_RXD ALT4 - CT_INP18 ALT5 - CT1_MAT2 ALT6 - FLEXIO0_D14 H4 ALT0 - P2_7 IO Supply - VDD ALT1 - TRIG_IN5 Pad type - SLOW ALT3 - LPUART4_TXD Default - DIS ALT4 - CT_INP19 ALT5 - CT1_MAT3 ALT6 - FLEXIO0_D15 H4 IO Supply - VDD Pad type - ANA -- ALT0 - P2_10 IO Supply - VDD ALT1 - TRIG_OUT5 Pad type - SLOW Table continues on the next page... Pinout Alternate Functions ANALOG CMP1_IN0/ADC1_A4 VDD SYS - WUU0_IN19 ANALOG - ADC1_A0 ANALOG - ADC1_A1 ANALOG - ADC1_A3 ANALOG - VREFI/ ADC0_A7/ADC1_A7 Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 66 / 88 NXP Semiconductors Table 46. Pinout (continued) Pin Name A14xA15x BGA112 A14xA15x LQFP100 P2_11 K5 31 VSS VDD P2_12 D4,D10,F7,G2,G6, 32 G8,K4,K10,M12 E5,F6,H8,J9 33 K6 34 P2_13 L6 35 P2_13 L6 35 P2_15 N6 36 A14xA15x BGA64 Pinmux Assignment Pad Settings ALT3 - LPUART2_TXD ALT4 - CT3_MAT2 ALT6 - FLEXIO0_D18 Default - DIS -- ALT0 - P2_11 IO Supply - VDD ALT1 - TRIG_IN4 Pad type - SLOW ALT3 - LPUART2_RXD Default - DIS ALT4 - CT3_MAT3 ALT6 - FLEXIO0_D19 D4,D5,D6,E6,F5,F 6 IO Supply - VDD G3 IO Supply - VDD J4 ALT0 - P2_12 IO Supply - VDD ALT1 - USB0_VBUS_DET Pad type - SLOW ALT2 - LPSPI1_SCK Default - DIS ALT3 - LPUART1_RXD ALT4 - CT4_MAT0 ALT5 - CT0_MAT0 ALT6 - FLEXIO0_D20 ALT11 - CAN0_RXD J5 ALT0 - P2_13 IO Supply - VDD ALT1 - TRIG_IN8 Pad type - SLOW ALT2 - LPSPI1_SDO Default - DIS ALT3 - LPUART1_TXD ALT4 - CT4_MAT1 ALT5 - CT0_MAT1 ALT6 - FLEXIO0_D21 ALT11 - CAN0_TXD J5 IO Supply - VDD Pad type - LOLK H5 ALT0 - P2_15 IO Supply - VDD ALT1 - TRIG_OUT4 Pad type - SLOW ALT2 - LPSPI1_SDI Default - DIS ALT3 - LPUART1_RTS_B ALT4 - CT4_MAT3 ALT5 - CT0_MAT2 Table continues on the next page... Pinout Alternate Functions ISP - USB0_VBUS_DET ANALOG ADC0_A5/OPAMP0_INP0 VDD SYS - WUU0_IN20 ANALOG - ADC1_A5 ANALOG - OPAMP0_INN ANALOG OPAMP0_OUT/ADC0_A2 Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 67 / 88 NXP Semiconductors Table 46. Pinout (continued) Pin Name A14xA15x BGA112 A14xA15x LQFP100 P2_16 M6 37 P2_17 M7 38 P2_19 M8 39 P2_20 N8 40 P2_21 L8 41 P2_23 L9 42 VDD_USB M11 43 USB0_DM M10 44 A14xA15x BGA64 Pinmux Assignment Pad Settings ALT6 - FLEXIO0_D23 -- ALT0 - P2_16 IO Supply - VDD ALT2 - LPSPI1_SDI Pad type - SLOW ALT3 - LPUART1_RTS_B Default - DIS ALT4 - CT3_MAT0 ALT5 - CT0_MAT2 ALT6 - FLEXIO0_D24 -- ALT0 - P2_17 IO Supply - VDD ALT1 - TRIG_IN9 Pad type - SLOW ALT2 - LPSPI1_PCS0 Default - DIS ALT3 - LPUART1_CTS_B ALT4 - CT3_MAT1 ALT5 - CT0_MAT3 ALT6 - FLEXIO0_D25 -- ALT0 - P2_19 IO Supply - VDD ALT1 - TRIG_OUT5 Pad type - SLOW ALT4 - CT3_MAT3 Default - DIS ALT6 - FLEXIO0_D27 -- ALT0 - P2_20 IO Supply - VDD ALT1 - TRIG_IN8 Pad type - SLOW ALT2 - LPSPI1_PCS2 Default - DIS ALT4 - CT2_MAT0 ALT6 - FLEXIO0_D28 -- ALT0 - P2_21 IO Supply - VDD ALT1 - TRIG_IN9 Pad type - SLOW ALT2 - LPSPI1_PCS3 Default - DIS ALT4 - CT2_MAT1 ALT6 - FLEXIO0_D29 -- ALT0 - P2_23 IO Supply - VDD ALT1 - TRIG_OUT5 Pad type - SLOW ALT4 - CT2_MAT3 Default - DIS ALT6 - FLEXIO0_D31 H6 IO Supply - VDD_USB H7 IO Supply - VDD_USB Table continues on the next page... Pinout Alternate Functions ANALOG - ADC0_A6 ANALOG - ADC1_A6 ANALOG - ADC1_A2 ANALOG - USB0_DM VDD SYS - WUU0_IN28 Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 68 / 88 NXP Semiconductors Table 46. Pinout (continued) Pin Name A14xA15x BGA112 A14xA15x LQFP100 USB0_DP N10 45 A14xA15x BGA64 J7 Pinmux Assignment Pad Settings IO Supply - VDD_USB VSS VDD_P3 P3_31 D4,D10,F7,G2,G6, 46 G8,K4,K10,M12 E9,F8 47 N12 48 P3_30 N13 49 P3_29 M13 50 P3_28 L11 51 P3_27 K11 52 D4,D5,D6,E6,F5,F 6 IO Supply - VDD_P3 G5 IO Supply - VDD_P3 J8 ALT0 - P3_31 IO Supply - VDD_P3 ALT1 - TRIG_IN10 Pad type - SLOW ALT2 - LPI2C3_SDAS Default - DIS ALT3 - LPUART4_CTS_B ALT4 - CT0_MAT3 ALT6 - FLEXIO0_D31 J9 ALT0 - P3_30 IO Supply - VDD_P3 ALT1 - TRIG_OUT6 Pad type - SLOW ALT2 - LPI2C3_SCLS Default - DIS ALT3 - LPUART4_RTS_B ALT4 - CT0_MAT2 ALT6 - FLEXIO0_D30 H9 ALT0 - P3_29 IO Supply - VDD_P3 ALT1 - ISPMODE_N Pad type - SLOW ALT2 - LPI2C3_HREQ Default - ALT1 ALT4 - CT_INP3 ALT5 - CT3_MAT3 ALT6 - FLEXIO0_D29 G7 ALT0 - P3_28 IO Supply - VDD_P3 ALT1 - TRIG_IN11 Pad type - 5VTOL ALT2 - LPI2C3_SDA Default - DIS ALT3 - LPUART4_RXD ALT4 - CT_INP12 ALT5 - CT3_MAT2 ALT6 - FLEXIO0_D28 E7 ALT0 - P3_27 IO Supply - VDD_P3 ALT1 - TRIG_OUT7 Pad type - 5VTOL ALT2 - LPI2C3_SCL Default - DIS ALT3 - LPUART4_TXD ALT4 - CT_INP13 Table continues on the next page... Pinout Alternate Functions ANALOG - USB0_DP VDD SYS - WUU0_IN29 ANALOG - ADC1_A20 VDD SYS - LPTMR0_ALT2 ANALOG - ADC1_A21 ANALOG - ADC1_A22 VDD SYS - WUU0_IN27 VDD SYS - WUU0_IN26 VDD SYS - WUU0_IN30 Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 69 / 88 NXP Semiconductors Table 46. Pinout (continued) Pin Name A14xA15x BGA112 A14xA15x LQFP100 P3_22 K13 53 P3_21 J10 54 P3_20 H10 55 P3_19 G11 56 P3_18 F10 57 P3_17 H11 58 A14xA15x BGA64 Pinmux Assignment Pad Settings ALT5 - CT3_MAT1 ALT6 - FLEXIO0_D27 -- ALT0 - P3_22 IO Supply - VDD_P3 ALT3 - LPUART1_RTS_B Pad type - SLOW ALT4 - CT_INP10 Default - DIS ALT6 - FLEXIO0_D30 ALT7 - PWM1_X2 -- ALT0 - P3_21 IO Supply - VDD_P3 ALT1 - TRIG_OUT1 Pad type - SLOW ALT2 - LPI2C3_SCL Default - DIS ALT3 - LPUART1_TXD ALT4 - CT2_MAT3 ALT6 - FLEXIO0_D29 -- ALT0 - P3_20 IO Supply - VDD_P3 ALT1 - TRIG_OUT0 Pad type - SLOW ALT2 - LPI2C3_SDA Default - DIS ALT3 - LPUART1_RXD ALT4 - CT2_MAT2 ALT5 - PWM0_X2 ALT6 - FLEXIO0_D28 -- ALT0 - P3_19 IO Supply - VDD_P3 ALT2 - LPUART4_TXD Pad type - SLOW ALT4 - CT2_MAT1 Default - DIS ALT5 - PWM0_X1 ALT6 - FLEXIO0_D27 ALT7 - PWM1_X1 -- ALT0 - P3_18 IO Supply - VDD_P3 ALT2 - LPUART4_RXD Pad type - SLOW ALT4 - CT2_MAT0 Default - DIS ALT5 - PWM0_X0 ALT6 - FLEXIO0_D26 ALT7 - PWM1_X0 -- ALT0 - P3_17 IO Supply - VDD_P3 ALT2 - LPUART4_CTS_B Pad type - SLOW ALT4 - CT_INP9 Default - DIS Table continues on the next page... Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 Pinout Alternate Functions 70 / 88 NXP Semiconductors Table 46. Pinout (continued) Pin Name A14xA15x BGA112 A14xA15x LQFP100 P3_16 H13 59 P3_15 H12 60 P3_14 G12 61 P3_13 F12 62 P3_12 F13 63 VSS D4,D10,F7,G2,G6, 64 G8,K4,K10,M12 A14xA15x BGA64 Pinmux Assignment Pad Settings ALT6 - FLEXIO0_D25 ALT7 - PWM1_B0 -- ALT0 - P3_16 IO Supply - VDD_P3 ALT2 - LPUART4_RTS_B Pad type - SLOW ALT4 - CT_INP8 Default - DIS ALT6 - FLEXIO0_D24 ALT7 - PWM1_A0 H8 ALT0 - P3_15 IO Supply - VDD_P3 ALT2 - LPUART2_TXD Pad type - SLOW ALT3 - LPUART3_RTS_B Default - DIS ALT4 - CT_INP7 ALT6 - FLEXIO0_D23 ALT7 - PWM1_B1 G8 ALT0 - P3_14 IO Supply - VDD_P3 ALT2 - LPUART2_RXD Pad type - SLOW ALT3 - LPUART3_CTS_B Default - DIS ALT4 - CT_INP6 ALT5 - PWM0_X2 ALT6 - FLEXIO0_D22 ALT7 - PWM1_A1 F8 ALT0 - P3_13 IO Supply - VDD_P3 ALT2 - LPUART2_CTS_B Pad type - SLOW ALT3 - LPUART3_RXD Default - DIS ALT4 - CT1_MAT3 ALT5 - PWM0_X1 ALT6 - FLEXIO0_D21 ALT7 - PWM1_B2 F9 ALT0 - P3_12 IO Supply - VDD_P3 ALT2 - LPUART2_RTS_B Pad type - SLOW ALT3 - LPUART3_TXD Default - DIS ALT4 - CT1_MAT2 ALT5 - PWM0_X0 ALT6 - FLEXIO0_D20 ALT7 - PWM1_A2 D4,D5,D6,E6,F5,F 6 IO Supply - VDD_P3 Table continues on the next page... Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 Pinout Alternate Functions VDD SYS - WUU0_IN25 71 / 88 NXP Semiconductors Table 46. Pinout (continued) Pin Name A14xA15x BGA112 A14xA15x LQFP100 VDD_P3 E9,F8 65 P3_11 F11 66 P3_10 E11 67 P3_9 D11 68 P3_8 D13 69 P3_7 D12 70 A14xA15x BGA64 Pinmux Assignment Pad Settings G5 IO Supply - VDD_P3 E9 ALT0 - P3_11 IO Supply - VDD_P3 ALT1 - TRIG_IN6 Pad type - MED ALT2 - LPSPI1_PCS0 Default - DIS ALT3 - LPUART1_CTS_B ALT4 - CT1_MAT1 ALT5 - PWM0_B2 ALT6 - FLEXIO0_D19 E8 ALT0 - P3_10 IO Supply - VDD_P3 ALT1 - TRIG_IN5 Pad type - MED ALT2 - LPSPI1_SCK Default - DIS ALT3 - LPUART1_RTS_B ALT4 - CT1_MAT0 ALT5 - PWM0_A2 ALT6 - FLEXIO0_D18 D8 ALT0 - P3_9 IO Supply - VDD_P3 ALT1 - TRIG_IN4 Pad type - MED ALT2 - LPSPI1_SDI Default - DIS ALT3 - LPUART1_TXD ALT4 - CT_INP5 ALT5 - PWM0_B1 ALT6 - FLEXIO0_D17 C8 ALT0 - P3_8 IO Supply - VDD_P3 ALT1 - TRIG_IN3 Pad type - MED ALT2 - LPSPI1_SDO Default - DIS ALT3 - LPUART1_RXD ALT4 - CT_INP4 ALT5 - PWM0_A1 ALT6 - FLEXIO0_D16 ALT12 - CLKOUT C9 ALT0 - P3_7 IO Supply - VDD_P3 ALT1 - TRIG_IN2 Pad type - MED ALT2 - LPSPI1_PCS2 Default - DIS ALT3 - LPUART3_CTS_B ALT4 - CT4_MAT3 ALT5 - PWM0_B0 Table continues on the next page... Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 Pinout Alternate Functions VDD SYS - WUU0_IN24 VDD SYS - WUU0_IN23 72 / 88 NXP Semiconductors Table 46. Pinout (continued) Pin Name A14xA15x BGA112 A14xA15x LQFP100 P3_6 C12 71 P3_2 B12 -- P3_1 B13 72 P3_0 A13 73 VSS VDD_P3 D4,D10,F7,G2,G6, 74 G8,K4,K10,M12 E9,F8 75 A14xA15x BGA64 Pinmux Assignment Pad Settings ALT6 - FLEXIO0_D15 ALT7 - PWM1_B0 B9 ALT0 - P3_6 IO Supply - VDD_P3 ALT1 - CLKOUT Pad type - MED ALT2 - LPSPI1_PCS3 Default - DIS ALT3 - LPUART3_RTS_B ALT4 - CT4_MAT2 ALT5 - PWM0_A0 ALT6 - FLEXIO0_D14 ALT7 - PWM1_A0 ALT12 - FREQME_CLK_OUT1 -- ALT0 - P3_2 IO Supply - VDD_P3 ALT2 - LPSPI1_PCS1 Pad type - MED ALT4 - CT4_MAT0 Default - DIS ALT6 - FLEXIO0_D10 ALT7 - PWM1_X2 A9 ALT0 - P3_1 IO Supply - VDD_P3 ALT1 - TRIG_IN1 Pad type - HD ALT3 - LPUART3_TXD Default - DIS ALT4 - CT_INP17 ALT5 - PWM0_B0 ALT6 - FLEXIO0_D9 ALT7 - PWM1_X1 ALT12 - FREQME_CLK_OUT0 A8 ALT0 - P3_0 IO Supply - VDD_P3 ALT1 - TRIG_IN0 Pad type - HD ALT3 - LPUART3_RXD Default - DIS ALT4 - CT_INP16 ALT5 - PWM0_A0 ALT6 - FLEXIO0_D8 ALT7 - PWM1_X0 D4,D5,D6,E6,F5,F 6 IO Supply - VDD_P3 G5 IO Supply - VDD_P3 Table continues on the next page... Pinout Alternate Functions VDD SYS - WUU0_IN22 Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 73 / 88 NXP Semiconductors Table 46. Pinout (continued) Pin Name A14xA15x BGA112 A14xA15x LQFP100 VDD E5,F6,H8,J9 -- P0_0 A12 76 P0_1 C11 77 P0_2 C10 78 P0_3 B10 79 P0_6 A10 80 A14xA15x BGA64 Pinmux Assignment Pad Settings G3 IO Supply - VDD B8 ALT0 - P0_0 IO Supply - VDD ALT1 - TMS/SWDIO Pad type - MED ALT2 - LPUART0_RTS_B Default - ALT1 ALT3 - LPSPI0_PCS0 ALT4 - CT_INP0 ALT6 - FLEXIO0_D0 B7 ALT0 - P0_1 IO Supply - VDD ALT1 - TCLK/SWCLK Pad type - MED ALT2 - LPUART0_CTS_B Default - ALT1 ALT3 - LPSPI0_SDI ALT4 - CT_INP1 ALT6 - FLEXIO0_D1 B6 ALT0 - P0_2 IO Supply - VDD ALT1 - TDO/SWO Pad type - MED ALT2 - LPUART0_RXD Default - ALT1 ALT3 - LPSPI0_SCK ALT4 - CT0_MAT0 ALT5 - UTICK_CAP0 ALT6 - FLEXIO0_D2 ALT10 - I3C0_PUR A6 ALT0 - P0_3 IO Supply - VDD ALT1 - TDI Pad type - MED ALT2 - LPUART0_TXD Default - ALT1 ALT3 - LPSPI0_SDO ALT4 - CT0_MAT1 ALT5 - UTICK_CAP1 ALT6 - FLEXIO0_D3 ALT8 - CMP0_OUT C7 ALT0 - P0_6 IO Supply - VDD ALT1 - ISPMODE_N Pad type - SLOW ALT2 - LPI2C0_HREQ Default - ALT1 ALT3 - LPSPI0_PCS1 ALT4 - CT_INP2 ALT6 - FLEXIO0_D6 ALT8 - CMP1_OUT Table continues on the next page... Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 Pinout Alternate Functions ISP - UART_RXD ISP - UART_TXD ANALOG CMP1_IN1/ADC0_A14 ISP - ISPMODE_N ANALOG - ADC0_A15 74 / 88 NXP Semiconductors Table 46. Pinout (continued) Pin Name A14xA15x BGA112 A14xA15x LQFP100 VDD VSS P0_16 E5,F6,H8,J9 81 D4,D10,F7,G2,G6, 82 G8,K4,K10,M12 D9 83 P0_17 D8 84 P0_18 C8 85 P0_19 A8 86 P0_20 B8 87 P0_21 B7 88 A14xA15x BGA64 Pinmux Assignment ALT12 - CLKOUT G3 D4,D5,D6,E6,F5,F 6 C5 ALT0 - P0_16 ALT2 - LPI2C0_SDA ALT3 - LPSPI0_PCS2 ALT4 - CT0_MAT0 ALT5 - UTICK_CAP2 ALT6 - FLEXIO0_D0 ALT10 - I3C0_SDA C3 ALT0 - P0_17 ALT2 - LPI2C0_SCL ALT3 - LPSPI0_PCS3 ALT4 - CT0_MAT1 ALT5 - UTICK_CAP3 ALT6 - FLEXIO0_D1 ALT10 - I3C0_SCL -- ALT0 - P0_18 ALT2 - LPI2C0_SCLS ALT4 - CT0_MAT2 ALT6 - FLEXIO0_D2 ALT8 - CMP0_OUT -- ALT0 - P0_19 ALT2 - LPI2C0_SDAS ALT4 - CT0_MAT3 ALT6 - FLEXIO0_D3 ALT8 - CMP1_OUT -- ALT0 - P0_20 ALT3 - LPUART0_RXD ALT4 - CT_INP0 ALT6 - FLEXIO0_D4 -- ALT0 - P0_21 ALT3 - LPUART0_TXD ALT4 - CT_INP1 Table continues on the next page... Pad Settings IO Supply - VDD IO Supply - VDD IO Supply - VDD Pad type - HD+I3C Default - DIS IO Supply - VDD Pad type - HD Default - DIS IO Supply - VDD Pad type - SLOW Default - DIS IO Supply - VDD Pad type - SLOW Default - DIS IO Supply - VDD Pad type - SLOW Default - DIS IO Supply - VDD Pad type - SLOW Default - DIS Pinout Alternate Functions ANALOG - NVM_TM0 VDD SYS - WUU0_IN2 ANALOG - NVM_TM1 ANALOG - ADC0_A8 ANALOG - ADC0_A9 ANALOG - ADC0_A10 ANALOG - ADC0_A11 Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 75 / 88 NXP Semiconductors Table 46. Pinout (continued) Pin Name A14xA15x BGA112 A14xA15x LQFP100 P0_22 B6 89 P0_23 A6 90 P1_0 C6 91 P1_1 C5 92 P1_2 C4 93 P1_3 A4 94 A14xA15x BGA64 Pinmux Assignment Pad Settings ALT6 - FLEXIO0_D5 -- ALT0 - P0_22 IO Supply - VDD ALT3 - LPUART0_RTS_B Pad type - SLOW ALT4 - CT_INP2 Default - DIS ALT5 - CT0_MAT0 ALT6 - FLEXIO0_D6 -- ALT0 - P0_23 IO Supply - VDD ALT3 - LPUART0_CTS_B Pad type - SLOW ALT4 - CT_INP3 Default - DIS ALT5 - CT0_MAT1 ALT6 - FLEXIO0_D7 A5 ALT0 - P1_0 IO Supply - VDD ALT1 - TRIG_IN0 Pad type - MED+I2C ALT2 - LPSPI0_SDO Default - DIS ALT3 - LPI2C1_SDA ALT4 - CT_INP4 ALT5 - CT0_MAT2 ALT6 - FLEXIO0_D8 B5 ALT0 - P1_1 IO Supply - VDD ALT1 - TRIG_IN1 Pad type - MED+I2C ALT2 - LPSPI0_SCK Default - DIS ALT3 - LPI2C1_SCL ALT4 - CT_INP5 ALT5 - CT0_MAT3 ALT6 - FLEXIO0_D9 B4 ALT0 - P1_2 IO Supply - VDD ALT1 - TRIG_OUT0 Pad type - MED ALT2 - LPSPI0_SDI Default - DIS ALT3 - LPI2C1_SDAS ALT4 - CT1_MAT0 ALT5 - CT_INP0 ALT6 - FLEXIO0_D10 ALT11 - CAN0_TXD B3 ALT0 - P1_3 IO Supply - VDD ALT1 - TRIG_OUT1 Pad type - MED Table continues on the next page... Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 Pinout Alternate Functions ANALOG - ADC0_A12 ANALOG - ADC0_A13 ISP - SPI_SDO ANALOG ADC0_A16/CMP0_IN3 VDD SYS WUU0_IN6/LPTMR0_ALT3 ISP - SPI_SCK ANALOG ADC0_A17/CMP1_IN3 ISP - SPI_SDI ANALOG - ADC0_A18 ISP - SPI_PCS ANALOG ADC0_A19/CMP0_IN1 76 / 88 NXP Semiconductors Table 46. Pinout (continued) Pin Name A14xA15x BGA112 A14xA15x LQFP100 VDD VSS P1_4 E5,F6,H8,J9 95 D4,D10,F7,G2,G6, 96 G8,K4,K10,M12 B4 97 P1_5 B3 98 P1_6 B2 99 P1_7 A2 100 A14xA15x BGA64 Pinmux Assignment Pad Settings ALT2 - LPSPI0_PCS0 ALT3 - LPI2C1_SCLS ALT4 - CT1_MAT1 ALT5 - CT_INP1 ALT6 - FLEXIO0_D11 ALT11 - CAN0_RXD Default - DIS G3 IO Supply - VDD D4,D5,D6,E6,F5,F 6 IO Supply - VDD A3 ALT0 - P1_4 IO Supply - VDD ALT1 - FREQME_CLK_IN0 Pad type - MED ALT2 - LPSPI0_PCS3 Default - DIS ALT3 - LPUART2_RXD ALT4 - CT1_MAT2 ALT6 - FLEXIO0_D12 A2 ALT0 - P1_5 IO Supply - VDD ALT1 - FREQME_CLK_IN1 Pad type - MED ALT2 - LPSPI0_PCS2 Default - DIS ALT3 - LPUART2_TXD ALT4 - CT1_MAT3 ALT6 - FLEXIO0_D13 A1 ALT0 - P1_6 IO Supply - VDD ALT1 - TRIG_IN2 Pad type - MED ALT2 - LPSPI0_PCS1 Default - DIS ALT3 - LPUART2_RTS_B ALT4 - CT_INP6 ALT5 - CT4_MAT0 ALT6 - FLEXIO0_D14 ALT11 - CAN0_TXD B1 ALT0 - P1_7 IO Supply - VDD ALT1 - TRIG_OUT2 Pad type - MED ALT3 - LPUART2_CTS_B Default - DIS ALT4 - CT_INP7 ALT5 - CT4_MAT1 ALT6 - FLEXIO0_D15 ALT11 - CAN0_RXD Pinout Alternate Functions VDD SYS - WUU0_IN7 ANALOG ADC0_A20/CMP0_IN2 VDD SYS - WUU0_IN8 ANALOG ADC0_A21/CMP1_IN2 ANALOG - ADC0_A22 ANALOG - ADC0_A23 VDD SYS - WUU0_IN9 Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 77 / 88 NXP Semiconductors NOTE · +I3C in Pad Type represents that strong pull up resistor is implemented on the pin. PV bit is implemented in Pin Control register of the pin. · +I2C_FILT in Pad Type represents that I2C filter is implemented on the pin. PFE bit is implemented in Pin Control register of the pin. · HD in Pad Type represents that the pin can support up to 20mA drive strength. I2C filter is implemented on the pin. PFE bit is implemented in Pin Control register of the pin. · 5VTOL in Pad Type represents that the pin is 5V tolerant · DIS in default column represents that the pin's input buffer is disabled by default · RST pads support passive filter and 1M ohm pull resistor. PFE and PV bits are implemented in Pin Control register of the pin. · PE, PS, SRE, ODE and DSE are supported in Pin Control register of all types of IO. · 5VTol and HD pads support two DSE bits in Pin Control register of the pin. · PWM1, OpAMP and DAC are not available in MCXA145 and MCXA146. · In LQFP100, BGA112 and BGA64, the ISPMODE_n pin is on P0_6. In 64LQFP and smaller pin count package, ISPMODE_n pin is on P3_29. · SLOW in Pad Type represents the IO supports 25 MHz. MED in Pad Type represents the Io supports 50 MHz. Pinout 6.2 MCXA156, A155, A154, A146, A145, A144 Pinout diagram The pinout diagrams are provided in an Excel file attached to this document: 1. Click the paperclip symbol on the left side of the PDF window. 2. Double-click on the Excel file to open it. 3. Select the respective package tab. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, refer to the "Pinout" tab in the Excel file. 6.3 Recommended connection for unused analog and digital pins Table 47 shows the recommended connections for pins if those pins are not used in the customer's application Table 47. Recommended connection for unused interfaces Pin Type Pin Function Recommendation Comments Power VDD Must be powered VDD is the IO supply of P0,P1,P2 and P4, and supplies internal modules including Flash, CMP, and etc. It must be on. Power VDD_P3 Must be powered VDD_P3 is the IO supply of P3. It must be ramp up together with or after VDD. If want to shut down VDD_P3, must assert the isolation in SPC EVD_CFG register before shut down VDD_P3 in Active mode. Power VDD_ANA Must be powered VDD_ANA must be same level with VDD, and ramps up together with VDD_ANA Power VDD_USB Tie to ground through a 10 k resistor if VDD_ Table continues on the next page... Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 78 / 88 NXP Semiconductors Ordering parts Table 47. Recommended connection for unused interfaces (continued) Pin Type Pin Function Recommendation Comments USB is an independent pin in the package version used Power VREFH Always connect to VDD_ANA potential Always connect to VDD_ANA potential Power VREFL Always connect to VSS Always connect to VSS potential potential Power VSS_ANA Always connect to VSS Always connect to VSS potential potential Power VSS_USB Always connect to VSS Always connect to VSS potential potential Analog/non-GPIO ADCn_x Float Analog/non-GPIO ADCn_x/DACn_OUT Float Analog/non-GPIO EXTAL Float Analog/non-GPIO XTAL Float Analog output - Float Analog/non-GPIO USB0_DP Float Float Analog/non-GPIO USB0_DM Float Float GPIO/Analog Px/ADCn_x Float Float (default is analog input) GPIO/Analog Px/CMPn_INx Float Float (default is analog input) GPIO/Digital JTAG_TCLK Float Float (default is JTAG with pulldown) GPIO/Digital JTAG_TDI Float Float (default is JTAG with pullup) GPIO/Digital JTAG_TDO Float Float (default is JTAG with pullup) GPIO/Digital JTAG_TMS Float Float (default is JTAG with pullup) GPIO/Digital Px Float Float (default is disabled) 7 Ordering parts 7.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to nxp.com and perform a part number search for the following device numbers: MCX A146 NOTE For complete list of Orderable part numbers, please refer Table 1 8 Part identification Part numbers for the device have fields that identify the specific part. Use the values of these fields to determine the specific part. Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 79 / 88 NXP Semiconductors Part identification 8.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 8.2 Part number format Part numbers for this device have the following format: B PS F C D FS T PG SR PT Table 48. Part number fields descriptions Field Description B Brand PS Product series name F Family C Core Features FS Flash Size T Junction Temperature range (°C) PG Package SR Silicon Revision PT Package Type · MCX Values ·A · 1 = First Device, Smallest Die size · 2 = 2nd Device w Always On Domain · 3 = 3rd Device w Advance Analog · 4 = 48 MHz, Motor PWM, USB FS · 5 = 96 MHz, Motor PWM, USB FS · 1 = 32 KB · 2 = 64 KB · 3 = 128 KB · 4 = 256 KB · 5 = 512 KB · 6 = 1024 KB · 7=2M · V = 40 to 125 · LL = LQFP100 · MP = LFBGA64 · PJ = VFBGA112 · A = Initial Mask set · B = 1st Major spin · C = 2nd Major spin · R = Tape and Reel · T = Tray 8.3 Example This is an example part number: Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 80 / 88 NXP Semiconductors MCXA146VLH 8.4 Small package marking 8.4.1 Package marking information Table 49. Package marking LQFP100 14*14 First line AAAAAAAAAA Second line MMMMM Third line XXXXYYWWXX LFBGA64 5*5 AAAAAA MMMMM XXYWXX Terminology and guidelines VFBGA112 7*7 AAAAAA MMMMM XXXYWXX Identifier a m y w x Description Part number code, refer to Ordering Information Mask set Year Work week NXP internal use 9 Terminology and guidelines 9.1 Definitions Key terms are defined in the following table: Term Rating Definition A minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: · Operating ratings apply during operation of the chip. · Handling ratings apply when the chip is not powered. NOTE The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions Typical value A specified value for a technical characteristic that: Table continues on the next page... Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 81 / 88 NXP Semiconductors Terminology and guidelines Term Table continued from the previous page... Definition · Lies within the range of values specified by the operating behavior · Is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions NOTE Typical values are provided as design guidelines and are neither tested nor guaranteed. 9.2 Examples 9.3 Typical-value conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD Supply voltage 3.3 V Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 82 / 88 NXP Semiconductors Terminology and guidelines 9.4 Relationship between ratings and operating requirements Fatal range Operating rating (min.) Operating requirement (min.) Operating requirement (max.) Operating rating (max.) Degraded operating range Normal operating range Degraded operating range Fatal range Expected permanent failure - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Correct operation - No permanent failure - Possible decreased life - Possible incorrect operation Expected permanent failure Operating (power on) Fatal range Handling rating (min.) Expected permanent failure Handling range No permanent failure Handling (power off) Handling rating (max.) Fatal range Expected permanent failure 9.5 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: · Never exceed any of the chip's ratings. · During normal operation, don't exceed any of the chip's operating requirements. · If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 9.6 Specification Test Methods Each specification is tested using one of these methods. Code P I C L Method Description Production direct On every chip during production, testing the specification Production indirect On every chip during production, testing parts of a module that affect whether the chip meets the specification but not testing the specification itself Characterization on a production tester Characterization on lab equipment or a nonproduction tester Measuring a statistically significant number of sample chips across process (matrix lot), voltage, and temperature Table continues on the next page... Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 83 / 88 NXP Semiconductors Revision History Code D O Table continued from the previous page... Method Description NOTE Typical values are not necessarily characterized across process. Guaranteed by design Other Specification based on scientific and engineering principles Using methods such as: · Performing silicon simulations · Performing package thermal simulations · Calculating specifications using reliability data 10 Revision History The following table provides a revision history for this document. Table 50. Revision History Rev. No. Date 5 July 2024 Substantial Changes · Initial public release Data Sheet: Technical Data MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 84 / 88 NXP Semiconductors Legal information Legal information Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. 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