Vishay Intertechnology: Passives & Discrete Semiconductorsvishay.com/doc?91000vishay.com/doc?99912IRFI840G MOSFETs | Vishay
Owner's Manual for VISHAY models including: IRFI840GPBF, IRFI840G, IRFI840G Power MOSFET, Power MOSFET, MOSFET
IRFI840GPBF | vishay - INELTP
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DocumentDocumentwww.vishay.com Power MOSFET D TO-220 FULLPAK G S GD S N-Channel MOSFET PRODUCT SUMMARY VDS (V) RDS(on) () Qg (Max.) (nC) Qgs (nC) Qgd (nC) Configuration 500 VGS = 10 V 67 10 34 Single 0.85 IRFI840G Vishay Siliconix FEATURES · Isolated package · High voltage isolation = 2.5 kVRMS (t = 60 s; f = 60 Hz) · Sink to lead creepage distance = 4.8 mm · Dynamic dV/dt rating · Low thermal resistance · Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 DESCRIPTION Third generation power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The TO-220 FULLPAK eliminates the need for additional insulating hardware in commercial-industrial applications. The molding compound used provides a high isolation capability and a low thermal resistance between the tab and external heatsink. The isolation is equivalent to using a 100 micron mica barrier with standard TO-220 product. The FULLPAK is mounted to a heatsink using a single clip or by a single screw fixing. ORDERING INFORMATION Package Lead (Pb)-free TO-220 FULLPAK IRFI840GPbF ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER SYMBOL Drain-source voltage Gate-source voltage Continuous drain current Pulsed drain current a Linear derating factor VDS VGS VGS at 10 V TC = 25 °C TC = 100 °C ID IDM Single pulse avalanche energy b Repetitive avalanche current a Repetitive avalanche energy a Maximum power dissipation Peak diode recovery dV/dt c TC = 25 °C EAS IAR EAR PD dV/dt Operating junction and storage temperature range Soldering recommendations (peak temperature) d For 10 s TJ, Tstg Mounting torque M3 screw Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11) b. VDD = 50 V, starting TJ = 25 °C, L = 31 mH, RG = 25 , IAS = 4.6 A (see fig. 12) c. ISD 8.0 A, dI/dt 100 A/s, VDD VDS, TJ 150 °C d. 1.6 mm from case LIMIT 500 ± 20 4.6 2.9 18 0.32 370 4.6 4.0 40 3.5 -55 to +150 300 0.6 UNIT V A W/°C mJ A mJ W V/ns °C Nm S21-0975-Rev. C, 11-Oct-2021 1 Document Number: 91161 For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Downloaded from Arrow.com. www.vishay.com IRFI840G Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL Maximum junction-to-ambient Maximum junction-to-case (drain) RthJA RthJC TYP. - MAX. 65 3.1 UNIT °C/W SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS Static Drain-ssource breakdown voltage VDS temperature coefficient Gate-source threshold voltage Gate-source leakage Zero gate voltage drain current Drain-source on-state resistance Forward transconductance Dynamic VDS VDS/TJ VGS(th) IGSS IDSS RDS(on) gfs VGS = 0 V, ID = 250 A Reference to 25 °C, ID = 1 mA VDS = VGS, ID = 250 A VGS = ± 20 V VDS = 500 V, VGS = 0 V VDS = 400 V, VGS = 0 V, TJ = 125 °C VGS = 10 V ID = 2.8 Ab VDS = 50 V, ID = 2.8 Ab Input capacitance Output capacitance Reverse transfer capacitance Drain to sink capacitance Ciss Coss Crss C VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 f = 1.0 MHz Total gate charge Gate-source charge Gate-drain charge Turn-on delay time Rise time Turn-off delay time Fall time Qg Qgs Qgd td(on) tr td(off) tf VGS = 10 V ID = 8.0 A, VDS = 400 V, see fig. 6 and 13b VDD = 250 V, ID = 8.0 A, RG = 9.1, RD= 31 , see fig. 10b Internal drain inductance Internal source inductance LD Between lead, 6 mm (0.25") from D package and center of G LS die contact S Drain-Source Body Diode Characteristics MIN. 500 - 2.0 - 3.7 - - - TYP. MAX. UNIT - - V 0.78 - V/°C - 4.0 V - ± 100 nA - 25 A - 250 - 0.85 - - S 1300 - 200 - pF 39 - 12 - - 67 - 10 nC - 34 14 - 22 - ns 55 - 21 - 4.5 - nH 7.5 - Continuous source-drain diode current Pulsed diode forward current a IS MOSFET symbol showing the integral reverse ISM p - n junction diode D G S - - 4.6 A - - 18 Body diode voltage VSD TJ = 25 °C, IS = 4.6 A, VGS = 0 Vb - - 2.0 V Body diode reverse recovery time Body diode reverse recovery charge trr - 340 680 ns TJ = 25 °C, IF = 8.0 A, dI/dt = 100 A/sb Qrr - 1.8 2.6 C Forward turn-on time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11) b. Pulse width 300 s; duty cycle 2 % S21-0975-Rev. C, 11-Oct-2021 2 Document Number: 91161 For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Downloaded from Arrow.com. www.vishay.com TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted IRFI840G Vishay Siliconix Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 3 - Typical Transfer Characteristics Fig. 2 - Typical Output Characteristics, TC= 150 °C Fig. 4 - Normalized On-Resistance vs. Temperature S21-0975-Rev. C, 11-Oct-2021 3 Document Number: 91161 For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Downloaded from Arrow.com. www.vishay.com IRFI840G Vishay Siliconix Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 8 - Maximum Safe Operating Area S21-0975-Rev. C, 11-Oct-2021 4 Document Number: 91161 For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Downloaded from Arrow.com. www.vishay.com Fig. 9 - Maximum Drain Current vs. Case Temperature IRFI840G Vishay Siliconix VDS VGS RG RD D.U.T. 10 V Pulse width 1 µs Duty factor 0.1 % +- VDD Fig. 10a - Switching Time Test Circuit VDS 90 % 10 % VGS td(on) tr td(off) tf Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case S21-0975-Rev. C, 11-Oct-2021 5 Document Number: 91161 For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Downloaded from Arrow.com. www.vishay.com VDS Vary tp to obtain required IAS RG 10 V tp L D.U.T. IAS 0.01 + - VDD Fig. 12a - Unclamped Inductive Test Circuit IRFI840G Vishay Siliconix VDS VDS tp VDD IAS Fig. 12b - Unclamped Inductive Waveforms Fig. 12c - Maximum Avalanche Energy vs. Drain Current 10 V QGS VG QG QGD Charge Fig. 13a - Basic Gate Charge Waveform Current regulator Same type as D.U.T. 12 V 50 k 0.2 µF 0.3 µF D.U.T. + -VDS VGS 3 mA IG ID Current sampling resistors Fig. 13b - Gate Charge Test Circuit S21-0975-Rev. C, 11-Oct-2021 6 Document Number: 91161 For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Downloaded from Arrow.com. www.vishay.com D.U.T. + - Peak Diode Recovery dV/dt Test Circuit + Circuit layout considerations · Low stray inductance · Ground plane · Low leakage inductance current transformer - - + IRFI840G Vishay Siliconix Rg · dV/dt controlled by Rg + · Driver same type as D.U.T. · ISD controlled by duty factor "D" - VDD · D.U.T. - device under test Driver gate drive P.W. Period D = P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt VDD Re-applied voltage Body diode forward drop Inductor current Ripple 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91161. S21-0975-Rev. C, 11-Oct-2021 7 Document Number: 91161 For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Downloaded from Arrow.com. www.vishay.com Package Information Vishay Siliconix TO-220 FULLPAK (High Voltage) OPTION 1: FACILITY CODE = 9 A E F G D Q1 Ø R A3 L L1 3 x b2 Mold flash 3 x b1 bleeding Q Exposed Cu 3 x b 2 x e C DIM. A b b1 b2 C D e E F G L L1 Q Q1 Ø R MIN. 4.60 0.70 1.20 1.10 0.45 15.80 10.00 2.44 6.50 12.90 3.13 2.65 3.20 3.08 MILLIMETERS NOM. 4.70 0.80 1.30 1.20 0.50 15.87 2.54 BSC 10.10 2.54 6.70 13.10 3.23 2.75 3.30 3.18 Notes 1. To be used only for process drawing 2. These dimensions apply to all TO-220 FULLPAK leadframe versions 3 leads 3. All critical dimensions should C meet Cpk > 1.33 4. All dimensions include burrs and plating thickness 5. No chipping or package damage 6. Facility code will be the 1st character located at the 2nd row of the unit marking Bottom view MAX. 4.80 0.91 1.47 1.30 0.63 15.97 10.30 2.64 6.90 13.30 3.33 2.85 3.40 3.28 Revision: 08-Apr-2019 1 Document Number: 91359 For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Downloaded from Arrow.com. www.vishay.com OPTION 2: FACILITY CODE = Y E n Ø P Package Information Vishay Siliconix A A1 d1 d3 D u L1 V L b3 b2 b A2 c DIM. MIN. A 4.570 A1 2.570 A2 2.510 b 0.622 b2 1.229 b3 1.229 c 0.440 D 8.650 d1 15.88 d3 12.300 E 10.360 e L 13.200 L1 3.100 n 6.050 Ø P 3.050 u 2.400 V 0.400 ECN: E19-0180-Rev. D, 08-Apr-2019 DWG: 5972 MILLIMETERS 2.54 BSC MAX. 4.830 2.830 2.850 0.890 1.400 1.400 0.629 9.800 16.120 12.920 10.630 13.730 3.500 6.150 3.450 2.500 0.500 Notes 1. To be used only for process drawing 2. These dimensions apply to all TO-220 FULLPAK leadframe versions 3 leads 3. All critical dimensions should C meet Cpk > 1.33 4. All dimensions include burrs and plating thickness 5. No chipping or package damage 6. Facility code will be the 1st character located at the 2nd row of the unit marking MIN. 0.180 0.101 0.099 0.024 0.048 0.048 0.017 0.341 0.622 0.484 0.408 0.520 0.122 0.238 0.120 0.094 0.016 INCHES 0.100 BSC MAX. 0.190 0.111 0.112 0.035 0.055 0.055 0.025 0.386 0.635 0.509 0.419 0.541 0.138 0.242 0.136 0.098 0.020 Revision: 08-Apr-2019 2 Document Number: 91359 For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Downloaded from Arrow.com. www.vishay.com Disclaimer Legal Disclaimer Notice Vishay ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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