Antifuse Product Information Brochure

Axcelerator Family

The Axcelerator FPGA family is a single-chip, nonvolatile solution offering high performance and unprecedented design security at densities of up to 2 million equivalent system gates. Utilizing the AX architecture, Axcelerator devices feature embedded SRAM (with embedded FIFO control logic), PLLs, segmentable clocks, chip-wide highway routing, and carry logic. The solution is based upon 0.15 µm, seven-layers-of-metal CMOS antifuse process technology and offers 350 MHz system performance.

Key Features:

• 500+ MHz internal performance
• 500+ MHz embedded FIFOs
• PLL output up to 1 GHz and 8 PLLs per device
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V mixed-voltage operation
• Bank-selectable I/Os - 8 banks per chip
• 4.5 kbits variable-aspect RAM blocks with built-in FIFO control

Axcelerator Devices Specifications:

I/Os Per Package (Axcelerator Devices):

eX Family

The eX family of FPGAs, with its focused combination of features, can meet all of your power, speed, package, and price requirements. eX devices are optimized for wired and mobile e-appliances, and enable designers to use a flexible single-chip FPGA for their traditional low-density ASIC requirements without the long lead times and costly NRE charges.

Key Features:

• Low power consumption
• Live at power-up
• 2.5 V, 3.3 V, and 5.0 V mixed-voltage operation with 5.0 V input tolerance and 5.0 V drive strength
• Up to 100% resource utilization with 100% pin locking
• Fuselock secure programming technology prevents reverse engineering and design theft
• Available in automotive temperature grades

eX Devices Specifications:

I/Os Per Package (eX Devices):

SX-A Family

The SX-A family of FPGAs offers a cost-effective, single-chip solution for low-power, high-performance designs. SX-A devices can be used to generate system-wide savings by integrating multiple functions into a single-chip solution. Providing a combination of performance, security, and low power, SX-A FPGAs decrease the premium for performance while providing a solution that is highly resistant to reverse engineering.

Key Features:

• 250 MHz system performance
• 350 MHz internal performance
• Power-up and power-down friendly (no sequencing required for supply voltages)
• 66 MHz, 64-bit 3.3 V / 5.0 V PCI performance (supporting target, master and master/target)
• 2.5 V, 3.3 V, and 5.0 V mixed-voltage support
• 100% resource utilization with 100% pin locking

SX-A Devices Specifications:

I/Os Per Package (SX-A Devices):

MX Family

Featuring very low power consumption and the industry's highest design security, MX FPGAs offer designers a reliable, single-chip ASIC alternative. MX devices provide high performance while shortening the system design and development cycle. Offering an efficient, flexible 5.0 V architecture, MX is an ideal high-volume platform for integrating your legacy PLDs into a single device. Example applications include high-speed controllers and address decoding, peripheral bus interfaces, DSP, and coprocessor functions.

Key Features:

• Single-chip ASIC alternative
• Fast wide-decode circuitry
• High performance mixed-voltage solution
• Contains embedded dual-port SRAM modules
• QML certification
• Ceramic devices available to DSCC SM

MX Devices Specifications:

I/Os Per Package (MX Devices):

FPGA Packages

Key: f - family, bs - package body size excluding leads, ps - overall package dimensions including package leads, h - package thickness, p - pin pitch / ball pitch

Axcelerator Packages:

• BG729: f: Axcelerator, ps: 35x35 mm, h: 2.33 mm, p: 1.27 mm
• FG1152: f: Axcelerator, ps: 35x35 mm, h: 2.23 mm, p: 1.00 mm
• FG324: f: Axcelerator, ps: 19x19 mm, h: 1.63 mm, p: 1.00 mm
• FG896: f: Axcelerator, ps: 31x31 mm, h: 2.23 mm, p: 1.00 mm
• FG676: f: Axcelerator, ps: 27x27 mm, h: 2.23 mm, p: 1.00 mm
• FG484: f: Axcelerator, ps: 23x23 mm, h: 2.23 mm, p: 1.00 mm
• FG256: f: Axcelerator, ps: 17x17 mm, h: 1.60 mm, p: 1.00 mm
• PQ208: f: Axcelerator, SX-A, SX, MX, bs: 28x28 mm, ps: 30.6x30.6 mm, h: 3.40 mm, p: 0.50 mm

eX Packages:

• TQ100: f: SX-A, eX, bs: 14x14 mm, ps: 16x16 mm, h: 1.40 mm, p: 0.50 mm
• TQ64: f: eX, bs: 10x10 mm, ps: 12x12 mm, h: 1.40 mm, p: 0.50 mm

SX-A Packages:

• BG329: f: SX-A, SX, ps: 31x31 mm, h: 2.33 mm, p: 1.27 mm
• BG313: f: SX, ps: 35x35 mm, h: 2.33 mm, p: 1.27 mm
• FG256: f: SX-A, ps: 17x17 mm, h: 1.76 mm, p: 1.00 mm
• FG144: f: SX-A, SX, ps: 13x13 mm, h: 1.45 mm, p: 1.00 mm
• FG484: f: SX-A, ps: 27x27 mm, h: 2.23 mm, p: 1.00 mm
• TQ176: f: SX-A, SX, MX, bs: 24x24 mm, ps: 26x26 mm, h: 1.40 mm, p: 0.50 mm
• TQ144: f: SX-A, SX, bs: 20x20 mm, ps: 22x22 mm, h: 1.40 mm, p: 0.50 mm
• VQ100: f: SX, MX, bs: 14x14 mm, ps: 16x16 mm, h: 1.00 mm, p: 0.50 mm
• PL84: f: SX, MX, ps: 1.154x1.154", h: 0.150", p: 0.050"

MX Packages:

• BG272: f: MX, ps: 27x27 mm, h: 2.33 mm, p: 1.27 mm
• PQ240: f: MX, bs: 32x32 mm, ps: 34.6x34.6 mm, h: 3.40 mm, p: 0.50 mm
• PQ160: f: MX, bs: 28x28 mm, ps: 31.2x31.2 mm, h: 3.37 mm, p: 0.65 mm
• PQ100: f: MX, bs: 14x20 mm, ps: 17.2x23.2 mm, h: 2.80 mm, p: 0.65 mm
• PL68: f: MX, ps: 0.954x0.954", h: 0.150", p: 0.050"
• PL44: f: MX, ps: 0.654x0.654", h: 0.152", p: 0.050"
• VQ80: f: MX, bs: 14x14 mm, ps: 16x16 mm, h: 1.00 mm, p: 0.65 mm

For more information on package dimensions, refer to the Package Mechanical Drawings document at www.microsemi.com/soc/documents/PckgMechDrwngs.pdf.

Antifuse FPGA Selector Guide

This guide compares Microsemi antifuse FPGAs across various parameters.

Notes: 1. With the use of an external resistor. 2. For SX-A routed clocks are called global clocks. Hard-wired clocks are called quadrant clocks. 3. Not all speed grades are available for all temperature ranges. Please refer to the Microsemi website and appropriate product datasheets for the latest device information and valid ordering codes.

Antifuse I/Os by Package

This section compares the Input/Output (I/O) counts for Microsemi's antifuse devices across different packages.

For more information, refer to the Microsemi website at www.microsemi.com/fpga-soc.