NXP AN14721 Development Board

ព័ត៌មានអំពីផលិតផល

លក្ខណៈបច្ចេកទេស

• Product Name: TRDC in i.MX Devices
• លេខ​ម៉ូដែល។: AN14721
• ក្រុមហ៊ុនផលិត៖ NXP Semiconductors
• Components: Domain Assignment Controller (DAC), Memory Block Checker (MBC), Memory Region Checker (MRC)

ព័ត៌មានឯកសារ

ព័ត៌មាន	មាតិកា
ពាក្យគន្លឹះ	AN14721, i.MX, TRDC, resource isolation, security
អរូបី	Resource isolation plays an important role in functional safety and security. In terms of functional safety, resource isolation can reduce the failure impact between different domains. In terms of security, resource isolation can protect sensitive data.

សេចក្តីផ្តើម

Resource isolation plays an important role in functional safety and security. In terms of functional safety, resource isolation can reduce the failure impact between different domains. In terms of security, resource isolation can protect sensitive data. Starting from NXP’s i.MX 8ULP and i.MX 9 series chips, there are two resource-isolation mechanisms: one is the MIX hardware design method, and the other is the Trusted Resource Domain Controller (TRDC) logic-isolation method. In the hardware design of the SoC, i.MX 9 chips are divided into multiple MIXs. For example, i.MX 95 contains AONMIX, ANAMIX, WAKEUPMIX, and others. All MIXs
are separated from one another on the die because they are designed as separate modules and integrated at the SoC level. A failure in a non-safety-relevant MIX does not directly affect the safety-relevant MIX. It helps to achieve functional safety. However, the design of the MIX is fixed in terms of hardware and the hardware resources within each MIX cannot be adjusted. The TRDC provides a more flexible method of resource isolation, which can be customized and configured by developers to implement any resource-access policies.

ហេតុផល

The Trusted Resource Domain Controller (TRDC) consists of three parts: Domain Assignment Controller (DAC), Memory Block Checker (MBC), and Memory Region Checker (MRC). The roles and functions of these three parts in the resource access process are shown in Figure 1.

When a specific master accesses a certain resource, the access process can be divided into the following steps:

1. The Domain Assignment Controller (DAC) assigns attributes to the master, including the domain ID (DID), privileged mode, and secure status.
2. The master access signal reaches the Memory Block Checker (MBC) or Memory Region Checker (MRC) via the system bus.
3. The MBC or MRC checks whether the access permissions are in line with the configuration based on the master attributes and access types (read, write, execute).
4. If the permissions are granted by the configuration, the access is successful. Otherwise, the access is denied.

DAC
The Domain Assignment Controller (DAC) is mainly used to assign attributes to the master. A master refers to a bus master that can issue data transactions, which can be classified into processor and non-processor, such as Arm Cortex A55 (CA55), Arm Cortex M33 (CM33), DMA, and so on.

Three attributes are assigned:

1. DID (domain ID)
   The DID is an attribute for dividing logical domains. Masters with the same DID are masters within the same domain. The range of the DID is from 0 to 15. Every master has a default DID, which can be obtained from the respective SoC reference manuals.
2. របៀបដែលមានសិទ្ធិ
   In the Arm system, all modes except the user mode are privileged modes. The DAC can reconfigure this attribute of the master, such as setting the attribute to “User” or “Privileged”, or directly use the master’s attribute.
3. Secure status
   The secure status originates from the Arm TrustZone technology, including secure and non-secure states. The DAC can also configure this attribute of the master such as secure or non-secure or directly use the master’s attribute.
   When the master access signal is processed by the DAC and the DID, the privilege mode and secure status for the master are determined.

MBC
The Memory Block Checker (MBC) is mainly used for checking the access rights of internal resources. Internal resources include the memory and peripherals, such as AIPS, OCRAM, and so on. Each resource is divided into multiple resource blocks according to a fixed granularity. The MBC mechanism is shown in Figure 2.

The principle of access checking is as follows:

1. Configure a set of the Global Access Control (GLBAC).
   Eight GLBACs are available. Each GLBAC contains permission settings for 12 different combinations of access modes, including: secure/non-secure, privileged/user, read/write/execute.
2. For the block of a certain resource, select a certain GLBAC for each DID.
3. According to the master attributes and GLBAC, the MBC checks the master access permission.
4. If the permission is granted by the configuration, the access is successful. Otherwise, the access is denied.

MRC
The Memory Region Checker (MRC) is used for checking the access rights of external resources. External resources are usually the external memory, such as DRAM, FlexSPI, and others. These resources can be divided into multiple regions of different sizes. The MRC mechanism is shown in Figure 3.

The principle of access checking is as follows:

1. Configure a set of Global Access Control (GLBAC).
2. Divide a certain resource into regions and select a certain GLBAC for each DID.
   The setting of the region size is completely determined by the user and has no fixed value. Usually, you must set the start address and the end address.
3. According to the master attributes and GLBAC, the MRC checks the master access permission.
4. If the permission is granted by the configuration, the access is successful. Otherwise, the access is denied.
   The principle of the MRC is similar to that of the MBC. The difference is that the MRC manages permissions by region and the size of the region is configurable. The MBC is divided into blocks and the block size is fixed.

TRDC usage

The following section describes how to use the TRDC for three aspects: registers, configuration software, and configuration tools.

ចុះឈ្មោះ
Registers are the most direct configuration method. In the TRDC, due to the large number of configuration registers, you must learn how to determine the corresponding register positions.

DAC
The DAC is used to assign the DID and other attributes for masters. Each master has a default DID value. For example, in i.MX 93, the default DID value allocation is shown in Table 1.

Table 1. Default DID in i.MX 93

Default DID	ចៅហ្វាយនាយ
0	EdgeLock Secure Enclave-AP
1	MTR_MSTR
2	CM33  I, CM33_S

Default DID	ចៅហ្វាយនាយ
3	CA55, GIC600

If you want to change the default DID or other attributes, such as Privileged/User and Secure/non-secure, find the DAC address of the required master in the chip and write the corresponding register value.
សម្រាប់អតីតample, if you want to change the DID of the CA55 in i.MX 93 to 4, the privilege mode attribute follows the master, and the secure status is fixed as secure, then perform the following steps:

1. Find the MDAC location of the CA55:
   The following information is in the MDAC configuration table, in the TRDC chapter:
   Table 2. CA55 MDAC information in i.MX 93
   

   មេ	លាយ	Master index	Number of DAC registers
   CA55 read channel	NICMIX	0	4
   CA55 write channel		1	4

2. Find the register location:
   The NICMIX TRDC base address is 0x49010000.
   The corresponding DAC register is MDA_W(r)_(m)_DFMT(n), where r is the number of registers, m is the master index, and n is the master type.
   Table 3. CA55 DAC registers in i.MX 93
   

   មេ	ចុះឈ្មោះ DAC	អុហ្វសិត
   CA55 read channel	MDA_W0_0_DFMT0	0x800
   	MDA_W1_0_DFMT0	0x804
   	MDA_W2_0_DFMT0	0x808
   	MDA_W3_0_DFMT0	០x៤ ស៊ី
   CA55 write channel	MDA_W0_1_DFMT0	0x820
   	MDA_W1_1_DFMT0	0x824
   	MDA_W2_1_DFMT0	0x828
   	MDA_W3_1_DFMT0	០x៤ ស៊ី

3. Write the register:The MDAC register description is in the memory map of the TRDC chapter of the reference manual.

If you want the DID of the CA55 to be 4, the privilege mode attribute follows the host, and the secure status is fixed as secure, then: DID=4, SA=0, VLD=1.
In the remaining bit domains, PE, PIDM, and PID are used to dynamically configure the DID. When these functions are not in use, you can configure them all to 0. For a detailed explanation, see the functional description in the TRDC chapter. LK1 can lock the register to prevent subsequent changes and set it to 0 when not in use.
Therefore, the register value to write is 0x80000004.
Since both channels of the CA55 require the DID configuration and only one register configuration is needed for each, the following applies:

CA55 read channel:

MBC
The MBC checks the access of the internal resources of the chip. After the DAC configuration completes, the master identifier is replaced by the DID.

សម្រាប់អតីតample, in i.MX 93, you must implement the following:
The master with DID=3 only in the SP (secure privilege) and SU (secure non-privilege) states has the read/write/execute permissions for the OCRAM segment from 0x20500000 to 0x2050FFFF.
The master with DID=5 has all access permissions for this segment of OCRAM.

បន្ទាប់មក៖

1. Find the OCRAM information in the MBC configuration table.
   Table 4. OCRAM MBC information in i.MX 93

   លាយ	MBC instance	លេខច្រក	គ្រឿងកុំព្យូទ័រ	រារាំងលេខ	ទំហំប្លុក
   NICMIX	3	0	OCRAM	40	16 គីឡូបៃ
   		1	OCRAM	40	16 គីឡូបៃ

   There are two OCRAM ports because the OCRAM is accessed via the AXI bus, which has two separate read and write access channels. Therefore, SLV0 corresponds to the OCRAM read channel, and SLV1 corresponds to the OCRAM write channel.
2. Find and configure a set of GLBAC:
   The NICMIX TRDC base address is 0x49010000.
   Table 5. GLBAC

   ចុះឈ្មោះ	អុហ្វសិត
   MBC3_MEMN_GLBAC0	0x16020
   MBC3_MEMN_GLBAC1	0x16024
   MBC3_MEMN_GLBAC2	0x16028
   MBC3_MEMN_GLBAC7	០x៤ ស៊ី

   

3. Find and write the MBC control register where the OCRAM block is located:
   • a. OCRAM configuration segment: 0x20500000~0x2050FFFF.
   • b. OCRAM in i.MX 93: 0x20480000~0x2051FFFF.
   • c. Block number: 40.
   • d. Block size: 16 kB (0x400).
4. Corresponding OCRAM blocks:
   • a. Start block: (0x20500000-0x20480000)/0x4000=32.
   • b. End block: (0x2050FFFF-0x20480000)/0x4000=35
5. The MBC configuration registers are MBC[m]_DOM[d]_MEM[s]_BLK_CFG_W[w]:
   • a. m is the instance number of MBC, and OCRAM corresponds to 3.
   • b. d is the DID. You must configure DID=3 and DID=5.
   • c. s is the memory port number. OCRAM corresponds to 0 and 1.
   • d. w is the configuration word number. Each word is used for eight memory blocks.
     Since the OCRAM configuration block is [32:35], w1=32/8=4 with a remainder of 0, and w2=35/8=4 with a remainder of 3. Therefore, you must configure block [0:3] in word4, which corresponds to bit [0:15].

Table 6. MBC OCRAM registers

ឌី	ចុះឈ្មោះ	អាស័យដ្ឋាន	តម្លៃ [0:15]
3	MBC3_DOM3_MEM0_BLK_CFG_W4	0x49026650	0x0000[1]
	MBC3_DOM3_MEM1_BLK_CFG_W4	0x49026790
5	MBC3_DOM5_MEM0_BLK_CFG_W4	0x49026A50	0x9999[2]
	MBC3_DOM5_MEM1_BLK_CFG_W4	0x49026B90

1. 0x0000: Use GLBAC0 and NSE=0, which means no access for the non-secure status.
2. 0x9999: Use GLBAC1 and NSE=1, which means that the access of the non-secure status is granted.

MRC
MRC is used for the access control of external resources.
សម្រាប់អតីតample, in i.MX 93, a master with DID=3 only in the secure state (SP/SU) can perform the read/write/execute accesses to the DDR region from 0x80000000 to 0x9FFFFFFF.

បន្ទាប់មក៖

1. Find the DDR information in the MRC table:
   Table 7. DRAM MRC information

   លាយ	MRC instance	Slave memory	MRC descriptors
   NICMIX	0	DRAM	16

2. Find and configure the GLBAC:
   The base address of the NICMIX TRDC is 0x49010000.
   Table 8. GLBAC
   

   ចុះឈ្មោះ	អុហ្វសិត
   MRC0_MEMN_GLBAC0	0x18020
   MRC0_MEMN_GLBAC1	0x18024
   MRC0_MEMN_GLBAC2	0x18028
   MRC0_MEMN_GLBAC7	០x៤ ស៊ី

   Since one domain is required to have the read/write/execute access only in the SP (secure privilege) and SU (secure non-privilege) states, set the GLBAC0 as follows:
   Write 0x7700 to address 0x49028020: SPR=1, SPW=1, SPX=1, SUR=1, SUW=1, SUX=1, others are 0.

3. Write the MRC configuration registers:
   The MRC configuration register is MRC[m]_DOM[d]_RGD[r]_W[w], where:
   • a. m is the instance number, 0.
   • b. d is DID, DID=3.
   • c. r is the required region number. Configure one area, r=0.
   • d. w is the configuration word number. Word0 is used to specify the start address and select the GLBAC, while word1 is used to specify the end address and perform other functions.

Table 9. MRC DRAM configuration

ឌី	ចុះឈ្មោះ	អុហ្វសិត	អាស័យដ្ឋាន	តម្លៃ [0:15]
3	MRC0_DOM3_RGD0_W0	0x18340	0x49028340	0x80000000[1]
	MRC0_DOM3_RGD0_w1	0x18344	0x49028344	0x9FFFC011[2]

1. 0x80000000: Start address=0x80000000, use GLBAC0.
2. 0x9FFFC011: End address=0x9FFFFFFF, NSE=1, no access for non-secure, VLD=1.

កម្មវិធីកំណត់រចនាសម្ព័ន្ធ
If the chip does not use the System Manager software, such as i.MX 93 and i.MX 91, the TRDC can be configured by the Arm Trusted Firmware (ATF) software.
If the chip uses the System Manager software, such as i.MX 95 and i.MX 943, the TRDC can be configured by the System Manager software.

អេធីអេហ្វ
អេធីអេហ្វ provides the reference implementation of the secure world software. It contains the TRDC configurations.
In ATF, the TRDC is configured by the plat/imx/{SOC name}/trdc_config.h header file. នេះ។ file lists the MBC and MRC settings in each MIX, including the GLBAC, MBC, and MRC configuration tables.

GLBAC
The GLBAC structure is defined as follows:

It means that the GLBAC0 in AONMIX MBC1 is set to read/write for all statuses.
If you want other GLBACs, just append them in the corresponding variable array.

MBC
The MBC configuration table structure is defined as follows:

If the block number is set to this macro, it indicates that all blocks of this memory port are set to the same access permission. If there are other special memory block configurations in this memory port, you can append them in the configuration table, which overwrites the settings in the MBC BLK ALL. When adding or modifying the MBC configuration, see Section 3.1.2 in the register level to find the corresponding memory block information in the reference manual and append it to the existing configuration list.

MRC
The MRC configuration table structure is defined as follows:

The DID2 access to the WAKEUPMIX MRC1 region 0 (0x28000000~0x08000000) is set to GLBAC0 and the non-secure status access is not allowed.
When adding or modifying the MRC configuration, see Section 3.1.3 in the register level to find the corresponding memory area information in the reference manual and append it to the existing configuration list.

DAC
The DAC is configured by the ATF API interfaces, such as:

For the processor masters, the input parameters are, respectively: TRDC base address, master number, MDAC register number, SA, DIDS, DID, PE, PIDM, and PID.

អ្នកគ្រប់គ្រងប្រព័ន្ធ
នេះ។ អ្នកគ្រប់គ្រងប្រព័ន្ធ (SM) is a low-level system function which runs on a System Control Processor (SCP) to support the isolation and management of power domains, clocks, resets, sensors, pins, and others on complex application processors. It often runs on a Cortex-M processor. The SM is supported on processors like i.MX 943, i.MX 95, and others.

ការកំណត់រចនាសម្ព័ន្ធ file of the System Manager is located at configs/{platform}.cfg. It includes the configuration of the TRDC. This configuration file is not written in the C language but parsed in Perl. The parsing  script is configs/configtool.pl. Running “make config={platform} cfg” parses the configuration file and generates the corresponding C language configuration header file និងផ្សេងទៀត។ files. The TRDC header file is generated at configs/{platform}/config_trdc.h. This configuration file is divided using domains and Logical Machines (LM). Each domain and logical machine contains the corresponding masters and resources that correspond to the configuration of the TRDC.

សម្រាប់អតីតample, in the ELE domain:

The master DAC is configured in the did= field.
The GLBAC is defined in the perm= field, similar to macro definitions in the C language. The preset permission types are in the sm/doc/config.md {Configtool Resources} section. For example, sec_rw is equivalent to GLBAC=0x6600.
The # Resources and # Memory sections (respectively) specify the access permission settings of domains or logical machines for specific resources, that is, the MBC and MRC configurations.
សម្រាប់អតីតample, if the ELE needs access to the OCRAM on i.MX 95, add the following configuration to the ELE domain of configs/mx95evk.cfg:

ឧបករណ៍កំណត់រចនាសម្ព័ន្ធ
NXP also provides the ឧបករណ៍កំណត់រចនាសម្ព័ន្ធ MCUXpresso to configure the TRDC with a GUI interface for some chips. The TEE tool, which is used to generate the TRDC configuration, is a submodule in the MCUXpresso Config Tools. In the TEE tool, each module of the TRDC can be configured in the GUI interface. After the configuration is completed, the configuration header file can be exported to replace the TRDC configuration header file in the ATF or the TRDC source code file in the M-core SDK. The detailed user manual is in the installation location of the TEE tool.

អក្សរកាត់និងអក្សរកាត់

តារាង 10. អក្សរកាត់ និងអក្សរកាត់

អក្សរកាត់	និយមន័យ
ELE-AP	EdgeLock Secure Enclave, also called EdgeLock Secure Enclave (Advanced Profile) (ELE-AP)
TRDC	Trusted Resource Domain Controller
MBC	ឧបករណ៍ពិនិត្យប្លុកអង្គចងចាំ
MRC	Memory Region Checker
GLBAC	Global Access Control
អេធីអេហ្វ	Arm Trusted Firmware
SM	អ្នកគ្រប់គ្រងប្រព័ន្ធ
ធីអេ	Trusted Execution Environment

ឯកសារយោង

• i.MX 9x Reference Manual (available at www.nxp.com)
• System Manager Document (available at https://github.com/nxp-imx/imx-sm)

ចំណាំអំពីកូដប្រភពនៅក្នុងឯកសារ

Example កូដដែលបង្ហាញក្នុងឯកសារនេះមានសិទ្ធិរក្សាសិទ្ធិ និង BSD-3-Clause ដូចខាងក្រោម៖
រក្សាសិទ្ធិ 2025 NXP ការចែកចាយឡើងវិញ និងការប្រើប្រាស់ក្នុងទម្រង់ប្រភព និងប្រព័ន្ធគោលពីរ ដោយមានឬគ្មានការកែប្រែ ត្រូវបានអនុញ្ញាត ផ្តល់លក្ខខណ្ឌដូចខាងក្រោមត្រូវបានបំពេញ៖

1. ការចែកចាយឡើងវិញនៃកូដប្រភពត្រូវតែរក្សាការជូនដំណឹងអំពីការរក្សាសិទ្ធិខាងលើ បញ្ជីលក្ខខណ្ឌ និងការបដិសេធខាងក្រោម។
2. ការចែកចាយឡើងវិញក្នុងទម្រង់គោលពីរត្រូវតែបង្កើតឡើងវិញនូវការជូនដំណឹងអំពីការរក្សាសិទ្ធិខាងលើ បញ្ជីនៃលក្ខខណ្ឌនេះ និងការបដិសេធខាងក្រោមនៅក្នុងឯកសារ និង/ឬសម្ភារៈផ្សេងទៀតដែលបានផ្តល់ជាមួយនឹងការចែកចាយ។
3. ទាំងឈ្មោះអ្នករក្សាសិទ្ធិនិងឈ្មោះអ្នកចូលរួមរបស់វាមិនអាចត្រូវបានប្រើដើម្បីគាំទ្រឬផ្សព្វផ្សាយផលិតផលដែលបានមកពីកម្មវិធីនេះដោយគ្មានការអនុញ្ញាតជាលាយលក្ខណ៍អក្សរជាមុន។

កម្មវិធីនេះត្រូវបានផ្តល់ដោយអ្នកកាន់កាប់សិទ្ធិអ្នកនិពន្ធ និងអ្នករួមវិភាគទាន "ដូចដែលមាន" និងការធានាណាមួយដែលបញ្ជាក់ ឬដោយប្រយោល រួមទាំង ប៉ុន្តែមិនកំណត់ចំពោះ ការធានាដោយអត្ថន័យនៃទំនិញគ្រប់គ្រាន់ ត្រូវបានបដិសេធ។ ក្នុងករណីណាក៏ដោយ អ្នកកាន់កាប់សិទ្ធិថតចម្លង ឬអ្នករួមចំណែកត្រូវទទួលខុសត្រូវចំពោះការខូចខាតដោយផ្ទាល់ ប្រយោល ចៃដន្យ ពិសេស គំរូ ឬការខូចខាតជាលទ្ធផល (រួមទាំង ប៉ុន្តែមិនកំណត់ចំពោះផ្នែករដ្ឋបាល សេវាកម្ម ការបាត់បង់ការប្រើប្រាស់ ទិន្នន័យ ឬប្រាក់ចំណេញ ឬការរំខានអាជីវកម្ម) ទោះជាបណ្តាលមកពី និងលើទ្រឹស្ដីទំនួលខុសត្រូវណាមួយ ទោះជាក្នុងកិច្ចសន្យា ទំនួលខុសត្រូវយ៉ាងតឹងរ៉ឹង ឬការបង្ខិតបង្ខំ (រួមទាំងការបិទសិទ្ធិប្រើប្រាស់)។ ការ​ប្រើ​ប្រាស់​កម្មវិធី​នេះ ទោះ​បី​ជា​មាន​ការ​ណែនាំ​អំពី​លទ្ធភាព​នៃ​ការ​ខូច​ខាត​បែប​នេះ​ក៏​ដោយ។

ប្រវត្តិនៃការពិនិត្យឡើងវិញ

តារាង 11. ប្រវត្តិនៃការពិនិត្យឡើងវិញ

លេខសម្គាល់ឯកសារ	កាលបរិច្ឆេទចេញផ្សាយ	ការពិពណ៌នា
AN14721 v.1.0	ថ្ងៃទី 30 ខែមិថុនា ឆ្នាំ 2025	• កំណែដំបូង

ព័ត៌មានផ្លូវច្បាប់

និយមន័យ
សេចក្តីព្រាង - ស្ថានភាពព្រាងនៅលើឯកសារបង្ហាញថាខ្លឹមសារនៅតែស្ថិតក្រោមការកែប្រែផ្ទៃក្នុងview និងស្ថិតនៅក្រោមការយល់ព្រមជាផ្លូវការ ដែលអាចបណ្តាលឱ្យមានការកែប្រែ ឬបន្ថែម។ NXP Semiconductors មិនផ្តល់ការតំណាង ឬការធានាណាមួយអំពីភាពត្រឹមត្រូវ ឬពេញលេញនៃព័ត៌មានដែលរួមបញ្ចូលនៅក្នុងកំណែព្រាងនៃឯកសារ ហើយនឹងមិនទទួលខុសត្រូវចំពោះផលវិបាកនៃការប្រើប្រាស់ព័ត៌មាននោះទេ។

ការបដិសេធ

ការធានា និងការទទួលខុសត្រូវមានកំណត់ - ព័ត៌មាននៅក្នុងឯកសារនេះត្រូវបានគេជឿថាមានភាពត្រឹមត្រូវ និងអាចទុកចិត្តបាន។ ទោះជាយ៉ាងណាក៏ដោយ NXP Semiconductors មិនផ្តល់ការតំណាង ឬការធានាណាមួយដែលបានបង្ហាញ ឬបង្កប់ន័យចំពោះភាពត្រឹមត្រូវ ឬពេញលេញនៃព័ត៌មាននោះទេ ហើយនឹងមិនទទួលខុសត្រូវចំពោះផលវិបាកនៃការប្រើប្រាស់ព័ត៌មាននោះទេ។ NXP Semiconductors មិនទទួលខុសត្រូវចំពោះខ្លឹមសារនៅក្នុងឯកសារនេះទេ ប្រសិនបើផ្តល់ដោយប្រភពព័ត៌មាននៅខាងក្រៅ NXP Semiconductors។ នៅក្នុងព្រឹត្តិការណ៍ណាមួយ NXP Semiconductors នឹងមិនទទួលខុសត្រូវចំពោះការខូចខាតដោយប្រយោល ចៃដន្យ ការដាក់ទណ្ឌកម្ម ពិសេស ឬជាលទ្ធផល (រួមទាំង - ដោយគ្មានដែនកំណត់ - ប្រាក់ចំណេញដែលបាត់បង់ ការសន្សំដែលបាត់បង់ ការរំខានអាជីវកម្ម ការចំណាយទាក់ទងនឹងការដកចេញ ឬការជំនួសផលិតផល ឬថ្លៃការងារឡើងវិញ) ថាតើ ឬមិនមែនការខូចខាតបែបនេះគឺផ្អែកលើការធ្វើទារុណកម្ម (រួមទាំងការធ្វេសប្រហែស) ការធានា ការបំពានកិច្ចសន្យា ឬទ្រឹស្តីច្បាប់ផ្សេងទៀត។ ទោះបីជាការខូចខាតណាមួយដែលអតិថិជនអាចកើតឡើងដោយហេតុផលណាមួយក៏ដោយ ទំនួលខុសត្រូវសរុបរបស់ NXP Semiconductors ចំពោះអតិថិជនចំពោះផលិតផលដែលបានពិពណ៌នានៅទីនេះ នឹងត្រូវកំណត់ដោយអនុលោមតាមលក្ខខណ្ឌនៃការលក់ពាណិជ្ជកម្មរបស់ NXP Semiconductors ។

សិទ្ធិធ្វើការផ្លាស់ប្តូរ - NXP Semiconductors រក្សាសិទ្ធិដើម្បីធ្វើការផ្លាស់ប្តូរព័ត៌មានដែលបានបោះពុម្ពផ្សាយនៅក្នុងឯកសារនេះ រួមទាំងការពិពណ៌នាអំពីផលិតផលដោយគ្មានដែនកំណត់ គ្រប់ពេលវេលា និងដោយគ្មានការជូនដំណឹងជាមុន។ ឯកសារនេះជំនួស និងជំនួសព័ត៌មានទាំងអស់ដែលបានផ្តល់មុនការបោះពុម្ពផ្សាយនៅទីនេះ។

ភាពស័ក្តិសមសម្រាប់ការប្រើប្រាស់ - ផលិតផល NXP Semiconductors មិនត្រូវបានរចនា អនុញ្ញាត ឬធានាឱ្យមានលក្ខណៈសមរម្យសម្រាប់ប្រើប្រាស់ក្នុងការគាំទ្រជីវិត ប្រព័ន្ធ ឬឧបករណ៍ដែលមានសារៈសំខាន់សម្រាប់ជីវិត ឬសុវត្ថិភាព ឬនៅក្នុងកម្មវិធីដែលការបរាជ័យ ឬដំណើរការខុសប្រក្រតីនៃផលិតផល NXP Semiconductors អាចរំពឹងទុកដោយហេតុផលថានឹងមានលទ្ធផលនៅក្នុង ការរងរបួសផ្ទាល់ខ្លួន ការស្លាប់ ឬទ្រព្យសម្បត្តិធ្ងន់ធ្ងរ ឬការខូចខាតបរិស្ថាន។ NXP Semiconductors និងអ្នកផ្គត់ផ្គង់របស់ខ្លួនមិនទទួលខុសត្រូវចំពោះការដាក់បញ្ចូល និង/ឬការប្រើប្រាស់ផលិតផល NXP Semiconductors នៅក្នុងឧបករណ៍ ឬកម្មវិធីនោះទេ ដូច្នេះការដាក់បញ្ចូល និង/ឬការប្រើប្រាស់បែបនេះគឺស្ថិតក្នុងហានិភ័យផ្ទាល់ខ្លួនរបស់អតិថិជន។

កម្មវិធី — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default
នៅក្នុងកម្មវិធី ឬផលិតផលរបស់អតិថិជន ឬកម្មវិធី ឬប្រើប្រាស់ដោយអតិថិជនភាគីទីបីរបស់អតិថិជន។ អតិថិជនមានទំនួលខុសត្រូវក្នុងការធ្វើតេស្តចាំបាច់ទាំងអស់សម្រាប់កម្មវិធី និងផលិតផលរបស់អតិថិជនដោយប្រើផលិតផល NXP Semiconductors ដើម្បីជៀសវាងការបរាជ័យនៃកម្មវិធី និងផលិតផល ឬនៃកម្មវិធី ឬប្រើប្រាស់ដោយអតិថិជនភាគីទីបីរបស់អតិថិជន។ NXP មិនទទួលយកការទទួលខុសត្រូវណាមួយក្នុងន័យនេះទេ។

ល័ក្ខខ័ណ្ឌនៃការលក់ពាណិជ្ជកម្ម - ផលិតផល NXP Semiconductors ត្រូវបានលក់តាមលក្ខខណ្ឌទូទៅនៃការលក់ពាណិជ្ជកម្ម ដូចដែលបានចុះផ្សាយនៅ https://www.nxp.com/profile/លក្ខខណ្ឌ លុះត្រាតែមានការយល់ព្រមផ្សេងពីនេះក្នុងកិច្ចព្រមព្រៀងបុគ្គលដែលមានសុពលភាព។ ក្នុងករណីកិច្ចព្រមព្រៀងបុគ្គលត្រូវបានបញ្ចប់ មានតែលក្ខខណ្ឌនៃកិច្ចព្រមព្រៀងរៀងៗខ្លួនប៉ុណ្ណោះដែលត្រូវអនុវត្ត។ NXP Semiconductors សម្តែងការជំទាស់ចំពោះការអនុវត្តលក្ខខណ្ឌទូទៅរបស់អតិថិជនទាក់ទងនឹងការទិញផលិតផល NXP Semiconductors ដោយអតិថិជន។

ការត្រួតពិនិត្យការនាំចេញ - ឯកសារនេះក៏ដូចជាធាតុដែលបានពិពណ៌នានៅទីនេះអាចជាកម្មវត្ថុនៃបទប្បញ្ញត្តិត្រួតពិនិត្យការនាំចេញ។ ការនាំចេញអាចទាមទារការអនុញ្ញាតជាមុនពីអាជ្ញាធរមានសមត្ថកិច្ច។

ភាពស័ក្តិសមសម្រាប់ប្រើប្រាស់ក្នុងផលិតផលដែលមិនមានគុណភាពសម្រាប់រថយន្ត — Unless this document expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

ការបោះពុម្ព HTML - កំណែ HTML នៃឯកសារនេះត្រូវបានផ្តល់ជូនជាការគួរសម។ ព័ត៌មានច្បាស់លាស់មាននៅក្នុងឯកសារដែលអាចអនុវត្តបានជាទម្រង់ PDF ។ ប្រសិនបើមានភាពមិនស្របគ្នារវាងឯកសារ HTML និងឯកសារ PDF នោះឯកសារ PDF មានអាទិភាព។

ការបកប្រែ - កំណែដែលមិនមែនជាភាសាអង់គ្លេស (បកប្រែ) នៃឯកសារ រួមទាំងព័ត៌មានផ្លូវច្បាប់នៅក្នុងឯកសារនោះ គឺសម្រាប់ជាឯកសារយោងតែប៉ុណ្ណោះ។ កំណែជាភាសាអង់គ្លេសនឹងមានសុពលភាពក្នុងករណីមានភាពខុសគ្នារវាងកំណែដែលបានបកប្រែ និងភាសាអង់គ្លេស។

សន្តិសុខ — Customer understands that all NXP products may be subject to unidentified vulnerabilities or may support established security standards or specifications with known limitations. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) ដែលគ្រប់គ្រងការស៊ើបអង្កេត ការរាយការណ៍ និងការចេញផ្សាយដំណោះស្រាយចំពោះភាពងាយរងគ្រោះផ្នែកសុវត្ថិភាពនៃផលិតផល NXP ។
NXP B.V. — NXP B.V. មិនមែនជាក្រុមហ៊ុនប្រតិបត្តិការទេ ហើយវាមិនចែកចាយ ឬលក់ផលិតផលទេ។

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សេចក្តីជូនដំណឹង៖ ម៉ាកដែលបានយោងទាំងអស់ ឈ្មោះផលិតផល ឈ្មោះសេវាកម្ម និងពាណិជ្ជសញ្ញា គឺជាកម្មសិទ្ធិរបស់ម្ចាស់រៀងៗខ្លួន។
NXP - ពាក្យ និងនិមិត្តសញ្ញាគឺជាពាណិជ្ជសញ្ញារបស់ NXP BV

AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, μVision, Versatile — គឺជាពាណិជ្ជសញ្ញា និង/ឬពាណិជ្ជសញ្ញាដែលបានចុះបញ្ជីរបស់ Arm Limited (ឬសាខា ឬសាខារបស់វា) នៅសហរដ្ឋអាមេរិក និង/ឬ កន្លែងផ្សេងទៀត។ បច្ចេកវិទ្យាដែលពាក់ព័ន្ធអាចត្រូវបានការពារដោយប៉ាតង់ ការរក្សាសិទ្ធិ ការរចនា និងអាថ៌កំបាំងពាណិជ្ជកម្មណាមួយ។ រក្សា​រ​សិទ្ធ​គ្រប់យ៉ាង។

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រក្សាសិទ្ធិគ្រប់យ៉ាង។

មតិកែលម្អឯកសារ

Date of release: 30 June 2025 Document identifier: AN14721

សំណួរគេសួរញឹកញាប់

• Q: What are the main components of TRDC in i.MX Devices?
  A: TRDC consists of Domain Assignment Controller (DAC), Memory Block Checker (MBC), and Memory Region Checker (MRC).
• Q: How does the DAC assign attributes to the master?
  A: The DAC assigns Domain ID (DID), privileged mode, and secure status to the master based on the access signal.

ឯកសារ/ធនធាន

NXP AN14721 Development Board [pdf] សៀវភៅណែនាំ i.MX 91, i.MX 93, i.MX 8ULP, i.MX 9, AN14721 Development Board, AN14721, Development Board, Board

ឯកសារយោង

• សៀវភៅណែនាំអ្នកប្រើប្រាស់