MICROCHIP AN5978 Polar Fire FPGA Splash Kit User Guide

The DATA_HANDLE_0 block interfaces with the GUI to select PRBS
or waveform input.
The selected input is forwarded to the DATA_GENERATOR_0 block
for data generation.

The data is sent to the CoreJESD204BTX IP core for transmitter
មុខងារ។
The transmitted data is received by the CoreJESD204BRX IP core
for receiver functions.

Data errors or link errors selected on the GUI are generated by
the error generator block.

សំណួរគេសួរញឹកញាប់

Q: What software versions are needed to create the reference
រចនា?

A: For all software versions required, refer to the readme.txt
file ផ្តល់ជូននៅក្នុងការរចនា files.

សំណួរ៖ តើខ្ញុំអាចធ្វើដូចម្តេច view the selected input on the GUI?

A: The GUI displays the selected input when connected to the
CoreJESD204BRX IP core.

“`

View Fullscreen

PolarFire FPGA Splash Kit JESD204B Standalone Interface Application Note
AN5978
សេចក្តីផ្តើម (សួរសំណួរ)
This document describes how to run the JESD204B standalone demo design on the PolarFire® Splash Board
using the JESD204B Standalone Demo GUI application. The GUI application is packaged along with the design files. The demo design is a reference design built using the PolarFire high-speed transceiver blocks and the CoreJESD204BTX and CoreJESD204BRX IP cores. It operates in Loopback mode by sending the CoreJESD204BTX data to the CoreJESD204BRX IP core through the transceiver lanes, which are looped back on the board. This loopback setup facilitates a standalone JESD interface demo that does not require Analog-to-Digital Converter (ADC) or Digital-to-Analog Converters (DAC).
Microchip PolarFire devices have embedded, high-speed transceiver blocks that can handle data rates ranging from 250 Mbps to 12.5 Gbps. The transceiver (PF_XCVR) module integrates several functional blocks to support multiple high-speed serial protocols within the FPGA. JESD204B is a high-speed serial interface standard for data converters developed by the JEDEC committee. The JESD204B standard reduces the number of data inputs and outputs between the high-speed data converters and receivers.
Microchip provides CoreJESD204BTX and CoreJESD204BRX IP cores that implement the transmitter and receiver interfaces of the JESD204B standard. These IP cores are easy to integrate with JESD204B- based data converters to develop high-bandwidth applications such as wireless infrastructure transceivers, software-defined radios, medical imaging systems, and radar and secure communications. These IP cores support link widths from x1 to x4, and link rates from 250 Mbps to 12.5 Gbps per lane using subclass 0, 1 and 2.
For more information about the JESD204B interface design implementation, and all the necessary blocks and IP
cores instantiated in Libero® SoC, see Demo Design.
The JESD204B standalone interface design can be programmed using any of the following options: · Using the .job file៖ ដើម្បីសរសេរកម្មវិធីឧបករណ៍ដោយប្រើ .job file ផ្តល់ជូនជាមួយនឹងការរចនា files មើល
Programming the Device Using FlashPro Express. · Using Libero SoC: To program the device using Libero SoC, see Running the Demo Design. Use this option
when the demo design is modified.

ចំណាំកម្មវិធី
© 2025 Microchip Technology Inc. និងក្រុមហ៊ុនបុត្រសម្ព័ន្ធរបស់ខ្លួន។

DS00005978A – 1

AN5978
តារាងមាតិកា
Introduction……………………………………………………………………………………………………………………………………………………… 1 1. Design Requirements………………………………………………………………………………………………………………………………… 3 2. Prerequisites……………………………………………………………………………………………………………………………………………… 4 3. Demo Design………………………………………………………………………………………………………………………………………………5
3.1. Design Implementation…………………………………………………………………………………………………………………….5 3.2. IP Configuration………………………………………………………………………………………………………………………………. 6 4. Clocking Structure……………………………………………………………………………………………………………………………………. 10 5. Reset Structure………………………………………………………………………………………………………………………………………… 11
6. Simulating the PolarFire® JESD204B Design……………………………………………………………………………………………… 12
6.1. Simulation Flow………………………………………………………………………………………………………………………………13 7. Setting Up the Demo……………………………………………………………………………………………………………………………….. 15 8. Programming the Device Using FlashPro Express…………………………………………………………………………………….. 17 9. Running the Demo…………………………………………………………………………………………………………………………………… 19
9.1. Installing the GUI…………………………………………………………………………………………………………………………….19 9.2. Running the Demo Design………………………………………………………………………………………………………………19 10. Appendix A: References…………………………………………………………………………………………………………………………….25 11. Appendix B: Running the TCL Script…………………………………………………………………………………………………………. 26 12. Revision History……………………………………………………………………………………………………………………………………….. 27 Microchip FPGA Support………………………………………………………………………………………………………………………………….28 Microchip Information……………………………………………………………………………………………………………………………………. 28 Trademarks……………………………………………………………………………………………………………………………………………… 28 Legal Notice………………………………………………………………………………………………………………………………………………28 Microchip Devices Code Protection Feature………………………………………………………………………………………………29

ចំណាំកម្មវិធី
© 2025 Microchip Technology Inc. និងក្រុមហ៊ុនបុត្រសម្ព័ន្ធរបស់ខ្លួន។

DS00005978A – 2

AN5978 Design Requirements

តម្រូវការរចនា (សួរសំណួរ)

The following table lists the resources required to run the demo.

តារាង 1-1 ។ តម្រូវការរចនា
Requirement Operating System
ផ្នែករឹង
PolarFire® Splash Kit with MPF300T-1FCG484E device
Software FlashPro Express GUI executable (provided with the design files)
Libero® SoC

កំណែ
Windows® 10 and 11
Rev 2 or later
For all the software versions needed to create this reference design, see readme.txt file ផ្តល់ជូននៅក្នុងការរចនា files.

ចំណាំកម្មវិធី
© 2025 Microchip Technology Inc. និងក្រុមហ៊ុនបុត្រសម្ព័ន្ធរបស់ខ្លួន។

DS00005978A – 3

AN5978 Prerequisites

តម្រូវការជាមុន (សួរសំណួរ)

មុនពេលអ្នកចាប់ផ្តើម សូមអនុវត្តជំហានខាងក្រោម៖
· Download and install Libero® SoC (as indicated in the website for this design) on the host PC
from Libero SoC Documentation.

· Download the demo design files from www.microchip.com/en-us/application-notes/an5978.

· Install the GUI application by running the setup.exe file មាននៅក្នុងការរចនា files folder: <$Design_Files_Directory>/mpf_an5978_df/GUI
At the end of the installation, you may be prompted to download and install the FPGA_GUI_Pack, if it is not already available on your system.

· Alternatively, you can manually download and install the Microchip FPGA_GUI_Pack.

Important:A Libero® Gold license is required to evaluate your designs using the PolarFire® Splash Kit.

ចំណាំកម្មវិធី
© 2025 Microchip Technology Inc. និងក្រុមហ៊ុនបុត្រសម្ព័ន្ធរបស់ខ្លួន។

DS00005978A – 4

AN5978 Demo Design

ការរចនាម៉ូដសាកល្បង (សួរសំណួរ)

The PolarFire® JESD204B demo design is developed to interface JESD204B-compliant data
converters with PolarFire devices. The design functions as follows:

1. The DATA_HANDLE_0 block interfaces with the GUI. The GUI enables the selection of either PRBS or waveform input.

2. The DATA_HANDLE_0 block forwards the input selection to the DATA_GENERATOR_0 block, which generates and sends the corresponding input data to the CoreJESD204BTX IP core.

3. The CoreJESD204BTX IP core performs JESD204B transmitter functions based on the configuration and transmits the data to the PF_XCVR (transceiver) IP core.

4. The encoded data is received by the CoreJESD204BRX IP core because the TX and RX lanes of the PF_XCVR block are looped back.

5. The CoreJESD204BRX IP core performs JESD204B receiver functions based on the configuration and transmits the data to the GUI for viewing the selected input.

Important:When a data error or link error is selected on the GUI, the error generator block generates that error and displays it on the GUI.

The following figure shows the hardware implementation of the JESD204B interface demo. Figure 3-1. Hardware Implementation Block Diagram

JESD204B_GUI

ក្រណាត់

DATA HANDLE

ម៉ាស៊ីនបង្កើតទិន្នន័យ

Core JESD204BTX

PRBS Checker

LINK ERROR GENERATOR
Core JESD204BRX

Lane 0 TX XCVR
Lane 0 RX

TXD_P, TXD_N RXD_P, RXD_N

PF_TPSRAM (Data Buffer)

PF_TPSRAM (Status Buffer)

LED_DEBUG_BLK

០១.

Design Implementation (Ask a Question)
The following figure shows the Libero® design implementation of the JESD204B interface demo.

ចំណាំកម្មវិធី
© 2025 Microchip Technology Inc. និងក្រុមហ៊ុនបុត្រសម្ព័ន្ធរបស់ខ្លួន។

DS00005978A – 5

Figure 3-2. JESD204B Interface Design

AN5978 Demo Design

The following table lists the important input and output signals of the design.

តារាង 3-1 ។ សញ្ញាបញ្ចូលនិងទិន្នផល
Signal Input Signals LANE0_RXD_P and LANE0_RXD_N ARST_N RX REF_CLK_PAD_P_0 and REF_CLK_PAD_N_0 SEL_IN[3:0] Output Signals LANE0_TXD_P and LANE0_TXD_N LED_OUT[7:0] TX

ការពិពណ៌នា
Transceiver receiver differential inputs External reset obtained from push button switch on board Receiver of UART interface Differential reference clock obtained from the on-board 125 MHz oscillator
Signal mapped to DIPs 1, 2, 3 and 4 of SW8 dip slide switch used to debug the status and errors
Transceiver transmitter differential outputs Signal that indicates whether link is up or down Transmitter of UART interface

០១.

IP Configuration (Ask a Question)
The hardware design for the JESD204B interface includes the following blocks.

០១.

Data Handle (Ask a Question)
The data handle (DATA_HANDLE_0) block receives the input data selection and link or data error generation information from the GUI. This block also sends the data output received from the CoreJESD204BRX core and the data or link status error to the GUI for viewing.

០១.

Data Generator (Ask a Question)
The data generator has a PRBS generator and a waveform generator. The PRBS generator generates PRBS7, PRBS15, PRBS23 and PRBS31 patterns. An error insertion mode implemented in the PRBS generator inserts an error into the PRBS sequence. The waveform generator generates sine, sawtooth, triangle and square waveforms. The data generator feeds a 64-bit test pattern to the JESD204BTX core, which subsequently transmits the data to the transceiver.

ចំណាំកម្មវិធី
© 2025 Microchip Technology Inc. និងក្រុមហ៊ុនបុត្រសម្ព័ន្ធរបស់ខ្លួន។

DS00005978A – 6

០១.

AN5978 Demo Design
PF_TPSRAM (Ask a Question)
There are two instances of PF_TPSRAM blocks, the PF_TPSRAM_C0 block stores the JESD204B link status before sending it to the GUI. The PF_TPSRAM_C1 block stores the data received from the CoreJESD204BRX before sending the data to the GUI.

០១.

Error Generator (Ask a Question)
The error generator block (ERR_GEN_0) generates link errors by sending random data between CoreJESD204BTX and PF_XCVR when link error generation is selected in the GUI.

០១.

PRBS_checker (Ask a Question)
The data checker receives 64-bit data from the CoreJESD204BRX IP core and checks whether the received data is correct. It generates an error count and a status signal, which are transmitted to the GUI for status indication. The data checker exclusively checks the PRBS sequences generated by the data generator.

០១.

LED Debug (Ask a Question)
The LED debug block (LED_DEBUG_BLK_0) debugs the JESD204B link status and other errors. When the link is up, LEDs 1, 2, 3, 4, 5 and 6 glow, while LEDs 7 and 8 do not glow (with DIP 1, 2, 3 and 4 are set to low on the SW8 dip slide switch).

០១.

Init_monitor (Ask a Question)
When the DEVICE_INIT_DONE signal from Init_monitor block goes high, the transceiver is completely configured. This signal is anded with ARST_N signal to get proper reset signal for the design.

០១.

CORERESET_PF (Ask a Question)
CoreReset_PF synchronizes resets to the user-specified clock domain. This ensures that while the assertion is asynchronous, the negation is synchronous with the clock.

០១.

CoreJESD204BTX (Ask a Question)
CoreJESD204BTX is the transmitter interface of the JEDEC JESD204B standard. For this demo design,
this IP core is configured in Libero®, as shown in the following figure.

Figure 3-3. CoreJESD204BTX Configurator

ចំណាំកម្មវិធី
© 2025 Microchip Technology Inc. និងក្រុមហ៊ុនបុត្រសម្ព័ន្ធរបស់ខ្លួន។

DS00005978A – 7

For more information about CoreJESD204BTX, see CoreJESD204BTX Handbook.

AN5978 Demo Design

3.2.10. CoreJESD204BRX (Ask a Question)
CoreJESD204BRX is the receiver interface of the JEDEC JESD204B standard. For this demo design, this
IP core is configured in Libero®, as shown in the following figure.
ចំណាំ៖ ទៅ view the complete configuration, open the configurator of IP from within the design.

Figure 3-4. CoreJESD204BRX Configurator

For more information about CoreJESD204BRX, see CoreJESD204BRX Handbook.

០១.

Transceiver Interface (Ask a Question) The PolarFire® high-speed transceiver (PF_XCVR) is a hard IP block designed to support high-speed
data rates ranging from 250 Mbps to 12.5 Gbps. In this demo, the transceiver block (PF_XCVR) is configured in 8b10b mode with a Clock Data Recovery (CDR) reference clock of 125 MHz to support 5.0 Gbps data rate.

The PolarFire transmit PLL (PF_TX_PLL) provides the reference clock feed to the transceiver. The dedicated reference clock (PF_XCVR_REF_CLK) drives the PF_TX_PLL to generate the desired output clock for the 5.0 Gbps data rate.

រូបខាងក្រោមបង្ហាញពីការកំណត់រចនាសម្ព័ន្ធចំណុចប្រទាក់ឧបករណ៍ចាប់សញ្ញា។

ចំណាំ៖ ទៅ view the complete configuration, open the configurator of IP from within the design.

ចំណាំកម្មវិធី
© 2025 Microchip Technology Inc. និងក្រុមហ៊ុនបុត្រសម្ព័ន្ធរបស់ខ្លួន។

DS00005978A – 8

Figure 3-5. Transceiver Interface Configurator

AN5978 Demo Design

ចំណាំកម្មវិធី
© 2025 Microchip Technology Inc. និងក្រុមហ៊ុនបុត្រសម្ព័ន្ធរបស់ខ្លួន។

DS00005978A – 9

AN5978 Clocking Structure

រចនាសម្ព័ន្ធនាឡិកា (សួរសំណួរ)

In the reference design, there are three clock domains:

· RX_CLK (125 MHz)

· TX_CLK (125 MHz) · FAB_REF_CLK (125 MHz)

The on-board 125-MHz crystal oscillator drives the XCVR reference clock, which provides clock to the DATA_GENERATOR, CoreJESD204BTX, ERR_GEN, CoreJESD204BRX, LED_DEBUG, PRBS_CHECKER, TPSRAM C0 & C1 and DATA_HANDLE.

Important:If there is a change in the data rate or reference clock of the transceiver, you must reconfigure COREUART.

The following figure shows the clocking structure. Figure 4-1. Clocking Structure

Clock Domain 1
On-Board 125 MHz Crystal Oscillator

DATA_GENERATOR

LANE0_TX_CLK_R

PF_XCVR_REF_CLK
REF_CLK
PF_TX_PLL
CLKS_TO_XCVR
PF_XCVR

CDR CLK

FAB_REF_CLK

អាន

DATA_HANDLE

TPSRAM 0 and 1

LANE0_RX_CLK_R WRITE

ERR_GEN

COREJESD204BTX

COREJESD204BRX

TPSRAM 0 and 1

PRBS_CHECKER

LED_DEBUG_BLK

ចំណាំកម្មវិធី
© 2025 Microchip Technology Inc. និងក្រុមហ៊ុនបុត្រសម្ព័ន្ធរបស់ខ្លួន។

DS00005978A – 10

AN5978 Reset Structure

កំណត់រចនាសម្ព័ន្ធឡើងវិញ (សួរសំណួរ)

The DEVICE_INIT_DONE and external reset signal ARST_N are mapped to pin N4 on the Splash Kit. These signals initiate the system reset (FABRIC_RESET_N) through the res_syn_0 block.

The FABRIC_RESET_N signal from the res_syn_0 block provides a direct reset to the following modules:
· CoreJESD204BRX

· CoreJESD204BTX · PF_XCVR (LANE0_PMA_ARST_N)

Additionally, FABRIC_RESET_N is connected to the reset synchronizer block, which distributes synchronized reset signals to the following functional blocks:
· prbs_checker

· DATA_HANDLE · DATA_GENERATOR

· ERR_GEN · LED_DEBUG_BLK

RX_RESET_N output from the CoreJESD204BRX module supplies reset signals to: · LANE0_PCS_ARST_N input of the PF_XCVR_0 module · LED_DEBUG block (EPCS_0_RX_RESET_N)

រូបខាងក្រោមបង្ហាញពីរចនាសម្ព័ន្ធកំណត់ឡើងវិញ។

រូបភាពទី 5-1 ។ កំណត់រចនាសម្ព័ន្ធឡើងវិញ

PF_INIT_MONITOR

DEVICE_INIT_DONE

Reset_syn_0

ARST_N (N4)

FABRIC_RESET_N

reset_synchronizer

CoreJESD204BTX

PF_XCVR

CoreJESD204BRX

prbs_checker

DATA_HANDLE DATA_GENERATOR

ERR_GEN

LED_DEBUG_BLK

RX_RESET_N

PF_XCVR

EPCS_0_RX_RESET_N
LED_DEBUG_BLK

ចំណាំកម្មវិធី
© 2025 Microchip Technology Inc. និងក្រុមហ៊ុនបុត្រសម្ព័ន្ធរបស់ខ្លួន។

DS00005978A – 11

AN5978 Simulating the PolarFire® JESD204B Design

Simulating the PolarFire® JESD204B Design (Ask a Question)

ដើម្បីក្លែងធ្វើការរចនា សូមអនុវត្តជំហានខាងក្រោម៖
1. Start Libero®, and select Project > Tool Profileស….

2. In the Tool Profiles window, select Synthesis and Simulation on the Tools panes and select the latest active installation directory paths for these two tools.

For Simulation, browse the design files folder, create Libero Project using provided TCL scripts, and click Simulate as highlighted in the Figure 6-2. For more information, see Appendix B: Running the TCL Script.

A testbench is provided to simulate the JESD204B PRBS pattern and waveform selection. The following figure shows the interaction between testbench and the design.

Figure 6-1. Testbench and JESD204B Demo Design Interaction

P_W_SEL PRBS_SEL WAVE_SEL ERR_EN NSYSRESET SYSCLK
TB_DATA_OUT TB_RX_SOMF TB_RX_SOF TB_SYNC_N TB_ALIGNED

JESD204B Top Block (DUT)

ម៉ាស៊ីនបង្កើតទិន្នន័យ
កម្មវិធីពិនិត្យទិន្នន័យ

Core JESD204BTx
Core JESD204BRx

Lane 0 Tx Transceiver Lane 0 Rx

TB_LINK_CD_ERR

TB_UCC_ERR TB_NIT_ERR TB_DISP_ERR TB_CGS_ERR TB_RX_READY

TB_0_BAD

TB_0_ERROR

កៅអីសាកល្បង

TXD2P, TXD2N Loopback
RXD2P, RXD2N

The testbench generates the test selection for the PRBS input (PRBS7, PRBS15, PRBS23 and PRBS31) and waveform input (sine wave, sawtooth wave, triangle wave and square wave). It also monitors the JESD204B output status signals (SYNC_N, ALIGNED and CGS_ERR) for the verification of JESD204B phases, and PRBS checker output status signals O_BAD and O_ERROR[4:0].
To simulate the design, in the Design Flow tab, double-click Simulate under Verify PreSynthesized Design. The Simulate option is highlighted in the following figure.

ចំណាំកម្មវិធី
© 2025 Microchip Technology Inc. និងក្រុមហ៊ុនបុត្រសម្ព័ន្ធរបស់ខ្លួន។

DS00005978A – 12

Figure 6-2. Simulating the Design

AN5978 Simulating the PolarFire® JESD204B Design

When the simulation is initiated, simulation tool compiles all the design source files, runs the simulation, and configures the waveform viewer to show the simulation signals.
Note:In certain cases, a prompt may appear asking for the selection of an active stimulus before starting the simulation. To resolve this, navigate to the Stimulus Hierarchy, right-click PF_JESD204B_SA_TOP_TB_8b (top.v) and select Set as Active Stimulus, as shown in the following figure.
Figure 6-3. Set As Active Stimulus

០១.

Simulation Flow (Ask a Question)
The following steps describe the JESD204B testbench simulation flow: 1. At the start, the NSYSRESET signal resets all of the components. 2. After the transceiver block is initialized, the TB_RX_READY signal is asserted high. 3. The JESD204BRX issues a synchronization request by driving the TB_SYNC_N pin low. 4. The JESD204BRX block checks the k28.5 characters transmitted by the JESD204BTX block. 5. The CGS and ILA phase starts after the TB_SYNC_N signal is asserted high. 6. The testbench checks whether the CGS_ERR signal asserts low or not, and completes the code
group synchronization phase. 7. The JESD204BRX link asserts the TB_SYNC_N signal to high. 8. After the successful completion of the CGS phase, the JESD204BTX block starts the Initial Lane
Alignment (ILA) sequence by transmitting four multi-frames in the following sequence: First frame at TB_TX_SOMF = 0x8 Second frame at TB_TX_SOMF = 0x2 Third frame at TB_TX_SOMF = 0x8

ចំណាំកម្មវិធី
© 2025 Microchip Technology Inc. និងក្រុមហ៊ុនបុត្រសម្ព័ន្ធរបស់ខ្លួន។

DS00005978A – 13

AN5978 Simulating the PolarFire® JESD204B Design
Fourth frame at TB_TX_SOMF = 0x2 9. The JESD204BRX link starts receiving four multi-frames in the following sequence:
First frame at TB_TX_SOMF = 0x8 Second frame at TB_TX_SOMF = 0x2 Third frame at TB_TX_SOMF = 0x8 Fourth frame at TB_TX_SOMF = 0x2 10. The ILA phase test passes if all JESD204BRX DATA_OUT is properly received with frame alignment. 11. After successful completion of the ILA phase, the JESD204BTX block enters into the data phase. 12. In the data phase, the following data is fed to the JESD204BTX block: PRBS7, PRBS15, PRBS23 and PRBS31 using the PRBS generator. 13. Sine, Square, Saw and triangular waves are generated from the waveform generator. 14. The PRBS checker checks the received PRBS pattern against the expected PRBS pattern. 15. The waveform output can be viewed in the simulation window on corresponding wave selection as shown in Figure 6-5. 16. If the data checker does not detect any error, the testbench issues a TESTBENCH PASSED message stating that the simulation was successful. If an error is detected, the testbench issues a TESTBENCH FAILED message to indicate that the testbench has failed.
While the simulation is running, you can see the status of the test cases in the Transcript window of ModelSim, as shown in the following figure.
Figure 6-4. Transcript Window

After simulation, the Waveform window displays the simulation waveforms as shown in the following figure.
Note:You may notice some warnings in the log. These appear because UART is not used in the simulation. The simulation is focused only on JESD, while UART and RAM are included for GUI purposes.
Figure 6-5. Simulation Waveform Window

SYNC_N Deassertion

CGS and ILA

PRBS Sequence: PRBS 7, 15, 25, 31

Waveforms: Sine, Square, Sawtooth, Triangle

ចំណាំកម្មវិធី
© 2025 Microchip Technology Inc. និងក្រុមហ៊ុនបុត្រសម្ព័ន្ធរបស់ខ្លួន។

DS00005978A – 14

AN5978 Setting Up the Demo

ដំឡើងការសាកល្បង (សួរសំណួរ)

After generating the bitstream, the PolarFire® device must be programmed. To program the

PolarFire device, perform the following steps:

1. Ensure that the jumper settings on the board are same as listed in the following table.

តារាង 7-1 ។ ការកំណត់ Jumper

ការពិពណ៌នាអំពី Jumper

J11

Close pin 1 and 2 for programming through the FTDI chip.

Open pin 1 and 2 for programming through an external FlashPro4 or FlashPro5 device.

Default Closed

Jumper to select the core voltage.

Close pin 1 and 2 for 1.05 V.

Open pin 1 and 2 for 1.0 V.

បើក

J10

Close pin 1 and 2 for programming through the external SPI flash.

If J10 is open, it allows SPI slave programming using the FTDI chip.

បើក

2. Connect the power supply cable to the J2 connector on the board. 3. Connect the USB cable from the host PC to the J1 (FTDI port) on the board. 4. Power On the board using the SW1 slide switch.
When the board is powered up, power supply LEDs 1 to 4 glow. For more information about LEDs on the PolarFire Splash Board, see UG0786: PolarFire FPGA Splash Kit User Guide. 5. In Libero Design Flow tab, double-click Run PROGRAM Action.

ទៅ view កំណត់ហេតុដែលត្រូវគ្នា។ file, navigate to Reports tab, right-click Run Program Action and select View រាយការណ៍។

When the device is successfully programmed, a green tick mark appears as shown in the following figure. For information about how to run the JESD204B standalone demo, see Running the Demo.

ចំណាំកម្មវិធី
© 2025 Microchip Technology Inc. និងក្រុមហ៊ុនបុត្រសម្ព័ន្ធរបស់ខ្លួន។

DS00005978A – 15

Figure 7-1. Device Programming Completed

AN5978 Setting Up the Demo

ចំណាំកម្មវិធី
© 2025 Microchip Technology Inc. និងក្រុមហ៊ុនបុត្រសម្ព័ន្ធរបស់ខ្លួន។

DS00005978A – 16

AN5978 Programming the Device Using FlashPro Express
8. Programming the Device Using FlashPro Express (Ask a Question)
This section describes how to program the PolarFire® device with the programming job file
ដោយប្រើ FlashPro Express ។ ការងារ file មាននៅការរចនាខាងក្រោម files folder location: mpf_an5978_df/Programming_Files/top.job.
To program the device, perform the following steps: 1. On the host PC, launch the FlashPro Express software. 2. To create a new project, click New or New Job Project from FlashPro Express Job from Project
menu. 3. Enter the following in the New Job Project from FlashPro Express Job dialog box:
Programming job file៖ ចុច រកមើល ហើយរុករកទៅទីតាំងដែលការងារ file មានទីតាំងនៅហើយជ្រើសរើស file. The default location is: mpf_an5978_df/Programming_Files/ top.job.
FlashPro Express job project location: Click Browse and navigate to the FlashPro Express project location.
Figure 8-1. New Job Project from FlashPro Express Job

4. ចុចយល់ព្រម។ ការសរសេរកម្មវិធីដែលត្រូវការ file ត្រូវបានជ្រើសរើស និងត្រៀមខ្លួនជាស្រេចដើម្បីដាក់កម្មវិធីនៅក្នុងឧបករណ៍។
5. The FlashPro Express window appears, as shown in the following figure. Confirm that a programmer number appears in the Programmer field. If not, confirm the board connections and click Refresh/Rescan Programmers.

DS00005978A – 17

រូបភាពទី 8-2 ។ ការសរសេរកម្មវិធីឧបករណ៍

AN5978 Programming the Device Using FlashPro Express

6. Click RUN. When the device is programmed successfully, a RUN PASSED status is displayed as shown in the following figure.
Figure 8-3. FlashPro Express–RUN PASSED

7. Close FlashPro Express or click Exit in the Project tab.

DS00005978A – 18

AN5978 Running the Demo

9.
០១.
០១.

ដំណើរការសាកល្បង (សួរសំណួរ)
This section describes how to use the JESD204B GUI to run the JESD204B demo on the PolarFire®
Splash Board.
Installing the GUI (Ask a Question)
To run the demo, install the JESD204B GUI. The GUI allows selection of different PRBS test patterns as input, and displays the JESD204B status signals and the PRBS status received from the board. The Waveform tab of the GUI displays the output waveforms received from the board for each waveform selected as input.
To install the GUI, perform the following steps: 1. Install the JESD204B_GUI application (setup.exe) from the following design files folder:
mpf_an5978_df/GUI.
2. To start the GUI application, double-click the JESD204B_GUI application from the installation directory.
Running the Demo Design (Ask a Question)
To run the JESD204B demo, perform the following steps:
1. Connect the jumpers and set up the PolarFire® Splash Board as described in steps 1 to 4 of
Setting Up the Demo.
2. In Device Manager on the host PC, note the COM port associated with the USB serial converter C. To determine the COM port, check the Location field in the properties of each COM port.
3. On the Start menu of the host PC, click JESD204B_GUI.
4. From the list of COM ports, select the COM port identified in the step 2, and click Connect, as shown in the following figure.
Figure 9-1. COM Port Selection

DS00005978A – 19

Important:Port numbers may vary. In this example, COM port 32 is the correct port to select.

AN5978 Running the Demo

After successful connection, the Host Connection indicator turns green, as shown in the following figure.
Figure 9-2. Successful Host Connection

The following table lists the status signals displayed in the JESD204B GUI.

Table 9-1. Status Signals in JESD204B GUI

សញ្ញា

ការពិពណ៌នា

Host Connection Shows the UART communication status.

ស្ថានភាពតំណ

Shows the communication link status between TX and RX.

SYNC_N

Indicates the JESD204B status.

បានតម្រឹម

Indicates that all transceiver lanes are aligned.

RX VALID

Indicates that RX data is valid. In 8b10b mode, indicates that comma alignment has occurred and the CDR is locked.

PRBS Status

Indicates PRBS error.

ចំនួនកំហុស

Provides the number of errors that occurred during PRBS check

CGS_ERR

Indicates a code group synchronization error.

NIT_ERR

Indicates a “not in table” error.

DISP_ERR

Indicates a disparity error.

LINK_CD_ERR Indicates a link configuration data mismatch.

UCC_ERR

Indicates an “unexpected control character” error.

5. From the Input Selection list, select the pattern to be transmitted, and click START, as shown in the following figure.

DS00005978A – 20

Figure 9-3. Pattern Selection

AN5978 Running the Demo

The selected pattern is sent over the serial transmit link and received by CoreJESD204BRX, which checks for errors. At any time, the JESD204B status can be monitored using the status signals on the GUI, as shown in the following figure.
Figure 9-4. Link Status and JESD204B Status

6. To generate an error in the PRBS data, click Generate Data Error. The PRBS Status indicator turns red, and the Error Count field displays the number of errors, as shown in the following figure.

DS00005978A – 21

Figure 9-5. Data Error

AN5978 Running the Demo

7. Click Clear Error to clear the errors in the PRBS data and reset the PRBS status. The PRBS Status indicator turns green, and the Error Count changes to 0, as shown in the following figure.
Figure 9-6. Data Error Cleared

8. To generate a link error between CoreJESD204BTX and the transceiver lane, click Generate Link Error.
The Link Status, SYNC_N, ALIGNED, RX VALID, DISP_ERR and CGS_ERROR indicators turn red, as shown in the following figure.

DS00005978A – 22

Figure 9-7. Link Error

AN5978 Running the Demo

9. To clear the link error, click Clear Error. The status indicators turn green, as shown in the following figure.
Figure 9-8. Clear Link Error

10. To change the pattern, select Triangle from the Input Selection list. The selected pattern is sent over the serial transmit link and received by CoreJESD204BRX. At any time, the JESD204B status can be monitored using the status signals on the GUI.
11. ទៅ view the waveform received from CoreJESD204BRX, click the Waveform tab, as shown in the following figure.

DS00005978A – 23

Figure 9-9. Triangle Waveform

AN5978 Running the Demo

12. To end the demo, click Stop and close the GUI.

DS00005978A – 24

AN5978 Appendix A: References

០១.

Appendix A: References (Ask a Question)
This section lists documents that provide more information about the JESD204B standard and IP cores used in the demo design.
· For information about the JESD204B interface standard, visit the JEDEC webគេហទំព័រ។
· For information about PolarFire transceiver blocks, PF_TX_PLL and PF_XCVR_REF_CLK, see PolarFire Family Transceiver User Guide.
· For more information about PF_TPSRAM (PF Micro SRAM), see PolarFire Family Fabric User Guide.
· For more information about CoreJESD204BTX, see CoreJESD204BTX Handbook.
· For more information about CoreJESD204BRX, see CoreJESD204BRX Handbook.
· For more information about Libero, ModelSim and Synplify, see the Microchip Libero SoC webទំព័រ។

DS00005978A – 25

AN5978 Appendix B: Running the TCL Script

០១.

Appendix B: Running the TCL Script (Ask a Question)
ស្គ្រីប TCL ត្រូវបានផ្តល់ជូននៅក្នុងការរចនា fileថតឯកសារនៅក្រោមថត HW ។ ប្រសិនបើចាំបាច់ លំហូរនៃការរចនាអាចត្រូវបានផលិតឡើងវិញពីការអនុវត្តការរចនារហូតដល់ជំនាន់នៃការងារ file. To run the TCL, perform the following steps:
1. Launch the Libero® software.
2. Select Project > Execute Script….
3. Click Browse and select script.tcl from the downloaded HW directory.
4. Click Run.
After successful execution of TCL script, Libero project is created within HW directory. For more information about TCL scripts, see mpf_an5978_df/HW/TCL_Script_readme.txt.
For more details on TCL commands, see TCL Commands Reference Guide. For any queries encountered when running the TCL script, contact Technical Support.

DS00005978A – 26

AN5978 ប្រវត្តិកែប្រែ

០១.

ប្រវត្តិនៃការកែប្រែ (សួរសំណួរ)
ប្រវត្តិនៃការកែប្រែពិពណ៌នាអំពីការផ្លាស់ប្តូរដែលត្រូវបានអនុវត្តនៅក្នុងឯកសារ។ ការផ្លាស់ប្តូរត្រូវបានរាយបញ្ជីដោយការកែប្រែ ដោយចាប់ផ្តើមជាមួយនឹងការបោះពុម្ពបច្ចុប្បន្ន។

ការពិនិត្យឡើងវិញអេ

កាលបរិច្ឆេទ 08/2025

Description The following is the list of changes made in the revision A of the document: · The document was migrated to the Microchip template. · The document number was updated from 50200796 to DS00005978. · The document ID was updated from DG0796 to AN5978.

3.0

—

This document is updated with respect to Libero® SoC PolarFire v2.2 release.

2.0

—

This document is updated with respect to Libero SoC PolarFire v2.1 release.

1.0

—

ការបោះពុម្ពលើកដំបូងនៃឯកសារនេះ។

DS00005978A – 27

AN5978

ការគាំទ្រ Microchip FPGA
ក្រុមផលិតផល Microchip FPGA គាំទ្រផលិតផលរបស់ខ្លួនជាមួយនឹងសេវាកម្មគាំទ្រផ្សេងៗ រួមទាំងសេវាអតិថិជន មជ្ឈមណ្ឌលជំនួយបច្ចេកទេសអតិថិជន ក webគេហទំព័រ និងការិយាល័យលក់ទូទាំងពិភពលោក។ អតិថិជនត្រូវបានស្នើឱ្យចូលមើលធនធានលើបណ្តាញ Microchip មុនពេលទាក់ទងផ្នែកជំនួយព្រោះវាទំនងណាស់ដែលសំណួររបស់ពួកគេត្រូវបានឆ្លើយរួចហើយ។
ទាក់ទងមជ្ឈមណ្ឌលគាំទ្របច្ចេកទេសតាមរយៈ webគេហទំព័រ www.microchip.com/support ។ រៀបរាប់លេខផ្នែកឧបករណ៍ FPGA ជ្រើសរើសប្រភេទករណីដែលសមស្រប និងការរចនាបង្ហោះ files ខណៈពេលដែលបង្កើតករណីជំនួយបច្ចេកទេស។
ទាក់ទងផ្នែកបម្រើអតិថិជនសម្រាប់ការគាំទ្រផលិតផលដែលមិនមែនជាបច្ចេកទេស ដូចជាតម្លៃផលិតផល ការធ្វើឱ្យប្រសើរផលិតផល ព័ត៌មានបច្ចុប្បន្នភាព ស្ថានភាពការបញ្ជាទិញ និងការអនុញ្ញាត។
· មកពីអាមេរិកខាងជើង ហៅទៅ 800.262.1060
· ពីជុំវិញពិភពលោក ទូរស័ព្ទទៅ 650.318.4460
· ទូរសារពីគ្រប់ទិសទីក្នុងពិភពលោក 650.318.8044
ព័ត៌មានមីក្រូឈីប
ពាណិជ្ជសញ្ញា
ឈ្មោះ និងស្លាកសញ្ញា "Microchip" និមិត្តសញ្ញា "M" និងឈ្មោះផ្សេងទៀត និមិត្តសញ្ញា និងម៉ាកនានាត្រូវបានចុះបញ្ជី និងមិនបានចុះបញ្ជីពាណិជ្ជសញ្ញានៃ Microchip Technology Incorporated ឬសាខា និង/ឬក្រុមហ៊ុនបុត្រសម្ព័ន្ធរបស់ខ្លួននៅសហរដ្ឋអាមេរិក និង/ឬប្រទេសផ្សេងទៀត ("Microchip Trademarks")។ ព័ត៌មានទាក់ទងនឹងពាណិជ្ជសញ្ញា Microchip អាចរកបាននៅ https://www.microchip.com/en-us/about/legalinformation/microchip-trademarks ។
ISBN: 979-8-3371-1709-6
សេចក្តីជូនដំណឹងផ្លូវច្បាប់
ការបោះពុម្ពផ្សាយនេះ និងព័ត៌មាននៅទីនេះអាចប្រើតែជាមួយផលិតផល Microchip ប៉ុណ្ណោះ រួមទាំងការរចនា សាកល្បង និងរួមបញ្ចូលផលិតផល Microchip ជាមួយកម្មវិធីរបស់អ្នក។ ការប្រើប្រាស់ព័ត៌មាននេះក្នុងលក្ខណៈផ្សេងទៀតបំពានលក្ខខណ្ឌទាំងនេះ។ ព័ត៌មានទាក់ទងនឹងកម្មវិធីឧបករណ៍ត្រូវបានផ្តល់ជូនសម្រាប់ភាពងាយស្រួលរបស់អ្នកប៉ុណ្ណោះ ហើយអាចត្រូវបានជំនួសដោយការអាប់ដេត។ វាជាទំនួលខុសត្រូវរបស់អ្នកក្នុងការធានាថាកម្មវិធីរបស់អ្នកត្រូវនឹងលក្ខណៈជាក់លាក់របស់អ្នក។ ទាក់ទងការិយាល័យលក់ Microchip ក្នុងតំបន់របស់អ្នកសម្រាប់ការគាំទ្របន្ថែម ឬទទួលបានជំនួយបន្ថែមនៅ www.microchip.com/en-us/support/design-help/ client-support-services។
ព័ត៌មាននេះត្រូវបានផ្តល់ដោយមីក្រូឈីប “ដូចដែល”។ មីក្រូឈីបមិនតំណាងឱ្យ ឬការធានានៃប្រភេទណាមួយឡើយ ទោះជាបញ្ជាក់ ឬបង្កប់ន័យ សរសេរ ឬផ្ទាល់មាត់ លក្ខន្តិកៈ ឬបើមិនដូច្នេះទេ ពាក់ព័ន្ធនឹងព័ត៌មានដែលរួមបញ្ចូល ប៉ុន្តែមិនកំណត់ចំពោះពេលវេលា ការមិនបំពានលើការលក់ដូរ និងភាពសមស្របសម្រាប់គោលបំណងពិសេស ឬការធានាទាក់ទងនឹងលក្ខខណ្ឌ គុណភាព ឬប្រតិបត្តិការរបស់វា។
នៅក្នុងករណីគ្មានមីក្រូឈីបនឹងទទួលខុសត្រូវចំពោះការខូចខាតដោយអចេតនា ពិសេស ការដាក់ទណ្ឌកម្ម ឧប្បត្តិហេតុ ឬជាផលវិបាកនៃការបាត់បង់ ការខូចខាត ថ្លៃដើម ឬការចំណាយនៃប្រភេទណាមួយដែលទាក់ទងនឹងការប្រើប្រាស់ ឬស្ថានភាពប្រែប្រួល មីក្រូឈីបត្រូវបានណែនាំពីលទ្ធភាព ឬការខូចខាតគឺអាចមើលបាន ក្នុងវិសាលភាពពេញលេញបំផុតដែលច្បាប់អនុញ្ញាត ការទទួលខុសត្រូវសរុបរបស់មីក្រូឈីប លើការទាមទារទាំងអស់ តាមរបៀបណាក៏ដោយ ដែលទាក់ទងនឹងព័ត៌មាន ឬការប្រើប្រាស់របស់វា នឹងមិនលើសពីចំនួននៃថ្លៃសេវានោះទេ ប្រសិនបើមាន ដែលអ្នកមាន ព័ត៌មាន។
ការប្រើប្រាស់ឧបករណ៍ Microchip នៅក្នុងកម្មវិធីជំនួយអាយុជីវិត និង/ឬកម្មវិធីសុវត្ថិភាពគឺស្ថិតក្នុងហានិភ័យរបស់អ្នកទិញទាំងស្រុង ហើយអ្នកទិញយល់ព្រមការពារ ទូទាត់សំណង និងកាន់ Microchip ដែលគ្មានគ្រោះថ្នាក់ពីការខូចខាត ការទាមទារ ការប្តឹងផ្តល់ ឬការចំណាយដែលបណ្តាលមកពីការប្រើប្រាស់បែបនេះ។ គ្មានអាជ្ញាប័ណ្ណណាមួយត្រូវបានបញ្ជូនដោយប្រយោល ឬបើមិនដូច្នេះទេ នៅក្រោមកម្មសិទ្ធិបញ្ញារបស់ Microchip ណាមួយ លើកលែងតែមានចែងផ្សេងពីនេះ។

DS00005978A – 28

AN5978
មុខងារការពារលេខកូដឧបករណ៍មីក្រូឈីប
ចំណាំព័ត៌មានលម្អិតខាងក្រោមនៃមុខងារការពារកូដនៅលើផលិតផល Microchip៖
· ផលិតផល Microchip បំពេញតាមលក្ខណៈជាក់លាក់ដែលមាននៅក្នុងសន្លឹកទិន្នន័យ Microchip ជាក់លាក់របស់ពួកគេ។ · Microchip ជឿជាក់ថាផលិតផលគ្រួសាររបស់វាមានសុវត្ថិភាពនៅពេលប្រើក្នុងលក្ខណៈដែលបានគ្រោងទុក
លក្ខណៈបច្ចេកទេសនៃប្រតិបត្តិការ និងក្រោមលក្ខខណ្ឌធម្មតា។ · តម្លៃមីក្រូឈីប និងការពារយ៉ាងចាស់ដៃនូវសិទ្ធិកម្មសិទ្ធិបញ្ញារបស់វា។ ការប៉ុនប៉ងរំលោភបំពាន
មុខងារការពារកូដនៃផលិតផល Microchip ត្រូវបានហាមឃាត់យ៉ាងតឹងរ៉ឹង ហើយអាចបំពានច្បាប់រក្សាសិទ្ធិសហស្សវត្សរ៍ឌីជីថល។ · ទាំង Microchip ឬក្រុមហ៊ុនផលិត semiconductor ផ្សេងទៀតមិនអាចធានាសុវត្ថិភាពនៃកូដរបស់វាបានទេ។ ការការពារលេខកូដមិនមានន័យថាយើងធានាថាផលិតផល "មិនអាចបំបែកបាន" នោះទេ។ ការការពារលេខកូដកំពុងវិវត្តឥតឈប់ឈរ។ មីក្រូឈីបបានប្តេជ្ញាចិត្តក្នុងការធ្វើឱ្យប្រសើរឡើងជាបន្តបន្ទាប់នូវមុខងារការពារកូដនៃផលិតផលរបស់យើង។

DS00005978A – 29

ឯកសារ/ធនធាន

MICROCHIP AN5978 Polar Fire FPGA Splash Kit [pdf] ការណែនាំអ្នកប្រើប្រាស់
AN5978 Polar Fire FPGA Splash Kit, AN5978, Polar Fire FPGA Splash Kit, Fire FPGA Splash Kit, FPGA Splash Kit, Splash Kit

ឯកសារយោង

សៀវភៅណែនាំអ្នកប្រើប្រាស់

AN5978 Polar Fire FPGA Splash Kit

ព័ត៌មានអំពីផលិតផល

លក្ខណៈបច្ចេកទេស

ការណែនាំអំពីការប្រើប្រាស់ផលិតផល

តម្រូវការរចនា

តម្រូវការជាមុន

ការរចនាម៉ូដសាកល្បង

សំណួរគេសួរញឹកញាប់

Q: What software versions are needed to create the reference រចនា?

សំណួរ៖ តើខ្ញុំអាចធ្វើដូចម្តេច view the selected input on the GUI?

ឯកសារ/ធនធាន

ឯកសារយោង

ទុកមតិយោបល់

បោះបង់ការឆ្លើយតប

Q: What software versions are needed to create the reference
រចនា?