intel FPGA Integer Arithmetic IP Cores Guide User

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1 FPGA Integer Arithmetic IP Cores

2 Akwụkwọ / akụrụngwa

2.1 Ntụaka

3 Ozi ndị metụtara

FPGA Integer Arithmetic IP Cores

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Ntuziaka onye ọrụ Intel FPGA Integer Arithmetic IP Cores
Emelitere maka Intel® Quartus® Prime Design Suite: 20.3

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NJ: 683490 Ụdị: 2020.10.05

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1. Intel FPGA Integer Arithmetic IP Cores……………………………………………………………………………………….. 5
2. LPM_COUNTER (Counter) IP isi……………………………………………………………………………………………………….. 7 2.1. Atụmatụ……………………………………………………………………………………………………………………………… Ụdị Verilog HDL……………………………………………………………………………………………………………………… Nkwuwapụta akụkụ VHDL……………………………………………………………………………………………………….7 2.2. Nkwupụta VHDL LIBRARY_USE……………………………………………………………………………………………………………… Ọdụ ụgbọ mmiri ………………………………………………………………………………………………………………………………………………………… Oke …………………………………………………………………………………………………………………………………………………………………………………………………………………
3. Lpm_Divide) Intel Intel intelE Intel :....................................................... .. 12 3.1. Akụkụ……………………………………………………………………………………………………………………………… 12 3.2. Ụdị Verilog HDL……………………………………………………………………………………………………………………………………………………………………… Nkwuwapụta akụkụ VHDL……………………………………………………………………………………….. 12 3.3. Nkwuwapụta VHDL LIBRARY_USE……………………………………………………………………………………………… 13 3.4. Ọdụ ụgbọ mmiri ………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………… Oke …………………………………………………………………………………………………………………………………………………………………………………………………………………………
4. LPM_MULT (Multiplier) IP isi……………………………………………………………………………………………………………… 16 4.1. Akụkụ……………………………………………………………………………………………………………………………… 16 4.2. Prototype Verilog HDL……………………………………………………………………………………………………………………………………………………………………………………………… Nkwuwapụta akụkụ VHDL………………………………………………………………………………………….. 17 4.3. Nkwuwapụta VHDL LIBRARY_USE……………………………………………………………………………………………… 17 4.4. Akara………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………… Oke maka Stratix V, Arria V, Cyclone V na Intel Cyclone 17 LP Ngwaọrụ………………… 4.5 18. Taabụ izugbe…………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………… Isi 4.6 Tab……………………………………………………………………………………………………………………………………………………………………………………………………………………………………… Mpempe akwụkwọ………………………………………………………………………………………………………………………………………………………………………………………………………… Parameters maka Intel Stratix 10, Intel Arria 18 na Intel Cyclone 4.6.1 GX Ngwaọrụ….. 18 4.6.2. Taabụ izugbe………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………… Ozuruọnụ 2 Tab……………………………………………………………………………………………………………………………………………………………………………………… Pipelin …………………………………………………………………………………………………………………………………………………………………
5. LPM_ADD_SUB (Adder/Subtractor)………………………………………………………………………………………………………………………………………………………………………………… Akụkụ……………………………………………………………………………………………………………………………… 22 5.1. Prototype Verilog HDL……………………………………………………………………………………………………………………………………………………………………… Nkwuwapụta akụkụ VHDL……………………………………………………………………………………….. 22 5.2. Nkwuwapụta VHDL LIBRARY_USE……………………………………………………………………………………………… 23 5.3. Ọdụ ụgbọ mmiri ………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………… Oke …………………………………………………………………………………………………………………………………………………………………………………………………………
6. LPM_COMPARE (Comparator)………………………………………………………………………………………………………………………………………………… Akụkụ……………………………………………………………………………………………………………………………… 26 6.1. Prototype Verilog HDL……………………………………………………………………………………………………………………………………………………………………………………………………… Nkwuwapụta akụkụ VHDL……………………………………………………………………………………….. 26 6.2. Nkwuwapụta VHDL LIBRARY_USE……………………………………………………………………………………………… 27 6.3. Ọdụ ụgbọ mmiri ………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………… Oke …………………………………………………………………………………………………………………………………………………………………………………………………………………………

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7. ALTECC (Igodo mgbazi mperi: Encoder/Decoder) IP isi……………………………………………… 30
7.1. Ihe ngbanwe ALTECC………………………………………………………………………………………………………..31 7.2. Prototype HDL Verilog (ALTECC_ENCODER)……………………………………………………………………………… 32 7.3. Prototype HDL Verilog (ALTECC_DECODER)……………………………………………………………………………………… 32 7.4. Nkwuwapụta akụrụngwa VHDL (ALTECC_ENCODER)……………………………………………………………………………… Nkwuwapụta akụrụngwa VHDL (ALTECC_DECODER)……………………………………………………………………… Nkwuwapụta VHDL LIBRARY_USE……………………………………………………………………………………………… 33 7.5. Ọdụ ụgbọ mmiri………………………………………………………………………………………………………………………………………… Ports decoder……………………………………………………………………………………………………………………………………………………… Mpempe ihe ngbanwe……………………………………………………………………………………………………………………………………………… 33 7.6. Mpempe ihe ndozi …………………………………………………………………………………………………………………………………………………………………………………………
8. Intel FPGA Multiply Adder IP Core………………………………………………………………………………………………………………………… 36
8.1. Akụkụ……………………………………………………………………………………………………………………………… 37 8.1.1. Pre-addder……………………………………………………………………………………………………………………………….. 38 8.1.2. Ndebanye aha igbu oge systolic……………………………………………………………………………………….. 40 8.1.3. Constant ebububuru………………………………………………………………………………………………………………………………… 43 8.1.4. Mgbakọ okpukpu abụọ………………………………………………………………………………………………………………………………………………………
8.2. Ụdị Verilog HDL……………………………………………………………………………………………………………………………………………………… Nkwuwapụta akụkụ VHDL……………………………………………………………………………………….. 44 8.3. Nkwuwapụta VHDL LIBRARY_USE……………………………………………………………………………………………… 44 8.4. Akara………………………………………………………………………………………………………………………………………………………………………………………………………………………… Oke …………………………………………………………………………………………………………………………………………………………………………………………………………………………
8.6.1. Taabụ izugbe……………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………… Taabụ mgbakwunye……………………………………………………………………………………………….. 47 8.6.2. Taabụ multipliers………………………………………………………………………………………………………………………….. 47 8.6.3. Taabụ Pread……………………………………………………………………………………………………………………… 49 8.6.4. Tab na-akwakọba………………………………………………………………………………………………………….. 51 8.6.5. Systolic/Chainout Tab……………………………………………………………………………………………………………… 53 8.6.6. Mpempe akwụkwọ…………………………………………………………………………………………………………………………………………………………………………………………………
9. ALTMEMMULT (Mmiri nke dabere na ebe nchekwa) IP isi……………………………… 57
9.1. Akụkụ……………………………………………………………………………………………………………………………… 57 9.2. Ụdị Verilog HDL……………………………………………………………………………………………………………………………………………………………………………………… Nkwuwapụta akụkụ VHDL……………………………………………………………………………………….. 58 9.3. Ọdụ ụgbọ mmiri ………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………… Oke …………………………………………………………………………………………………………………………………………………………………………………………………………
10. ALTMULT_ACCUM (Multiply-Accumulate) IP isi………………………………………………………………
10.1. Atụmatụ………………………………………………………………………………………………………………………….. 62 10.2. Ụdị Verilog HDL………………………………………………………………………………………………………..62 10.3. Nkwuwapụta akụkụ VHDL……………………………………………………………………………………………… 63 10.4. Nkwuwapụta VHDL LIBRARY_USE………………………………………………………………………………………….63 10.5. Ọdụ ụgbọ mmiri……………………………………………………………………………………………………………………………………… 63 10.6. Parameter……………………………………………………………………………………………………………………… 64
11. ALTMULT_ADD (Multiply-Adder) IP isi………………………………………………………………………………………………..69
11.1. Atụmatụ………………………………………………………………………………………………………………………….. 71 11.2. Ụdị Verilog HDL………………………………………………………………………………………………..72 11.3. Nkwuwapụta akụkụ VHDL……………………………………………………………………………………… 72 11.4. Nkwuwapụta VHDL LIBRARY_USE………………………………………………………………………………………….72

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11.5. Ọdụ ụgbọ mmiri……………………………………………………………………………………………………………………………………… 72 11.6. Parameter……………………………………………………………………………………………………………………… 73
12. ALTMULT_COMPLEX (Mgbagwoju anya Multiplier) IP isi……………………………………………………………………… 86 12.1. Mgbakwụnye Mgbakwụnye………………………………………………………………………………………………………………………… 86 12.2. Nnọchi anya nke akwụkwọ nsọ……………………………………………………………………………………………………………………… 87 12.3. Nnọchiteanya Ochie……………………………………………………………………………………………………… 87 12.4. Atụmatụ………………………………………………………………………………………………………………………………….. 88 12.5. Ụdị Verilog HDL………………………………………………………………………………………………………..88 12.6. Nkwuwapụta akụkụ VHDL……………………………………………………………………………………………………… 89 12.7. Nkwuwapụta VHDL LIBRARY_USE………………………………………………………………………………………………………….89 12.8. Akara……………………………………………………………………………………………………………………………………………… 89 12.9. Parameter……………………………………………………………………………………………………………………… 90
13. ALTSQRT (Integer Square Root) IP isi………………………………………………………………………………………………………… Atụmatụ………………………………………………………………………………………………………………………….. 92 13.1. Ụdị Verilog HDL………………………………………………………………………………………………………..92 13.2. Nkwuwapụta akụkụ VHDL……………………………………………………………………………………………… 92 13.3. Nkwuwapụta VHDL LIBRARY_USE………………………………………………………………………………………………….93 13.4. Ọdụ ụgbọ mmiri……………………………………………………………………………………………………………………………………… 93 13.5. Parameter……………………………………………………………………………………………………………………………… 93
14. PARALLEL_ADD (Parallel Adder) IP isi……………………………………………………………………………….. 95 14.1. Njirimara……………………………………………………………………………………………………………………………………………….95 14.2. Ụdị Verilog HDL………………………………………………………………………………………………………..95 14.3. Nkwuwapụta akụkụ VHDL……………………………………………………………………………………………… 96 14.4. Nkwuwapụta VHDL LIBRARY_USE……………………………………………………………………………………………….96 14.5. Ọdụ ụgbọ mmiri……………………………………………………………………………………………………………………………………… 96 14.6. Parameter……………………………………………………………………………………………………………………… 97
15. Ndekọ akwụkwọ ntuziaka onye ọrụ integer Arithmetic IP Cores……………………………………………………………… 98
16. Document Revision History maka Intel FPGA Integer Arithmetic IP Cores Guide User…. 99

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1. Intel FPGA Integer Arithmetic IP Cores

Ị nwere ike iji Intel® FPGA integer IP cores rụọ ọrụ mgbakọ na mwepụ n'ime imewe gị.

Ọrụ ndị a na-enye njikọ mgbagha na mmejuputa ngwaọrụ dị mma karịa itinye koodu ọrụ nke gị. Ị nwere ike hazie cores IP iji nabata ihe ị chọrọ ime.

A na-ekewa ọnụọgụ ọnụọgụ IP nke integer n'ime ụzọ abụọ a: · Library of parameterized modules (LPM) IP cores · Intel-specific (ALT) IP cores.

Tebụlụ na-esonụ na-edepụta cores IP integer mgbakọ na mwepụ.

Tebụl 1.

Ndepụta nke IP Cores

Ndị isi IP

LPM IP isi

LPM_COUNTER

LPM_DIVIDE

LPM_MULT

LPM_ADD_SUB
LPM_COMPARE
Imirikiti Intel-Specific (ALT) IP cores ALTECC

Emechaala Ọrụview Mkpokọta nkesa
Adder ma ọ bụ mwepu Comparator
ECC Encoder/Decoder

Ngwaọrụ akwadoro
Arria® II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone® IV E, Cyclone IV GX, Cyclone V, Intel Cyclone 10 LP,
Intel Cyclone 10 GX, MAX® II, MAX V, MAX 10, Stratix® IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX 10, Stratix IV, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX 10, Stratix IV, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Cyclone IV E, Cyclone IV GX, Cyclone V, Intel Cyclone 10 LP, MAX 10, MAX
II, MAX V, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Cyclone IV E, Cyclone IV GX, Cyclone V, Intel Cyclone 10 LP, MAX 10, MAX
II, MAX V, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V gara n'ihu…

Ụlọ ọrụ Intel. Ikike niile echekwabara. Intel, akara Intel, na akara Intel ndị ọzọ bụ ụghalaahịa nke Intel Corporation ma ọ bụ ndị enyemaka ya. Intel nyere ikike ịrụ ọrụ nke FPGA na ngwaahịa semiconductor na nkọwapụta ugbu a dịka akwụkwọ ikike ọkọlọtọ Intel siri dị, mana nwere ikike ịme mgbanwe na ngwaahịa na ọrụ ọ bụla n'oge ọ bụla na-enweghị ọkwa. Intel anaghị ewere ọrụ ọ bụla ma ọ bụ ụgwọ sitere na ngwa ma ọ bụ iji ozi ọ bụla, ngwaahịa ma ọ bụ ọrụ akọwara n'ime ebe a belụsọ dị ka Intel kwetara na ederede. A dụrụ ndị ahịa Intel ọdụ ka ha nweta ụdị nkọwa ngwaọrụ kachasị ọhụrụ tupu ha adabere na ozi ọ bụla ebipụtara yana tupu ịnye iwu maka ngwaahịa ma ọ bụ ọrụ. * Enwere ike ịzọrọ aha na akara ndị ọzọ dị ka ihe onwunwe nke ndị ọzọ.

ISO 9001: 2015 edebanye aha

1. Intel FPGA Integer Arithmetic IP Cores 683490 | 2020.10.05

IP Cores Intel FPGA Multiply Adder ma ọ bụ ALTERA_MULT_ADD ALTMEMMULT
ALTMULT_ACCUM ALTMULT_ADD ALTMULT_COMPLEX
ALTSQRT
PARALLEL_ADD

Emechaala Ọrụview Multiplier-Adder
Ọnụọgụ ọnụọgụgụ ọnụọgụgụ dabere na ebe nchekwa
Multiplier-Accumulator Multiplier-Adder
Mgbakwụnye Multiplier
Integer Square-Root
Mgbakwunye Adder

Ngwaọrụ akwadoro
Arria V, Stratix V, Cyclone V, Intel Stratix 10, Intel Arria 10, Intel Cyclone
10 GX
Arria II GX, Arria II GZ, Arria V, Intel Arria 10 (Intel Quartus® Prime Standard Edition), Cyclone IV E, Cyclone IV GX, Cyclone V, Intel
Cyclone 10 LP, MAX II, MAX V, MAX 10, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Cyclone IV E, Cyclone IV GX, Intel Cyclone 10 LP, MAX 10, MAX II, MAX V, Stratix IV
Arria II GX, Arria II GZ, Cyclone IV E, Cyclone IV GX, Intel Cyclone 10 LP, MAX 10, MAX II, MAX V, Stratix IV
Arria II GX, Arria II GZ, Intel Arria 10, Arria V, Arria V GZ, Cyclone IV E, Cyclone IV GX, Cyclone V, Intel
Cyclone 10 GX, Intel Cyclone 10 LP, MAX 10, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V

Ozi metụtara
· Ndetu mwepụta nke FPGA nke Intel na ngwa mmemme
· Okwu mmalite nke Intel FPGA IP Cores na-enye ozi ndị ọzọ gbasara Intel FPGA IP Cores.
Ntuziaka onye ọrụ floating-Point IP Cores na-enye ozi ndị ọzọ gbasara cores IP FPGA floating-Point.
· Okwu mmalite nke Intel FPGA IP Cores na-enye ozi izugbe gbasara cores IP Intel FPGA niile, gụnyere parameterizing, imepụta, nkwalite, na ịmegharị cores IP.
· Ịmepụta ụdịdị IP nọọrọ onwe ya na scripts Simulation Mepụta script simulation nke na-achọghị mmelite akwụkwọ ntuziaka maka nkwalite ngwanrọ ma ọ bụ ụdị IP.
· Ntuziaka kachasị mma nke njikwa ọrụ maka njikwa ọrụ nke ọma na ibugharị nke ọrụ gị na IP files.
Ndekọ ndekọ ndekọ aha onye ọrụ dị na ibe 98 Integer Arithmetic IP Cores na-enye ndepụta ntuziaka onye ọrụ maka ụdị mbụ nke Integer Arithmetic IP cores.

Ntuziaka onye ọrụ Intel FPGA Integer Arithmetic IP Cores 6

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2. LPM_COUNTER (Akara) IP isi

Onyonyo 1.

LPM_COUNTER IP core bụ ọnụọgụ ọnụọgụ abụọ na-emepụta ọnụ ọgụgụ, ọnụ ọgụgụ ala na ọnụ ọgụgụ elu ma ọ bụ ala nwere mpụta ruru 256 n'obosara.

Ọnụọgụ ndị a na-egosi ọdụ ụgbọ mmiri maka LPM_COUNTER IP isi.

Ọdụ ụgbọ mmiri LPM_COUNTER

LPM_COUNTER

data ssclr sload[]

q[]

emelite

kwuputa

aclr ebu ihe

clk_en cnt_en cin
inst

2.1. Atụmatụ
LPM_COUNTER IP isi na-enye atụmatụ ndị a: · Na-emepụta ọnụ ọgụgụ elu, ala, na elu/ala · Na-emepụta ụdị counter ndị a:
- ọnụọgụ abụọ dị larịị - mmụba nke counter na-amalite site na efu ma ọ bụ mbelata malite na 255
- Modulus – counter na-abawanye ma ọ bụ na-ebelata site na uru modulu nke onye ọrụ akọwapụtara wee kwugharịa.
Na-akwado nhọrọ synchronous n'ụzọ doro anya, ibu, na tọọ ọdụ ọdụ ntinye · Na-akwado nhọrọ asynchronous doro anya, ibu, na ịtọ ọdụ ụgbọ mmiri ntinye.

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2. LPM_COUNTER (Akara) IP isi
683490 | 2020.10.05
2.2. Prototype Verilog HDL
Ụdị Verilog HDL ndị a dị na Verilog Design File (.v) lpm.v n'ime edesynthesis ndekọ.
modul lpm_counter (q, data, clock, cin, cout, clk_en, cnt_en, updown, aset, aclr, aload, sset, sclr, sload, eq); oke lpm_type = "lpm_counter"; oke lpm_width = 1; oke lpm_modul = 0; paramita lpm_direction = "UJI ejighị ya"; paramita lpm_avalue = "EJIGHỊ"; paramita lpm_svalue = "EJIGHỊ"; paramita lpm_pvalue = "EJIGHỊ"; oke lpm_port_updown = "PORT_CONNECTIVITY"; paramita lpm_hint = "EJIGHỊ"; mmepụta [lpm_width-1:0] q; mmepụta ihe; mmepụta [15:0] eq; ntinye cin; ntinye [lpm_width-1:0] data; elekere ntinye, clk_en, cnt_en, mgbada; ntinye aset, aclr, ibu; ntinye ntinye, sclr, sload; endmodule
2.3. Nkwupụta akụkụ VHDL
Nkwupụta akụrụngwa VHDL dị na Nhazi VHDL File (.vhd) LPM_PACK.vhd n'ime akwụkwọ ndekọ aha vhdllpm.
akụrụngwa LPM_COUNTER jeneriki ( LPM_WIDTH : eke; LPM_MODULUS : eke: = 0; LPM_DIRECTION : eriri : = "A naghị eji ya eme ihe "; LPM_AVALUE : eriri : = " ejighi ya "; LPM_SVALUE : eriri : = " ejighi ya eme ihe "; LPM_PORT "PORT_CONNECTIVITY"; LPM_PVALUE : eriri: = "EJIGHỊ"; LPM_TYPE : eriri: = L_COUNTER; ọdụ ụgbọ mmiri (DATA: na std_logic_vector(LPM_WIDTH-1 ruo 0): = (Ndị ọzọ =>
'0'); Elekere : na std_logic ; CLK_EN : na std_logic: = '1'; CNT_EN : na std_logic: = '1'; UpDAWN : na std_logic: = '1'; SLOAD : na std_logic: = '0'; SSET : na std_logic: = '0'; SCLR : na std_logic: = '0'; ALOAD: na std_logic: = '0'; ASET : na std_logic: = '0'; ACLR : na std_logic: = '0'; CIN : na std_logic: = '1'; COUT : pụọ std_logic: = '0'; Ajụjụ: pụọ std_logic_vector(LPM_WIDTH-1 ruo 0); EQ: pụọ std_logic_vector (15 ruo 0));
akụkụ njedebe;

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2. LPM_COUNTER (Ngụgụ) IP isi 683490 | 2020.10.05

2.4. Nkwupụta VHDL LIBRARY_USE
Achọghị nkwupụta VHDL LIBRARY-USE ma ọ bụrụ na ijiri nkwupụta akụrụngwa VHDL.
Ụlọ akwụkwọ lpm; Jiri lpm.lpm_components.all;

2.5. ọdụ ụgbọ mmiri

Tebụlụ ndị a depụtara ọdụ ụgbọ mmiri ntinye na mmepụta maka LPM_COUNTER IP core.

Tebụl 2.

Ọdụ ụgbọ mmiri ntinye LPM_COUNTER

Aha Port

Achọrọ

Nkọwa

data[]

Mba

Ntinye data na counter. Ogo ọdụ ụgbọ mmiri ntinye dabere na uru paramita LPM_WIDTH.

elekere

Ntinye elekere dị mma-ọnụ-kpalitere.

clk_en

Mba

Elekere na-enye ntinye aka iji mee ka mmemme niile na-emekọrịta ihe. Ọ bụrụ na ewepụrụ, uru ndabara bụ 1.

cnt_en

Mba

Ngụ nyere ntinye aka iji gbanyụọ ọnụọgụ ahụ mgbe ekwuputara na ọ dị ala na-emetụtaghị sload, sset, ma ọ bụ sclr. Ọ bụrụ na ewepụrụ, uru ndabara bụ 1.

emelite

Mba

Na-achịkwa ntụziaka nke ọnụ ọgụgụ ahụ. Mgbe ekwuputara n'elu (1), ntụzịaka ọnụọgụ na-elu, ma mgbe ekwuputara na ọ dị ala (0), ntụzịaka ọnụọgụ na-agbada. Ọ bụrụ na ejiri paramita LPM_DIRECTION, enweghị ike ijikọ ọdụ ụgbọ elu mgbada. Ọ bụrụ na ejighị LPM_DIRECTION, ọdụ ụgbọ elu mgbada bụ nhọrọ. Ọ bụrụ na ewepụrụ, uru ndabara dị elu (1).

cin

Mba

Buru-na na obere usoro. Maka ọnụ ọgụgụ elu, omume nke ntinye cin bụ

yiri omume nke ntinye cnt_en. Ọ bụrụ na ewepụrụ, uru ndabara bụ 1

(VCC).

aclr

Mba

Ntinye doro anya na-ejikọtaghị ọnụ. Ọ bụrụ na ejiri ma aset na aclr wee kwupụta ya, aclr na-ewepụ aset. Ọ bụrụ na ewepụrụ, uru ndabara bụ 0 (nwere nkwarụ).

aset

Mba

Ntinye ntọala anaghị agbanwe agbanwe. Na-akọwapụta mpụta q[] dị ka 1s niile, ma ọ bụ na uru nke paramita LPM_AVALUE akọwapụtara. Ọ bụrụ na ejiri ma aset na aclr ọdụ ụgbọ mmiri ma kwupụta ya, uru nke ọdụ ụgbọ mmiri aclr na-ewepụ uru nke ọdụ ụgbọ mmiri ahụ. Ọ bụrụ na ewepụrụ, uru ndabara bụ 0, enweghị nkwarụ.

ibu

Mba

Ndenye ibu asynchronous nke na-ejikọta ọnụ ọnụ counter na uru dị na ntinye data. Mgbe ejiri ọdụ ụgbọ mmiri na-ebu ibu, ọdụ ụgbọ mmiri [] ga-ejikọrịrị. Ọ bụrụ na ewepụrụ, uru ndabara bụ 0, enweghị nkwarụ.

sclr

Mba

Ntinye doro anya na-emekọrịta ihe nke na-ehichapụ counter na nsọtụ elekere na-esote. Ọ bụrụ na ejiri ma sset na sclr ọdụ ụgbọ mmiri ma kwupụta, uru nke ọdụ ụgbọ mmiri sclr na-ewepụ uru nke ọdụ ụgbọ mmiri. Ọ bụrụ na ewepụrụ, uru ndabara bụ 0, enweghị nkwarụ.

set

Mba

Ntinye ihe nrụkota nke na-edobe counter n'akụkụ elekere na-arụ ọrụ na-esote. Na-akọwapụta uru nke mpụtara q dị ka 1s niile, ma ọ bụ na uru akọwapụtara site na paramita LPM_SVALUE. Ọ bụrụ na ejiri ma ọdụ ụgbọ mmiri sset na sclr ma kwupụta,
uru nke ọdụ ụgbọ mmiri sclr na-ewepụ uru nke ọdụ ụgbọ mmiri set. Ọ bụrụ na ewepụrụ, uru ndabara bụ 0 (nwere nkwarụ).

sload

Mba

Ntinye ibu na-emekọrịta ihe nke na-ebu data na counter [] na nsọtụ elekere na-esote. Mgbe eji sload ọdụ ụgbọ mmiri, data[] ọdụ ụgbọ mmiri ga-ejikọta. Ọ bụrụ na ewepụrụ, uru ndabara bụ 0 (nwere nkwarụ).

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Tebụl 3.

Ọdụ ụgbọ mmiri LPM_COUNTER

Aha Port

Achọrọ

Nkọwa

q[]

Mba

Nsonaazụ data sitere na counter. The size nke mmepụta ọdụ ụgbọ mmiri dabere na

Uru oke LPM_WIDTH. Ma q[] ma ọ bụ opekata mpe otu ọdụ ụgbọ mmiri eq[15..0].

ga-ejikọta.

nha[15]

Mba

Mbupute mpụta koodu. Enweghị ike ịnweta ọdụ ụgbọ mmiri eq [15..0] na nchịkọta nhọrọ n'ihi na oke na-akwado AHDL.
Ma ọ bụ ọdụ ụgbọ mmiri q[] ma ọ bụ eq[] ga-ejikọrịrị. Enwere ike iji ọdụ ụgbọ mmiri ruru c eq (0 <= c <= 15). Naanị ọnụ ahịa ọnụ ọgụgụ 16 kacha ala ka emepụtara. Mgbe uru ọnụ ọgụgụ ahụ bụ c, a na-ekwuputa na mmepụta eqc dị elu (1). Maka example, mgbe ọnụ ọgụgụ ahụ bụ 0, eq0 = 1, mgbe ọnụ ọgụgụ ahụ bụ 1, eq1 = 1, na mgbe ọnụ ọgụgụ ahụ bụ 15, eq 15 = 1. Mwepụta decoded maka ọnụ ọgụgụ nke 16 ma ọ bụ karịa chọrọ ngbanwe nke mpụga. Nsonaazụ eq[15..0] adabaghị na mpụta q[].

kwuputa

Mba

Bugharịa ọdụ ụgbọ mmiri nke mpempe MSB nke counter. Enwere ike iji ya jikọọ na counter ọzọ iji mepụta counter buru ibu.

2.6. Nkeji

Tebụlụ na-esonụ na-edepụta parampat maka LPM_COUNTER IP core.

Tebụl 4.

Oke LPM_COUNTER

Aha oke

Ụdị

LPM_WIDTH

Ọnụọgụ

LPM_DIRECTION

Ụdọ

LPM_MODULUS LPM_AVALUE

Ọnụọgụ
Ọnụọgụ / eriri

LPM_SVALUE LPM_HINT

Ọnụọgụ / eriri
Ụdọ

LPM_TYPE

Ụdọ

Achọrọ Ee Mba Mba Mba
Mba Mba
Mba

Nkọwa
Na-akọwapụta obosara nke data[] na q[] ọdụ ụgbọ mmiri, ọ bụrụ na ejiri ya.
Uru dị elu, ala, na ejighi ya. Ọ bụrụ na ejiri paramita LPM_DIRECTION, enweghị ike ijikọ ọdụ ụgbọ elu mgbada. Mgbe ejikọtaghị ọdụ ụgbọ mmiri mgbada, uru ndabara LPM_DIRECTION bụ UP.
Ọnụ ọgụgụ kachasị, gbakwunyere otu. Ọnụọgụ steeti pụrụ iche na okirikiri counter. Ọ bụrụ na uru ibu ahụ karịrị paramita LPM_MODULUS, akọwapụtaghị omume nke counter.
Uru mgbe niile nke a na-ebunye mgbe ekwenyesiri ike na akụrụngwa dị elu. Ọ bụrụ na uru akọwapụtara ka ibu ma ọ bụ ha nhata , omume nke counter bụ undefined (X) mgbagha larịị, ebe bụ LPM_MODULUS, ọ bụrụ na ọ dị, ma ọ bụ 2 ^ LPM_WIDTH. Intel na-akwado ka ị kọwapụta uru a dị ka ọnụọgụ iri maka atụmatụ AHDL.
Uru mgbe niile nke a na-ebu n'elu na-arị elu nke ọdụ ụgbọ mmiri elekere mgbe a na-ekwusi ike na ọdụ ụgbọ mmiri dị elu. Intel na-akwado ka ị kọwapụta uru a dị ka ọnụọgụ iri maka atụmatụ AHDL.
Mgbe ị na-eme ka ọbá akwụkwọ nke modul parameterized (LPM) na-arụ ọrụ na VHDL Design File (.vhd), ị ga-ejiri oke LPM_HINT iji kọwapụta paramita akọwapụtara nke Intel. Maka example: LPM_HINT = "CHAIN_SIZE = 8, ONE_INPUT_IS_CONSTANT = EE"
Uru ndabara bụ ejighị ya.
Na-achọpụta ọba akwụkwọ nke modul parameterized (LPM) aha ngalaba na imewe VHDL files.
gara n'ihu…

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Aha oke INTENDED_DEVICE_FAMILY CARRY_CNT_EN
LABWIDE_SCLR
LPM_PORT_UPDOWN

Ụdị eriri eriri
Ụdọ
Ụdọ

Achọrọ Mba Mba
Mba
Mba

Nkọwa
A na-eji oke a maka nlegharị anya na ebumnuche ịme anwansị omume. A na-eji oke a maka nlegharị anya na ebumnuche ịme anwansị omume. Onye ndezi paramita na-agbakọ uru maka oke a.
Paramita akọwapụtara nke Intel. Ị ga-ejirịrị LPM_HINT iji kọwapụta oke CARRY_CNT_EN na imewe VHDL files. Uru bụ SMART, GBANYE, gbanyụọ, na ejighi ya. Na-enyere ọrụ LPM_COUNTER aka ịgbasa mgbama cnt_en site n'agbụ ebu. N'ọnọdụ ụfọdụ, ntọala paramita CARRY_CNT_EN nwere ike inwe mmetụta dị nta na ọsọ ahụ, yabụ ị nwere ike chọọ ịgbanyụ ya. Uru ndabara bụ SMART, nke na-enye azụmaahịa kacha mma n'etiti nha na ọsọ.
Paramita akọwapụtara nke Intel. Ị ga-ejirịrị LPM_HINT iji kọwapụta paramita LABWIDE_SCLR na imewe VHDL files. Uru dị na agbanyụrụ, gbanyụọ, ma ọ bụ ejighi ya. Uru ndabara bụ GBANYE. Na-enye gị ohere gbanyụọ iji njirimara LABwide sclr nke achọtara n'ezinaụlọ ngwaọrụ emechiela. Ịgbanyụ nhọrọ a na-abawanye ohere nke iji LAB zuru ezu, ma si otú a nwere ike ikwe ka njupụta mgbagha dị elu mgbe SCLR anaghị etinye aka na LAB zuru ezu. Oke a dị maka ndakọrịta azụ, Intel na-atụ aro ka ị ghara iji oke a.
Na-akọwapụta ojiji nke ọdụ ụgbọ mmiri mgbada. Ọ bụrụ na ewepụrụ uru ndabara bụ PORT_CONNECTIVITY. Mgbe atọrọ uru ọdụ ụgbọ mmiri na PORT_USED, a na-emeso ọdụ ụgbọ mmiri ahụ ka ejiri ya. Mgbe atọrọ uru ọdụ ụgbọ mmiri ka ọ bụrụ PORT_UNUSED, a na-ewere ọdụ ụgbọ mmiri ahụ ka ejighi ya. Mgbe atọrọ uru ọdụ ụgbọ mmiri na PORT_CONNECTIVITY, a na-ekpebi ojiji ọdụ ụgbọ mmiri site na ịlele njikọ ọdụ ụgbọ mmiri.

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3. LPM_DIVIDE (Divider) Intel FPGA IP isi

Onyonyo 2.

LPM_DIVIDE Intel FPGA IP core na-eme ihe nkesa iji kesaa uru ndenye ọnụọgụ site na uru ntinye denominator iji wepụta ọnụ na nke fọdụrụ.

Ọnụọgụ na-esonụ na-egosi ọdụ ụgbọ mmiri maka LPM_DIVIDE IP core.

ọdụ ụgbọ mmiri LPM_DIVIDE

LPM_DIVIDE

ọnụọgụ[] denom[] elekere

ihe fọdụrụ[] fọdụrụ[]

clen aclr

inst

3.1. Atụmatụ
LPM_DIVIDE IP isi na-enye atụmatụ ndị a: · Na-emepụta nkesa na-ekewa uru ndenye ọnụọgụ site na ntinye denominator.
uru iji mepụta quotient na nke fọdụrụ. Na-akwado obosara data nke 1 bits. Na-akwado usoro nnochite anya data mbinye aka na nke etinyeghị aka maka ma ọnụọgụgụ
na ụkpụrụ ụkpụrụ. · Na-akwado mpaghara ma ọ bụ njikarịcha ọsọ. · Na-enye nhọrọ iji kọwapụta nsonaazụ fọdụrụ dị mma. Na-akwado pipelining configurable mmepụta latency. Na-akwado nhọrọ asynchronous doro anya na elekere na-enyere ọdụ ụgbọ mmiri.

3.2. Prototype Verilog HDL
Ụdị Verilog HDL ndị a dị na Verilog Design File (.v) lpm.v n'ime edesynthesis ndekọ.
modul lpm_divide ( quotient, foduru, ọnụọgụ, denom, elekere, clken, aclr); oke lpm_type = "lpm_divide"; oke lpm_widthn = 1; oke lpm_widthd = 1; paramita lpm_nrepresentation = "Enweghị ama"; paramita lpm_drepresentation = "Enweghị ama"; paramita lpm_remainderpositive = "EZIOKWU"; oke lpm_pipeline = 0;

ISO 9001: 2015 edebanye aha

3. LPM_DIVIDE (Divide) Intel FPGA IP isi 683490 | 2020.10.05

paramita lpm_hint = "EJIGHỊ"; ntinye elekere; ntinye klken; ntinye aclr; ntinye [lpm_widthn-1:0] ọnụọgụ; ntinye [lpm_widthd-1:0] denom; mmepụta [lpm_widthn-1:0] quotient; mmepụta [lpm_widthd-1:0] fọdụrụ; endmodule

3.3. Nkwupụta akụkụ VHDL
Nkwupụta akụrụngwa VHDL dị na Nhazi VHDL File (.vhd) LPM_PACK.vhd n'ime akwụkwọ ndekọ aha vhdllpm.
akụrụngwa LPM_DIVIDE jeneriki (LPM_WIDTHN: eke; LPM_WIDTHD: eke;
LPM_Nnọchite anya : eriri : = "Enweghị aha"; LPM_DREPRESENTATION : eriri : = "Enweghị aha"; LPM_PIPELINE : eke: = 0; LPM_TYPE : eriri: = L_DIVIDE; LPM_HINT: eriri: = "EJIGHỊ"); ọdụ ụgbọ mmiri (NUMER: na std_logic_vector(LPM_WIDTHN-1 ruo 0); DENOM : na std_logic_vector (LPM_WIDTHD-1 ruo 0); ACLR : na std_logic: = '0'; CLOCK : na std_logic: CL = 'std : = '0'; QUOTIENT: pụọ std_logic_vector(LPM_WIDTHN-1 ruo 1): pụọ std_logic_vector (LPM_WIDTHD-0 ruo 1)); akụkụ njedebe;

3.4. Nkwupụta VHDL LIBRARY_USE
Achọghị nkwupụta VHDL LIBRARY-USE ma ọ bụrụ na ijiri nkwupụta akụrụngwa VHDL.
Ụlọ akwụkwọ lpm; Jiri lpm.lpm_components.all;

3.5. ọdụ ụgbọ mmiri

Tebụlụ ndị a depụtara ọdụ ụgbọ mmiri ntinye na mmepụta maka LPM_DIVIDE IP core.

Tebụl 5.

Ọdụ ụgbọ mmiri ntinye LPM_DIVIDE

Aha Port

Achọrọ

nọmba[]

denom[]

Nkọwa
Ntinye data ọnụọgụgụ. Ogo ọdụ ụgbọ mmiri ntinye dabere na uru paramita LPM_WIDTHN.
Ntinye data denominator. Ogo ọdụ ụgbọ mmiri ntinye dabere na uru paramita LPM_WIDTHD.
gara n'ihu…

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Elekere ọdụ ụgbọ mmiri klken
aclr

Achọrọ Mba Mba
Mba

Nkọwa
Ntinye elekere maka ojiji pipeline. Maka ụkpụrụ LPM_PIPELINE karịa 0 (ndabere), ekwesịrị ịgbanye ọdụ ụgbọ mmiri ahụ.
Elekere na-enyere iji pipeline eme ihe. Mgbe a na-ekwusi ike na ọdụ ụgbọ mmiri klken dị elu, ọrụ nkewa na-ewere ọnọdụ. Mgbe mgbama dị ala, ọ nweghị ọrụ na-eme. Ọ bụrụ na ewepụrụ, uru ndabara bụ 1.
Asynchronous ọdụ ụgbọ mmiri doro anya na-eji n'oge ọ bụla iji tọgharịa pipeline na '0' niile na ntinye elekere.

Tebụl 6.

Ọdụ ụgbọ mmiri LPM_DIVIDE

Aha Port

Achọrọ

Nkọwa

okwu[]

Mbupute data. Ogo ọdụ ụgbọ mmiri ahụ dabere na LPM_WIDTHN

oke uru.

nọrọ[]

Mbupute data. Ogo ọdụ ụgbọ mmiri ahụ dabere na LPM_WIDTHD

oke uru.

3.6. Nkeji

Tebụlụ na-esote depụtara parampat maka LPM_DIVIDE Intel FPGA IP core.

Aha oke

Ụdị

Achọrọ

Nkọwa

LPM_WIDTHN

Ọnụọgụ

Na-akọwapụta obosara nke ọnụọgụgụ[] na

ọdụ ụgbọ mmiri[]. Uru bụ 1 ruo 64.

LPM_WIDTHD

Ọnụọgụ

Na-akọwapụta obosara nke denom[] na

fọdụrụ[] ọdụ ụgbọ mmiri. Uru bụ 1 ruo 64.

LPM_NREPRESENTATION LPM_DREPRESENTATION

Ụdọ eriri

Mba

Ihe nnochite anya ntinye ọnụọgụgụ.

AKWỤKWỌ KWESỊRỊ ụkpụrụ yana enweghị aha. Mgbe nke a

atọrọ paramita na SIGNED, nkesa

na-akọwa ntinye nọmba[] ka nke abụọ abịanyere aka na ya

imeju.

Mba

Ihe nnochite anya ntinye ọnụ ala.

AKWỤKWỌ KWESỊRỊ ụkpụrụ yana enweghị aha. Mgbe nke a

atọrọ paramita na SIGNED, nkesa

na-akọwa ntinye denom[] ka nke abụọ abịanyere aka na ya

imeju.

LPM_TYPE

Ụdọ

Mba

Na-achọpụta ọba akwụkwọ nke parameterized

modul (LPM) aha njirimara na imewe VHDL

files (.vhd).

LPM_HINT

Ụdọ

Mba

Mgbe ị na-emepe ụlọ akwụkwọ ọta akara

modul parameterized (LPM) na-arụ ọrụ na a

VHDL imewe File (.vhd), ị ga-eji

Oke LPM_HINT iji kọwapụta ihe Intel-

kpọmkwem oke. Maka example: LPM_HINT

= "CHAIN_SIZE = 8,

ONE_INPUT_IS_CONSTANT = EE” The

ejighị uru ndabara.

LPM_REMAINDERPOSITIVE

Ụdọ

Mba

Paramita akọwapụtara nke Intel. Ị ga-eji

Oke LPM_HINT iji kọwapụta ya

Oke LPM_REMAINDERPOSITIVE n'ime

VHDL imewe files. Uru bụ EZIOKWU ma ọ bụ Ụgha.

Ọ bụrụ na edobere oke a ka ọ bụrụ TRUE, yabụ a

uru nke ọdụ ụgbọ mmiri fọdụrụ[] ga-abụrịrị nke ukwuu

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Aha oke

Ụdị

MAXIMIZE_SPEED

Ọnụọgụ

LPM_PIPELINE

Ọnụọgụ

INTENDED_DEVICE_FAMILY SKIP_BITS

eriri eriri

Achọrọ Mba
Mba Mba Mba

Nkọwa
karịa ma ọ bụ hà nhata na efu. Ọ bụrụ na edobere oke a ka ọ bụrụ TRUE, uru nke ọdụ ụgbọ mmiri fọdụrụ [] bụ ma efu, ma ọ bụ uru ya bụ otu akara, ma ọ dị mma ma ọ bụ adịghị mma, dịka uru nke ọdụ ụgbọ mmiri. Iji belata mpaghara ma melite ọsọ, Intel na-atụ aro ka ịtọ ntọala a ka ọ bụrụ TRUE na arụ ọrụ ebe nke fọdụrụ ga-adị mma ma ọ bụ ebe nke fọdụrụ adịghị mkpa.
Paramita akọwapụtara nke Intel. Ị ga-ejirịrị LPM_HINT iji kọwapụta oke MAXIMIZE_SPEED na imewe VHDL files. Uru bụ [0..9]. Ọ bụrụ na ejiri ya, sọftụwia Intel Quartus Prime na-anwa ibuli otu ihe atụ nke ọrụ LPM_DIVIDE maka ọsọ karịa ka ọ na-emezigharị, wee mebie ntọala nke nhọrọ mgbagha kacha mma. Ọ bụrụ na ejighi MAXIMIZE_SPEED, uru nke Nhọrọ Nkachamma ka a na-eji kama. Ọ bụrụ na uru MAXIMIZE_SPEED bụ 6 ma ọ bụ karịa, Compiler na-ebuli LPM_DIVIDE IP core maka ọsọ dị elu site na iji ụdọ ebu; ọ bụrụ na ọnụ ahịa ahụ dị 5 ma ọ bụ obere, onye nchịkọta na-emejuputa nhazi ahụ n'ebughị ụdọ.
Na-akọwapụta ọnụọgụ okirikiri elekere nke latency jikọtara ya na mpụta[] ma nọgide[]. Uru nke efu (0) na-egosi na ọ nweghị nkwụsị dị adị, yana na a na-ewepụta ọrụ njikọta naanị ozugbo. Ọ bụrụ na ewepụrụ, uru ndabara bụ 0 (anaghị etinye ya). Ị nweghị ike ịkọwa uru maka paramita LPM_PIPELINE dị elu karịa LPM_WIDTHN.
A na-eji oke a maka nlegharị anya na ebumnuche ịme anwansị omume. Onye ndezi paramita na-agbakọ uru maka oke a.
Na-enye ohere maka nkewa obere akụkụ nke ọma na-arụ ọrụ nke ọma iji kwalite mgbagha na ibe n'igosi site n'inye ọnụọgụ ndị na-eduga GND na isi LPM_DIVIDE IP. Kpebie ọnụ ọgụgụ GND na-eduga na mmepụta quotient na oke a.

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4. LPM_MULT (Multiplier) IP isi

Onyonyo 3.

The LPM_MULT IP core na-emejuputa atumatu iji mụbaa ụkpụrụ data ntinye abụọ iji mepụta ngwaahịa dị ka mmepụta.

Ọnụọgụ ndị a na-egosi ọdụ ụgbọ mmiri maka LPM_MULT IP isi.

Ọdụ ụgbọ mmiri LPM_Mult

LPM_MULT elekere data[] nsonaazụ[] datab[] aclr/sclr clken
inst

Atụmatụ ozi emetụtara na ibe 71

4.1. Atụmatụ
LPM_MULT IP core na-enye atụmatụ ndị a: · Na-emepụta ọnụọgụ nke na-amụba ụkpụrụ data ntinye abụọ · Na-akwado obosara data nke 1 bits · Na-akwado usoro nnochite anya data bịanyere aka na nke na-edeghị aha · Na-akwado mpaghara ma ọ bụ njikarịcha ọsọ · Na-akwado pipelining site na iji configurable mmepụta latency. nhọrọ maka mmejuputa na nhazi akara ngosi dijitalụ raara onwe ya nye (DSP)
igbochi sekit ma ọ bụ ihe mgbagha (LEs) Mara: Mgbe ị na-ewu ọtụtụ ndị na-ebuwanye ibu karịa nha obodo akwadoro enwere ike/
ga-abụ mmetụta arụmọrụ sitere na cascading nke ngọngọ DSP. Na-akwado nhọrọ asynchronous doro anya na elekere na-enye ohere ntinye ọdụ ụgbọ mmiri · Na-akwado nhọrọ synchronous doro anya maka Intel Stratix 10, Intel Arria 10 na Intel Cyclone 10 GX ngwaọrụ.

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4.2. Prototype Verilog HDL
Ụdị Verilog HDL ndị a dị na Verilog Design File (.v) lpm.v n'ime edesynthesis ndekọ.
modul lpm_mult (nsona, dataa, datab, nchikota, elekere, clken, aclr ) parameter lpm_type = "lpm_mult"; oke lpm_widtha = 1; oke lpm_widthb = 1; oke lpm_widths = 1; oke lpm_widthp = 1; paramita lpm_representation = "ESIGHỊ"; oke lpm_pipeline = 0; paramita lpm_hint = "EJIGHỊ"; elekere ntinye; ntinye klken; ntinye aclr; ntinye [lpm_widtha-1:0] data; ntinye [lpm_widthb-1:0] datab; ntinye [lpm_widths-1:0] nchikota; mmepụta [lpm_widthp-1:0] nsonaazụ; endmodule
4.3. Nkwupụta akụkụ VHDL
Nkwupụta akụrụngwa VHDL dị na Nhazi VHDL File (.vhd) LPM_PACK.vhd n'ime akwụkwọ ndekọ aha vhdllpm.
akụrụngwa LPM_MULT jeneriki ( LPM_WIDTHA : eke; LPM_WIDTHB : eke; LPM_WIDTHS : eke: = 1 ; LPM_WIDTHP : eke;
LPM_Nnọchite anya : eriri : = "Enweghị aha"; LPM_PIPELINE : eke: = 0; LPM_TYPE: eriri: = L_MULT; LPM_HINT: eriri: = "EJIGHỊ"); ọdụ ụgbọ mmiri (DATAA: na std_logic_vector (LPM_WIDTHA-1 ruo 0); DATAB: na std_logic_vector (LPM_WIDTHB-1 ruo 0); ACLR: na std_logic: = '0'; CLOCK: na std_logic: CL = 'std : = '0'; SUM: na std_logic_vector(LPM_WIDTHS-1 ruo 1): = (OTHERS => '0'); akụkụ njedebe;
4.4. Nkwupụta VHDL LIBRARY_USE
Achọghị nkwupụta VHDL LIBRARY-USE ma ọ bụrụ na ijiri nkwupụta akụrụngwa VHDL.
Ụlọ akwụkwọ lpm; Jiri lpm.lpm_components.all;

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4.5. Akara ngosi

Tebụl 7.

Ihe nrịbama ntinye LPM_MULT

Aha mgbaàmà

Achọrọ

Nkọwa

data[]

Ntinye data.

Maka Intel Stratix 10, Intel Arria 10 na Intel Cyclone 10 GX ngwaọrụ, nha mgbama ntinye na-adabere na uru paramita obosara Dataa.

Maka ngwaọrụ ndị okenye na Intel Cyclone 10 LP, nha mgbama ntinye dabere na uru paramita LPM_WIDTHA.

data[]

Ntinye data.

Maka Intel Stratix 10, Intel Arria 10, na Intel Cyclone 10 GX ngwaọrụ, nha mgbama ntinye dabere na uru paramita obosara Datab.

Maka ngwaọrụ ndị okenye na Intel Cyclone 10 LP, nha mgbama ntinye dabere

na uru paramita LPM_WIDTHB.

elekere

Mba

Ntinye elekere maka ojiji pipeline.

Maka ngwaọrụ ndị agadi na Intel Cyclone 10 LP, a ga-agbanyerịrị mgbaama elekere maka ụkpụrụ LPM_PIPELINE karịa 0 (nke ndabara).

Maka Intel Stratix 10, Intel Arria 10, na Intel Cyclone 10 GX ngwaọrụ, mgbama elekere ga-emerịrị ma ọ bụrụ na uru Latency dị iche karịa 1 (nke ndabara).

clan

Mba

Kwado elekere maka ojiji pipeline. Mgbe a na-ekwusi ike na mgbama klken dị elu, nke

adder/ subtractor ọrụ na-ewere ọnọdụ. Mgbe mgbama dị ala, enweghị ọrụ ọ bụla

emee. Ọ bụrụ na ewepụrụ, uru ndabara bụ 1.

aclr sclr

Mba

Asynchronous doro anya mgbama ejiri n'oge ọ bụla iji tọgharịa pipeline na 0s niile,

asynchronously na mgbama elekere. Pipeline na-amalite ruo na enweghị nkọwa (X)

mgbagha larịị. Nsonaazụ a na-agbanwe agbanwe, mana enweghị efu.

Mba

Mgbama doro anya na-arụkọ ọrụ ọnụ ejiri n'oge ọ bụla iji tọgharịa pipeline na 0s niile,

na-emekọrịta ihe na mgbama elekere. Pipeline na-amalite na nke enweghị nkọwa (X)

mgbagha larịị. Nsonaazụ a na-agbanwe agbanwe, mana enweghị efu.

Tebụl 8.

LPM_MULT Mbupute

akara aha

Achọrọ

Nkọwa

Nsonaazụ[]

Mbupute data.

Maka ngwaọrụ ndị okenye na Intel Cyclone 10 LP, nha mgbama mmepụta dabere na uru paramita LPM_WIDTHP. Ọ bụrụ LPM_WIDTHP <max (LPM_WIDTHA + LPM_WIDTHB, LPM_WIDTHS) ma ọ bụ (LPM_WIDTHA + LPM_WIDTHS), naanị LPM_WIDTHP MSB dị.

Maka Intel Stratix 10, Intel Arria 10 na Intel Cyclone 10 GX, nha nke nrịbama mmepụta dabere na oke obosara nsonaazụ.

4.6. Oke maka Stratix V, Arria V, Cyclone V na Intel Cyclone 10 LP Ngwaọrụ

4.6.1. General Tab

Tebụl 9.

General Tab

Oke

Uru

Nhazi ọtụtụ

Mụbaa ntinye 'data' site na ntinye 'datab'

Uru ndabara

Nkọwa

Mụbaa ntinye 'data' site na ntinye 'datab'

Họrọ nhazi achọrọ maka ọtụtụ.
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Oke
Ogologo ole ka ntinye 'data' kwesịrị ịdị? Ogologo ole ka ntinye 'datab' kwesịrị ịdị? Kedu ka esi ekpebi obosara nke nsonaazụ 'mpụta'? Machibido obosara

Uru
Mụbaa ntinye 'data' n'onwe ya (ọrụ squaring)
1-256 ibe

Uru ndabara

Nkọwa

8 ibeji

Ezipụta obosara nke ọdụ ụgbọ mmiri dataa[].

1-256 ibe

8 ibeji

Ezipụta obosara nke ọdụ ụgbọ mmiri[].

Gbakọọ obosara na akpaghị aka Machibido obosara
1-512 ibe

Akpaaka y gbakọọ obosara

Họrọ usoro achọrọ iji chọpụta obosara nke ọdụ ụgbọ mmiri nsonaazụ[].

16 ibeji

Ezipụta obosara nke ọdụ ụgbọ mmiri [].
Uru a ga-adị irè naanị ma ọ bụrụ na ịhọrọ Machibido obosara na paramita Ụdị.

4.6.2. General 2 Tab

Isiokwu 10. General 2 Tab

Oke

Uru

Ntinye data

Ụgbọ ala ntinye 'datab' nwere uru mgbe niile?

Mba Ee

Ụdị mmụba

Kedu ụdị nke

Ebinyeghị aka na ya

ịba ụba ị chọrọ? Binyere aka

Mmejuputa

Kedu mmejuputa mmejuputa a ga-eji mee ihe?

Jiri mmejuputa atumatu
Jiri sekit multiplikator raara onwe ya nye (Ọ dịghị maka ezinụlọ niile)
Jiri ihe mgbagha mee ihe

Uru ndabara

Nkọwa

Mba

Họrọ E-eh ka ezipụta uru mgbe niile nke

bọs ntinye 'datab', ọ bụrụ na ọ bụla.

Ebinyeghị aka na ya

Ezipụta usoro nnọchite anya maka ntinye dataa[] na datab[].

Jiri ion emejuputa atumatu

Họrọ usoro achọrọ iji chọpụta obosara nke ọdụ ụgbọ mmiri nsonaazụ[].

4.6.3. Taabụ ọkpọkọ

Isiokwu 11. Pipelining Tab

Oke

Ịchọrọ ịgbanye ọkpọkọ No

ọrụ?

Uru

Mepụta 'aclr'

—

ọdụ ụgbọ mmiri doro anya asynchronous

Uru ndabara

Nkọwa

Mba

Họrọ Ee iji mee ka ndekọ pipeline nwee ike ịbanye na ya

mmepụta multiplier na ezipụta chọrọ

mmepụta latency na okirikiri elekere. Na-enyere aka

ndekọ pipeline na-agbakwụnyekwu latency na

mmepụta.

Achọpụtaghị ya

Họrọ nhọrọ a iji mee ka ọdụ ụgbọ mmiri aclr jiri asynchronous clear maka ndekọ pipeline.
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Oke
Mepụta elekere 'clken' na-enyere aka elekere
Nkwalite
Kedu ụdị njikarịcha ị chọrọ?

Uru -
Mpaghara Ọsọ Ọsọ

Uru ndabara

Nkọwa

Achọpụtaghị ya

Na-akọwapụta aka elekere dị elu na-arụ ọrụ maka ọdụ ụgbọ mmiri nke ndekọ pipeline

Ọdabara

Ezipụta njikarịcha achọrọ maka isi IP.
Họrọ Ndi an-kpọ ka ikwe ka Intel Quartus Prime software chọpụta njikarịcha kacha mma maka isi IP.

4.7. Parameters maka Intel Stratix 10, Intel Arria 10 na Intel Cyclone 10 GX Ngwaọrụ

4.7.1. General Tab

Tebụl 12. General Tab

Oke

Uru

Uru ndabara

Nkọwa

Ụdị nhazi multiplier
obosara ọdụ ụgbọ mmiri

Mụbaa ntinye 'data' site na ntinye 'datab'
Mụbaa ntinye 'data' n'onwe ya (ọrụ squaring)

Mụbaa ntinye 'data' site na ntinye 'datab'

Họrọ nhazi achọrọ maka ọtụtụ.

Obosara data

1-256 ibe

8 ibeji

Ezipụta obosara nke ọdụ ụgbọ mmiri dataa[].

Ogologo data

1-256 ibe

8 ibeji

Ezipụta obosara nke ọdụ ụgbọ mmiri[].

Kedu ka esi ekpebi obosara nke nsonaazụ 'mpụta'?

Ụdị

Gbakọọ obosara na akpaghị aka
Machibido obosara

Akpaaka y gbakọọ obosara

Họrọ usoro achọrọ iji chọpụta obosara nke ọdụ ụgbọ mmiri nsonaazụ[].

Uru

1-512 ibe

16 ibeji

Ezipụta obosara nke ọdụ ụgbọ mmiri [].
Uru a ga-adị irè naanị ma ọ bụrụ na ịhọrọ Machibido obosara na paramita Ụdị.

Obosara nsonaazụ

1-512 ibe

—

Na-egosiputa obosara dị irè nke ọdụ ụgbọ mmiri[].

4.7.2. General 2 Tab

Isiokwu 13. General 2 Tab

Oke

Ntinye data

Ụgbọ ala ntinye 'datab' nwere uru mgbe niile?

Mba Ee

Uru

Uru ndabara

Nkọwa

Mba

Họrọ E-eh ka ezipụta uru mgbe niile nke

bọs ntinye 'datab', ọ bụrụ na ọ bụla.

gara n'ihu…

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Oke

Uru

Uru ọ bụla karịrị 0

Ụdị mmụba

Kedu ụdị nke

Ebinyeghị aka na ya

ịba ụba ị chọrọ? Binyere aka

Ụdị mmejuputa

Kedu mmejuputa mmejuputa a ga-eji mee ihe?

Jiri mmejuputa atumatu
Jiri sekit multiplikator raara onwe ya nye
Jiri ihe mgbagha mee ihe

Uru ndabara

Nkọwa

Ezipụta uru ọdụ ụgbọ mmiri datab[] mgbe niile.

Ebinyeghị aka na ya

Ezipụta usoro nnọchite anya maka ntinye dataa[] na datab[].

Jiri ion emejuputa atumatu

Họrọ usoro achọrọ iji chọpụta obosara nke ọdụ ụgbọ mmiri nsonaazụ[].

4.7.3. Pipelining

Isiokwu 14. Pipelining Tab

Oke

Uru

Ịchọrọ ikpochapụ ọrụ ahụ?

Pipeline

Mba Ee

Ụdị akara ngosi Latency

Uru ọ bụla karịrị 0.
Ọ BỤGHỊ ACLR SCLR

Mepụta elekere 'clken'

—

mee elekere

Kedu ụdị njikarịcha ị chọrọ?

Ụdị

Mpaghara Ọsọ Ọsọ

Uru ndabara

Nkọwa

Mba 1 Ọ BỤGHỊ
—

Họrọ E-eh iji mee ka ndekọ pipeline nwee mmepụta nke ọtụtụ. Ịkwado ndekọ pipeline na-agbakwụnyekwu latency na mmepụta.
Ezipụta nkwụsị mmepụta achọrọ na okirikiri elekere.
Ezipụta ụdị nrụpụta maka ndekọ pipeline. Họrọ Ọ BỤGHỊ ma ọ bụrụ na ijighị ndekọ pipeline ọ bụla. Họrọ ACLR ka ijiri asynchronous doro anya maka ndekọ ọkpọkọ. Nke a ga-emepụta ọdụ ụgbọ mmiri ACLR. Họrọ SCLR ka ijiri mmekọrịta doro anya maka ndekọ pipeline. Nke a ga-emepụta ọdụ ụgbọ mmiri SCLR.
Na-akọwapụta aka elekere dị elu na-arụ ọrụ maka ọdụ ụgbọ mmiri nke ndekọ pipeline

Ọdabara

Ezipụta njikarịcha achọrọ maka isi IP.
Họrọ Ndi an-kpọ ka ikwe ka Intel Quartus Prime software chọpụta kacha mma maka isi IP.

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5. LPM_ADD_SUB (Adder/Ndepụta)

Onyonyo 4.

LPM_ADD_SUB IP isi na-enye gị ohere mejuputa adder ma ọ bụ mwepu iji gbakwunye ma ọ bụ wepụ data iji mepụta mpụta nwere nchikota ma ọ bụ ọdịiche nke ụkpụrụ ntinye.

Ọnụọgụ ndị a na-egosi ọdụ ụgbọ mmiri maka LPM_ADD_SUB IP isi.

Ọdụ ụgbọ mmiri LPM_ADD_SUB

LPM_ADD_SUB tinye_sub cin

data[]

cliken datab[] aclr

nsonaazụ[] oke oke mmiri

inst

5.1. Atụmatụ
LPM_ADD_SUB IP isi na-enye atụmatụ ndị a: · Na-emepụta adder, subtractor, na dynamically configurable adder/ subtractor
ọrụ. Na-akwado obosara data nke 1 bits. · Na-akwado usoro nnochite anya data dị ka mbinye aka na enweghị aha. Na-akwado ibubata nhọrọ (mbinye-mgbazinye), doro anya na-emekọrịtaghị ihe na elekere
ọdụ ụgbọ mmiri ntinye. Na-akwado mbubata nhọrọ (binye-na) yana ọdụ ụgbọ mmiri na-ebufe oke. · Na-ekenye otu bọs ntinye data na-adịgide adịgide. · Na-akwado pipelining na configurable mmepụta latency.

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5.2. Prototype Verilog HDL
Ụdị Verilog HDL ndị a dị na Verilog Design File (.v) lpm.v n'ime edesynthesis ndekọ.
modul lpm_add_sub (nsonaazụ, cout, njupụta, add_sub, cin, dataa, datab, clock, clken, aclr); oke lpm_type = "lpm_add_sub"; oke lpm_width = 1; paramita lpm_direction = "USED"; paramita lpm_representation = "SIGNED"; oke lpm_pipeline = 0; paramita lpm_hint = "EJIGHỊ"; ntinye [lpm_width-1:0] data, datab; ntinye add_sub, cin; ntinye elekere; ntinye klken; ntinye aclr; mmepụta [lpm_width-1:0] nsonaazụ; mpụta mmepụta, oke ibu; endmodule
5.3. Nkwupụta akụkụ VHDL
Nkwupụta akụrụngwa VHDL dị na Nhazi VHDL File (.vhd) LPM_PACK.vhd n'ime akwụkwọ ndekọ aha vhdllpm.
akụrụngwa LPM_ADD_SUB jeneriki (LPM_WIDTH: eke;
LPM_DIRECTION : eriri: = "EJIGHỊ"; LPM_Nnọchite anya: eriri : = "AKWỤKWỌ"; LPM_PIPELINE : eke: = 0; LPM_TYPE : eriri: = L_ADD_SUB; LPM_HINT: eriri: = "EJIGHỊ"); ọdụ ụgbọ mmiri (DATAA: na std_logic_vector (LPM_WIDTH-1 ruo 0); DATAB: na std_logic_vector (LPM_WIDTH-1 ruo 0); ACLR: na std_logic: = '0'; CLOCK: na std_logic na : CL '0'; : = '1'; CIN: na std_logic: = 'Z'; na std_logic: = '1'; akụkụ njedebe;
5.4. Nkwupụta VHDL LIBRARY_USE
Achọghị nkwupụta VHDL LIBRARY-USE ma ọ bụrụ na ijiri nkwupụta akụrụngwa VHDL.
Ụlọ akwụkwọ lpm; Jiri lpm.lpm_components.all;
5.5. ọdụ ụgbọ mmiri
Tebụlụ ndị a depụtara ọdụ ụgbọ mmiri ntinye na mmepụta maka LPM_ADD_SUB IP core.

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Tebụl 15. LPM_ADD_SUB IP isi ntinye ọdụ ụgbọ mmiri

Aha Port

Achọrọ

Nkọwa

cin

Mba

Buru-na na obere usoro. Maka ọrụ mgbakwunye, uru ndabara bụ 0. Maka

arụmọrụ mwepu, uru ndabara bụ 1.

data[]

Ntinye data. Ogo ọdụ ụgbọ mmiri ntinye dabere na uru paramita LPM_WIDTH.

data[]

Ntinye data. Ogo ọdụ ụgbọ mmiri ntinye dabere na uru paramita LPM_WIDTH.

tinye_sub

Mba

ọdụ ụgbọ mmiri ntinye nhọrọ iji mee ka mgbanwe dị ike n'etiti adder na mwepu

ọrụ. Ọ bụrụ na ejiri paramita LPM_DIRECTION, enweghị ike iji add_sub. Ọ bụrụ

ewepụrụ, uru ndabara bụ ADD. Intel na-atụ aro ka ị jiri ya

Oke LPM_DIRECTION iji kọwapụta arụmọrụ nke ọrụ LPM_ADD_SUB,

kama ịkenye oge niile na ọdụ ụgbọ mmiri add_sub.

elekere

Mba

Ntinye maka ojiji pipeline. Ọdụ ụgbọ mmiri elekere na-enye ntinye elekere maka pipelined

ọrụ. Maka ụkpụrụ LPM_PIPELINE karịa 0 (ndabere), ọdụ ụgbọ mmiri ga-abụrịrị

enyere.

clan

Mba

Kwado elekere maka ojiji pipeline. Mgbe a na-ekwusi ike na ọdụ ụgbọ mmiri klken dị elu, adder/

ọrụ subtractor na-ewere ọnọdụ. Mgbe mgbama dị ala, ọ nweghị ọrụ na-eme. Ọ bụrụ

ewepụrụ, uru ndabara bụ 1.

aclr

Mba

Asynchronous doro anya maka ojiji pipeline. Pipeline na-amalite ruo na enweghị nkọwa (X)

mgbagha larịị. Enwere ike iji ọdụ ụgbọ mmiri aclr n'oge ọ bụla iji tọgharịa pipeline na 0s niile,

asynchronously na mgbama elekere.

Tebụl 16. LPM_ADD_SUB IP isi ọdụ ụgbọ mmiri

Aha Port

Achọrọ

Nkọwa

Nsonaazụ[]

Mbupute data. Ogo ọdụ ụgbọ mmiri ahụ dabere na oke LPM_WIDTH

uru.

kwuputa

Mba

Na-ebu (binye-na) nke kacha dị mkpa (MSB). Ọdụ ụgbọ mmiri nwere anụ ahụ

nkọwa dị ka ibu-ebu (mbiri-na) nke MSB. Ọdụ ụgbọ mmiri na-achọpụta

jubigara ókè na ọrụ UNSIGNED. The cout port na-arụ ọrụ n'otu ụzọ ahụ maka

Ọrụ mbinye aka na enweghị aha.

jubigara ókè

Mba

Mbupu oke oke oke nhọrọ. Ụgbọ mmiri na-ejubiga ókè nwere nkọwa anụ ahụ dịka

XOR nke ebubata na MSB na mbupu nke MSB. Ụgbọ mmiri na-ejubiga ókè

na-ekwupụta mgbe nsonaazụ gafere nkenke dị adị, ma a na-eji ya naanị mgbe

Uru oke LPM_REPRESENTATION bụ SIGNED.

5.6. Nkeji

Tebụlụ na-esote depụtara LPM_ADD_SUB IP isi paramita.

Tebụl 17. LPM_ADD_SUB IP Core Parameters

Oke aha LPM_WIDTH

Ụdị Integer

Achọrọ Ee

Nkọwa
Na-akọwapụta obosara nke ọdụ ụgbọ mmiri dataa[], datab[] na nsonaazụ[].

LPM_DIRECTION

Ụdọ

Mba

Uru bụ ADD, SUB, na ejighi ya. Ọ bụrụ na ewepụrụ, uru ndabara bụ DEFAULT, nke na-eduzi parameter ka ọ were uru ya n'ọdụ ụgbọ mmiri add_sub. Enweghị ike iji ọdụ ụgbọ mmiri add_sub ma ọ bụrụ na ejiri LPM_DIRECTION. Intel na-atụ aro ka ị jiri paramita LPM_DIRECTION iji kọwapụta ọrụ LPM_ADD_SUB arụrụ arụ, kama ịkenye mgbe niile na ọdụ ụgbọ mmiri add_sub.
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Oke aha LPM_REPRESENTATION LPM_PIPELINE LPM_HINT LPM_TYPE ONE_INPUT_IS_CONSTANT MAXIMIZE_SPEED
INTENDED_DEVICE_FAMILY

Ụdị eriri eriri eriri eriri eriri eriri
Ụdọ

Achọrọ Mba Mba Mba Mba Mba Mba
Mba

Nkọwa
Na-akọwapụta ụdị mgbakwunye emere. AKWỤKWỌ KWESỊRỊ ụkpụrụ yana enweghị aha. Ọ bụrụ na ewepụrụ, uru ndabara bụ OBIARA. Mgbe atọrọ oke a ka ọ bụrụ SIGNED, ihe mgbakwunye/onye na-ewepụta ihe na-akọwa ntinye data dị ka ihe nkwado abụọ bịanyere aka na ya.
Na-akọwapụta ọnụọgụ okirikiri elekere latency jikọtara ya na nsonaazụ[]. Uru nke efu (0) na-egosi na ọ nweghị nkwụsị dị adị, yana na a ga-ewepụta ọrụ njikọta naanị ozugbo. Ọ bụrụ na ewepụrụ, uru ndabara bụ 0 (anaghị etinye ya).
Na-enye gị ohere ịkọwapụta paramita kpọmkwem Intel na imewe VHDL files (.vhd). Uru ndabara bụ ejighị ya.
Na-achọpụta ọba akwụkwọ nke modul parameterized (LPM) aha ngalaba na imewe VHDL files.
Paramita akọwapụtara nke Intel. Ị ga-ejiri oke LPM_HINT iji kọwapụta paramita ONE_INPUT_IS_CONSTANT na imewe VHDL files. Uru bụ EE, mba, na ejighi ya. Na-enye njikarịcha ma ọ bụrụ na otu ntinye na-adịgide adịgide. Ọ bụrụ na ewepụrụ, uru ndabara bụ NO.
Paramita akọwapụtara nke Intel. Ị ga-ejirịrị LPM_HINT iji kọwapụta oke MAXIMIZE_SPEED na imewe VHDL files. Ị nwere ike ịkọwa uru dị n'etiti 0 na 10. Ọ bụrụ na ejiri ya, Intel Quartus Prime software na-anwa ịkwalite otu ihe atụ nke ọrụ LPM_ADD_SUB maka ọsọ ọsọ kama ịmegharị ya, ma mebie ntọala nke Optimization Technique Logic nhọrọ. Ọ bụrụ na ejighi MAXIMIZE_SPEED, uru nke Nhọrọ Nkachamma ka a na-eji kama. Ọ bụrụ na ntọala maka MAXIMIZE_SPEED bụ 6 ma ọ bụ karịa, Compiler na-ebuli LPM_ADD_SUB IP core maka ọsọ dị elu site na iji ụdọ ebu; Ọ bụrụ na ntọala ahụ bụ 5 ma ọ bụ obere, Compiler na-arụ ọrụ ahụ n'ebughị agbụ. Ekwesịrị ịkọwapụta oke a maka ngwaọrụ Cyclone, Stratix na Stratix GX naanị mgbe ejighị ọdụ ụgbọ mmiri add_sub.
A na-eji oke a maka nlegharị anya na ebumnuche ịme anwansị omume. Onye ndezi paramita na-agbakọ uru maka oke a.

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6. LPM_COMPARE (Comparator)

Onyonyo 5.

LPM_COMPARE IP isi na-atụnyere uru nke usoro data abụọ iji chọpụta mmekọrịta dị n'etiti ha. N'ụdị ya kachasị mfe, ị nwere ike iji ọnụ ụzọ pụrụ iche-OR iji chọpụta ma ibeji abụọ nke data hà nhata.

Ọnụọgụ na-esonụ na-egosi ọdụ ụgbọ mmiri maka LPM_COMPARE IP core.

Ọdụ ụgbọ mmiri LPM_COMPARE

LPM_COMPARE

clan

alb

ebe

data[]

agba

data[]

agba

elekere

ebe

aclr

ebe

inst

6.1. Atụmatụ
LPM_COMPARE IP core na-enye atụmatụ ndị a: · Na-emepụta ọrụ comparator iji tụnyere usoro abụọ nke data · Na-akwado obosara data nke 1 bits · Na-akwado usoro nnochite anya data dị ka mbinye aka na enweghị aha · Na-emepụta ụdị mmepụta ndị a:
— alb (ntinye A bụ ihe na-erughị ntinye B) — aeb (ntinye A dị ka ntinye B) — agb (ntinye A ka ntinye B) — ageb (ntinye A karịrị ma ọ bụ nhata na ntinye B) — aneb ( ntinye A adịghị nhata na ntinye B) — aleb (ntinye A erughị ma ọ bụ hà nhata na ntinye B) · Na-akwado nhọrọ asynchronous clear na elekere na-enyere ọdụ ụgbọ mmiri aka · Nyefee ntinye datab[] na-aga n'ihu mgbe niile · Na-akwado pipelining site na iji latency mmepụta ahazi

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6. LPM_COMPARE (Comparator) 683490 | 2020.10.05
6.2. Prototype Verilog HDL
Ụdị Verilog HDL ndị a dị na Verilog Design File (.v) lpm.v n'ime edesynthesis ndekọ.
modul lpm_compare (alb, aeb, agb, aleb, aneb, ageb, dataa, datab, clock, clken, aclr); oke lpm_type = "lpm_compare"; oke lpm_width = 1; paramita lpm_representation = "ESIGHỊ"; oke lpm_pipeline = 0; paramita lpm_hint = "EJIGHỊ"; ntinye [lpm_width-1:0] data, datab; elekere ntinye; ntinye klken; ntinye aclr; mmepụta alb, aeb, agb, aleb, aneb, agba; endmodule
6.3. Nkwupụta akụkụ VHDL
Nkwupụta akụrụngwa VHDL dị na Nhazi VHDL File (.vhd) LPM_PACK.vhd n'ime akwụkwọ ndekọ aha vhdllpm.
akụrụngwa LPM_COMPARE jeneriki (LPM_WIDTH: eke;
LPM_Nnọchite anya : eriri : = "Enweghị aha"; LPM_PIPELINE : eke: = 0; LPM_TYPE: eriri: = L_COMPARE; LPM_HINT: eriri: = "EJIGHỊ"); ọdụ ụgbọ mmiri (DATAA: na std_logic_vector (LPM_WIDTH-1 ruo 0); DATAB: na std_logic_vector (LPM_WIDTH-1 ruo 0); ACLR: na std_logic: = '0'; CLOCK: na std_logic na : CL '0'; : = '1'; AGB: out std_logic; AEB: out std_logic; akụkụ njedebe;
6.4. Nkwupụta VHDL LIBRARY_USE
Achọghị nkwupụta VHDL LIBRARY-USE ma ọ bụrụ na ijiri nkwupụta akụrụngwa VHDL.
Ụlọ akwụkwọ lpm; Jiri lpm.lpm_components.all;
6.5. ọdụ ụgbọ mmiri
Tebụlụ ndị a depụtara ọdụ ụgbọ mmiri ntinye na mmepụta maka LMP_COMPARE IP core.

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Tebụl 18. LPM_COMPARE IP isi ntinye ọdụ ụgbọ mmiri

Aha Port

Achọrọ

Nkọwa

data[]

Ntinye data. Ogo ọdụ ụgbọ mmiri ntinye dabere na uru paramita LPM_WIDTH.

data[]

Ntinye data. Ogo ọdụ ụgbọ mmiri ntinye dabere na uru paramita LPM_WIDTH.

elekere

Mba

Ntinye elekere maka ojiji pipeline. Ọdụ ụgbọ mmiri elekere na-enye ntinye elekere maka pipelined

ọrụ. Maka ụkpụrụ LPM_PIPELINE karịa 0 (ndabere), ọdụ ụgbọ mmiri ga-abụrịrị

enyere.

clan

Mba

Kwado elekere maka ojiji pipeline. Mgbe a na-ekwusi ike na ọdụ ụgbọ mmiri klken dị elu, nke

ọrụ ntụnyere na-ewere ọnọdụ. Mgbe mgbama dị ala, ọ nweghị ọrụ na-eme. Ọ bụrụ

ewepụrụ, uru ndabara bụ 1.

aclr

Mba

Asynchronous doro anya maka ojiji pipeline. Pipeline na-amalite na mgbagha (X) enweghị nkọwa

ọkwa. Enwere ike iji ọdụ ụgbọ mmiri aclr n'oge ọ bụla iji tọgharịa pipeline na 0s niile,

asynchronously na mgbama elekere.

Tebụl 19. LPM_COMPARE IP core Output Ports

Aha Port

Achọrọ

Nkọwa

alb

Mba

Ọdụ ụgbọ mmiri mmepụta maka comparator. Ekwenyere ma ọ bụrụ na ntinye A erughị ntinye B.

ebe

Mba

Ọdụ ụgbọ mmiri mmepụta maka comparator. Ekwenyere ma ọ bụrụ na ntinye A hà nhata na ntinye B.

agba

Mba

Ọdụ ụgbọ mmiri mmepụta maka comparator. Ekwenyere ma ọ bụrụ na ntinye A karịrị ndenye B.

agba

Mba

Ọdụ ụgbọ mmiri mmepụta maka comparator. Ekwenyere ma ọ bụrụ na ntinye A karịrị ma ọ bụ hà nhata na ntinye

ebe

Mba

Ọdụ ụgbọ mmiri mmepụta maka comparator. Ekwenyere ma ọ bụrụ na ntinye A erughị ka ntinye B.

ebe

Mba

Ọdụ ụgbọ mmiri mmepụta maka comparator. Ekwenyere ma ọ bụrụ na ntinye A erughị ma ọ bụ hà nhata na ntinye B.

6.6. Nkeji

Tebụlụ na-esonụ na-edepụta parampat maka LPM_COMPARE IP isi.

Tebụl 20. LPM_COMPARE IP core Parameters

Aha oke

Ụdị

Achọrọ

LPM_WIDTH

Integer Ee

LPM_REPRESENTATION

Ụdọ

Mba

LPM_PIPELINE

Ọnụọgụ nọmba

LPM_HINT

Ụdọ

Mba

Nkọwa
Na-akọwapụta obosara nke ọdụ ụgbọ mmiri dataa[] na datab[].
Na-akọwapụta ụdị ntụnyere emere. AKWỤKWỌ KWESỊRỊ ụkpụrụ yana enweghị aha. Ọ bụrụ na ewepụrụ, uru ndabara bụ EKWESỊGHỊ. Mgbe atọrọ uru oke a na SIGNED, onye comparator na-akọwa ntinye data dị ka ihe nkwado abụọ bịanyere aka na ya.
Na-akọwapụta ọnụọgụ elekere nke latency jikọtara ya na mmepụta alb, aeb, agb, ageb, aleb, ma ọ bụ aneb. Uru nke efu (0) na-egosi na ọ nweghị nkwụsị dị adị, yana na a ga-ewepụta ọrụ njikọta naanị ozugbo. Ọ bụrụ na ewepụrụ, uru ndabara bụ 0 (anaghị etinye ya).
Na-enye gị ohere ịkọwapụta paramita kpọmkwem Intel na imewe VHDL files (.vhd). Uru ndabara bụ ejighị ya.
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6. LPM_COMPARE (Comparator) 683490 | 2020.10.05
Oke aha LPM_TYPE INTENDED_DEVICE_FAMILY
ONE_INPUT_IS_CONSTANT

Ụdị eriri eriri
Ụdọ

Achọrọ Mba Mba
Mba

Nkọwa
Na-achọpụta ọba akwụkwọ nke modul parameterized (LPM) aha ngalaba na imewe VHDL files.
A na-eji oke a maka nlegharị anya na ebumnuche ịme anwansị omume. Onye ndezi paramita na-agbakọ uru maka oke a.
Paramita akọwapụtara nke Intel. Ị ga-ejiri oke LPM_HINT iji kọwapụta paramita ONE_INPUT_IS_CONSTANT na imewe VHDL files. Uru bụ EE, mba, ma ọ bụ ejighi ya. Na-enye njikarịcha ma ọ bụrụ na ntinye na-adịgide adịgide. Ọ bụrụ na ewepụrụ, uru ndabara bụ NO.

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7. ALTECC (Error Mmezi Code: Encoder/Decoder) IP Core

Onyonyo 6.

Intel na-enye ALTECC IP isi iji mejuputa ọrụ ECC. ECC na-achọpụta data mebiri emebi na-eme n'akụkụ nnata n'oge nnyefe data. Usoro mgbazi njehie a kacha dabara adaba maka ọnọdụ ebe mperi na-eme na enweghị usoro kama ịgbawa.

ECC na-achọpụta mperi site na usoro ntinye data na ngbanwe. Maka example, mgbe etinyere ECC na ngwa nnyefe, data agụ si na isi mmalite na-edobe tupu ezigara onye nnata ya. Mmepụta (okwu koodu) sitere na koodu ngbanwe nwere data a na-edoghị anya nke etinyere na ọnụọgụ nke ibe n'ibe. Ọnụ ọgụgụ ziri ezi nke ibe n'ibe agbakwunyere dabere na ọnụọgụ nke ibe n'ime data ntinye. A na-ebunye okwu koodu emepụtara na ebe a na-aga.

Onye nnata na-enweta koodu koodu wee depụta ya. Ozi nwetara site na decoder na-ekpebi ma achọpụtara mperi. The decoder na-achọpụta njehie otu-bit na abụọ-bit, mana ọ nwere ike idozi naanị njehie otu-bit na data mebiri emebi. Ụdị ECC a bụ nchọpụta njehie ugboro abụọ (SECDED).

Ị nwere ike hazie koodu ntinye na ọrụ ngbanwe nke ALTECC IP core. A na-edobe ntinye data na koodu ngbanwe ka iwepụta mkpụrụokwu koodu bụ nchikota ntinye data na ibe n'ibe n'ụdị emepụtara. A na-ebufe mkpụrụokwu koodu emepụtara na modul decoder maka imezi koodu tupu eruo ngọngọ ebe ọ na-aga. Ihe ngbanwe ahụ na-ewepụta vector syndrome iji chọpụta ma ọ dị mperi na mkpụrụokwu koodu enwetara. The decoder na-edozi data naanị ma ọ bụrụ na njehie otu-bit sitere na ibe n'ibe data. Enweghị akara ngosi ọ bụla ma ọ bụrụ na njehie otu-bit sitere na ibe n'ibe. Ihe ngbanwe ahụ nwekwara akara ọkọlọtọ iji gosi ọkwa nke data enwetara yana ihe onye ngbanwe mere, ọ bụrụ na ọ dị.

Ọnụọgụ ndị a na-egosi ọdụ ụgbọ mmiri maka isi ALTECC IP.

Ọdụ ụgbọ mmiri ALTECC

ALTECC_ENCODER

data[]

q[]

elekere

aclr

inst

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7. ALTECC (Error Mmezi Usoro: Encoder/Decoder) IP Core 683490 | 2020.10.05

Ọgụgụ 7. ALTECC Decoder Ports

ALTECC_DECODER

data[] elekere elekere

q[] err_chọpụtara err_mezie
err_fatal

aclr

inst

7.1. Njirimara ALTECC Encoder

Ihe ngbanwe ALTECC IP isi na-enye atụmatụ ndị a: · Na-eme koodu ntinye data site na iji atụmatụ Hamming Coding · Na-akwado obosara data nke 2 bits · Na-akwado usoro nnochite anya data bịanyere aka na nke na-edeghị aha · Nkwado pipelining na nkwụsị mmepụta nke ma ọ bụ otu elekere ma ọ bụ abụọ elekere · Na-akwado nhọrọ nhọrọ. asynchronous doro anya na elekere na-enyere ọdụ ụgbọ mmiri

Ihe mkpuchi ALTECC IP isi na-ewebata wee tinye koodu ahụ site na iji atụmatụ koodu Hamming. Atụmatụ koodu Hamming na-ewepụta ihe nhata ma tinye ha na data mbụ iji mepụta okwu koodu mmepụta. Ọnụọgụ nke ibe ngwungwu agbakwunyere dabere na obosara nke data ahụ.

Tebụlụ na-esonụ na-edepụta ọnụ ọgụgụ nke nha nha agbakwunyere maka ọkwa dị iche iche nke obosara data. Kọlụm mkpokọta Bits na-anọchi anya ọnụọgụ ọnụọgụ data ntinye yana ngwungwu agbakwunyere.

Tebụl 21.

Ọnụọgụ nke Parity Bits na Usoro Okwu Dị ka obosara data siri dị

Ogologo data

Ọnụọgụ nke nha nhata

Mkpokọta Bits (koodu Okwu)

2-4

3+1

6-8

5-11

4+1

10-16

12-26

5+1

18-32

27-57

6+1

34-64

58-64

7+1

66-72

Mwepụta nke mbịarambịa na-eji nleba anya nha anya. Ihe mgbakwunye 1 (nke egosiri na tebụl dị ka +1) ka etinyere na ibe n'ike n'ike dịka MSB nke okwu koodu. Nke a na-eme ka a mata na koodu koodu nwere ọnụọgụgụ nke 1. Maka example, ọ bụrụ na obosara data bụ 4 ibe n'ibe, 4 parity ibe n'ibe na-agbakwunyere na data ka ọ bụrụ koodu koodu na ngụkọta nke 8 ibe n'ibe. Ọ bụrụ na 7 ibe n'ibe sitere na LSB nke okwu koodu 8-bit nwere ọnụ ọgụgụ dị njọ nke 1, nke 8th bit (MSB) nke koodu koodu bụ 1 na-eme ka ngụkọta nke 1 dị na koodu koodu ọbụna.
Ọnụọgụ na-esonụ na-egosi koodu agbapụtara na nhazi nke ibe n'ibe na data n'ime ntinye data 8-bit.

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Onyonyo 8.

Nhazi Bits na Data Bits n'ime Okwu Koodu Mepụtara 8-bit

Ọkachamara

LSB

4 parity ibe n'ibe

4 nkeji data

Ihe ntinye koodu ALTECC IP na-anabata naanị obosara ntinye nke 2 ruo 64 n'otu oge. obosara ntinye nke 12 bits, 29bits, na 64bits, bụ ndị dabara adaba na ngwaọrụ Intel, na-emepụta ntinye nke 18 bits, 36 bits, na 72 bits n'otu n'otu. Ị nwere ike ijikwa mmachi bitselection na nchịkọta nhọrọ parameter.

7.2. Ụdị Verilog HDL (ALTECC_ENCODER)
Ụdị Verilog HDL ndị a dị na Verilog Design File (.v) lpm.v n'ime edesynthesis ndekọ.
modul altecc_encoder #(parameter decide_device_family = "ejighi ya", parameter lpm_pipeline = 0, parameter width_codeword = 8, parameter width_dataword = 8, parameter lpm_type = "altecc_encoder", parameter lpm_hint = "ejighi ya") (ntinye waya aclr, ntinye waya elekere waya, waya ntinye [width_dataword-1:0] data, waya mmepụta [width_codeword-1:0] q); endmodule

7.3. Ụdị Verilog HDL (ALTECC_DECODER)
Ụdị Verilog HDL ndị a dị na Verilog Design File (.v) lpm.v n'ime edesynthesis ndekọ.
modul altecc_decoder #(parametertention_device_family = "ejighi ya", parameter lpm_pipeline = 0, parameter width_codeword = 8, parameter width_dataword = 8, parameter lpm_type = "altecc_decoder", parameter lpm_hint = "ejighi ya") (mgbanye waya aclr, ntinye waya elekere waya, waya ntinye [width_codeword-1:0] data, waya mmepụta err_corrected, mmepụta waya err_detected, outut waya err_fatal, mmepụta waya [width_dataword-1:0] q); endmodule

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7.4. Nkwupụta akụkụ VHDL (ALTECC_ENCODER)
Nkwupụta akụrụngwa VHDL dị na Nhazi VHDL File (.vhd) altera_mf_components.vhd na librariesvhdlaltera_mf ndekọ.
akụrụngwa altecc_encoder jeneriki (zubere_device_family: eriri: = "ejighi ya"; lpm_pipeline: eke: = 0; width_codeword: eke: = 8; width_dataword: eke: = 8; lpm_hint: eriri: = "UNUSED"; lpm_encoder: CC: ”); ọdụ ụgbọ mmiri (aclr: na std_logic: = '0'; elekere: na std_logic: = '0'; clocken: na std_logic: = '1'; data: na std_logic_vector (width_dataword-1 ruo 0); q: pụọ std_logic_vector (wid std_logic_vector) -1 ruo 0)); akụkụ njedebe;
7.5. Nkwuwapụta akụkụ VHDL (ALTECC_DECODER)
Nkwupụta akụrụngwa VHDL dị na Nhazi VHDL File (.vhd) altera_mf_components.vhd na librariesvhdlaltera_mf ndekọ.
akụrụngwa altecc_decoder jeneriki (zubere_device_family: eriri: = "ejighi ya"; lpm_pipeline: eke: = 0; width_codeword: eke: = 8; width_dataword: eke: = 8; lpm_hint: eriri: = "UNUSED"; lpm_de: string: string ”); ọdụ ụgbọ mmiri (aclr: na std_logic: = '0'; elekere: na std_logic: = '0'; clocken: na std_logic: = '1'; data: na std_logic_vector (width_codeword-1 ruo 0); err_corrected : out std_logic : pụta std_logic; akụkụ njedebe;
7.6. Nkwupụta VHDL LIBRARY_USE
Achọghị nkwupụta VHDL LIBRARY-USE ma ọ bụrụ na ijiri nkwupụta akụrụngwa VHDL.
LIBRARY altera_mf; Jiri altera_mf.altera_mf_components.all;
7.7. Ports encoder
Tebụlụ ndị a depụtara ọdụ ụgbọ mmiri ntinye na mmepụta maka ALTECC encoder IP core.

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Isiokwu 22. ALTECC Encoder ọdụ ụgbọ mmiri

Aha Port

Achọrọ

Nkọwa

data[]

ọdụ ụgbọ mmiri ntinye data. Ogo ọdụ ụgbọ mmiri ntinye dabere na WIDTH_DATAWORD

oke uru. Ọdụ ụgbọ mmiri[] nwere data adịchaghị nke a ga-etinye koodu.

elekere

Ọdụ ụgbọ mmiri ntinye elekere nke na-enye mgbama elekere iji mekọrịta ọrụ ntinye.

Achọrọ ọdụ ụgbọ mmiri elekere mgbe uru LPM_PIPELINE karịrị 0.

elekere

Mba

Kwado elekere. Ọ bụrụ na ewepụrụ, uru ndabara bụ 1.

aclr

Mba

Ntinye doro anya na-ejikọtaghị ọnụ. Enwere ike iji mgbama elu aclr na-arụ ọrụ n'oge ọ bụla

kpochapu ihe ndekọ ahụ n'otu n'otu.

Isiokwu 23. ALTECC Encoder Output Ports

Aha Port q[]

Achọrọ Ee

Nkọwa
ọdụ ụgbọ mmiri mmepụta data etinyere. Nha ọdụ ụgbọ mmiri mmepụta dabere na uru paramita WIDTH_CODEWORD.

7.8. Ports decoder

Tebụlụ ndị a depụtara ọdụ ụgbọ mmiri ntinye na mmepụta maka ALTECC decoder IP core.

Tebụl 24. ALTECC Decoder ọdụ ụgbọ mmiri

Aha Port

Achọrọ

Nkọwa

data[]

ọdụ ụgbọ mmiri ntinye data. Ogo ọdụ ụgbọ mmiri ntinye dabere na uru paramita WIDTH_CODEWORD.

elekere

Ọdụ ụgbọ mmiri ntinye elekere nke na-enye mgbama elekere iji mekọrịta ọrụ ntinye. Achọrọ ọdụ ụgbọ mmiri elekere mgbe uru LPM_PIPELINE karịrị 0.

elekere

Mba

Kwado elekere. Ọ bụrụ na ewepụrụ, uru ndabara bụ 1.

aclr

Mba

Ntinye doro anya na-ejikọtaghị ọnụ. Enwere ike iji akara aclr dị elu na-arụ ọrụ n'oge ọ bụla iji kpochapụ ndekọ aha n'otu oge.

Isiokwu 25. ALTECC Decoder Output Ports

Aha Port q[]

Achọrọ Ee

Nkọwa
ọdụ ụgbọ mmiri ewepụtara data. Ogo ọdụ ụgbọ mmiri mmepụta dabere na uru paramita WIDTH_DATAWORD.

err_chọpụtara Ee

Ọkọlọtọ ọkọlọtọ iji gosipụta ọkwa nke data enwetara wee kọwapụta mperi ọ bụla achọtara.

err_ziri ezi Ee d

Mgbama ọkọlọtọ iji gosipụta ọkwa data enwetara. Na-egosi mperi otu-bit chọtara ma mezie ya. Ị nwere ike iji data ahụ n'ihi na edozila ya.

err_fatal

Mgbama ọkọlọtọ iji gosipụta ọkwa data enwetara. Na-egosi mperi-bit abụọ achọtara, mana emezighị ya. Ị gaghị eji data ahụ ma ọ bụrụ na ekwenyesiri ike na mgbaama a.

syn_e

Mba

Mgbama mmepụta ga-adị elu mgbe ọ bụla achọpụtara mperi otu-bit na nha nha

ibe n'ibe.

7.9. Ihe ngbanwe koodu
Tebụlụ na-esonụ na-edepụta parampat maka ALTECC encoder IP core.

Ntuziaka onye ọrụ Intel FPGA Integer Arithmetic IP Cores 34

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Isiokwu 26. ALTECC Encoder Parameters

Aha oke

Ụdị

Achọrọ

Nkọwa

WIDTH_DATAWORD

Integer Ee

Na-akọwapụta obosara nke data raw. Uru sitere na 2 ruo 64. Ọ bụrụ na ewepụrụ ya, uru ndabara bụ 8.

WIDTH_CODEWORD

Integer Ee

Na-akọwapụta obosara nke okwu koodu kwekọrọ. Ụkpụrụ ziri ezi sitere na 6 ruo 72, ewezuga 9, 17, 33, na 65. Ọ bụrụ na ewepụrụ ya, uru ndabara bụ 13.

LPM_PIPELINE

Ọnụọgụ nọmba

Na-akọwapụta pipeline maka sekit. Uru sitere na 0 ruo 2. Ọ bụrụ na uru bụ 0, edeghị ọdụ ụgbọ mmiri ndị ahụ. Ọ bụrụ na ọnụ ahịa ahụ bụ 1, edebanye aha ọdụ ụgbọ mmiri mmepụta. Ọ bụrụ na ọnụ ahịa ahụ bụ 2, a na-edebanye aha ntinye na ọdụ ụgbọ mmiri. Ọ bụrụ na ewepụrụ, uru ndabara bụ 0.

7.10. Paramita ihe ndozi

Tebụlụ na-esote depụtara ALTECC decoder IP core parameters.

Isiokwu 27. ALTECC Decoder Parameters

Oke aha WIDTH_DATAWORD

Ụdị Integer

Achọrọ

Nkọwa

Na-akọwapụta obosara nke data raw. Uru bụ 2 ruo 64. The

uru ndabara bụ 8.

WIDTH_CODEWORD

Ọnụọgụ

Na-akọwapụta obosara nke okwu koodu kwekọrọ. Uru bụ 6

ruo 72, ewezuga 9, 17, 33, na 65. Ọ bụrụ na ewepụrụ, uru ndabara

bụ 13 €.

LPM_PIPELINE

Ọnụọgụ

Mba

Na-akọwapụta ndekọ nke sekit. Uru sitere na 0 ruo 2. Ọ bụrụ na

uru bụ 0, ọ dịghị ndekọ na-emejuputa atumatu. Ọ bụrụ na uru bụ 1, na

edebanye aha mmepụta. Ọ bụrụ na uru bụ 2, ma ntinye na nke

edebanye aha mmepụta. Ọ bụrụ na uru karịrị 2, gbakwunyere

A na-emejuputa ndekọ ndekọ na mmepụta maka mgbakwunye

latencies. Ọ bụrụ na ewepụrụ, uru ndabara bụ 0.

Mepụta ọdụ ụgbọ mmiri 'syn_e'

Ọnụọgụ

Mba

Gbanwuo oke a ka imepụta ọdụ ụgbọ mmiri syn_e.

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8. Intel FPGA Multiply Adder IP Core

Onyonyo 9.

The Intel FPGA Multiply Adder (Intel Stratix 10, Intel Arria 10, na Intel Cyclone 10 GX ngwaọrụ) ma ọ bụ ALTERA_MULT_ADD (Arria V, Stratix V, na Cyclone V ngwaọrụ) IP isi na-enye gị ohere mejuputa a multiplier-adder.

Ọnụọgụ a na-egosi ọdụ ụgbọ mmiri maka Intel FPGA Multiply Adder ma ọ bụ ALTERA_MULT_ADD IP core.

Intel FPGA Multiply Adder ma ọ bụ ọdụ ụgbọ mmiri ALTERA_MULT_ADD

Intel FPGA Multiply Adder ma ọ bụ ALTERA_MULT_ADD

dataa[] akara datab[] signb datac[] coefsel0[] coefsel1[] coefsel2[] coefsel3[] addnsub1 addnsub3 aclr/sclr[] scanina[] clock0 clock1 clock2 ena0 ena1 ena2 sload_accum
accum_sload chainin[]

nsonaazụ scanouta[]

aclr0 aclr1

inst
Onye na-abawanye ụba-adder na-anabata ụzọ abụọ nke ntinye, na-amụba ụkpụrụ ọnụ wee gbakwunye na ma ọ bụ wepụ na ngwaahịa nke ụzọ abụọ ndị ọzọ.
Ọ bụrụ na obosara ntinye data niile dị 9-bit n'obosara ma ọ bụ obere, ọrụ ahụ na-eji nhazi ntinye ntinye ntinye 9 x 9 bit na ngọngọ DSP maka ngwaọrụ ndị na-akwado nhazi 9 x 9. Ọ bụrụ na ọ bụghị, ngọngọ DSP na-eji ntinye ntinye ntinye 18 × 18-bit iji hazie data na obosara n'etiti 10 bits na 18 bits. Ọ bụrụ na otutu Intel FPGA Multiply Adder ma ọ bụ ALTERA_MULT_ADD IP cores na-eme na imewe, a na-ekesa ọrụ ndị dị ka

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8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05
ọtụtụ ngọngọ DSP dị iche iche dị ka o kwere mee ka ụzọ na-aga na ngọngọ ndị a na-agbanwe agbanwe. Ndị na-emewanyewanye ihe n'otu ngọngọ DSP na-enye ohere ka nhọrọ ntụgharị ọzọ banye na ngọngọ site na ibelata ụzọ gaa na ngwaọrụ ndị ọzọ.
A na-etinyekwa ndekọ ndekọ na akwụkwọ ndekọ pipeline maka akara ndị a n'ime ngọngọ DSP: · Ntinye data · mbinye aka ma ọ bụ nke edeghị aha họrọ · Tinye ma ọ bụ wepụ họrọ · Ngwaahịa nke ndị na-abawanye ụba.
N'ihe banyere nsonaazụ mmepụta, a na-etinye ndekọ mbụ na ngọngọ DSP. Otú ọ dị, a na-edobe akwụkwọ ndekọ latency ndị ọzọ n'ime ihe mgbagha na mpụga ngọngọ. Ihe dị n'akụkụ ngọngọ DSP, gụnyere ntinye data na ụbara, ntinye akara njikwa, na ntinye nke adder, na-eji ụzọ ntụgharị oge niile iji kparịta ụka na ngwaọrụ ndị ọzọ. Njikọ niile dị na ọrụ ahụ na-eji ụzọ a raara onwe ya nye n'ime ngọngọ DSP. Ụzọ a raara onwe ya nye na-agụnye ụdọ ndekọ mgbanwe mgbanwe mgbe ị họrọ nhọrọ iji gbanwee data ntinye ndebanye aha nke ọtụtụ site na otu ọnụọgụ gaa na nke dị n'akụkụ.
Maka ozi ndị ọzọ gbasara ngọngọ DSP n'ime usoro ngwaọrụ Stratix V na Arria V ọ bụla, rụtụ aka na DSP Blocks isi nke akwụkwọ ntuziaka dị iche iche na ibe akwụkwọ edemede na nka nka.
Ozi emetụtara AN 306: Na-eme ọtụtụ ihe n'ime ngwaọrụ FPGA
Na-enye ozi ndị ọzọ gbasara mmejuputa atumatu n'iji DSP na ebe nchekwa na ngwaọrụ Intel FPGA.
8.1. Atụmatụ
Intel FPGA Multiply Adder ma ọ bụ ALTERA_MULT_ADD IP core na-enye atụmatụ ndị a:
ọnụọgụgụ Rịba ama: Mgbe ị na-ewu ọtụtụ ndị na-ebuwanye ibu karịa nha nke obodo akwadoro enwere ike/
ga-abụ mmetụta arụmọrụ sitere na cascading nke ngọngọ DSP. Na-akwado obosara data nke 1 256 bits · Na-akwado usoro nnochite anya data bịanyere aka na ya na nke edeghị aha. Nhọrọ asynchronous na synchronous doro anya na elekere na-enye ohere ntinye ọdụ ụgbọ mmiri · Na-akwado ọnọdụ ndekọ igbu oge systolic · Na-akwado tupu adder na 8 pre-load coefficients per multiplier · Na-akwado ibu ibu mgbe niile iji kwado nzaghachi mkpokọta

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8.1.1. Pre-adder
Na pre-adder, mgbakwunye ma ọ bụ mwepu ka a na-eme tupu enye nri nke ukwuu.
Enwere usoro ụzọ tupu adder ise: · Ụdị dị mfe · Ọnọdụ ọnụọgụ · Ụdị ntinye · Square mode · Ọnọdụ mgbe niile

Mara:

Mgbe eji pre-adder (pre-adder coefficient/input/square mode), ihe ntinye data niile na-abawanye ga-enwerịrị otu ntọala elekere.

8.1.1.1. Pre-adder Mfe Mode

N'ụdị a, operands abụọ na-enweta site na ọdụ ụgbọ mmiri ntinye na pre-adder adịghị eji ma ọ bụ gafere. Nke a bụ ọnọdụ ndabara.

Ọgụgụ 10. Pre-adder Mfe Mode
a0 b0

Mult0

pụta

8.1.1.2. Ụdị ọnụọgụgụ tupu-adder
Na nke a mode, otu multiplier operand na-enweta site na pre-adder, na nke ọzọ operand na-enweta na esịtidem ọnụọgụ nchekwa nchekwa. Ebe nchekwa ọnụọgụ na-enye ohere ruo 8 preset constants. Ihe nrịbama nhọrọ ọnụọgụ bụ coefsel[0..3].
A na-egosipụta ọnọdụ a n'usoro n'usoro.

Ndị na-esonụ na-egosi usoro ọnụọgụ ọnụọgụ tupu adder nke ọtụtụ.

Ọgụgụ 11. Pre-adder Coefficient Mode

Onye na-agụ ihe

Mult0

+/-

pụta

coefsel0 coef

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8.1.1.3. Ọnọdụ ntinye tupu adder Na ọnọdụ a, otu operand na-ebuwanye ibu na-enweta site na pre-adder, nke ọzọ operand na-enweta site na ọdụ datac[]. A na-egosipụta ọnọdụ a n'usoro n'usoro.

Ndị na-esonụ na-egosi ụdị ntinye tupu adder nke ọtụtụ.

Ọgụgụ 12. Ụdị ntinye nke mbụ
a0 b0

Mult0

+/-

pụta

8.1.1.4. Pre-adder Square Mode A na-egosipụta ọnọdụ a n'usoro na-esonụ.

Ndị na-esonụ na-egosi tupu adder square mode nke abụọ multipliers.

Ọgụgụ 13. Pre-adder Square Mode
a0 b0

Mult0

+/-

pụta

8.1.1.5. Ọnọdụ mgbe niile tupu-adder
Na nke a mode, otu multiplier operand na-enweta site n'ọdụ ụgbọ mmiri ntinye, na nke ọzọ operand na-enweta na esịtidem ọnụọgụ nchekwa nchekwa. Ebe nchekwa ọnụọgụ na-enye ohere ruo 8 preset constants. Ihe nrịbama nhọrọ ọnụọgụ bụ coefsel[0..3].
A na-egosipụta ọnọdụ a n'usoro n'usoro.

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Ọnụọgụ na-esonụ na-egosi na tupu adder mgbe nile mode nke a multiplier.

Ọgụgụ 14. Pre-adder Constant Mode
a0

Mult0

pụta

agba 0
coef
8.1.2. Ndebanye aha igbu oge systolic
N'ime ihe owuwu systolic, a na-etinye data ntinye n'ime ebe ndekọ aha na-eme dị ka ihe nchekwa data. Ndebanye aha ọ bụla na-ebunye ntinye sample ka onye na-abawanye ụba ebe a na-amụba ya site na ọnụọgụ dị iche iche. Akara agbụ a na-echekwa rịzọlt ji nwayọọ nwayọọ na-ejikọta site na ụbara yana nsonaazụ edebanye aha mbụ sitere na ọdụ ụgbọ mmiri chainin[] iji mepụta nsonaazụ ikpeazụ. Ihe mgbakwunye mgbakwunye ọ bụla ga-egbu oge site na otu okirikiri ka nsonaazụ ya mekọrịta nke ọma mgbe agbakwunyere ọnụ. A na-eji igbu oge ọ bụla na-aga n'ihu na-eleba anya ma ebe nchekwa ọnụọgụ yana nchekwa data nke ihe mgbakwunye ọtụtụ n'otu n'otu. Maka example, otu igbu oge maka nke abụọ ịba ụba tinye mmewere, abụọ igbu oge maka nke atọ ịba ụba-gbakwunye element, na na.
Ọgụgụ 15. Systolic Registers
Akwụkwọ ndekọ systolic

x (t) c(0)

S-1

c(1)

S-1

c(2)

S-1

c(N-1)

S-1

S -1 y (t)

x(t) na-anọchite anya nsonaazụ sitere na iyi ntinye s na-aga n'ihuamples na y (t)
na-anọchi anya nchikota nke otu ntinye samples, na oge, mụbaa site na ha
ụdị ọnụọgụgụ. Ma nsonaazụ ntinye na mmepụta na-esi n'aka ekpe gaa n'aka nri. Ihe c(0) ruo c(N-1) na-egosi ọnụọgụgụ. A na-akọwapụta ndekọ igbu oge systolic site na S-1, ebe 1 na-anọchi anya otu oge igbu oge. A na-agbakwunye ndekọ igbu oge systolic na
ntinye na ntinye maka pipelining n'ụzọ na-eme ka ihe si na ya pụta
multiplier operand na nchikota chịkọbara na-anọ na synch. Nke a nhazi mmewere
a na-emegharịgharị iji mepụta sekit nke na-agbakọ ọrụ nzacha. Ọrụ a bụ
ekwuputara n'usoro n'okpuru.

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N na-anọchi anya ọnụọgụ nke usoro data nke batara n'ime ihe nchịkọta, y (t) na-anọchite anya mmepụta n'oge t, A(t) na-anọchite anya ntinye n'oge t, na B(i) bụ ọnụọgụgụ. T na i na nha nhata kwekọrọ n'otu ntabi anya n'ime oge, yabụ iji gbakọọ mmepụta sample y (t) n'oge t, otu ntinye samples na N dị iche iche n'oge, ma ọ bụ A(n), A(n-1), A(n-2), … A(n-N+1) ka achọrọ. Otu ntinye N sampA na-amụba les site na ọnụọgụ N wee chịkọta ọnụ iji mepụta nsonaazụ ikpeazụ y.
Ihe owuwu ndekọ systolic dị naanị maka ụdị nchikota-2 na nchikota-4. Maka ụdị ụlọ ndekọ aha systolic abụọ, ọ dị mkpa ijikọ akara chainin nke mbụ na 0.
Ọnụọgụ na-esonụ na-egosi mmejuputa ndebanye aha igbu oge systolic nke ọnụọgụ abụọ.
Ọgụgụ 16. Ndebanye aha igbu oge systolic mmejuputa nke 2 Multipliers
chainin

Mult0

+/-

Mult1

+/-

pụta
A na-egosipụta nchikota nke nbawanye ụba abụọ n'usoro na-esote.
Ọnụọgụ na-esonụ na-egosi mmejuputa ndebanye aha igbu oge systolic nke ọnụọgụ abụọ.

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Ọgụgụ 17. Ndebanye aha igbu oge systolic mmejuputa nke 4 Multipliers
chainin

Mult0

+/-

Mult1

+/-

Mult2

+/-

Mult3

+/-

pụta
A na-egosipụta nchikota nke ọnụọgụ anọ n'usoro n'usoro. Ọgụgụ 18. Nchikota nke 4 Multipliers
Ndị a na-edepụta advantagMmejuputa ndebanye aha systolic: · Na-ebelata ojiji akụrụngwa DSP · Na-eme ka eserese nke ọma na ngọngọ DSP site na iji usoro adder chain.

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8.1.3. Buru ụzọ ebu Constant
Ibu ibu mgbe niile na-achịkwa operand accumulator ma na-emeju nzaghachi mkpokọta. LOADCONST_VALUE dị irè sitere na 0. Uru mgbe niile ruru 64N, ebe N = LOADCONST_VALUE. Mgbe edobere LOADCONST_VALUE ka ọ bụrụ 2, uru ya na-adị mgbe niile ruru 64. Enwere ike iji ọrụ a dị ka okirikiri na-enweghị isi.
Ọnụọgụ na-esonụ na-egosi mmejuputa a ga-ebufe ibu mgbe niile.
Ọgụgụ 19. Tupu-ebufe Constant

Accumulator nzaghachi

na-adịgide adịgide

Mult0

+/-

Mult1

+/b1

pụta

accum_sload sload_accum

Rụtụ aka na cores IP ndị a maka mmejuputa ọtụtụ ihe ndị ọzọ: · ALTMULT_ACCUM · ALTMEMMULT · LPM_MULT
8.1.4. Accumulator ugboro abụọ
Njirimara mkpokọta okpukpu abụọ na-agbakwunye ndebanye aha ọzọ na ụzọ nzaghachi mkpokọta. Ndebanye aha nnabata okpukpu abụọ na-esote ndekọ mmepụta, nke gụnyere elekere, ike elekere, na aclr. Ndebanye aha mkpokọta ihe mgbakwunye na-eweghachi nsonaazụ ya na igbu oge otu okirikiri. Njirimara a na-enyere gị aka ịnweta ọwa mkpokọta abụọ nwere otu ọnụọgụ akụrụngwa.
Ọnụ ọgụgụ na-esonụ na-egosi mmejuputa accumulator okpukpu abụọ.

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Ọgụgụ 20. Ugboro abụọ Accumulator

Ndebanye aha mulator ugboro abụọ

Accu mulator feedba ck

Mult0

+/-

Mult1

+/b1

Ndebanye aha mmepụta ihe

8.2. Prototype Verilog HDL
Ị nwere ike ịchọta Intel FPGA Multiply Adder ma ọ bụ ALTERA_MULT_ADD Verilog HDL prototype. file (altera_mult_add_rtl.v) na akwụkwọ ndekọ ụlọ akwụkwọmegafunctions.
8.3. Nkwupụta akụkụ VHDL
Nkwupụta akụrụngwa VHDL dị na altera_lnsim_components.vhd na librariesvhdl altera_lnsim ndekọ.
8.4. Nkwupụta VHDL LIBRARY_USE
Achọghị nkwupụta VHDL LIBRARY-USE ma ọ bụrụ na ijiri nkwupụta akụrụngwa VHDL.
LIBRARY altera_mf; Jiri altera_mf.altera_mf_components.all;

8.5. Akara ngosi

Tebụl ndị a na-edepụta akara ntinye na mmepụta nke Multiply Adder Intel FPGA IPor ALTERA_MULT_ADD IP core.

Tebụl 28. Mmụba Adder Intel FPGA IPor ALTERA_MULT_ADD akara ngosi ntinye

Signal

Achọrọ

Nkọwa

dataa_0[]/data_1[]/

dataa_2[]/data_3[]

Ntinye data na otutu. Ntinye ọdụ ụgbọ mmiri [NUMBER_OF_MULTIPLIERS * WIDTH_A – 1 … 0] n'obosara
gara n'ihu…

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Signal datab_0[]/datab_1[]/ datab_2[]/datab_3[] datac_0[] /datac_1[]/ datac_2[]/datac_3[] elekere[1:0] aclr[1:0] sclr[1:0] ena [1:0] akara
akara
scanina[] accum_sload

Achọrọ Ee Mba
Mba Mba Mba Mba Mba
Mba
Mba Mba

Nkọwa
Ụdị ịme anwansị maka IP a na-akwado uru ntinye achọpụtaghị (X) na mgbama ndị a. Mgbe ị na-enye uru X na mgbaama ndị a, a na-agbasa uru X na mgbama mmepụta.
Ntinye data na otutu. Mgbama ntinye [NUMBER_OF_MULTIPLIERS * WIDTH_B – 1 … 0] n'obosara Ụdị simulation maka IP a na-akwado uru ntinye akọwapụtaghị (X) na mgbama ndị a. Mgbe ị na-enye uru X na mgbama ndị a, a na-agbasa uru X na mgbama mmepụta.
Ntinye data na otutu. Mgbama ntinye [NUMBER_OF_MULTIPLIERS * WIDTH_C – 1, … 0] n'obosara Họrọ INPUT maka Họrọ ọnọdụ preadder iji mee ka mgbama ndị a nwee ike. Ụdị ịme anwansị maka IP a na-akwado uru ntinye achọpụtaghị (X) na mgbama ndị a. Mgbe ị na-enye uru X na mgbaama ndị a, a na-agbasa uru X na mgbama mmepụta.
Ọdụ ụgbọ mmiri ntinye elekere na ndebanye aha kwekọrọ. Enwere ike iji akara ngosi a site na ndebanye aha ọ bụla na isi IP. Ụdị ịme anwansị maka IP a na-akwado uru ntinye achọpụtaghị (X) na mgbama ndị a. Mgbe ị na-enye uru X na mgbaama ndị a, a na-agbasa uru X na mgbama mmepụta.
Ntinye doro anya na-ejikọtaghị ọnụ na ndekọ kwekọrọ. Ụdị ịme anwansị maka IP a na-akwado uru ntinye achọpụtaghị (X) na mgbama ndị a. Mgbe ị na-enye uru X na mgbaama ndị a, a na-agbasa uru X na mgbama mmepụta.
Ntinye doro anya gakọrịta na ndekọ kwekọrọ. Ụdị ịme anwansị maka IP a na-akwado uru ntinye X na akara ngosi ndị a ekpebibeghị. Mgbe ị na-enye uru X na mgbaama ndị a, a na-agbasa uru X na mgbama mmepụta
Kwado ntinye mgbaàmà na ndebanye aha kwekọrọ. Ụdị ịme anwansị maka IP a na-akwado uru ntinye achọpụtaghị (X) na mgbama ndị a. Mgbe ị na-enye uru X na mgbama ndị a, a na-agbasa uru X na mgbama mmepụta.
Na-akọwapụta ọnụọgụgụ nke ntinye ihe nrịba ụba A. Ọ bụrụ na akara ngosi dị elu, onye na-emewanye ihe na-emeso ntinye ntinye A dị ka nọmba aka aka. Ọ bụrụ na akara ngosi dị ala, onye na-abawanye ụba na-emeso mgbama ntinye ọtụtụ A dị ka ọnụọgụ na-edeghị aha. Họrọ VARIABLE maka Gịnị bụ usoro nnọchite anya maka ntinye ntinye Multipliers A iji mee ka mgbama a nwee ike. Ụdị ịme anwansị maka IP a na-akwado uru ntinye achọpụtaghị (X) na mgbama a. Mgbe ị na-enye uru X na ntinye a, uru X na-agbasa na mgbama mmepụta.
Na-akọwapụta ọnụọgụgụ nke mgbama ntinye ntinye B. Ọ bụrụ nrịbama akara ahụ dị elu, onye na-ebuwanye ibu na-ewere mgbama ntinye ntinye B dị ukwuu dịka ọnụọgụ mmeju abụọ bịanyere aka na ya. Ọ bụrụ na akara ngosi dị ala, onye na-abawanye ụba na-ewere mgbama ntinye ntinye B dị ukwuu dị ka ọnụọgụ na-edeghị aha. Ụdị ịme anwansị maka IP a na-akwado uru ntinye achọpụtaghị (X) na mgbama a. Mgbe ị nyere uru X na ntinye a, uru X na-agbasa na mgbama mmepụta.
Ntinye maka yinye nyocha A. Mgbama ntinye [WIDTH_A – 1, … 0] obosara. Mgbe paramita INPUT_SOURCE_A nwere uru SCANA, akara ngosi scanina[] chọrọ.
Na-akọwapụta n'ụzọ dị iche iche ma uru mkpokọ na-adị mgbe niile. Ọ bụrụ na akara ngosi accum_sload dị ala, mgbe ahụ, a na-ebuba mmepụta nke ọtụtụ n'ime ihe nchịkọta. Ejila accum_sload na sload_accum n'out oge.
gara n'ihu…

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Signal sload_accum
chainin[] addnsub1
addnsub3
coefsel0[] coefsel1[] coefsel2[] coefsel3[]

Achọrọ Mba
Mba Mba
Mba
Mba Mba Mba Mba

Nkọwa
Ụdị ịme anwansị maka IP a na-akwado uru ntinye achọpụtaghị (X) na mgbama a. Mgbe ị na-enye uru X na ntinye a, uru X na-agbasa na mgbama mmepụta.
Na-akọwapụta n'ụzọ dị iche iche ma uru mkpokọ na-adị mgbe niile. Ọ bụrụ na akara ngosi sload_accum dị elu, mgbe ahụ, a na-ebuba ihe mmepụta ihe n'ime ihe nchịkọta. Ejila accum_sload na sload_accum n'out oge. Ụdị ịme anwansị maka IP a na-akwado uru ntinye achọpụtaghị (X) na mgbama a. Mgbe ị na-enye uru X na ntinye a, uru X na-agbasa na mgbama mmepụta.
bọs ntinye rịzọlt agbakwunyere site na s ndị bu ụzọtage. Mgbama ntinye [WIDTH_CHAININ – 1, … 0] obosara.
Mee mgbakwunye ma ọ bụ mwepu na nsonaazụ sitere na ụzọ abụọ mbụ nke nba ụba. Tinye 1 ka ọ bụrụ akara addnsub1 ka ịtinye mpụta sitere na ụzọ abụọ mbụ nke mmụba. Tinye 0 ka ọ bụrụ akara addnsub1 iji wepụ ihe ndị a sitere na ụzọ abụọ nke ọnụọgụ mbụ. Ụdị ịme anwansị maka IP a na-akwado uru ntinye achọpụtaghị (X) na mgbama a. Mgbe ị nyere uru X na ntinye a, uru X na-agbasa na mgbama mmepụta.
Mee mgbakwunye ma ọ bụ mwepu na nsonaazụ sitere na ụzọ abụọ mbụ nke nba ụba. Tinye 1 ka ọ bụrụ akara addnsub3 ka ịtinye mpụta sitere na ụzọ abụọ nke nbawanye ụba. Tinye 0 na akara addnsub3 iji wepụ ihe arụpụta na ụzọ mbụ nke ọtụtụ ọnụọgụ. Ụdị ịme anwansị maka IP a na-akwado uru ntinye achọpụtaghị (X) na mgbama a. Mgbe ị na-enye uru X na ntinye a, uru X na-agbasa na mgbama mmepụta.
Mgbama ntinye ọnụọgụ ọnụọgụ[0:3] na ọnụọgụ nke mbụ. Ụdị ịme anwansị maka IP a na-akwado uru ntinye achọpụtaghị (X) na mgbama a. Mgbe ị na-enye uru X na ntinye a, uru X na-agbasa na mgbama mmepụta.
Mgbama ntinye ọnụọgụ ọnụọgụ[0:3] na ọnụọgụ nke abụọ. Ụdị ịme anwansị maka IP a na-akwado uru ntinye achọpụtaghị (X) na mgbama a. Mgbe ị nyere uru X na ntinye a, uru X na-agbasa na mgbama mmepụta.
Mgbama ntinye ọnụọgụ ọnụọgụ[0:3] na ọnụọgụ nke atọ. Ụdị ịme anwansị maka IP a na-akwado uru ntinye achọpụtaghị (X) na mgbama a. Mgbe ị nyere uru X na ntinye a, uru X na-agbasa na mgbama mmepụta.
Mgbama ntinye ọnụọgụgụ [0:3] na ọnụọgụ nke anọ. Ụdị ịme anwansị maka IP a na-akwado uru ntinye achọpụtaghị (X) na mgbama a. Mgbe ị nyere uru X na ntinye a, uru X na-agbasa na mgbama mmepụta.

Isiokwu 29. Ọtụtụ Adder Intel FPGA IP ngosi ngosi

Signal

Achọrọ

Nkọwa

nsonaazụ []

Mgbama mmepụta ọtụtụ. Mgbama mmepụta [WIDTH_RESULT – 1 … 0] obosara

Ụdị ịme anwansị maka IP a na-akwado uru mmepụta a na-achọpụtaghị (X). Mgbe ị nyere uru X dị ka ntinye, uru X na-agbasa na mgbama a.

nyocha []

Mba

Mwepụta nke yinye nyocha A. Mgbama mmepụta [WIDTH_A – 1..0] n'obosara.

Họrọ karịa 2 maka ọnụọgụ ọnụọgụ ọnụọgụ wee họrọ ntinye ntinye ntụtụ nyocha maka Gịnị bụ ntinye A nke ọtụtụ ihe ejikọrọ na paramita iji mee ka mgbama a nwee ike.

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8.6. Nkeji

8.6.1. General Tab

Tebụl 30. General Tab

Oke

Parameter emepụtara IP

Uru

Gịnị bụ ọnụ ọgụgụ nke ọtụtụ?

nọmba_of_m 1 - 4 ultipliers

Ogologo obosara ka ụgbọ ala ntinye A width_a kwesịrị ịdị?

1-256

Ogologo ka obosara ụgbọ ala ntinye B width_b kwesịrị ịdị?

1-256

Ogologo ole ka ụgbọ ala mmepụta 'npụtara' kwesịrị ịdị?

width_result

1-256

Mepụta aka elekere metụtara maka elekere ọ bụla

gui_associate Na d_clock_enabl Gbanyụọ e

8.6.2. Ụdị Taabụ Mgbakwunye

Tebụl 31. Mgbakwunye ụdịdị Tab

Oke

Parameter emepụtara IP

Uru

Nhazi mmepụta

Deba aha mmepụta nke otu adder

gui_output_re Gbanye

gister

Gbanyụọ

Kedu isi mmalite ntinye elekere?

gui_output_re gister_clock

Clock0 Clock1 elekere2

Kedu isi mmalite maka ntinye doro anya asynchronous?

gui_output_re gister_aclr

Ọ dịghị onye ACLR0 ACLR1

Kedu isi mmalite maka ntinye doro anya mekọrịtara ọnụ?

gui_output_re gister_sclr

Ọ dịghị onye SCLR0 SCLR1

Adder ọrụ

Kedu ọrụ a ga-arụ na ntinye nke ụzọ abụọ mbụ nke multipliers?

gui_multiplier 1_direction

gbakwunye, SUB, Mgbanwe

Ihe ndabara 1
16

Nkọwa
Ọnụọgụ nke ndị na-ebuwanye ibu a ga-agbakwunye ọnụ. Uru bụ 1 ruo 4. Ezipụta obosara nke ọdụ ụgbọ mmiri dataa[].

Ezipụta obosara nke ọdụ ụgbọ mmiri[].

Ezipụta obosara nke ọdụ ụgbọ mmiri [].

Gbanyụọ

Họrọ nhọrọ a ka ịmepụta aka elekere

maka elekere ọ bụla.

Uru ndabara

Nkọwa

Gbanyụọ elekere0
Ọ dịghị onye

Họrọ nhọrọ a iji mee ka ndebanye aha mmepụta nke modul adder.
Họrọ Clock0, Clock1 ma ọ bụ Clock2 iji mee ka ma kọwaa isi mmalite elekere maka ndekọ mmepụta. Ị ga-ahọrọ aha mmepụta nke adder unit iji mee ka oke a nwee ike.
Na-akọwapụta isi mmalite doro anya asynchronous maka ndekọ mmepụta adder. Ị ga-ahọrọ aha mmepụta nke adder unit iji mee ka oke a nwee ike.
Na-akọwapụta isi mmalite doro anya maka ndekọ mmepụta ihe nkwụnye. Ị ga-ahọrọ aha mmepụta nke adder unit iji mee ka oke a nwee ike.

gbakwunye

Họrọ ọrụ mgbakwunye ma ọ bụ mwepu iji rụpụta nsonaazụ n'etiti ọnụọgụ nke mbụ na nke abụọ.
Họrọ ADD ka ịrụ ọrụ mgbakwunye.
Họrọ SUB ka ịrụ ọrụ mwepu.
Họrọ VARIABLE ka ijiri ọdụ ụgbọ mmiri addnsub1 maka njikwa mgbakwunye na mwepu ike.
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Oke

Parameter emepụtara IP

Uru

Deba aha ntinye 'adnsub1'

gui_addnsub_ Na multiplier_reg Gbanyụọ ister1

Kedu isi mmalite ntinye elekere?

gui_addnsub_ multiplier_reg ister1_clock

Clock0 Clock1 elekere2

Kedu isi mmalite maka ntinye doro anya asynchronous?

gui_addnsub_ multiplier_aclr 1

Ọ dịghị onye ACLR0 ACLR1

Kedu isi mmalite maka ntinye doro anya mekọrịtara ọnụ?

gui_addnsub_ multiplier_sclr 1

Ọ dịghị onye SCLR0 SCLR1

Kedu ọrụ a ga-arụ na ntinye nke ụzọ abụọ nke multipliers?

gui_multiplier 3_direction

gbakwunye, SUB, Mgbanwe

Deba aha ntinye 'adnsub3'

gui_addnsub_ Na multiplier_reg Gbanyụọ ister3

Kedu isi mmalite ntinye elekere?

gui_addnsub_ multiplier_reg ister3_clock

Clock0 Clock1 elekere2

Uru ndabara
Gbanyụọ Clock0 Ọ DỊGHỊ onye gbakwunyere
Gbanyụọ elekere0

Nkọwa
Mgbe ahọpụtara uru VARIABLE: · Gbanwee akara addnsub1 ka ọ dị elu maka
mgbakwunye ọrụ. · Gbanwee akara addnsub1 ka ọ dị ala maka
ọrụ mwepu. Ị ga-ahọrọ ihe karịrị ọnụọgụ abụọ iji mee ka oke a nwee ike.
Họrọ nhọrọ a iji mee ka ndenye ntinye aha maka ọdụ ụgbọ mmiri addnsub1. Ị ga-ahọrọ VARIABLE maka Kedu ọrụ a ga-arụ na ntinye nke ụzọ abụọ nke ọnụọgụ mbụ iji mee ka oke a nwee ike.
Họrọ Clock0, Clock1 ma ọ bụ Clock2 iji kọwaa mgbaama elekere ntinye maka ndebanye aha addnsub1. Ị ga-ahọrọ ntinye 'addnsub1' deba aha iji mee ka oke a nwee ike.
Na-akọwapụta isi mmalite doro anya asynchronous maka ndebanye aha addnsub1. Ị ga-ahọrọ ntinye 'addnsub1' deba aha iji mee ka oke a nwee ike.
Na-akọwapụta isi mmalite doro anya maka ndebanye aha addnsub1. Ị ga-ahọrọ ntinye 'addnsub1' deba aha iji mee ka oke a nwee ike.
Họrọ ọrụ mgbakwunye ma ọ bụ mwepu iji rụpụta nsonaazụ n'etiti ọnụọgụ nke atọ na nke anọ. Họrọ ADD ka ịrụ mgbakwunye
ọrụ. Họrọ SUB ka ịrụ mwepu
ọrụ. Họrọ VARIABLE ka iji addnsub1
ọdụ ụgbọ mmiri maka njikwa mgbakwunye/mwepu ike. Mgbe ahọpụtara uru VARIABLE: · Gbanwee akara addnsub1 na elu maka ọrụ mgbakwunye. * Gbaa akara addnsub1 gaa ala maka ọrụ mwepu. Ị ga-ahọrọ uru 4 maka Gịnị bụ ọnụ ọgụgụ nke multipliers? iji mee ka oke a nwee ike.
Họrọ nhọrọ a iji mee ka ndenye ntinye aka maka akara addnsub3. Ị ga-ahọrọ VARIABLE maka Kedu ọrụ a ga-arụ na ntinye nke abụọ nke ọnụọgụ abụọ iji mee ka oke a nwee ike.
Họrọ Clock0, Clock1 ma ọ bụ Clock2 iji kọwaa mgbaama elekere ntinye maka ndebanye aha addnsub3. Ị ga-ahọrọ ntinye 'adnsub3' deba aha iji mee ka oke a nwee ike.
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Oke
Kedu isi mmalite maka ntinye doro anya asynchronous?

Parameter emepụtara IP

Uru

gui_addnsub_ multiplier_aclr 3

Ọ dịghị onye ACLR0 ACLR1

Kedu isi mmalite maka ntinye doro anya mekọrịtara ọnụ?

gui_addnsub_ multiplier_sclr 3

Ọ dịghị onye SCLR0 SCLR1

Kwado 'use_subadd'

gui_use_sub Na

tinye

Gbanyụọ

8.6.3. Multipliers Tab

Isiokwu 32. Multipliers Tab

Oke

Parameter emepụtara IP

Uru

Gịnị bụ

gui_anọchi anya

usoro nnọchite anya ation_a

maka ntinye Multipliers A?

mbinye aka, enweghị aha, mgbanwe

Deba aha ntinye 'signa'

gui_register_s Gbanwuo

igna

Gbanyụọ

Kedu isi mmalite ntinye elekere?

gui_register_s igna_clock

Clock0 Clock1 elekere2

Kedu isi mmalite maka ntinye doro anya asynchronous?

gui_register_s igna_aclr

Ọ dịghị onye ACLR0 ACLR1

Kedu isi mmalite maka ntinye doro anya mekọrịtara ọnụ?

gui_register_s igna_sclr

Ọ dịghị onye SCLR0 SCLR1

Gịnị bụ

gui_anọchi anya

usoro nnọchite anya ation_b

maka ntinye Multipliers B?

mbinye aka, enweghị aha, mgbanwe

Deba aha ntinye 'signb'

gui_register_s Gbanwuo

ignb

Gbanyụọ

Uru ndabara Ọ BỤGHỊ
Ọ DỊGHỊ

Nkọwa
Na-akọwapụta isi mmalite doro anya asynchronous maka ndebanye aha addnsub3. Ị ga-ahọrọ ntinye 'addnsub3' deba aha iji mee ka oke a nwee ike.
Na-akọwapụta isi mmalite doro anya maka ndekọ addnsub3. Ị ga-ahọrọ ntinye 'adnsub3' deba aha iji mee ka oke a nwee ike.

Gbanyụọ

Họrọ nhọrọ a iji tụgharịa ọrụ ahụ

nke ọdụ ụgbọ mmiri addnsub.

Gbanye addnsub n'elu maka ọrụ mwepu.

Gbanye addnsub ka ọ dị ala maka ọrụ mgbakwunye.

Uru ndabara

Nkọwa

Edebanyeghị aha Ezipụta usoro nnọchite anya maka ntinye ọtụtụ A.

Gbanyụọ

Họrọ nhọrọ a iji mee ka akara aka

debanye aha.

Ị ga-ahọrọ uru VARIABLE maka Gịnị bụ usoro nnọchite anya maka ntinye Multipliers A? oke iji mee nhọrọ a.

Elekere0

Họrọ Clock0 , Clock1 ma ọ bụ Clock2 iji mee ka ma kọwaa mgbama elekere ntinye maka ndebanye aha.
Ị ga-ahọrọ ntinye 'signa' aha iji mee ka oke a nwee ike.

Ọ DỊGHỊ

Na-akọwapụta isi mmalite doro anya asynchronous maka ndekọ akara.
Ị ga-ahọrọ ntinye 'signa' aha iji mee ka oke a nwee ike.

Ọ DỊGHỊ

Na-akọwapụta isi mmalite doro anya maka ndebanye aha.
Ị ga-ahọrọ ntinye 'signa' aha iji mee ka oke a nwee ike.

Edebanyeghị aha Ezipụta usoro nnọchite anya maka ntinye ọtụtụ B.

Gbanyụọ

Họrọ nhọrọ a iji mee ka signb nwee ike

debanye aha.

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Oke

Parameter emepụtara IP

Uru

Uru ndabara

Kedu isi mmalite ntinye elekere?

gui_register_s ignb_clock

Clock0 Clock1 elekere2

Elekere0

Kedu isi mmalite maka ntinye doro anya asynchronous?

gui_register_s ignb_aclr

Ọ dịghị onye ACLR0 ACLR1

Kedu isi mmalite maka ntinye doro anya mekọrịtara ọnụ?

gui_register_s ignb_sclr

Ọ dịghị onye SCLR0 SCLR1

Nhazi ntinye
Deba aha ntinye A nke nba ụba
Kedu isi mmalite ntinye elekere?

gui_input_reg Gbanụrụ

ister_a

Gbanyụọ

gui_input_reg ister_a_clock

Clock0 Clock1 elekere2

Ọ dịghị onye
Gbanyụọ elekere0

Kedu isi mmalite maka ntinye doro anya asynchronous?

gui_input_reg ister_a_aclr

Ọ dịghị onye ACLR0 ACLR1

Kedu isi mmalite maka ntinye doro anya mekọrịtara ọnụ?

gui_input_reg ister_a_sclr

Ọ dịghị onye SCLR0 SCLR1

Deba aha ntinye B nke nbawanye ụba
Kedu isi mmalite ntinye elekere?

gui_input_reg Gbanụrụ

ister_b

Gbanyụọ

gui_input_reg ister_b_clock

Clock0 Clock1 elekere2

Ọ BỤGHỊ Ọ BỤGHỊ N'EGO 0

Kedu isi mmalite maka ntinye doro anya asynchronous?

gui_input_reg ister_b_aclr

Ọ dịghị onye ACLR0 ACLR1

Ọ DỊGHỊ

Kedu isi mmalite maka ntinye doro anya mekọrịtara ọnụ?

gui_input_reg ister_b_sclr

Ọ dịghị onye SCLR0 SCLR1

Ọ DỊGHỊ

Kedu ihe ntinye A nke ọtụtụ ihe ejikọrọ?

gui_multiplier Multiplier ntinye Multiplier

_ntinye

Nyochaa ntinye ntinye yinye

Nkọwa
Ị ga-ahọrọ uru VARIABLE maka Gịnị bụ usoro nnọchite anya maka ntinye Multipliers B? oke iji mee nhọrọ a.
Họrọ Clock0, Clock1 ma ọ bụ Clock2 iji mee ma kọwaa mgbama elekere ntinye maka ndebanye aha. Ị ga-ahọrọ ntinye 'signb' aha iji mee ka oke a nwee ike.
Na-akọwapụta isi mmalite doro anya maka ndebanye aha. Ị ga-ahọrọ ntinye 'signb' aha iji mee ka oke a nwee ike.
Na-akọwapụta isi mmalite doro anya maka ndebanye aha. Ị ga-ahọrọ ntinye 'signb' aha iji mee ka oke a nwee ike.
Họrọ nhọrọ a iji mee ka ndenye ntinye aha maka ụgbọ ala ntinye data.
Họrọ Clock0 , Clock1 ma ọ bụ Clock2 iji mee ma kọwaa akara elekere ndenye aha maka ụgbọ ala ntinye data. Ị ga-ahọrọ ndenye ndenye A nke ọtụtụ ihe ka ị nwee ike mee oke a.
Na-akọwapụta isi mmalite doro anya na-enweghị atụ maka ụgbọ ala ntinye data. Ị ga-ahọrọ ndenye ndenye A nke ọtụtụ ihe ka ị nwee ike mee oke a.
Na-akọwapụta isi mmalite doro anya mekọrịtara ọnụ maka ụgbọ ala ntinye data. Ị ga-ahọrọ ndenye ndenye A nke njupụta ka ị nwee ike mee oke a.
Họrọ nhọrọ a iji mee ka ndenye ntinye aha maka ụgbọ ala ntinye datab.
Họrọ Clock0, Clock1 ma ọ bụ Clock2 iji mee ma kọwaa akara elekere ndenye aha maka ụgbọ ala ntinye data. Ị ga-ahọrọ Deba aha ndenye B nke onye na-ebuwanye ibu iji mee ka oke a nwee ike.
Na-akọwapụta isi mmalite doro anya na-ejikọtaghị ọnụ maka ụgbọ ala ntinye datab. Ị ga-ahọrọ Deba aha ndenye B nke onye na-ebuwanye ibu iji mee ka oke a nwee ike.
Na-akọwapụta isi mmalite doro anya mekọrịtara ọnụ maka bọs ntinye datab. Ị ga-ahọrọ Deba aha ndenye B nke onye na-ebuwanye ibu iji mee ka oke a nwee ike.
Họrọ isi iyi ntinye maka ntinye A nke ọtụtụ.
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Oke

Parameter emepụtara IP

Uru

Nyochaa nhazi ndekọ aha

Deba aha mmepụta nke yinye nyocha

gui_scanouta Gbanyụọ

_debanye aha

Gbanyụọ

Kedu isi mmalite ntinye elekere?

gui_scanouta _register_clock k

Clock0 Clock1 elekere2

Kedu isi mmalite maka ntinye doro anya asynchronous?

gui_scanouta _register_aclr

Ọ dịghị onye ACLR0 ACLR1

Kedu isi mmalite maka ntinye doro anya mekọrịtara ọnụ?

gui_scanouta _register_sclr

Ọ dịghị onye SCLR0 SCLR1

8.6.4. Preadder Tab

Isiokwu 33. Preadder Tab

Oke

Parameter emepụtara IP

Uru

Họrọ ụdị predder

preadder_mo de

MFE, COEF, INPUT, SQUARE, na-adị mgbe niile

Uru ndabara

Nkọwa
Họrọ ndenye ọtụtụ ka iji bọs ntinye data dị ka isi iyi na-abawanye ụba. Họrọ ndenye nyocha nke yinye ka iji bọs ntinye scanin dị ka isi mmalite na-abawanye ma mee ka bọs mmepụta ihe nyocha. Nke a oke dị mgbe ị họrọ 2, 3 ma ọ bụ 4 maka Gịnị bụ ọnụ ọgụgụ nke multipliers? oke.

Gbanyụọ elekere0 Ọ BỤGHỊ

Họrọ nhọrọ a iji mee ka ndebanye aha mmepụta maka ụgbọ ala mmepụta scanouta.
Ị ga-ahọrọ ntinye ntụtụ nyocha maka Gịnị bụ ntinye A nke ọtụtụ ihe ejikọrọ? oke iji mee nhọrọ a.
Họrọ Clock0, Clock1 ma ọ bụ Clock2 iji mee ma kọwaa akara elekere ndenye aha maka ụgbọ ala mmepụta scanouta.
Ị ga-agbanyerịrị mmepụta ndebanye aha nke paramita ihe nrịbama nyocha iji mee nhọrọ a.
Na-akọwapụta aha ndekọ aha asynchronous doro anya maka ụgbọ ala mmepụta scanouta.
Ị ga-agbanyerịrị mmepụta ndebanye aha nke paramita ihe nrịbama nyocha iji mee nhọrọ a.
Na-akọwapụta isi mmalite doro anya na-emekọrịta ọnụ maka ụgbọ ala mmepụta scanouta.
Ị ga-ahọrọ Deba aha mmepụta nke nyocha yinye oke iji mee nhọrọ a.

Uru ndabara
MFE

Nkọwa
Na-akọwapụta ọnọdụ ọrụ maka modul preadder. MFE MMADỤ: Ọnọdụ a gafere ihe nrịbama ụzọ. Nke a bụ ọnọdụ ndabara. COEF: Ụdị a na-eji mmepụta nke preadder na coefsel ntinye ụgbọ ala dị ka ntinye na ụba. INPUT: Ụdị a na-eji mmepụta nke preadder na ụgbọ ala ntinye datac dị ka ntinye aka na ụba. SQUARE: Ụdị a na-eji mmepụta nke preadder dị ka ma ntinye na ụba.
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Oke

Parameter emepụtara IP

Uru

Họrọ ntụzịaka ntụzịaka

gui_reader tinye,

_nduzi

SUB

Ogologo ụgbọ ala ntinye C width_c kwesịrị ịdị?

1-256

Nhazi ndekọ ntinye data C

Deba aha ntinye datac

gui_datac_inp Gbanwuo

ut_debanye aha

Gbanyụọ

Kedu isi mmalite ntinye elekere?

gui_datac_inp ut_register_cl ock

Clock0 Clock1 elekere2

Kedu isi mmalite maka ntinye doro anya asynchronous?

gui_datac_inp ut_register_a clr

Ọ dịghị onye ACLR0 ACLR1

Kedu isi mmalite maka ntinye doro anya mekọrịtara ọnụ?

gui_datac_inp ut_register_sc lr

Ọ dịghị onye SCLR0 SCLR1

Ọnụọgụ ọnụ
Olee otú obosara kwesịrị ịdị obosara coef?

obosara_coef

1-27

Nhazi ndekọ aha Coef

Deba aha ndenye coefsel

gui_coef_regi Gbanyụọ

ster

Gbanyụọ

Kedu isi mmalite ntinye elekere?

gui_coef_regi ster_clock

Clock0 Clock1 elekere2

Uru ndabara
gbakwunye
16

Nkọwa
AKWỤKWỌ: Ụdị a na-eji ụgbọ ala ntinye dataa nwere preadder gafere na bọs ntinye coefsel dị ka ntinye na ụbara.
Na-akọwapụta ọrụ nke predder. Iji mee nke a oke, họrọ ihe ndị a maka Họrọ preadder mode: · COEF · INPUT · SQUARE ma ọ bụ · CONSTANT.
Na-akọwapụta ọnụọgụ nke bits maka ụgbọ ala ntinye C. Ị ga-ahọrọ INPUT maka Họrọ preadder mode iji mee ka oke a nwee ike.

Na Clock0 Ọ BỤGHỊ

Họrọ nhọrọ a iji mee ka ndenye ntinye aha maka ụgbọ ala ntinye datac. Ị ga-edobe INPUT ka ị họrọ paramita ọnọdụ preadder iji mee nhọrọ a.
Họrọ Clock0, Clock1 ma ọ bụ Clock2 iji kọwapụta mgbaama elekere ntinye maka ndekọ ntinye datac. Ị ga-ahọrọ ntinye datac deba aha iji mee ka oke a nwee ike.
Na-akọwapụta isi mmalite doro anya asynchronous maka ndekọ ntinye datac. Ị ga-ahọrọ ntinye datac deba aha iji mee ka oke a nwee ike.
Na-akọwapụta isi mmalite doro anya na-emekọrịta ihe maka ndekọ ntinye datac. Ị ga-ahọrọ ntinye datac deba aha iji mee ka oke a nwee ike.

Na-akọwapụta ọnụọgụ nke ibe n'ibe maka

ụgbọ ala ntinye coefsel.

Ị ga-ahọrọ COEF ma ọ bụ CONSTANT maka ọnọdụ preadder iji mee ka oke a nwee ike.

Na elekere 0

Họrọ nhọrọ a iji mee ka ndenye ntinye aha maka ụgbọ ala ntinye coefsel. Ị ga-ahọrọ COEF ma ọ bụ CONSTANT maka ọnọdụ preadder iji mee ka oke a nwee ike.
Họrọ Clock0, Clock1 ma ọ bụ Clock2 iji kọwapụta mgbaama elekere ntinye maka ndenye ntinye coefsel. Ị ga-ahọrọ Deba aha ndenye coefsel iji mee ka oke a nwee ike.
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Ntuziaka onye ọrụ Intel FPGA Integer Arithmetic IP Cores 52

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Oke
Kedu isi mmalite maka ntinye doro anya asynchronous?

Parameter emepụtara IP

Uru

gui_coef_regi ster_aclr

Ọ dịghị onye ACLR0 ACLR1

Kedu isi mmalite maka ntinye doro anya gakọrịtara ọnụ

gui_coef_regi ster_sclr

Ọ dịghị onye SCLR0 SCLR1

Nhazi Coefficient_0

coef0_0 ruo coef0_7

0x00000 0xFFFFFF

Nhazi Coefficient_1

coef1_0 ruo coef1_7

0x00000 0xFFFFFF

Nhazi Coefficient_2

coef2_0 ruo coef2_7

0x00000 0xFFFFFF

Nhazi Coefficient_3

coef3_0 ruo coef3_7

0x00000 0xFFFFFF

8.6.5. Accumulator Tab

Isiokwu 34. Accumulator Tab

Oke

Parameter emepụtara IP

Uru

Kwado akwakọba?

accumulator

EE, ee e

Gịnị bụ accumulator ụdị ọrụ?

accum_directi ADD,

SUB

Uru ndabara Ọ BỤGHỊ
Ọ DỊGHỊ
0 x0000000
0 x0000000
0 x0000000
0 x0000000

Nkọwa
Na-akọwapụta isi mmalite doro anya maka ndenye ntinye coefsel. Ị ga-ahọrọ Deba aha ndenye coefsel iji mee ka oke a nwee ike.
Na-akọwapụta isi mmalite doro anya maka ndekọ ntinye coefsel. Ị ga-ahọrọ Deba aha ndenye coefsel iji mee ka oke a nwee ike.
Na-akọwapụta ọnụọgụ ọnụọgụgụ maka ọnụọgụ mbụ a. Ọnụọgụ nke ibe n'ibe ga-abụ otu ka akọwapụtara n'ime Kedu ka obosara coef kwesịrị ịdị? oke. Ị ga-ahọrọ COEF ma ọ bụ CONSTANT maka ọnọdụ preadder iji mee ka oke a nwee ike.
Na-akọwapụta ọnụọgụ ọnụọgụgụ maka ọnụọgụ nke abụọ a. Ọnụọgụ nke ibe n'ibe ga-abụ otu ka akọwapụtara n'ime Kedu ka obosara coef kwesịrị ịdị? oke. Ị ga-ahọrọ COEF ma ọ bụ CONSTANT maka ọnọdụ preadder iji mee ka oke a nwee ike.
Na-akọwapụta ọnụọgụ ọnụọgụgụ maka ọnụọgụ nke atọ a. Ọnụọgụ nke ibe n'ibe ga-abụ otu ka akọwapụtara n'ime Kedu ka obosara coef kwesịrị ịdị? oke. Ị ga-ahọrọ COEF ma ọ bụ CONSTANT maka ọnọdụ preadder iji mee ka oke a nwee ike.
Na-akọwapụta ọnụọgụ ọnụọgụgụ maka ọnụọgụ nke anọ a. Ọnụọgụ nke ibe n'ibe ga-abụ otu ka akọwapụtara n'ime Kedu ka obosara coef kwesịrị ịdị? oke. Ị ga-ahọrọ COEF ma ọ bụ CONSTANT maka ọnọdụ preadder iji mee ka oke a nwee ike.

Uru ndabara NO
gbakwunye

Nkọwa
Họrọ EE iji mee ka mkpokọta. Ị ga-ahọrọ Deba aha mmepụta nke adder unit mgbe ị na-eji atụmatụ accumulator.
Na-akọwapụta ọrụ nke mkpokọ: · ADD maka ọrụ mgbakwunye · SUB maka ọrụ mwepu. Ị ga-ahọrọ EE maka Kwado akwakọba? oke iji mee nhọrọ a.
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Oke
Bugharịa mgbe niile Kwado ibubu mgbe niile

Parameter emepụtara IP

Uru

gui_ena_prelo Na

ad_const

Gbanyụọ

Gịnị bụ ntinye nke mkpokọta ọdụ ụgbọ mmiri ejikọrọ?

gui_accumula ACCUM_SLOAD, te_port_select SLOAD_ACCUM

Họrọ uru maka ebugo ibu loadconst_val 0 – 64

na-adịgide adịgide

Kedu isi mmalite ntinye elekere?

gui_accum_sl oad_register_ elekere

Clock0 Clock1 elekere2

Kedu isi mmalite maka ntinye doro anya asynchronous?

gui_accum_sl oad_register_ aclr

Ọ dịghị onye ACLR0 ACLR1

Kedu isi mmalite maka ntinye doro anya mekọrịtara ọnụ?

gui_accum_sl oad_register_ sclr

Ọ dịghị onye SCLR0 SCLR1

Kwado akwakọba okpukpu abụọ

gui_double_a Na

kpom

Gbanyụọ

Uru ndabara

Nkọwa

Gbanyụọ

Kwado accum_sload ma ọ bụ

sload_accum akara na ndenye aha

ka dynamically họrọ ntinye na

onye nchịkọta.

Mgbe accum_sload dị ala ma ọ bụ sload_accum, a na-eri nri na-abawanye ụba n'ime ihe nchịkọta.

Mgbe accum_sload dị elu ma ọ bụ sload_accum, onye ọrụ akọwapụtara preload mgbe niile na-enye nri n'ime mkpọkọta.

Ị ga-ahọrọ EE maka Kwado akwakọba? oke iji mee nhọrọ a.

ACCUM_SL OAD

Na-akọwapụta omume nke mgbama accum_sload/sload_accum.
ACCUM_SLOAD: Ụgbọala accum_sload dị ala ka ọ buru mmepụta ihe nrịbawanye n'ime igwe.
SLOAD_ACCUM: Ụgbọala sload_accum dị elu ka ọ na-ebupụta mmepụta ihe na-ebuwanye ibu na onye nchịkọta.
Ị ga-ahọrọ Kwado mbugoro nhọrọ mgbe niile iji mee ka oke a nwee ike.

Ezipụta uru atọrọ mgbe niile.

Uru a nwere ike ịbụ 2N ebe N bụ uru nke atọrọ mgbe niile.

Mgbe N=64, ọ na-anọchi anya efu mgbe niile.

Ị ga-ahọrọ Kwado mbugoro nhọrọ mgbe niile iji mee ka oke a nwee ike.

Elekere0

Họrọ Clock0, Clock1 ma ọ bụ Clock2 iji kọwapụta akara elekere ntinye maka ndekọ ndekọ accum_sload/sload_accum.
Ị ga-ahọrọ Kwado mbugoro nhọrọ mgbe niile iji mee ka oke a nwee ike.

Ọ DỊGHỊ

Na-akọwapụta isi mmalite doro anya asynchronous maka ndekọ aha accum_sload/sload_accum.
Ị ga-ahọrọ Kwado mbugoro nhọrọ mgbe niile iji mee ka oke a nwee ike.

Ọ DỊGHỊ

Na-akọwapụta isi mmalite doro anya maka ndekọ aha accum_sload/sload_accum.
Ị ga-ahọrọ Kwado mbugoro nhọrọ mgbe niile iji mee ka oke a nwee ike.

Gbanyụọ

Na-eme ka ndekọ mkpọkọta okpukpu abụọ.

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8.6.6. Systolic/Chainout Tab

Tebụl 35. Systolic/Chainout Adder Tab

Parameter Kwado chainout adder

Parameter emepụtara IP

Uru

chainout_gbakwunye EE,

Mba

Kedu ihe bụ ụdị ọrụ chainout adder?

chainout_gbakwunye ADD,

er_direction

SUB

Kwado ntinye 'negate' maka chainout adder?

Port_negate

PORT_USED, PORT_UNUSED

Deba aha ntinye 'negate'? negate_regist er

Edebanyeghị aha, CLOCK0, CLOCK1, CLOCK2, CLOCK3

Kedu isi mmalite maka ntinye doro anya asynchronous?

negate_aclr

Ọ dịghị onye ACLR0 ACLR1

Kedu isi mmalite maka ntinye doro anya mekọrịtara ọnụ?

negate_sclr

Ọ dịghị onye SCLR0 SCLR1

Ọnwụ systolic
Kwado ndekọ igbu oge systolic

gui_systolic_d Gbanyụọ

lee

Gbanyụọ

Kedu isi mmalite ntinye elekere?

gui_systolic_d CLOCK0,

elay_clock

EGO 1,

Uru ndabara
Mba

Nkọwa
Họrọ EE iji mee ka modul chainout adder nwee ike.

gbakwunye

Na-akọwapụta ọrụ chainout adder.
Maka ọrụ mwepu, a ga-ahọpụtarịrị SIGNED maka Gịnị bụ usoro nnọchite anya maka ntinye Multipliers A? na Gịnị bụ usoro nnọchite anya maka ntinye Multipliers B? na Multipliers Tab.

PORT_UN ji

Họrọ PORT_USED iji mee ka mgbama ntinye negate.
Nke a na-adịghị mma mgbe chainout adder nwere nkwarụ.

Edebanyela aha aha

Iji mee ka ndenye ntinye aha maka mgbama ntinye negate ma kọwaa akara elekere ntinye maka ndebanye aha negate.
Họrọ UN REGISTERED ma ọ bụrụ na aha ndenye negate na-adịghị mkpa
Oke a abaghị uru mgbe ịhọrọ:
Ọ dịghị maka Kwado chainout adder ma ọ bụ
PORT_UNUSED maka Kwado ntinye 'negate' maka chainout adder? paramita ma ọ bụ

Ọ DỊGHỊ

Na-akọwapụta isi mmalite doro anya asynchronous maka ndebanye aha negate.
Oke a abaghị uru mgbe ịhọrọ:
Ọ dịghị maka Kwado chainout adder ma ọ bụ
PORT_UNUSED maka Kwado ntinye 'negate' maka chainout adder? paramita ma ọ bụ

Ọ DỊGHỊ

Na-akọwapụta isi mmalite doro anya maka ndebanye aha negate.
Oke a abaghị uru mgbe ịhọrọ:
Ọ dịghị maka Kwado chainout adder ma ọ bụ
PORT_UNUSED maka Kwado ntinye 'negate' maka chainout adder? paramita ma ọ bụ

Gbanyụọ CLOCK0

Họrọ nhọrọ a iji mee ka ọnọdụ systolic nwee ike. Nke a oke dị mgbe ị họrọ 2, ma ọ bụ 4 maka Gịnị bụ ọnụ ọgụgụ nke multipliers? oke. Ị ga-emerịrị ka mmepụta Ndebanye aha nke unit adder jiri ndekọ igbu oge systolic.
Na-akọwapụta mgbama elekere ntinye maka ndekọ igbu oge systolic.
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Oke

Parameter emepụtara IP

Uru

EGO 2,

Kedu isi mmalite maka ntinye doro anya asynchronous?

gui_systolic_d elay_aclr

Ọ dịghị onye ACLR0 ACLR1

Kedu isi mmalite maka ntinye doro anya mekọrịtara ọnụ?

gui_systolic_d elay_sclr

Ọ dịghị onye SCLR0 SCLR1

Uru ndabara
Ọ DỊGHỊ
Ọ DỊGHỊ

Nkọwa
Ị ga-ahọrọ mee ka ndekọ igbu oge systolic iji mee nhọrọ a.
Na-akọwapụta isi mmalite doro anya asynchronous maka ndekọ igbu oge systolic. Ị ga-ahọrọ mee ka ndekọ igbu oge systolic iji mee nhọrọ a.
Na-akọwapụta isi mmalite doro anya maka ndekọ igbu oge systolic. Ị ga-ahọrọ mee ka ndekọ igbu oge systolic iji mee nhọrọ a.

8.6.7. Taabụ ọkpọkọ

Isiokwu 36. Pipelining Tab

Nhazi pipelining parameter

Parameter emepụtara IP

Uru

Ịchọrọ ịgbakwunye ndekọ pipeline na ntinye?

gui_pipelining Mba, Ee

Uru ndabara
Mba

Biko kọwaa ya

latency

ọnụ ọgụgụ nke latency elekere

okirikiri

Uru ọ bụla karịrị 0 karịa 0

Kedu isi mmalite ntinye elekere?

gui_input_late ncy_clock

CLOCK0, CLOCK1, CLOCK2

Kedu isi mmalite maka ntinye doro anya asynchronous?

gui_input_late ncy_aclr

Ọ dịghị onye ACLR0 ACLR1

Kedu isi mmalite maka ntinye doro anya mekọrịtara ọnụ?

gui_input_late ncy_sclr

Ọ dịghị onye SCLR0 SCLR1

CLOCK0 Ọ BỤGHỊ

Nkọwa
Họrọ E-eh iji mee ka ọkwa ọzọ nke ndekọ pipeline dị na akara ntinye. Ị ga-ezipụta uru karịrị 0 maka Biko kọwaa ọnụọgụgụ nke usoro elekere latency.
Na-akọwapụta latency achọrọ na okirikiri elekere. Otu ọkwa nke ndekọ pipeline = 1 latency na okirikiri elekere. Ị ga-ahọrọ EE maka Ịchọrọ ịgbakwunye ndekọ pipeline na ntinye? iji mee ka nhọrọ a nwee ike.
Họrọ Clock0, Clock1 ma ọ bụ Clock2 iji mee ma kọwaa mgbama elekere ndenye pipeline. Ị ga-ahọrọ EE maka Ịchọrọ ịgbakwunye ndekọ pipeline na ntinye? iji mee ka nhọrọ a nwee ike.
Na-akọwapụta aha ndekọ aha asynchronous doro anya maka ndebanye aha pipeline agbakwunyere. Ị ga-ahọrọ EE maka Ịchọrọ ịgbakwunye ndekọ pipeline na ntinye? iji mee ka nhọrọ a nwee ike.
Na-akọwapụta isi mmalite doro anya na-emekọrịta ọnụ maka ndekọ pipeline agbakwunyere. Ị ga-ahọrọ EE maka Ịchọrọ ịgbakwunye ndekọ pipeline na ntinye? iji mee ka nhọrọ a nwee ike.

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9. ALTMEMMULT (Memory based Constant Coefficient Multiplier) IP Core

Nlebara anya:

Intel ewepụla nkwado nke IP a na Intel Quartus Prime Pro Edition 20.3. Ọ bụrụ na isi IP dị n'ime ime gị lekwasịrị anya ngwaọrụ dị na Intel Quartus Prime Pro Edition, ị nwere ike dochie IP na LPM_MULT Intel FPGA IP ma ọ bụ megharịa IP wee chịkọta imewe gị site na iji Intel Quartus Prime Standard Edition software.

A na-eji ALTMEMMULT IP isi mepụta ọtụtụ ndị dabere na ebe nchekwa site na iji blocks ebe nchekwa onchip achọtara na Intel FPGA (ya na M512, M4K, M9K, na MLAB ebe nchekwa). Isi IP a bara uru ma ọ bụrụ na ịnweghị ego zuru oke iji mejuputa ọtụtụ ihe na ihe mgbagha (LEs) ma ọ bụ ihe onwunwe ọtụtụ raara onwe ya nye.
AlTMEMMULT IP isi bụ ọrụ mmekọrịta nke chọrọ elekere. ALTMEMMULT IP core na-emejuputa ihe ngbasawanye nke nwere ntinye kacha nta na latency enwere ike maka otu nkeji na nkọwapụta.
Ọnụọgụ na-esonụ na-egosi ọdụ ụgbọ mmiri maka ALTMEMMULT IP isi.

Ọgụgụ 21. Ọdụ ụgbọ mmiri ALTMEMMULT

ALTMEMMULT

data_in[] sload_data coeff_in[]

Nsonaazụ[] results_valid load_done

sload_coeff

sclr elekere
inst

Atụmatụ ozi emetụtara na ibe 71

9.1. Atụmatụ
AlTMEMMULT IP core na-enye atụmatụ ndị a: · Na-emepụta sọọsọ ịgbasa ebe nchekwa site na iji blocks memory on-chip hụrụ na ya.
Intel FPGAs · Na-akwado obosara data nke 1 bits · Na-akwado usoro nnọchite anya data abịanyere aka na nke enweghị mbinye aka · Na-akwado pipelin site na iji latency arụpụtara arụ ọrụ.

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9. ALTMEMMULT (Memory dabeere na Constant Coefficient Multiplier) IP Core 683490 | 2020.10.05
* Na-echekwa ọnụọgụ ọnụọgụ na ebe nchekwa ohere ohere (RAM)
· Na-enye nhọrọ ịhọrọ ụdị ngọngọ RAM
Na-akwado ọdụ ụgbọ mmiri ntinye doro anya yana njikwa ibu gakọrịta nhọrọ
9.2. Prototype Verilog HDL
Ụdị Verilog HDL ndị a dị na Verilog Design File (.v) altera_mf.v na eda ndekọ ndekọ.
modul altmemmult #(parameter coeff_representation = "SIGNED", parameter coefficient0 = "UNUSED", parameter data_representation = "SIGNED", parameter decide_device_family = "ejighi ya", parameter max_clock_cycles_per_result = 1, parameter number_of_coffice " AU_type , parameter number_of_coffice " parameter total_latency = 1, paramita width_c = 1, paramita width_d = 1, paramita width_r = 1, parameter width_s = 1, parameter lpm_type = "altmemmult", parameter lpm_hint = "ejighi ya") (elekere waya ntinye, waya ntinye [obosara_c-1) :1]coeff_in, waya ntinye [width_d-0:1] data_in, mmepụta waya load_done, waya mmepụta [width_r-0: 1] nsonaazụ, mmepụta waya result_valid, ntinye waya sclr, ntinye waya [width_s-0:1] sel, ntinye waya sload_coeff, ntinye waya sload_data)/* njikọ syn_black_box=0 */; endmodule
9.3. Nkwupụta akụkụ VHDL
Nkwupụta akụrụngwa VHDL dị na Nhazi VHDL File (.vhd) altera_mf_components.vhd na librariesvhdlaltera_mf ndekọ.
akụrụngwa altmemmult jeneriki (coeff_representation: eriri: = "SIGNED"; coefficient0: eriri: = "UUSED"; data_representation: eriri : = "SIGNED"; zubere_device_family: eriri : = "ejighi ya"; max_clock_cycles_per_result = coefficient: _natural number:_natural number: : = 1; ram_block:string: = "AUTO"; total_latency: natural; width_d: natural; width_s: natural ”); ọdụ ụgbọ mmiri (elekere: na std_logic; coeff_in: na std_logic_vector (width_c-1 ruo 1): = (ndị ọzọ => '1'); data_in: na std_logic_vector (width_d-0 ruo 0);

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load_mere: pụọ std_logic; nsonaazụ: pụta std_logic_vector (obosara_r-1 ruo 0); result_valid: pụọ std_logic; sclr: na std_logic: = '0'; sel: na std_logic_vector (obosara_s-1 ruo 0): = (ndị ọzọ => '0'); sload_coeff: na std_logic: = '0'; sload_data: na std_logic: = '0'); akụkụ njedebe;

9.4. ọdụ ụgbọ mmiri

Tebụlụ ndị a depụtara ọdụ ụgbọ mmiri ntinye na mmepụta maka isi ALTMEMMULT IP.

Isiokwu 37. ALTMEMMULT ọdụ ụgbọ mmiri ntinye

Aha Port

Achọrọ

Nkọwa

elekere

Ntinye elekere na ọtụtụ.

coeff_in[]

Mba

ọdụ ụgbọ mmiri ntinye ọnụ maka ọtụtụ. Ogo ọdụ ụgbọ mmiri ntinye dabere na uru paramita WIDTH_C.

data_in[]

ọdụ ụgbọ mmiri ntinye data na ụbara. Ogo ọdụ ụgbọ mmiri ntinye dabere na uru paramita WIDTH_D.

sclr

Mba

Ntinye doro anya gakọrịta. Ọ bụrụ na ejighi ya, uru ndabara na-arụ ọrụ dị elu.

sel[]

Mba

Nhọrọ ọnụọgụgụ emebere. Ogo ọdụ ụgbọ mmiri ntinye dabere na WIDTH_S

oke uru.

sload_coeff

Mba

ọdụ ụgbọ mmiri ntinye ọnụọgụ nrụkọ ọrụ. Dochie uru ọnụọgụ ahọpụtara ugbu a na uru akọwapụtara na ntinye coeff_in.

sload_data

Mba

ọdụ ụgbọ ntinye data ibu mmekọrịta. Mgbama na-akọwapụta ọrụ mmụba ọhụrụ ma kagbuo ọrụ mmụba ọ bụla dị. Ọ bụrụ na oke MAX_CLOCK_CYCLES_PER_RESULT nwere uru 1, a na-eleghara ọdụ ụgbọ mmiri sload_data anya.

Isiokwu 38. ALTMEMMULT ọdụ ụgbọ mmiri

Aha Port

Achọrọ

Nkọwa

Nsonaazụ[]

ọdụ ụgbọ mmiri mmepụta ọtụtụ. Ogo ọdụ ụgbọ mmiri ntinye dabere na uru paramita WIDTH_R.

nsonaazụ_dị irè

Na-egosi mgbe mmepụta bụ ezigbo nsonaazụ nke mmụba zuru oke. Ọ bụrụ na paramita MAX_CLOCK_CYCLES_PER_RESULT nwere uru 1, arụpụtaghị ọdụ ụgbọ mmiri arụpụtaghị ihe.

ibu_emela

Mba

Na-egosi mgbe ọnụọgụ ọhụrụ emechara nbudata. Ihe mgbama load_done na-ekwupụta mgbe ọnụọgụ ọhụrụ emechara nbudata. Ọ gwụla ma mgbama load_done dị elu, ọ nweghị uru ọnụọgụ ọzọ enwere ike ibunye na ebe nchekwa.

9.5. Nkeji

Tebụlụ na-esonụ na-edepụta parampat maka ALTMEMMULT IP isi.

Tebụl 39.
WIDTH_D WIDTH_C

Paramita ALTMEMMULT
Aha oke

Ụdị achọrọ

Nkọwa

Integer Ee

Na-akọwapụta obosara nke ọdụ ụgbọ mmiri_in[].

Integer Ee

Na-akọwapụta obosara nke ọdụ ụgbọ mmiri coeff_in[]. gara n'ihu…

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Ntuziaka onye ọrụ Intel FPGA Integer Arithmetic IP Cores 59

9. ALTMEMMULT (Memory dabeere na Constant Coefficient Multiplier) IP Core 683490 | 2020.10.05

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intel FPGA Integer Arithmetic IP Cores [pdf] Ntuziaka onye ọrụ
FPGA Integer Arithmetic IP Cores, Integer Arithmetic IP Cores, Arithmetic IP Cores, IP Cores

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FPGA Integer Arithmetic IP Cores

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