F Tile Serial Lite IV Intel FPGA IP ntuziaka onye ọrụ

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F Tile Serial Lite IV Intel FPGA IP

F-Tile Serial Lite IV Intel® FPGA IP ntuziaka onye ọrụ
Emelitere maka Intel® Quartus® Prime Design Suite: 22.1 Ụdị IP: 5.0.0

Ụdị ntanetị Zipụ nzaghachi

UG-20324

NJ: 683074 Ụdị: 2022.04.28

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1. Banyere F-Tile Serial Lite IV Intel® FPGA IP ntuziaka onye ọrụ……………………………………………….. 4
2. F-Tile Serial Lite IV Intel FPGA IP karịrịview…………………………………………………………………………………. 6 2.1. Ozi mwepụta ………………………………………………………………………………………………………….7 2.2. Atụmatụ akwadoro………………………………………………………………………………………………………….. 7 2.3. Ọkwa nkwado ụdị IP………………………………………………………………………………………………….8 2.4. Nkwado Ọsọ Ọsọ Ngwaọrụ……………………………………………………………………………………………………………….8 2.5. Iji akụrụngwa na ịnwụ anwụ………………………………………………………………………………………………………… 9 2.6. arụmọrụ bandwit……………………………………………………………………………………………………………………………… 9
3. Mmalite……………………………………………………………………………………………………………………………………………………… 11 3.1. Ịwụnye na inye ikike Intel FPGA IP Cores……………………………………………………………………………………… Ụdị nlebanya IP FPGA ………………………………………………………………………………………. 11 3.1.1. Ikowapụta oke na nhọrọ IP……………………………………………………………………………………………………………………………………………… Emepụtara File Ihe owuwu…………………………………………………………………………………………………………………………………… Ịmepụta Intel FPGA IP Cores………………………………………………………………………………………………………… Ịme emume na ikwado atụmatụ ahụ………………………………………………………………. 14 3.4. Njikọ IP Cores na Ngwa EDA Ndị Ọzọ……………………………………………………………………………… 16 3.4.1. Ịchịkọta atụmatụ zuru oke…………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………
4. Nkọwa ọrụ………………………………………………………………………………………………………………….. 19 4.1. Ụzọ data TX ………………………………………………………………………………………………………………………….20 4.1.1. Ihe nkwụnye TX MAC……………………………………………………………………………………………………….. 21 4.1.2. Ntinye Okwu njikwa (CW)……………………………………………………………………………………… 23 4.1.3. TX CRC……………………………………………………………………………………………………………………………………………………………… TX MII Encoder……………………………………………………………………………………………………….28 4.1.4. TX PCS na PMA……………………………………………………………………………………………………………………….. 29 4.1.5. Ụzọ data RX……………………………………………………………………………………………………………… 30 4.2. RX PCS na PMA……………………………………………………………………………………………………………………….. 30 4.2.1. Ihe nrụpụta RX MII……………………………………………………………………………………………………………………………… 31 4.2.2. RX CRC………………………………………………………………………………………………………………………………………….. 31 4.2.3. RX Deskew……………………………………………………………………………………………………………………………………….31 4.2.4. Mwepụ RX CW………………………………………………………………………………………………………………………………………………………………………… 32 4.2.5. F-Tile Serial Lite IV Intel FPGA IP ihe owuwu elekere……………………………………………………………… 35 4.3. Tọgharia na mmalite njikọ ………………………………………………………………………………………….36 4.4. Usoro nrụpụta na mmalite TX………………………………………………………………. 37 4.4.1. Usoro nrụpụta na mmalite RX………………………………………………………………. 38 4.4.2. Ọnụego Njikọ na Mgbakọ arụmọrụ bandwit……………………………………………………………………….. 39
5. Oke ………………………………………………………………………………………………………………………………………………… 42
6. F-Tile Serial Lite IV Intel FPGA IP nrịbama ihu igwe……………………………………………………………………………….. 44 6.1. Mgbama elekere……………………………………………………………………………………………………………………………………….44 6.2. Tọgharia nrịbama ………………………………………………………………………………………………………………………………………… 44 6.3. Ihe akara MAC …………………………………………………………………………………………………………………………………………………………………. 45 6.4. Mgbama nhazigharị transceiver……………………………………………………………………………………………… 48 6.5. Mgbama PMA………………………………………………………………………………………………………………………………………………………………………………………………………

F-Tile Serial Lite IV Intel® FPGA IP ntuziaka onye ọrụ 2

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7. Ime ya na F-Tile Serial Lite IV Intel FPGA IP………………………………………………………………………………… Tọgharia ntuziaka……………………………………………………………………………………………….. 51 7.1. Ntuziaka ijikwa mperi……………………………………………………………………………………………………….51
8. F-Tile Serial Lite IV Intel FPGA IP Ntuziaka onye ọrụ Archives………………………………………………………………. 52 9. Akụkọ ngbanwe akwụkwọ maka F-Tile Serial Lite IV Ntuziaka onye ọrụ IP FPGA…53

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1. Banyere F-Tile Serial Lite IV Intel® FPGA IP ntuziaka onye ọrụ

Akwụkwọ a na-akọwa njirimara IP, nkọwa ụlọ, usoro iji mepụta, yana ntuziaka iji chepụta F-Tile Serial Lite IV Intel® FPGA IP site na iji transceivers F-tile na ngwaọrụ Intel AgilexTM.

Ndị na-ege ntị e bu n'obi

Ezubere akwụkwọ a maka ndị ọrụ ndị a:
· Ndị na-ese ụkpụrụ ụlọ ka ha mee nhọrọ IP n'oge nhazi nhazi ọkwa ọkwa
· Ndị na-emepụta ngwaike mgbe ha na-ejikọta IP n'ime nhazi ọkwa ha
· Ndị injinia na-akwado n'oge usoro ịme anwansị na usoro nkwado ngwaike

Akwụkwọ ndị emetụtara

Tebụlụ na-esote depụtara akwụkwọ ntụaka ndị ọzọ metụtara F-Tile Serial Lite IV Intel FPGA IP.

Tebụl 1.

Akwụkwọ ndị emetụtara

Ntụaka

F-Tile Serial Lite IV Intel FPGA IP Design Example ntuziaka onye ọrụ

Akwụkwọ data ngwaọrụ Intel Agilex

Nkọwa
Akwụkwọ a na-enye ọgbọ, ntuziaka ojiji, yana nkọwa ọrụ nke F-Tile Serial Lite IV Intel FPGA IP imewe ex.amples na ngwaọrụ Intel Agilex.
Akwụkwọ a na-akọwa njirimara eletrik, njirimara mgbanwe, nkọwa nhazi, na oge maka ngwaọrụ Intel Agilex.

Tebụl 2.
CW RS-FEC PMA TX RX PAM4 NRZ

Acronyms na Ndepụta Mkpọ okwu nkọwa
Mkpọchi okwu

Njikwa Mgbasawanye Okwu Reed-Solomon ga-aga n'ihu Mmezi mmezi anụ ahụ nke ọkara mgbakwụnye ihe na-anata usu-Amplitude Modulation 4-Level anaghị alaghachi na efu

gara n'ihu…

Ụlọ ọrụ Intel. Ikike niile echekwabara. Intel, akara Intel, na akara Intel ndị ọzọ bụ ụghalaahịa nke Intel Corporation ma ọ bụ ndị enyemaka ya. Intel nyere ikike ịrụ ọrụ nke FPGA na ngwaahịa semiconductor na nkọwapụta ugbu a dịka akwụkwọ ikike ọkọlọtọ Intel siri dị, mana nwere ikike ịme mgbanwe na ngwaahịa na ọrụ ọ bụla n'oge ọ bụla na-enweghị ọkwa. Intel anaghị ewere ọrụ ọ bụla ma ọ bụ ụgwọ sitere na ngwa ma ọ bụ iji ozi ọ bụla, ngwaahịa ma ọ bụ ọrụ akọwara n'ime ebe a belụsọ dị ka Intel kwetara na ederede. A dụrụ ndị ahịa Intel ọdụ ka ha nweta ụdị nkọwa ngwaọrụ kachasị ọhụrụ tupu ha adabere na ozi ọ bụla ebipụtara yana tupu ịnye iwu maka ngwaahịa ma ọ bụ ọrụ. * Enwere ike ịzọrọ aha na akara ndị ọzọ dị ka ihe onwunwe nke ndị ọzọ.

ISO 9001: 2015 edebanye aha

1. Banyere F-Tile Serial Lite IV Intel® FPGA IP ntuziaka onye ọrụ 683074 | 2022.04.28

PCS MII XGMII

Mkpọchi okwu

Mgbasawanye Ndozi Anụ ahụ Sublayer Media Independent Interface 10 Gigabit Media Independent Interface

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2. F-Tile Serial Lite IV Intel FPGA IP karịrịview

Onyonyo 1.

F-Tile Serial Lite IV Intel FPGA IP dabara adaba maka nzikọrịta data bandwidth dị elu maka mgbawa-na-chip, bọọdụ na bọọdụ, na ngwa azụ azụ.

F-Tile Serial Lite IV Intel FPGA IP na-agụnye njikwa ohere mgbasa ozi (MAC), sublayer nzuzo (PCS), na mgbakwunye mgbasa ozi anụ ahụ (PMA). IP na-akwado ọsọ mbufe data ruru 56 Gbps n'otu ụzọ nwere oke ụzọ anọ PAM4 ma ọ bụ 28 Gbps n'otu ụzọ nwere oke ụzọ 16 NRZ. IP a na-enye bandwidth dị elu, okpokolo agba dị ala, ọnụ ọgụgụ I/O dị ala, ma na-akwado scalability dị elu na ọnụọgụ abụọ nke ụzọ na ọsọ. IP a na-adịkwa mfe ịhazigharị ya site na nkwado nke ọnụọgụ data dị iche iche na ọnọdụ PCS Ethernet nke transceiver F-tile.

IP a na-akwado ụdị nnyefe abụọ:
Ọnọdụ ntọala - Nke a bụ ụdị nkwanye ugwu dị ọcha ebe ezigara data na-enweghị mmalite nke ngwugwu, okirikiri efu, na ngwugwu njedebe iji bulie bandwit. IP na-ewere data izizi dị irè dị ka mmalite nke mgbawa.
Ọnọdụ zuru oke - Nke a bụ ụdị mbufe ngwugwu. Na ọnọdụ a, IP na-eziga mgbawa na usoro mmekọrịta na mmalite na njedebe nke ngwugwu dị ka ndị na-egbochi.

Ihe eserese F-Tile Serial Lite IV dị elu

Avalon Streaming Interface TX

F-Tile Serial Lite IV Intel FPGA IP
MAC TX
TX USRIF_CTRL

64 * n ụzọ bits (ụdị NRZ) / 2 * n ụzọ ibe n'ibe (PAM4 mode)

TX MAC

Ihe nkwụnye INSERT

MII ENCODE

PCS omenala

TX PCS

TX MII

EMIB ENCODE SCRAMBLER FEC

TX PMA

n Lanes Bits (ụdị PAM4)/ n Lanes Bits (ụdị NRZ)
TX Oghere Usoro Interface

Avalon Streaming Interface RX
64 * n ụzọ bits (ụdị NRZ) / 2 * n ụzọ ibe n'ibe (PAM4 mode)

PCS RX

CW RMV

DESKEW

MII

& Kpọgharịa dekode

RX MII

EMIB

Kpebie mmekọrịta ngọngọ & FEC DESCRAMBLER

RX PMA

CSR

2n Lanes Bits (ụdị PAM4)/ n Lanes Bits (ụdị NRZ) RX Serial Interface
Avalon ebe nchekwa-mapped interface ndekọ Config

Akụkọ mgbe ochie

Echiche dị nro

Echiche siri ike

ISO 9001: 2015 edebanye aha

2. F-Tile Serial Lite IV Intel FPGA IP karịrịview 683074 | 2022.04.28

Ị nwere ike ịmepụta F-Tile Serial Lite IV Intel FPGA IP imewe exampka ịmatakwu gbasara njirimara IP. Rụtụ aka na F-Tile Serial Lite IV Intel FPGA IP Design Example ntuziaka onye ọrụ.
Ozi metụtara · Nkọwa ọrụ na ibe 19 · F-Tile Serial Lite IV Intel FPGA IP Design Ex.ample ntuziaka onye ọrụ

2.1. Ozi mwepụta

Ụdị Intel FPGA IP dabara na ụdị ngwanrọ Intel Quartus® Prime Design Suite ruo mgbe v19.1. Malite na ụdị sọftụwia Intel Quartus Prime Design Suite 19.2, Intel FPGA IP nwere atụmatụ mbipụta ọhụrụ.

Nọmba Intel FPGA IP ụdị (XYZ) nwere ike ịgbanwe na ụdị sọftụwia Intel Quartus Prime ọ bụla. Mgbanwe na:

X na-egosi ntughari isi nke IP. Ọ bụrụ na imelite ngwa ngwa Intel Quartus Prime, ị ga-emerịrị IP.
Y na-egosi na IP gụnyere atụmatụ ọhụrụ. Megharịa IP gị ka ịtinye atụmatụ ọhụrụ ndị a.
Z na-egosi na IP gụnyere obere mgbanwe. Megharịa IP gị ka ịtinye mgbanwe ndị a.

Tebụl 3.

F-Tile Serial Lite IV Intel FPGA IP ozi mwepụta

Nkebi IP Ụdị Intel Quartus Prime Ụdị Mwepụta ụbọchị ịtụ koodu

5.0.0 22.1 2022.04.28 IP-SLITE4F

Nkọwa

2.2. Atụmatụ akwadoro
Tebụlụ na-esonụ depụtara atụmatụ dị na F-Tile Serial Lite IV Intel FPGA IP:

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Tebụl 4.

F-Tile Serial Lite IV Intel FPGA IP atụmatụ

Njirimara

Nkọwa

Nyefee data

Maka ụdị PAM4:
- FHT na-akwado naanị 56.1, 58, na 116 Gbps kwa uzo nwere oke ụzọ anọ.
- FGT na-akwado ihe ruru 58 Gbps n'otu ụzọ yana oke ụzọ iri na abụọ.
Rụtụ aka na Tebụl 18 na ibe 42 maka nkọwa ndị ọzọ na ọnụego data transceiver akwadoro maka ọnọdụ PAM4.
Maka ụdị NRZ:
- FHT na-akwado naanị 28.05 na 58 Gbps kwa uzo nwere oke ụzọ anọ.
- FGT na-akwado ihe ruru 28.05 Gbps n'otu ụzọ yana oke ụzọ iri na isii.
Rụtụ aka na tebụl 18 na ibe 42 maka nkọwa ndị ọzọ na ọnụego data transceiver akwadoro maka ọnọdụ NRZ.
Na-akwado ụdị nkwanye ugwu na-aga n'ihu (Basic) ma ọ bụ ngwugwu (Full).
· Na-akwado ngwugwu etiti etiti dị ala.
Na-akwado mbufe granularity byte maka nha ọ bụla gbawara.
Na-akwado nhazi ụzọ onye ọrụ malitere ma ọ bụ akpaka.
· Na-akwado oge itinye n'usoro mmemme.

PCS

Na-eji mgbagha IP siri ike nke na-ejikọta Intel Agilex F-tile transceivers maka mbelata akụrụngwa mgbagha dị nro.
Na-akwado ụdị mgbanwe PAM4 maka nkọwapụta 100GBASE-KP4. A na-enyere RS-FEC aka mgbe niile n'ụdị modulation a.
Na-akwado NRZ na nhọrọ RS-FEC modulation mode.
· Na-akwado ngbanwe ngbanwe 64b/66b.

Nchọpụta na njikwa njehie

Na-akwado ịlele njehie CRC na ụzọ data TX na RX. Na-akwado ịlele njehie njikọ RX. Na-akwado nchọpụta njehie RX PCS.

Ọnụ ụzọ

· Na-akwado naanị mbufe ngwugwu duplex zuru oke yana njikọ nwere onwe.
Na-eji njikọ ọnụ-na-atụ n'ọtụtụ ngwaọrụ FPGA nwere nkwụsị mbufe dị ala.
· Na-akwado iwu akọwapụtara onye ọrụ.

2.3. Ọkwa nkwado ụdị IP

Akụrụngwa Intel Quartus Prime na nkwado ngwaọrụ Intel FPGA maka F-Tile Serial Lite IV Intel FPGA IP bụ nke a:

Tebụl 5.

Ụdị IP na ọkwa nkwado

Intel Quartus Prime 22.1

Ngwaọrụ Intel Agilex F-tile transceivers

Nhazi ngwaike mbipụta ụdịdị IP

5.0.0

2.4. Nkwado ọkwa ọsọ ngwaọrụ
The F-Tile Serial Lite IV Intel FPGA IP na-akwado akara ọsọ ọsọ ndị a maka ngwaọrụ Intel Agilex F-tile: · Ọsọ ọsọ transceiver: -1, -2, na -3 · Isi ọsọ ọsọ: -1, -2, na - 3

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Ozi metụtara
Mpempe akwụkwọ data ngwaọrụ Intel Agilex Ozi ndị ọzọ gbasara ọnụego data akwadoro na transceivers F-tile Intel Agilex.

2.5. Iji akụrụngwa na nkwụsị

Enwetara akụrụngwa na ọgbaghara maka F-Tile Serial Lite IV Intel FPGA IP sitere na ụdị sọftụwia Intel Quartus Prime Pro Edition 22.1.

Tebụl 6.

Intel Agilex F-Tile Serial Lite IV Intel FPGA IP akụrụngwa itinye n'ọrụ
Ntụle latency gbadoro ụkwụ na mgbagha njem okirikiri site na ntinye isi TX gaa na mmepụta isi RX.

Ụdị transceiver

Ọdịiche

Ọnụọgụ Data Ụzọ Ụzọ RS-FEC ALM

Latency (usoro elekere TX isi)

FGT

28.05 Gbps NRZ 16

Isi nkwarụ 21,691 65

Enwere nkwarụ zuru oke 22,135 65

Agbanyere isi 21,915 189

Ejuputara 22,452 189

58 Gbps PAM4 12

Agbanyere isi 28,206 146

Ejuputara 30,360 146

FHT

58 Gbps NRZ

Agbanyere isi 15,793 146

Ejuputara 16,624 146

58 Gbps PAM4 4

Agbanyere isi 15,771 154

Ejuputara 16,611 154

116 Gbps PAM4 4

Agbanyere isi 21,605 128

Ejuputara 23,148 128

2.6. arụmọrụ bandwit

Tebụl 7.

arụmọrụ bandwit

Ụdị mgbanwe mgbanwe

PAM4

Ụdị gụgharia RS-FEC

Agbanyere n'uju

Agbanyere isi

Ọnụego ntanye interface serial na Gbps (RAW_RATE)
Nha mbufe n'ọnụọgụ okwu (BURST_SIZE) (1)
Oge nhazi n'ime okirikiri elekere (SRL4_ALIGN_PERIOD)

56.0 2,048 4,096

56.0 4,194,304 4,096

Ntọala

NRZ

Juputara

Agbanyụrụ

Agbanyere

28.0

2,048

4,096

Isi nkwarụ 28.0

Agbanyere 28.0

4,194,304

4,096

4,096 gara n'ihu…

(1) BURST_SIZE maka Basic mode na-abịaru nso enweghi ngwụcha, ya mere a na-eji ọnụọgụ buru ibu.

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Mgbanwe

Ntọala

64/66b koodu

0.96969697 0.96969697 0.96969697 0.96969697 0.96969697

N'elu nha nchara n'ọnụọgụ okwu (BURST_SIZE_OVHD)

2 (2)

0 (3)

2 (2)

0 (3)

Oge nrịbama 81,915 na okirikiri elekere (ALIGN_MARKER_PERIOD)

81,915

81,916

obosara akara nkwụnye n'ime 5

okirikiri elekere

(ALIGN_MARKER_WIDTH)

arụmọrụ bandwit (4)

0.96821788 0.96916433 0.96827698 0.96822967 0.96922348

Ọnụego dị irè (Gbps) (5)

54.2202012 54.27320236 27.11175544 27.11043076 27.13825744

Oge elekere onye ọrụ kacha (MHz) (6)

423.59532225 424.00939437 423.62117875 423.6004806 424.0352725

Ọnụego Njikọ Ozi emetụtara na Mgbakọ arụmọrụ bandwit na ibe 40

(2) N'ụdị zuru oke, nha BURST_SIZE_OVHD gụnyere Okwu njikwa START/END jikọtara ọnụ na iyi data.
(3) N'ihi na Basic mode, BURST_SIZE_OVHD bụ 0 n'ihi na ọ dịghị START/END n'oge nkwanye.
(4) Rụtụ aka na Ọnụego Njikọ na Mgbakọ arụmọrụ bandwit maka ngụkọ arụmọrụ bandwit.
(5) Rụtụ aka na Ọnụego Njikọ na Mgbakọ arụmọrụ bandwit maka ịgbakọ ọnụego dị irè.
(6) Rụtụ aka na ọnụ ọgụgụ njikọ yana mgbako arụmọrụ bandwit maka ịgbakọ oge elekere onye ọrụ kacha.

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3. Mmalite

3.1. Ịwụnye na inye ikike Intel FPGA IP Cores

Nrụnye ngwanrọ Intel Quartus Prime gụnyere ọba akwụkwọ Intel FPGA IP. Ọbá akwụkwọ a na-enye ọtụtụ cores IP bara uru maka iji mmepụta gị na-enweghị mkpa maka ikike ọzọ. Ụfọdụ cores Intel FPGA IP chọrọ ịzụrụ ikike dị iche maka iji mmepụta. Ụdị nyocha IP FPGA nke Intel na-enye gị ohere inyocha ihe ndị a nwere ikike Intel FPGA IP cores na simulation na ngwaike, tupu ị kpebie ịzụta ikikere IP isi mmepụta zuru oke. Naanị ị ga-azụta ikikere mmepụta zuru oke maka cores Intel IP nwere ikikere mgbe ịmechara nyocha ngwaike ma dị njikere iji IP na mmepụta.

Akụrụngwa Intel Quartus Prime na-etinye cores IP na ebe ndị a na ndabara:

Onyonyo 2.

Ụzọ nwụnye isi IP
intelFPGA(_pro) quartus - Nwere Intel Quartus Prime sọftụwia ip - Nwere ọbá akwụkwọ Intel FPGA IP na cores IP nke ndị ọzọ - Nwere koodu isi iyi ọba akwụkwọ Intel FPGA IP - Nwere isi iyi IP FPGA Intel files

Tebụl 8.

Ebe nwụnye isi IP

Ebe

Ngwa ngwa

:intelFPGA_proquartusipaltera

Intel Quartus Prime Pro Edition

:/intelFPGA_pro/quartus/ip/altera Intel Quartus Prime Pro Edition

Windows Platform* Linux*

Mara:

Akụrụngwa Intel Quartus Prime anaghị akwado oghere na ụzọ nwụnye.

3.1.1. Ọnọdụ nyocha Intel FPGA IP
Ụdị nlebanya IP FPGA nke efu na-enye gị ohere inyocha cores FPGA IP nwere ikikere na simulation na ngwaike tupu ịzụrụ. Ụdị nyocha IP FPGA nke Intel na-akwado nyocha ndị a na-enweghị ikike ọzọ:
Mepụta omume nke isi Intel FPGA IP nwere ikike na sistemụ gị. · Nyochaa arụmọrụ, nha na ọsọ nke isi IP ngwa ngwa na ngwa ngwa. · Mepụta mmemme ngwaọrụ nwere oke oge files maka imewe na-agụnye IP cores. · Hazie ngwaọrụ na isi IP gị wee nyochaa imewe gị na ngwaike.

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Ọnọdụ nyocha Intel FPGA IP na-akwado ụdị ọrụ ndị a:
Ejikọtara - Na-enye ohere ịme nhazi ahụ nwere ikikere Intel FPGA IP ruo mgbe ebighị ebi yana njikọ dị n'etiti bọọdụ gị na kọmputa ndị ọbịa. Ụdị ejikọrọ chọrọ otu ihe omume nyocha njikọ njikọ (JTAG) eriri ejikọrọ n'etiti JTAG ọdụ ụgbọ mmiri na bọọdụ gị na kọmpụta nnabata, nke na-agba Intel Quartus Prime Programmer maka oge nyocha ngwaike. Onye mmemme chọrọ naanị ntinye opekempe nke sọftụwia Intel Quartus Prime, ọ nweghị ikike Intel Quartus Prime. Kọmputa onye nnabata na-ejikwa oge nleba anya site na izipu mgbaama oge na ngwaọrụ site na JTAG ọdụ ụgbọ mmiri. Ọ bụrụ na cores IP niile nwere ikike na imewe na-akwado ọnọdụ ejikọtara, oge nleba anya na-aga ruo mgbe nyocha isi IP ọ bụla ga-agwụ. Ọ bụrụ na cores IP niile na-akwado oge nleba anya na-akparaghị ókè, ngwaọrụ anaghị akwụsị oge.
Enweghị njikọ - Na-enye ohere ịme nhazi nke nwere IP nwere ikike maka obere oge. Isi IP na-alaghachi na ọnọdụ enweghị njikọ ma ọ bụrụ na ngwaọrụ ahụ kwụsịrị na kọmputa onye ọbịa na-agba Intel Quartus Prime software. Isi IP na-alaghachikwa na ọnọdụ enweghị njikọ ma ọ bụrụ na isi IP ọ bụla nwere ikikere na imewe anaghị akwado ọnọdụ ejikọrọ.
Mgbe oge nlebanya ga-agwụ maka Intel FPGA IP ọ bụla nwere ikike na nhazi ahụ, imewe ahụ kwụsịrị ịrụ ọrụ. Cores IP niile na-eji Intel FPGA IP Evaluation Mode na-apụ n'otu oge mgbe isi IP ọ bụla na-apụ. Mgbe oge nlebanya ga-agwụ, ị ga-emegharị ngwaọrụ FPGA tupu ịga n'ihu nkwenye ngwaike. Iji gbasaa ojiji nke isi IP maka mmepụta, zụta ikike mmepụta zuru oke maka isi IP.
Ị ga-azụrịrị ikikere wee wepụta igodo ikike mmepụta zuru oke tupu ị nwee ike ịmepụta mmemme ngwaọrụ na-enweghị mgbochi file. N'oge Intel FPGA IP Evaluation Mode, Compiler na-ewepụta mmemme ngwaọrụ nwere obere oge. file ( _time_limited.sof) na-ekubi ume na njedebe oge.

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Onyonyo 3.

Ọnọdụ nyocha Intel FPGA IP
Wụnye Intel Quartus Prime Software na Intel FPGA IP Library

Mepụta ma kwalite Intel FPGA IP Core ikikere

Nyochaa IP na Simulator akwadoro

Mepụta atụmatụ ahụ na Intel Quartus Prime Software

Mepụta mmemme ngwaọrụ nwere oke oge File

Hazie ngwaọrụ FPGA Intel wee nyochaa ọrụ na bọọdụ
Ọ nweghị IP dị njikere maka iji mmepụta?
Ee zụrụ mmepụta zuru oke
Ikikere IP

Mara:

Tinye IP nwere ikike na ngwaahịa azụmaahịa
Rụtụ aka na ntuziaka onye ọrụ IP nke ọ bụla maka usoro nbipụta na nkọwa mmejuputa.
Intel na-enye ikikere IP cores na otu oche, na-adịgide adịgide. Ụgwọ akwụkwọ ikike gụnyere mmezi na nkwado afọ mbụ. Ị ga-emerịrị nkwekọrịta mmezi ka ị nweta mmelite, ndozi ahụhụ, na nkwado teknụzụ gafere afọ mbụ. Ị ga-azụrịrị ikikere mmepụta zuru oke maka Intel FPGA IP cores nke chọrọ ikikere mmepụta, tupu ịmepụta mmemme filenke ị nwere ike iji maka oge na-akparaghị ókè. N'oge Intel FPGA IP Evaluation Mode, Compiler na-ewepụta mmemme ngwaọrụ nwere obere oge. file ( _time_limited.sof) na-ekubi ume na njedebe oge. Iji nweta igodo ikike mmepụta gị, gaa na ụlọ ọrụ ikikere ọrụ onwe nke Intel FPGA.
Nkwekọrịta ikike sọftụwia Intel FPGA na-achịkwa nrụnye na ojiji nke cores IP nwere ikike, sọftụwia Intel Quartus Prime imewe, yana cores IP niile na-enweghị ikike.

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Ozi metụtara · Ebe nkwado ikike ikike Intel FPGA · Okwu Mmalite na ntinye na ikikere ngwa ngwa Intel FPGA
3.2. Na-akọwapụta oke IP na nhọrọ
Ihe ndezi paramita IP na-enye gị ohere ịhazi mgbanwe IP nke omenala gị ngwa ngwa. Jiri usoro ndị a iji kọwapụta nhọrọ IP na parampat na sọftụwia Intel Quartus Prime Pro Edition.
1. Ọ bụrụ na i nwebeghị ọrụ Intel Quartus Prime Pro Edition nke iji jikọta F-Tile Serial Lite IV Intel FPGA IP, ị ga-emerịrị otu. a. Na Intel Quartus Prime Pro Edition, pịa File Ọkachamara Project ọhụrụ iji mepụta ọrụ Quartus Prime ọhụrụ, ma ọ bụ File Mepee Project ka imepe ọrụ Quartus Prime dị. Ọkachamara na-akpali gị ezipụta ngwaọrụ. b. Ezipụta ezinụlọ ngwaọrụ Intel Agilex wee họrọ ngwaọrụ F-tile mmepụta nke na-emezu ọkwa ọkwa ọsọ maka IP. c. Pịa N'ikpeazụ.
2. Na katalọgụ IP, chọta ma họrọ F-Tile Serial Lite IV Intel FPGA IP. Window mgbanwe IP ọhụrụ na-egosi.
3. Ezipụta aha ọkwa dị elu maka mgbanwe IP omenala ọhụrụ gị. Onye ndezi paramita na-echekwa ntọala IP dị iche na a file aha ya .ip.
4. Pịa OK. Ihe ndezi paramita na-egosi. 5. Ezipụta paramita maka mgbanwe IP gị. Gaa na ngalaba Parameter maka
ozi gbasara F-Tile Serial Lite IV Intel FPGA IP paramita. 6. Nhọrọ, ka ịmepụta testbench simulation ma ọ bụ nchịkọta na nhazi ngwaike
example, soro ntuziaka dị na Kere Example ntuziaka onye ọrụ. 7. Pịa n'ịwa HDL. Igbe okwu ọgbọ na-egosi. 8. Ezipụta mmepụta file ọgbọ nhọrọ, wee pịa n'ịwa. IP dị iche iche
files n'ịwa dị ka gị nkọwa. 9. Pịa N'ikpeazụ. Onye ndezi paramita na-agbakwụnye .ip file ruo ugbu a
oru ngo na-akpaghị aka. Ọ bụrụ na a kpaliri gị iji aka tinye .ip file na oru ngo, pịa Project Tinye/Wepụ Files na Project ịgbakwunye ihe file. 10. Mgbe ịmepụta na ozugbo IP gị mgbanwe, mee pin kwesịrị ekwesị ọrụ jikọọ ọdụ ụgbọ mmiri na tọọ ihe ọ bụla kwesịrị ekwesị kwa oge RTL parameters.
Oke ozi emetụtara na ibe 42
3.3. Emepụtara File Nhazi
Akụrụngwa Intel Quartus Prime Pro na-emepụta mmepụta IP ndị a file nhazi.
Maka ozi gbasara file Ọdịdị nke imewe example, rụtụ aka na F-Tile Serial Lite IV Intel FPGA IP Design Example ntuziaka onye ọrụ.

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Ọgụgụ 4. F-Tile Serial Lite IV Intel FPGA IP Emepụtara Files
.ip – IP mwekota file

IP mgbanwe files

_ IP mgbanwe files

example_design

.cmp – nkwupụta akụrụngwa VHDL file _bb.v – Verilog HDL igbe ojii EDA njikọ file _inst.v na .vhd – Sample instantiation ndebiri .xml- akụkọ XML file

Example ebe maka IP isi imewe gị example files. Ebe ndabara bụ example_design, mana a kpaliri gị ịkọwa ụzọ dị iche.

.qgsimc – Na-edepụta paramita ịme anwansị iji kwado mmeghari ohuru .qgsynthc - Na-edepụta paramita njikọ iji kwado mmeghari ohuru

.qip – Ndepụta IP njikọ files

_generation.rpt- IP ọgbọ akụkọ

.sopcinfo- Ngwakọta ngwa-agbụ akụrụngwa file .html- Njikọ na ebe nchekwa data data

.csv – Pin ọrụ file

.spd - Na-ejikọta edemede ịme anwansị n'otu n'otu

Simulation files

synth IP njikọ files

.v Simulation dị elu file

.v Njikọ IP dị elu file

Ederede simulator

Subcore ọba akwụkwọ

synth
Subcore njikọ files

sim
Subcore Simulation files

Tebụl 9.

F-Tile Serial Lite IV Intel FPGA IP emepụtara Files

File Aha

Nkọwa

.ip

Sistemụ Onye nrụpụta Platform ma ọ bụ mgbanwe IP dị elu file. bụ aha ị na-enye IP gị iche.

.cmp

Nkwupụta akụkụ VHDL (.cmp) file bụ ederede file nke nwere nkọwa mpaghara yana nkọwa ọdụ ụgbọ mmiri ị nwere ike iji na imewe VHDL files.

.html

Akụkọ nwere ozi njikọ, map ebe nchekwa na-egosi adres ohu nke ọ bụla gbasara nna ukwu ọ bụla e jikọtara ya na ya, na ihe omume ndị e kenyere ya.

_generation.rpt

log ọgbọ IP ma ọ bụ Platform Designer file. Nchịkọta nke ozi n'oge ọgbọ IP.

.qgsimc

Na-edepụta parampat ịme anwansị iji kwado mmeghari ohuru.

.qgsynthc

Na-edepụta paramita njikọ iji kwado mmekwalite ọhụrụ.

.qip

Nwere ozi niile achọrọ gbasara akụrụngwa IP iji jikọta yana chịkọta mpaghara IP na sọftụwia Intel Quartus Prime.
gara n'ihu…

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File Aha .sopcinfo
.csv .spd _bb.v _inst.v ma ọ bụ _inst.vhd .regmap
.svd
.v ma ọ bụ .vhd mentor/ synopsys/vcs/ synopsys/vcsmx/ xcelium/ submodules/ /

Nkọwa
Na-akọwa njikọ dị na mpaghara IP dị n'ime sistemụ Onye nrụpụta Platform gị. Ị nwere ike ịtụgharị ọdịnaya ya ka ị nweta ihe achọrọ mgbe ịmepụtara ndị ọkwọ ụgbọala software maka ihe IP. Ngwa ndị dị n'okpuru ala dịka ụdọ ngwá ọrụ Nios® II na-eji nke a file. The .sopcinfo file na usoro.h file emebere maka yinye ngwa Nios II gụnyere ozi maapụ adreesị maka ohu ọ bụla onye ikwu nke nna ukwu ọ bụla na-abanye na ohu ahụ. Ndị nna ukwu dị iche iche nwere ike ịnwe map adreesị dị iche iji nweta otu akụkụ ohu.
Nwere ozi gbasara ọkwa nkwalite nke akụrụngwa IP.
Ntinye achọrọ file maka ip-make-simscript iji wepụta script simulation maka simulators akwadoro. Ihe .spd file nwere ndepụta nke files emepụtara maka ịme anwansị, yana ozi gbasara ncheta ị nwere ike ibido.
Ị nwere ike iji Verilog black-box (_bb.v) file dị ka nkwupụta modul efu maka iji dị ka igbe ojii.
HDL example instantiation template. Ị nwere ike idetuo na mado ọdịnaya nke a file n'ime HDL gị file iji mee ka IP dị iche iche ozugbo.
Ọ bụrụ na IP nwere ozi ndekọ aha, .regmap file na-ebute. The .regmap file na-akọwa ozi map ndekọ aha nke oghere nna ukwu na ohu. Nke a file emeju .sopcinfo file site n'inye nkọwa ndekọ aha zuru ezu gbasara usoro. Nke a na-enyere ngosi ndekọ aha views na ọnụ ọgụgụ ahaziri nke onye ọrụ na Console Sistemu.
Na-enye ohere maka sistemụ nrụpụta siri ike (HPS) ngwaọrụ nbipu sistemụ view maapụ ndekọ aha nke mpụta ejikọrọ na HPS n'ime sistemu Onye nrụpụta Platform. N'oge nhazi, .svd fileA na-echekwa s maka oghere ndị ohu na-ahụ anya nye ndị isi Sistemu Console na .sof file na ngalaba debug. Sistemụ njikwa na-agụ ngalaba a, nke Onye nrụpụta Platform nwere ike jụọ maka ịdebanye aha maapụ ozi. Maka ndị ohu sistemụ, Onye nrụpụta Platform nwere ike ịnweta ndekọ aha ya.
HDL files na-emepe submodule ọ bụla ma ọ bụ IP nwa maka njikọ ma ọ bụ ịme anwansị.
Nwere a ModelSim*/QuestaSim* script msim_setup.tcl iji melite na mee ihe ngosi.
Nwere script shei vcs_setup.sh iji hazie ma mee simulation VCS*. Nwere script shei vcsmx_setup.sh na synopsys_sim.setup file ka ịtọlite ma mee ihe ngosi VCS MX.
Nwere script shei xcelium_setup.sh na nhazi ndị ọzọ files ka ịtọlite ma mee simulation Xcelium*.
Nwere HDL files maka submodules IP.
Maka akwụkwọ ndekọ aha IP ụmụaka ọ bụla emepụtara, Platform Designer na-ewepụta akwụkwọ ndekọ aha synth/ na sim/ sub-directories.

3.4. Ịmepụta Intel FPGA IP Cores
Akụrụngwa Intel Quartus Prime na-akwado simulation IP isi RTL na simulators EDA akọwapụtara. Ọgbọ IP na-emepụta simulation na nhọrọ files, gụnyere ụdị ịme anwansị na-arụ ọrụ, testbench ọ bụla (ma ọ bụ example design), na scripts ntọala simulator akọwapụtara nke onye na-ere ahịa maka isi IP ọ bụla. Ị nwere ike iji ụdị ịme anwansị na-arụ ọrụ yana testbench ọ bụla ma ọ bụ example imewe maka ịme anwansị. Mmepụta ọgbọ IP nwekwara ike ịgụnye scripts iji chịkọta ma mee testbench ọ bụla. Edemede a depụtara ụdị ma ọ bụ ọba akwụkwọ niile ịchọrọ iji megharịa isi IP gị.

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Akụrụngwa Intel Quartus Prime na-enye njikọta na ọtụtụ simulators ma na-akwado ọtụtụ usoro ịme anwansị, gụnyere nke gị scripted na usoro ịme anwansị. Usoro ọ bụla ị họọrọ, simulation IP core gụnyere usoro ndị a:
1. Mepụta IP HDL, testbench (ma ọ bụ example design), na edemede ntọlite simulator files.
2. Hazie gburugburu simulator gị na script simulation ọ bụla.
3. Chịkọta ụlọ akwụkwọ simulation model.
4. Gbaa simulator gị.

3.4.1. Ịmepụta na nyochaa imewe ahụ

Site na ndabara, onye na-edezi paramita na-ewepụta script nke simulator nwere iwu iji chịkọta, kọwapụta, na ịmegharị ụdị Intel FPGA IP na ọba akwụkwọ simulation. files. Ị nwere ike idetuo iwu n'ime edemede testbench simulation gị, ma ọ bụ dezie ndị a files ịgbakwunye iwu maka ịchịkọta, ịkọwapụta na ịmegharị imewe na testbench gị.

Isiokwu 10. Intel FPGA IP Core Simulation Scripts

Simulator

File Akwụkwọ ndekọ aha

ModelSim

_sim/ndụmọdụ

QuestaSim

VCS

_sim/synopsys/vcs

VCS MX

_sim/synopsys/vcsmx

Xcelium

_sim/xcelium

Ederede msim_setup.tcl (7)
vcs_setup.sh vcsmx_setup.sh synopsys_sim.setup xcelium_setup.sh

3.5. Ịmekọrịta IP Cores na Ngwa EDA ndị ọzọ
Nhọrọ, jiri ngwa EDA ọzọ akwadoro iji rụpụta imewe nke gụnyere Intel FPGA IP cores. Mgbe ị na-emepụta njikọ IP isi files maka iji ya na ngwa mgbakwunye EDA ndị ọzọ, ị nwere ike ịmepụta mpaghara na netlist atụmatụ oge. Iji mee ka ọgbọ nwee ike, gbanye Mepụta oge na atụmatụ akụrụngwa maka ngwaọrụ njikọ EDA ndị ọzọ mgbe ị na-ahazi ụdị IP gị.
Mpaghara na ngụ oge netlist na-akọwa njikọ IP isi na ụkpụrụ ụlọ, mana anaghị agụnye nkọwa gbasara ezigbo ọrụ. Ozi a na-enyere ụfọdụ ngwaọrụ njikọ nke ndị ọzọ aka ka ọ dị mma ịkọ mpaghara yana atụmatụ oge. Na mgbakwunye, ngwaọrụ njikọ nwere ike iji ozi oge iji nweta nkwalite oge na-akwalite ma melite ogo nsonaazụ.
Ngwa Intel Quartus Prime na-emepụta ihe ndị a _syn.v netlist file na usoro Verilog HDL, n'agbanyeghị mmepụta file format ị ezipụta. Ọ bụrụ na ijiri netlist a maka njikọ, ị ga-etinyerịrị ihe mkpuchi IP isi file .v ma ọ bụ .vhd n'ime ọrụ Intel Quartus Prime gị.

(7) Ọ bụrụ na ịtọbeghị nhọrọ ngwaọrụ EDA - nke na-enyere gị aka ịmalite simulators EDA nke atọ site na sọftụwia Intel Quartus Prime-gbaa edemede a na ModelSim ma ọ bụ QuestaSim simulator Tcl console (ọ bụghị na sọftụ Intel Quartus Prime. Tcl console) iji zere mperi ọ bụla.

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3.6. Na-achịkọta atụmatụ zuru oke
Ị nwere ike iji iwu mmalite nchịkọta na menu nhazi na Intel Quartus Prime Pro Edition software iji chịkọta nhazi gị.

F-Tile Serial Lite IV Intel® FPGA IP ntuziaka onye ọrụ 18

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4. Nkọwa ọrụ

Onyonyo 5.

F-Tile Serial Lite IV Intel FPGA IP nwere PC MAC na Ethernet. MAC na-ekwurịta okwu na PCS omenala site na MII interfaces.

IP na-akwado ụdị modulation abụọ:
PAM4 – Na-enye ọnụọgụ ụzọ 1 ruo 12 maka nhọrọ. IP na-ewepụta ọwa PCS abụọ maka ụzọ ọ bụla na ọnọdụ mgbanwe PAM4.
· NRZ – Na-enye ọnụọgụ ụzọ 1 ruo 16 maka nhọrọ.

Ụdị modulation ọ bụla na-akwado ụdị data abụọ:
Ọnọdụ ntọala - Nke a bụ ụdị nkwanye ugwu dị ọcha ebe ezigara data na-enweghị mmalite nke ngwugwu, okirikiri efu, na ngwugwu njedebe iji bulie bandwit. IP na-ewere data izizi dị irè dị ka mmalite nke mgbawa.

Nbufe data nke usoro tx_core_clkout tx_avs_ready

tx_avs_valid tx_avs_data rx_core_clkout rx_avs_ready

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

rx_avs_valid rx_avs_data

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

ISO 9001: 2015 edebanye aha

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Onyonyo 6.

Ọnọdụ zuru oke - Nke a bụ ịnyefe data ọnọdụ ngwugwu. Na ọnọdụ a, IP na-eziga mgbawa na usoro mmekọrịta na mmalite na njedebe nke ngwugwu dị ka ndị na-egbochi.

Nbufe data zuru oke tx_core_clkout

tx_avs_ready tx_avs_valid tx_avs_startofpacket tx_avs_endofpacket
tx_avs_data rx_core_clkout rx_avs_ready rx_avs_valid rx_avs_startofpacket rx_avs_endofpacket

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

rx_avs_data

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

Ozi metụtara · F-Tile Serial Lite IV Intel FPGA IP Overview na ibe 6 · F-Tile Serial Lite IV Intel FPGA IP Design Example ntuziaka onye ọrụ

4.1. Data ụzọ TX
Ụzọ data TX nwere ihe ndị a: · Ihe nkwụnye MAC · Mgbochi ntinye okwu njikwa · CRC · MII koodu · ngọngọ PCS · ngọngọ PMA

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Ọgụgụ 7. TX Datapath

Site na mgbagha onye ọrụ

TX MAC

Avalon Streaming Interface

Ihe nkwụnye MAC

Njikwa ntinye Okwu

CRC

MII koodu

PCS Custom Interface MII
PCS na PMA

Oghere Usoro TX na ngwaọrụ FPGA ndị ọzọ

4.1.1. Ihe nkwụnye TX MAC
Ihe nkwụnye TX MAC na-achịkwa nnyefe data na mgbagha onye ọrụ site na iji Avalon® gụgharia interface. Ihe mgbochi a na-akwado nnyefe ozi akọwapụtara nke onye ọrụ yana njikwa eruba.

Ịnyefe ozi akọwapụtara nke onye ọrụ

Na ọnọdụ zuru oke, IP na-enye tx_is_usr_cmd mgbama ị nwere ike iji bido okirikiri ozi akọwapụtara onye ọrụ dị ka nnyefe XOFF/XON na mgbagha onye ọrụ. Ị nwere ike ibido okirikiri ozi akọwapụtara nke onye ọrụ site n'ịkwado mgbama a wee bufee ozi site na iji tx_avs_data yana nkwuputa nke tx_avs_startofpacket na tx_avs_valid signal. Ihe mgbochi ahụ wee deassert tx_avs_ready maka okirikiri abụọ.

Mara:

Njirimara nkọwa nke onye ọrụ dị naanị na ọnọdụ zuru oke.

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Onyonyo 8.

Njikwa usoro

Enwere ọnọdụ ebe TX MAC adịghị njikere ịnata data sitere na mgbagha onye ọrụ dị ka n'oge usoro nhazigharị njikọ ma ọ bụ mgbe enweghị data dị maka nnyefe site na njirimara onye ọrụ. Iji zere mfu data n'ihi ọnọdụ ndị a, IP na-eji akara tx_avs_ready iji chịkwaa ndapụta data sitere na mgbagha onye ọrụ. IP na-edozi mgbaama mgbe ọnọdụ ndị a mere:
Mgbe ekwuputara tx_avs_startofpacket, tx_avs_ready na-atọ ụtọ maka otu okirikiri elekere.
Mgbe ekwuputara tx_avs_endofpacket, tx_avs_ready bụ deasserted maka otu elekere.
Mgbe CW ọ bụla jikọtara ọnụ na-ekwuputa tx_avs_ready bụ deasserted maka okirikiri elekere abụọ.
Mgbe ntinye akara ntinye RS-FEC na-eme na interface PCS omenala, tx_avs_ready bụ deasserted maka okirikiri elekere anọ.
17 ọ bụla 4 Ethernet isi okirikiri elekere na PAM33 modulation mode na ọ bụla XNUMX Ethernet isi okirikiri elekere na NRZ modulation mode. Emebere tx_avs_ready maka otu okirikiri elekere.
Mgbe mgbagha onye ọrụ deassert tx_avs_valid n'oge enweghị nnyefe data.

Eserese oge ndị a bụ examples nke TX MAC nkwụnye na-eji tx_avs_ready maka njikwa ọsọ data.

Njikwa ngagharị na tx_avs_valid deassertion na START/END ejikọtara CW

tx_core_klout

tx_avs_valid tx_avs_data

D1 D2 D3

Deassert mgbama bara uru

NKX5

tx_avs_ready tx_avs_startofpacket

Deassert mgbama dị njikere maka okirikiri abụọ iji fanye END-STRT CW

tx_avs_endofpacket

usrif_data

D1 D2 D3

CW_data

DN Ọgwụgwụ STRT D0 D1 D2 D3 EMPTY D4

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Onyonyo 9.

Njikwa usoro na ntinye akara ntinye
tx_core_klout tx_avs_valid

tx_avs_data tx_avs_dị njikere

DN-5 DN-4 DN-3 DN-2 DN-1

DNA+1

01234

tx_avs_startofpacket tx_avs_endofpacket

usrif_data CW_data CRC_data MII_data

DN-1 DN DN DN DN DN DN+1 DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 DN-XNUMX DN

i_sl_tx_mii_valid

i_sl_tx_mii_d[63:0]

DNA-1

DNA+1

i_sl_tx_mii_c[7:0]

0x0

i_sl_tx_mii_am

01234

i_sl_tx_mii_am_pre3

01234

Onyonyo 10.

Njikwa usoro na START/END Ejikọtara CW na ntinye nrịbama

tx_core_klout tx_avs_valid

tx_avs_data

DN-5 DN-4 DN-3 DN-2 DN-1

tx_avs_dị njikere

012 345 6

tx_avs_startofpacket

tx_avs_endofpacket

usrif_data

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 Ọgwụgwụ STRT D0

CW_data

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 Ọgwụgwụ STRT D0

CRC_data

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 Ọgwụgwụ STRT D0

MII_data

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 Ọgwụgwụ STRT D0

i_sl_tx_mii_valid

i_sl_tx_mii_d[63:0]

DNA-1

Nkwụsị STRT D0

i_sl_tx_mii_c[7:0]

0x0

i_sl_tx_mii_am i_sl_tx_mii_am_pre3

01234

4.1.2. Ntinye Okwu njikwa (CW).
F-Tile Serial Lite IV Intel FPGA IP na-ewuli CW dabere na akara ntinye sitere na mgbagha onye ọrụ. Ndị CW na-egosi oke ngwungwu, ozi ọkwa ọkwa ma ọ bụ data onye ọrụ na ngọngọ PCS wee nweta ha na koodu njikwa XGMII.
Tebụlụ na-esonụ na-egosi nkọwa nke CW ndị akwadoro:

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Tebụl 11.
Malite Nkwụsị Ndozi

Nkọwa nke CW akwadoro

Ọnụọgụ nke Okwu (1 okwu

= 64 bit)

EMPTY_CYC

IDLE

Mba

DATA

Na-gbalaga

Nkọwa
Mmalite nke nchapụta data. Ọgwụgwụ nke nchapụta data. Okwu njikwa (CW) maka nhazi RX. okirikiri efu na mbufe data. IDLE (esighị na band). Ibu ibu.

Tebụl 12. Nkọwa Ubi CW
Ubi RSVD num_valid_bytes_eob
EMPTY eop sop seop align CRC32 usr

Nkọwa
Ogige echekwara. Enwere ike iji maka ndọtị n'ọdịnihu. Ejikọtara ya na 0.
Ọnụọgụ bytes dị irè na okwu ikpeazụ (64-bit). Nke a bụ uru 3bit. 3'b000: 8 bytes · 3'b001: 1 byte · 3'b010: 2 bytes · 3'b011: 3 bytes · 3'b100: 4 bytes · 3'b101: 5 bytes · 3'b110: 6 bytes · 3'b111:7 bytes
Ọnụọgụ nke okwu na-adịghị mma na njedebe nke nwawa.
Na-egosi interface nkwanye ugwu RX Avalon iji kwupụta akara ngwụcha nke ngwugwu.
Na-egosi interface nkwanye ugwu RX Avalon iji kwupụta akara mmalite nke ngwugwu.
Na-egosi interface nkwanye ugwu RX Avalon iji kwupụta mmalite nke ngwugwu na ngwugwu njedebe n'otu okirikiri ahụ.
Lelee nhazi RX.
Ụkpụrụ nke CRC agbakọrọ.
Na-egosi na okwu njikwa (CW) nwere ozi akọwapụtara nke onye ọrụ.

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4.1.2.1. Mmalite nke mgbawa CW

Ọgụgụ 11. Ụdị CW nke mmalite mmalite

Malite

63:56

RSVD

55:48

RSVD

47:40

RSVD

data

39:32 31:24

RSVD RSVD

23:16

sop usr align = 0 seop

15:8

ọwa

7:0

'hFB(START)

njikwa 7:0

Tebụl 13.

Na ọnọdụ zuru oke, ị nwere ike itinye START CW site n'ịkwado akara ngosi tx_avs_startofpacket. Mgbe ị kwuputara naanị tx_avs_startofpacket mgbama, a na-edozi bit sop. Mgbe ị kwuputara ma tx_avs_startofpacket yana akara tx_avs_endofpacket, edobere seop bit.

Malite ụkpụrụ ubi CW
Ubi sop/seop
usr (8)
dozie

Uru

Dabere na tx_is_usr_cmd mgbama:

1: Mgbe tx_is_usr_cmd = 1

0: Mgbe tx_is_usr_cmd = 0

Na Basic mode, Mac na-eziga a START CW mgbe nrụpụta na deasserted. Ọ bụrụ na enweghị data dị, MAC na-aga n'ihu na-eziga EMPTY_CYC jikọtara ya na END na START CW ruo mgbe ịmalitere izipu data.

4.1.2.2. Ọgwụgwụ nke mgbawa CW

Ọgụgụ 12. Ọkpụkpọ CW nke njedebe

N'ikpeazụ

63:56

'hFD

55:48

CRC32[31:24]

47:40

CRC32[23:16]

data 39:32 31:24

CRC32[15:8] CRC32[7:0]

23:16 eop=1 RSVD RSVD RSVD

RSVD

15:8

RSVD

EFU

7:0

RSVD

num_valid_bytes_eob

njikwa

7:0

(8) A na-akwado nke a naanị na ọnọdụ zuru oke.
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Tebụl 14.

MAC na-etinye END CW mgbe tx_avs_endofpacket kwadoro. Ọgwụgwụ CW nwere ọnụọgụ bytes ziri ezi na okwu data ikpeazụ yana ozi CRC.

Uru CRC bụ 32-bit CRC nsonaazụ maka data dị n'etiti START CW na okwu data tupu ọgwụgwụ CW.

Tebụlụ na-esonụ na-egosi ụkpụrụ nke ubi na END CW.

Ọgwụgwụ CW Ubi Ubi
Ubi eop CRC32 num_valid_bytes_eob

Uru 1
CRC32 gbakọrọ ọnụ ahịa. Ọnụọgụ bytes dị irè n'okwu data ikpeazụ.

4.1.2.3. Ejikọtara ọnụ CW

Ọgụgụ 13. Nhazi CW jikọtara ọnụ

Kpọkọtanụ CW Mmakọ na Mmalite/Ọgwụgwụ

64+8bits XGMII interface

Malite

63:56

RSVD

55:48

RSVD

47:40

RSVD

data

39:32 31:24

RSVD RSVD

23:16 eop=0 sop=0 usr=0 align=1 seop=0

15:8

RSVD

7:0

'hFB

njikwa 7:0

64+8bits XGMII interface

N'ikpeazụ

63:56

'hFD

55:48

RSVD

47:40

RSVD

data

39:32 31:24

RSVD RSVD

23:16 eop=0 RSVD RSVD RSVD

RSVD

15:8

RSVD

7:0

RSVD

njikwa 7:0

ALIGN CW bụ CW jikọtara ya na START/END ma ọ bụ END/START CWs. Ị nwere ike ịtinye ALIGN jikọtara CW site n'ịkwado akara tx_link_reinit, tọọ counter Period counter, ma ọ bụ malite nrụpụta. Mgbe etinyere ALIGN paired CW, a na-edobe oghere n'ahịrị ka ọ bụrụ 1 iji malite ngọngọ nkwụnye nnata ka ịlele nhazi data n'ofe ụzọ niile.

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Tebụl 15.

KWESỊRỊ CW Ubi Ubi
Nhazi mpaghara
nke uwa seop

Uru 1 0 0 0 0

4.1.2.4. okirikiri CW efu

Ọgụgụ 14. Ọkpụkpọ CW efu

EMPTY_CYC Jikọọ na END/START

64+8bits XGMII interface

N'ikpeazụ

63:56

'hFD

55:48

RSVD

47:40

RSVD

data

39:32 31:24

RSVD RSVD

23:16 eop=0 RSVD RSVD RSVD

RSVD

15:8

RSVD

7:0

RSVD

njikwa 7:0

64+8bits XGMII interface

Malite

63:56

RSVD

55:48

RSVD

47:40

RSVD

data

39:32 31:24

RSVD RSVD

23:16

sop=0 usr=0 align=0 seop=0

15:8

RSVD

7:0

'hFB

njikwa 7:0

Tebụl 16.

Mgbe ị desasịrị tx_avs_valid maka okirikiri elekere abụọ n'oge mgbawa, MAC na-etinye EMPTY_CYC CW jikọtara ya na END/START CW. Ị nwere ike iji CW a mgbe enweghị data dị maka nnyefe nwa oge.

Mgbe ị deassert tx_avs_valid maka otu okirikiri, IP deassert tx_avs_valid ugboro abụọ oge nke tx_avs_valid deassertion iji mepụta otu ụzọ END/START CW.

EMPTY_CYC CW Uru Ubi
Nhazi mpaghara
eop

Uru 0 0

gara n'ihu…

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Ubi sop usr seop

Uru 0 0 0

4.1.2.5. CW na-abaghị uru

Ọgụgụ 15. Ụdị CW na-abaghị uru

IDLE CW

63:56

'h07

55:48

'h07

47:40

'h07

data

39:32 31:24

07h07

23:16

'h07

15:8

'h07

7:0

'h07

njikwa 7:0

MAC tinye IDLE CW mgbe enweghị nnyefe. N'ime oge a, mgbama tx_avs_valid dị ala.
Ị nwere ike iji IDLE CW mgbe nfefe kwụsịrị ma ọ bụ na nnyefe ahụ nọ n'ọnọdụ efu.

4.1.2.6. Okwu data

Okwu data bụ ugwo nke ngwugwu. Ihe njikwa XGMII ka edobere na 0 n'ụdị okwu data.

Ọgụgụ 16. Usoro Okwu Data

64+8 bit XGMII Interface

Okwu DATA

63:56

data onye ọrụ 7

55:48

data onye ọrụ 6

47:40

data onye ọrụ 5

data

39:32 31:24

data onye ọrụ 4 data onye ọrụ 3

23:16

data onye ọrụ 2

15:8

data onye ọrụ 1

7:0

data onye ọrụ 0

njikwa 7:0

4.1.3. TX CRC
Ị nwere ike mee ka ngọngọ TX CRC jiri paramita Kwado CRC na IP Parameter Editor. A na-akwado atụmatụ a na ma Basic na Full ụdịdị.

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MAC na-agbakwunye uru CRC na END CW site n'ịkwado akara tx_avs_endofpacket. Na ọnọdụ BASIC, naanị ALIGN CW jikọtara ya na END CW nwere mpaghara CRC bara uru.
Ihe mgbochi TX CRC nwere ntinye okwu njikwa TX yana ngọngọ TX MII. Ihe mgbochi TX CRC na-agbakọ uru CRC maka uru 64-bit kwa okirikiri data malite na START CW ruo na njedebe CW.
Ị nwere ike kwupụta akara ngosi crc_error_inject ka ọ bụrụ na-ama ụma mebie data n'otu ụzọ iji mepụta njehie CRC.

4.1.4. TX MII koodu

Ihe ngbanwe TX MII na-ejikwa nnyefe ngwugwu site na MAC gaa na TX PCS.

Ọnụọgụ na-esonụ na-egosi ụkpụrụ data na ụgbọ ala 8-bit MII na PAM4 modulation mode. Mmalite na Ọgwụgwụ CW na-apụta otu ugboro n'ụzọ MII abụọ ọ bụla.

Ọgụgụ 17. PAM4 Modulation Mode MII Data Pattern

MGBE 1

MGBE 2

MGBE 3

MGBE 4

MGBE 5

SOP_CW

DATA_1

DATA_9 DATA_17

IDLE

DATA_DUMMY SOP_CW
DATA_DUMMY

DATA_2 DATA_3 DATA_4

DATA_10 DATA_11 DATA_12

DATA_18 DATA_19 DATA_20

EOP_CW IDLE
EOP_CW

SOP_CW

DATA_5 DATA_13 DATA_21

IDLE

DATA_DUMMY DATA_6 DATA_14 DATA_22 EOP_CW

SOP_CW DATA_DUMMY

DATA_7 DATA_8

DATA_15 DATA_16

DATA_23 DATA_24

IDLE EOP_CW

Ọnụọgụ na-esonụ na-egosi ụkpụrụ data na ụgbọ ala MII 8-bit na ọnọdụ NRZ. Mmalite na Ọgwụgwụ CW na-apụta n'ụzọ MII ọ bụla.

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Ọgụgụ 18. NRZ Modulation Mode MII Data Pattern

MGBE 1

MGBE 2

MGBE 3

SOP_CW

DATA_1

DATA_9

SOP_CW

DATA_2 DATA_10

SOP_CW SOP_CW

DATA_3 DATA_4

DATA_11 DATA_12

SOP_CW

DATA_5 DATA_13

SOP_CW

DATA_6 DATA_14

SOP_CW

DATA_7 DATA_15

SOP_CW

DATA_8 DATA_16

CYCLE 4 DATA_17 DATA_18 DATA_19 DATA_20 DATA_21 DATA_22 DATA_23 DATA_24

CYCLE 5 EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW

4.1.5. TX PCS na PMA
F-Tile Serial Lite IV Intel FPGA IP na-ahazi transceiver F-tile na ọnọdụ Ethernet PCS.

4.2. Ụzọ data RX
Ụzọ data RX nwere ihe ndị a: · ngọngọ PMA · ngọngọ PCS · MII decoder · CRC · Deskew ngọngọ · njikwa mkpochapụ okwu

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Ọgụgụ 19. RX Datapath

Iji mgbagha onye ọrụ Avalon Streaming Interface
RX MAC
Mwepụ Okwu jikwaa
Deskew

CRC

MII Decoder

PCS Custom Interface MII
PCS na PMA

Oghere Usoro RX Site na Ngwaọrụ FPGA ndị ọzọ
4.2.1. RX PCS na PMA
F-Tile Serial Lite IV Intel FPGA IP na-ahazi transceiver F-tile na ọnọdụ PCS Ethernet.
4.2.2. Ihe nrụpụta RX MII
Ihe mgbochi a na-achọpụta ma ọ bụrụ na data mbata nwere okwu njikwa na akara nhazi. RX MII decoder na-ewepụta data n'ụdị nke 1-bit ziri ezi, akara akara 1-bit, akara njikwa 1bit, yana data 64-bit n'otu ụzọ.
4.2.3. Ọnụ ego nke RX CRC
Ị nwere ike mee ka ngọngọ TX CRC jiri paramita Kwado CRC na IP Parameter Editor. A na-akwado atụmatụ a na ma Basic na Full ụdịdị. Ihe mgbochi RX CRC nwere Mwepụ Okwu Njikwa RX yana mgbochi RX MII Decoder. IP na-ekwupụta akara rx_crc_error mgbe njehie CRC mere.

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IP deassert rx_crc_error na mgbawa ọhụrụ ọ bụla. Ọ bụ mmepụta na mgbagha onye ọrụ maka njikwa njehie mgbagha onye ọrụ.
4.2.4. RX Deskew
Ihe mgbochi RX deskew na-achọpụta akara nrịbama maka ụzọ ọ bụla wee megharịa data ahụ tupu iziga ya na ngọngọ mwepụ RX CW.
Ị nwere ike ịhọrọ ịhapụ isi IP ka ọ kwado data maka ụzọ ọ bụla na-akpaghị aka mgbe njehie nrụnye na-eme site na ịtọ ntọala Kwado Ndozi Nchekwa onwe na IP Parameter Editor. Ọ bụrụ na ị gbanyụọ njirimara nhazigharị akpaaka, isi IP na-ekwupụta akara rx_error iji gosi njehie nhazi. Ị ga-ekwupụtarịrị rx_link_reinit iji bido usoro nhazi okporo ụzọ mgbe mperi nhazi okporo ụzọ mere.
RX deskew na-achọpụta akara nzizi dabere na igwe steeti. Eserese na-esonụ na-egosi steeti ndị dị na RX deskew ngọngọ.

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Onyonyo 20.

RX Deskew Lane Alignment State Machine nwere eserese akpaaka enyere aka
Malite

IDLE

Tọgharia = 1 ee mba

PCS niile

mba

ụzọ dị njikere?

Chere

Ihe nrịbama mmekọrịta ọ bụla
achọpụtara?
ee
Bido

mba
ee Oge agwụla?

ee
Ndozigharị efuola?
enweghị ngwụcha

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Onyonyo 21.

RX Deskew Lane Alignment State Machine nwere Chart nwere nkwarụ nwere nkwarụ akpaaka
Malite

IDLE

Tọgharia = 1 ee mba

PCS niile

mba

ụzọ dị njikere?

ee
rx_link_reinit = 1
ọnweghị ERROR

mba ee Oge agwụla?

Chere
enweghị ihe nrịbama mmekọrịta niile
achọpụtara?
ee ALIGN

ee
Ndozigharị efuola?
mba
Ọgwụgwụ
1. Usoro nhazi na-amalite na steeti IDLE. Ngwongwo a na-aga na steeti WAIT mgbe ụzọ PCS niile adịla njikere ma rx_link_reinit esirila nri.
2. Na steeti echere, ihe mgbochi na-enyocha akara niile achọpụtara na-ekwupụta n'ime otu okirikiri. Ọ bụrụ na ọnọdụ a bụ eziokwu, ngọngọ na-aga na steeti ALIGNED.
3. Mgbe ngọngọ ahụ dị na steeti ALIGNED, ọ na-egosi na a na-ejikọta okporo ụzọ. Na steeti a, ngọngọ na-aga n'ihu na-enyocha nhazi n'ụzọ wee lelee ma akara niile dị n'ime otu okirikiri. Ọ bụrụ na opekata mpe otu nrịbama anọghị n'otu okirikiri ma edobere paramita Enable Auto Alignment, ngọngọ na-aga na

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Ọnọdụ IDLE ka ịmalitegharịa usoro nhazi ahụ. Ọ bụrụ na edobeghi nhazi akpaaka ma ọ dịkarịa ala otu akara adịghị n'otu okirikiri ahụ, ngọngọ ahụ na-aga na steeti ERROR wee chere mgbagha onye ọrụ iji kwupụta akara rx_link_reinit iji malite usoro nhazi ụzọ.

Ọgụgụ 22. Ndozigharị okporo ụzọ na Kwado Ndozi akpaaka rx_core_clk

rx_link_up

rx_link_reinit

na_akara_niile

Obodo Deskew

ALGNED

IDLE

Chere

ALGNED

AUTO_ALIGN = 1

Ọgụgụ 23. Ndozigharị okporo ụzọ na Kwado Ndozi akpaaka rx_core_clk

rx_link_up

rx_link_reinit

na_akara_niile

Obodo Deskew

ALGNED

ERROR

IDLE

Chere

ALGNED

AUTO_ALIGN = 0
4.2.5. Mwepụ RX CW
Nke a ngọngọ decodes ndị CWs na-eziga data na onye ọrụ mgbagha site na iji Avalon gụgharia interface mgbe mwepụ nke CWs.
Mgbe enweghị data ziri ezi dị, ihe mgbochi RX CW na-ewepụ akara ngosi rx_avs_valid.
Na ọnọdụ zuru oke, ọ bụrụ na edobere bit onye ọrụ, ngọngọ a na-ekwupụta akara rx_is_usr_cmd yana data dị na okirikiri elekere mbụ ka ejiri ya dị ka ozi akọwapụtara ma ọ bụ iwu.
Mgbe rx_avs_ready deasserts na rx_avs_valid kwusiri ike, ihe mgbochi mwepu RX CW na-ebute ọnọdụ njehie na mgbagha onye ọrụ.
Ihe akara ngosi Avalon metụtara ngọngọ a bụ: · rx_avs_startofpacket · rx_avs_endofpacket · rx_avs_channel · rx_avs_empty · rx_avs_data

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· rx_avs_valid
rx_num_valid_bytes_eob
rx_is_usr_cmd (naanị dị na ọnọdụ zuru oke)
4.3. F-Tile Serial Lite IV Intel FPGA IP Clock Architecture
F-Tile Serial Lite IV Intel FPGA IP nwere ntinye elekere anọ nke na-ewepụta elekere gaa na ngọngọ dị iche iche: · Elekere ntụgharị ntụgharị (xcvr_ref_clk) – Elekere ntinye sitere na elekere mpụga.
ibe ma ọ bụ oscillators nke na-ewepụta elekere maka TX MAC, RX MAC, na TX na RX PCS omenala. Rụtụ aka na Parameters maka oke ugboro akwadoro. · TX isi elekere (tx_core_clk) – A na-enweta elekere a site na transceiver PLL maka TX MAC. Elekere a bụkwa elekere mmepụta sitere na transceiver F-tile iji jikọọ na mgbagha onye ọrụ TX. · RX isi elekere (rx_core_clk) – A na-enweta elekere a site na transceiver PLL maka RX deskew FIFO na RX MAC. Elekere a bụkwa elekere mmepụta sitere na transceiver F-tile iji jikọọ na mgbagha onye ọrụ RX. Elekere maka transceiver reconfiguration interface (reconfig_clk) – ntinye elekere sitere na sekit elekere mpụga ma ọ bụ oscillators nke na-ewepụta clocks maka F-tile transceiver reconfiguration interface na TX na RX datapaths. Ugboro elekere bụ 100 ruo 162 MHz.
Eserese ngọngọ na-esote na-egosi ngalaba elekere F-Tile Serial Lite IV Intel FPGA IP yana njikọ dị n'ime IP.

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Onyonyo 24.

F-Tile Serial Lite IV Intel FPGA IP Clock Architecture

Oscillator

FPGA1
F-Tile Serial Lite IV Intel FPGA IP Transceiver Reconfiguration Interface elekere
(reconfig_clk)

tx_core_clkout (jikọọ na mgbagha onye ọrụ)

tx_core_clk= clk_pll_div64[mid_ch]

FPGA2

F-Tile Serial Lite IV Intel FPGA IP

Ntụgharị ihu igwe ntụgharị transceiver

(reconfig_clk)

Oscillator

rx_core_clk= clk_pll_div64[mid_ch]

rx_core_clkout (jikọọ na mgbagha onye ọrụ)

clk_pll_div64[mid_ch] clk_pll_div64[n-1:0]

Avalon Streaming Interface TX Data
TX MAC

serial_link[n-1:0]

Deskew

FIFO

Avalon Streaming Interface RX Data RX MAC

Avalon Streaming Interface RX Data
RX MAC

Ọnọdụ FIFO

rx_core_clkout (jikọọ na mgbagha onye ọrụ)

rx_core_clk= clk_pll_div64[mid_ch]

PCS omenala

serial_link[n-1:0]

TX MAC

Avalon Streaming Interface TX Data

tx_core_clk= clk_pll_div64[mid_ch]

tx_core_clkout (jikọọ na mgbagha onye ọrụ)

Ihe ntụgharị ntụgharị ntụgharị (xcvr_ref_clk)
Ihe ntụgharị ntụgharị ntụgharị (xcvr_ref_clk)

Oscillator*

Akụkọ mgbe ochie

Ngwa FPGA
ngalaba elekere TX isi
ngalaba elekere RX isi
Ngalaba elekere ntụgharị transceiver mgbama data ngwaọrụ mpụga

4.4. Tọgharịa na njikọ mmalite
MAC, F-tile Hard IP na ihe nrụgharị nwere akara nrụpụta dị iche iche: · TX na RX MAC blocks na-eji tx_core_rst_n na rx_core_rst_n reset signals. tx_pcs_fec_phy_reset_n na rx_pcs_fec_phy_reset_n nrụpụta akara ngosi
onye njikwa nrụpụta nro dị nro iji tọgharịa F-tile Hard IP. · ngọngọ nhazigharị na-eji mgbama nrụpụta reconfig_reset.

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Ọgụgụ 25. Tọgharia ihe owuwu
Avalon Streaming Interface TX Data
MAC
Avalon Streaming SYNC Interface RX Data

FPGA F-tile Serial Lite IV Intel FPGA IP

tx_mii rx_mii
phy_ehip_dị njikere phy_rx_pcs_ready

F-tile Hard IP

TX Oghere Usoro Data RX Oghere Usoro Data

tx_core_rstn rx_core_rstn tx_pcs_fec_phy_reset_n rx_pcs_fec_phy_reset_n reconfig_reset

Tọgharia mgbagha
Ozi metụtara · Tọgharia ntuziaka na ibe 51 · F-Tile Serial Lite IV Intel FPGA IP Design Ex.ample ntuziaka onye ọrụ
4.4.1. Usoro nrụpụta na mmalite TX
Usoro nrụpụta TX maka F-Tile Serial Lite IV Intel FPGA IP bụ nke a: 1. Tinye tx_pcs_fec_phy_reset_n, tx_core_rst_n, na reconfig_reset
n'otu oge iji tọgharịa F-tile hard IP, MAC, na reconfiguration blocks. Hapụ tx_pcs_fec_phy_reset_n na nhazigharị nhazi ka ichere tx_reset_ack iji hụ na emezigharịrị ihe mgbochi ahụ nke ọma. 2. IP wee kwupụta phy_tx_lanes_stable, tx_pll_locked, na phy_ehip_ready signals ka ewepụtara tx_pcs_fec_phy_reset_n reset, iji gosi na TX PHY dị njikere maka mbufe. 3. The tx_core_rst_n mgbaàmà deasserts mgbe phy_ehip_ready mgbaàmà na-aga elu. 4. IP na-amalite na-ebusa IDLE odide na MII interface ozugbo MAC bụ nke nrụpụta. Ọ nweghị ihe achọrọ maka nhazi ụzọ TX na skewing n'ihi na ụzọ niile na-eji otu elekere. 5. Mgbe ị na-ebufe mkpụrụedemede IDLE, MAC na-ekwupụta akara tx_link_up. 6. MAC wee malite ịnyefe ALIGN jikọtara ya na START/END ma ọ bụ END/START CW n'oge a kapịrị ọnụ iji malite usoro nhazi uzo nke nnata ejikọrọ.

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Onyonyo 26.

Ntọgharị TX na mmalite oge eserese
reconfig_sl_clk

reconfig_clk

tx_core_rst_n

tx_pcs_fec_phy_reset_n 1

reconfig_reset

reconfig_sl_reset

tx_reset_ack

tx_pll _kpọchiri

phy_tx_lanes_stable

phy_ehip_dị njikere

tx_li nk_up

7
5 6 8

4.4.2. Usoro nrụpụta na mmalite RX
Usoro nrụpụta RX maka F-Tile Serial Lite IV Intel FPGA IP bụ nke a:
1. Gwa rx_pcs_fec_phy_reset_n, rx_core_rst_n, na reconfig_reset n'out oge iji tọgharịa F-tile hard IP, MAC, na reconfiguration blocks. Hapụ rx_pcs_fec_phy_reset_n na nhazigharị nhazi ka ichere rx_reset_ack iji hụ na emezigharịrị ihe mgbochi ahụ nke ọma.
2. IP wee kwupụta akara ngosi phy_rx_pcs_ready mgbe emechara nrụpụta PCS omenala, iji gosi RX PHY dị njikere maka mbufe.
3. The rx_core_rst_n mgbaàmà deasserts mgbe phy_rx_pcs_ready mgbaàmà na-aga elu.
4. IP na-amalite usoro nhazi okporo ụzọ mgbe emechara nrụpụta RX MAC yana mgbe ọ natara ALIGN jikọtara ya na START/END ma ọ bụ END/START CW.
5. Ihe mgbochi RX deskew na-ekwupụta akara ngosi rx_link_up ozugbo nhazi maka ụzọ niile zuru ezu.
6. IP wee kwupụta akara ngosi rx_link_up na mgbagha onye ọrụ iji gosi na njikọ RX dị njikere ịmalite nnabata data.

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Ọgụgụ 27. Ntọgharị RX na mmalite oge eserese
reconfig_sl_clk

reconfig_clk

rx_core_rst_n

rx_pcs_fec_phy_reset_n 1

reconfig_reset

reconfig_sl_reset

rx_reset_ack

rx_cdr_lock

rx_block_lock

rx_pcs_dị njikere

rx_link_up

3 3 3 2

4 5 5

6 7

4.5. Ọnụego Njikọ na Mgbakọ arụmọrụ bandwit

F-Tile Serial Lite IV Intel FPGA IP ngụkọta bandwidth arụmọrụ dị n'okpuru:

Ọrụ bandwit = raw_rate * 64/66 * (burst_size – burst_size_ovhd)/burst_size * [align_marker_period / (align_marker_period + align_marker_width)] * [(srl4_align_period - 2) / srl4_align

Tebụl 17. Nkọwapụta arụmọrụ bandwit dị iche iche

Na-agbanwe agbanwe

Nkọwa

raw_rate burst_size

Nke a bụ ọnụọgụ bit nwetara site na interface serial. raw_rate = obosara SERDES * ugboro elekere transceiver Example: raw_rate = 64 * 402.812500 Gbps = 25.78 Gbps
Uru nke nha mgbawa. Iji gbakọọ nkezi bandwit arụmọrụ, jiri uru nha nha gbawara nkịtị. Maka ọnụego kacha, jiri oke nha nha nwawa.

gbawara_size_ovhd

Nha mgbawa n'elu uru.
Na ọnọdụ zuru oke, uru burst_size_ovhd na-ezo aka na START na END jikọtara ọnụ CW.
Na Basic mode, enweghị burst_size_ovhd n'ihi na enweghị START na END jikọtara CW.

align_marker_period

Uru nke oge ebe etinyere nrịbama nhazi. Uru ya bụ okirikiri elekere 81920 maka mkpokọta yana 1280 maka ịme anwansị ngwa ngwa. A na-enweta uru a site na mgbagha siri ike PCS.

align_marker_width srl4_align_period

Ọnụọgụ okirikiri elekere ebe akara nrịbama nzizi ziri ezi na-adị elu.
Ọnụọgụ okirikiri elekere n'etiti akara nrịbama abụọ. Ị nwere ike ịtọ uru a site na iji paramita Oge Nhazi na IP Parameter Editor.

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Ngụkọ ọnụ ọgụgụ njikọ dị n'okpuru: Ọnụego dị irè = arụmọrụ bandwidth * raw_rate Ị nwere ike nweta oge elekere onye ọrụ kachasị na nha na-esonụ. Mgbakọ oge elekere kachasị nke onye ọrụ na-ewere nkwanye data na-aga n'ihu na enweghị okirikiri IDLE na-apụta n'echiche onye ọrụ. Ọnụego ya dị mkpa mgbe ị na-emepụta echiche onye ọrụ FIFO iji zere oke FIFO. Ugboro elekere onye ọrụ kachasị = ọnụọgụ dị irè / 64

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5. Nkeji

Tebụl 18. F-Tile Serial Lite IV Intel FPGA IP Parameter Description

Oke

Uru

Ọdabara

Nkọwa

Nhọrọ imewe izugbe

Ụdị mgbanwe PMA

PAM4 · NRZ

PAM4

Họrọ ụdị ngbanwe PCS.

Ụdị PMA

· FHT · FGT

FGT

Na-ahọpụta ụdị transceiver.

Ọnụego data PMA

Maka ụdị PAM4:
- Ụdị transceiver FGT: 20 Gbps 58 Gbps
- Ụdị transceiver FHT: 56.1 Gbps, 58 Gbps, 116 Gbps
Maka ụdị NRZ:
- Ụdị transceiver FGT: 10 Gbps 28.05 Gbps
- Ụdị transceiver FHT: 28.05 Gbps, 58 Gbps

56.1 (FGT/FHT PAM4)
28.05 Gbps (FGT/FHT NRZ)

Na-akọwapụta ọnụego data dị irè na mmepụta nke transceiver na-agụnye nnyefe na ego ndị ọzọ. A na-agbakọ uru site na IP site n'ịchịkọta ihe ruru 1 decimal na nkeji Gbps.

Ụdị PMA

· Duplex · Tx · Rx

Duplex

Maka ụdị transceiver FHT, ntụzịaka akwadoro bụ naanị duplex. Maka ụdị transceiver FGT, ntụzịaka akwadoro bụ Duplex, Tx, na Rx.

Ọnụọgụ nke PMA

Maka ụdị PAM4:

uzo

- 1 ruo 12

Maka ụdị NRZ:

- 1 ruo 16

Họrọ ọnụọgụ nke ụzọ. Maka imewe simplex, ọnụọgụ ụzọ akwadoro bụ 1.

Ugboro elekere ntụaka PLL

· Maka ụdị transceiver FHT: 156.25 MHz
Maka ụdị transceiver FGT: 27.5 MHz 379.84375 MHz, dabere na ọnụego data transceiver ahọpụtara.

· Maka ụdị transceiver FHT: 156.25 MHz
· Maka ụdị transceiver FGT: 165 MHz

Na-akọwapụta ugboro elekere nrụtụ aka nke transceiver.

Sistemụ PLL

—

elekere ntụaka

ugboro ugboro

170 MHz

Ọ dị naanị maka ụdị transceiver FHT. Na-akọwapụta elekere ntụaka Sistemu PLL na a ga-eji ya dị ka ntinye nke F-Tile Reference na Sistemu PLL Clocks Intel FPGA IP iji mepụta elekere Sistemu PLL.

Ugboro PLL sistemu
Oge Nhazi

- 128 65536

Kwado RS-FEC

Kwado

876.5625 MHz 128 Kwado

Na-akọwapụta ugboro elekere Sistemu PLL.
Na-akọwapụta oge nrịbama nhazi. Ọnụ ahịa ahụ ga-abụrịrị x2. Gbanye ka ị mee ka njirimara RS-FEC dị.
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Oke

Uru

Ọdabara

Nkọwa

Gbanyụọ

Maka ọnọdụ mgbanwe PAM4 PCS, RS-FEC na-enyere aka mgbe niile.

Interface onye ọrụ

Ụdị gụgharia

· zuru ezu · BASIC

Juputara

Họrọ nkwanye data maka IP.

Zuru ezu: Ụdị a na-eziga usoro mmalite nke ngwugwu na njedebe nke ngwugwu n'ime etiti.

Ihe ndabere: Nke a bụ ụdị nkwanye ugwu dị ọcha ebe ezigara data na-enweghị mmalite nke ngwugwu, ihe efu, na ngwugwu njedebe iji mụbaa bandwit.

Kwado CRC

Kwado Gbanyụọ

Gbanyụọ

Gbanye iji mee ka nchọpụta na mezie njehie CRC nwee ike.

Kwado nhazi akpaaka

Kwado Gbanyụọ

Gbanyụọ

Gbanwuo iji mee ka atụmatụ nhazi okporo ụzọ akpaka.

Kwado ebe njedebe nkwụsị

Kwado Gbanyụọ

Gbanyụọ

Mgbe ONYE, F-Tile Serial Lite IV Intel FPGA IP gụnyere ihe agbakwunyere Debug Endpoint nke na-ejikọ n'ime na interface Avalon ebe nchekwa. IP nwere ike ịrụ ụfọdụ ule na ọrụ debug site na JTAG iji Sistemu Console. Ọnụ ahịa ndabara agbanyụrụ.

Ngwakọta Simplex (Ntọala oke a dị naanị mgbe ịhọrọ imewe FGT dual simplex.)

RSFEC nyeere na Serial Lite IV Simplex IP nke ọzọ etinyere n'otu ọwa FGT.

Kwado Gbanyụọ

Gbanyụọ

Gbanwuo nhọrọ a ma ọ bụrụ na ịchọrọ ngwakọta nke nhazi na RS-FEC nyere ma nwee nkwarụ maka F-Tile Serial Lite IV Intel FPGA IP n'ụdị dual simplex maka ọnọdụ transceiver NRZ, ebe TX na RX na-etinye n'otu FGT. ọwa (s).

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6. F-Tile Serial Lite IV Intel FPGA IP Interface Signals

6.1. Mgbama elekere

Tebụl 19. mgbama elekere

Aha

Ụzọ obosara

Nkọwa

tx_core_klout

Mpụta TX isi elekere maka TX omenala PCS interface, TX MAC na onye ọrụ mgbagha n'ime

Ọnụ ego nke TX.

Emepụtara elekere a site na ngọngọ PCS omenala.

rx_core_klout

Mpụta RX isi elekere maka RX omenala PCS interface, RX deskew FIFO, RX MAC

na mgbagha onye ọrụ na ụzọ data RX.

Emepụtara elekere a site na ngọngọ PCS omenala.

xcvr_ref_clk
reconfig_clk reconfig_sl_clk

Ntinye elekere ntụgharị ntụgharị.

Mgbe atọrọ ụdị transceiver na FGT, jikọọ elekere a na mgbama mmepụta (out_refclk_fgt_0) nke F-Tile Reference na Sistemu PLL Clocks Intel FPGA IP. Mgbe atọrọ ụdị transceiver na FHT, jikọọ

elekere a na mgbama mmepụta (out_fht_cmmpll_clk_0) nke F-Tile Reference na Sistemu PLL Clocks Intel FPGA IP.

Rụtụ aka na Parameters maka oke ugboro akwadoro.

Elekere ntinye ntinye maka interface nhazigharị transceiver.

Ugboro elekere bụ 100 ruo 162 MHz.

Jikọọ mgbaama elekere ntinye a na sekit elekere mpụga ma ọ bụ oscillators.

Elekere ntinye ntinye maka interface nhazigharị transceiver.

Ugboro elekere bụ 100 ruo 162 MHz.

Jikọọ mgbaama elekere ntinye a na sekit elekere mpụga ma ọ bụ oscillators.

out_systempll_clk_ 1

Ntinye

Elekere PLL sistemụ.
Jikọọ elekere a na mgbama mmepụta (out_systempll_clk_0) nke F-Tile Reference na Sistemu PLL Clocks Intel FPGA IP.

Oke ozi emetụtara na ibe 42

6.2. Tọgharia akara ngosi

Tebụl 20. Tọgharia akara ngosi

Aha

Ụzọ obosara

tx_core_rst_n

Ntinye

Ngalaba elekere anaghị arụkọ ọrụ

rx_core_rst_n

Ntinye

Asynchronous

tx_pcs_fec_phy_reset_n 1

Ntinye

Asynchronous

Nkọwa

Mgbama nrụpụta nrụpụta dị ala na-arụ ọrụ. Tụgharịa F-Tile Serial Lite IV TX MAC.

Mgbama nrụpụta nrụpụta dị ala na-arụ ọrụ. Tụgharịa F-Tile Serial Lite IV RX MAC.

Mgbama nrụpụta nrụpụta dị ala na-arụ ọrụ.

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Aha

ngalaba elekere ntụzịaka obosara

Nkọwa

Tụgharịa PCS omenala F-Tile Serial Lite IV TX.

rx_pcs_fec_phy_reset_n 1

Ntinye

Asynchronous

Mgbama nrụpụta nrụpụta dị ala na-arụ ọrụ. Tụgharịa PCS omenala F-Tile Serial Lite IV RX.

reconfig_reset

Ntinye

reconfig_clk Mgbama nrụpụta ọrụ dị elu.

Tụgharịa ngọngọ nhazigharị nhazigharị ebe nchekwa Avalon.

reconfig_sl_reset

Ntinye reconfig_sl_clk Mgbama nrụpụta ọrụ dị elu.

Tụgharịa ngọngọ nhazigharị nhazigharị ebe nchekwa Avalon.

6.3. Ihe mgbaàmà MAC

Tebụl 21.

TX MAC akara
N'ime tebụl a, N na-anọchi anya ọnụọgụ nke ụzọ edobere na ndezi paramita IP.

Aha

Obosara

Ngalaba elekere ntụzịaka

Nkọwa

tx_avs_dị njikere

Mpụta tx_core_clkout Avalon nkwanye mgbama.

Mgbe ekwuputara, na-egosi na TX MAC dị njikere ịnakwere data.

tx_avs_data

· (64*N)*2 (ụdị PAM4)
64*N (ụdị NRZ)

Ntinye

tx_core_klout Avalon nkwanye mgbama. data TX.

tx_avs_channel

Tinye akara ngosi tx_core_clkout Avalon.

Nọmba ọwa maka data na-ebufe na okirikiri dị ugbu a.

Mgbama a adịghị na ọnọdụ ntọala.

tx_avs_dị irè

Tinye akara ngosi tx_core_clkout Avalon.

Mgbe ekwuputara, na-egosi na mgbama data TX bara uru.

tx_avs_startofpacket

Tinye akara ngosi tx_core_clkout Avalon.

Mgbe ekwuputara, na-egosi mmalite nke ngwugwu data TX.

Kwupụta maka naanị otu okirikiri elekere maka ngwugwu ọ bụla.

Mgbama a adịghị na ọnọdụ ntọala.

tx_avs_endofpacket

Tinye akara ngosi tx_core_clkout Avalon.

Mgbe ekwuputara, na-egosi njedebe nke ngwugwu data TX.

Kwupụta maka naanị otu okirikiri elekere maka ngwugwu ọ bụla.

Mgbama a adịghị na ọnọdụ ntọala.

tx_avs_efu

Tinye akara ngosi tx_core_clkout Avalon.

Na-egosi ọnụọgụ nke mkpụrụokwu na-ezighi ezi na mgbawa ikpeazụ nke data TX.

Mgbama a adịghị na ọnọdụ ntọala.

tx_num_valid_bytes_eob

Ntinye

tx_core_klout

Na-egosi ọnụọgụ bytes ziri ezi na okwu ikpeazụ nke mgbawa ikpeazụ. Mgbama a adịghị na ọnọdụ ntọala.
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Aha tx_is_usr_cmd
tx_link_up tx_link_reinit
crc_error_inject tx_error

Ogologo 1
1 1
N 5

Ngalaba elekere ntụzịaka

Nkọwa

Ntinye

tx_core_klout

Mgbe ekwuputara, mgbaama a na-ebute okirikiri ozi akọwapụtara nke onye ọrụ.
Wepụta akara ngosi a n'otu okirikiri elekere dịka nkwuputa tx_startofpacket.
Mgbama a adịghị na ọnọdụ ntọala.

Mpụta tx_core_clkout Mgbe ekwuputara, na-egosi njikọ data TX adịla njikere maka nnyefe data.

Mpụta

tx_core_klout

Mgbe ekwuputara ya, mgbaama a na-ebute nhazigharị ụzọ.
Kwupụta akara ngosi a maka otu okirikiri elekere iji kpalite MAC izipu ALIGN CW.

Ntinye

tx_core_clkout Mgbe ekwuputara ya, MAC na-agbanye mperi CRC32 na ụzọ ahọpụtara.

Mpụta tx_core_clkout Ejighị ya.

Eserese oge na-esote na-egosi exampMbufe data TX nke mkpụrụokwu iri sitere na mgbagha onye ọrụ n'ofe okporo ụzọ 10 TX.

Onyonyo 28.

Eserese oge nnyefe data TX
tx_core_klout

tx_avs_dị irè

tx_avs_dị njikere

tx_avs_startofpackets

tx_avs_endofpackets

tx_avs_data

0,1...,19 10,11…19 …… N-10..

0,1,2,…,9

N-10.

Ụzọ 0

…………

STRT 0 10

N-10 Ọgwụgwụ STRT 0

Ụzọ 1

…………

STRT 1 11

N-9 Ọgwụgwụ STRT 1

N-10 Ọgwụgwụ Idle Idle N-9 Ọgwụgwụ Idle

Ụzọ 9

…………

STRT 9 19

N-1 Ọgwụgwụ STRT 9

N-1 ỌJỤJỤ NDỊ NA-AHỤGHỊ IHE

Tebụl 22.

Mgbama RX MAC
N'ime tebụl a, N na-anọchi anya ọnụọgụ nke ụzọ edobere na ndezi paramita IP.

Aha

Obosara

Ngalaba elekere ntụzịaka

Nkọwa

rx_avs_dị njikere

Tinye akara ngosi rx_core_clkout Avalon.

Mgbe ekwuputara, na-egosi na mgbagha onye ọrụ adịla njikere ịnakwere data.

rx_avs_data

(64*N)*2 (ụdị PAM4)
64*N (ụdị NRZ)

Mpụta

rx_core_klout Avalon nkwanye mgbama. data RX.

rx_avs_channel

Mpụta rx_core_clkout Avalon nkwanye mgbama.

Nọmba ọwa maka data ịbụ

natara na nke ugbu a okirikiri.

Mgbama a adịghị na ọnọdụ ntọala.

rx_avs_valid

Mpụta rx_core_clkout Avalon nkwanye mgbama.

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Aha

Obosara

Ngalaba elekere ntụzịaka

Nkọwa

Mgbe ekwuputara, na-egosi na mgbama data RX bara uru.

rx_avs_startofpacket

Mpụta rx_core_clkout Avalon nkwanye mgbama.

Mgbe ekwuputara, na-egosi mmalite nke ngwugwu data RX.

Kwupụta maka naanị otu okirikiri elekere maka ngwugwu ọ bụla.

Mgbama a adịghị na ọnọdụ ntọala.

rx_avs_endofpacket

Mpụta rx_core_clkout Avalon nkwanye mgbama.

Mgbe ekwuputara, na-egosi njedebe nke ngwugwu data RX.

Kwupụta maka naanị otu okirikiri elekere maka ngwugwu ọ bụla.

Mgbama a adịghị na ọnọdụ ntọala.

rx_avs_efu

Mpụta rx_core_clkout Avalon nkwanye mgbama.

Na-egosi ọnụọgụ nke mkpụrụokwu na-ezighi ezi na mgbawa ikpeazụ nke data RX.

Mgbama a adịghị na ọnọdụ ntọala.

rx_num_valid_bytes_eob

Mpụta

rx_core_clkout na-egosi ọnụọgụ bytes ziri ezi na okwu ikpeazụ nke mgbawa ikpeazụ.
Mgbama a adịghị na ọnọdụ ntọala.

rx_is_usr_cmd

Mpụta rx_core_clkout Mgbe ekwuputara, mgbaama a na-ebute onye ọrụ-

okirikiri ozi akọwapụtara.

Wepụta akara ngosi a n'otu okirikiri elekere dịka nkwuputa tx_startofpacket.

Mgbama a adịghị na ọnọdụ ntọala.

rx_link_up

Mpụta rx_core_clkout Mgbe ekwuputara, na-egosi njikọ data RX

dị njikere maka nnabata data.

rx_link_reinit

Ntinye rx_core_clkout Mgbe ekwuputara ya, mgbaama a na-ebute ụzọ

nhazigharị ọzọ.

Ọ bụrụ na ị gbanyụọ Kwado Nhazi akpaaka, kwupụta akara ngosi a maka otu elekere iji kpalite MAC ka ọ kwadogharịa ụzọ ahụ. Ọ bụrụ na edobere Kwado akpaaka, MAC na-edozigharị ụzọ ahụ na-akpaghị aka.

Ekwughachila mgbaama a mgbe akwadodo nhazi akpaaka.

rx_error

(N*2*2)+3 (ụdị PAM4)
(N*2)*3 (Ụdị NRZ)

Mpụta

rx_core_klout

Mgbe ekwuputara, na-egosi ọnọdụ mperi na-eme na ụzọ data RX.
· [(N*2+2):N+3] = Na-egosi njehie PCS maka ụzọ a kapịrị ọnụ.
· [N+2] = Na-egosi mperi nhazi. Malitegharịa nhazi okporo ụzọ ma ọ bụrụ na akwadoro ntakịrị ihe a.
[N+1]= Na-egosi na ezigara data na mgbagha onye ọrụ mgbe mgbagha onye ọrụ adịghị njikere.
· [N] = Na-egosi mfu nke nhazi.
· [(N-1):0] = Na-egosi data nwere mperi CRC.

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6.4. Mgbama nhazigharị transceiver

Tebụl 23.

Ngosipụta nhazigharị PCS
N'ime tebụl a, N na-anọchi anya ọnụọgụ nke ụzọ edobere na ndezi paramita IP.

Aha

Obosara

Ngalaba elekere ntụzịaka

Nkọwa

reconfig_sl_read

Tinye reconfig_sl_ PCS reconfiguration agụ iwu

klk

akara.

reconfig_sl_write

Tinye reconfig_sl_ PCS nhazigharị dee

klk

akara ngosi.

reconfig_sl_adreesị

14-bit + clogb2N

Ntinye

reconfig_sl_ clk

Na-akọwapụta adreesị nrụgharị PCS Avalon ebe nchekwa nwere mapped n'okporo ụzọ ahọpụtara.
Ụzọ nke ọ bụla nwere 14 ibe n'ibe na elu ibe n'ibe na-ezo aka n'ahịrị akwụkwụ.
Example, maka imewe NRZ/PAM4 nwere uzo 4, ya na reconfig_sl_address[13:0] na-ezo aka uru adreesị:
· reconfig_sl_address[15:1 4] ka 00 = adreesị maka uzo 0.
· reconfig_sl_address[15:1 4] ka 01 = adreesị maka uzo 1.
· reconfig_sl_address[15:1 4] ka 10 = adreesị maka uzo 2.
· reconfig_sl_address[15:1 4] ka 11 = adreesị maka uzo 3.

reconfig_sl_readata

Mmepụta reconfig_sl_ Na-akọwapụta data nhazigharị PCS

klk

a ga-agụ ya site na okirikiri dị njikere na a

uzo ahọpụtara.

reconfig_sl_waitrequest

Mpụta reconfig_sl_ na-anọchi anya nhazigharị PCS

klk

Avalon ebe nchekwa-mapped interface

mgbama na-akwụsị n'ahịrị ahọpụtara.

reconfig_sl_writedata

Ntinye reconfig_sl_ Na-akọwapụta data nhazigharị PCS

klk

a ga-ede na okirikiri ide na a

uzo ahọpụtara.

reconfig_sl_readata_vali

Mpụta

reconfig_sl_ Na-akọwa nhazigharị PCS

klk

data enwetara bara uru na ahọpụtara

uzo.

Tebụl 24.

F-Tile Hard IP Reconfiguration Signals
N'ime tebụl a, N na-anọchi anya ọnụọgụ nke ụzọ edobere na ndezi paramita IP.

Aha

Obosara

Ngalaba elekere ntụzịaka

Nkọwa

reconfig_read

Ntinye reconfig_clk PMA nhazigharị agụ

akara ngosi.

reconfig_write

Tinye reconfig_clk PMA nhazigharị dee

akara ngosi.

reconfig_address

18-bit + clog2bN

Ntinye

reconfig_clk

Ezipụta adrees interface nwere ebe nchekwa PMA Avalon n'ụzọ ahọpụtara.
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Aha
reconfig_readdata reconfig_waitrequest reconfig_writedata reconfig_readdatavalid

Obosara
32 1 32 1

Ngalaba elekere ntụzịaka

Nkọwa

Na ụdịdị PAM4 ad NRZ abụọ, ụzọ nke ọ bụla nwere 18 ibe n'ibe na nke fọdụrụ n'elu na-ezo aka n'ịkwụ ụgwọ.
Example, maka imewe ụzọ anọ:
· reconfig_address[19:18] ka 00 = adreesị maka uzo 0.
· reconfig_address[19:18] ka 01 = adreesị maka uzo 1.
· reconfig_address[19:18] ka 10 = adreesị maka uzo 2.
· reconfig_address[19:18] ka 11 = adreesị maka uzo 3.

Mpụta

reconfig_clk Na-akọwapụta data PMA ga-agụ site na okirikiri dị njikere n'ụzọ ahọpụtara.

Mpụta

reconfig_clk na-anọchi anya PMA Avalon ebe nchekwa interface na-egbochi mgbaàmà n'ụzọ ahọpụtara.

Ntinye

reconfig_clk Na-akọwapụta data PMA nke a ga-ede na okirikiri ederede n'ụzọ ahọpụtara.

Mpụta

reconfig_clk Na-akọwapụta nhazigharị PMA natara data bara uru n'ụzọ ahọpụtara.

6.5. Akara ngosi PMA

Tebụl 25.

Akara ngosi PMA
N'ime tebụl a, N na-anọchi anya ọnụọgụ nke ụzọ edobere na ndezi paramita IP.

Aha

Obosara

Ngalaba elekere ntụzịaka

Nkọwa

phy_tx_lanes_stable

N*2 (ụdị PAM4)
N (ụdị NRZ)

Mpụta

Asynchronous Mgbe ekwuputara, na-egosi data ụzọ TX adịla njikere izipu data.

tx_pll_kpọchiri

N*2 (ụdị PAM4)
N (ụdị NRZ)

Mpụta

Asynchronous Mgbe ekwuputara, na-egosi na TX PLL enwetala ọkwa mkpọchi.

phy_ehip_dị njikere

N*2 (ụdị PAM4)
N (ụdị NRZ)

Mpụta

Asynchronous

Mgbe ekwuputara ya, na-egosi na PCS omenala emechala mmalite nke ime ma dịrị njikere maka mbufe.
Mgbama a na-ekwupụta mgbe tx_pcs_fec_phy_reset_n na tx_pcs_fec_phy_reset_nare deasserted.

tx_serial_data

Mpụta TX Oghere Usoro elekere TX Oghere Usoro ntụtụ.

rx_serial_data

Tinye Oghere Usoro elekere RX Oghere Usoro ntụtụ.

phy_rx_block_lock

N*2 (ụdị PAM4)
N (ụdị NRZ)

Mpụta

Asynchronous Mgbe ekwuputara, na-egosi na nhazi ihe mgbochi 66b emechaala maka ụzọ ahụ.

rx_cdr_lock

N*2 (ụdị PAM4)

Mpụta

Asynchronous

Mgbe ekwuputara, na-egosi na akpọchiri elekere ndị enwetara na data.
gara n'ihu…

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Aha phy_rx_pcs_ready phy_rx_hi_ber

Obosara

Ngalaba elekere ntụzịaka

Nkọwa

N (ụdị NRZ)

N*2 (ụdị PAM4)
N (ụdị NRZ)

Mpụta

Asynchronous

Mgbe ekwuputara, na-egosi na ụzọ RX nke ọwa Ethernet kwekọrọ na-adakọrịrị nke ọma ma dị njikere ịnata data.

N*2 (ụdị PAM4)
N (ụdị NRZ)

Mpụta

Asynchronous

Mgbe ekwuputara, na-egosi na RX PCS nke ọwa Ethernet kwekọrọ na steeti HI BER.

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7. Ime na F-Tile Serial Lite IV Intel FPGA IP

7.1. Tọgharịa ntuziaka
Soro ntuziaka nrụpụta ndị a iji mejuputa ntọgharị ọkwa sistemụ gị.
Tie tx_pcs_fec_phy_reset_n na rx_pcs_fec_phy_reset_n akara ọnụ n'ọkwa sistemụ iji tọgharịa TX na RX PCS n'out oge.
Nyefee tx_pcs_fec_phy_reset_n, rx_pcs_fec_phy_reset_n, tx_core_rst_n, rx_core_rst_n, na reconfig_reset akara n'otu oge. Rụtụ aka na Tọgharia na njikọ mmalite maka ozi ndị ọzọ gbasara usoro nrụpụta IP na mmalite.
Jide tx_pcs_fec_phy_reset_n, yana rx_pcs_fec_phy_reset_n na-egosi ala, yana reconfig_reset mgbama dị elu wee chere tx_reset_ack na rx_reset_ack iji tọgharịa IP siri ike F-tile nke ọma na ngọngọ nhazigharị.
Iji nweta njikọ ngwa ngwa n'etiti ngwaọrụ FPGA, tọgharịa F-Tile Serial Lite IV Intel FPGA IP ejikọrọ n'otu oge. Rụtụ aka na F-Tile Serial Lite IV Intel FPGA IP Design ExampNtuziaka onye ọrụ maka ozi gbasara nyochaa njikọ IP TX na RX site na iji ngwa ngwa.
Ozi metụtara
· Tọgharia na mmalite njikọ na ibe 37
F-Tile Serial Lite IV Intel FPGA IP Design Example ntuziaka onye ọrụ

7.2. Ntuziaka ijikwa njehie

Tebụlụ na-esote depụtara ntuziaka njikwa njehie maka ọnọdụ njehie nke nwere ike ime site na imewe F-Tile Serial Lite IV Intel FPGA IP.

Tebụl 26. Ọnọdụ njehie na ntuziaka njikwa

Ọnọdụ mperi
Otu ụzọ ma ọ bụ karịa enweghị ike ịmepụta nzikọrịta ozi ka oge enyerechara.

Ntuziaka
Tinye usoro nkwụsị oge iji tọgharịa njikọ na ọkwa ngwa.

Ụzọ na-efunahụ nzikọrịta ozi ka emechara nkwurịta okwu.
Ụzọ na-efunahụ nkwukọrịta n'oge usoro deskew.

Nke a nwere ike ime ma ọ bụ n'oge usoro mbufe data. Mejuputa nchọpụta ọnwụ njikọ na ọkwa ngwa wee tọgharịa njikọ ahụ.
Mejuputa usoro nnabata njikọ maka ụzọ ezighi ezi. Ị ga-ahụrịrị na ụzọ ụgbọ mmiri agaghị agafe 320 UI.

Ndozi n'okporo ụzọ mfu ka emechara ụzọ niile.

Nke a nwere ike ime mgbe ma ọ bụ n'oge nnyefe data. Mejuputa nchọpụta mfu nhazi usoro n'ogo ngwa ka ịmalitegharịa usoro nhazi okporo ụzọ.

ISO 9001: 2015 edebanye aha

683074 | 2022.04.28 zipu nzaghachi

8. F-Tile Serial Lite IV Intel FPGA IP Ntuziaka Ntuziaka

Ụdị IP bụ otu ụdị sọftụwia Intel Quartus Prime Design Suite ruo v19.1. Site na ụdị sọftụwia Intel Quartus Prime Design Suite 19.2 ma ọ bụ karịa, IP cores nwere atụmatụ mbipụta IP ọhụrụ.

Ọ bụrụ na edepụtaghị ụdị isi IP, ntuziaka onye ọrụ maka ụdị IP isi gara aga na-emetụta.

Intel Quartus Prime Version
21.3

Ụdị IP Core 3.0.0

Ntuziaka onye ọrụ F-Tile Serial Lite IV Intel® FPGA IP ntuziaka onye ọrụ

ISO 9001: 2015 edebanye aha

683074 | 2022.04.28 zipu nzaghachi

9. Akụkọ ngbanwe akwụkwọ maka F-Tile Serial Lite IV Intel FPGA IP ntuziaka onye ọrụ

Ụdị akwụkwọ 2022.04.28
2021.11.16 2021.10.22 2021.08.18

Intel Quartus Prime Version
22.1
21.3 21.3 21.2

Ụdị IP 5.0.0
3.0.0 3.0.0 2.0.0

Mgbanwe
Tebụl emelitere: F-Tile Serial Lite IV Akụkụ Intel FPGA IP - Nkọwa mbufe data emelitere yana nkwado ọnụego transceiver FHT ọzọ: 58G NRZ, 58G PAM4, na 116G PAM4
Tebụl emelitere: F-Tile Serial Lite IV Nkọwapụta Paramita IP FPGA - Agbakwunyere oke ọhụrụ · Oge elekere elekere Sistemu PLL · Kwado ebe njedebe nbipu - Emelitere uru maka ọnụego data PMA - aha njirimara emelitere dabara na GUI
Emelitere nkọwa maka ịnyefe data na Tebụlụ: F-Tile Serial Lite IV Njirimara FPGA IP.
Akpọgharịrị aha tebụl IP ka ọ bụrụ F-Tile Serial Lite IV Intel FPGA IP Parameter Description na ngalaba Parameters maka idoanya.
Tebụl emelitere: paramita IP: - Agbakwunyere oke ọhụrụ–RSFEC enyere na Serial Lite IV Simplex IP nke ọzọ etinyere n'otu ọwa FGT. - Emelitere ụkpụrụ ndabara maka ugboro elekere ntụgharị ntụgharị.
Ntọhapụ mbụ.

ISO 9001: 2015 edebanye aha

Akwụkwọ / akụrụngwa

	intel F Tile Serial Lite IV Intel FPGA IP [pdf] Ntuziaka onye ọrụ F Tile Serial Lite IV Intel FPGA IP, F Tile Serial Lite IV, Intel FPGA IP
	intel F-Tile Serial Lite IV Intel FPGA IP [pdf] Ntuziaka onye ọrụ F-Tile Serial Lite IV Intel FPGA IP, Serial Lite IV Intel FPGA IP, Lite IV Intel FPGA IP, IV Intel FPGA IP, FPGA IP, IP