HOPERF CMT2186A Sub-1G Transmitting Micro Controller User Guide

The CMT2186A features various memory storage options. Ensure
proper utilization of the MTP program storage, XRAM, IRAM, and
EEPROM for your application needs.

5. Working Temperature

Operate the CMT2186A within the specified temperature range of
-40°C to 85°C for optimal performance.

Frequently Asked Questions (FAQ)

Q: What is the working frequency range of the CMT2186A?

A: The CMT2186A operates within a frequency range of 210 – 960
MHz.

Q: How can I adjust the output power of the transmitter
module?

A: The output power can be adjusted from 0 to +13dBm. Refer to
the manual for specific instructions on adjusting the output
power.

Q: What is the memory capacity of the CMT2186A?

A: The CMT2186A features 4-KB MTP program storage, 512-Byte
XRAM, 256-Byte IRAM, and 512-Bit EEPROM for memory usage.

“`

View Fullscreen

AN261-CMT2186A User Guide
CMT2186A
210-960 MHz OOK/ASK Transmitter SoC
CMT2186A Sub-1G Transmitting Micro-controller
User guide

1. This document describes the functions, operations, and usage of the CMT2186A. It is guidance for engineers who uses the CMT2186A.
2. This manual is limited by the length of the document, and the referred registers of the chip function modules are only listed. Please refer to the CMT2186A Register Detailed Manual for detailed register description. Users can understand the chip functions more efficiently by referring to this document.

Rev 0.1A | 1/100 Page

www.hoperf.com

AN261-CMT2186A User Guide

MCU Feature

Sub-1G Transmitting Module Attributes

CPU kernal

Working frequency: 210 – 960MHz

– High performance single instruction period 1T-8051 kernal Modulated Mode: OOK / ASK

– Supports up to 26MHz (XOSC) or 24Mhz (HFOSC) Data rate: 0.5 40kbpsOOK

operating frequencies with a maximum access efficiency of Output power+13dBmMax.

20MIPS

Working current24mA @+13dBm433.92MHz CW

– Operating consumption Storage

Single-ended high efficiency Class E high frequency transmitting PA

– 4-KB MTP program storage, support 10K erasing time

PA Ramping varies according to the data rate

– 512-Byte XRAM and 256-Byte IRAM

– 512-Bit EEPROMsupport 1,000,000 erasing time

Working Condition

Power

Temperature range is -40 – 85

– Power on reset and low voltage detection

Working voltage range is 1.8V – 3.6V

– Embeded independent LDO provides power for CPU and

digital citcuit

Application

– The embeded ultra-low power ULPLDO achieves the Remote garage door control Retention function of CPU/RAM/SFR and some of the Remote door control system

peripherals in STOP mode I/O

Consumer wireless remote control Smart home

– 11/9 multi-functional IO pins (SOP16 / SOP14)

House security

– Supports highly flexible peripheral function mapping

Source RFID tagging

– Support level change interrupt/wake up

Wireless sensor network

Clock source

WM-Bus T1 mode

– Support up to 26Mhz XOSC (high speed frequency crystal

oscillator)

Package

– Built-in high speed 24MHz HFOSC (±1% RC oscillator)

SOP16

– Built-in low power consumption 32kHz LFOSC (±1% RC SOP14

oscillator)

Debug onchip

– CPU built-in 1-Wire debugger hardware circuit

– Support Keil C51 for online program debugging

– Supports 3 hardware breakpoints, single step debugging Peripheral

– 1x UART

– 1x SPI – 1x CDRsingle wire RX input clock recovery – 1x WDTindependent hardware – 1x sleep timer32KHz LFOSC

SOP-14
8.65 x 6 x 1.75 mm

SOP-16
9.9 x 6 x 1.75 mm

– 2x 16 bit simple timer – 2x 16 bit multi-Function timer3 channel PWM/CCP

– 2x analog comparator Code Security

– The burning serial ports and single-wire debugging interface

have locking function

Rev 0.1A | 2/100 Page

www.hoperf.com

AN261-CMT2186A User Guide
Introduction
The CMT2186A is a low-power SoC RF transmitter embedded with an enhanced 1T-8051 core 1. which supports OOK/ASK modulation wireless transmission function among 210 ~ 960 MHz 2. The transmitter module not only provides high efficient single-ended PA, with adjustable output power from 0 to
+13dBm, and only 24mA needed for +13dBm transmission; 3. But also provides 4-KB MTP program memory, 512-Byte XRAM, 256-Byte IRAM, and 512-bit EEPROM; 4. The built-in ultra-low power ULPLDO supports the chip to save CPU status, RAM data, and configuration register
data in STOP mode 5. With 1-WIRE online simulation function, users can download the target debugging code directly to the on-chip
MTP through the dedicated 1-WIRE debugger and Keil C51 software, which is very convenient. 6. It supports external 26MHz XO or built-in 24MHz HFOSC as the system main frequency and the built-in low
power 32 kHz LFOSC can be used for low power timer wake-up; 7. It also supports single-wire input hardware clock recovery module, which is convinient for the kernel to collect the
external data synchronously (such as RX receiving data).

Combined with CMOSTEK’s NextGenRFTM series receivers, CMT2186A can be applied in a wide range of ultra-low power wireless network.

Part Number
CMT2186A-ESR14 CMT2186A-ESR16

Product Information.
Package
SOP-14 SOP-16

Dimension
8.65 mm x 6.00 mm x 1.75mm 9.90 mm x 6.00 mm x 1.75mm

Rev 0.1A | 3/100 Page

www.hoperf.com

Categories

AN261-CMT2186A User Guide

1 SYSTEM ARCHITECT …………………………………………………………………………………………………………………………….. 7
2 SYSTEM OPERATING PROCESS AND WORKING MODE ………………………………………………………………………………. 8
2.1 SYSTEM OPERATING PROCESS……………………………………………………………………………………………………………………… 8 2.2 SYSTEM OPERATING MODE………………………………………………………………………………………………………………………… 9 2.3 PROTECT MECHANISM ……………………………………………………………………………………………………………………………. 12
3 DEBUGGING AND BURNING INTERFACES ……………………………………………………………………………………………….12
3.1 1-WIRE ONLINE DEBUGGING AND BURNING INTERFACES ………………………………………………………………………………….. 12 3.2 S3S BUS BURNING INTERFACE…………………………………………………………………………………………………………………… 13
4 T8051XC3 MICRO CONTROLLER…………………………………………………………………………………………………………….14
4.1 PROCESSOR ARCHITECTURE………………………………………………………………………………………………………………………. 14 4.2 INSTRUCTION SETS: ……………………………………………………………………………………………………………………………….. 15 4.3 8051 CORES INITIAL REGISTER ………………………………………………………………………………………………………………….. 15
5 MEMORY STRUCTURE …………………………………………………………………………………………………………………………17
5.1 INTRODUCTION…………………………………………………………………………………………………………………………………….. 17 5.2 SPECIAL FEATURE REGISTERSSFR…………………………………………………………………………………………………………. 18 5.3 ALWAYS-ON DOMAIN REGISTER (AON REG) …………………………………………………………………………………………………. 19 5.4 MEMORY RUNNING ACCESS MODE …………………………………………………………………………………………………………….. 19
6 RESET STRUCTURE………………………………………………………………………………………………………………………………20
7 CLOCK STRUCTURE ……………………………………………………………………………………………………………………………..20
7.1 CLOCK SOURCE…………………………………………………………………………………………………………………………………….. 20 7.2 CLOCK CALIBRATION ………………………………………………………………………………………………………………………………. 22 7.3 CLOCK FREQUENCY DIVISION…………………………………………………………………………………………………………………….. 22 7.4 CLOCK GATE CONTROL ……………………………………………………………………………………………………………………………. 22 7.5 RELATED REGISTER………………………………………………………………………………………………………………………………. 26
8 INTERRUPTS AND WAKEUP ………………………………………………………………………………………………………………….27
8.1 INTRODUCTION…………………………………………………………………………………………………………………………………….. 27 8.2 WAKEUP SOURCE………………………………………………………………………………………………………………………………….. 27 8.3 INTERRUPT SOURCE AND INTERRUPT CONTROL ……………………………………………………………………………………………….. 28 8.4 EXTERNAL INTERRUPT MAPPING ………………………………………………………………………………………………………………… 29 8.5 RELATED REGISTER ………………………………………………………………………………………………………………………………… 32
9 GPIO MODULE …………………………………………………………………………………………………………………………………..34
9.1 BASIC FUNCTION ………………………………………………………………………………………………………………………………….. 34 9.2 GPIO STRUCTURE INTRODUCTION ……………………………………………………………………………………………………………… 34 9.3 GPIO DIGITAL INPUT……………………………………………………………………………………………………………………………… 36

Rev 0.1A | 4/100 Page

www.hoperf.com

AN261-CMT2186A User Guide
9.4 GPIO DIGITAL OUTPUT…………………………………………………………………………………………………………………………… 36 9.5 GPIO ANALOG INPUT AND OUTPUT ……………………………………………………………………………………………………………. 37 9.6 GPIO DIGITAL INPUT MAPPING…………………………………………………………………………………………………………………. 37 9.7 GPIO DIGITAL OUTPUT MAPPING………………………………………………………………………………………………………………. 39 9.8 GPIO LEVEL FLIPPING DETECTION………………………………………………………………………………………………………………. 45 9.9 RELATED REGISTER ………………………………………………………………………………………………………………………………… 47
10 TIMER0 MODULE…………………………………………………………………………………………………………………………….49
10.1 BASIC FUNCTION ………………………………………………………………………………………………………………………………….. 49 10.2 TIMER0 MODE0…………………………………………………………………………………………………………………………………… 49 10.3 TIMER0 MODE1…………………………………………………………………………………………………………………………………… 50 10.4 TIMER0 MODE2…………………………………………………………………………………………………………………………………… 50 10.5 RELATED REGISTER ………………………………………………………………………………………………………………………………… 51
11 TIMER1 MODULE…………………………………………………………………………………………………………………………….52
11.1 BASIC FUNCTION ………………………………………………………………………………………………………………………………….. 52 11.2 TIMER1 MODE0…………………………………………………………………………………………………………………………………… 52 11.3 TIMER1 MODE1…………………………………………………………………………………………………………………………………… 53 11.4 TIMER1 MODE2…………………………………………………………………………………………………………………………………… 53 11.5 RELATED REGISTER ………………………………………………………………………………………………………………………………… 54
12 SPI MODULE …………………………………………………………………………………………………………………………………..55
12.1 BASIC FUNCTION ………………………………………………………………………………………………………………………………….. 55 12.2 CONFIGURATION OPTION ………………………………………………………………………………………………………………………… 56 12.3 WORKING MODE………………………………………………………………………………………………………………………………….. 57 12.4 STATUS FLAG……………………………………………………………………………………………………………………………………….. 58 12.5 RELATED REGISTER ………………………………………………………………………………………………………………………………… 59
13 UART MODULE ……………………………………………………………………………………………………………………………….60
13.1 BASIC FUNCTION ………………………………………………………………………………………………………………………………….. 60 13.2 SYNCHRONOUS SHIFT MODE (MODE0)………………………………………………………………………………………………………… 60 13.3 ASYNCHRONOUS FULL-DUPLEX MODE WITH CONFIGURABLE BAUD RATE (MODE 1 AND MODE 3) …………………………………… 62 13.4 ASYNCHRONOUS FULL-DUPLEX MODE WITH FIXED BAUD RATE (MODE 2) ……………………………………………………………….. 65 13.5 ENHANCED MODE OF USART …………………………………………………………………………………………………………………… 66 13.6 RELATED REGISTER ………………………………………………………………………………………………………………………………… 68
14 TIMER A/TIMER B MODULE………………………………………………………………………………………………………………69
14.1 OPERATION METHOD …………………………………………………………………………………………………………………………….. 70 14.2 UP MODE ………………………………………………………………………………………………………………………………………….. 71 14.3 CONTINUOUS MODE ……………………………………………………………………………………………………………………………… 72 14.4 UP / DOWN MODE ……………………………………………………………………………………………………………………………….. 73 14.5 CAPTURE/COMPARE MODULE …………………………………………………………………………………………………………………… 75 14.6 EXAMPLES FOR VARIOUS MODES ……………………………………………………………………………………………………………….. 77 14.7 RELATED REGISTER ………………………………………………………………………………………………………………………………… 79

Rev 0.1A | 5/100 Page

www.hoperf.com

AN261-CMT2186A User Guide
15 WATCHDOG (WDT) MODULE …………………………………………………………………………………………………………….80 15.1 BASIC FUNCTION ………………………………………………………………………………………………………………………………….. 80 15.2 RELATED REGISTER ………………………………………………………………………………………………………………………………… 80
16 SLEEP TIMERMODULE ……………………………………………………………………………………………………………………..81 16.1 BASIC FUNCTION ………………………………………………………………………………………………………………………………….. 81 16.2 LPOSC CALIBRATION……………………………………………………………………………………………………………………………… 81 16.3 RELATED REGISTER ………………………………………………………………………………………………………………………………… 81
17 COMPARATOR ………………………………………………………………………………………………………………………………..82 17.1 COMPARATOR ANALOG INPUT …………………………………………………………………………………………………………………… 82 17.2 COMPARATOR REFERENCE VOLTAGE…………………………………………………………………………………………………………….. 83 17.3 COMPARATOR WORK MODE …………………………………………………………………………………………………………………….. 83 17.4 RELATED REGISTER ………………………………………………………………………………………………………………………………… 83
18 LOW VOLTAGE RESET (LVR) ……………………………………………………………………………………………………………….84 19 LOW VOLTAGE DETECTION MODULE ………………………………………………………………………………………………….84
19.1 BASIC FUNCTION ………………………………………………………………………………………………………………………………….. 84 19.2 RELATED REGISTER ………………………………………………………………………………………………………………………………… 85 20 SUB-1G TRANSMITTING MODULE ……………………………………………………………………………………………………..85 20.1 INTRODUCTION…………………………………………………………………………………………………………………………………….. 85 20.2 PA OUTPUT METHOD…………………………………………………………………………………………………………………………….. 86 20.3 TRANSMITTING PROCESS OF BUFFER MODE …………………………………………………………………………………………………… 86 20.4 TRANSMITTING PROCESS OF DIRECT MODE……………………………………………………………………………………………………. 88 20.5 RELATED REGISTER ………………………………………………………………………………………………………………………………… 89 21 PACKAGE OUTLINE ………………………………………………………………………………………………………………………….90 21.1 CMT2186A-ESR14 PACKAGE …………………………………………………………………………………………………………………. 90 21.2 CMT2186A-ESR16 PACKAGE …………………………………………………………………………………………………………………. 91 22 TOP SILK PRINTING………………………………………………………………………………………………………………………….92 23 OTHER RELATED DOCUMENT…………………………………………………………………………………………………………….93 24 REVISE HISTORY ……………………………………………………………………………………………………………………………..94 25 CONTACTS ……………………………………………………………………………………………………………………………………..95 APPENDIX A!…………………………………………………………………………………………………………………………………………….96

Rev 0.1A | 6/100 Page

www.hoperf.com

1 System Architect

AN261-CMT2186A User Guide

Embedded with a sub-1 GHz OOK / ASK transmitterCMT2186A is a high-performance 8051 wireless MCU. The user program is burned in the 4K Bytes MTP, which can be operated at clock frequency up to 26MHz. The chip integrates the below major modules:

High-performance 8051 core with 1-Wire online debug circuit; Rich digital and analog peripheral resources. Sub-1G OOK / ASK modulated transmitting module

1-Wire (D10)

1-Wire Debug Hardware

Power-On Reset

Reset

Core / Momory 1T-8051 Core 4K-Byte MTP 512-Byte XRAM

Supply Monitor
RSTn (D0)

256-Byte IRAM 16 x 32b EEPROM

Wake-up Interrupts

AON domain

Independent Watchdog Timer

I/O Change Scan

Sleep Timer

AON REG

INT

Bus

XTAL

D0,1,2…

LFOSC_CLK

Clock Configuration

32 kHz LFOSC

24 MHz HFOSC

/ n

26 MHz XOSC

MCU_CLK SYS_CLK TX_CLK

DVDD GND

DLDO

ULPLDO

SFR Bus

Port I/O Configuration

Digital Peripherals Driven by MCU_CLK
16-bit Timer 0
16-bit Timer 1
UART
Port 0
Port 1
Digital Peripherals Driven by SYS_CLK
SPI 16-bit Timer A
3ch PCA w/ PWM 16-bit Timer B 3ch PCA w/ PWM RX CDR

GPIO MUX
& Drivers

Analog Peripherals Comparator 0 Comparator 1
LBD

Sub-1Ghz Transmitter ASK / OOK Modulator

PLL

Divider

D0,1,2 …
AVDD TX

Chart 1- 1. System Block Diagram

Rev 0.1A | 7/100 Page

www.hoperf.com

AN261-CMT2186A User Guide
2 System Operating Process and Working Mode
2.1 System Operating Process
The system operation process of CMT2186A is shown as follows:

POR power on reset RSTn pin reset
BOR voltage detection reset Watchdog reset

Initial power on

Yes The burner burns

MTP burning mode

MTP through S3S

Yes Online debug mode
No

The debugger downloads program through 1-Wire and
debugs it

Internal handling during initial power-on
(Module correction, MTP configuration takes effect)

Complete poweroff

User code operation

Enter into

Shutdown

Yes

Shutdown mode

No Enter into IDLE
Yes
CPU is suspended in IDLE state

No Enter into STOP
Yes
Unlock ULPLDOIn sleep state Retention)

Yes

POR or

RSTn reset

Yes

Interrupt wakeup

No Interrupt wakeup
Yes
Unlock DLDO and clock
Restart MTP

Chart 2- 1. System Operating Process Chart

Rev 0.1A | 8/100 Page

www.hoperf.com

AN261-CMT2186A User Guide
As shown in the chart above, the initial chip power-on is triggered by enabling the DVDD pin and resetting the POR. When the RSTn pin and the BOR voltage detection are reset, as well as the watchdog reset takes effect, the chip will enter the power-on process, which is hereinafter referred to as “power-on”. After power-on, a 6 ms time window will be opened, and if the burning command triggered by the S3S serial port is detected in the window, it will enter the burning mode, allowing the burner to burn the internal MTP; If a debug command triggered by the 1-Wire interface is detected in the window, it goes into debug mode, allowing users to debug user code through the Keil C51 software and debugger. After burning or debugging complete, the chip needs to be powered off before other operations to enabling again.

If the burn mode or debug mode is not triggered within 6 ms after power-on, the chip will continue the internal processing of the initial power-on, including power and clock correction, and configuration in the MTP Config area. The user code will then start to run from address 0x0000, during which the user can configure registers to put the chip into SDN, IDLE, or STOP mode. In SDN mode, it can only be wakeup by power-on reset or external pin reset. In IDLE mode, it can be wakeup by interrupts caused by I/O level changes or comparator output reversals. In STOP mode, user can wake up interrupts caused by I/O level change, sleep timer timeout, or comparator output, after which user can turn on the DLDO, clock, and MTP of the digital circuit power supply, so that the user code can make the chip to run under the pre-sleep state.

2.2 System Operating Mode

The chip has the following four working modes:

Table 2-1. Working Modes of CMT2186A

Working Mode Normal IDLE
STOP (Retention)
SDN

Description
Normal Status
DLDO enabled System ClockHFOS or XOSCenabled CPU kernal suspended Peripherals work ULPLDO enabled System ClockHFOS or XOSCdisabled CPU core save all the storage, peripheral
configurations: and state. LFOSC enabled, Always-On module and
comparator work GPIO state remain unchanged ULPLDO disabled System ClockHFOS or XOSCdisabled

Mode
User program will automatically enter after burning and powered on
Set the IDLE bit in the PCON register
Set the STOP bit in the PCON register
Set the SLEEP bit in the AON_SFR_03 register
1.Set the PD_LFOSC bit in register AON_SFR_04 to disable LFOSC.

Wakeup source
None
I/O level change Comparator output

I/O level change

Comparator

output flipping

Sleep

timer

timed out

I/O level change Power on reset

Rev 0.1A | 9/100 Page

www.hoperf.com

AN261-CMT2186A User Guide

Working Mode

Description

Mode

Wakeup source

CPU core save all the storage, peripheral 2.Set the TIMER_SLEEP_EN bit in the RSTn pin reset

configurations: and state.

HV_SFR_02 register to turn off the

LFOSC enabled, Always-On module and sleep timer.

comparator disabled

3. Set the STOP bit in the PCON

GPIO state remain unchanged

4.Set the SLEEP bit in the

AON_SFR_03

Comparing from the power consumption in all four modes, Normal > IDLE > STOP > SDN. CMT2186A has two power pins, the AVDD supply power to the internal RF circuit, and the DVDD supply power to the Always-On digital module and the analog module except RF. Most of the digital modules work under the built-in DLDO and can be switched to ULPLDO power supply at STOP to achieve low leakage Retention mode.

The Retention mode allows the chip to recover from its previous state immediately after a STOP wake-up and continue working without having to restart the program. In Retention mode, all RAM data is stored; MTP and EEPROM data can be stored without power.

Table 2-2. CMT2186A Stores Contents in STOP Mode

Storage
MTP EEPROM
IRAM XRAM

Saving data

Power Supply Mode File Save File Save ULPLDO ULPLDO

In Retention mode, both power-on reset (POR) and real-time voltage Monitor (Power Monitor) remain in working state. The following lists whether all functional modules save the SFR configuration and working status, whether they work, and their corresponding power supply mode.

Table 2-2. CMT2186A Stores Contents in STOP Mode

Number

Module name

Configuration Save State
saved

Work status

Power Supply Mode

Watch Dog Timer

DVDD

Rev 0.1A | 10/100 Page

www.hoperf.com

AN261-CMT2186A User Guide

Number

Module name

Configuration Save State
saved

Work status

Power Supply Mode

Sleep Timer

DVDD

Key Scan

DVDD

Comparator 0

DVDD

Comparator 1

DVDD

UID & CFG Register

DVDD

IO Configuration Status

DVDD

1T-8051 core

ULPLDO

Timer 0

ULPLDO

Timer 1

ULPLDO

UART

ULPLDO

Port 0

ULPLDO

Port 1

ULPLDO

SPI

ULPLDO

Timer A

ULPLDO

Timer B

ULPLDO

CDR

ULPLDO

Sub-1G Transmitter

ULPLDO

LBD

Power off

1-Wire Debug

Power off

In the above table, numbered 1-7 modules exist in the Always-On (Always powered on) area, which is referred

to as the AON area below. This area is directly powered by DVDD, and the leakage of the module is very small

when it is not working. Among them, the watchdog, sleep timer, key scan, and two comparators can all enable

or disable in STOP mode according to user configuration; However, IO configuration and status do not change

in STOP mode in UID & CFG register.

CPU cores and peripherals of modules from 8 to 13 are driven by MCU_CLK. All configurations and current status of this part of circuit are saved in STOP mode with no other operation.

Modules of 14 – 18 are peripherals driven by SYS_CLK, of which all the circuit configurations are saved under STOP mode, while not saved the current working sate. User does not need to reconfigure the modules after wakeup, and will start working again, which is somehow like module reset automatically.

Rev 0.1A | 11/100 Page

www.hoperf.com

AN261-CMT2186A User Guide
Modules 19 -20 are the power off modules under STOP mode, which will not save any content.
2.3 Protect Mechanism
In order to ensure the chip security after burning, there is a security mechanism designed inside the chip. There is a READ_LOCK protection bit in the Config area of MTP. When this protection bit is burned, the user code and configuration of MTP cannot be read by S3S. If the user needs to unlock, the MTP can be re-burned through the burner, during which the original user code and configuration will be erased, including the READ_LOCK bit.
3 Debugging and Burning Interfaces
3.1 1-WIRE Online Debugging and Burning Interfaces
CMT2186A can be connected to the PC through the CMT2186A emulator of CMOSTEK for online debugging and MTP burning. The following shows figure of tool connection and interface connection between the debugger and CMT2186A. It should be noted that the 1-Wire debugging interface needs to occupy pin D10, and it is recommended that the user leave this pin empty during the debugging phase. MTP burning is implemented through the three-wire S3S interface.

SMA

Run COM USB

CMT2186A

LED

CMOSTEK
www.cmostek.com

Simulator
CMT2186A

CMT2186A 1-Wire Simulator

USB B-TYPE

CMT2186A-EB or CMT2186A-DM
Chart 3-1. 1-Wire Tool Connecting Diagram

1-WIRE online debugging interface, general functions can be achieved in Keil C51 platform: Full speed operating, stop, single step execution, multi-step execution and other debugging modes; Supporting for software breakpoints (arbitrarily); Supports 3 hardware breakpoints Read and write R0~R7, part of the system status register, memory and other internal storage; Reset keyRST symboldisabledit can only ahieved by using the exit: to reconnect.

Rev 0.1A | 12/100 Page

www.hoperf.com

Run, Stop, Step

Breakpoint

AN261-CMT2186A User Guide

system status and r0~r7

memory data

Chart 3-2. 1-Wire debugging screenshot on Keil C51
3.2 S3S Bus Burning Interface
The S3S bus is used for burning MTP, which is limited to burning and production tools, and is generally not open to users. If it was required to know the specific timing and communication protocol of S3S bus, please contact sales or agents of HOPERF.

SMA

Run COM USB

CMT2186A

LED

CMOSTEK

Programmer

www.cmostek.com CMT216xA & CMT2186A

CMT2186A 1-Wire Simulator

USB B-TYPE

CMT2186A-EB or CMT2186A-DM
Chart 3-3. Online burning tool connection diagram

Rev 0.1A | 13/100 Page

www.hoperf.com

XTAL
CMT2186A-ESR16
SOP16
GND DVDD & AVDD

5
X1
8 2 & 7

D6/S3S_CSB 11 D7/S3S_SCL 15 D8/S3S_SDA 14

13 D10/1-Wire

GND VCC

AN261-CMT2186A User Guide

Burner/simulater interface

S3S_CSB/D6

S3S_SCL/D7 S3S_SDA/D8 1-Wire/D10

Only for simulator

Chart 3-4. Burning/simulation Interface Connection Diagram

4 T8051XC3 Micro Controller

4.1 Processor Architecture
CMT2186A adopts T8051XC3 as the core controller of the system, including an enhanced 1T-8051 kernal, single period operating instruction, which is compatible to the MCS-51 command serial. The structure is shown as Chart 4-1.

CODE / XDATA
IDATA

CPU Core ALU
Decoder BIU

T8051XC3

PMU

Interrupt Control

Timer 0

Timer 1

SFR

1-Wire Debug

Serial 0

Port 0

Port 1

Chart 4- 1. T8051XC3 System Block Diagram

As shown in the figure, T8051XC3 includes the following parts:

The CPU core is composed of BIU bus interface unit, Decoder instruction decoding unit, and ALU

Rev 0.1A | 14/100 Page

www.hoperf.com

AN261-CMT2186A User Guide
arithmetic logic unit The power management unit supports IDLE and STOP modes Interrupt control unit supports up to 8 external interrupts with level 2 interrupt priority control Two timers, Timer 0 and Timer 1 One serial port, Serial Port 0, can implement UART mode An 11-bit parallel port, Port0 and Port1[1], is limited by the numbers of I/Os, and Port1 is only
available in low 0-3 bits Single-wire (1-WIRE) online debugging module, support Keil C51 platform for software programming
development and debugging

Note: [1] Port0 and Port1 come with the T8051XC3 kernel and are not directly equivalent to the GPIO of the chip. Comparing to the CPU kernal, the GPIO belongs to peripheral and Port0 and Port1 can be mapping to GPIOs.

T8051XC3 adopts an 8-bit SFR bus to connect the above mention peripherals. CMT2186A supports more peripherals, which are connected to the kernel via the SFR bus. In addition, the kernel uses a separate IDATA bus to connect to internal storage IRAM, and a shared CODE/XDATA bus to connect to MTP and XRAM respectively.

4.2 Instruction sets:

The 8051 instruction set consists of 111 instructions, each consisting of 1,2 or 3 bytes. Instruction execution is calculated in a single clock cycle. See Appendix A for more information of all instructions and their execution cycles.

4.3 8051 Core Initial Register

The core 8051 initial associated register group is shown in the following table. For the specific content and meaning of each register, please refer to the CMT2186A Register Detailed Manual.

Table 4-1. Initial Registers of 8051 Core

Name
P0
SP DPL DPH PCON

SFR Page
0
0 0 0 0

Address
0x80
0x81 0x82 0x83 0x87

Default Values
0x00
0x00 0x00 0x00 0x00

Funtion
Port0 register, support bit access, corresponding to eight kernel ports of P0.0-p0.7 Stack Pointer Register Data pointer (DPTR) register, low 8 bits Data pointer (DPTR) register, high 8 bits Power Control Register

Rev 0.1A | 15/100 Page

www.hoperf.com

Name
TCON TMOD
TL0 TL1 TH0 TH1
P1
SCON0 SBUF0
IEN0 IPL0 PSW ACC IEN1
B IRCON1
IPL1

SFR Page
0 0 0 0 0 0
0
0 0 0 0 0 0 0 0 0 0

AN261-CMT2186A User Guide

Address
0x88 0x89 0x8A 0x8B 0x8C 0x8D
0x90
0x98 0x99 0xA8 0xB8 0xD0 0xE0 0xE6 0xF0 0xF1 0xF6

Default Values
0x00 0x00 0x00 0x00 0x00 0x00
0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00

Funtion
Timer0 and Timer1 Control Registers Timer0 and Timer1 Working Mode Registers Timer0 register low 8 bit Timer1 register low 8 bit Timer 0 register high 8 bit Timer1 register high 8 bit Port1 register, support bit access, corresponding to eight kernel ports from P1.0 – P0.7. Due to the I/O numbers, only P1.0 P1.3 can be accessed. Serial port control register Serial port data cache register Interrupt enabling register 0 Interrupt priority register 0 Program status/ marking register Accumulated Register Interrupt enabling register 1 B Register Peripheral interrupt request flag register Interrupt priority register 1

Rev 0.1A | 16/100 Page

www.hoperf.com

5 Memory Structure
5.1 Introduction
The CMT216xA on-chip storage architecture is shown in Chart 5-1.

AN261-CMT2186A User Guide

0xFFFF

CODE

Unused

0x0200 0x0FFF
0x0000

4K Bytes MTP (code)

CONFIG

512 Bits

0x0040

MTP (ID & Config) 0x0000

0xFF
0x80 0x7F
0x30 0x2F 0x20 0x1F 0x00

IDATA / DATA

Upper 128 Bytes IRAM
(Indirect Access)

Special Function Registers Page 0 (Direct Access)

Special Function Registers Page 1 (Direct Access)

Lower 128 Bytes IRAM
(Direct or Indirect Access)
Bit-Addressable
Working Registers

0xFFFF

XDATA

Unused

0x0200 0x01FF
0x0000

512 Bytes XRAM

Chart 5-1. CMT2186A Storage and Logical Address
CMT2186A storage area consists of 3 spaces.
Program Code Space The space where 8051 kernel code is stored and loaded to run, the carrier is 4K Bytes MTP that can be erased multiple times. MTP also supports configuration space of 512 bits for storing user IDs and some specific configurations of chip features. The contents of the code and configuration space are burned through the burner. The entire 4KB code space is available to the user, and the code starts executing at 0x0000.
Internal Data Space The 8051 kernel contains 256 bytes of internal data space for fast access by the MCU. The internal DATA space can be divided into DATA, IDATA and SFR according to the access method, which is corresponding to the key words in the Keil C51 compiler, and the carrier is 256 Bytes of IRAM and SFR registers respectively. SFR is divided into two pages, which can be selected with the SFR_PAGE_SEL bit.
External Data Space Storage of 8051 external data, XDATA is stored in 512 bytes of XRAM. Users can also store specific
data that needs to be saved at power off in the 512-bit EEPROM, which can be accessed via SFR. In addition, there are some AON_REGS in the AON region, these registers are mainly used to configure

Rev 0.1A | 17/100 Page

www.hoperf.com

AN261-CMT2186A User Guide
and control the modules and I/O of the AON region. Users can access them indirectly through SFR.

Table 5-1. Internal memory description;

Storage space

Storage

Logic address Capabilities

Description

Program Code Space

MTP

0x0000 – 0x0FFF

4K bytes

User program run space, Keil C51 needs to use the keyword code to define variables.

IDATA low level bits, it can be both directly and indirectly accessed. In addition, a 16-byte

Internal Data Space

IRAM

0x00 – 0x7F 0x80 – 0xFF

128 bytes 128 bytes

addressable space is provided in the address range 0x20-0x2F. Keil C51 can be defined with the keyword data or idata, and variables accessed by bit can be defined by sbit. IDATA high level bits can be access indirectly. Keil C51 has to uses keywords.to define idata.

8051 can directly access the special feature register

SFR

0x80 – 0xFF

145 bytes

among the address range in internal RAM, including 2 pages of Page 0 and Page 1, which compare through SFR_PAGE_SEL bit of SFR.

XRAM

0x0000 – 0x01FF

512 bytes

Keil C51 needs to use the keyword code to define variables.

External Data Space

EEPROM

0x00 – 0x1F

512 bits

16 Bit x 32 multi-programming memory. The kernel is accessed indirectly through SFR, or through the open source API program alignment to increase its usage.

AON REG

0x00 – 0x1F

32 bytes

Registers located in the AON region are indirectly accessed by the kernel via SFR.

Notes: [1]. After MTP is programmed, the burnt data (user program) will not be lost regardless of whether the system is powered or not, or which mode the system is operating in.

[2]. After the EEPROM is rewritten (requires the power supply being stable during the rewriting process), the rewritten data

will not be lost regardless of whether the system is powered or not, or which mode the system is operating in. [3] AON REG is in the regin of AONcontent will not lost so long as the DVDD keeps powering. [4] Content of IRAMXRAM and some SFR can save under STOP mode.

5.2 Special Feature RegistersSFR

8051 kernel can access SFR directly for it is the internal memory space. CMT2186A serial products are rich in features and related configured SFR, so we do access distribution by page, that is Page 0 and 1. Page 0 contains most of the peripheral configuration and control, and Page 1 contains registers of the EEPROM and the PA power configuration. Therefore, it is necessary to confirm that the Page point is correct when you

Rev 0.1A | 18/100 Page

www.hoperf.com

AN261-CMT2186A User Guide
directly access the corresponding SFR, otherwise it is easy to cause configuration errors.

The SFR is powered by the ULPLDO in STOP mode, ensuring that most configurations of the peripherals can be saved in low leakage.

5.3 Always-on Domain Register (AON REG)

The always on (AON) domain system is powered directly by DVDD and it contains the watchdog, sleep timer, I/O change detection, and 32-byte register AON REG. Users can access AON REG indirectly through the AON_ADDR, AON_WDATA, and AON_RDATA registers in SFR. The objects controlled and configured by these registers include: the three peripherals in the AON domain above, the two analog comparators, and all I/Os. At the same time, there are 8 bytes in the AON REG, and when the chip is powered on for the first time, the system will automatically copy the 64 bit user ID in the MTP to the 8 byte register, which is convenient for users. Users are also free to use the 8-byte register for other purposes.

5.4 Memory Running Access Mode

The Memory Running Access Mode is shown in Table 5-2.

Table 5-2. Memory Running Access Mode

Memory Type

Access Method

Example

CODE

Constant definition in the program, using uint8_t code array[3] = {0x12, 0x34, 0x56 };

keyword “code”

XDATA

Variable definition in the program, using uint8_t xdata tx_buf[64];

keyword “xdata”

IDATA

Variable definition in the program, using uint8_t xdata tx_buf[3];

keyword “idata”

SFR

Direct Access Address[2]

IEN0= 0x00;

AON REG

Access through SFR[1]

None

EEPROM

Access via SFR, or API functions[2]

None

Notes:

[1] The official will show how to access these registers. [2] The official will show how to access these registers and the API source code. The API can be used to increase the

number of EEPROM erasing times.

Rev 0.1A | 19/100 Page

www.hoperf.com

6 Reset Structure
The CMT2186A has four reset systems, including:

AN261-CMT2186A User Guide

Power on reset POR The POR is enabled only once when the DVDD is powered on.

Voltage detection reset (BOR) BOR is generated when abnormal fluctuations occur in DVDD to avoid chip confusion.

Pin Reset RSTn The reset pin RSTn multiplexes D0 pin and it is enabled by default. Users can disable it after
power-on if there is no need to use this function.

Watchdog ResetWDT_RSTn Watchdog reset is a reset that prevents the program from running away or the system from crashing.
When the user program is running normally, it is necessary to periodically “feed the dog” to avoid reset caused by the timeout of the watchdog timer.

These four resets all have the same effect, that is, after the reset is triggered, the chip will be re-powered for the first time.
7 Clock Structure

7.1 Clock Source
The CMT2186A has three master clock sources, namely the 26 MHz high speed crystal oscillator XOSC, the 24 MHz internal high speed RC oscillator HFOSC, and 32 kHz internal low speed RC oscillator LFOSC. A refined clock gating mechanism is embeded inside the chip so that users can save as much power as possible.

Rev 0.1A | 20/100 Page

www.hoperf.com

AN261-CMT2186A User Guide

Analog

13 MHz / 2
Sub-1G TX PLL Reference

Digital Core

tx_clk
G

div_bypass

1 mcu_clk

/ n

debug_clk
G
cpu_clk
G
ana_clk
G
ee_clk
G
ioint_clk
G
port0_clk
G
port1_clk
G
timer0_clk
G
timer1_clk
G
uart_clk
G

XOSC 26 MHz
24 MHz HFOSC

hfosc_xo_sel

hfosc_div2_en

/ 2

32 kHz LFOSC

sys_clk

lfosc_clk (for calibration)

Digital AON
lfosc_clk

spim_clk
G
spis_clk
G
timera_clk
G
timerb_clk
G
cdr_clk
G
lbd_clk
G
lfcal_clk
G
hfcal_clk
G
sltimer_clk
G
watchdog_clk
G

Chart 7-1. System Block Diagram

As shown in the figure above, the XOSC serves as the reference clock for the Sub-1G wireless transmitter PLL and is used to drive the digital transmission control and adjustment module after frequency division. The system master clock (SYS_CLK) is provided from HFOSC by default, and HFOSC can be calibrated to ±1% accuracy. If user wants to improve the accuracy of the master clock, the relevant configuration can be configured when burning the MTP, so that the chip automatically switches the master clock to XOSC after powering on, and the accuracy can be improved to the accuracy of the crystal oscillator itself, such as ±10ppm, while increasing some power consumption. LFOSC provides clocks for sleep timers and watch dog specifically that can achieve ±1% accuracy after calibration.

Rev 0.1A | 21/100 Page

www.hoperf.com

7.2 Clock Calibration

AN261-CMT2186A User Guide

When the chip is shipped, HFOSC and LFOSC will be calibrated and the results will be burned to the MTP. The hardware correction module can also be invoked by manipulating the SFR register to correct the two clocks while using.

Calibration of HFOSC requires the use of XOSC as the reference clock. If there is no connection among the chip and external crystal oscillator while application (such as, non-wireles transmitting application), the XOSC cannot adapt normally, and HFOSC cannot be calibrated. Before correcting HFOSC, it is necessary to ensure that HFOSC serves as the clock source of SYS_CLK, set the HFOSC_DIV2_EN ratio in SFR to 1, and use the HFOSC clock as SYS_CLK after half frequency. This is to avoid excessive HFOSC frequency increase during the correction process, which will cause the system to malfunction.

Calibration of LFOSC requires SYS_CLK as the reference clock. If the user selects HFOSC as the clock source for SYS_CLK through MTP burning, it is recommended to correct HFOSC first and then LFOSC, for which the accuracy of HFOSC determines the accuracy of LFOSC.

The specific operation of correction can refer to the official open source routine code.
7.3 Clock Frequency Division
User can operate a frequency divider to divide SYS_CLK to generate MCU_CLK. The 8-bit frequency division coefficient of the divider can be configured from 1 to 255 except for 0. Therefore, the maximum operating frequency of MCU_CLK is 24 MHz (HFOSC) or 26 MHz (XOSC), and the minimum operating frequency is 94 kHz (HFOSC) or 102 kHz (XOSC).

SYS_CLK does not perform any frequency division during normal operation except for the situation described above at calibration (which will also affect MCU_CLK). Peripherals driven by SYS_CLK, the SPIM, SPIS, TIMERA, TIMERB, and CDR have their own operating frequency of SFR register configuration except for LBD, which uses a fixed clock frequency. Therefore, there is no need to operate frequency division of the driver clock.

LFOSC_CLK drives the sleep timer and the watchdog timer directly without any frequency division processing.

7.4 Clock Gate Control

In order to give full play to the characteristics of low power consumption of the chip, the chip provides a unique clock gate for each module, which are not only control the clock of the module itself, but also control the clock

Rev 0.1A | 22/100 Page

www.hoperf.com

AN261-CMT2186A User Guide
of the corresponding SFR register. Clock gating is turned on by default. It is recommended that the user turn off the gated clock of the module that does not need to work immediately at the beginning of the program after configuring all SFR, and turn on the clock only when the module needs to be configured, controlled, and used.

The following shows the corresponding control module for each clock gate, as well as the detailed SFR register:

Chart 7-1. Clock Gating of the Corresponding Modules and Registers

Clock Gate Control
TX_CLK_EN
CPU_CLK_EN

Module
OOK / ASK Transmitting controller and
modulator
CPU kernal

SFR Page
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 None

DEBUG_CLK_EN

1-Wire debugger

None

EE_CLK_EN

EEPROM controller

SFR Address
0xDD 0xDE 0xDF 0xE1 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF2 0xF3 0xF8 0xF9 0xFA 0xFB 0xFC None
None
0x2A 0x2B 0x2C 0x2D 0x30 0x31 0x32

SFR Name
ANA_CTL_0 ANA_CTL_1 ANA_CTL_2 ANA_CTL_3 PLLN PLLK_H PLLK_M PLLK_L TX_DR_0 TX_DR_1 TX_DR_2 TX_SYM_BYTE TX_SYM_CTL TX_PKT_CTL RAMP_STEP_H RAMP_STEP_L PA_IDAC_CODE LBD_CTL_0[1] LBD_CTL_1[1] Switch automatically according to the working mode Switch automatically based on whether to enter the debugging mode EE_CTL EE_ADDR EE_WDATA_H EE_WDATA_L EE_RDATA_H EE_RDATA_L EE_STA

Rev 0.1A | 23/100 Page

www.hoperf.com

Clock Gate Control

Module

IOINT_CLK_EN

IO and Interrupt Controller

PORT0_CLK_EN PORT1_CLK_EN TIMER0_CLK_EN
TIMER1_CLK_EN
UART_CLK_EN

Port 0 Port 1 Timer 0
Timer 1
UART 0

ANA_CLK_EN

Analog circuit controller

SPIM_CLK_EN SPIS_CLK_EN

SPI master machine SPI slave machine

TIMERA_CLK_EN

Timer A

SFR Page
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SFR Address
0x33 0x92 0x93 0x94 0x95 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA9 0xAA 0xAB 0xAC 0xAD 0xB0 0xB1 0x80 0x90 0x8A 0x8C 0x8B 0x8D 0x98 0x99 0xE2 0xE3 0xE4 0xE5 0xE7 0x96 0x97 0x96 0x97 0xB7 0xB9 0xBA 0xBB 0xBC

AN261-CMT2186A User Guide
SFR Name
EE_MANU INTCTL_0 INTCTL_1 INTCTL_2 INTCTL_3 GPIO_INA_SEL GPIO_INB_SEL GPIO_INC_SEL GPIO_IND_SEL GPIO_INE_SEL GPIO_INF_SEL GPIO_ING_SEL GPIO_OUTA_SEL GPIO_OUTB_SEL GPIO_OUTC_SEL GPIO_OUTD_SEL GPIO_OUTE_SEL GPIO_OUTF_SEL P08051 Initial Register P18051 Initial Register TL08051 Initial Register TH08051 Initial Register TL18051 Initial Register TH18051 Initial Register SCON08051 Initial Register SBUF08051 Initial Register ANA_CTL_4 ANA_CTL_5 ANA_CTL_6 ANA_CTL_7 ANA_CTL_8 SPI_CTL_0 SPI_CTL_1 SPI_CTL_0[2] SPI_CTL_1[2] TACLK_DIV_H TACLK_DIV_L TAC_H TAC_L TACCR0_H

Rev 0.1A | 24/100 Page

www.hoperf.com

Clock Gate Control

Module

TIMERB_CLK_EN

Timer B

CDR_CLK_EN

Clock restorer

LBD_CLK_EN LFOSC_CLK_EN HFOSC_CLK_EN SLTMR_CLK_EN

Low voltage detector LFOSC calibration LFOSC calibration Sleep timer

SFR Page
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 None None None None

WDG_CLK_EN

Watchdog Timer

None

SFR Address
0xBD 0xBE 0xBF 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0x9D 0x9E 0x9F None None None None
None

AN261-CMT2186A User Guide
SFR Name
TACCR0_L TACCTL0_H TACCTL0_L TACCR1_H TACCR1_L TACCTL1_H TACCTL1_L TACCR2_H TACCR2_L TACCTL2_H TACCTL2_L TACNT_H TACNT_L TBCLK_DIV_H TBCLK_DIV_L TBC_H TBC_L TBCCR0_H TBCCR0_L TBCCTL0_H TBCCTL0_L TBCCR1_H TBCCR1_L TBCCTL1_H TBCCTL1_L TBCCR2_H TBCCR2_L TBCCTL2_H TBCCTL2_L TBCNT_H TBCNT_L CDR_DR_0 CDR_DR_1 CDR_DR_2 Only control the LBD module[1] Only control the LFOSC module[3] Only control the HFOSC module[3] Switches automatically through the AON_REG switch module[4] Switches automatically through the

Rev 0.1A | 25/100 Page

www.hoperf.com

AN261-CMT2186A User Guide

Clock Gate

Module

SFR

SFR Name

Control

Page

Address

AON_REG switch module[4]

Notes:

[1] The configuration of the LBD register affects part of the TX circuit function, so the gated clock is drivenby TX_CLK_EN,

and the LBD_CLK_EN gated clock only drives the LBD module itself. It is necessary to detect the battery voltage before the

transmission to compensate the transmission power in operation, so it is recommended that user turns on TX_CLK_EN and

LBD_CLK_EN at the same time before transmission. If user needs to use the LBD module alone when not

transmitting,enabling TX_CLK_EN to use the LBD_CTL_0 and LBD_CTL_1 registers, and opening LBD_CLK_EN to make

the LBD module work.

[2] When SPIM_CLK_EN = 1 or SPIS_CLK_EN = 1, the clocks of both the SPI_CTL_0 and SPI_CTL_1 registers are turned

on.

[3] When using the LFOSC or HFOSC correction module, it is control by the ANA_CTL_8 register, so ANA_CLK_EN is set

to 1.

[4] All AON_REG does not require clock gating, and the clocks are only turned on when the CPU accesses them.

7.5 Related Register

Table 7-2. Related Register of System Clock

Name
CLK_GATE_0 CLK_GATE_1 CLK_GATE_2 MCU_CLK_DIV

SFR page
0
0 0 0

address
0x84 0x85 0x86 0xFD

default values
0x7F
0xFF 0x7F 0x01

Function
Port0 register, support bit access, corresponding to of P0.0-p0.7 Stack Pointer Register Data pointer (DPTR) register, low 8 bits MCU_CLK frequency divider coefficient

eight kernel ports

Rev 0.1A | 26/100 Page

www.hoperf.com

8 Interrupts and Wakeup

AN261-CMT2186A User Guide

8.1 Introduction

The interrupt control of CMT2186A has two main functions:
The first: interrupt the current running process, and prioritize the interrupt service process;
The second: wake up the system from low power mode;
The first function play the same role as the traditional microcontrollers, which is to response to interrupt handling during program operation, supported by all interrupt sources. The second function is to meet the needs of low-power applications, which is woke up through interruptions after the system enters all the low-power modes. In this case, only a limited number of interrupt sources can support the wakeup function. Here we call the interrupt source that can support wake up “wake up source” in order to better understand its working mechanism. Wake source and low power mode are related to each other, here are detail information of three low power modes of CMT2186A:
IDLE Mode In IDLE mode, the 8051 kernel and the clock of the CPU_CLK will stop working, while the MCU_CLK will not stop. Thus, the initial and the system peripherals still work normally. This is the reason that the IDLE mode can be enabled by the interruption of these two peripherals.
STOP Mode In STOP mode, the chip enters into sleep state and the MCU power supply switches from DLDO to ULPLDO to save the current working state with low power consumption. At this time, all clocks except LFOSC stop and can only rely on interrupts in the AON area to wake up, including I/O level changes, sleep timer timeout, and analog comparator output flip. If the user does not use sleep wakeup, the LFOSC and sleep timer can also not be turned on before entering STOP mode, which can further save power.
SDN Mode The way to enter SDN mode is also to set the STOP register bit, but it has to close ULPLDO and LFOSC at first, as well as all I/O input level detection in the AON area (if not, I/O flipping may cause false wake-up and make the chip work incorrectly). In SDN mode, since both DLDO and ULPLDO are disabled, all clocks are stopped, only POR power-on reset or RSTn pin reset can power the chip back on.

8.2 Wakeup Source

As mentioned in the previous section, only system peripherals in the normally open domain can support

Rev 0.1A | 27/100 Page

www.hoperf.com

AN261-CMT2186A User Guide
wakeup system in STOP mode, which we call the wakeup source. The wakeup source of CMT2186A mainly comes from the following three functional modules:
I/O Change Scan Module The D0-D11 of CMT2186A can support this function. Users need to configure the GPIO that needs to
detect wake-up before entering the STOP mode.
Sleep Timer Module Low power sleep timer wakes up the STOP mode.
Analog Comparator Modular The analog comparator is used to compare two input signals. When the comparison results change, it
will trigger the interrupt wakeup system. User needs to configure the working mode of the comparator before entering the STOP mode.
8.3 Interrupt Source and Interrupt Control
The wakeup sources for CMT2186A have been described in the previous section. Since they support a pure wakeup system, it can also be understand as the wakeup source system. The CMT2186A interrupt source that will be introduced in this section is mainly associated with the 8051 operating, that is, the specific processing of the interrupt response based on the code operation.

The internal 8051 of CMT2186A supports 11 interrupt sources, namely: One Timer 0 interrupt One Timer 1 interrupt One Serial 0 (i.e. UART) interrupt; Eight external interrupt (hereinafter referred to as INT);

Each interrupt source can be independently enabled and a 2-level interrupt priority can be configured. Table 8-1 lists the interrupt vectors corresponding to the 11 interrupt sources and the corresponding interrupt source relationships.

Table 8-1. CMT2186A Interrupt Vector

Interrupt signal 0 1 2 3

Interrupt Vector 0x0003 0x000B 0x0013 0x001B

Interrupt source
External interrupt 0 Timer 0 interrupt
External interrupt 1 Timer 1 interrupt

Interrupt Request signal
IE0 TF0 IE1 TF1

Interrupt enable control
EX0 ET0 EX1 ET1

interrupt priority
IPL0[0] IPL0[1] IPL0[2] IPL0[3]

Rev 0.1A | 28/100 Page

www.hoperf.com

AN261-CMT2186A User Guide

0x0023

UART Interrupt

TI0/RI0

ES0

IPL0[4]

0x004B

External interrupt 2

IE2

EX2

IPL1[2]

0x0053

External interrupt 3

IE3

EX3

IPL1[3]

0x005B

External interrupt 4

IE4

EX4

IPL1[4]

0x0063

External interrupt 5

IE5

EX5

IPL1[5]

0x006B

External interrupt 6

IE6

EX6

IPL1[6]

0x0073

External interrupt 7

IE7

EX7

IPL1[7]

Notes:

The T8051XC3 core controller has a minimum interrupt response time of 3 system clocks, which are provided by the

internal 24MHz RC oscillator HFOSC or the external 26MHz crystal oscillator XOSC.

8.4 External Interrupt Mapping

There are 11 interrupt sources supported by the T8051XC3 mentioned above. Except for the three interrupt sources of Timer 0, Timer 1 and UART are non-selectable interrupt trigger sources, the other eight external interrupts can be flexibly selected as the interrupt sources. The CPU core is connected to the peripheral interrupt sources via the INT BUS (interrupt bus). There are 27 external interrupt sources, listed as follows:

I/O input interrupt function, D0-D11,a total of 12; Timer A/B module, each group of timers has 4 interrupts, a total of 8; 1 FIFO blank signal interrupt triggering of Sub-1G transmitting module; 2 SPI module transmitting and receiving data interrupt triggering; 2 Comparator output interrupt; 1 CDR output interrupt; 1 sleep timer interrupt

External interrupts INT0 and INT1 are used to connect the three wake sources, INT2- INT7 are used to connect the interrupt sources of each peripheral and I/O, and the mappings are different. The following uses INT0, INT1 and INT2 as examples to draw the interrupt structure diagram.

As shown in the figure below, INT0 is connected to the comparator interrupt and IO input interrupt, and any comparator or I/O edge detection will trigger INT0 to be used as the wakeup source in STOP mode; INT1 is fixed to the sleep timer interrupt and is also used as a wakeup source in STOP mode. After the CPU is woken up, it enters into the interrupt response program. User can query the FLAG by SFR to determine the specific interrupt that wakes up the system and perform related processing. INT2 mainly maps to peripheral interrupts, and I/O interrupts only maps to D0-D3. Noted that in this case, changes in D0-D3 will affect INT0 and may map to INT2. Users should configure interrupt enabling and mapping appropriately, using INT0 when stopping and

Rev 0.1A | 29/100 Page

www.hoperf.com

INT2 when the program is running.

AN261-CMT2186A User Guide

COMP0_OUT COMP1_OUT
D0 D11

COMP0_FLAG COMP1_FLAG IO_CHANGE_FLAG

I/O Change Scan

(Rising / Falling

Edge Detection)

SLEEP_TMO_FLAG

Sleep Timer

TA_TMR_INT

Timer A Interrupts

TA_CCR0_INT TA_CCR1_INT

TA_CCR2_INT

TX FIFO Interrupt TX_SYM_EMPTY

SPI Interrupts

SPI_TXMTY SPI_RXNMTY

TB_TMR_INT

Timer B Interrupts

TB_CCR0_INT TB_CCR1_INT

TB_CCR2_INT

CDR Interrupt

CDR_CLK_OUT D0

Sync by SYS_CLK

D1
I/O Interrupts
D2
(Only map D0 D3 to INT2)
D3

INT2_SEL<3:0>
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

INT_POLAR<0>

INT0

INT_POLAR<2>

INT1

INT_POLAR<2>

INT2

Chart 8-1. Peripheral INT0, INT1 and INT2 Mapping
The following is a detailed mapping between INT2-INT7 and each interrupt source:

Rev 0.1A | 30/100 Page

www.hoperf.com

AN261-CMT2186A User Guide

Chart 8-2. Peripheral interrupt source and eight external interrupt mapping

Inter

Interrupt

rupt Selection

INT2_SEL = 0000

INT2_SEL = 0001

INT2_SEL = 0010

INT2_SEL = 0011

INT2_SEL = 0100

INT2_SEL = 0101

INT2_SEL = 0110

INT2

INT2_SEL = 0111 INT2_SEL = 1000

INT2_SEL = 1001

Interrupt source
TA_TMR_INT TA_CCR0_INT TA_CCR1_INT TA_CCR2_INT TX_SYM_EMPTY
SPI_TXMTY SPI_RXNMTY TB_TMR_INT TB_CCR0_INT TB_CCR1_INT

Descripti Inter Interrupt

Interrupt

rupt Selection

source

INT3_SEL = 0000 TA_TMR_INT

Timer A

INT3_SEL = 0001 TA_CCR0_INT

Interrupt

INT3_SEL = 0010 TA_CCR1_INT

INT3_SEL = 0011 TA_CCR2_INT

Transmitter

INT3_SEL = 0100 TX_SYM_EMPTY

Interrupt

SPI

INT3_SEL = 0101 COMP0_OUT

Interrupt

INT3_SEL = 0110 COMP1_OUT

Timer B

INT3

INT3_SEL = 0111 INT3_SEL = 1000

TB_TMR_INT TB_CCR0_INT

Interrupt

INT3_SEL = 1001 TB_CCR1_INT

Descript ion
Timer A Interrupt
Transmitter Interrupt Comparator interrupt
Timer B Interrupt

INT2_SEL = 1010 TB_CCR2_INT

INT3_SEL = 1010 TB_CCR2_INT

INT2_SEL = 1011 CDR_CLK_OUT
INT2_SEL = 1100 D0 INT2_SEL = 1101 D1 INT2_SEL = 1110 D2 INT2_SEL = 1111 D3

CDR Interrupt
I/O input Interrupt

INT3_SEL = 1011 CDR_CLK_OUT
INT3_SEL = 1100 D4 INT3_SEL = 1101 D5 INT3_SEL = 1110 D6 INT3_SEL = 1111 D7

CDR Interrupt
I/O input Interrupt

INT4_SEL = 0000 TA_TMR_INT

INT5_SEL = 0000 TA_TMR_INT

INT4_SEL = 0001 INT4_SEL = 0010 INT4_SEL = 0011 INT4_SEL = 0100

TA_CCR0_INT TA_CCR1_INT TA_CCR2_INT TX_SYM_EMPTY

Timer A Interrupt
Transmitter interrupt

INT5_SEL = 0001 TA_CCR0_INT INT5_SEL = 0010 TA_CCR1_INT INT5_SEL = 0011 TA_CCR2_INT INT5_SEL = 0100 TX_SYM_EMPTY

Timer A Interrupt
Transmitter interrupt

INT4_SEL = 0101 INT4 INT4_SEL = 0110
INT4_SEL = 0111 INT4_SEL = 1000 INT4_SEL = 1001 INT4_SEL = 1010

SPI_TXMTY SPI_RXNMTY TB_TMR_INT TB_CCR0_INT TB_CCR1_INT TB_CCR2_INT

SPI Interrupt
Timer B Interrupt

INT5_SEL = 0101 COMP0_OUT INT5 INT5_SEL = 0110 COMP1_OUT
INT5_SEL = 0111 TB_TMR_INT INT5_SEL = 1000 TB_CCR0_INT INT5_SEL = 1001 TB_CCR1_INT INT5_SEL = 1010 TB_CCR2_INT

Comparator interrupt
Timer B Interrupt

INT4_SEL = 1011 CDR_CLK_OUT INT4_SEL = 1100 D8

CDR Interrupt I/O input

INT5_SEL = 1011 CDR_CLK_OUT INT5_SEL = 1100 D0

CDR Interrupt I/O input

Rev 0.1A | 31/100 Page

www.hoperf.com

Inter rupt

Interrupt Selection

INT4_SEL = 1101

INT4_SEL = 1110

INT4_SEL = 1111

INT6_SEL = 0000

INT6_SEL= 0001

INT6_SEL = 0010

INT6_SEL = 0011

INT6_SEL = 0100

INT6

INT6_SEL = 0101 INT6_SEL = 0110 INT6_SEL = 0111 INT6_SEL = 1000 INT6_SEL = 1001 INT6_SEL = 1010 INT6_SEL = 1011

INT6_SEL = 1100 INT6_SEL = 1101 INT6_SEL = 1110 INT6_SEL = 1111

Interrupt source
D9 D10 D11 TA_TMR_INT TA_CCR0_INT TA_CCR1_INT TA_CCR2_INT TX_SYM_EMPTY
SPI_TXMTY SPI_RXNMTY TB_TMR_INT TB_CCR0_INT TB_CCR1_INT TB_CCR2_INT CDR_CLK_OUT
D4 D5 D6 D7

AN261-CMT2186A User Guide

Descripti Inter

rupt

Interrupt Selection

Interrupt source

Interrupt

INT5_SEL = 1101 D1

INT5_SEL = 1110 D2

INT5_SEL = 1111 D3

INT7_SEL= 0000 TA_TMR_INT

Timer A

INT7_SEL = 0001 TA_CCR0_INT

Interrupt

INT7_SEL = 0010 TA_CCR1_INT

INT7_SEL = 0011 TA_CCR2_INT

Transmitter

INT7_SEL = 0100 TX_SYM_EMPTY

interrupt

SPI

INT7_SEL = 0101 COMP0_OUT

Interrupt

INT7_SEL = 0110 COMP1_OUT

Timer B

INT7

INT7_SEL = 0111 TB_TMR_INT INT7_SEL = 1000 TB_CCR0_INT

Interrupt

INT7_SEL = 1001 TB_CCR1_INT

INT7_SEL = 1010 TB_CCR2_INT

CDR

INT7_SEL = 1011 CDR_CLK_OUT

Interrupt

INT7_SEL = 1100 D8

I/O input

INT7_SEL = 1101 D9

Interrupt

INT7_SEL = 1110 D10

INT7_SEL = 1111 D11

Descript ion
Interrupt
Timer A Interrupt
Transmitter interrupt Comparator interrupt
Timer B Interrupt
CDR Interrupt
I/O input Interrupt

External interrupts INT0 and INT1 support both level and edge interrupts, while INT2-INT7 supports only edge interrupts. The polarity of the interrupt trigger is selected by the user by configuring the relevant SFR, the level trigger can be selected as a high or low level trigger, and the edge trigger can be selected as a rising or falling edge trigger.
8.5 Related Register

Table 8-3. System related register groups

Name
TCON IEN0 IPL0

SFR page
0 0 0

address
0x88 0xA8 0xB8

default values
0x00 0x00 0x00

Timer 1 Control Registers Interrupt enabling register 0 Interrupt priority register 0

Function

Rev 0.1A | 32/100 Page

www.hoperf.com

Name
IEN1 IRCON1
IPL1 INTCTL_0 INTCTL_1 INTCTL_2 INTCTL_3

SFR page
0 0 0 0 0 0 0

AN261-CMT2186A User Guide

address
0xE6 0xF1 0xF6 0x92 0x93 0x94 0x95

default values
0x00 0x00 0x00 0x00 0x00 0x00 0x00

Function
Interrupt enabling register 1 Peripheral interrupt request flag register Interrupt priority register 1 INT0 – INT7 Interrupt polarity selected register INT2 and INT3 mapping configured registers INT4 and INT5 mapping configured registers INT6 and INT7 mapping configured registers

Rev 0.1A | 33/100 Page

www.hoperf.com

9 GPIO Module

AN261-CMT2186A User Guide

9.1 Basic Function
The CMT2186A series chips support up to 12 GPIOs, GPIO0 ~ GPIO11. GPIO2-GPIO5 supports digital ports and analog ports, and the rest only supports digital functions. The related operating modes are listed in the below table.

Table 9-1. GPIO Operating Modes

Property 1 Analog port

Property 2

Working Mode Analog input[1] Input mode only (floating input)

Input mode[3]

Input mode with pull-up

Digital port[2]

Input mode with pull-down

Output mode

Open-drain output Push-pull output

Notes:

[1]. The analog input port serves as input of two analog comparators; [2]. When it is used as a digital port, it is represented by D, such as D1, D2, etc., and the label corresponds to the serial number of

GPIO.

[3]. Only when the GPIO operates in input mode, can it select to enable the IOC level detection function; [4]. Support the selection of on-chip pull-up or pull-down with enabling control. The typical pull-up/ pull-down is 50 k. Meanwhile,

the pull-up also provides a very weak pull-up, typically a 500 k pull-up resistor.

9.2 GPIO Structure Introduction
The functional block diagram of D0 to D11 is shown below:

Rev 0.1A | 34/100 Page

www.hoperf.com

AN261-CMT2186A User Guide
Dn_open_drain Dn
Dn_out
OUTPUT
Dn_pd_odrv

Dn_pd_idrv ~Dn_pd_idrv

Dn_pd_pullup

Dn_pd_pullup2

50k

500k

~Dn_pd_idrv

Dn_in

50k

Dn_pd_idrv

Dn_pd_pulldown ~Dn_pd_pullup

INPUT

~Dn_pd_pullup2

Dn_pd_ana

ANALOG
Dn_ana

~Dn_pd_ana Chart 9-1. GPIO Functional Diagram

Table 9-2. Function Description of GPIOs

Port Name Dn Dn_open_drain
Dn_out Dn_pd_odrv

Signal type General IO PAD

Description

Configure signal

The corresponding Dn open drain value is set in the 0x19 register AON_REG_19 and 0x1A register AON_REG_1A. 0: open_drain, 1: push_pull;

System internal When Dn is the digital output mode, Dn_out is the internal output

control signal

signal.

System internal When Dn is used as the digital output mode, Dn_pd_odrv = 0,

Rev 0.1A | 35/100 Page

www.hoperf.com

Port Name Dn_pd_idrv
Dn_pd_pullup2
Dn_pd_pulldown Dn_pd_ana Dn_ana

AN261-CMT2186A User Guide

Signal type

Description

control signal

otherwise Dn_pd_odrv = 1;

When Dn is used as the digital input mode, Dn_pd_idrv = 0, otherwise

Dn_pd_idrv = 1

When the Dn is used as a digital input mode, the corresponding

Configure signal

registers are configured through the 0x15 registers AON_REG_15 and 0x16 registers AON_REG_16 to independently control whether the 50Kohm pull-up resistance of each Dn is enabled or not.

Dn_pd_pullup 0: Enable. 1 Disable

When Dn is entered in digital input mode, whether all the digital input

System control

Dn of 500Kohm weak pullup resistance is enabled or not can be internal
configured through the 0x10 register AON_REG_10[5] of
pd_pullup_500K.
0: Enable1: Disable ;

When the Dn is entered in digital input mode, the corresponding

registers are configured through the 0x17 registers AON_REG_17

System internal control signal

and 0x18 registers AON_REG_18 to independently control whether the 50Kohm pull-down resistance of each Dn is enabled or not. Dn_pd_pulldown 0: Enable1: Disable;

Note: When a pull-down resistor and a pull-up resistoris are enabled

at the same time, the pull-up resistor has a higher priority.

System internal control signal

When Dn is in analog I/O mode, the internal analog signal line is connected to the system internal control signal via the 0x10 register AON_REG_10[4:0] Dn_ana.

9.3 GPIO Digital Input
When GPIO is configured as a digital input:
the output part is disabled. Whether the pull-up/pull-down resistance is enabled depends on the configuration related to IO
pull-down in the AON register; The voltage on IO is sampled to the SFR registers of GPIO_IN_0 and GPIO_IN_1, which are
readable by the software.

9.4 GPIO Digital Output
Copyright © By HOPERF

Rev 0.1A | 36/100 Page

www.hoperf.com

AN261-CMT2186A User Guide
When GPIO is configured as output: the output channel is enabled. Open drain output mode
– If the output register is 0, the output NMOS is enabled. – If the output register is 1, the output NMOS and PMOS are disabled, and GPIO is in a high
resistance state. Push-pull output mode:
– If the output register is 0, the output NMOS is enabled and the output PMOS is disabled. – If the output register is 1, the output NMOS is disabled, and the output PMOS is enabled. In output mode, input mode is disabled and the input signal is pulled up internally, so GPIOn_in reads 1.
9.5 GPIO Analog Input and Output
When GPIO is configured in analog mode:
The digital output function is disabled. The digital input mode is disabled and the input signal is forced to pull up internally, so GPIOn_in
reads 1.
9.6 GPIO Digital Input Mapping
When the GPIO0-GPIO11 are in digital input mode, they are referred to as D0-D11, which can be used for I/O level flip detection to generate interrupts before the system clock SYS_CLK synchronization, and after synchronization they are used for the following three purposes:
As an external input to the various peripherals As an input source for external interrupts INT2-INT7 (described in the External Interrupt Mapping
section) As GPIO_IN_SFR<11:0>, user can read datas through the two SFR GPIO_IN_0<7:0> and
GPIO_IN_1<7:0>
The following figure shows configuration t0_gpio_sel<3:0> as the external input of peripheral Timer 0

Rev 0.1A | 37/100 Page

www.hoperf.com

AN261-CMT2186A User Guide

t0_gpio_sel<3:0>

Sync by

SYS_CLK

t0_in

D10

D11

I/O Change
Scan

ioc_detected

as INT2 INT7 sources
Read through GPIO_IN_SFR<11:0>

Chart 9-2. Functional Block Diagram of GPIO as Digital Inputs
By configuring the register t0_gpio_sel<3:0>, the user can select any digital input signal from D0-D11 that is synchronized by SYS_CLK to send to the external input t0_in of Timer 0. There are a total of 14 such as MUX, as shown in the following table:

Table 9-3. GPIO Input Mapping Register for each Peripheral

Peripheral Module

SFR

MUX Selection Signal T0_GPIO_SEL<3:0>

MUX Output t0_in

Timer 0

GPIO_INC_SEL

T0_INTN_GPIO_SEL<3: 0> T1_GPIO_SEL<3:0>

t0_int0_n t1_in

Timer 1 Timer A

GPIO_IND_SEL GPIO_INF_SEL

T1_INTN_GPIO_SEL<3: 0> TA_CCI0_GPIO_SEL<3: 0>

t1_int0_n ta_cci0_in

MUX Output Purpose
External signal input of the 8051 kernel initial peripheral Timer 0 Counting gate control input for the 8051 kernel initial peripheral Timer 0 External signal input of the 8051 kernel initial peripheral Timer 1 Counting gate input for the 8051 kernel initial peripheral Timer 1 One of the Timer A external capture source

Rev 0.1A | 38/100 Page

www.hoperf.com

AN261-CMT2186A User Guide

Peripheral

SFR

MUX Selection Signal MUX

MUX Output Purpose

Module

Output

TA_CCI1_GPIO_SEL<3: ta_cci1_in One of the Timer A external capture source

TB_CCI0_GPIO_SEL<3: tb_cci0_in One of the Timer B external capture source

Timer B

0> GPIO_ING_SEL
TB_CCI1_GPIO_SEL<3: tb_cci1_in

One of the Timer B external capture source

NSS_IN_GPIO_SEL<3:0 nss_in

Selected input of the SPI slave mode

> GPIO_INA_SEL
SCK_IN_GPIO_SEL<3:0 sck_in

Clock input of the SPI slave mode

SPI

MISO_IN_GPIO_SEL<3: miso_in

Data input of the SPI slave mode

0> GPIO_INB_SEL
MOSI_IN_GPIO_SEL<3: mosi_int

Data output of the SPI master mode

UART

RXD0_GPIO_SEL<3:0> GPIO_INE_SEL

rxd0_in

External input signal of the 8051 kernal initial peripheral UART

CDR

CDR_GPIO_SEL<3:0> cdr_in

External signal input of CDR

Notes:

[1] One GPIO input can be used as an external peripheral input, interrupt source, and map to the SFR at the same time,

and user needs to avoid functional conflicts through proper configuration.

9.7 GPIO Digital Output Mapping

When GPIO0-GPIO11 is used as a digital output, the output signal source can be configured by SFR and selected from the following table:

Table 9-4. Signal source that selected from the GPIOn

Select Item gpio_out_sfr[n] port0_out[n] Port1_out[n] ta_out0 ta_out1 ta_out2 tb_out0 tb_out1 tb_out2 sck_out nss_out

Function GPIO_OUT_0 and GPIO_OUT_1 registers Port0[7:0] output Port1[3:0] output Output of Timer A capture/comparison in module 0 Output of Timer A capture/comparison in module 1 Output of Timer A capture/comparison in module 2 Output of Timer B capture/comparison in module 0 Output of Timer B capture/comparison in module 1 Output of Timer B capture/comparison in module 2 Clock output of SPI master mode Selected output of SPI master mode

Rev 0.1A | 39/100 Page

www.hoperf.com

Select Item mosi_out miso_out
csb_out
fcsb_out
rxd0_out txd0_out
T0_ov t1_ov

AN261-CMT2186A User Guide
Function Data output of SPI master mode Data input of SPI slave mode Access register chip selection output of CMT specific 4-wire in SPI master mode Access FIFO chip selection output of CMT specific 4-wire in SPI master mode UART output enabling signal UART clock or data output Signal output of timer0 Module overflow Signal output of timer0 Module overflow

The mapping between GPIOn and each output signal source is shown in the following table:

GPIOn GPIO0 GPIO1

Table 9-5. Mappings between GPIOn and Function Module Output

SFR GPIO_OUTA_SEL GPIO_OUTA_SEL

Selected signal and code value GPIO0_OUT_SEL<3:0> = 4’d0 GPIO0_OUT_SEL<3:0> = 4’d1 GPIO0_OUT_SEL<3:0> = 4’d2 GPIO0_OUT_SEL<3:0> = 4’d3 GPIO0_OUT_SEL<3:0> = 4’d4 GPIO0_OUT_SEL<3:0> = 4’d5 GPIO0_OUT_SEL<3:0> = 4’d6 GPIO0_OUT_SEL<3:0> = 4’d7 GPIO0_OUT_SEL<3:0> = 4’d8 GPIO0_OUT_SEL<3:0> = 4’d9 GPIO0_OUT_SEL<3:0> = 4’d10 GPIO0_OUT_SEL<3:0> = 4’d11 GPIO0_OUT_SEL<3:0> = 4’d12 GPIO0_OUT_SEL<3:0> = 4’d13 GPIO0_OUT_SEL<3:0> = 4’d14 GPIO0_OUT_SEL<3:0> = 4’d15 GPIO1_OUT_SEL<3:0> = 4’d0 GPIO1_OUT_SEL<3:0> = 4’d1 GPIO1_OUT_SEL<3:0> = 4’d2 GPIO1_OUT_SEL<3:0> = 4’d3 GPIO1_OUT_SEL<3:0> = 4’d4 GPIO1_OUT_SEL<3:0> = 4’d5 GPIO1_OUT_SEL<3:0> = 4’d6 GPIO1_OUT_SEL<3:0> = 4’d7 GPIO1_OUT_SEL<3:0> = 4’d8 GPIO1_OUT_SEL<3:0> = 4’d9

Output signal source gpio_out_sfr<0> port0_out<0> tb_ccr0_out tb_cc1_out tb_ccr2_out nss_out sck_out miso_out mosi_out fcsb_out txd0_out ta_ccr0_out ta_cc1_out ta_ccr2_out t0_ov_out t1_ov_out gpio_out_sfr<1> port0_out<1> tb_ccr0_out tb_cc1_out tb_ccr2_out nss_out sck_out miso_out mosi_out rxd0_out

Rev 0.1A | 40/100 Page

www.hoperf.com

GPIOn GPIO2 GPIO3 GPIO4

AN261-CMT2186A User Guide

SFR GPIO_OUTB_SEL GPIO_OUTB_SEL GPIO_OUTB_SEL

Selected signal and code value GPIO1_OUT_SEL<3:0> = 4’d10 GPIO1_OUT_SEL<3:0> = 4’d11 GPIO1_OUT_SEL<3:0> = 4’d12 GPIO1_OUT_SEL<3:0> = 4’d13 GPIO1_OUT_SEL<3:0> = 4’d14 GPIO1_OUT_SEL<3:0> = 4’d15 GPIO2_OUT_SEL<3:0> = 4’d0 GPIO2_OUT_SEL<3:0> = 4’d1 GPIO2_OUT_SEL<3:0> = 4’d2 GPIO2_OUT_SEL<3:0> = 4’d3 GPIO2_OUT_SEL<3:0> = 4’d4 GPIO2_OUT_SEL<3:0> = 4’d5 GPIO2_OUT_SEL<3:0> = 4’d6 GPIO2_OUT_SEL<3:0> = 4’d7 GPIO2_OUT_SEL<3:0> = 4’d8 GPIO2_OUT_SEL<3:0> = 4’d9 GPIO2_OUT_SEL<3:0> = 4’d10 GPIO2_OUT_SEL<3:0> = 4’d11 GPIO2_OUT_SEL<3:0> = 4’d12 GPIO2_OUT_SEL<3:0> = 4’d13 GPIO2_OUT_SEL<3:0> = 4’d14 GPIO2_OUT_SEL<3:0> = 4’d15 GPIO3_OUT_SEL<3:0> = 4’d0 GPIO3_OUT_SEL<3:0> = 4’d1 GPIO3_OUT_SEL<3:0> = 4’d2 GPIO3_OUT_SEL<3:0> = 4’d3 GPIO3_OUT_SEL<3:0> = 4’d4 GPIO3_OUT_SEL<3:0> = 4’d5 GPIO3_OUT_SEL<3:0> = 4’d6 GPIO3_OUT_SEL<3:0> = 4’d7 GPIO3_OUT_SEL<3:0> = 4’d8 GPIO3_OUT_SEL<3:0> = 4’d9 GPIO3_OUT_SEL<3:0> = 4’d10 GPIO3_OUT_SEL<3:0> = 4’d11 GPIO3_OUT_SEL<3:0> = 4’d12 GPIO3_OUT_SEL<3:0> = 4’d13 GPIO3_OUT_SEL<3:0> = 4’d14 GPIO3_OUT_SEL<3:0> = 4’d15 GPIO4_OUT_SEL<3:0> = 4’d0 GPIO4_OUT_SEL<3:0> = 4’d1 GPIO4_OUT_SEL<3:0> = 4’d2

Output signal source csb_out ta_ccr0_out ta_cc1_out ta_ccr2_out t0_ov_out t1_ov_out gpio_out_sfr<2> port0_out<2> tb_ccr0_out tb_cc1_out tb_ccr2_out nss_out sck_out miso_out mosi_out rxd0_out txd0_out ta_ccr0_out ta_cc1_out ta_ccr2_out t0_ov_out t1_ov_out gpio_out_sfr<3> port0_out<3> tb_ccr0_out tb_cc1_out tb_ccr2_out nss_out sck_out miso_out mosi_out rxd0_out txd0_out ta_ccr0_out ta_cc1_out ta_ccr2_out t0_ov_out t1_ov_out gpio_out_sfr<4> port0_out<4> tb_ccr0_out

Rev 0.1A | 41/100 Page

www.hoperf.com

GPIOn GPIO5 GPIO6

AN261-CMT2186A User Guide

SFR GPIO_OUTC_SEL GPIO_OUTD_SEL

Selected signal and code value GPIO4_OUT_SEL<3:0> = 4’d3 GPIO4_OUT_SEL<3:0> = 4’d4 GPIO4_OUT_SEL<3:0> = 4’d5 GPIO4_OUT_SEL<3:0> = 4’d6 GPIO4_OUT_SEL<3:0> = 4’d7 GPIO4_OUT_SEL<3:0> = 4’d8 GPIO4_OUT_SEL<3:0> = 4’d9 GPIO4_OUT_SEL<3:0> = 4’d10 GPIO4_OUT_SEL<3:0> = 4’d11 GPIO4_OUT_SEL<3:0> = 4’d12 GPIO4_OUT_SEL<3:0> = 4’d13 GPIO4_OUT_SEL<3:0> = 4’d14 GPIO4_OUT_SEL<3:0> = 4’d15 GPIO5_OUT_SEL<3:0> = 4’d0 GPIO5_OUT_SEL<3:0> = 4’d1 GPIO5_OUT_SEL<3:0> = 4’d2 GPIO5_OUT_SEL<3:0> = 4’d3 GPIO5_OUT_SEL<3:0> = 4’d4 GPIO5_OUT_SEL<3:0> = 4’d5 GPIO5_OUT_SEL<3:0> = 4’d6 GPIO5_OUT_SEL<3:0> = 4’d7 GPIO5_OUT_SEL<3:0> = 4’d8 GPIO5_OUT_SEL<3:0> = 4’d9 GPIO5_OUT_SEL<3:0> = 4’d10 GPIO5_OUT_SEL<3:0> = 4’d11 GPIO5_OUT_SEL<3:0> = 4’d12 GPIO5_OUT_SEL<3:0> = 4’d13 GPIO5_OUT_SEL<3:0> = 4’d14 GPIO5_OUT_SEL<3:0> = 4’d15 GPIO6_OUT_SEL<3:0> = 4’d0 GPIO6_OUT_SEL<3:0> = 4’d1 GPIO6_OUT_SEL<3:0> = 4’d2 GPIO6_OUT_SEL<3:0> = 4’d3 GPIO6_OUT_SEL<3:0> = 4’d4 GPIO6_OUT_SEL<3:0> = 4’d5 GPIO6_OUT_SEL<3:0> = 4’d6 GPIO6_OUT_SEL<3:0> = 4’d7 GPIO6_OUT_SEL<3:0> = 4’d8 GPIO6_OUT_SEL<3:0> = 4’d9 GPIO6_OUT_SEL<3:0> = 4’d10 GPIO6_OUT_SEL<3:0> = 4’d11

Output signal source tb_cc1_out tb_ccr2_out nss_out sck_out miso_out mosi_out fcsb_out txd0_out ta_ccr0_out ta_cc1_out ta_ccr2_out t0_ov_out t1_ov_out gpio_out_sfr<5> port0_out<5> tb_ccr0_out tb_cc1_out tb_ccr2_out nss_out sck_out miso_out mosi_out fcsb_out txd0_out ta_ccr0_out ta_cc1_out ta_ccr2_out t0_ov_out t1_ov_out gpio_out_sfr<6> port0_out<6> tb_ccr0_out tb_cc1_out tb_ccr2_out nss_out sck_out miso_out mosi_out rxd0_out txd0_out ta_ccr0_out

Rev 0.1A | 42/100 Page

www.hoperf.com

GPIOn GPIO7 GPIO8 GPIO9

AN261-CMT2186A User Guide

SFR GPIO_OUTD_SEL GPIO_OUTE_SEL GPIO_OUTE_SEL

Selected signal and code value GPIO6_OUT_SEL<3:0> = 4’d12 GPIO6_OUT_SEL<3:0> = 4’d13 GPIO6_OUT_SEL<3:0> = 4’d14 GPIO6_OUT_SEL<3:0> = 4’d15 GPIO7_OUT_SEL<3:0> = 4’d0 GPIO7_OUT_SEL<3:0> = 4’d1 GPIO7_OUT_SEL<3:0> = 4’d2 GPIO7_OUT_SEL<3:0> = 4’d3 GPIO7_OUT_SEL<3:0> = 4’d4 GPIO7_OUT_SEL<3:0> = 4’d5 GPIO7_OUT_SEL<3:0> = 4’d6 GPIO7_OUT_SEL<3:0> = 4’d7 GPIO7_OUT_SEL<3:0> = 4’d8 GPIO7_OUT_SEL<3:0> = 4’d9 GPIO7_OUT_SEL<3:0> = 4’d10 GPIO7_OUT_SEL<3:0> = 4’d11 GPIO7_OUT_SEL<3:0> = 4’d12 GPIO7_OUT_SEL<3:0> = 4’d13 GPIO7_OUT_SEL<3:0> = 4’d14 GPIO7_OUT_SEL<3:0> = 4’d15 GPIO8_OUT_SEL<3:0> = 4’d0 GPIO8_OUT_SEL<3:0> = 4’d1 GPIO8_OUT_SEL<3:0> = 4’d2 GPIO8_OUT_SEL<3:0> = 4’d3 GPIO8_OUT_SEL<3:0> = 4’d4 GPIO8_OUT_SEL<3:0> = 4’d5 GPIO8_OUT_SEL<3:0> = 4’d6 GPIO8_OUT_SEL<3:0> = 4’d7 GPIO8_OUT_SEL<3:0> = 4’d8 GPIO8_OUT_SEL<3:0> = 4’d9 GPIO8_OUT_SEL<3:0> = 4’d10 GPIO8_OUT_SEL<3:0> = 4’d11 GPIO8_OUT_SEL<3:0> = 4’d12 GPIO8_OUT_SEL<3:0> = 4’d13 GPIO8_OUT_SEL<3:0> = 4’d14 GPIO8_OUT_SEL<3:0> = 4’d15 GPIO9_OUT_SEL<3:0> = 4’d0 GPIO9_OUT_SEL<3:0> = 4’d1 GPIO9_OUT_SEL<3:0> = 4’d2 GPIO9_OUT_SEL<3:0> = 4’d3 GPIO9_OUT_SEL<3:0> = 4’d4

Output signal source ta_cc1_out ta_ccr2_out t0_ov_out t1_ov_out gpio_out_sfr<7> port0_out<7> tb_ccr0_out tb_cc1_out tb_ccr2_out nss_out sck_out miso_out mosi_out rxd0_out txd0_out ta_ccr0_out ta_cc1_out ta_ccr2_out t0_ov_out t1_ov_out gpio_out_sfr<8> port1_out<0> tb_ccr0_out tb_cc1_out tb_ccr2_out nss_out sck_out miso_out mosi_out rxd0_out txd0_out ta_ccr0_out ta_cc1_out ta_ccr2_out t0_ov_out t1_ov_out gpio_out_sfr<9> port1_out<1> tb_ccr0_out tb_cc1_out tb_ccr2_out

Rev 0.1A | 43/100 Page

www.hoperf.com

GPIOn GPIO10 GPIO11

AN261-CMT2186A User Guide

SFR GPIO_OUTF_SEL GPIO_OUTF_SEL

Selected signal and code value GPIO9_OUT_SEL<3:0> = 4’d5 GPIO9_OUT_SEL<3:0> = 4’d6 GPIO9_OUT_SEL<3:0> = 4’d7 GPIO9_OUT_SEL<3:0> = 4’d8 GPIO9_OUT_SEL<3:0> = 4’d9 GPIO9_OUT_SEL<3:0> = 4’d10 GPIO9_OUT_SEL<3:0> = 4’d11 GPIO9_OUT_SEL<3:0> = 4’d12 GPIO9_OUT_SEL<3:0> = 4’d13 GPIO9_OUT_SEL<3:0> = 4’d14 GPIO9_OUT_SEL<3:0> = 4’d15 GPIO10_OUT_SEL<3:0> = 4’d0 GPIO10_OUT_SEL<3:0> = 4’d1 GPIO10_OUT_SEL<3:0> = 4’d2 GPIO10_OUT_SEL<3:0> = 4’d3 GPIO10_OUT_SEL<3:0> = 4’d4 GPIO10_OUT_SEL<3:0> = 4’d5 GPIO10_OUT_SEL<3:0> = 4’d6 GPIO10_OUT_SEL<3:0> = 4’d7 GPIO10_OUT_SEL<3:0> = 4’d8 GPIO10_OUT_SEL<3:0> = 4’d9 GPIO10_OUT_SEL<3:0> = 4’d10 GPIO10_OUT_SEL<3:0> = 4’d11 GPIO10_OUT_SEL<3:0> = 4’d12 GPIO10_OUT_SEL<3:0> = 4’d13 GPIO10_OUT_SEL<3:0> = 4’d14 GPIO10_OUT_SEL<3:0> = 4’d15 GPIO11_OUT_SEL<3:0> = 4’d0 GPIO11_OUT_SEL<3:0> = 4’d1 GPIO11_OUT_SEL<3:0> = 4’d2 GPIO11_OUT_SEL<3:0> = 4’d3 GPIO11_OUT_SEL<3:0> = 4’d4 GPIO11_OUT_SEL<3:0> = 4’d5 GPIO11_OUT_SEL<3:0> = 4’d6 GPIO11_OUT_SEL<3:0> = 4’d7 GPIO11_OUT_SEL<3:0> = 4’d8 GPIO11_OUT_SEL<3:0> = 4’d9 GPIO11_OUT_SEL<3:0> = 4’d10 GPIO11_OUT_SEL<3:0> = 4’d11 GPIO11_OUT_SEL<3:0> = 4’d12 GPIO11_OUT_SEL<3:0> = 4’d13

Output signal source nss_out sck_out miso_out mosi_out rxd0_out txd0_out ta_ccr0_out ta_cc1_out ta_ccr2_out t0_ov_out t1_ov_out gpio_out_sfr<10> port0_out<2> tb_ccr0_out tb_cc1_out tb_ccr2_out nss_out sck_out miso_out mosi_out rxd0_out txd0_out ta_ccr0_out ta_cc1_out ta_ccr2_out t0_ov_out t1_ov_out gpio_out_sfr<11> port0_out<3> tb_ccr0_out tb_cc1_out tb_ccr2_out nss_out sck_out miso_out mosi_out rxd0_out txd0_out ta_ccr0_out ta_cc1_out ta_ccr2_out

Rev 0.1A | 44/100 Page

www.hoperf.com

AN261-CMT2186A User Guide

GPIOn

SFR

Selected signal and code value

Output signal source

GPIO11_OUT_SEL<3:0> = 4’d14

t0_ov_out

GPIO11_OUT_SEL<3:0> = 4’d15

t1_ov_out

Notes:

[1]. The default mapping is controlled by the GPIO_OUT_SFR<11:0> register group and for the reason that the register

group does not support the bit access mode, so the control output needs to follow the “read-change-write” mode.

9.8 GPIO Level Flipping Detection
The GPIO level flip detection (I/O Change Scan) module located in the AON domain is used to detect the level flip of any I/O after the system enters the STOP mode, generating an interrupt source that wakes the system and sends it to the external interrupt INT0. When the system is running normally, users need to disable this module to avoid conflicts with other I/O functions.
To use this module, process of user program is shown as followed:
1. The module can only be opened when STOP, and the IO_EVENT_RST_N bit of WKINT_STA register in SFR PAGE0 is maintained as 0 when the program is running, that is, the whole module is in the reset state.
2. After selecting the GPIO to be detected, users can start configuring the GPIO and detection module via AON REG. Since the module is in reset mode, there will not have any misdetection during the configuration process.
3. The GPIO must be configured in digital input mode with digital output function disabled. 4. Configure the pull-up/pull-down resistance of the GPIO; 5. Configure the reversing polarity of the GPIO (rising or falling edge); 6. Enable the GPIO level flipping detection; 7. Set IO_EVENT_RST_N to 1 to release the detection module and configure INT0 through SFR; 8. The system enters the STOP mode. 9. When the GPIO detects a level flip and wakes up the system via INT0, it sets the
IO_EVEN_RST_N bit to 0 after the relevant IO query and processing.
The common application scenario of this module is that GPIO connects external keys. Two connection methods are usually used. The following shows example of connecting keys with D0-D11:
Independent key connection

Rev 0.1A | 45/100 Page

www.hoperf.com

D11_IN

VDD

Strong-Pull Week-Pull

D11

D10_IN

D10

D9_IN

D8_IN

D7_IN

D6_IN

D5_IN

D4_IN

D3_IN

D2_IN

D1_IN

D0_IN

AN261-CMT2186A User Guide

Chart 9-3. Independent Key Connection Diagram
D0-D11 in the figure below are all connected to the ground, so these ports can all enble the pull-up digital input port mode, and configure Dn_POLAR (n generally refers to any number from 0-11, each IO has a corresponding polarity selection bit) to 1, that is, the normal state is 1. When a key is pressed to port 0 and the falling edge is detected, the interrupt will be triggered.
Matrix key connection

D0_OUT

VDD

D1_OUT

D2_OUT

D3_OUT

D4_OUT

D5_IN

D6_IN

D7_IN

D8_IN

D9_IN

D10_IN

D11_IN

VDD

Strong-Pull Week-Pull

D5 D6 D7 D8 D9 D10
D11

Chart 9-4. Matrix Key Connection Diagram
Rev 0.1A | 46/100 Page

www.hoperf.com

AN261-CMT2186A User Guide

According to the above connection method, D0-D11 is a matrix keyboard consist of D5-D11, which is used as a set of input detection, and D0-D4, which is used as a set of output control. Before entering the STOP mode, user needs to configure D0-D4 as digital output mode, with output value of 0. The D5-D11 group of digital inputs can be configured to enable the detection function as independent keys. After entering STOP mode, any key on the Matrix keyboard will wake up the system via D5-D11. The software can normally scan the keyboard as general procedure to identify keys after waking up the system.

9.9 Related Register

Table 9-6. AON register groups of GPIO

Name AON_REG_10

Address 0x10

AON_REG_11 AON_REG_12 AON_REG_13 AON_REG_14 AON_REG_15 AON_REG_16 AON_REG_17 AON_REG_18 AON_REG_19 AON_REG_1A AON_REG_1B AON_REG_1C AON_REG_1D AON_REG_1E

0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E

Default Values
0xE0
0x00 0x00 0x00 0x00 0xFF 0x0F 0xFF 0x0F 0xFF 0x0F 0x00 0x00 0x00 0x00

Funtion
Enabling GPIO analog functions and configure the pull up and pull down resistance value Digital output enabling bit of D0 – D7 Digital output of the enabling bit of D8 – D11 Digital input enabling bit of D0 – D7 Digital input enabling bit of D8 – D11 Pull up resistance switch of D0 – D7 Pull up resistance switch of D8 – D11 Pull down resistance switch of D0 – D7 Pull down resistance switch of D8 – D11 Open drain switch of D0 – D7 Open drain switch of D8 – D11 Level flip detection enable bit for D0-D7 Level flip detection enable bit for D8-D11 Level flip detection polarity selection for D0-D7 Level flip detection polarity selection for D8-D11

Table 9-7. SFR register groups of GPIO

Name
GPIO_INA_SEL GPIO_INB_SEL GPIO_INC_SEL GPIO_IND_SEL GPIO_INE_SEL GPIO_INF_SEL

SFR page
0 0 0 0 0 0

address
0xA1 0xA2 0xA3 0xA4 0xA5 0xA6

default values
0x00 0x00 0x00 0x00 0x00 0x00

Functions
GPIO Input function mapping GPIO Input function mapping GPIO Input function mapping GPIO Input function mapping GPIO Input function mapping GPIO Input function mapping

Rev 0.1A | 47/100 Page

www.hoperf.com

Name
GPIO_ING_SEL GPIO_OUTA_SEL GPIO_OUTB_SEL GPIO_OUTC_SEL GPIO_OUTD_SEL GPIO_OUTE_SEL GPIO_OUTF_SEL
GPIO_OUT_0 GPIO_OUT_1
GPIO_IN_0 GPIO_IN_1

SFR page
0 0 0 0 0 0 0 0 0 0 0

AN261-CMT2186A User Guide

address
0xA9 0xAA 0xAB 0xAC 0xAD 0xB0 0xB1 0xB3 0xB4 0xB5 0xB6

default values
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00

Functions
GPIO Input function mapping GPIO output function mapping GPIO output function mapping GPIO output function mapping GPIO output function mapping GPIO output function mapping GPIO output function mapping GPIO output data via SFR configuration GPIO output data via SFR configuration Readable GPIO input data from SFR Readable GPIO input data from SFR

Rev 0.1A | 48/100 Page

www.hoperf.com

10 Timer0 Module

AN261-CMT2186A User Guide

10.1 Basic Function

Timer0 is a 16-Bit programmable timer/counter that can be configured with TMOD registers to select how it works, start or stop counting, and generate counting overflow interrupts. Timer0 supports 3 working modes and they are shown as Table 10-1.

Table 10-1. Working Modes in Timer0

TMOD. M01 TMOD.M00

Working Mode Mode 0 Mode 1 Mode 2 disable

Functions
8-Bit timing/counter with 5 bit prescale, i.e. 13-Bit timing/count mode 16-Bit timer/counter mode 8-Bit timing/counting mode with overloaded initial values

10.2 Timer0 Mode0
Block diagram of Timer0 mode 0 is shown below.

TIMER0_CLK /12 t0_in C/T0 TR0
GATE0 t0_int0_n

Timer 0

TL0[4:0]

TH0

TF0

Interrupt to

enable

8051 core

Chart 10-1. Block diagram of Timer 0 mode 0

When Timer0 works in Mode0, a 13-bit counter is combined from a 5-bit prescaler provided by TL0[4:0] and an 8-bit counter provided by TH0 :
If TMOD.C/T0 is set to 0, timing mode is selected, and the timing clock source is the 12-prescale of FPCLK.
If TMOD.C/T0 is set to 1, counting mode is selected, and the falling edge of the external input pin t0 is used as the counting signal.

Rev 0.1A | 49/100 Page

www.hoperf.com

AN261-CMT2186A User Guide
If TMOD.GATE0 is set to 1, the gate control trigger counting is selected. it requires high level of external interrupt t0_int0_n and Ton.tr0 to trigger Timer0 counting.
If TMOD.GATE0 is set to 0, Timer0 counting is triggered as the TCON.TR0 is set to 1 The total switch of Timer0 counting is TCON.TR0, the counting function is enabled when it is set 1 and
disable when it is set 0.
10.3 Timer0 Mode1
Block diagram of Timer0 mode 1 is shown in the chart below.

TIMER0_CLK /12
t0_in C/T0 TR0 GATE0 t0_int0_n

enable

Timer 0

TL0

TH0

TF0

Interrupt to

8051 core

Chart 10-2. Block diagram of Timer 0 mode 1
When TIMER0 works in Mode0, it is a 16-bit counter, consisting of TL0 and TH0, the difference from Mode0 is only in the number of counter bits. Functions of other control bits are the same as Mode0.
10.4 Timer0 Mode2
Block diagram of Timer0 mode 2 is shown in the chart below.

TIMER0_CLK /12 t0_in C/T0 TR0
GATE0 t0_int0_n
Copyright © By HOPERF

enable

TL0

Overflow

TF0

Timer 0 Interrupt to

8051 core

TH0

Rev 0.1A | 50/100 Page

www.hoperf.com

AN261-CMT2186A User Guide Chart 10-3. Block diagram of Timer 0 mode 2

When Timer0 works in Mode2, the counter is automatically overloads with initial value of 8 bits, and when the TL0 count overflows, it automatically loads the value saved by TH0 (the initial value), making TL0 re-count from the initial value. This is the main difference from Mode0/1, where the counter is cleared to zero after the count overflows. While other control bits function is the same as Moode0/1.

10.5 Related Register

Name
TCON TMOD
TL0 TH0

Table 10-2. Register Group of Timer0 Module

SFR page
0 0 0 0

address
0x88 0x89 0x8A 0x8C

default values 0x00 0x00 0x00 0x00

Functions
Timer0 and Timer1 Control Registers Timer0 and Timer1 Working Mode Registers Timer0 register low 8 bit Timer0 register high 8 bit

Rev 0.1A | 51/100 Page

www.hoperf.com

11 Timer1 Module

AN261-CMT2186A User Guide

11.1 Basic Function

Timer1 is a 16-Bit programmable timer/counter that can be configured with TMOD registers to select how it works, start or stop counting, and generate count overflow interrupts. Timer 1 supports 3 kinds of working modes, which are shown in the following table.

TMOD. M11 TMOD.M10

Table 11-1. Work Modes in Timer 1

Work Mode Mode 0 Mode 1 Mode 2 Disable

Functions
8-Bit timing/counter with 5-bit prescale, i.e. 13-Bit timing/count mode 16-Bit timing/counting mode 8-Bit timing/counting mode with overloaded initial values

11.2 Timer1 Mode0

Block diagram of Timer1 mode 0 is shown below.

TIMER1_CLK /12 t1_in C/T1 TR1
GATE1 t1_int1_n

Timer 1

TL1[4:0]

TH1

TF1

Interrupt to

enable

8051 core

Chart 11-1. Block Diagram of Timer1 Mode0
When Timer1 works in Mode0, a 13-bit counter is combined from a 5-bit prescaler provided by TL1[4:0] and an 8-bit counter provided by TH1:
If TMOD.C/T1 is set to 0, timing mode is selected, and the timing clock source is the 12-prescale of FPCLK.
If TMOD.C/T1 is set to 1, counting mode is selected, and the falling edge of the external input pin t1 is used as the counting signal.

Rev 0.1A | 52/100 Page

www.hoperf.com

AN261-CMT2186A User Guide
If TMOD.GATE1 is set to 1, the gate control trigger counting is selected. it requires high level of external interrupt t1_int1_n and TCON.TR1 to trigger Timer1 counting.
If TMOD.GATE1 is set to 0,Timer1 counting is triggered as the TCON.TR1 is set to 1 The total switch of Timer1 counting is TCON.TR1, the counting function is enabled when it is set 1 and
disable when it is set 0.
11.3 Timer1 Mode1
Block diagram of Timer1 mode 1 is shown below.

TIMER1_CLK /12
t1_in C/T1 TR1 GATE1 t1_int1_n

enable

Timer 1

TL1

TH1

TF1

Interrupt to

8051 core

Chart 11-2. Block Diagram in Timer1 Mode1
When TIMER1 works in Mode1, it is a 16-bit counter, consisting of TL1 and TH1, and differs from Mode0 only in the number of counter bits. While other control bit function is the same as Moode0.
11.4 Timer1 Mode2
Block diagram of Timer1 mode 2 is shown below.

TIMER1_CLK /12 t1_in C/T1 TR1
GATE1 t1_int1_n
Copyright © By HOPERF

enable

TL1

Overflow TF1

Timer 1 Interrupt to

8051 core

TH1

Rev 0.1A | 53/100 Page

www.hoperf.com

AN261-CMT2186A User Guide Chart 11-3. Block Diagram of Timer1 Mode2

When Timer1 works in Mode2, the counter is automatically overloads with initial value of 8 bits, and when the TL1 count overflows, it automatically loads the value saved by TH1 (the initial value), making TL1 re-count from the initial value.

This is the main difference from Mode0/1, where the counter is cleared to zero after the count overflows.

While other control bit function is the same as Moode0/1.

11.5 Related Register

Name
TCON TMOD
TL1 TH1 USART_SEL

Table 11-2. Register Group of Timer1 Module

SFR page
0 0 0 0 0

address
0x88 0x89 0x8B 0x8D 0x9F

default values
0x00 0x00 0x00 0x00 0x01

Functions
Timer0 and Timer1 Control Registers Timer0 and Timer1 Working Mode Registers Timer1 register low 8 bit Timer1 register high 8 bit Prescaler options of Timer1 clock source

Rev 0.1A | 54/100 Page

www.hoperf.com

12 SPI Module

AN261-CMT2186A User Guide

12.1 Basic Function
The serial peripheral interface (SPI) allows the chip and peripherals to communicate in a half/full duplex, synchronous and serial manner. It supports master mode and slave mode from the operating manner view. The master provides communication clock to the slave. The interface also supports multi-master configuration or 1-wire bi-directional simplex synchronous transmission (3-wire mode).

Usually, 4 pins need to be connected between the master and slave SPI devices.

MISO: master-in-slave-out pin. The pins are received from master device and transmitted form slave device. The pin can send data from the slave device to the master device.
MOSI; master-out-slave-in pin. The pins received from slave device and transmitted form master device. The pin can send data from the master device to the slave device.
SCK: serial data synchronous clock, which is output from the master device to the slave device. NSSslave device selection enabling, an optional pin used for the master device to select the target
slave device. It allows the master device to communicate with a specific slave device individually, avoiding conflicts on the data lines. The NSS pin of the slave device can be driven by the master device as a standard IO. Once enabled (SSOE bit), the NSS pin can also be used as an output pin and can be pulled low when the SPI is set to master mode; At this time, all SPI devices with their NSS pins connecting to the master NSS pin will get low levels and will enter into slave mode automatically if they are set as NSS hardware mode.
The SPI interface timing of master and slave mode are shown in Chart 12-1 and Chart 12-2 respectively. Among them, the sampling clock phase CPHA of SCK is configured by register SPI_CTL_1.SPI_EDGE_SEL. If it is 1, SPI will send data on the first edge of the clock and sample data on the second edge; if it is set 0, SPI will sample data on the first edge of the clock and send data on the second edge. CPOL determines the status of the SCK when it is idle. When CPOL is 1, the SCK line will remain high during idle. When CPOL is 0, the SCK line will remain low during idle.

Rev 0.1A | 55/100 Page

www.hoperf.com

SCK (CPOL = 1)
SCK (CPOL = 0)
MISO from master
MOSI from slave
NSS to slave

MSB MSB

AN261-CMT2186A User Guide
LSB LSB

Chart 12-1. SPI Interface TimingCPHA = 1

CPOL = 1

CPOL = 0

MISO

from master

MSB

LSB

MOSI

from slave

MSB

LSB

NSS to slave

Chart 12-2. SPI Interface TimingCPHA = 0
12.2 Configuration Option
Master Mode and Slave Mode Setting

The SPI module contains the complete program of master mode and slave mode. User can set the currently controlled SPI as a master or slave device by configuring register SPI_CTL_1.SPI_MS_SEL, so as to communicate with the other slave or master devices. If SPI_MS_SEL is set to 1’b1, the current SPI module will be set to master mode; if SPI_MS_SELl is set to 1’b0, the current SPI module will be set to slave mode.

Configuration of Clock Phase and Clock Polarity

To set the clock phase, the variable SPI_CTL_1.SPI_EDGE_SEL needs to be configured. If this variable is set to 1, SPI will sample the second edge of the clock, and if 0 is set, SPI will sample the first edge of the clock.

Clock polarity can be set by configuring register SPI_CTL_1.SPI_CKPOL_SEL. If SPI_CKPOL_SEL is set 1,

Rev 0.1A | 56/100 Page

www.hoperf.com

AN261-CMT2186A User Guide
SCK will be high in IDLE state; if SPI_CKPOL_SEL is set 0, SCK will be low in IDLE state. The following figure shows the edge of data sampling and transmitting when configured with different clock polarities and phases.

SPI_CKPOL_SEL = 0

Send

SPI_EDGE_SEL = 0 SCK

Cap Send

SPI_EDGE_SEL = 1 SCK Cap

SPI_CKPOL_SEL = 1

Send

SCK

Cap Send

SCK Cap

Chart 12-3. Diagram of SPI Interface Timing CPHA = 1

Setting of the transmitting data bit width

When register SPI_CTL_0.SPI_8B16B_SEL is set to 1, SPI will select to transmit 16bit data, master device will transmit 16 cycles of clocks to the slave device, and the slave will also collect 16 bits of data in turn along the corresponding clock. When SPI_8B16B_SEL is set to 0, only 8 bits of data are transmitted, which are the lower 8 bits of the 16 bits in SPI_DATA.

Baud Rate Setting

Table 12-1. SPI Module Rate

SPI_CTL_0.SPI_MBR Setting Value 3’b000 3’b001 3’b010 3’b011 3’b100 3’b101 3’b110 3’b111

Transfer rate:sys_clk is the system clock, default by 24Mhz sys_clk/4 sys_clk/8 sys_clk/16 sys_clk/24 sys_clk/32 sys_clk/64 sys_clk/128 sys_clk/256

The setting of high-low bit priority transmission

If the input signal SPI_CTL_1.SPI_LSBF is set to 1, the low-level data will be transmitted first; if it is set to 0, the high-level data will be transmitted first.

12.3 Working Mode

Both master and slave device have four working modes and they can be separated into 2 types, which

Rev 0.1A | 57/100 Page

www.hoperf.com

AN261-CMT2186A User Guide
includes full duplex and half-duplex. Three variables of SPI_CTL_0.SPI_BIDI_MODE SPI_CTL_0.SPI_BIDI_OENSPI_CTL_0.SPI_RX_ONLY can be configured as the following list and acheive 4 working modes.

Table 12-2. SPI Module Operating Modes

SPI_BIDI_MODE SPI_RX_ONLY

1’b0

1’b1

Random value

1’b1

Random value

SPI_BIDI_OEN Random value Random value 1’b1 1’b0

Mode Selection Priority
First Level
Second level
Third level
Fourth level

Working Mode
Full duplex normal mode
Full duplex read only mode
Half duplex write only mode
Half duplex read only mode

1. Full-duplex normal mode: When a master or slave device is configured in this mode, data is sent and received synchronously. Taking the master device as an example, the data transmitting port MOSI sends data out, while the MISO port also receives data from the slave device.
2. Full duplex read-only mode: The receiving end of the master device and slave device in this mode works normally, while the transmitting end always sends 0.
3. Half-duplex write only mode: In this mode, a host or slave device has only three external interfaces. For example, on a master device, SCK sends out clocks, NSS transmission is enabled, and the last I/O port is allocated to MOSI to transmitting data.
3. Half-duplex read only mode: In this mode, a host or slave device has only three external interfaces. For example, on a master device, SCK sends out clocks, NSS transmission is enabled, and the last I/O port is allocated to MOSI to receive data.

Application: The SPI can communicate with the S3S interface by switching back and forth between read-only and write only in half duplex. When the SPI wants to send an address to the S3S interface, it can be set to the half-duplex write only mode, and map the MOSI to the PAD to connect with the SDA of the S3S to realize the address writing. When the SPI wants to read out the data transmit by S3S, it can set the SPI to half-duplex read-only mode and map the MISO to the PAD to connect to the SDA of S3S in order to read out the data transmitted by S3S. In this case, data communication between SPI and S3S can be realized when only three physical wires are connected.
12.4 Status Flag
The SPI module provides the bus status through 3 status flags to serve software monitoring.

Rev 0.1A | 58/100 Page

www.hoperf.com

AN261-CMT2186A User Guide

Busy flagSPI_CTL2.SPI_BUSY flag bitwhen the SPI is in the process of transmission, the flag bit wil be pulled high.

Send buffer free flag (SPI_CTL2.SPI_TXMTY flag bit); When the SPI is configured with new transmiting data, the flag bit will be pull low. When the new transmitting data is configured and transmited successfully, the flag bit will be pull high.

Receive buffer is not empty (SPI_CTL2.SPI_RXNMTY flag bit); When the SPI completes a cycle of data transmission, it pulls up the SPI_RXNMTY flag bit to indicate that the data has been successfully sent and received. When the user reads the data received in SPI_DATA, the flag bit will be automatically pull low.

12.5 Related Register

Table 12-3. Register Group of SPI Module

Name
SPI_CTL_0 SPI_CTL_1 SPI_CTL_2 SPI_DATA_H SPI_DATA_L

SFR page Page0 Page0 Page0 Page0 Page0

address
0x96 0x97 0x9A 0x9B 0x9C

default values
0x00 0x00 0x00 0x00 0x00

Functions
SPI module control register 0 SPI module control register 1 SPI module control register 2 SPI module data high bytes SPI module data low bytes

Rev 0.1A | 59/100 Page

www.hoperf.com

13 UART Module

AN261-CMT2186A User Guide

13.1 Basic Function
The on-chip UART of CMT2186A is a flexible full-duplex asynchronous transceiver fully compatible with the 8051 architecture. The baud rate is configured by the software and supports the following 4 operating modes.

Mode0: synchronous shift mode, with baud rate fixed to UART_CLK / 12 Mode18-Bit UART modewith configurable baud rate generated by the internal Timer 1 Mode29-Bit UART modewith baud rate of UART_CLK / 64 or UART_CLK / 32 Mode39-Bit UART modewith configurable baud rate generated by the internal Timer 1

Users can select the interrupts of UART module’s operating mode, communication enabling, and data transmitting/receiving by configuring SCON0.
13.2 Synchronous Shift Mode (Mode0)
The synchronous shift mode is a synchronous operating mode of the UART module, similar to the SPI slave mode, to have serial communication with other 8051s. It adopts half-duplex communication with the serial line RxD being used as bidirectional input & output data interface, and the TxD generating the fixed serial baud rate clock with a clock frequency of UART_CLK / 12.. When SCON0.SM00 and SCON0.SM10 are configured as 00, the UART module selects to operate in Mode 0, and its transmission architecture is shown in the below figure.
SBUF0 Write

TX Shift Register

rxd0_o

SERIAL0_CLK

1/12

TX Counter

txd0

Chart 13-1. Transmission Block Diagram for UART in Mode 0
In the process of transmission, when data is written to the transmitting buffer SBUF, a positive pulse is generated, and the serial port starts to send data. At this time, SCON0.REN0 needs to be set as 0. After transmission complete, the sending interrupt flag bit SCON0.TI0 is set to 1. The sequence diagram is as follows.

Rev 0.1A | 60/100 Page

www.hoperf.com

AN261-CMT2186A User Guide

SBUF0 Write 12xTPCLK 5xTPCLK
txd0
rxd0_o

1xTPCLK D0 D1

D6 D7

TI0 1xTPCLK
Chart 13-2. Transmission Timing Diagram for UART in Mode 0

Mode0 receiving structure diagram is shown in the below figure.
SBUF0 Read

SBUF0

Data In rxd0_i

RX Shift Register

rxd0_o

FPCLK

1/12

RX Counter

txd0 Clock Out
Chart 13-3. Receiving Diagram for UART in Mode 0

When it receives in mode0, the receiving enabling bit SCON0.REN 0 is set 1, and when the receiving interrupt flag bit SCON0.RI0 is cleared, a positive pulse is generated and the serial port starts receiving data. The TxD output shift clock samples the data on the RxD line. When 8-bit data is received, the receiving interrupt flag bit SCON0.RI0 is set 1 and the data is buffered in SBUF0. The timing diagram is shown in the below figure.

Rev 0.1A | 61/100 Page

www.hoperf.com

SCON0 Write 12xTPCLK 5xTPCLK txd0
rxd0_i
REN0 RI0
SBUF0

1xTPCLK 1xTPCLK D0 D1

AN261-CMT2186A User Guide
D6 D7 1xTPCLK
D[7:0]

Chart 13-4. Receiving Timing Diagram of UART in Mode 0
13.3 Asynchronous Full-duplex Mode with Configurable Baud Rate
(Mode 1 and Mode 3)
Both mode 1 and mode 3 of the UART module are asynchronous full-duplex transceiver mode with variable baud rates. The only difference between them is that mode 1 is an 8-bit data transmitting and receiving mode, while mode 3 is a 9-bit data transmitting and receiving mode.
Settings Serial Port 0 as Mode1: Configure SCON0.SM00 and SCON0.SM10 as 01. Generate baud rate through Timer1 and PCON.SMOD1 bits. When receiving, set the receiving enabling bit SCON0.REN0 to 1. When sending, write data to the transmission buffer SBUF.
Settings Serial Port 0 as Mode3: Configure SCON0.SM00 and SCON0.SM10 as 11. Generate baud rate through Timer1 and PCON.SMOD1 bits. When receiving, set the receiving enabling bit SCON0.REN0 to 1. When transmitting, write data to the transmission buffer SBUF and SCON0.TB8.

Rev 0.1A | 62/100 Page

www.hoperf.com

AN261-CMT2186A User Guide
The frame formats of mode 1 and mode 3 are shown in the below figures.

S D0

D7 STOP

S D0

D7 D8 STOP

Chart 13-5. Frame Format of Mode 1 and Mode 3 of UART

The baud rates in mode 1 and mode 3 depend on overflow rate of Timer1. The transmission and receiving block diagrams are shown in the below figures.

SBUF0 Write
Transmit Buffer

TX Shift Register

txd0

Timer 1 Overflow

1/2

1/16 1

SMOD1

TX Counter

Chart 13-6. Transmission Block Diagram of UART in Mode 1 and Mode 3

SBUF0 Read
SBUF0

rxd0_i

RX Shift Register

Timer 1 Overflow

1/2

SMOD1

1/16

RX Counter

Chart 13-7. Receiving Block Diagram of UART in Mode 1 and Mode 3

Rev 0.1A | 63/100 Page

www.hoperf.com

AN261-CMT2186A User Guide

Configure Timer1 to generate the baud rate:

TMOD.M1[1:0] is configured as 10 (Timer1 in mode 2), TMOD.GATE1 is configured as 0, and TMOD.C/T1 is configured as 0.
Write the 8-bit initial count value to the TH1. TCON.TR1 is configured as 1 and starts timing.

The baud rate is calculated according to the following formula:

Baud_Rate = 21

[32 × 12 × (256 – 1)]

It is equivalent to:

BaudRate

1_ 32

During transmission, when 8-bit data is written to the transmission buffer SBUF0 (in mode3, write the data to SCON0.TB8 first, then write the 8-bit data to SBUF0), a positive pulse is generated, and the serial port starts transmitting data. First send the 1-bit as start bit 0, then send the LSB bit of SBUF, send the 8-bit data in turn, then send SCON0.TB8 (mode 3), and finally send the 1-bit stop bit 1. When the data transmission completes, set the transmission interrupt flag bit SCON0.TI0 to 1. The timing diagram is shown in the figure below.

Mode 1
txd0

D1 D2 D3

D4 D5 D6 D7 STOP S

SBUF0 Write

Buffered write can occur anywhere

TI0 TX Buffer

D[7:0]

X[7:0]

Mode 2, 3
txd0
SBUF0 Write

D1 D2 D3

D4 D5 D6 D7 D8 STOP S

Buffered write can occur anywhere

TI0 TX Buffer

D[7:0]

X[7:0]

TB80 D8

Chart 13-8. Asynchronous Transmission Timing Diagram for UART in Mode 1 and Mode 3

Rev 0.1A | 64/100 Page

www.hoperf.com

AN261-CMT2186A User Guide

When the mode 1 or mode 3 receiving mode of UART is enabled, the receiving enable bit SCON0.REN0 must be set 1 first, then the RxD pin state is sampled at 16 times of the baud rate, then wait for the falling edge of the start bit. While the falling edge is sampled, it is checked again whether RxD is 0 during start bit sampling, to confirm whether it is a valid start bit. If it is not 0, continue to sample the start bit. When it is confirmed as a valid start bit, it starts to receive 8-bit / 9-bit data, and each bit of data is sampled in the middle position. In the 8-bit receiving state, checking that whether the sampling stop bit is valid and copy it to SCON0.RB80, and set the receiving interrupt flag bit SCON0.RI0 to 1. If the stop bit is wrong, the FE0 (framing error) flag is set to 1. In the 9-bit receiving, after sampling the 9th bit, the interrupt bit flag SCON0.RI0 is set to 1 in the position of the stop bit, and the 9th bit is written to SCON0.RB80. The stop bit error is only used to generate the FE0 flag. When SCON0.RI0 is set to 1, SBUF loads the received 8-bit data. The timing diagram is shown in the figure below.

Mode 1
rxd0_i
Sample
RI0 SBUF0
Mode 2, 3
rxd0_i SBUF0 Write
RI0 SBUF0
RB80

D1 D2 D3

D4 D5 D6 D7 STOP S

D[7:0]

D1 D2 D3

D4 D5 D6 D7 D8 STOP S

D[7:0] D8

Chart 13-9. Asynchronous Receiving Timing Diagram of UART (Mode 1 and Mode 3)
13.4 Asynchronous Full-duplex Mode with Fixed Baud Rate (Mode 2)
Mode 2 is a 9-bit asynchronous full-duplex transceiver operating mode with fixed baud rate. The transmitting and receiving block diagrams are shown in the below figure.

Rev 0.1A | 65/100 Page

www.hoperf.com

SBUF0 Read
SBUF0

AN261-CMT2186A User Guide
SBUF0 Write
Transmit Buffer

rxd0_ i

RX Shift Register

TX Shift Register

txd0

FPCLK / 2

1/2

1/16

SMOD1

RX Counter

TX Counter

Chart 13-10. Transmitting and Receiving Block Diagram of UART Mode 2

Steps to setup UART to mode 2 are as follows. Configure SCON0.SM00 and SCON0.SM10 as 10. When receiving, set the receiving enabling bit SCON0.REN0 to 1. When transmitting, write data to the transmission buffer SBUF and SCON0.TB8.
The only difference between mode 2 and mode 3 is the baud rate difference. The baud rate of mode 2 is calculated as follows.
Baud_Rate = 2SMOD1 × PCLK 64
Both mode 2 and mode 3 of UART support multi-machine communication, which just needs to set SCON0.SM20 to 1. In this mode, a master can send data to multiple slaves through the serial line. A salve can be recognized by the master only when it receives the 9th bit of RB8 data as 1. The remaining 8-bit data is used to transmit the slave address. It can receive full data only if the address is matched. The further data stream is only sent to the identified slave devices. The 9th bit of the data stream needs to be set to 0 thus other slaves cannot recognize the data.

13.5 Enhanced Mode of USART
Among the various operating modes of UART, only in mode 1 and mode 3 can achieve different baud rates according to the Timer1 overflow period. It’s the most simple but practical when Timer 1 operating in mode 2. However, the CMT2186A HFOSC clock source supports relatively limited frequencies, namely 24 MHz, 12 MHz, 3 MHz, and external 13 MHz (generated by 26 MHz/2). Therefore, the corresponding baud rate options are also limited. Detail informations are listed in the below table.

Rev 0.1A | 66/100 Page

www.hoperf.com

AN261-CMT2186A User Guide Table 13-1. UART Baud Rate Error in Standard Mode (Timer1 in Mode2)

Target baud rate
300 600 1200 2400 4800 9600 14400 19200

Setting Value.of
TH1 -48 152 204 230 243 247 249

SMOD=1
Actual Baud Rate:
-601 1202 2404 4808 9615 13889 17857

Error Value

Setting Value.of TH1

SMOD=0
Actual Baud Rate:

Error Value

—

300.48

0.16%

0.17%

152

601

0.17%

204

1202

0.17%

230

2404

0.17%

243

4808

0.17%

0.16%

249

8929

-6.99%

-3.55%

252

15625

8.51%

-6.99%

253

20833

8.51%

Note: Select the HFOSC clock with frequency of 24MHz (i.e. FPCLK = 24MHz).
Table 13-1 shows that only the six common low rate of 300, 600, 1200, 2400, 4800, 9600 are less errors and meet the requirement of using. The higher baud rate is basically unable to be used. In order to enable CMT2186A to support more baud rate options, it is embedded with enhanced mode on chip. CMT2186A can set USART_SEL (located in SFR register USART_CTL) to 1, otherwise canceling the 12 frequency divider in front of the Timer1 clock source and directly provide Timer1 from FPCLK as the clock source, as shown in the following figure.

FPCLK

/ 12

Timer1

USART_SEL

Chart 13-11. Schematic diagram of the Timer1 clock source in enhanced mode

When USART_SEL=0, the Timer1 clock source is FPCLK/12 according to the standard 51 architecture. When USART_SEL=1, the Timer1 clock source is in enhanced mode and is directly provided by
FPCLK.

The baud rate errors calculated in enhanced mode are shown below.

Rev 0.1A | 67/100 Page

www.hoperf.com

AN261-CMT2186A User Guide Table 13-2. UART baud rate errors in enhanced mode (Timer1 Mode 2)

Target Baud rate
4800 9600 14400 19200 38400 56000 57600 115200

TH1 Setting Value
-100 152 178 217 229 230 243

SMOD=1
Actual Baud rate
-9615 14423 19230 38462 55556 57692 115385

Error rate
-0.16% 0.16% 0.16% 0.16% -0.79% 0.16% 0.16%

TH1 Setting Value

SMOD=0
Actual Baud rate:

100

4808

178

9615

204

14423

217

19231

236

37500

243

57692

243

57692

249

107143

Error rate
0.16% 0.16% 0.16% 0.16% -2.34% 3.02% 0.16% -6.99%

13.6 Related Register

Name
PCON SCON0 SBUF0 USART_SEL

SFR page
0 0 0 0

address
0x87 0x98 0x99 0x9F

default values
0x00 0x00 0x00 0x01

Functions
Power Control Register Serial port control register Serial port 0 data cache register Timer1 clock source prescaler selection

Rev 0.1A | 68/100 Page

www.hoperf.com

14 Timer A/Timer B Module

AN261-CMT2186A User Guide

Both Timer A and Timer B consist of a 16-bit timer/counter and three capture/comparators, enabling multiple capture/comparators, PWM outputs, and time intervals for counting trigger conditions. Timer A has multiple interrupt modes that trigger overflows and capture/comparators from the timer/counter. Characteristics of Timer A / Timer B includes

16-bit timing/counter supporting 4 operating modes; Support for configuring the the clock source as the system clock 1 ~ 65535 frequency division . 2 or 3 configurable capture/comparators; Configurable PWM output; Asynchronous input sampling; Quickly capturing the interrupt source

Timer clock

ta_cnt_mode Timer Block

system clock FSYSCLK

DIVIDER 1~65535

16bit Timer TACNT
clear
ta_clr

Count Mode

EQU0

Set Timer IFG

taccr2_ccis taccr2_cm

(from GPIO)tacci0 (from GPIO)tacci1 (from SFR)tacci2

00 01

(from SFR)tacci3 10

Capture Mode

taccr2_cov_set logic

sync

taccr2_cci

Timer clock taccr2_scs

taccr2_scci A
Y EN

EQU2

EQU2 EQU0 taccr2_out

Output Unit2

ta_out2

CCR0 CCR1 CCR2

TACCR2

comparator2
EQU2
0 1

Set CCR2 CCIFG

taccr2_cap

taccr2_outmode
Chart 14-1. Diagram of Timer A Structure

Rev 0.1A | 69/100 Page

www.hoperf.com

AN261-CMT2186A User Guide
Note: The structure of Timer A and Timer B are identical. The figure above shows the structure of Timer A.

14.1 Operation Method

The operation of Timer A/Timer B module is controlled by software. TACCR0TH/TBCCR0TH mentioned in this section is a configurable 16-bit count threshold. It is consists of register TACCR0TH_H/TBCCR0TH_H and TACCR0TH_L /TBCCR0TH_L. Table 14-1 lists the counting modes of the 16-bit timing/counter (TACNT and TBCNT) according to different working modes.

Table 14-1. Work Modes of Timer

TA/TB_CNT_MODE 00 01 10
11

Working Mode Stop Up
Continuous
Up/ Down

Description

TACNT/TBCNT does not work and stops counting , namely count stop mode

TACNT/TBCNT increments repeatedly from 0 to the TACCR0TH/TBCCR0TH

value, namely count up mode

TACNT/TBCNT repeatedly increments from 0 to 0xFFFF, namely continuous

counting mode

TACNT/TBCNT

repeatedly

increments

from

TACCR0TH/TBCCR0TH,then decreasing to 0, in cycle, namely continuous

counting mode.

As can be seen from the above table, Timer A or Timer B includes four working modes: Stop, Up, Continuous, Up/Down, and the working mode can be determined by configuring TA_CNT_MODE or TB_CNT_MODE. When it is necessary to temporarily modify the operating mode of Timer A or Timer B (except the modification of interrupt enabling and interrupt flag), suggest stopping the TACNT or TBCNT counting first to avoid unpredictable misoperation.

In count up mode, TACNT or TBCNT generates an interrupt once it reaches the setting threshold TACCR0TH/TBCCR0TH. In continuous count mode, TACNT or TBCNT will generate an interrupt once it reaches 0xFFFF. In Up/Down mode, TACNT or TBCNT will generate interrupt once decrement to 0x0001.

Before starting Timer A or Timer B, configure TAC_L.TA_CNT_MODE or TBC_L.TB_CNT_MODE (non-stop mode), count threshold TACCR0TH or TBCCR0TH value (0), capture/compare parameters (see section 4.14.5). Then set TAC_H.TA_START or TBC_H.TB_START to zero first and then to 1 to trigger effectively.

During counting, user can set TACL.TA_CLR or TBCL.TB_CLR to 1 to clear most of the counter configuration. Take Timer A as an example, values that TA_CLR can clear include: Count clock source frequency division value TACLK_DIV, count value TACNT, counter working mode TA_CNT_MODE and count threshold TACCR0TH.

Rev 0.1A | 70/100 Page

www.hoperf.com

14.2 Up Mode

AN261-CMT2186A User Guide

In Up mode, user can configure the count threshold TACCR0TH or TBCCR0TH to any value, and TACNT (or TBCNT) will increase from 0 to the threshold TACCR0TH (or TBCCR0TH) repeatedly, with the count period being TACCR0TH (or TBCCR0TH) +1. When the TACNT (or TBCNT) count reaches the threshold, it immediately returns to 0 to re-count.

0xFFFF TACCR0 (TBCCR0)
0

Chart 14-2. Schematic for Timer A/ Timer B Works in Up Mode

When TACNT (or TBCNT) counts to TACCR0TH or TBCCR0TH and overflows back to 0, the interrupt flag TA_CCR0_INT or TB_CCR0_INT is set, The interrupt flag TA_TMR_INT (or TB_TMR_INT) of Timer A (or Timer B) is set one beat later than TA_CCR0_INT. The following diagram shows the generation diagram of two different interrupts after the pre-split value TA_CLK_DIV is set to 3:

SYS_CLK TACNT

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

CCR0-1

CCR0

TA_CCR0_INT TA_TMR_INT

Chart 14-3. Schematic for Interrupt of Timer A Working in Up Mode

It is not recommended to modify the value of TACCR0TH (or TBCCR0TH) during the counting process of TACNT (or TBCNT). In case users have modifications forcedly, it will have the below 2 effect depending on different conditions. 1. If the new TACCR0TH (or TBCCR0TH) modification value is greater than the previous one, or greater than
the current TACNT (or TBCNT) count value, TACNT (or TBCNT) will continue counting to the new TACCR0TH (or TBCCR0TH) value and then return to 0 to recount. 2. If the new TACCR0TH (or TBCCR0TH) modification value is less than the previous TACNT (or TBCNT) count value, the TACNTor TBCNTwill be immediately set 0, and it will continue counting to new TACCR0TH (or TBCCR0TH).

Rev 0.1A | 71/100 Page

www.hoperf.com

14.3 Continuous Mode

AN261-CMT2186A User Guide

In continuous mode, TACNT (or TBCNT) is increased from 0 to 0xFFFF repeatedly, reset and then counts from 0. In this mode, the 3 sets of capturer/comparator CCR0 ~ CCR2 have the same function and operate independently, which is different with the up mode. In Up mode, TACCR0TH (or TBCCR0TH) is the period value of the TACNT (or TBCNT) count.

0xFFFF

Chart 14-4. Schematic for Timer A Works in Continuous Mode
In the continuous mode, the capture/compare module can generate interrupts separately, as shown in the below figure.
When TACNT (TBCNT) counts to the TACCR0TH+1 (TBCCR0TH+1) value, the interrupt flag TA_CCR0_INT (TB_CCR0_INT) of the comparator ta_ccr0 or tb_ccr0 is set.
When TACNT (TBCNT) counts to 0xFFFF and then returns to 0 to re-count, the Timer interrupt flag TA_TMR_INT (TB_TMR_INT) is set.

SYS_CLK TACNT

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

TACCR0TH-1 TACCR0TH TACCR0TH+1

0 xFFFE 0 xFFFF

TA_CCR0_INT TA_TMR_INT

Chart 14-5. Schematic for Interrupt of Timer A Working in Continuous Mode

The Continuous mode can be used to generate independent time intervals and output frequencies by the above ways. In the case of comparator ccr0, Timer A will generate an interrupt when counting to TACCR0TH. After the software detects this interrupt in the register, it can configure the comparison threshold TACCR0TH to TACCR0TH + n, where n is the set period value and n<0XFFFF. Keep updating the value of TACCR0TH in cycles and interrupts of n period is generated.

Therefore, three sets of capture/comparators ta_ccr0~ ta_ccr2 (tb_ccr0~ tb_ccr2) are used to produce three sets of independent time interval and frequency outputs, as shown in the figure below, where TACCR0THa, TACCR0THb, TACCR0THc, and TACCR0THd are the values

Rev 0.1A | 72/100 Page

www.hoperf.com

AN261-CMT2186A User Guide
calculated via the equation of TACCR0TH =TACCR0TH+ n, the same goes for ta_ccr1.

TACCR1THb TACCR1THc TACCR1THd

0xFFFF

TACCR0THb

TACCR1THa

TACCR0THa

TACCR0THc TACCR0THd

Chart 14-6. Schematic for Independent Operation of Each Capture/Compare of Timer A (Same for Timer B)

14.4 Up / Down Mode
In Up/Down mode, TACNT (TBCNT) increments repeatedly from 0 to TACCR0TH (TBCCR0TH) and then decrements to 0. One period is twice the TACCR0TH (TBCCR0TH) value.
0xFFFF TACCRTH0 (TBCCRTH0)
0
Chart 14-7. Schematic for Timer A / B Works in Up / Down Mode
TA_CCR0_INT (TB_CCR0_INT) interrupt of ta_ccr0 and tb_ccr0 and TA_TMR_INT (TB_TMR_INT) interrupt flags of TACNT (TBCNT) are distributed in the first and second half in one cycle. Similarly to Up mode, when TACNT (TBCNT) counts to the TACCR0TH (TBCCR0TH) value, interrupt flag TA_CCR0_INT (TB_CCR0_INT) of ta_ccr0 is set. When TACNT (TBCNT) counts to the threshold of ta_ccr0 and returns to 0 to count again, the Timer A (Timer B) interrupt flag TA_TMR_INT (TB_TMR_INT) is set.

Rev 0.1A | 73/100 Page

www.hoperf.com

SYS_CLK

AN261-CMT2186A User Guide
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

TACNT

TACCR0TH-1 TACCR0TH TACCR0TH-1

TA_CCR0_INT

TA_TMR_INT

Chart 14-8. Schematic for Interrupt of Timer A Working in Up/ Down Mode
The up / down mode can support the application requiring Dead Time between two output signals. For example, 2 outputs that drive an H-bridge synchronously while cannot output a high level at the same time to avoid overload.
TDead=TTimerxTACCR1THTACCR2TH
In above, 1. TDead refers to the duration of the dead time 2. TTimer refers to the clock period of TACNT or TBCNT 3. TACCR1TH and TACCR2TH refer to the configuration values of the 2 sets of capturer/comparators.

0xFFFF
TACCR0TH
TACCR1TH TACCR2TH
0

Dead Time Output Mode 6: Toggle/Set

EQU1

EQU2

EQU0

Timer INT

EQU1 EQU2

Timer INT

EQU0

Output Mode 2: Toggle/Reset
EQU1 EQU2

Chart 14-9. Schematic for Up / Down Mode with Dead Time Control

Rev 0.1A | 74/100 Page

www.hoperf.com

14.5 Capture/compare Module

AN261-CMT2186A User Guide

Timer A / B contains 2 to 3 independent capture/compare modules for capturing TACNT (or TBCNT) data or generating time intervals. Note that, in Up and Up / Down modes, TACCR0 (TBCCR0) is used as a period register and cannot store captured values.

In Continuous modeboth ta_ccr0~ ta_ccr2tb_ccr0~ tb_ccr2can store captured values.

Capture Mode
If TACCTL0_H.TA_CCR0_FUNC_MODE to TA_CCR2_FUNC_MODE is set to 1, the corresponding capture/comparison module enters the capture mode. Capture mode is used to record time related events, such as speed estimates or time measurements. There are 4 capture sources, of which TACCI0 and TACCI1 are from GPIOn (configurable selection, see Section 4.9 GPIO Module for details) and TAC_H.TA_CCI2_IN_SFR and TAC_H.TA_CCI3_IN_SFR are from internal SFR registers, accessible to software. By configuring TA_CCR0_SRC_SEL – TA_CCR1_SRC_SEL can select different capture sources (CCI0 – CCI3) for three capture channels. Timer B is exactly the same,the same hereinafter. Configure TACCR0_CM ~ TACCR2_CM to select the capture mode of the corresponding capture/compare module as rising edge, falling edge or double edge trigger. After successful capture, the TACNT value will be stored in the TACCRn register of the corresponding capture/comparison module, and their interrupt flag TA_CCR0_INT~TA_CCR2_INT will be set at the same time.

Configure TACCR0_SCS ~ TACCR2_SCS to select whether to perform system clock synchronization on the capture source.

Timer clock TACNT CCI
TA_CCR0_FUNC_MODE TA_CCR0_INT
TACCR0TH

n-2

n-1

n+1

n+2

n+3

n+4

Chart 14-10. Schematic for Timer A Capture Mode

If the previous capture result has not been read, and the capture source is triggered again and generate capture overflow, the COV flag of the corresponding capture/comparison module will be set to 1, which will be re-captured after being cleared by the software.

Rev 0.1A | 75/100 Page

www.hoperf.com

Recapture
Clear the corresponding
COV bit

AN261-CMT2186A User Guide

Trigger capture source
Capture success

Read capture

Read capture result

Trigger capture source No capture occurs after reading
Trigger capture source

Capture overflow COV=1

Trigger capture source
Chart 14-11. Schematic for Capture Mode State and Interrupt of Timer A
Compare mode
When TA_CCR0_FUNC_MODE ~ TA_CCR2_FUNC_MODE is set to 0, the corresponding capture/compare module enters the compare mode. The compare mode is used to generate a PWM output signal or generate an interrupt at a specific time interval. When TACNT counts to TACCR0TH ~ TACCR2TH

1) The corresponding interrupt flag TACCR0 /1/2 is set to 1. 2) The corresponding count is equal means that the signal of EQU0 ~ EQU2 is set to 1; 3) EQU0~EQU2 affects the output signal according to different output modes; 4) The capture source selected by each comparator is stored in the corresponding TA_CCR0_SRC ~
TA_CCR2_SRC register;
Output Units
Each capture/comparison module contains an output unit to generate output signal such as PWM signal. Each output unit is based on EQU0 and EQU1/EQU2 signals and can be combined into eight output modes.
TA_CCR0_OUT_MODE ~ TA_CCR2_OUT_MODE is the output configuration register for the corresponding capture/compare module, where output modes of 2, 3, 6, and 7 do not apply to output the 0 unit because EQUx = EQU0. (EQUx means EQU1 and EQU2)

Rev 0.1A | 76/100 Page

www.hoperf.com

AN261-CMT2186A User Guide

Table 14-2. Various Modes of Output Unit

OUTMODE

Mode

Description

REMARKS

Direct mode, the output TA_OUTx is configured by

Applicable to the 3

000

OUTPUT

capture/compare modules.

When TACNT counts to TACCRxTH, the output

TA_OUTx is set and the state retains until Timer A is

Applicable to the 3

001

bits

reset or the output mode changes and affects the

capture/compare modules.

output..

When TACNT counts to TACCRxTH, the output

Only applicable to capture 1

010

TA_OUTx flips. When TAR counts to TACCR0TH,

and 2

output TA_OUTx resets.

When TACNT counts to TACCRxTH, the output

Set bits /

Only applicable to capture 1

011

TA_OUTx is set. When TAR counts to TACCR0TH,

reset

and 2

output TA_OUTx resets.

When TACNT counts to TACCRxTH, the output

Applicable to the 3

100

Flip

TA_OUTx flip

capture/compare modules.

When TACNT counts to TACCRxTH, the output

Applicable to the 3

101

Reset

TA_OUTx is reset and the state retains until the

capture/compare modules.

output mode changes and affects the output..

When TACNT counts to TACCRxTH, the output

Only applicable to capture 1

110

Flip / Reset

TA_OUTx flips. When TAR counts to TACCR0TH,

and 2

output TA_OUTx is set..

When TACNT counts to TACCRxTH, the output

Only applicable to capture 1

111

Resets/ bits TA_OUTx reset. When TAR counts to TACCR0TH,

and 2

output TA_OUTx is set..

Notice: 1. T

Documents / Resources

HOPERF CMT2186A Sub-1G Transmitting Micro Controller [pdf] User Guide
CMT2186A Sub-1G Transmitting Micro Controller, CMT2186A Sub-1G, Transmitting Micro Controller, Micro Controller, Controller

References

User Manual

CMT2186A Sub-1G Transmitting Micro Controller

Product Specifications

Product Usage Instructions

1. Powering On the CMT2186A

2. Modulation Settings

3. Output Power Adjustment

4. Memory Usage

5. Working Temperature

Frequently Asked Questions (FAQ)

Q: What is the working frequency range of the CMT2186A?

Q: How can I adjust the output power of the transmitter
module?

Q: What is the memory capacity of the CMT2186A?

Documents / Resources

References

Leave a comment

Cancel reply