STMicroelectronics STM32H5 Series Microcontrollers

Gabatarwa

Wannan bayanin kula na aikace-aikacen yana bayyana cache na umarni (ICACHE) da cache na bayanai (DCACHE), cache na farko da SMicroelectronics ya haɓaka. ICACHE da DCACHE da aka gabatar akan bas ɗin AHB na Arm® Cortex®-M33 processor an saka su a cikin STM32 microcontroller (MCUs) da aka jera a teburin da ke ƙasa. Waɗannan caches suna ba masu amfani damar haɓaka aikin aikace-aikacen su kuma rage yawan amfani lokacin da ake ɗauko umarni da bayanai daga ƙwaƙwalwar ciki da waje, ko don zirga-zirgar bayanai daga ƙwaƙwalwar waje. Wannan takaddun yana ba da misali exampdon haskaka fasalin ICACHE da DCACHE da sauƙaƙe tsarin su.

Tebur 1. Abubuwan da suka dace

Nau'in	Jerin samfur
Microcontrollers	jerin STM32H5, STM32L5 jerin, STM32U5

Janar bayani

Lura:

Wannan bayanin kula na aikace-aikacen ya shafi jerin STM32 microcontrollers waɗanda ke tushen na'urorin Arm® Cortex® ne. Arm alamar kasuwanci ce mai rijista ta Arm Limited (ko rassan sa) a cikin Amurka da/ko wani wuri.

ICACHE da DCACHE sun ƙareview

Wannan sashe yana ba da ƙarewaview na musaya na ICACHE da DCACHE da aka saka a cikin STM32 Arm® Cortex® core-based microcontrollers. Wannan sashe yana ba da cikakken bayani game da zane na ICACHE da DCACHE da haɗin kai a cikin tsarin gine-gine.
STM32L5 jerin wayayyun gine-gine
Wannan gine-ginen ya dogara ne akan matrix na bas yana ba da izinin masters da yawa (Cortex-M33, ICACHE, DMA1/2, da SDMMC1) don samun dama ga bayi da yawa (kamar ƙwaƙwalwar walƙiya, SRAM1/2, OCTOSPI1, ko FSMC). Hoton da ke ƙasa yana kwatanta tsarin gine-gine mai kaifin STM32L5.

Hoto na 1. STM32L5 jerin wayayyun gine-gine

An inganta aikin Cortex-M33 ta hanyar amfani da 8-Kbyte ICACHE interface da aka gabatar a cikin motar sa ta C-AHB, lokacin da ake samo code ko bayanai daga ƙwaƙwalwar ajiyar ciki (flash memory, SRAM1, ko SRAM2) ta hanyar bas mai sauri, da kuma daga ƙwaƙwalwar waje (OCTOSPI1 ko FSMC) ta cikin bas ɗin jinkirin.
STM32U5 jerin wayayyun gine-gine
Wannan gine-ginen ya dogara ne akan matrix bas yana ba da izinin masters da yawa (Cortex-M33, ICACHE, DCACHE, GPDMA, DMA2D da SDMMCs, OTG_HS, LTDC, GPU2D, GFXMMU) don samun dama ga bayi da yawa (kamar ƙwaƙwalwar walƙiya, SRAMs, BKPSRAM, HSPI/ OCTOSPI, ko FSMC).Hoton da ke ƙasa yana kwatanta tsarin STM32U5 mai kaifin gine-gine.

Hoto 2. STM32U5 jerin wayayyun gine-gine

Abubuwan haɗin Cortex-M33 da GPU2D duka suna amfana daga amfani da CACHE.

• ICACHE yana inganta aikin Cortex-M33 lokacin da ake samo lamba ko bayanai daga memories na ciki ta cikin bas mai sauri (ƙwaƙwalwar ƙwaƙwalwa, SRAMs) kuma daga ƙwaƙwalwar waje ta cikin bas ɗin jinkirin (OCTOSPI1/2 da HSPI1, ko FSMC). DCACHE1 yana haɓaka aiki lokacin da ake samo bayanai daga abubuwan ƙwaƙwalwar ciki ko waje ta s-bus (GFXMMU, OCTOSPI1/2 da HSPI1, ko FSMC).
•  DCACHE2 yana inganta aikin GPU2D lokacin da aka samo bayanai daga ƙwaƙwalwar ciki da waje (GFXMMU, ƙwaƙwalwar filashi, SRAMs, OCTOSPI1/2 da HSPI1, ko FSMC) ta hanyar tashar tashar tashar M0.

STM32H5 jerin wayayyun gine-gine
STM32H523/H533, STM32H563/H573 da STM32H562 smart architecture Wannan gine-ginen ya dogara ne akan matrix bas yana ba da izinin masters da yawa (Cortex-M33, ICACHE, DCACHE, GPDMAs, Ethernet da SDMMCs) don samun dama ga bayi masu yawa (kamar ƙwaƙwalwar ajiyar BPSK, SRAM). , OCTOSPI da FMC). Hoton da ke ƙasa yana bayanin tsarin gine-gine mai kaifin STM32H5.

Hoto na 3. STM32H563/H573 da STM32H562 jerin wayayyun gine-gine

Cortex-M33 yana amfana daga amfani da CACHE.

• ICACHE yana inganta aikin Cortex-M33 lokacin da ake samo lamba ko bayanai daga memories na ciki ta hanyar bas mai sauri (ƙwaƙwalwar ajiya, SRAMs) kuma daga ƙwaƙwalwar waje ta hanyar bas ɗin jinkirin (OCTOSPI da FMC).
• DCACHE yana inganta aikin lokacin da ake samo bayanai daga abubuwan tunanin waje ta cikin bas ɗin jinkirin (OCTOSPI da FMC).

Saukewa: STM32H503
Wannan gine-ginen ya dogara ne akan matrix na bas yana ba da izinin masters da yawa (Cortex-M33, ICACHE da GPDMAs) don samun dama ga bayi da yawa (kamar ƙwaƙwalwar filasha, SRAMs da BKPSRAM). Hoton da ke ƙasa yana bayanin tsarin gine-gine mai kaifin STM32H5.

Hoto 4. STM32H503 jerin wayayyun gine-gine

Cortex-M33 yana amfana daga amfani da CACHE.

• ICACHE yana inganta aikin Cortex-M33 lokacin da ake samun lamba ko bayanai daga memories na ciki ta hanyar bas mai sauri (ƙwaƙwalwar ƙwaƙwalwa, SRAMs).

ICACHE toshe zane
An ba da zanen toshe ICACHE a cikin hoton da ke ƙasa.

Hoto na 5. ICACHE toshe zane

Ƙwaƙwalwar ICACHE ta ƙunshi:

• da TAG memory tare da:
  • adireshin tags wanda ke nuna waɗanne bayanai ke ƙunshe a cikin ma'adanar bayanan cache
  • ingancin bits
•  ƙwaƙwalwar ajiyar bayanai, wanda ya ƙunshi bayanan da aka adana

Tsarin toshe DCACHE
An ba da zanen toshe DCACHE a cikin hoton da ke ƙasa.

Hoto na 6. Tsarin toshe DCACHE

Ƙwaƙwalwar DCACHE ta ƙunshi:

• da TAG memory tare da:
  • adireshin tags wanda ke nuna waɗanne bayanai ke ƙunshe a cikin ma'adanar bayanan cache
  • ingancin bits
  • 'yan gata
  • da datti rago
• ƙwaƙwalwar ajiyar bayanai, wanda ya ƙunshi bayanan da aka adana

ICACHE da DCACHE fasali

Masters biyu
ICACHE tana shiga matrix bas na AHB ko dai:

• Babban tashar jiragen ruwa na AHB: master1 (bas mai sauri)
• Babban tashar jiragen ruwa na AHB guda biyu: master1 (bas mai sauri) da master2 (bas mai jinkirin)

Wannan fasalin yana ba da damar haɓaka zirga-zirgar zirga-zirgar zirga-zirgar lokacin shiga yankuna daban-daban na ƙwaƙwalwar ajiya (kamar ƙwaƙwalwar ajiyar filasha ta ciki, SRAM na ciki da ƙwaƙwalwar waje), don rage rumbun CPU akan cache. Tebur mai zuwa yana taƙaita yankunan ƙwaƙwalwar ajiya da adiresoshin su.

Table 2. Yankunan ƙwaƙwalwar ajiya da adiresoshin su

Na gefe				Samun damar ƙwaƙwalwar ajiya mai iya cache			Ba samun damar ƙwaƙwalwar ajiya ba
Nau'in	Suna	Sunan samfur da girman yanki		Sunan bas	Adireshin farawa yanki mara tsaro	Amintaccen, adireshin farawa yanki mara tsaro	Sunan bas	Adireshin farawa yanki mara tsaro	Amintaccen, adireshin farawa yanki mara tsaro
Na ciki	FLASH	Saukewa: STM32H503	128 KB	ICACHE bas mai sauri	0 x0800	N/A	N/A	N/A	N/A
		Saukewa: STM32L5 jerin/ STM32U535/545/ STM32H523/533	512 KB			0x0C00 0000
		Saukewa: STM32U575/585 STM32H563/573/562	2 MB
		STM32U59x/ 5Ax/5Fx/5Gx	4 MB
	SRAM1	Saukewa: STM32H503	16 KB		0x0A00 0000	N/A	S- bas	0 x2000	0 x3000
		Saukewa: STM32L5 series/ STM32U535/ 545/575/585	192 KB			0x0E00 0000
		Saukewa: STM32H523/533	128 KB
		STM32H563/573/562	256 KB
		STM32U59x/ 5Ax/5Fx/5Gx	768 KB
	SRAM2	Saukewa: STM32H503 jerin	16 KB		0x0A00 4000	N/A		0 x2000	N/A
		Saukewa: STM32L5 series/ STM32U535/ 545/575/585	64 KB		0x0A03 0000	0x0E03 0000		0 x2003	0 x3003
		Saukewa: STM32H523/533	64 KB		0x0A04 0000	0x0E04 0000		0 x2004	0 x3004

Na gefe				Samun damar ƙwaƙwalwar ajiya mai iya cache			Ba samun damar ƙwaƙwalwar ajiya ba
Na ciki	SRAM2	STM32H563/573/562	80 KB	ICACHE bas mai sauri	0x0A04 0000	0x0E04 0000	S- bas	0 x2004	0 x3004
		STM32U59x/ 5Ax/5Fx/5Gx	64 KB		0x0A0C 0000	0x0E0C 0000		0x200C 0000	0x300C 0000
	SRAM3	Saukewa: STM32U575/585	512 KB		0x0A04 0000	0x0E04 0000		0 x2004	0 x3004
		Saukewa: STM32H523/533	64 KB		0x0A05 0000	0x0E05 0000		0 x2005	0 x3005
		STM32H563/573/562	320 KB
		STM32U59x/ 5Ax/5Fx/5Gx	832 KB		0x0A0D 0000	0x0E0D 0000		0x200D 0000	0x300D 0000
	SRAM5	STM32U59x/ 5Ax/5Fx/5Gx	832 KB		0x0A1A 0000	0x0E1A 0000		0x201A 0000	0x301A 0000
	SRAM6	STM32U5Fx/ 5gx ku	512 KB		0x0A27 0000	0x0E27 0000		0 x2027	N/A
Na waje	HSPI1	STM32U59x/ 5Ax/5Fx/5Gx	256 MB	ICACHE bas a hankali (1)	Adireshin laƙabi a cikin kewayon [0x0000 0000 zuwa 0x07FF FFFF] ko [0x1000 0000: 0x1FFF FFFF] an ayyana ta hanyar fasalin fasalin	N/A		0xA 000 0000
	FMC SDRAM	STM32H563/573/562						0xC000 0000
	OCTOSPI1 banki mara tsaro	Saukewa: STM32L5/U5 jerin STM32H563/573/562						0 x9000
	FMC Bank 3 rashin tsaro	Saukewa: STM32L5/U5 jerin STM32H563/573/562						0 x8000
	OCTOSPI2 banki mara tsaro	STM32U575/ 585/59x/5Ax/ 5Fx/5Gx						0 x7000
	FMC Bank 1 rashin tsaro	Saukewa: STM32L5/U5 jerin STM32H563/573/562						0 x6000

1. Za a zaɓa lokacin da ake yin taswirar irin waɗannan yankuna.

Hanya 1 da ICACHE 2-way
Ta hanyar tsoho, ana saita ICACHE a cikin yanayin aiki na haɗin gwiwa (hanyoyi biyu sun kunna), amma yana yiwuwa a saita ICACHE a yanayin taswira kai tsaye (an kunna hanya ɗaya), don aikace-aikacen da ke buƙatar ƙarancin wutar lantarki. Ana yin tsarin ICACHE tare da bit WAYSEL a cikin ICACHE_CR kamar haka:

• WAYSEL = 0: Yanayin aiki na taswira kai tsaye (hanyar 1)
• WAYSEL = 1 (tsoho): Yanayin aiki na haɗin gwiwa (hanyar 2)

Tebur 3. Hanya 1 da ICACHE 2-way

Siga	1-hanya ICACHE	2-hanya ICACHE
Girman cache (Kbytes)	8(1)/32(2)
Cache hanyoyi da yawa	1	2
Girman layin cache	128 bits (16 bytes)
Adadin layukan cache	512(1)/2048(2)	256 (1) / 1024 (2) kowace hanya

1. Don jerin STM32L5 / jerin STM32H5 / STM32U535/545/575/585
2. For STM32U59x/5Ax/5Fx/5Gx

Nau'in fashewa
Wasu ƙwaƙwalwar Octo-SPI suna goyan bayan fashewar WRAP, wanda ke ba da fa'idar aiki mai mahimmanci na kalma-farko. Nau'in fashewar ICACHE na ma'amalar ƙwaƙwalwar ajiyar AHB don yankuna da aka sake taswira ana iya daidaita su. Yana aiwatar da fashewar ƙara ko fashewar WRAP, wanda aka zaɓa tare da bit HBURST a cikin rajistar ICACHE_CRRx. Ana ba da bambance-bambance tsakanin WRAP da fashewar ƙara a ƙasa (duba kuma adadi):

• WRAP ya fashe:
  • Girman layin cache = 128 bits
  • fashe don fara adireshin = adireshin kalma na bayanan farko da CPU ta nema
•  Kara fashewa:
  • Girman layin cache = 128 bits
  • fashe farawa adireshin = adireshin da aka daidaita akan iyakar layin cache mai dauke da kalmar da aka nema

Hoto na 7. Ƙaruwa da WRAP ya fashe

Yankunan da za a iya adanawa da fasalin sake taswira
An haɗa ICACHE zuwa Cortex-M33 ta cikin motar C-AHB kuma tana adana yankin lambar daga adireshi [0x0000 0000 zuwa 0x1FFF FFFF]. Tunda an tsara abubuwan ƙwaƙwalwar waje a adireshi a cikin kewayon [0x6000 0000 zuwa 0xAFFF FFFF], ICACHE tana goyan bayan fasalin taswira wanda ke ba da damar kowane yanki na ƙwaƙwalwar waje a sake taswira a adireshin da ke cikin kewayon [0x0000 0000 zuwa 0x07FF FFFF] ko [0x1000 0000 zuwa 0x1FFF FFFF], kuma don samun dama ta bas ɗin C-AHB. Har zuwa yankuna huɗu na ƙwaƙwalwar ajiya na waje ana iya sake taswira tare da wannan fasalin. Da zarar an sake taswirar yanki, aikin sake fasalin yana faruwa ko da an kashe ICACHE ko kuma idan ma'amalar ba ta ɓoye ba. Yankunan ƙwaƙwalwar ajiya waɗanda za a iya ƙera su kuma mai amfani ya tsara su a cikin naúrar kariyar ƙwaƙwalwar ajiya (MPU). Teburin da ke ƙasa yana taƙaita daidaitawar jerin abubuwan ƙwaƙwalwar STM32L5 da STM32U5.

Table 4. Kanfigareshan STM32L5 da STM32U5 jerin abubuwan tunawa

Ƙwaƙwalwar samfur	Mai iya cache (MPU shirye-shirye)	An sake tsarawa a cikin ICACHE (ICACHE_CRRx shirye-shirye)
Flash memory	Ee ko A'a	Ba a buƙata
SRAM	Ba a ba da shawarar ba
Tunawa da waje (HSPI/ OCTOSPI ko FSMC)	Ee ko A'a	Ana buƙata idan mai amfani yana son fitar da lambar waje akan bas ɗin C- AHB (wani akan bas ɗin S-AHB)

Fa'idodin ICACHE na rage ƙwaƙwalwar ajiyar waje
The example a cikin hoton da ke ƙasa yana nuna yadda ake amfana daga ingantaccen aikin ICACHE yayin aiwatar da code ko karanta bayanan lokacin samun damar ƙwaƙwalwar Octo-SPI ta waje ta 8-Mbyte (kamar ƙwaƙwalwar filashin waje ko RAM).

Hoto na 8. Octo-SPI remap memory example

Ana buƙatar matakai masu zuwa don gyara wannan ƙwaƙwalwar ajiyar waje:

Tsarin OCTOSPI don ƙwaƙwalwar waje

Saita hanyar sadarwa ta OCTOSPI don samun damar ƙwaƙwalwar ajiyar waje a cikin yanayin taswira na Ƙwaƙwalwar ajiya (ana ganin ƙwaƙwalwar waje azaman ƙwaƙwalwar ciki da aka tsara a cikin yankin [0x9000 0000 zuwa 0x9FFF FFFF]). Tunda girman ƙwaƙwalwar ajiyar waje shine 8 Mbytes, ana ganinta a yankin [0x9000 0000 zuwa 0x907F FFFF]. Ƙwaƙwalwar ajiyar waje a wannan yanki ana samun dama ta cikin bas ɗin S-bas kuma ba za a iya ɓoyewa ba. Mataki na gaba yana nuna tsarin ICACHE don sake fasalin wannan yanki.
Lura: Don daidaitawar OCTOSPI a yanayin da aka yi taswirar ƙwaƙwalwar ajiya, koma zuwa bayanin aikace-aikacen Octo-SPI akan masu sarrafa STM32 (AN5050).

Tsarin ICACHE don sake taswirar yankin da aka yi taswirar ƙwaƙwalwar ajiya na waje
8 Mbytes da aka sanya a cikin [0x9000 0000 zuwa 0x907F FFFF] an sake tsara su zuwa yankin [0x1000 0000 zuwa 0x107F FFFF]. Ana iya samun su ta hanyar bas ɗin jinkirin (ICACHE master2 bas).

• Tsarin rijistar ICACHE_CR
  • Kashe ICACHE tare da EN = 0.
  • Zaɓi 1-way ko 2-way (dangane da bukatun aikace-aikacen) tare da WAYSEL = 0 ko 1, bi da bi.
• Tsarin rijistar ICACHE_CRRx (har zuwa yankuna huɗu, x = 0 zuwa 3)
  • Zaɓi adireshin tushe 0x1000 0000 (adireshin sake taswira) tare da BASEADDR [28:21] = 0x80.
  • Zaɓi girman yankin 8-Mbyte don yin taswira tare da RSIZE[2:0] = 0x3.
  • Zaɓi adireshin 0x9000 0000 da aka sake taswira REMAPADDR[31:21] = 0x480.
  • Zaɓi tashar tashar ICACHE AHB master2 don ƙwaƙwalwar waje tare da MSTSEL = 1.
  • Zaɓi nau'in fashewar WRAP tare da HBURST = 0.
  • Kunna sake taswirar yanki x tare da REN = 1.

Hoto mai zuwa yana nuna yadda ake ganin yankunan ƙwaƙwalwar ajiya tare da IAR bayan kunna taswirar.

Hoto 9. Yankunan ƙwaƙwalwar ajiya da ke sake taswira example

Ƙwaƙwalwar 8-Mbyte na waje yanzu an sake tsara shi kuma ana iya samun dama ga yankin [0x1000 0000 zuwa 0x107F FFFF].

ICACHE kunna

• Tsarin rijistar ICACHE_CR Kunna ICACHE tare da EN = 1.

Buga-da-miss saka idanu
ICACHE tana ba da masu saka idanu guda biyu don nazarin aiki: mai lura da bugu 32-bit da mai saka idanu miss 16-bit.

• Mai lura da bugu yana ƙididdige ma'amalar AHB mai cacheable akan tashar cache ɗin bawa wanda ya taɓa abun cikin ICACHE (da aka samo bayanan da aka rigaya a cikin cache). Ana samun ma'aunin duba da bugu a cikin rajistar ICACHE_HMONR.
• Mai saka idanu na kuskure yana ƙididdige ma'amalar AHB mai cacheable akan tashar cache ɗin bawa wanda ya ɓace abun cikin ICACHE (ba a riga an samo bayanan da aka samo a cikin cache). Akwai ma'aunin da ya ɓace a cikin rajistar ICACHE_MMONR.

Lura:

Waɗannan na'urori biyu ba sa nannade lokacin da suka kai iyakar ƙimar su. Ana sarrafa waɗannan masu saka idanu daga ragi masu zuwa a cikin rajistar ICACHE_CR:

• HITMEN bit (bi da bi MISSMEN bit) don kunna / dakatar da bugun (bi da bi miss) saka idanu
• HITMRST bit (bi da bi MISSMRST bit) don sake saita buga (bi da bi miss) saka idanu Ta hanyar tsoho, ana kashe masu saka idanu don rage amfani da wutar lantarki.

Kulawar ICACHE
Software na iya bata ICACHE ta hanyar saita cacheINV bit a cikin rajistar ICACHE_CR. Wannan aikin yana lalata duk cache ɗin, yana mai da shi fanko. A halin yanzu, idan an kunna wasu yankuna da aka sake taswira, fasalin taswirar yana aiki har yanzu, koda lokacin da ICACHE ke kashewa. Kamar yadda ICACHE kawai ke sarrafa ma'amalar karantawa kuma baya sarrafa ma'amalar rubutu, baya tabbatar da daidaituwa a cikin yanayin rubutu. Don haka, dole ne software ta bata ICACHE bayan shirya wani yanki.

ICACHE tsaro
ICACHE yanki ne mai tsaro wanda za'a iya saita shi azaman amintacce ta GTZC TZSC amintaccen rijistar sanyi. Lokacin da aka saita shi azaman amintacce, amintattun hanyoyin shiga kawai ana ba da izinin yin rijistar ICACHE. Hakanan za'a iya saita ICACHE azaman gata ta hanyar rijistar gata na GTZC TZSC. Lokacin da aka saita ICACHE a matsayin mai gata, masu gata kawai ake ba da izinin shiga rajistar ICACHE. Ta hanyar tsoho, ICACHE ba ​​shi da tsaro kuma ba shi da gata ta GTZC TZSC.

Gudanar da taron da katsewa

ICACHE tana sarrafa kurakuran aiki lokacin da aka gano, ta saita tutar ERRF a cikin ICACHE_SR. Hakanan ana iya haifar da katsewa idan an saita bit ERRIE a cikin ICACHE_IER. Idan akwai rashin aiki na ICACHE, lokacin da yanayin cache ya ƙare, an saita tutar BSYENDF a cikin ICACHE_SR. Hakanan ana iya haifar da katsewa idan an saita bit BSYENDIE a cikin ICACHE_IER. Teburin da ke ƙasa yana lissafin katsewar ICACHE da tutocin taron.

Tebur 5. ICACHE katsewa da raguwar sarrafa taron

Yi rijista	Sunan Bit	Bit bayanin	Nau'in shiga Bit
ICACHE_SR	KASUWANCI	Cache yana aiwatar da cikakken aiki mara inganci	Karanta-kawai
	BSYENDF	An gama aikin lalata cache
	KUSKURE	An sami kuskure yayin aikin caching
ICACHE_IER	KUSKURE	Kunna katsewa don kuskuren cache	Karanta/rubuta
	BSYENDIE	Kunna katsewa idan an gama aikin ɓarna
ICACHE_FCR	CERRF	Yana share ERRF a cikin ICACHE_SR	Rubuta-kawai
	CBSYENDF	Yana share BSYENDF a cikin ICACHE_SR

DCACHE fasali
Manufar cache ɗin bayanan shine don adana lodin bayanan ƙwaƙwalwar ajiya na waje da ma'ajin bayanan da ke fitowa daga na'urar sarrafa bayanai ko kuma daga wani babban ɓangaren bas. DCACHE yana sarrafa karanta da rubuta ma'amaloli.
DCACHE cacheability zirga-zirga

DCACHE tana adana bayanan waje daga babban tashar tashar jiragen ruwa ta bas ɗin AHB. An ayyana buƙatun ƙwaƙwalwar ajiya mai shigowa azaman mai ɓoyewa bisa ga sifa ta kulle ƙwaƙwalwar ajiyar ma'amala ta AHB. An bayyana manufar rubuta DCACHE azaman rubuta-ta ko rubuta-baya dangane da sifa ta ƙwaƙwalwar ajiya da MPU ta daidaita. Lokacin da aka saita yanki azaman wanda ba'a iya adanawa, ana ƙetare DCACHE.

 Table 6. DCACHE cacheability ga AHB ma'amala

AHB duba sifa	AHB bufferable sifa	Cacheability
0	X	Karanta kuma rubuta: ba za a iya adanawa ba
1	0	Karanta: cacheable Rubuta: (wanda za a iya adanawa) rubuta ta hanyar
1	1	Karanta: cacheable Rubutu: (mai iya ɓoyewa) rubuta-baya

DCACHE yankuna masu ɓoyewa
Don jerin STM32U5, an haɗa haɗin haɗin bawa na DCACHE1 zuwa Cortex-M33 ta hanyar bas ɗin S-AHB kuma yana cache GFXMMU, FMC, da HSPI/OCTOSPI. An haɗa haɗin bawan DCACHE2 zuwa DMA2D ta hanyar bas ɗin tashar tashar M0, kuma yana adana duk abubuwan ƙwaƙwalwar ciki da na waje (sai SRAM4 da BRKPSRAM). Don jerin STM32H5, an haɗa haɗin haɗin bawa na DCACHE zuwa Cortex-M33 ta hanyar ƙwaƙwalwar waje ta S-AHB ta FMC da OCTOSPI.

Table 7. DCACHE yankuna da musaya masu cacheable

Yankin adireshin ƙwaƙwalwar ajiya mai cache	DCACHE1 cacheable musaya	DCACHE2 cacheable musaya
GFXMMU	X	X
SRAM1	N/A	X
SRAM2		X
SRAM3		X
SRAM5		X
SRAM6		X
HSPI1	X	X
OCTOSPI1	X	X
FMC Banks	X	X
OCTOSPI2	X	X

Lura

Wasu musaya ba su da tallafi a wasu samfuran. Koma zuwa Hoto 1 ko takamaiman jagorar bayanin samfur.
Nau'in fashewa
Daidai da ICACHE, DCACHE tana goyan bayan fashe da aka nannade (duba Sashe na 3.1.3). Don DCACHE, ana saita nau'in fashewa ta hanyar HBURST bit a cikin DCACHE_CR.
Tsarin DCACHE
Yayin taya, DCACHE an kashe shi ta tsohuwa yin buƙatun ƙwaƙwalwar ajiyar bawa kai tsaye zuwa babban tashar jiragen ruwa. Don kunna DCACHE, dole ne a saita EN bit a cikin rajistar DCACHE_CR. Masu lura da bugu-da-miss DCACHE tana aiwatar da na'urori guda huɗu don nazarin aikin cache:

• Biyu 32-bit (R/W) buga saka idanu: ƙidaya adadin lokutan da CPU ke karantawa ko rubuta bayanai a cikin ƙwaƙwalwar ajiyar cache ba tare da samar da ma'amala akan manyan tashoshin jiragen ruwa na DCACHE (bayanai da aka rigaya a cikin cache). (R/W) na'urorin saka idanu suna samuwa bi da bi a cikin rajistar DCACHE_RHMONR da DCACHE_WHMONR.
• Biyu 16-bit (R/W) miss monitoring: ƙidaya adadin lokutan da CPU karanta ko rubuta bayanai a cikin cache memory da kuma haifar da wani ma'amala a kan DCACHE master ports, domin loda bayanai daga memory yankin (debo bayanai ba. akwai a cikin cache). Ana samun lissafin masu saka idanu (R/W) bi da bi a cikin rajistar DCACHE_RMMONR da DCACHE_WMMONR.

Lura:

Waɗannan na'urori guda huɗu ba sa nannade lokacin da suka kai iyakar ƙimar su. Ana sarrafa waɗannan masu saka idanu daga ragi masu zuwa a cikin rajista na DCACHE_CR:

• WHITMAN bit (bi da bi WMISSMEN bit) don kunna / dakatar da buga rubutu (bi da bi ya ɓace) saka idanu
• RHITMEN bit (bi da bi RMISSMEN bit) don kunna / dakatar da bugun karatun (bi da bi) saka idanu
• WHITMRST bit (bi da bi WMISSMRST bit) don sake saita buga buga (bi da bi miss) duba
• RHITMRST bit (bi da bi RMISSMRST bit) don sake saita bugun karanta (bi da bi miss) duba

Ta hanyar tsoho, waɗannan na'urori suna kashe su don rage yawan wutar lantarki.

Kulawar DCACHE
DCACHE tana ba da ayyukan kulawa da yawa waɗanda za'a iya daidaita su ta hanyar CACHECMD[2:0] a cikin DCACHE_CR.

• 000: babu aiki (default)
• 001: tsaftataccen zango. Tsaftace takamaiman kewayon a cikin cache
• 010: iyaka mara inganci. ɓata takamaiman kewayon a cikin cache
• 010: Tsaftace kuma mara inganci. Tsaftace kuma ɓata takamaiman kewayon a cikin cache

An saita kewayon da aka zaɓa ta hanyar:

• CMDSTARTADDR rajista: umarnin farawa adireshin
• CMDENDADDR rajista: umarnin ƙare adireshin

Lura:

Dole ne a saita wannan rajista kafin a rubuta CACHECMD. Kula da umarnin cache yana farawa lokacin da aka saita STARTCMD bit a cikin rajista na DCACHE_CR. DCACHE kuma tana goyan bayan cikakken rashin inganci ta hanyar saita cacheINV bit a cikin rijistar DCACHE_CR.

DCACHE tsaro
DCACHE amintaccen yanki ne wanda za'a iya saita shi azaman amintacce ta hanyar amintaccen rijistar sanyi na GTZC TZSC. Lokacin da aka saita ta azaman amintacce, amintattun hanyoyin shiga kawai ana ba da izinin yin rijistar DCACHE. Hakanan za'a iya saita DCACHE azaman gata ta hanyar rajistar gata ta GTZC TZSC. Lokacin da aka saita DCACHE a matsayin mai gata, masu gata kawai ana ba da izinin shiga rajistar DCACHE. Ta hanyar tsoho, DCACHE ba ​​ta da tsaro kuma ba ta da gata ta GTZC TZSC.

Gudanar da taron da katsewa
DCACHE tana sarrafa kurakuran aiki lokacin da aka gano, ta saita tutar ERRF a cikin DCACHE_SR. Hakanan ana iya haifar da katsewa idan an saita bit ERRIE a cikin DCACHE_IER. Idan akwai rashin aiki na DCACHE, lokacin da aka gama aikin cache, an saita tutar BSYENDF a cikin DCACHE_SR. Hakanan ana iya haifar da katsewa idan an saita bit BSYENDIE a cikin DCACHE_IER. Ana iya bincika matsayin umarnin DCACHE ta CMDENF da BUSYCMDF ta DCACHE_SR Hakanan ana iya haifar da katsewa idan an saita bit CMDENDIE a DCACHE_IER. Teburin da ke ƙasa yana lissafin katsewar DCACHE da tutocin taron

Tebur 8. DCACHE Katsewa da abubuwan sarrafa abubuwan da suka faru

Yi rijista	Yi rijista	Bit bayanin	Nau'in shiga Bit
DCACHE_SR	KASUWANCI	Cache yana aiwatar da cikakken aiki mara inganci	Karanta-kawai
	BSYENDF	Cache cikakken aiki mara inganci ya ƙare
	BUSYCMDF	Cache yana aiwatar da umarnin kewayon
	CMENDF	Ƙarshen umarnin kewayon
	ERRF	An sami kuskure yayin aikin caching
DCACHE_IER	KUSKURE	Kunna katsewa don kuskuren cache	Karanta/rubuta
	CMDENDIE	Kunna katsewa a ƙarshen umarnin kewayon
	BSYENDIE	Kunna katsewa a kan cikakken ƙarshen aiki mara inganci
DCACHE_FCR	CERRF	Yana share ERRF a cikin DCACHE_SR	Rubuta-kawai
	CCMDENDF	Yana share CMENDF a cikin DCACHE_SR
	CBSYENDF	Yana share BSYENDF a cikin DCACHE_SR

Ayyukan ICACHE da DCACHE da amfani da wutar lantarki

Amfani da ICACHE da DCACHE suna haɓaka aikin aikace-aikacen lokacin samun damar ƙwaƙwalwar waje. Tebur mai zuwa yana nuna tasirin ICACHE da DCACHE akan aiwatar da CoreMark® lokacin samun damar ƙwaƙwalwar waje.

Tebur 9. Ayyukan ICACHE da DCACHE akan aiwatar da CoreMark tare da tunanin waje

(1)
CoreMark code	CoreMark Data	Tsarin ICACHE	Tsarin DCACHE	Makin CoreMark/Mhz
Ƙwaƙwalwar Flash na ciki	SRAM na ciki	An kunna (hanyoyi biyu)	An kashe	3.89
Ƙwaƙwalwar Flash na ciki	PSRAM Octo-SPI na Waje (S-bus)	An kunna (hanyoyi biyu)	An kunna	3.89
Ƙwaƙwalwar Flash na ciki	PSRAM Octo-SPI na Waje (S-bus)	An kunna (hanyoyi biyu)	An kashe	0.48
Filashin Octo-SPI na waje (C-bus)	SRAM na ciki	An kunna (hanyoyi biyu)	An kashe	3.86
Filashin Octo-SPI na waje (C-bus)	SRAM na ciki	An kashe	An kashe	0.24
Ƙwaƙwalwar Flash na ciki	SRAM na ciki	An kashe	An kashe	2.69

Yanayin Gwajin:

• Samfura masu dacewa: STM32U575/585
• Mitar tsarin: 160 MHz.
• Ƙwaƙwalwar PSRAM Octo-SPI na waje: 80 MHz (yanayin DTR).
• Ƙwaƙwalwar ƙwaƙwalwar ajiyar Octo-SPI na waje: 80 MHz (yanayin STR).
• Mai haɗawa: IAR V8.50.4.
• KYAUTA FLASH na ciki: ON.

Amfani da ICACHE da DCACHE yana rage yawan amfani da wutar lantarki yayin samun damar ƙwaƙwalwar ciki da waje. Tebur mai zuwa yana nuna tasirin ICACHE akan amfani da wutar lantarki yayin aiwatar da CoreMark.

Tebur 10. ICACHE aiwatar da CoreMark tasiri akan amfani da wutar lantarki

Tsarin ICACHE	Amfanin wutar lantarki na MCU (mA)
An kunna (hanyoyi biyu)	7.60
An kunna (hanyar 1)	7.13
An kashe	8.89

1. Yanayin Gwajin:
   • Samfura masu dacewa: STM32U575/585
   • Lambar CoreMark: ƙwaƙwalwar Flash na ciki.
   • CoreMark bayanai: na ciki SRAM.
   • Ƙwaƙwalwar ƙwaƙwalwar ajiya na ciki: KYAUTA: ON.
   • Mitar tsarin: 160 MHz.
   • Mai haɗawa: IAR V8.32.2.
   • Voltage tafe: 1.
   • SMPS: ON.
2. hanyar saita haɗin haɗin gwiwa yana aiki fiye da saitin haɗin gwiwa na hanya 1 don lambar da ba za a iya lodawa gabaɗaya a cikin cache ba. A halin yanzu, saitin haɗin haɗin-hany 1 kusan koyaushe yana da ƙarfi fiye da saitin haɗin haɗin-hanyoyi biyu. Dole ne a kimanta kowace lamba a cikin tsarin haɗin gwiwa biyu, don zaɓar mafi kyawun ciniki tsakanin aiki da amfani da wutar lantarki. Zaɓin ya dogara da fifikon mai amfani.

Kammalawa

Caches na farko da STMicroelectronics, ICACHE da DCACHE suka kirkira, suna da ikon adana abubuwan tunawa na ciki da na waje, suna ba da haɓaka aiki don zirga-zirgar bayanai da ɗebo umarni. Wannan daftarin aiki yana nuna nau'ikan fasali daban-daban waɗanda ICACHE da DCACHE ke goyan bayan, sauƙin daidaita su da sassauci suna ba da damar ƙarancin haɓakar farashi da sauri zuwa kasuwa.

Tarihin bita

Tebur 11. Tarihin bitar daftarin aiki

Kwanan wata	Sigar	Canje-canje
10-Oktoba-2019	1	Sakin farko.
27-Fabrairu-2020	2	An sabunta: • Tebur 2. Yankunan ƙwaƙwalwar ajiya da adiresoshin su • Sashe na 2.1.7 ICACHE kiyayewa • Sashe na 2.1.8 Tsaro na ICACHE
7-Dec-2021	3	An sabunta: • Taken takarda Gabatarwa • Sashe na 1 ICACHE da DCACHE sun ƙareview • Sashi na 4 Ƙarshe: • Sashe na 2 ICACHE da DCACHE fasali • Sashe na 3 ICACHE da DCACHE aiki da amfani da wutar lantarki
15-Fabrairu-2023	4	An sabunta: •         Sashi na 2.2: STM32U5 jerin tsarin gine-gine mai kaifin baki •         Sashi na 2.5: Tsarin toshe DCACHE •         Sashe na 3.1.1: Masters biyu •         Sashe na 3.1.2: Hanya 1 da ICACHE 2-way •         Sashe na 3.1.4: Yankunan da za a iya ɓoyewa da fasalin sake taswira •         Sashi na 3.2: Abubuwan DCACHE •         Sashi na 3.2.2: Yankunan da za a iya cache DCACHE •         Sashi na 4: Ayyukan ICACHE da DCACHE da amfani da wutar lantarki Ƙara: •         Sashi na 1: Gabaɗaya Bayani
11-Maris-2024	5	An sabunta: •         Sashi na 2.3: STM32H5 jerin zane mai kaifin baki •         Sashe na 3.1.1: Masters biyu

MUHIMMAN SANARWA – KU KARANTA A HANKALI
STMicroelectronics NV da rassan sa ("ST") sun tanadi haƙƙin yin canje-canje, gyare-gyare, haɓakawa, gyare-gyare, da haɓakawa ga samfuran ST da/ko ga wannan takaddar a kowane lokaci ba tare da sanarwa ba. Masu siye yakamata su sami sabbin bayanai masu dacewa akan samfuran ST kafin yin oda. Ana siyar da samfuran ST bisa ga sharuɗɗa da sharuɗɗan siyarwa na ST a wurin lokacin amincewa. Masu siye ke da alhakin zaɓi, zaɓi, da amfani da samfuran ST kuma ST ba ta ɗaukar alhakin taimakon aikace-aikacen ko ƙirar samfuran masu siye. Babu lasisi, bayyananne ko fayyace, ga kowane haƙƙin mallakar fasaha da ST ke bayarwa a nan. Sake siyar da samfuran ST tare da tanadi daban-daban da bayanan da aka gindaya a ciki zai ɓata kowane garantin da ST ya bayar don irin wannan samfurin. ST da tambarin ST alamun kasuwanci ne na ST. Don ƙarin bayani game da alamun kasuwanci na ST, koma zuwa www.st.com/trademarks. Duk sauran samfuran ko sunayen sabis mallakin masu su ne. Bayanin da ke cikin wannan takarda ya maye gurbin bayanan da aka kawo a baya a cikin kowane juzu'in wannan takaddar. © 2024 STMicroelectronics – Duk haƙƙin mallaka

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