F Tile Serial Lite IV Intel FPGA IP Jagorar Mai Amfani

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F Tile Serial Lite IV Intel FPGA IP

F-Tile Serial Lite IV Intel® FPGA IP Jagorar Mai Amfani
An sabunta don Intel® Quartus® Prime Design Suite: 22.1 Sigar IP: 5.0.0

Sigar Kan layi Aika Amsa

Saukewa: UG-20324

ID: 683074 Shafin: 2022.04.28

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Abubuwan da ke ciki
1. Game da F-Tile Serial Lite IV Intel® FPGA IP Jagorar Mai amfani………………………………………….. 4
2. F-Tile Serial Lite IV Intel FPGA IP Overview…………………………………………………………………. 6 2.1. Bayanin Sakin………………………………………………………………………………………………………………….7 2.2. Siffofin Tallafawa ………………………………………………………………………………………………………….. 7 2.3. Matsayin Tallafin Sigar IP………………………………………………………………………………………………………….8 2.4. Taimakon Matsayin Gudun Na'ura……………………………………………………………………………………………………………………….8 2.5. Amfani da Albarkatu da Latency………………………………………………………………………………………………… 9 2.6. Ingantacciyar hanyar Bandwidth………………………………………………………………………………………………………………………. 9
3. Farawa………………………………………………………………………………………………………………………………………. 11 3.1. Shigarwa da lasisi Intel FPGA IP Cores……………………………………………………………………… Yanayin Ƙimar IP na Intel FPGA………………………………………………………………………. 11 3.1.1. Ƙayyadaddun Ma'auni da Zaɓuɓɓuka na IP……………………………………………………………………………………………………………… 11 3.2. An ƙirƙira File Tsarin……………………………………………………………………………………………………………………………………… Simulating Intel FPGA IP Cores………………………………………………………………………………………………… Kwaikwayi da Tabbatar da Ƙirar………………………………………………………………. 14 3.4. Haɗa Ƙa'idodin IP a cikin Wasu Kayan aikin EDA……………………………………………………………………………… 16 3.4.1. Haɗa Cikakken Zane……………………………………………………………………………………………………….17
4. Bayanin Aiki………………………………………………………………………………………………………………….. 19 4.1. Tafarkin Bayanan TX……………………………………………………………………………………………………………….20 4.1.1. TX MAC Adafta……………………………………………………………………………………………………….. 21 4.1.2. Shigar Kalma Mai Sarrafa (CW)……………………………………………………………………………………………… 23 4.1.3. TX CRC……………………………………………………………………………………………………………………………………………………………… TX MII Encoder……………………………………………………………………………………………………….28 4.1.4. TX PCS da PMA……………………………………………………………………………………………………………….. 29 4.1.5. Hanyar Bayanan RX……………………………………………………………………………………………………………… 30 4.2. RX PCS da PMA……………………………………………………………………………………………………………….. 30 4.2.1. Mai Rarraba RX MII……………………………………………………………………………………………………………………………… 31 4.2.2. RX CRC………………………………………………………………………………………………………………………….. 31 4.2.3. RX Deskew……………………………………………………………………………………………………………………………………….31 4.2.4. Cire RX CW………………………………………………………………………………………………………………………………………… F-Tile Serial Lite IV Intel FPGA IP Architecture Architecture………………………………………………………. 32 4.2.5. Sake saiti da Ƙaddamarwar haɗin kai………………………………………………………………………………………………………..35 4.3. Sake saitin TX da Tsarin Farkowa………………………………………………………………………. 36 4.4. Sake saitin RX da Tsarin Farkowa……………………………………………………………… 37 4.4.1. Ƙididdigar Haɗin Haɗi da Ƙididdiga Ingantaccen Bandwidth……………………………………………………………………….. 38
5. Ma'auni………………………………………………………………………………………………………………………………………… 42
6. F-Tile Serial Lite IV Intel FPGA IP Siginonin Mu'amalar Fayil………………………………………………………………….. 44 6.1. Alamomin Agogo……………………………………………………………………………………………………………………………………………………… Sake saitin sigina………………………………………………………………………………………………………………………………………………………………… Alamar MAC………………………………………………………………………………………………………………………………………….. 44 6.2. Siginonin Sake saita Mai Canjawa……………………………………………………………………………………… 44 6.3. Sigina na PMA .................................................................... .. 45

F-Tile Serial Lite IV Intel® FPGA IP Jagorar Mai Amfani 2

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7. Zanewa tare da F-Tile Serial Lite IV Intel FPGA IP……………………………………………………………………………………… Sake saitin Jagororin……………………………………………………………………………………………………….. 51 7.1. Jagororin Gudanar da Kuskure………………………………………………………………………………………………………..51
8. F-Tile Serial Lite IV Rukunin Rubutun Jagorar Mai Amfani na Intel FPGA…………………………………………………. 52 9. Tarihin Bita na Takardu don F-Tile Serial Lite IV Jagorar Mai Amfani ta IP FPGA………53

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F-Tile Serial Lite IV Intel® FPGA IP Jagorar Mai Amfani 3

683074 | 2022.04.28 Aika Ra'ayoyin

1. Game da F-Tile Serial Lite IV Intel® FPGA IP Jagorar mai amfani

Wannan daftarin aiki yana bayyana fasalulluka na IP, bayanin gine-gine, matakai don samarwa, da jagororin ƙirƙira F-Tile Serial Lite IV Intel® FPGA IP ta amfani da transceivers F-tile a cikin na'urorin Intel AgilexTM.

Masu Sauraron Niyya

An yi nufin wannan takaddar don masu amfani masu zuwa:
· Zane masu gine-gine don yin zaɓin IP a lokacin tsarin tsara tsarin tsarin tsarin
· Masu zanen kayan masarufi lokacin haɗa IP ɗin cikin ƙirar tsarin su
· Injiniyoyi masu tabbatarwa yayin ƙirar matakin-tsari da matakan tabbatar da kayan aiki

Takardu masu alaƙa

Tebur mai zuwa yana lissafin wasu takaddun tunani waɗanda ke da alaƙa da F-Tile Serial Lite IV Intel FPGA IP.

Tebur 1.

Takardu masu alaƙa

Magana

F-Tile Serial Lite IV Intel FPGA IP Design ExampJagorar Mai Amfani

Bayanan Bayani na Na'urar Intel Agilex

Bayani
Wannan takaddar tana ba da tsararraki, jagororin amfani, da bayanin aiki na F-Tile Serial Lite IV Intel FPGA IP ƙirar ex.ampa cikin na'urorin Intel Agilex.
Wannan takaddun yana bayyana halayen lantarki, halayen canzawa, ƙayyadaddun ƙayyadaddun tsari, da lokacin na'urorin Intel Agilex.

Tebur 2.
CW RS-FEC PMA TX RX PAM4 NRZ

Acronyms da Ƙwaƙwalwar Ƙwaƙwalwar Lissafi
Acronym

Fadada Sarrafa Kalma Reed-Solomon Kuskuren Gabatarwa Gyara Matsakaicin Maƙalacin Jiki Mai Watsawa Pulse-AmpLitude Modulation 4-Level Rashin komawa-zuwa-sifili

ci gaba…

Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka. *Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.

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1. Game da F-Tile Serial Lite IV Intel® FPGA IP Jagorar Mai amfani 683074 | 2022.04.28

PCS MII XGMII

Acronym

Fadada Ƙofar Jiki Sublayer Media Interface Interface 10 Gigabit Media Independent Interface

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F-Tile Serial Lite IV Intel® FPGA IP Jagorar Mai Amfani 5

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2. F-Tile Serial Lite IV Intel FPGA IP Overview

Hoto na 1.

F-Tile Serial Lite IV Intel FPGA IP ya dace da babban sadarwar bayanan bandwidth don guntu-zuwa-guntu, allo-to-board, da aikace-aikacen jirgin baya.

F-Tile Serial Lite IV Intel FPGA IP ya haɗa da ikon samun damar watsa labarai (MAC), sublayer codeing (PCS), da abubuwan haɗin kafofin watsa labarai na zahiri (PMA). IP ɗin yana goyan bayan saurin canja wurin bayanai har zuwa 56 Gbps akan kowane layi tare da iyakar hanyoyin PAM4 guda huɗu ko 28 Gbps akan kowane layi tare da iyakar 16 NRZ. Wannan IP yana ba da babban bandwidth, ƙananan firam ɗin sama, ƙananan I/O ƙidaya, kuma yana goyan bayan babban scalability a cikin lambobi biyu da sauri. Hakanan ana iya sake daidaita wannan IP ɗin cikin sauƙi tare da goyan bayan ƙimar ƙimar bayanai da yawa tare da yanayin PCS na Ethernet na transceiver F-tile.

Wannan IP tana goyan bayan hanyoyin watsawa guda biyu:
Yanayi na asali-Wannan yanayin yawo ne mai tsafta inda ake aika bayanai ba tare da fara fakiti ba, zagayowar fanko, da ƙarshen fakiti don ƙara yawan bandwidth. IP ɗin yana ɗaukar ingantaccen bayanai na farko azaman farkon fashe.
Cikakken yanayin – Wannan yanayin canja wurin fakiti ne. A cikin wannan yanayin, IP ɗin yana aika fashewa da sake zagayowar daidaitawa a farkon da ƙarshen fakiti azaman masu iyakancewa.

F-Tile Serial Lite IV Babban Matsayin Toshe Hoto

Avalon Streaming Interface TX

F-Tile Serial Lite IV Intel FPGA IP
MAC TX
TX USRIF_CTRL

64 * n raƙuman hanyoyi (yanayin NRZ) / 2 * n raƙuman hanyoyi (yanayin PAM4)

TX MAC

Adafta INSERT

MII ENCODE

PCS na al'ada

Farashin TX PCS

TX MII

EMIB ENCODE SCRAMBLER FEC

Farashin PMA

n Lanes Bits (yanayin PAM4)/ n Lanes Bits (yanayin NRZ)
TX Serial Interface

Avalon Streaming Interface RX
64 * n raƙuman hanyoyi (yanayin NRZ) / 2 * n raƙuman hanyoyi (yanayin PAM4)

RX PCS

Farashin RMV

DESKEW

MII

& DECODE CODE

RX MII

EMIB

DECODE BLOCK SYNC & FEC DESCRAMBLER

RX PMA

CSR

2n Lanes Bits (yanayin PAM4)/ n Lanes Bits (yanayin NRZ) RX Serial Interface
Avalon ƙwaƙwalwar ajiya

Labari

Hankali mai laushi

Hard dabaru

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2. F-Tile Serial Lite IV Intel FPGA IP Overview 683074 | 2022.04.28

Kuna iya samar da F-Tile Serial Lite IV Intel FPGA IP ƙirar misaliampdon ƙarin koyo game da fasalulluka na IP. Koma zuwa F-Tile Serial Lite IV Intel FPGA IP Design ExampJagorar Mai Amfani.
Bayani mai alaƙa · Bayanin Aiki a shafi na 19 · F-Tile Serial Lite IV Intel FPGA IP Design ExampJagorar Mai Amfani

2.1. Bayanin Saki

Siffofin IP na Intel FPGA sun dace da nau'ikan software na Intel Quartus® Prime Design Suite har zuwa v19.1. An fara a cikin sigar software ta Intel Quartus Prime Design Suite 19.2, Intel FPGA IP yana da sabon tsarin siga.

Lambar Intel FPGA IP (XYZ) na iya canzawa tare da kowace sigar software ta Intel Quartus Prime. Canji a:

X yana nuna babban bita na IP. Idan kun sabunta Intel Quartus Prime software, dole ne ku sake haɓaka IP ɗin.
Y yana nuna IP ɗin ya ƙunshi sabbin abubuwa. Sake haɓaka IP ɗin ku don haɗa waɗannan sabbin fasalolin.
Z yana nuna IP ɗin ya ƙunshi ƙananan canje-canje. Sake haɓaka IP ɗin ku don haɗa waɗannan canje-canje.

Tebur 3.

F-Tile Serial Lite IV Intel FPGA IP Bayanin Sakin

Abun IP Sigar Intel Quartus Prime Sigar Sakin Kwanan Wata lambar oda

5.0.0 22.1 2022.04.28 IP-SLITE4F

Bayani

2.2. Abubuwan Goyon baya
Tebur mai zuwa yana lissafin fasalulluka da ake samu a cikin F-Tile Serial Lite IV Intel FPGA IP:

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2. F-Tile Serial Lite IV Intel FPGA IP Overview 683074 | 2022.04.28

Tebur 4.

F-Tile Serial Lite IV Intel FPGA IP Features

Siffar

Bayani

Canja wurin bayanai

Domin yanayin PAM4:
- FHT yana goyan bayan 56.1, 58, da 116 Gbps akan kowane layi tare da matsakaicin layin 4.
- FGT yana goyan bayan har zuwa 58 Gbps akan kowane layi tare da matsakaicin layin 12.
Koma zuwa Tebur 18 a shafi na 42 don ƙarin cikakkun bayanai kan goyan bayan ƙimar bayanan transceiver don yanayin PAM4.
Domin yanayin NRZ:
- FHT yana goyan bayan 28.05 da 58 Gbps akan kowane layi tare da matsakaicin layin 4.
- FGT yana tallafawa har zuwa 28.05 Gbps akan kowane layi tare da iyakar 16.
Koma zuwa Tebur 18 a shafi na 42 don ƙarin cikakkun bayanai kan goyan bayan ƙimar bayanan transceiver don yanayin NRZ.
· Yana goyan bayan ci gaba da yawo (Basic) ko fakiti (Cikakken).
Yana goyan bayan fakitin firam ɗin ƙananan sama.
Yana goyan bayan canja wurin granularity byte don kowane girman fashe.
· Yana goyan bayan daidaita layin mai amfani ko ta atomatik.
· Yana goyan bayan lokacin daidaita tsarin.

PCS

Yana amfani da dabaru na IP mai ƙarfi wanda ke mu'amala da Intel Agilex F-tile transceivers don raguwar albarkatu mai laushi.
Yana goyan bayan yanayin daidaitawa PAM4 don ƙayyadaddun 100GBASE-KP4. Ana kunna RS-FEC koyaushe a cikin wannan yanayin daidaitawa.
Yana goyan bayan NRZ tare da zaɓi na RS-FEC na zaɓi.
Yana goyan bayan 64b/66b yin rikodin rikodi.

Gano Kuskure da Gudanarwa

Yana goyan bayan bincika kuskuren CRC akan hanyoyin bayanan TX da RX. Yana goyan bayan binciken kuskuren hanyar haɗin RX. Yana goyan bayan gano kuskuren RX PCS.

Hanyoyin sadarwa

· Yana goyan bayan canja wurin fakiti na duplex kawai tare da hanyoyin haɗin kai.
Yana amfani da haɗin kai-zuwa-aya zuwa na'urorin FPGA da yawa tare da ƙarancin jinkirin canja wuri.
Yana goyan bayan ƙayyadaddun umarni mai amfani.

2.3. Matsayin Tallafin Sigar IP

Intel Quartus Prime software da tallafin na'urar Intel FPGA don F-Tile Serial Lite IV Intel FPGA IP shine kamar haka:

Tebur 5.

Sigar IP da Matsayin Tallafi

Intel Quartus Prime 22.1

Na'urar Intel Agilex F-tile transceivers

Tsarin Kayan Aikin Kwaikwaiyo na IP

5.0.0

2.4. Taimakon Girman Na'ura
F-Tile Serial Lite IV Intel FPGA IP yana goyan bayan maki masu zuwa na sauri don na'urorin Intel Agilex F-tile: · Matsayin saurin transceiver: -1, -2, da -3 · Core gudun grade: -1, -2, da - 3

F-Tile Serial Lite IV Intel® FPGA IP Jagorar Mai Amfani 8

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2. F-Tile Serial Lite IV Intel FPGA IP Overview 683074 | 2022.04.28

Bayanai masu alaƙa
Bayanan Bayani na Na'urar Intel Agilex Ƙarin bayani game da goyan bayan ƙimar bayanai a cikin Intel Agilex F-tile transceivers.

2.5. Amfani da Albarkatu da Latency

An samo albarkatu da latency na F-Tile Serial Lite IV Intel FPGA IP daga sigar software ta Intel Quartus Prime Pro Edition 22.1.

Tebur 6.

Intel Agilex F-Tile Serial Lite IV Intel FPGA IP Amfani da Albarkatun albarkatun
Ma'aunin latency ya dogara ne akan jinkirin tafiya zagaye daga ainihin shigarwar TX zuwa ainihin fitowar RX.

Nau'in Transceiver

Bambance-bambance

Adadin Yanayin Hanyoyin Bayanai RS-FEC ALM

Latency (TX core clockcycle)

FGT

28.05 Gbps NRZ 16

Naƙasasshe na asali 21,691 65

Cikakken Naƙasasshe 22,135 65

An kunna Asalin 21,915 189

Cikakken An kunna 22,452 189

58 Gbps PAM4 12

An kunna Asalin 28,206 146

Cikakken An kunna 30,360 146

FHT

58 Gbps NRZ

An kunna Asalin 15,793 146

Cikakken An kunna 16,624 146

58 Gbps PAM4 4

An kunna Asalin 15,771 154

Cikakken An kunna 16,611 154

116 Gbps PAM4 4

An kunna Asalin 21,605 128

Cikakken An kunna 23,148 128

2.6. Ingantaccen Bandwidth

Tebur 7.

Ingantaccen Bandwidth

Yanayin Canja-canje

Saukewa: PAM4

Yanayin yawo RS-FEC

Cikakken An Kunna

An kunna Basic

Matsakaicin matsakaicin matsakaici a Gbps (RAW_RATE)
Fashe girman canja wuri a adadin kalma (BURST_SIZE) (1)
Lokacin daidaitawa a cikin zagayen agogo (SRL4_ALIGN_PERIOD)

56.0 2,048 4,096

56.0 4,194,304 4,096

Saituna

NRZ

Cikakkun

An kashe

An kunna

28.0

2,048

4,096

Naƙasasshe na asali 28.0

An kunna 28.0

4,194,304

4,096

4,096 sun ci gaba…

(1) Yanayin BURST_SIZE na Basic Yanayin yana kusanci marar iyaka, don haka ana amfani da adadi mai yawa.

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F-Tile Serial Lite IV Intel® FPGA IP Jagorar Mai Amfani 9

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Masu canji

Saituna

64/66b code

0.96969697 0.96969697 0.96969697 0.96969697 0.96969697 0.96969697

Sama da girman fashe a adadin kalma (BURST_SIZE_OVHD)

2 (2)

0 (3)

2 (2)

0 (3)

Lokacin alamar daidaitawa 81,915 a cikin zagayowar agogo (ALIGN_MARKER_PERIOD)

81,915

81,916

Faɗin alamar daidaitawa a cikin 5

zagayowar agogo

(ALIGN_MARKER_WIDTH)

Ingantaccen bandwidth (4)

0.96821788 0.96916433 0.96827698 0.96822967 0.96922348 0.96917616

Matsakaicin inganci (Gbps) (5)

54.2202012 54.27320236 27.11175544 27.11043076 27.13825744 27.13693248

Matsakaicin mitar agogo mai amfani (MHz) (6)

423.59532225 424.00939437 423.62117875 423.6004806 424.0352725 424.01457

Ƙididdigar Haɗin Bayanan Bayani mai alaƙa da Ƙididdiga Ingantaccen Bandwidth a shafi na 40

(2) A cikin cikakken yanayin, girman BURST_SIZE_OVHD ya haɗa da START/END masu haɗa Kalmomin Sarrafa a cikin rafin bayanai.
(3) Don Yanayin asali, BURST_SIZE_OVHD shine 0 saboda babu START/END yayin yawo.
(4) Koma zuwa Ƙididdigar Ƙimar Haɗin Haɗi da Ƙididdiga Nagartaccen Ƙirar don ƙididdige ingancin bandwidth.
(5) Koma zuwa Ƙimar Haɗi da Ƙididdiga Ingantaccen Bandwidth don ingantaccen lissafin ƙimar.
(6) Koma zuwa Ƙididdigar Ƙimar Haɗin Haɗi da Ƙirar Ƙididdiga don iyakar lissafin mitar agogo mai amfani.

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3. Farawa

3.1. Shigarwa da lasisi Intel FPGA IP Cores

Shigar da software na Intel Quartus Prime ya haɗa da ɗakin karatu na Intel FPGA IP. Wannan ɗakin karatu yana ba da yawancin abubuwan amfani na IP don amfanin samarwa ku ba tare da buƙatar ƙarin lasisi ba. Wasu Intel FPGA IP cores suna buƙatar siyan lasisi daban don amfanin samarwa. Yanayin Ƙimar IP na Intel FPGA yana ba ku damar kimanta waɗannan lasisin Intel FPGA IP cores a cikin kwaikwaiyo da kayan aiki, kafin yanke shawarar siyan cikakken lasisin tushen IP na samarwa. Kuna buƙatar siyan cikakken lasisin samarwa don masu lasisi na Intel IP bayan kun kammala gwajin kayan aiki kuma kuna shirye don amfani da IP a samarwa.

Software na Intel Quartus Prime yana shigar da kayan aikin IP a cikin wurare masu zuwa ta tsohuwa:

Hoto na 2.

Hanyar Shigar da Core IP
intelFPGA(_pro) ma'adini - Ya ƙunshi Intel Quartus Prime software ip - Ya ƙunshi ɗakin karatu na Intel FPGA IP da altera na IP na ɓangare na uku - Ya ƙunshi lambar tushen ɗakin karatu na Intel FPGA IP. - Ya ƙunshi tushen Intel FPGA IP files

Tebur 8.

Wuraren Shigar Core IP

Wuri

Software

:intelFPGA_proquartusipaltera

Intel Quartus Prime Pro Edition

:/intelFPGA_pro/quartus/ip/altera Intel Quartus Prime Pro Edition

Windows Platform* Linux*

Lura:

Intel Quartus Prime software baya goyan bayan sarari a hanyar shigarwa.

3.1.1. Yanayin FPGA IP na Intel
Yanayin Ƙimar IP na Intel FPGA na kyauta yana ba ku damar kimanta ƙirar Intel FPGA IP masu lasisi a cikin siminti da hardware kafin siye. Yanayin Ƙimar IP na Intel FPGA yana goyan bayan kimantawa masu zuwa ba tare da ƙarin lasisi ba:
Yi kwaikwayi halayen Intel FPGA IP core mai lasisi a cikin tsarin ku. · Tabbatar da ayyuka, girma, da saurin tushen IP cikin sauri da sauƙi. · Ƙirƙirar shirye-shiryen na'ura mai iyakance lokaci files don ƙira waɗanda suka haɗa da muryoyin IP. · Shirya na'ura tare da ainihin IP ɗin ku kuma tabbatar da ƙirar ku a cikin kayan masarufi.

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3. Farawa
683074 | 2022.04.28
Yanayin Ƙimar IP na Intel FPGA yana goyan bayan hanyoyin aiki masu zuwa:
Haɗe-Yana ba da damar gudanar da ƙira mai ɗauke da lasisin Intel FPGA IP har abada tare da haɗin kai tsakanin allon ku da kwamfutar mai masaukin baki. Yanayin da aka haɗa yana buƙatar ƙungiyar aikin gwajin haɗin gwiwa (JTAG) na USB da aka haɗa tsakanin JTAG tashar jiragen ruwa a kan allonku da kwamfutar mai masaukin baki, wacce ke tafiyar da Intel Quartus Prime Programmer na tsawon lokacin tantance kayan aikin. Mai shirye-shiryen kawai yana buƙatar ƙaramar shigarwa na Intel Quartus Prime software, kuma baya buƙatar lasisin Intel Quartus Prime. Kwamfutar mai masauki tana sarrafa lokacin kimantawa ta hanyar aika sigina na lokaci-lokaci zuwa na'urar ta JTAG tashar jiragen ruwa. Idan duk maƙallan IP masu lasisi a cikin ƙirar ƙira suna goyan bayan yanayin haɗaɗɗiya, lokacin kimantawa yana gudana har sai kowane ƙimar ƙimar IP ta ƙare. Idan duk na'urorin IP suna goyan bayan lokacin kimantawa mara iyaka, na'urar ba ta ƙarewa.
Ba a haɗa ba – Yana ba da damar gudanar da ƙira mai ɗauke da IP mai lasisi na ƙayyadadden lokaci. Cibiyoyin IP na komawa zuwa yanayin da ba a haɗa su ba idan na'urar ta katse daga kwamfutar da ke aiki da Intel Quartus Prime software. Har ila yau, tushen IP ɗin yana komawa zuwa yanayin da ba a haɗa shi ba idan duk wani tushen IP mai lasisi a cikin ƙira baya goyan bayan yanayin haɗaɗɗiyar.
Lokacin da lokacin kimantawa ya ƙare ga kowane Intel FPGA IP mai lasisi a cikin ƙira, ƙirar ta daina aiki. Duk abubuwan da ke amfani da Intel FPGA IP Evaluation Mode suna ƙare lokaci guda lokacin da kowane tushen IP a cikin lokutan ƙira ya ƙare. Lokacin da lokacin kimantawa ya ƙare, dole ne ku sake tsara na'urar FPGA kafin ci gaba da tabbatar da kayan aikin. Don tsawaita amfani da tushen IP don samarwa, saya cikakken lasisin samarwa don ainihin IP.
Dole ne ku sayi lasisin kuma ku samar da cikakken maɓallin lasisin samarwa kafin ku iya samar da shirye-shiryen na'urar mara iyaka file. Yayin Yanayin Ƙimar IP na Intel FPGA, Mai tarawa kawai yana haifar da ƙayyadaddun na'ura shirye-shirye. file ( _time_limited.sof) wanda zai ƙare a iyakar lokacin.

F-Tile Serial Lite IV Intel® FPGA IP Jagorar Mai Amfani 12

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Hoto na 3.

Yanayin Ƙimar IP na Intel FPGA
Shigar da Intel Quartus Prime Software tare da Intel FPGA IP Library

Daidaita da Ƙaddamar da lasisin Intel FPGA IP Core

Tabbatar da IP a cikin Na'urar kwaikwayo mai Tallafawa

Haɗa Zane a cikin Intel Quartus Prime Software

Ƙirƙirar Shirye-shiryen Na'ura Mai Iyakancin Lokaci File

Shirya na'urar Intel FPGA kuma Tabbatar da Aiki akan Hukumar
Babu Shirye IP don Amfani da Samfura?
Ee Siyan Cikakkun Samfura
Lasisin IP

Lura:

Haɗa IP mai lasisi a cikin Samfuran Kasuwanci
Koma zuwa kowane jagorar mai amfani na ainihin IP don matakan daidaitawa da cikakkun bayanan aiwatarwa.
Intel yana ba da lasisin muryoyin IP akan kowane wurin zama, madawwamin tushe. Kudin lasisi ya haɗa da kulawa da goyan bayan shekara ta farko. Dole ne ku sabunta kwangilar kulawa don karɓar sabuntawa, gyaran kwari, da goyan bayan fasaha fiye da shekara ta farko. Dole ne ku sayi cikakken lasisin samarwa don Intel FPGA IP cores waɗanda ke buƙatar lasisin samarwa, kafin ƙirƙirar shirye-shirye files cewa za ku iya amfani da shi na wani lokaci mara iyaka. Yayin Yanayin Ƙimar IP na Intel FPGA, Mai tarawa kawai yana haifar da ƙayyadaddun na'ura shirye-shirye. file ( _time_limited.sof) wanda zai ƙare a iyakar lokacin. Don samun maɓallan lasisin samarwa, ziyarci Cibiyar Bayar da Sabis na Sabis na Intel FPGA.
Yarjejeniyar Lasisin Software na Intel FPGA suna sarrafa shigarwa da amfani da maƙallan IP masu lasisi, Intel Quartus Prime ƙirar ƙirar ƙira, da duk na'urorin IP marasa lasisi.

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Bayani mai alaƙa · Cibiyar Tallafawa Lasisin Intel FPGA · Gabatarwa zuwa Shigarwa da Lasisi na Software na Intel FPGA
3.2. Ƙayyadaddun Matsalolin IP da Zaɓuɓɓuka
Editan sigar IP yana ba ku damar daidaita bambancin IP na al'ada da sauri. Yi amfani da matakai masu zuwa don tantance zaɓuɓɓukan IP da sigogi a cikin software na Intel Quartus Prime Pro Edition.
1. Idan baku riga kuna da aikin Intel Quartus Prime Pro Edition wanda a cikinsa zaku haɗa F-Tile Serial Lite IV Intel FPGA IP, dole ne ku ƙirƙiri ɗaya. a. A cikin Intel Quartus Prime Pro Edition, danna File Sabon Project Wizard don ƙirƙirar sabon aikin Quartus Prime, ko File Buɗe Project don buɗe aikin Quartus Prime da ke akwai. Mayen yana tambayarka don saka na'ura. b. Ƙayyade dangin Intel Agilex na na'urar kuma zaɓi na'urar F-tile mai samarwa wacce ta dace da buƙatun maki na sauri don IP. c. Danna Gama.
2. A cikin IP Catalog, gano wuri kuma zaɓi F-Tile Serial Lite IV Intel FPGA IP. Sabuwar taga Bambancin IP yana bayyana.
3. Ƙayyade sunan babban mataki don sabon bambancin IP na al'ada. Editan siga yana adana saitunan bambancin IP a cikin a file mai suna .ip.
4. Danna Ok. Editan siga ya bayyana. 5. Ƙayyade sigogi don bambancin IP ɗin ku. Koma zuwa sashin Parameter don
bayani game da F-Tile Serial Lite IV Intel FPGA IP sigogi. 6. Zabi, don samar da simulation testbench ko haɗawa da ƙirar kayan aiki
example, bi umarnin da ke cikin Zane ExampJagorar Mai Amfani. 7. Danna Ƙirƙirar HDL. Akwatin maganganu na Generation ya bayyana. 8. Ƙayyade fitarwa file zažužžukan tsara, sa'an nan kuma danna Generate. Bambancin IP
files samar bisa ga ƙayyadaddun ku. 9. Danna Gama. Editan siga yana ƙara babban matakin .ip file zuwa halin yanzu
aikin ta atomatik. Idan an sa ka ƙara da .ip file zuwa aikin, danna Project Ƙara / Cire Files a cikin Project don ƙara da file. 10. Bayan ƙirƙira da ƙaddamar da bambancin IP ɗin ku, yi ayyukan fil ɗin da suka dace don haɗa tashoshin jiragen ruwa kuma saita kowane daidaitattun sigogin RTL na kowane lokaci.
Ma'auni na Bayani mai alaƙa a shafi na 42
3.3. An ƙirƙira File Tsarin
Software na Intel Quartus Prime Pro Edition yana haifar da fitowar IP mai zuwa file tsari.
Don bayani game da file tsarin zane example, koma zuwa F-Tile Serial Lite IV Intel FPGA IP Design ExampJagorar Mai Amfani.

F-Tile Serial Lite IV Intel® FPGA IP Jagorar Mai Amfani 14

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Hoto 4. F-Tile Serial Lite IV Intel FPGA IP An Samar da shi Files
.ip – IP hadewa file

Bambancin IP files

_ Bambancin IP files

example_design

.cmp – VHDL bangaren sanarwar file _bb.v – Verilog HDL akwatin baki EDA kira file _inst.v da .vhd – Sampda instantiation shaci .xml- Rahoton XML file

Example wurin don ƙirar IP core example files. Wurin tsoho shine example_design, amma an sa ka saka wata hanya ta daban.

.qgsimc – Ya lissafa sigogin siminti don tallafawa haɓaka haɓakawa .qgsynthc - Ya lissafa sigogin haɗin kai don tallafawa haɓaka haɓakawa

.qip – Jerin haɗin IP files

_generation.rpt- Rahoton ƙarni na IP

.sopcinfo- Haɗin kayan aikin-sarkar software file html- Haɗi da bayanan taswirar ƙwaƙwalwar ajiya

.csv – Pin aiki file

.spd - Haɗa rubutun kwaikwaiyo ɗaya

simulation files

synth IP kira files

.v Babban kwaikwaiyo file

.v Babban matakin IP kira file

Rubutun na'urar kwaikwayo

Subcore dakunan karatu

synth
Subcore kira files

sim
Subcore Simulation files

Tebur 9.

F-Tile Serial Lite IV Intel FPGA IP An Samar da shi Files

File Suna

Bayani

.ip

Tsarin Platform Designer ko babban matakin IP bambancin file. shine sunan da kuke ba da bambancin IP naku.

.cmp

Sanarwar Bangaren VHDL (.cmp) file rubutu ne file wanda ya ƙunshi jigon gida da ma'anar tashar jiragen ruwa waɗanda zaku iya amfani da su a ƙirar VHDL files.

.html

Rahoton da ya ƙunshi bayanan haɗin kai, taswirar ƙwaƙwalwar ajiya da ke nuna adireshin kowane bawa dangane da kowane ubangidan da aka haɗa shi da shi, da ayyukan sigina.

_tsara.rpt

.qgsimc

Yana lissafin sigogin kwaikwaiyo don tallafawa haɓaka haɓakawa.

.qgsynthc

Ya lissafa sigogin haɗin kai don tallafawa haɓaka haɓakawa.

.qip

Ya ƙunshi duk bayanan da ake buƙata game da bangaren IP don haɗawa da haɗa bangaren IP a cikin software na Intel Quartus Prime.
ci gaba…

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File Suna .sopcinfo
.csv .spd _bb.v _inst.v ko _inst.vhd .regmap
.svd
.v ko .vhd mentor/ synopsys/vcs/ synopsys/vcsmx/ xcelium/ submodules/ /

Bayani
Yana bayyana haɗin kai da ma'auni na abubuwan IP a cikin tsarin Mai tsara Platform ɗin ku. Kuna iya rarraba abubuwan da ke cikin sa don samun buƙatu lokacin da kuke haɓaka direbobin software don abubuwan IP. Kayan aikin ƙasa kamar sarkar kayan aikin Nios® II suna amfani da wannan file. The .sopcinfo file da tsarin.h file An ƙirƙira don sarkar kayan aiki na Nios II sun haɗa da bayanan taswirar adireshi ga kowane bawa dangi ga kowane maigidan da ya isa ga bawa. Masters daban-daban na iya samun taswirar adireshin daban don samun damar wani ɓangaren bawa.
Ya ƙunshi bayani game da haɓakawa na bangaren IP.
Shigar da ake buƙata file don ip-make-simscript don samar da rubutun kwaikwayo don na'urorin kwaikwayo masu goyan baya. Da .spd file ya ƙunshi jerin fileAn ƙirƙira don kwaikwayo, tare da bayanai game da abubuwan da za ku iya farawa.
Kuna iya amfani da akwatin Verilog black-box (_bb.v) file a matsayin shela mara komai don amfani azaman akwatin baki.
HDL misaliampda instantiation samfuri. Kuna iya kwafa da liƙa abubuwan da ke cikin wannan file cikin HDL ku file don aiwatar da bambance-bambancen IP.
Idan IP ya ƙunshi bayanin rajista, .regmap file haifar da. The .regmap file ya bayyana bayanin taswirar rijistar mahaɗan master da bawa. Wannan file ya cika .sopcinfo file ta hanyar samar da ƙarin cikakkun bayanan rajista game da tsarin. Wannan yana ba da damar nunin rijista views da ƙididdiga masu iya daidaita masu amfani a cikin Tsarin Console.
Yana ba da damar tsarin sarrafa kayan aiki mai ƙarfi (HPS) kayan aikin gyara kuskuren tsarin zuwa view taswirorin rijistar abubuwan da ke da alaƙa da HPS a cikin tsarin Tsarin Platform. A lokacin hadawa, .svd files don mu'amalar bayi da ake iya gani ga masanan System Console ana adana su a cikin .sof file a cikin sashin gyara kuskure. System Console yana karanta wannan sashe, wanda Mai tsara Platform zai iya tambaya don yin rijistar bayanan taswira. Don tsarin bayi, Platform Designer na iya samun damar yin rajista da suna.
HDL files wanda ke hanzarta kowane ƙaramin abu ko IP na yaro don haɗawa ko kwaikwaya.
Ya ƙunshi rubutun ModelSim*/QuestaSim* msim_setup.tcl don saita da gudanar da simulation.
Ya ƙunshi rubutun harsashi vcs_setup.sh don saita da gudanar da simintin VCS*. Ya ƙunshi rubutun harsashi vcsmx_setup.sh da synopsys_sim.setup file don saita da gudanar da simintin VCS MX.
Ya ƙunshi rubutun harsashi xcelium_setup.sh da sauran saitin files don saita da gudanar da simintin Xcelium*.
Ya ƙunshi HDL files don submodules na IP.
Ga kowane kundin adireshin IP na yara da aka samar, Platform Designer yana haifar da synth/ da sim/ sub-directory.

3.4. Simulating Intel FPGA IP Cores
Software na Intel Quartus Prime yana goyan bayan simintin IP core RTL a cikin takamaiman na'urar kwaikwayo ta EDA. Ƙirƙirar IP na zaɓin ƙirƙira simulation files, gami da ƙirar simintin aiki, kowane testbench (ko example zane), da takamaiman rubutun saitin na'urar kwaikwayo na mai siyarwa don kowane ainihin IP. Kuna iya amfani da samfurin siminti mai aiki da kowane testbench ko example zane don kwaikwayo. Fitowar tsarar IP na iya haɗawa da rubutun don haɗawa da gudanar da kowane benci. Rubutun suna jera duk samfura ko ɗakunan karatu da kuke buƙata don kwaikwayi ainihin IP ɗin ku.

F-Tile Serial Lite IV Intel® FPGA IP Jagorar Mai Amfani 16

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Software na Intel Quartus Prime yana ba da haɗin kai tare da na'urori masu yawa da yawa kuma yana goyan bayan kwararar simintin gyare-gyare masu yawa, gami da naku rubutun da naku na kwaikwaiyo. Ko wane kwarara kuka zaba, simintin simintin IP ya ƙunshi matakai masu zuwa:
1. Ƙirƙirar IP HDL, testbench (ko example zane), da rubutun saitin na'urar kwaikwayo files.
2. Saita yanayin na'urar kwaikwayo da kowane rubutun kwaikwayo.
3. Haɗa dakunan karatu na simulation.
4. Guda na'urar kwaikwayo.

3.4.1. Simulating da Tabbatar da Zane

Ta hanyar tsoho, editan siga yana haifar da takamaiman rubutun na'urar kwaikwayo masu ƙunshe da umarni don haɗawa, dalla-dalla, da kwaikwayi samfuran Intel FPGA IP da ɗakin karatu na ƙirar simulation. files. Kuna iya kwafin umarnin cikin rubutun gwajin gwajin ku, ko shirya waɗannan files don ƙara umarni don haɗawa, haɓakawa, da kwaikwaya ƙira da bench ɗin ku.

Table 10. Intel FPGA IP Core Simulation Scripts

Na'urar kwaikwayo

File Jagora

ModelSim

_sim/masu jagoranci

QuestaSim

VCS

_sim/synopsys/vcs

Farashin VCS MX

_sim/synopsys/vcsmx

Xcelium

_sim/xcelium

Rubutun msim_setup.tcl (7)
vcs_setup.sh vcsmx_setup.sh synopsys_sim.setup xcelium_setup.sh

3.5. Haɗa Ƙa'idodin IP a cikin Wasu Kayan aikin EDA
Zabi, yi amfani da wani goyan bayan kayan aikin EDA don haɗa ƙira wanda ya haɗa da kayan kwalliyar IP na Intel FPGA. Lokacin da kake samar da haɗin haɗin IP files don amfani tare da kayan aikin haɗin EDA na ɓangare na uku, zaku iya ƙirƙirar yanki da lissafin adadin lokaci. Don kunna tsarawa, kunna Ƙirƙirar lokaci da ƙididdiga na albarkatu don kayan aikin haɗin EDA na ɓangare na uku lokacin keɓance bambancin IP naku.
Wurin da lissafin ƙididdiga na lokaci yana bayyana haɗin haɗin kai da gine-gine na IP, amma baya haɗa da cikakkun bayanai game da ayyuka na gaskiya. Wannan bayanin yana ba da damar wasu kayan aikin haɗin kai na ɓangare na uku don ingantaccen rahoton yanki da ƙididdigar lokaci. Bugu da ƙari, kayan aikin haɗawa na iya amfani da bayanan lokaci don cimma ƙwaƙƙwaran ƙayyadaddun lokaci da haɓaka ingancin sakamako.
Intel Quartus Prime software yana haifar da _syn.v netlist file a cikin tsarin Verilog HDL, ba tare da la'akari da fitarwa ba file format ka saka. Idan kuna amfani da wannan jerin saƙon don haɗawa, dole ne ku haɗa da abin kundi na ainihin IP file .v ko .vhd a cikin Intel Quartus Prime aikin ku.

(7) Idan baku saita zaɓin kayan aikin EDA ba - wanda ke ba ku damar fara na'urorin EDA na ɓangare na uku daga Intel Quartus Prime software - gudanar da wannan rubutun a cikin ModelSim ko QuestaSim na'urar kwaikwayo Tcl console (ba a cikin Intel Quartus Prime software ba. Tcl console) don guje wa kowane kurakurai.

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3.6. Haɗa Cikakken Zane
Kuna iya amfani da umarnin Fara Tari akan menu na sarrafawa a cikin Intel Quartus Prime Pro Edition software don haɗa ƙirar ku.

F-Tile Serial Lite IV Intel® FPGA IP Jagorar Mai Amfani 18

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4. Bayanin Aiki

Hoto na 5.

F-Tile Serial Lite IV Intel FPGA IP ya ƙunshi MAC da Ethernet PCS. MAC yana sadarwa tare da PCS na al'ada ta hanyar musaya na MII.

IP ɗin yana goyan bayan hanyoyin daidaitawa guda biyu:
PAM4 – Yana ba da lamba 1 zuwa 12 don zaɓi. IP koyaushe yana ɗaukar tashoshi na PCS guda biyu don kowane layi a cikin yanayin daidaitawa na PAM4.
NRZ-Yana ba da lamba 1 zuwa 16 don zaɓi.

Kowane yanayin daidaitawa yana goyan bayan hanyoyin bayanai guda biyu:
Yanayi na asali-Wannan yanayin yawo ne mai tsafta inda ake aika bayanai ba tare da fara fakiti ba, zagayowar fanko, da ƙarshen fakiti don ƙara yawan bandwidth. IP ɗin yana ɗaukar ingantaccen bayanai na farko azaman farkon fashe.

Canja wurin bayanai na asali tx_core_klout tx_avs_ready

tx_avs_valid tx_avs_data rx_core_clkout rx_avs_ready

D0 D1 D2 D3 D4 D5 D6

rx_avs_valid rx_avs_data

D0 D1 D2 D3 D4 D5 D6

ISO 9001: 2015 Rajista

4. Bayanin Aiki 683074 | 2022.04.28

Hoto na 6.

Cikakken yanayin - Wannan shine canjin yanayin fakiti. A cikin wannan yanayin, IP ɗin yana aika fashewa da sake zagayowar daidaitawa a farkon da ƙarshen fakiti azaman masu iyakancewa.

Canja wurin bayanai cikakke tx_core_klout

tx_avs_ready tx_avs_valid tx_avs_startofpacket tx_avs_endofpacket
tx_avs_data rx_core_clkout rx_avs_ready rx_avs_daidaitacce rx_avs_startofpacket rx_avs_endofpacket

D0 D1 D2 D3 D4 D5 D6

rx_avs_data

D0 D1 D2 D3 D4 D5 D6

Bayani mai alaƙa · F-Tile Serial Lite IV Intel FPGA IP Overview a shafi na 6 · F-Tile Serial Lite IV Intel FPGA IP Design ExampJagorar Mai Amfani

4.1. Bayanan Bayani na TX
Hanyar data TX ta ƙunshi abubuwa masu zuwa: · Adaftar MAC · Sarrafa toshe kalmar shiga · CRC · MII codeer · PCS block · PMA block

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Hoto 7. TX Datapath

Daga ma'anar mai amfani

TX MAC

Avalon Streaming Interface

MAC Adafta

Sarrafa Shigar Kalma

CRC

MII Encoder

MII Interface Custom PCS
PCS da PMA

TX Serial Interface Zuwa Wasu Na'urar FPGA

4.1.1. TX MAC adaftar
Adaftar TX MAC tana sarrafa watsa bayanai zuwa mahangar mai amfani ta amfani da mahallin yawo Avalon. Wannan toshe yana goyan bayan watsa bayanai da aka ayyana mai amfani da sarrafa kwarara.

Canja wurin bayanin da aka ayyana mai amfani

A cikin cikakken yanayin, IP ɗin yana ba da siginar tx_is_usr_cmd wanda zaku iya amfani dashi don fara zagayowar bayanin bayanin mai amfani kamar watsa XOFF/XON zuwa dabaru na mai amfani. Kuna iya fara zagayowar watsa bayanan da aka ayyana mai amfani ta hanyar tabbatar da wannan siginar da canja wurin bayanin ta amfani da tx_avs_data tare da tabbacin tx_avs_startofpacket da sigina tx_avs_valid. Toshe sai ya zana tx_avs_ready na zagayowar biyu.

Lura:

Siffar bayanin da aka ayyana mai amfani yana samuwa kawai a Cikakken Yanayin.

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Hoto na 8.

Gudanar da Yawo

Akwai yanayi inda TX MAC ba ya shirye don karɓar bayanai daga ma'anar mai amfani kamar lokacin tsarin sake daidaitawa ta hanyar haɗin gwiwa ko lokacin da babu bayanai don watsawa daga ma'anar mai amfani. Don guje wa asarar bayanai saboda waɗannan sharuɗɗan, IP ɗin yana amfani da siginar tx_avs_ready don sarrafa kwararar bayanai daga dabarun mai amfani. IP ɗin yana ƙaddamar da siginar lokacin da yanayi masu zuwa suka faru:
Lokacin da aka tabbatar da tx_avs_startofpacket, tx_avs_ready ana zazzagewa don zagayowar agogo ɗaya.
· Lokacin da aka tabbatar da tx_avs_endofpacket, tx_avs_ready ana deaserty don zagayowar agogo ɗaya.
· Lokacin da aka tabbatar da kowane CW guda biyu tx_avs_ready ana zazzage shi don zagayowar agogo biyu.
Lokacin shigar da alamar daidaitawa ta RS-FEC yana faruwa a cikin ƙirar PCS na al'ada, tx_avs_ready ana zazzagewa don zagayowar agogo huɗu.
Kowane 17 Ethernet core clock cycles in PAM4 modulation mode da kowane 33 Ethernet core clock cycles in NRZ modulation mode. tx_avs_ready an dafa shi don zagayen agogo ɗaya.
Lokacin da ma'anar mai amfani ya yi kayan zaki tx_avs_valid lokacin babu watsa bayanai.

Jadawalin lokaci masu zuwa sune examples na TX MAC adaftar ta amfani da tx_avs_ready don sarrafa kwararar bayanai.

Gudanar da Yawo tare da tx_avs_valid Deassertion da START/END Haɗe-haɗe CWs

tx_core_clout

tx_avs_valid tx_avs_data

D1D2D3

Ingantattun kayan abinci na sigina

D5D6

tx_avs_ready tx_avs_startofpacket

Shirye-shiryen kayan zaki na sigina don hawan keke biyu don saka KARSHEN-STRT CW

tx_avs_endofpacket

usrif_data

D1D2D3

CW_data

KARSHEN DN STRT D0 D1 D2 D3 BAKWAI D4

F-Tile Serial Lite IV Intel® FPGA IP Jagorar Mai Amfani 22

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Hoto na 9.

Ikon yawo tare da Shigar Alamar Daidaitawa
tx_core_klout tx_avs_valid

tx_avs_data tx_avs_ready

DN-5 DN-4 DN-3 DN-2 DN-1

DN+1

01234

tx_avs_startofpacket tx_avs_endofpacket

usrif_data CW_data CRC_data MII_data

DN-1 DN DN DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 DN-1

i_sl_tx_mii_valid

i_sl_tx_mii_d[63:0]

Saukewa: DN-1

DN+1

i_sl_tx_mii_c[7:0]

0 x0

i_sl_tx_mii_am

01234

i_sl_tx_mii_am_pre3

01234

Hoto na 10.

Ikon yawo tare da START/END CWs Haɗe-haɗe sun yi daidai da Shigar Alamar Daidaitawa

tx_core_klout tx_avs_valid

tx_avs_data

DN-5 DN-4 DN-3 DN-2 DN-1

tx_avs_a shirye

012 345 6

tx_avs_startofpacket

tx_avs_endofpacket

usrif_data

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 KARSHEN STRT D0

CW_data

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 KARSHEN STRT D0

CRC_bayanai

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 KARSHEN STRT D0

MII_bayanai

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 KARSHEN STRT D0

i_sl_tx_mii_valid

i_sl_tx_mii_d[63:0]

Saukewa: DN-1

KARSHEN STRT D0

i_sl_tx_mii_c[7:0]

0 x0

i_sl_tx_mii_am i_sl_tx_mii_am_pre3

01234

4.1.2. Sarrafa Kalma (CW) Shigar
F-Tile Serial Lite IV Intel FPGA IP yana gina CWs dangane da siginar shigarwa daga ma'anar mai amfani. CWs suna nuna masu iyakance fakiti, bayanin halin watsawa ko bayanan mai amfani zuwa toshe PCS kuma an samo su daga lambobin sarrafawa na XGMII.
Tebur mai zuwa yana nuna bayanin CWs masu goyan baya:

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Tebur 11.
FARA KYAUTA

Bayanin CWs masu goyan baya

Adadin Kalmomi (kalmar 1

= 64 bit)

EMPTY_CYC

IDLE

A'a

DATA

In-band

Bayani
Fara mai iyakance bayanai. Ƙarshen ƙayyadaddun bayanai. Kalmar sarrafawa (CW) don daidaita RX. Zagaye mara komai a cikin canja wurin bayanai. IDLE (daga band). Kayan aiki.

Tebur 12. Bayanin Filin CW
Filin RSVD num_valid_bytes_eob
EMPTY eop sop seop align CRC32 usr

Bayani
Filin da aka keɓe. Ana iya amfani da shi don tsawo na gaba. An ɗaure zuwa 0.
Adadin ingantattun bytes a cikin kalmar ƙarshe (64-bit). Wannan darajar 3bit ce. 3'b000: 8 bytes · 3'b001: 1 byte · 3'b010: 2 bytes · 3'b011: 3 bytes · 3'b100: 4 bytes · 3'b101: 5 bytes · 3'b110: 6 bytes · 3'b111: 7 bytes
Yawan kalmomi marasa inganci a ƙarshen fashe.
Yana nuna alamar raɗaɗin raɗaɗin RX Avalon don tabbatar da siginar fakitin ƙarshen.
Yana nuna alamar raɗaɗin raɗaɗin RX Avalon don tabbatar da siginar fakitin farawa.
Yana nuna madaidaicin raɗaɗin raɗaɗin RX Avalon don tabbatar da fakitin farawa da fakitin ƙarewa a cikin zagayowar guda ɗaya.
Duba daidaita RX.
Ma'aunin ƙididdiga na CRC.
Yana nuna cewa kalmar sarrafawa (CW) ta ƙunshi ƙayyadaddun bayanin mai amfani.

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4.1.2.1. Farkon fashe CW

Hoto 11. Fara-na-fashe Tsarin CW

FARA

63:56

RSVD

55:48

RSVD

47:40

RSVD

data

39:32 31:24

Farashin RSVD

23:16

sop usr align = 0 seop

15:8

tashar

7:0

'hFB(START)

sarrafa 7:0

Tebur 13.

A cikin cikakken yanayin, zaku iya saka START CW ta hanyar tabbatar da siginar tx_avs_startofpacket. Lokacin da ka tabbatar da siginar tx_avs_startofpacket kawai, an saita bit sop. Lokacin da kuka tabbatar duka tx_avs_startofpacket da tx_avs_endofpacket sigina, an saita seop bit.

FARA ƙimar filin CW
Filin sop/seop
usr (8)
daidaita

Daraja

Dangane da siginar tx_is_usr_cmd:

1: Lokacin tx_is_usr_cmd = 1

0: Lokacin tx_is_usr_cmd = 0

A cikin yanayin asali, MAC yana aika START CW bayan an sake saita saiti. Idan babu bayanai, MAC ta ci gaba da aika EMPTY_CYC tare da END da START CWs har sai kun fara aika bayanai.

4.1.2.2. Ƙarshen fashe CW

Hoto 12. Tsarin CW na Ƙarshen Fashe

KARSHE

63:56

' hFD

55:48

CRC32[31:24]

47:40

CRC32[23:16]

bayanai 39:32 31:24

CRC32[15:8] CRC32[7:0]

23:16 eop=1 RSVD RSVD RSVD

RSVD

15:8

RSVD

EMPTY

7:0

RSVD

num_valid_bytes_eob

sarrafawa

7:0

(8) Ana goyan bayan wannan a Cikakken Yanayin kawai.
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Tebur 14.

MAC tana saka END CW lokacin da aka tabbatar da tx_avs_endofpacket. END CW ya ƙunshi adadin ingantattun bytes a kalmar bayanai ta ƙarshe da bayanin CRC.

Ƙimar CRC shine sakamakon 32-bit CRC don bayanai tsakanin START CW da kalmar bayanai kafin END CW.

Tebu mai zuwa yana nuna ƙimar filayen a END CW.

KARSHEN Ƙimar Filin CW
Filin eop CRC32 num_valid_bytes_eob

Daraja 1
CRC32 ƙididdige ƙima. Adadin ingantattun bytes a kalmar bayanan ƙarshe.

4.1.2.3. Daidaita Haɗakar CW

Hoto 13. Daidaitaccen Tsarin CW Haɗe-haɗe

alignn CW Haɗa tare da FARA/KARSHE

64+8bits XGMII Interface

FARA

63:56

RSVD

55:48

RSVD

47:40

RSVD

data

39:32 31:24

Farashin RSVD

23:16 eop=0 sop=0 usr=0 align=1 seop=0

15:8

RSVD

7:0

da hFB

sarrafa 7:0

64+8bits XGMII Interface

KARSHE

63:56

' hFD

55:48

RSVD

47:40

RSVD

data

39:32 31:24

Farashin RSVD

23:16 eop=0 RSVD RSVD RSVD

RSVD

15:8

RSVD

7:0

RSVD

sarrafa 7:0

ALIGN CW shine CW guda biyu tare da START/END ko END/START CWs. Kuna iya saka ALIGN da aka haɗa CW ta ko dai tabbatar da siginar tx_link_reinit, saita ma'aunin Lokacin Daidaitawa, ko fara sake saiti. Lokacin da aka saka ALIGN mai haɗaka CW, an saita filin daidaitawa zuwa 1 don fara shingen daidaitawar mai karɓa don duba daidaitawar bayanai a duk hanyoyin.

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Tebur 15.

ALIGN CW Field Values
Daidaita filin
eop da usr seop

Darajar 1 0 0 0 0

4.1.2.4. CW mara amfani

Hoto 14. Tsarin CW mara amfani

EMPTY_CYC Haɗa tare da END/START

64+8bits XGMII Interface

KARSHE

63:56

' hFD

55:48

RSVD

47:40

RSVD

data

39:32 31:24

Farashin RSVD

23:16 eop=0 RSVD RSVD RSVD

RSVD

15:8

RSVD

7:0

RSVD

sarrafa 7:0

64+8bits XGMII Interface

FARA

63:56

RSVD

55:48

RSVD

47:40

RSVD

data

39:32 31:24

Farashin RSVD

23:16

sop=0 usr=0 align=0 seop=0

15:8

RSVD

7:0

da hFB

sarrafa 7:0

Tebur 16.

Lokacin da kuka saka tx_avs_valid na zagayowar agogo biyu yayin fashewa, MAC ta saka EMPTY_CYC CW wanda aka haɗa tare da END/START CWs. Kuna iya amfani da wannan CW lokacin da babu bayanai don watsawa na ɗan lokaci.

Lokacin da kuka saka tx_avs_valid na zagayowar guda ɗaya, IP ɗin yana yin kayan zaki tx_avs_valid sau biyu tsawon lokacin tx_avs_valid abin ƙawa don samar da biyu na END/START CWs.

EMPTY_CYC CW Matsayin Filin
Daidaita filin
eop

Darajar 0 0

ci gaba…

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Field sop usr seop

Darajar 0 0 0

4.1.2.5. Rashin aiki CW

Hoto 15. Tsarin CW mara aiki

Farashin CW

63:56

h07

55:48

h07

47:40

h07

data

39:32 31:24

h07 h07

23:16

h07

15:8

h07

7:0

h07

sarrafa 7:0

MAC saka IDLE CW lokacin da babu watsawa. A wannan lokacin, siginar tx_avs_valid yayi ƙasa sosai.
Kuna iya amfani da IDLE CW lokacin da fashewar canja wuri ya ƙare ko watsa yana cikin rashin aiki.

4.1.2.6. Data Word

Kalmar bayanan ita ce nauyin fakiti. An saita ragowar sarrafawa na XGMII zuwa 0 a tsarin kalmar bayanai.

Hoto 16. Tsarin Kalmomin Bayanai

64+8 bits XGMII Interface

DATA MAGANA

63:56

masu amfani data 7

55:48

masu amfani data 6

47:40

masu amfani data 5

data

39:32 31:24

bayanan mai amfani 4 bayanan mai amfani 3

23:16

masu amfani data 2

15:8

masu amfani data 1

7:0

masu amfani data 0

sarrafa 7:0

4.1.3. Farashin CRC
Kuna iya kunna toshewar TX CRC ta amfani da Enable CRC parameter a cikin Editan Sigar IP. Ana samun goyan bayan wannan fasalin a duka Na asali da Cikakken halaye.

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MAC yana ƙara ƙimar CRC zuwa END CW ta hanyar tabbatar da siginar tx_avs_endofpacket. A cikin yanayin BASIC, kawai ALIGN CW wanda aka haɗa tare da END CW ya ƙunshi ingantaccen filin CRC.
TX CRC toshe musaya tare da TX Control Word Insertion da TX MII Encode block. Tushen TX CRC yana ƙididdige ƙimar CRC don ƙimar 64-bit kowane bayanan sake zagayowar farawa daga START CW har zuwa KARSHEN CW.
Kuna iya tabbatar da siginar crc_error_inject zuwa lalata bayanai da gangan a cikin takamaiman layi don ƙirƙirar kurakuran CRC.

4.1.4. TX MII Encoder

TX MII encoder yana sarrafa watsa fakiti daga MAC zuwa TX PCS.

Hoto mai zuwa yana nuna tsarin bayanai akan bas ɗin MII 8-bit a cikin yanayin daidaitawa PAM4. START da END CW suna bayyana sau ɗaya a cikin kowane hanyoyin MII guda biyu.

Hoto 17. PAM4 Modulation Mode MII Tsarin Bayanai

ZAGAYA 1

ZAGAYA 2

ZAGAYA 3

ZAGAYA 4

ZAGAYA 5

SOP_CW

DATA_1

DATA_9 DATA_17

IDLE

DATA_DUMMY SOP_CW
DATA_DUMMY

DATA_2 DATA_3 DATA_4

DATA_10 DATA_11 DATA_12

DATA_18 DATA_19 DATA_20

EOP_CW IDLE
EOP_CW

SOP_CW

DATA_5 DATA_13 DATA_21

IDLE

DATA_DUMMY DATA_6 DATA_14 DATA_22 EOP_CW

SOP_CW DATA_DUMMY

DATA_7 DATA_8

DATA_15 DATA_16

DATA_23 DATA_24

IDLE EOP_CW

Hoto mai zuwa yana nuna tsarin bayanai akan bas ɗin MII 8-bit a cikin yanayin daidaitawa na NRZ. START da END CW suna bayyana a kowane hanyoyin MII.

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Hoto 18. NRZ Modulation Mode MII Tsarin Bayanai

ZAGAYA 1

ZAGAYA 2

ZAGAYA 3

SOP_CW

DATA_1

DATA_9

SOP_CW

DATA_2 DATA_10

SOP_CW SOP_CW

DATA_3 DATA_4

DATA_11 DATA_12

SOP_CW

DATA_5 DATA_13

SOP_CW

DATA_6 DATA_14

SOP_CW

DATA_7 DATA_15

SOP_CW

DATA_8 DATA_16

CYCLE 4 DATA_17 DATA_18 DATA_19 DATA_20 DATA_21 DATA_22 DATA_23 DATA_24

CYCLE 5 EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW

4.1.5. TX PCS da PMA
F-Tile Serial Lite IV Intel FPGA IP yana daidaita mai karɓar tile F-tile zuwa yanayin PCS na Ethernet.

4.2. RX Datapath
Hanyar data RX ta ƙunshi abubuwa masu zuwa: · PMA block · PCS block · MII decoder · CRC · Deskew block · Sarrafa kauwar Kalma

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Hoto 19. RX Datapath

Don dabaru na mai amfani Avalon Streaming Interface
RX MAC
Sarrafa Cire Kalma
Deskew

CRC

MII Decoder

MII Interface Custom PCS
PCS da PMA

RX Serial Interface Daga Sauran Na'urar FPGA
4.2.1. RX PCS da PMA
F-Tile Serial Lite IV Intel FPGA IP yana daidaita mai karɓar tayal F-tile zuwa yanayin PCS na Ethernet.
4.2.2. RX MII Dikoda
Wannan toshe yana gano idan bayanan mai shigowa ya ƙunshi kalmar sarrafawa da alamomin daidaitawa. Mai ƙididdigewa na RX MII yana fitar da bayanai a cikin hanyar 1-bit mai inganci, mai nuna alama 1-bit, mai nuna iko 1bit, da bayanan 64-bit kowane layi.
4.2.3. Farashin CRC
Kuna iya kunna toshewar TX CRC ta amfani da Enable CRC parameter a cikin Editan Sigar IP. Ana samun goyan bayan wannan fasalin a duka Na asali da Cikakken halaye. RX CRC toshe musaya tare da RX Control Word Removal da RX MII blocks. IP ɗin yana tabbatar da siginar rx_crc_error lokacin da kuskuren CRC ya auku.

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IP ɗin yana fitar da rx_crc_error a kowane sabon fashe. Fitarwa ce zuwa dabaru na mai amfani don sarrafa kuskuren dabaru na mai amfani.
4.2.4. RX Deskew
Tushen deskew na RX yana gano alamomin daidaitawa don kowane layi kuma ya sake daidaita bayanan kafin aika shi zuwa toshewar cirewar RX CW.
Kuna iya zaɓar barin ainihin IP ɗin don daidaita bayanai don kowane layi ta atomatik lokacin da kuskuren jeri ya faru ta hanyar saita madaidaicin daidaitawa ta atomatik a cikin Editan sigar IP. Idan kun kashe fasalin daidaitawa ta atomatik, ainihin IP ɗin yana tabbatar da siginar rx_error don nuna kuskuren jeri. Dole ne ku tabbatar da rx_link_reinit don fara aikin daidaita layin lokacin da kuskuren daidaita layin ya faru.
Deskew na RX yana gano alamun daidaitawa bisa injin jiha. Hoton da ke gaba yana nuna jahohin da ke cikin RX toshewar deskew.

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Hoto na 20.

RX Deskew Lane Daidaita Injin Jiha tare da Daidaita Kai tsaye Taswirar Yawo
Fara

IDLE

Sake saiti = 1 eh a'a

Duk PCS

a'a

hanyoyi shirye?

iya

JIRA

Duk alamomin sync no
gano?
iya
ALIGN

a'a
a Timeout?

iya
An rasa daidaitawa?
babu Karshe

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Hoto na 21.

RX Deskew Lane Daidaita Injin Jiha tare da Taswirar Rarrabuwar Tashin Kai
Fara

IDLE

Sake saiti = 1 eh a'a

Duk PCS

a'a

hanyoyi shirye?

iya

iya
rx_link_reinit = 1
babu KUSKURE

a'a a Timeout?

JIRA
babu Duk alamomin daidaitawa
gano?
iya ALIGN

iya
An rasa daidaitawa?
a'a
Ƙarshe
1. Tsarin daidaitawa yana farawa da jihar IDLE. Katangar tana matsawa zuwa JIRA lokacin da duk hanyoyin PCS suka shirya kuma rx_link_reinit an dafa shi.
2. A cikin JIRA, toshe yana duba duk alamomin da aka gano ana tabbatar dasu a cikin zagayowar guda ɗaya. Idan wannan yanayin gaskiya ne, toshe yana motsawa zuwa jihar ALIGNED.
3. Lokacin da toshe yana cikin ALIGNED state, yana nuna layin sun daidaita. A cikin wannan jiha, toshe yana ci gaba da lura da daidaita layin da duba ko duk alamomin suna nan a cikin zagayowar guda ɗaya. Idan aƙalla alamar alama ɗaya baya cikin zagayowar guda kuma an saita siginar Enable Auto Alignment, toshe yana zuwa

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Jihar IDLE don sake fara aikin daidaitawa. Idan ba a saita Enable Auto Alignment kuma aƙalla alamar alama ɗaya ba ta kasancewa a cikin zagayowar guda ɗaya, toshe yana zuwa ERROR jihar kuma yana jira dabarar mai amfani don tabbatar da siginar rx_link_reinit don fara aikin daidaita layi.

Hoto 22. Daidaita Layi tare da Kunna Daidaitawa ta atomatik An kunna rx_core_clk

rx_link_up

rx_link_reinit

da_duk_alama

Jihar Deskew

ALGNED

IDLE

JIRA

ALGNED

AUTO_ALIGN = 1

Hoto 23. Gyaran Layi tare da Kunna Daidaitawa ta atomatik rx_core_clk

rx_link_up

rx_link_reinit

da_duk_alama

Jihar Deskew

ALGNED

KUSKURE

IDLE

JIRA

ALGNED

AUTO_ALIGN = 0
4.2.5. Cire RX CW
Wannan toshe yana ƙaddamar da CWs kuma yana aika bayanai zuwa dabaru na mai amfani ta amfani da keɓancewar raɗaɗin Avalon bayan cirewar CWs.
Lokacin da babu ingantaccen bayanai da ake samu, toshewar cirewar RX CW yana sanya siginar rx_avs_valid.
A CIKAKKEN yanayin, idan an saita bit mai amfani, wannan toshe yana tabbatar da siginar rx_is_usr_cmd kuma ana amfani da bayanan da ke cikin zagayowar agogon farko azaman bayanin da aka ayyana mai amfani ko umarni.
Lokacin da rx_avs_ready deasserts da rx_avs_valid ya tabbatar, toshewar cirewar RX CW yana haifar da yanayin kuskure ga tunanin mai amfani.
Sigina masu yawo na Avalon masu alaƙa da wannan toshe sune kamar haka: · rx_avs_startofpacket · rx_avs_endofpacket · rx_avs_channel · rx_avs_empty · rx_avs_data

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· rx_avs_mai inganci
· rx_num_valid_bytes_eob
rx_is_usr_cmd (ana samunsa a cikin cikakken yanayin kawai)
4.3. F-Tile Serial Lite IV Intel FPGA IP Architecture
F-Tile Serial Lite IV Intel FPGA IP yana da abubuwan shigar agogo huɗu waɗanda ke haifar da agogo zuwa tubalan daban-daban: · Agogon nuni (xcvr_ref_clk) – Agogon shigarwa daga agogon waje.
kwakwalwan kwamfuta ko oscillators waɗanda ke haifar da agogo don TX MAC, RX MAC, da TX da RX tubalan PCS na al'ada. Koma zuwa Ma'auni don kewayon mitar mai goyan baya. · TX core clock (tx_core_clk) – Wannan agogon an samo shi daga transceiver PLL ana amfani dashi don TX MAC. Wannan agogon kuma agogon fitarwa ne daga mai jujjuyawar tile F-tile don haɗawa da dabaru na mai amfani da TX. · RX core clock (rx_core_clk) – Wannan agogon an samo shi daga transceiver PLL ana amfani dashi don RX deskew FIFO da RX MAC. Wannan agogon kuma agogon fitarwa ne daga mai jujjuyawar tile F-tile don haɗawa da dabaru na mai amfani da RX. * Agogo don sake fasalin fasalin transceiver (reconfig_clk) - agogon shigarwa daga da'irori na agogo na waje ko oscillators waɗanda ke haifar da agogo don sake fasalin fasalin F-tile transceiver a duka hanyoyin TX da RX. Mitar agogo shine 100 zuwa 162 MHz.
Hoton toshe mai zuwa yana nuna F-Tile Serial Lite IV Intel FPGA IP yankin agogo da haɗin kai a cikin IP.

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Hoto na 24.

F-Tile Serial Lite IV Intel FPGA IP Architecture

Oscillator

Farashin FPGA1
F-Tile Serial Lite IV Intel FPGA IP Transceiver Reconfiguration Interface Clock
(reconfig_clk)

tx_core_clkout (haɗa zuwa dabaru na mai amfani)

tx_core_clk= clk_pll_div64[mid_ch]

Farashin FPGA2

F-Tile Serial Lite IV Intel FPGA IP

Agogon Sake Canja wurin Mai Canjawa

(reconfig_clk)

Oscillator

rx_core_clk= clk_pll_div64[mid_ch]

rx_core_clkout (haɗa zuwa ma'anar mai amfani)

clk_pll_div64[mid_ch] clk_pll_div64[n-1:0]

Avalon Streaming Interface TX Data
TX MAC

serial_link[n-1:0]

Deskew

FIFO

Avalon Streaming Interface RX Data RX MAC

Avalon Streaming Interface RX Data
RX MAC

Farashin FIFO

rx_core_clkout (haɗa zuwa ma'anar mai amfani)

rx_core_clk= clk_pll_div64[mid_ch]

PCS na al'ada

serial_link[n-1:0]

TX MAC

Avalon Streaming Interface TX Data

tx_core_clk= clk_pll_div64[mid_ch]

tx_core_clkout (haɗa zuwa dabaru na mai amfani)

Agogon Ref (xcvr_ref_clk)
Agogon Ref (xcvr_ref_clk)

Oscillator*

Labari

Na'urar FPGA
TX ainihin agogon yanki
yankin agogon ainihin RX
Yankin agogo mai jujjuyawar siginar bayanai na na'urar waje

4.4. Sake saiti da Ƙaddamar da Haɗin kai
MAC, F-tile Hard IP, da tubalan sake fasalin suna da siginar sake saiti daban-daban: · TX da RX MAC tubalan suna amfani da tx_core_rst_n da rx_core_rst_n siginar sake saiti. tx_pcs_fec_phy_reset_n da rx_pcs_fec_phy_reset_n sake saitin sigina
mai taushin sake saitin mai sarrafa don sake saita F-tile Hard IP. Toshewar sake fasalin yana amfani da siginar sake saiti na reconfig_reset.

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Hoto 25. Sake saita Gine-gine
Avalon Streaming Interface TX Data
MAC
Bayanan Bayani na Avalon Streaming SYNC Interface RX

FPGA F-tile Serial Lite IV Intel FPGA IP

tx_mii rx_mii
phy_ehip_a shirye phy_rx_pcs_shirye

F-tile Hard IP

TX Serial Data RX Serial Data

tx_core_rstn rx_core_rstn tx_pcs_fec_phy_reset_n rx_pcs_fec_phy_reset_n reconfig_reset

Sake saita gicari
Bayani mai alaƙa · Sake saitin jagororin shafi na 51 · F-Tile Serial Lite IV Intel FPGA IP Design ExampJagorar Mai Amfani
4.4.1. Sake saitin TX da Jerin farawa
Jerin sake saitin TX na F-Tile Serial Lite IV Intel FPGA IP shine kamar haka: 1. Sanya tx_pcs_fec_phy_reset_n, tx_core_rst_n, da reconfig_reset
lokaci guda don sake saita F-tile hard IP, MAC, da tubalan sake saitawa. Saki tx_pcs_fec_phy_reset_n da sake saita saitin bayan jira tx_reset_ack don tabbatar da sake saita tubalan da kyau. 2. IP din yana tabbatar da phy_tx_lanes_stable, tx_pll_locked, da phy_ehip_ready sigina bayan an saki tx_pcs_fec_phy_reset_n reset, don nuna TX PHY yana shirye don watsawa. 3. Siginar tx_core_rst_n yana yin deassert bayan siginar phy_ehip_ready yana girma. 4. IP yana fara watsa haruffa IDLE akan MII dubawa da zarar MAC ya fita sake saiti. Babu buƙatu don daidaita layin TX da skewing saboda duk hanyoyin suna amfani da agogo iri ɗaya. 5. Yayin aika haruffa IDLE, MAC tana tabbatar da siginar tx_link_up. 6. MAC sai ta fara watsa ALIGN wanda aka haɗa tare da START/END ko END/START CW a ƙayyadaddun tazara don fara tsarin daidaita layi na mai karɓa mai haɗawa.

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Hoto na 26.

Sake saitin TX da Zane-zanen Farawa
reconfig_sl_clk

reconfig_clk

tx_core_rst_n

tx_pcs_fec_phy_reset_n 1

reconfig_reset

reconfig_sl_reset

tx_reset_ack

tx_pll _kulle

phy_tx_hanyoyin_stable

phy_hip_a shirye

tx_li nk_up

7
5 6 8

4.4.2. Sake saitin RX da Tsarin Farkowa
Jerin sake saitin RX don F-Tile Serial Lite IV Intel FPGA IP kamar haka:
1. Sanya rx_pcs_fec_phy_reset_n, rx_core_rst_n, da reconfig_reset lokaci guda don sake saita F-tile hard IP, MAC, da tubalan sake saitawa. Saki rx_pcs_fec_phy_reset_n da sake saita saitin bayan jiran rx_reset_ack don tabbatar da sake saita tubalan da kyau.
2. IP ɗin yana tabbatar da siginar phy_rx_pcs_ready bayan an sake saitin PCS na al'ada, don nuna RX PHY yana shirye don watsawa.
3. A rx_core_rst_n siginar deasserts bayan phy_rx_pcs_ready siginar tafi high.
4. IP yana fara tsarin daidaita layin bayan an sake saitin RX MAC kuma akan karɓar ALIGN tare da START/END ko END/START CW.
5. Rukunin deskew na RX yana tabbatar da siginar rx_link_up da zarar daidaitawa ga duk hanyoyin ya cika.
6. IP ɗin yana ƙaddamar da siginar rx_link_up zuwa ma'anar mai amfani don nuna cewa hanyar haɗin RX ta shirya don fara karɓar bayanai.

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Hoto 27. Sake saitin RX da Tsarin Ƙaddamarwa
reconfig_sl_clk

reconfig_clk

rx_core_rst_n

rx_pcs_fec_phy_reset_n 1

reconfig_reset

reconfig_sl_reset

rx_reset_ack

rx_cdr_kulle

rx_block_lock

rx_pcs_ shirye

rx_link_up

3 3 3 2

4 5 5

6 7

4.5. Adadin Haɗi da Ƙididdiga Ingantaccen Bandwidth

The F-Tile Serial Lite IV Intel FPGA IP ƙimar ingancin bandwidth yana kamar ƙasa:

Ingantaccen bandwidth = raw_rate * 64/66 * (burst_size - burst_size_ovhd)/burst_size * [align_marker_period / (align_marker_period + align_marker_width)] * [(srl4_align_period - 2) / srl4_align

Tebur 17. Bayanin Canjin Canjin Canjin Bandwidth

Mai canzawa

Bayani

raw_rate fashe_size

Wannan shi ne ƙimar bit ɗin da aka samu ta hanyar haɗin yanar gizo. raw_rate = SERDES nisa * mitar agogo mai wucewa Example: raw_rate = 64 * 402.812500 Gbps = 25.78 Gbps
Darajar girman fashe. Don ƙididdige matsakaicin ingancin bandwidth, yi amfani da ƙimar fashe gama gari. Don matsakaicin ƙima, yi amfani da matsakaicin ƙimar girman fashe.

fashe_size_ovhd

Girman fashe kimar sama.
A cikin cikakken yanayin, ƙimar burst_size_ovhd tana nufin START da END CWs.
A cikin yanayin asali, babu fashewar_size_ovhd saboda babu START da END hade CWs.

align_marker_period

Darajar lokacin da aka saka alamar jeri. Ƙimar ita ce zagayowar agogo 81920 don haɗawa da 1280 don kwaikwaiyo cikin sauri. Ana samun wannan ƙimar daga ma'auni mai ƙarfi na PCS.

align_marker_width srl4_align_period

Adadin zagayowar agogo inda ingantaccen siginar alamar jeri ke riƙe babba.
Adadin zagayowar agogo tsakanin alamomin daidaitawa biyu. Kuna iya saita wannan ƙimar ta amfani da sigar Lokacin Daidaitawa a cikin Editan Sigar IP.

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Lissafin ƙimar hanyar haɗin suna kamar ƙasa: Ƙimar ƙima = ingancin bandwidth * raw_rate Zaka iya samun matsakaicin mitar agogo mai amfani tare da ma'auni mai zuwa. Matsakaicin lissafin mitar agogon mai amfani yana ɗaukar ci gaba da yawo bayanai kuma babu wani zagayowar IDLE da ke faruwa a mahangar mai amfani. Wannan ƙimar yana da mahimmanci yayin zayyana ma'anar FIFO mai amfani don gujewa ambaliya FIFO. Matsakaicin mitar agogo mai amfani = ƙimar inganci / 64

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5. Sigogi

Tebur 18. F-Tile Serial Lite IV Intel FPGA IP Siffar Siga

Siga

Daraja

Default

Bayani

Gabaɗaya Zaɓuɓɓukan Zane

Nau'in daidaitawa na PMA

PAM4 · NRZ

Saukewa: PAM4

Zaɓi yanayin daidaitawar PCS.

Nau'in PMA

FHT · FGT

FGT

Yana zaɓar nau'in transceiver.

Farashin PMA

Domin yanayin PAM4:
- Nau'in transceiver FGT: 20 Gbps 58 Gbps
- Nau'in transceiver FHT: 56.1 Gbps, 58 Gbps, 116 Gbps
Domin yanayin NRZ:
- Nau'in transceiver FGT: 10 Gbps 28.05 Gbps
- Nau'in transceiver FHT: 28.05 Gbps, 58 Gbps

56.1 (FGT/FHT PAM4)
28.05 Gbps (FGT/FHT NRZ)

Yana ƙayyadad da ingantaccen ƙimar bayanai a fitowar mai watsawa da ke haɗa watsawa da sauran abubuwan da ke sama. Ana ƙididdige ƙimar ta IP ta hanyar zagayawa har zuwa wuri 1 a rukunin Gbps.

Yanayin PMA

· Duplex · Tx · Rx

Duplex

Don nau'in transceiver FHT, jagorar da aka goyan bayan duplex ne kawai. Don nau'in transceiver FGT, jagoran da aka goyan baya shine Duplex, Tx, da Rx.

Adadin PMA

Domin yanayin PAM4:

hanyoyi

- 1 zuwa 12

Domin yanayin NRZ:

- 1 zuwa 16

Zaɓi adadin layuka. Don ƙirar simplex, adadin hanyoyin da aka goyan baya shine 1.

Mitar agogo PLL

Domin nau'in transceiver FHT: 156.25 MHz
Don nau'in transceiver FGT: 27.5 MHz 379.84375 MHz, ya danganta da ƙimar bayanan da aka zaɓa.

Domin nau'in transceiver FHT: 156.25 MHz
Domin nau'in transceiver FGT: 165 MHz

Yana ƙayyadad da mitar agogo mai jujjuyawa na transceiver.

Tsarin PLL

—

agogon tunani

mita

170 MHz

Akwai kawai don nau'in transceiver FHT. Yana ƙayyadadden agogon tunani na System PLL kuma za a yi amfani da shi azaman shigar da Maganar F-Tile da Tsarin PLL Clocks Intel FPGA IP don samar da agogon System PLL.

Mitar tsarin PLL
Lokacin daidaitawa

— 128 65536

Kunna RS-FEC

Kunna

876.5625 MHz 128 Kunna

Yana ƙayyade mitar agogon System PLL.
Yana ƙayyadadden lokacin daidaitawa. Dole ne ƙimar ta zama x2. Kunna don kunna fasalin RS-FEC.
ci gaba…

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Siga

Daraja

Default

Bayani

A kashe

Don yanayin daidaitawar PAM4 PCS, RS-FEC koyaushe yana kunna.

Interface mai amfani

Yanayin yawo

CIKAKKA · GASKIYAR BASIC

Cikakkun

Zaɓi bayanan yawo don IP.

Cikak: Wannan yanayin yana aika fakitin farawa da zagaye na ƙarshen fakiti a cikin firam.

Na asali: Wannan yanayin yawo ne mai tsafta inda aka aika bayanai ba tare da fara-fakiti ba, fanko, da ƙarshen fakiti don ƙara bandwidth.

Kunna CRC

Kunna Kashe

A kashe

Kunna don kunna gano kuskuren CRC da gyara.

Kunna daidaitawa ta atomatik

Kunna Kashe

A kashe

Kunna don kunna fasalin daidaita layi ta atomatik.

Kunna ƙarshen gyara kuskure

Kunna Kashe

A kashe

Lokacin da ON, F-Tile Serial Lite IV Intel FPGA IP ya haɗa da madaidaicin Ƙarshen Ƙarshen Debug wanda ke haɗa cikin ciki zuwa ƙirar ƙwaƙwalwar ajiyar Avalon. IP na iya yin wasu gwaje-gwaje da ayyukan gyara kuskure ta hanyar JTAG amfani da System Console. Ƙimar ta asali ta ƙare.

Haɗin Simplex (Wannan saitin sigar yana samuwa ne kawai lokacin da kuka zaɓi ƙirar FGT dual simplex.)

An kunna RSFEC akan sauran Serial Lite IV Simplex IP wanda aka sanya a tashar (s) FGT iri ɗaya.

Kunna Kashe

A kashe

Kunna wannan zaɓi idan kuna buƙatar cakuda daidaitawa tare da kunna RS-FEC kuma an kashe shi don F-Tile Serial Lite IV Intel FPGA IP a cikin ƙirar siffa mai sauƙi don yanayin transceiver NRZ, inda duka TX da RX aka sanya su akan FGT iri ɗaya. channel(s).

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6. F-Tile Serial Lite IV Intel FPGA IP Interface Sigina

6.1. Sigina na agogo

Tebur 19. Siginonin agogo

Suna

Hanyar Nisa

Bayani

tx_core_clout

Fitar da agogon ainihin TX don ƙirar PCS na al'ada na TX, TX MAC da dabaru masu amfani a ciki

Bayanan Bayani na TX.

An samar da wannan agogon daga tsarin PCS na al'ada.

rx_core_clout

Fitar agogon ainihin RX don ƙirar PCS na al'ada, RX deskew FIFO, RX MAC

da dabaru masu amfani a cikin hanyar bayanan RX.

An samar da wannan agogon daga tsarin PCS na al'ada.

xcvr_ref_clk
reconfig_clk reconfig_sl_clk

Input Transceiver reference Agogon.

Lokacin da aka saita nau'in transceiver zuwa FGT, haɗa wannan agogon zuwa siginar fitarwa (out_refclk_fgt_0) na F-Tile Reference da System PLL Clocks Intel FPGA IP. Lokacin da aka saita nau'in transceiver zuwa FHT, haɗa

wannan agogon zuwa siginar fitarwa (out_fht_cmmpll_clk_0) na F-Tile Reference da System PLL Clocks Intel FPGA IP.

Koma zuwa Ma'auni don kewayon mitar mai goyan baya.

Agogon shigar da bayanai don sake fasalin fasalin transceiver.

Mitar agogo shine 100 zuwa 162 MHz.

Haɗa siginar agogon shigarwa zuwa na'urorin agogo na waje ko oscillators.

Agogon shigar da bayanai don sake fasalin fasalin transceiver.

Mitar agogo shine 100 zuwa 162 MHz.

Haɗa siginar agogon shigarwa zuwa na'urorin agogo na waje ko oscillators.

fita_systempll_clk_ 1

Shigarwa

Tsarin agogon PLL.
Haɗa wannan agogon zuwa siginar fitarwa (out_systempll_clk_0) na F-Tile Reference da System PLL Clocks Intel FPGA IP.

Ma'auni na Bayani mai alaƙa a shafi na 42

6.2. Sake saitin sigina

Tebur 20. Sake saitin sigina

Suna

Hanyar Nisa

tx_core_rst_n

Shigarwa

Clock Domain Asynchronous

rx_core_rst_n

Shigarwa

Asynchronous

tx_pcs_fec_phy_reset_n 1

Shigarwa

Asynchronous

Bayani

Siginar sake saiti mara ƙarancin aiki. Yana sake saita F-Tile Serial Lite IV TX MAC.

Siginar sake saiti mara ƙarancin aiki. Yana sake saita F-Tile Serial Lite IV RX MAC.

Siginar sake saiti mara ƙarancin aiki.

ci gaba…

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Suna

Domain Agogon Jagoranci

Bayani

Yana sake saita F-Tile Serial Lite IV TX PCS na al'ada.

rx_pcs_fec_phy_reset_n 1

Shigarwa

Asynchronous

Siginar sake saiti mara ƙarancin aiki. Yana sake saita F-Tile Serial Lite IV RX PCS na al'ada.

reconfig_reset

Shigarwa

reconfig_clk Siginar sake saiti mai aiki-high.

Yana sake saita toshewar sake saita taswirar ƙwaƙwalwar ajiyar Avalon.

reconfig_sl_reset

Shigar da reconfig_sl_clk Siginar sake saiti mai aiki mai ƙarfi.

Yana sake saita toshewar sake saita taswirar ƙwaƙwalwar ajiyar Avalon.

6.3. Alamar MAC

Tebur 21.

TX MAC Sigina
A cikin wannan tebur, N yana wakiltar adadin hanyoyin da aka saita a cikin editan sigar IP.

Suna

Nisa

Hanyar Agogo Domain

Bayani

tx_avs_a shirye

Fitowa tx_core_klout Avalon siginar yawo.

Lokacin da aka tabbatar, yana nuna cewa TX MAC yana shirye don karɓar bayanai.

tx_avs_data

· (64*N)*2 (yanayin PAM4)
64*N (yanayin NRZ)

Shigarwa

tx_core_clout Avalon siginar yawo. Bayanan Bayani na TX.

tx_avs_channel

Shigar tx_core_klout Avalon siginar yawo.

Lambar tashar don canja wurin bayanai akan zagayowar yanzu.

Babu wannan siginar a Yanayin asali.

tx_avs_mai inganci

Shigar tx_core_klout Avalon siginar yawo.

Lokacin da aka tabbatar, yana nuna siginar bayanan TX yana aiki.

tx_avs_startofpacket

Shigar tx_core_klout Avalon siginar yawo.

Lokacin da aka tabbatar, yana nuna farkon fakitin bayanan TX.

Tabbatar da zagayowar agogo ɗaya kawai ga kowane fakiti.

Babu wannan siginar a Yanayin asali.

tx_avs_endofpacket

Shigar tx_core_klout Avalon siginar yawo.

Lokacin da aka tabbatar, yana nuna ƙarshen fakitin bayanan TX.

Tabbatar da zagayowar agogo ɗaya kawai ga kowane fakiti.

Babu wannan siginar a Yanayin asali.

tx_avs_ba komai

Shigar tx_core_klout Avalon siginar yawo.

Yana nuna adadin kalmomi marasa inganci a ƙarshen fashe bayanan TX.

Babu wannan siginar a Yanayin asali.

tx_num_valid_bytes_eob

Shigarwa

tx_core_clout

Yana nuna adadin ingantattun bytes a cikin kalmar ƙarshe na fashewar ƙarshe. Babu wannan siginar a Yanayin asali.
ci gaba…

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Suna tx_is_usr_cmd
tx_link_up tx_link_reinit
crc_error_inject tx_error

Fadin 1
1 1
N5

Hanyar Agogo Domain

Bayani

Shigarwa

tx_core_clout

Lokacin da aka tabbatar, wannan siginar yana fara zagayowar bayanin bayanin mai amfani.
Tabbatar da wannan siginar a zagayen agogo ɗaya kamar yadda tx_startofpacket ta tabbatar.
Babu wannan siginar a Yanayin asali.

Fitarwa tx_core_clkout Lokacin da aka tabbatar, yana nuna hanyar haɗin bayanan TX ta shirya don watsa bayanai.

Fitowa

tx_core_clout

Lokacin da aka tabbatar, wannan siginar yana fara sake daidaita layi.
Ƙaddamar da wannan sigina don zagayowar agogo ɗaya don kunna MAC don aika ALIGN CW.

Shigarwa

tx_core_clkout Lokacin da aka tabbatar, MAC tana shigar da kuskuren CRC32 zuwa zaɓaɓɓun hanyoyin.

Fitowa tx_core_clout Ba a yi amfani da shi ba.

Jadawalin lokaci mai zuwa yana nuna tsohonample na watsa bayanai na TX na kalmomi 10 daga ma'anar mai amfani a cikin layin serial 10 TX.

Hoto na 28.

Jadawalin Lokacin Isar Data TX
tx_core_clout

tx_avs_mai inganci

tx_avs_a shirye

tx_avs_startofpackets

tx_avs_endofpackets

tx_avs_data

0,1...,19 10,11…19 …… N-10..

0,1,2,,9

N-10..

Hanyar 0

…………

Farashin STRT0

N-10 KARSHEN STRT 0

Hanyar 1

…………

Farashin STRT1

N-9 KARSHEN STRT 1

N-10 KARSHEN Idle N-9 KARSHEN Idle

Hanyar 9

…………

Farashin STRT9

N-1 KARSHEN STRT 9

N-1 KARSHEN IDLE

Tebur 22.

RX MAC Sigina
A cikin wannan tebur, N yana wakiltar adadin hanyoyin da aka saita a cikin editan sigar IP.

Suna

Nisa

Hanyar Agogo Domain

Bayani

rx_avs_a shirye

Shigar da siginar yawo rx_core_klout Avalon.

Lokacin da aka tabbatar, yana nuna cewa dabarar mai amfani ya shirya don karɓar bayanai.

rx_avs_data

(64*N)*2 (Yanayin PAM4)
64*N (Yanayin NRZ)

Fitowa

rx_core_klout Avalon siginar yawo. Bayanan Bayani na RX.

rx_avs_channel

Fitar da siginar yawo rx_core_clout Avalon.

Lambar tashar don data kasance

samu akan zagayowar yanzu.

Babu wannan siginar a Yanayin asali.

rx_avs_mai inganci

Fitar da siginar yawo rx_core_clout Avalon.

ci gaba…

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Suna

Nisa

Hanyar Agogo Domain

Bayani

Lokacin da aka tabbatar, yana nuna siginar bayanan RX yana aiki.

rx_avs_startofpacket

Fitar da siginar yawo rx_core_clout Avalon.

Lokacin da aka tabbatar, yana nuna farkon fakitin bayanan RX.

Tabbatar da zagayowar agogo ɗaya kawai ga kowane fakiti.

Babu wannan siginar a Yanayin asali.

rx_avs_endofpacket

Fitar da siginar yawo rx_core_clout Avalon.

Lokacin da aka tabbatar, yana nuna ƙarshen fakitin bayanai na RX.

Tabbatar da zagayowar agogo ɗaya kawai ga kowane fakiti.

Babu wannan siginar a Yanayin asali.

rx_avs_ba komai

Fitar da siginar yawo rx_core_clout Avalon.

Yana nuna adadin kalmomi marasa inganci a ƙarshen fashe bayanan RX.

Babu wannan siginar a Yanayin asali.

rx_num_valid_bytes_eob

Fitowa

rx_core_clkout Yana Nuna adadin ingantattun bytes a cikin kalmar ƙarshe na fashewar ƙarshe.
Babu wannan siginar a Yanayin asali.

rx_is_usr_cmd

Fitar rx_core_clkout Lokacin da aka tabbatar, wannan siginar yana fara mai amfani-

ayyana sake zagayowar bayanai.

Tabbatar da wannan siginar a zagayen agogo ɗaya kamar yadda tx_startofpacket ta tabbatar.

Babu wannan siginar a Yanayin asali.

rx_link_up

Fitar rx_core_clkout Lokacin da aka tabbatar, yana nuna hanyar haɗin bayanan RX

yana shirye don karɓar bayanai.

rx_link_reinit

Shigar da rx_core_clkout Lokacin da aka tabbatar, wannan siginar yana fara hanyoyi

sake daidaitawa.

Idan kun kashe Kunna alignment ta atomatik, tabbatar da wannan siginar don zagayen agogo ɗaya don kunna MAC don sake daidaita hanyoyin. Idan an saita Enable Auto Alignment, MAC sake daidaita hanyoyin ta atomatik.

Kar a tabbatar da wannan siginar lokacin da aka saita Enable Auto alignment.

rx_error

(N*2*2)+3 (yanayin PAM4)
(N*2)*3 (Yanayin NRZ)

Fitowa

rx_core_clout

Lokacin da aka tabbatar, yana nuna yanayin kuskure yana faruwa a hanyar bayanan RX.
· [(N*2+2):N+3] = Yana Nuna Kuskuren PCS don takamaiman layi.
· [N+2] = Yana nuna kuskuren daidaitawa. Sake fara daidaita layi idan an tabbatar da wannan bit.
[N+1]= Yana nuna ana tura bayanai zuwa ga dabarar mai amfani lokacin da ba a shirya dabaru na mai amfani ba.
· [N] = Yana nuna asarar daidaitawa.
· [(N-1):0] = Yana nuna bayanan sun ƙunshi kuskuren CRC.

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6.4. Sigina na sake daidaitawa ta Transceiver

Tebur 23.

Sigina na sake saita PCS
A cikin wannan tebur, N yana wakiltar adadin hanyoyin da aka saita a cikin editan sigar IP.

Suna

Nisa

Hanyar Agogo Domain

Bayani

reconfig_sl_read

Shigar da reconfig_sl_ PCS sake saita umarnin karanta umarnin

clk

sigina.

reconfig_sl_write

Shigar da reconfig_sl_ PCS rubuta sake tsarawa

clk

alamun umarni.

reconfig_sl_address

14 bits + clogb2N

Shigarwa

reconfig_sl_ clk

Yana ƙayyadad da adreshin dubawar ƙwaƙwalwar ajiya na Avalon na PCS a cikin hanyar da aka zaɓa.
Kowane layi yana da rago 14 kuma babban ragowa yana nufin kashe layin.
Example, don ƙirar NRZ/PAM4 mai lamba 4, tare da reconfig_sl_address[13:0] yana nufin ƙimar adireshin:
· reconfig_sl_address[15:1 4] saita zuwa 00 = adireshin layin 0.
· reconfig_sl_address[15:1 4] saita zuwa 01 = adireshin layin 1.
· reconfig_sl_address[15:1 4] saita zuwa 10 = adireshin layin 2.
· reconfig_sl_address[15:1 4] saita zuwa 11 = adireshin layin 3.

reconfig_sl_readata

Fitarwa reconfig_sl_ Yana ƙayyade bayanan sake saita PCS

clk

za a karanta ta shirye-shiryen sake zagayowar a cikin a

hanyar da aka zaba.

reconfig_sl_waitrequest

Fitar reconfig_sl_ yana wakiltar sake fasalin PCS

clk

Avalon memory-mapped interface

siginar tsayawa a cikin zaɓaɓɓen layi.

reconfig_sl_writedata

Shigar da reconfig_sl_ Yana Ƙayyadaddun bayanan sake saita PCS

clk

da za a rubuta a kan sake zagayowar rubutu a cikin a

hanyar da aka zaba.

reconfig_sl_readata_vali

Fitowa

reconfig_sl_ Yana ƙayyadad da sake fasalin PCS

clk

bayanan da aka karɓa suna aiki a cikin zaɓin da aka zaɓa

layi.

Tebur 24.

F-Tile Hard IP Siginonin Sake daidaitawa
A cikin wannan tebur, N yana wakiltar adadin hanyoyin da aka saita a cikin editan sigar IP.

Suna

Nisa

Hanyar Agogo Domain

Bayani

reconfig_read

Shigar da reconfig_clk PMA sake saitawa karanta

alamun umarni.

reconfig_write

Shigar da reconfig_clk PMA reconfiguration rubuta

alamun umarni.

reconfig_address

18 bits + clog2bN

Shigarwa

reconfig_clk

Yana ƙayyadaddun adreshin dubawar ƙwaƙwalwar ajiya na PMA Avalon a cikin zaɓaɓɓen layi.
ci gaba…

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Suna
reconfig_readdata reconfig_waitrequest reconfig_writedata reconfig_readdatavalid

Nisa
32 1 32 1

Hanyar Agogo Domain

Bayani

A cikin duka hanyoyin PAM4 ad NRZ, kowane layi yana da ragowa 18 kuma ragowar manyan ragi suna nuni ga layin layi.
Example, don ƙirar hanya 4:
· reconfig_address[19:18] saita zuwa 00 = adireshin layin 0.
· reconfig_address[19:18] saita zuwa 01 = adireshin layin 1.
· reconfig_address[19:18] saita zuwa 10 = adireshin layin 2.
· reconfig_address[19:18] saita zuwa 11 = adireshin layin 3.

Fitowa

reconfig_clk Yana Ƙayyade bayanan PMA da shirye-shiryen sake zagayowar za a karanta a cikin hanyar da aka zaɓa.

Fitowa

reconfig_clk Yana wakiltar PMA Avalon memory taswirar keɓancewar siginar siginar a cikin layin da aka zaɓa.

Shigarwa

reconfig_clk Yana Ƙayyade bayanan PMA da za a rubuta akan zagayowar rubutu a cikin zaɓaɓɓen layi.

Fitowa

reconfig_clk Yana Ƙayyade sake daidaitawar PMA da aka karɓa yana aiki a cikin hanyar da aka zaɓa.

6.5. Alamomin PMA

Tebur 25.

Alamomin PMA
A cikin wannan tebur, N yana wakiltar adadin hanyoyin da aka saita a cikin editan sigar IP.

Suna

Nisa

Hanyar Agogo Domain

Bayani

phy_tx_hanyoyin_stable

N*2 (yanayin PAM4)
N (yanayin NRZ)

Fitowa

Asynchronous Lokacin da aka tabbatar, yana nuna hanyar bayanan TX yana shirye don aika bayanai.

tx_pll_kulle

N*2 (yanayin PAM4)
N (yanayin NRZ)

Fitowa

Asynchronous Lokacin da aka tabbatar, yana nuna TX PLL ta sami matsayin kullewa.

phy_hip_a shirye

N*2 (yanayin PAM4)
N (yanayin NRZ)

Fitowa

Asynchronous

Lokacin da aka tabbatar, yana nuna cewa PCS na al'ada ya kammala farawa na ciki kuma a shirye don watsawa.
Wannan siginar yana tabbatarwa bayan tx_pcs_fec_phy_reset_n da tx_pcs_fec_phy_reset_nare deasserted.

tx_serial_data

Fitar TX serial agogon TX serial fil.

rx_serial_data

Shigar da serial agogon RX serial fil.

phy_rx_block_lock

N*2 (yanayin PAM4)
N (yanayin NRZ)

Fitowa

Asynchronous Lokacin da aka tabbatar, yana nuna cewa an gama daidaita toshewar 66b don hanyoyin.

rx_cdr_kulle

N*2 (yanayin PAM4)

Fitowa

Asynchronous

Lokacin da aka tabbatar, yana nuna cewa agogon da aka kwato an kulle su zuwa bayanai.
ci gaba…

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Suna phy_rx_pcs_ready phy_rx_hi_ber

Nisa

Hanyar Agogo Domain

Bayani

N (yanayin NRZ)

N*2 (yanayin PAM4)
N (yanayin NRZ)

Fitowa

Asynchronous

Lokacin da aka tabbatar, yana nuna cewa hanyoyin RX na tashar Ethernet madaidaici sun daidaita kuma suna shirye don karɓar bayanai.

N*2 (yanayin PAM4)
N (yanayin NRZ)

Fitowa

Asynchronous

Lokacin da aka tabbatar, yana nuna cewa RX PCS na tashar Ethernet mai dacewa yana cikin yanayin HI BER.

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7. Zayyana tare da F-Tile Serial Lite IV Intel FPGA IP

7.1. Sake saitin Jagora
Bi waɗannan jagororin sake saitin don aiwatar da sake saitin matakin tsarin ku.
Haɗa sigina tx_pcs_fec_phy_reset_n da rx_pcs_fec_phy_reset_n tare akan matakin tsarin don sake saita TX da RX PCS lokaci guda.
Sanya tx_pcs_fec_phy_reset_n, rx_pcs_fec_phy_reset_n, tx_core_rst_n, rx_core_rst_n, da sake saita sigina a lokaci guda. Koma zuwa Sake saiti da Ƙaddamarwar Haɗin don ƙarin bayani game da sake saitin IP da jerin farawa.
· Rike tx_pcs_fec_phy_reset_n, da rx_pcs_fec_phy_reset_n sigina low, kuma reconfig_reset sigina sama da jira tx_reset_ack da rx_reset_ack don sake saita F-tile hard IP da kyau da tubalan sake fasalin.
Don samun haɗin kai cikin sauri tsakanin na'urorin FPGA, sake saita haɗin F-Tile Serial Lite IV Intel FPGA IPs a lokaci guda. Koma zuwa F-Tile Serial Lite IV Intel FPGA IP Design ExampJagorar mai amfani don bayani game da sa ido kan hanyar haɗin IP TX da RX ta amfani da kayan aiki.
Bayanai masu alaƙa
Sake saiti da Ƙaddamar da haɗin kai a shafi na 37
F-Tile Serial Lite IV Intel FPGA IP Design ExampJagorar Mai Amfani

7.2. Jagororin Gudanar da Kuskure

Tebur mai zuwa yana lissafin jagororin sarrafa kuskure don yanayin kuskure wanda zai iya faruwa tare da ƙirar F-Tile Serial Lite IV Intel FPGA IP.

Tebura 26. Kuskuren Yanayin Kuskure da Jagoran Gudanarwa

Yanayin Kuskure
Hanya ɗaya ko fiye ba za ta iya kafa sadarwa ba bayan ƙayyadaddun lokaci.

Jagorori
Aiwatar da tsarin kashe lokaci don sake saita hanyar haɗin gwiwa a matakin aikace-aikacen.

Hanya ta rasa sadarwa bayan kafa sadarwa.
Hanya ta rasa sadarwa yayin aikin deskew.

Wannan na iya faruwa bayan ko lokacin canja wurin bayanai. Aiwatar da gano asarar hanyar haɗi a matakin aikace-aikacen kuma sake saita hanyar haɗin.
Aiwatar da tsarin sake kunna hanyar haɗi don kuskuren layi. Dole ne ku tabbatar da cewa hanyar jirgin ba ta wuce 320 UI ba.

Daidaita layin asara bayan an daidaita dukkan hanyoyin.

Wannan na iya faruwa bayan ko lokacin canja wurin bayanai. Aiwatar da gano asarar daidaita layin a matakin aikace-aikace don sake fara aikin daidaita layin.

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8. F-Tile Serial Lite IV Intel FPGA IP Jagorar Jagorar Rubutun

Sifofin IP iri ɗaya ne da nau'ikan software na Intel Quartus Prime Design Suite har zuwa v19.1. Daga Intel Quartus Prime Design Suite software version 19.2 ko kuma daga baya, IP cores suna da sabon tsarin sigar IP.

Idan ba a jera sigar ainihin IP ba, jagorar mai amfani don sigar ainihin IP ta baya tana aiki.

Intel Quartus Prime Version
21.3

Shafin IP Core 3.0.0

Jagorar mai amfani F-Tile Serial Lite IV Intel® FPGA IP Jagorar mai amfani

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683074 | 2022.04.28 Aika Ra'ayoyin

9. Tarihin Bita na Takardu don F-Tile Serial Lite IV Jagorar Mai Amfani ta IP FPGA

Takardar Shafin 2022.04.28
2021.11.16 2021.10.22 2021.08.18

Intel Quartus Prime Version
22.1
21.3 21.3 21.2

Shafin IP 5.0.0
3.0.0 3.0.0 2.0.0

Canje-canje
Teburin da aka sabunta: F-Tile Serial Lite IV Siffofin IP na FPGA - Sabunta bayanin Canja wurin bayanai tare da ƙarin tallafin ƙimar FHT mai ɗaukar hoto: 58G NRZ, 58G PAM4, da 116G PAM4
Teburin da aka sabunta: F-Tile Serial Lite IV Bayanin sigar siginar IP na FPGA - Ƙara sabon siga · Mitar agogon tsarin PLL · Kunna ƙarshen gyara kuskure - An sabunta ƙimar ƙimar bayanan PMA - Sabunta suna don daidaitawa GUI
An sabunta bayanin don canja wurin bayanai a cikin Tebura: F-Tile Serial Lite IV Fasalolin IP na FPGA.
An Sake Sunan Teburi IP zuwa F-Tile Serial Lite IV Intel FPGA IP Siffar Siffar Siga a cikin sashin Ma'auni don tsabta.
Teburin da aka sabunta: sigogin IP: - Ƙara sabon siga-RSFEC da aka kunna akan sauran Serial Lite IV Simplex IP wanda aka sanya a tashar FGT iri ɗaya. - An sabunta tsoffin dabi'u don mitar agogo mai jujjuyawa.
Sakin farko.

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	intel F Tile Serial Lite IV Intel FPGA IP [pdf] Jagorar mai amfani F Tile Serial Lite IV Intel FPGA IP, F Tile Serial Lite IV, Intel FPGA IP
	intel F-Tile Serial Lite IV Intel FPGA IP [pdf] Jagorar mai amfani F-Tile Serial Lite IV Intel FPGA IP, Serial Lite IV Intel FPGA IP, Lite IV Intel FPGA IP, IV Intel FPGA IP, FPGA IP, IP

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