Geniatech SOM3568SMARC Smart Module
Product Usage Instructions
- The CBD-3568-SMARC is a development board featuring the SMARC-Module chipset with a Rock-Chip RK3568 CPU. It is designed for various applications requiring the capabilities of a Quad-core ARM Cortex-A55 CPU.
- The device comes with standard interfaces and connectors for external I/O, including I2C touch connector, CAN Bus, LVDS VCC switch connector, and more.
- The board supports Debian 11(Linux) or Android 12 operating systems and offers Wi-Fi/BT connectivity. It is equipped with LPDDR4 memory and eMMC storage options.
- The board features various connectors labeled for different functions such as Touch Panel Connector (J22) and DEBUG UART Connector (J20). Refer to the manual for pin definitions and usage details.
FAQ
- Q: What are the default operating systems supported by the CBD-3568-SMARC?
- A: The default operating systems supported are Global Debian 11(Linux) and Android 12.
- Q: What are the memory options available for the CBD-3568-SMARC?
- A: The board comes with 2GB LPDDR4 memory as standard, with optional configurations ranging from 1GB to 8 GB. The eMMC storage options include an 8GB base option with up to 32GB as an alternative.
- Q: What is the power requirement for the CBD-3568-SMARC?
- A: The board requires a DC input of 12V at 2A.
Revision History
| VERSION | DATE | BOARD ID | PAGE | DESCRIPTION | AUTHOR |
| V1.0 | 22/06/14 | RCB220614_V1.0 | |||
| V1.1 | 24/08/07 | RCB220614_V1.1 | |||
GENERAL DESCRIPTION
- The RK3568 SMARC Development Platform incorporates RK3568 SoC-based SOM-3568-SMARC and CBD-3568-SMARC Carrier board for complete validation of RK3568 SoC functionality.
- The Development board CBD-3568-SMARC can be used for quick prototyping of various applications targeted by the RK3568 Applications Processor.
- With the 170mmx138mm size, the SMARC Carrier board is highly packed with all the necessary on-board connectors to validate the features of SOM-3568-SMARC.
- With the high SOC performance, applications focusing on smart NVR, cloud terminal, industrial automation, Internet of Things applications, commercial display, and other fields.
PRODUCT OVERVIEW
- The below picture is for reference only, please prevail in kind.
FEATURES
Connectors List
| Label | Function | Note |
| J31 | Speaker connector | 4x 1 wafer, pitch 2.00mm |
| J30 | HP Jack connector | |
| MIC1 | MIC Connector | 2×1 wafer, pitch 2.00mm |
| J24 | RJ-45 Ethernet | |
| J25 | RJ-45 Ethernet(Support POE) | |
| J27 | Micro SD slot | |
| J35 | SIM Card slot | |
| J18 | POE-IN Connector | |
| J19 | POE-12V Connector | |
| J28 | USB2.0-Type A connector | |
| J26 | USB3.0-Type A connector | OTG |
| J23 | HDMI out Connector | |
| J29 | DC-IN Jack | |
| SW6 | RESET KEY | |
| JRTC1 | RTC Battery connector | |
| J22 | Touch Panel connector | 6 x 1 wafer, pitch 2.00mm |
| J20 | Debug connector (UART) | 4 x 1 wafer, pitch 2.00mm |
| J9 | LVDS_PANELVCC SWITCH CONNECTOR | 2 x 3 HDR, pitch 2.00mm |
| J11 | LVDS connector | 2 x 15 HDR, pitch 2.00mm |
| J36 | GPIO connector | 6 x 1 wafer, pitch 2.00mm |
| J10 | eDP Connector | 2 x 10 HDR, pitch 2.00mm |
| J8 | eDP_PANELVCC SWITCH CONNECT | 2 x 3 HDR, pitch 2.00mm |
| LCD1 | Single- MIPI1 LCM Connector | FPC 34 Pin, pitch 0.5mm |
| J3 | SATA Power Connector | SATA_IDE_DIP_4Pin |
| J1 | LVDS backlight connector | 6 x 1 wafer, pitch 2.00mm |
| J4 | eDP backlight connector | 6 x 1 wafer, pitch 2.00mm |
| SW1 | RECOVERY KEY | |
| SW4 | PWR_ON/OFF KEY | |
| IR1 | IR Receiver | |
| J2 | SATA3.0 connector | |
| J33 | PCIe M.2 KEY M for Storage | |
| J6 | mini PCIe Connector | |
| J32 | PCIe M.2 KEY B connector | |
| J5 | USB2.0 slot | 4 x 1 wafer, pitch 2.00mm |
| J7 | USB2.0 slot | 4 x 1 wafer, pitch 2.00mm |
| J37 | GPIO connector | 10 x 2 wafer, pitch 2.00mm |
| J16 | SMARC connector |
Touch Panel Connector (J22)
| Pin NO | Definition |
| 1 | VCC3V3_TP |
| 2 | TP_RST |
| 3 | TP_INT |
| 4 | I2C_SDA_TP |
| 5 | I2C_SCL_TP |
| 6 | GND |
DEBUG UART Connector (J20)
| Pin NO | Definition |
| 1 | UART2_RX_M0_DEBUG_3V3 |
| 2 | GND |
| 3 | UART2_TX_M0_DEBUG_3V3 |
| 4 | NC |
General purpose I/O connector (J37)
| Pin NO | Definition | Pin NO | Definition |
| 1 | VCC5V0_SYS | 2 | VCC3V3_SYS |
| 3 | VCC5V0_SYS | 4 | VCC3V3_SYS |
| 5 | GND | 6 | GND |
| 7 | UART7_TX_M1_3V3 | 8 | GPIO4_C5 |
| 9 | UART7_RX_M1_3V3 | 10 | GPIO4_C6 |
| 11 | GPIO3_B2 | 12 | NA |
| 13 | GPIO3_B1 | 14 | NA |
| 15 | NA | 16 | NA |
| 17 | GND | 18 | GND |
| 19 | GND | 20 | GND |
LVDS/DSI Connector (J11)
| Pin NO | Definition | Pin NO | Definition |
| 1 | LVDS_PANELVCC | 2 | LVDS_PANELVCC |
| 3 | LVDS_PANELVCC | 4 | GND |
| 5 | GND | 6 | GND |
| 7 | MIPI_DSI_TX0_D0N/LVDS_TX0_D0N | 8 | MIPI_DSI_TX0_D0P/LVDS_TX0_D0P |
| 9 | MIPI_DSI_TX0_D1N/LVDS_TX0_D1N | 10 | MIPI_DSI_TX0_D1P/LVDS_TX0_D1P |
| 11 | MIPI_DSI_TX0_D2N/LVDS_TX0_D2N | 12 | MIPI_DSI_TX0_D2P/LVDS_TX0_D2P |
| 13 | GND | 14 | GND |
| 15 | MIPI_DSI_TX0_CLKN/LVDS_TX0_CLKN | 16 | MIPI_DSI_TX0_CLKP/LVDS_TX0_CLKP |
| 17 | MIPI_DSI_TX0_D3N/LVDS_TX0_D3N | 18 | MIPI_DSI_TX0_D3P/LVDS_TX0_D3P |
| 19 | NC | 20 | NC |
| 21 | NC | 22 | NC |
| 23 | NC | 24 | NC |
| 25 | GND | 26 | GND |
| 27 | NC | 28 | NC |
| 29 | NC | 30 | NC |
eDP Connector (J10)
| Pin NO | Definition | Pin NO | Definition |
| 1 | EDP_PANELVCC | 2 | EDP_PANELVCC |
| 3 | GND | 4 | GND |
| 5 | EDP_TX_D0N | 6 | EDP_TX_D0P |
| 7 | EDP_TX_D1N | 8 | EDP_TX_D1P |
| 9 | EDP_TX_D2N | 10 | EDP_TX_D2P |
| 11 | EDP_TX_D3N | 12 | EDP_TX_D3P |
| 13 | GND | 14 | GND |
| 15 | EDPTX_AUXN | 16 | EDPTX_AUXP |
| 17 | GND | 18 | GND |
| 19 | EDP_HPD | 20 | VCC3V3_LCD0 |
LVDS_PANELVCC SWITCH CONNECTOR(J9)
| Pin NO | Definition | Pin NO | Definition |
| 1 | VCC12V_DCIN | 2 | LVDS_PANELVCC |
| 3 | VCC5V0_SYS | 4 | LVDS_PANELVCC |
| 5 | VCC3V3_SYS | 6 | LVDS_PANELVCC |
eDP_PANELVCC SWITCH CONNECTOR(J8)
| Pin NO | Definition | Pin NO | Definition |
| 1 | VCC12V_DCIN | 2 | eDP_PANELVCC |
| 3 | VCC5V0_SYS | 4 | eDP_PANELVCC |
| 5 | VCC3V3_SYS | 6 | eDP_PANELVCC |
SATA Power Connector (J3)
| Pin NO | Definition |
| 1 | VCC5V0_SYS |
| 2 | GND |
| 3 | GND |
| 4 | VCC12V_DCIN |
MIPI-DSI FPC34 Connector (LCD1)
| Pin NO | Definition | Pin NO | Definition |
| 1 | VCC3V3_LCD0 | 19 | MIPI_DSI_TX1_D0P_SOC |
| 2 | VCC3V3_LCD0 | 20 | MIPI_DSI_TX1_D0N_SOC |
| 3 | NC | 21 | GND |
| 4 | EDP_BL_ON | 22 | MIPI_DSI_TX1_D3P_SOC |
| 5 | LCD1_BL_PWM_5 | 23 | MIPI_DSI_TX1_D3N_SOC |
| 6 | I2C3_SDA_M_0 | 24 | GND |
| 7 | I2C3_SCL_M_0 | 25 | GND |
| 8 | NC | 26 | GND |
| 9 | GND | 27 | GND |
| 10 | MIPI_DSI_TX1_D2P_SOC | 28 | TP1 |
| 11 | MIPI_DSI_TX1_D2N_SOC | 29 | TP2 |
| 12 | GND | 30 | NC |
| 13 | MIPI_DSI_TX1_D1P_SOC | 31 | VCC5V0_SYS |
| 14 | MIPI_DSI_TX1_D1N_SOC | 32 | VCC5V0_SYS |
| 15 | GND | 33 | VCC5V0_SYS |
| 16 | MIPI_DSI_TX1_CLKP_SOC | 34 | VCC5V0_SYS |
| 17 | MIPI_DSI_TX1_CLKP_SOC | ||
| 18 | GND |
LCD backlight connector (J1)
| Pin NO | Definition |
| 1 | VCC12V_DCIN |
| 2 | VCC12V_DCIN |
| 3 | LVDS_BL_ON |
| 4 | LCD0_BL_PWM_4 |
| 5 | GND |
| 6 | GND |
eDP backlight connector (J4)
| Pin NO | Definition |
| 1 | VCC12V_DCIN |
| 2 | VCC12V_DCIN |
| 3 | EDP_BL_ON |
| 4 | LCD1_BL_PWM_5 |
| 5 | GND |
| 6 | GND |
USB2.0 Slot (J5 & J7)
| J5 | J7 | ||
| Pin NO | Definition | Pin NO | Definition |
| 1 | VCC5V0_USB | 1 | VCC5V0_USB |
| 2 | USB2_HUB_DM_3 | 2 | USB2_HUB_DM_4 |
| 3 | USB2_HUB_DP_3 | 3 | USB2_HUB_DP_4 |
| 4 | GND | 4 | GND |
SPEAKER & MIC Connector (J31 & MIC1)
| J31 | MIC1 | ||
| Pin NO | Definition | Pin NO | Definition |
| 1 | SPKR_LN_CONN | 1 | LIN2 |
| 2 | SPKR_LP_CONN | 2 | RIN2 |
| 3 | SPKR_RN_CONN | ||
| 4 | SPKR_RP_CONN | ||
POE IN Connector (J18)
| Pin NO | Definition |
| 1 | TR0_TAP |
| 2 | TR1_TAP |
| 3 | TR2_TAP |
| 4 | TR3_TAP |
POE12V OUT connector(J19)
| Pin NO | Definition |
| 1 | VCC12V_POE |
| 2 | VCC12V_POE |
| 3 | GND |
| 4 | GND |
MIPI-CSI Camera Connector (J34)
| Pin NO | Definition | Pin NO | Definition |
| 1 | GND | 16 | GND |
| 2 | MIPI_CSI_RX_D0P | 17 | VCC2V8_AVDD_DVP0 |
| 3 | MIPI_CSI_RX_D0N | 18 | VCC2V8_DVP0 |
| 4 | GND | 19 | GND |
| 5 | MIPI_CSI_RX_D2P | 20 | I2C2_SCL_M1 |
| 6 | MIPI_CSI_RX_D2N | 21 | I2C2_SDA_M1 |
| 7 | GND | 22 | VDD1V2_DVDD_DVP0 |
| 8 | MIPI_CSI_RX_D3P | 23 | GND |
| 9 | MIPI_CSI_RX_D3N | 24 | VCC1V8_DOVDD_DVP0 |
| 10 | GND | 25 | GND |
| 11 | CIF_CLKOUT | 26 | MIPI_CSI_RX_D1N |
| 12 | MIPI_CSI_X4_RST | 27 | MIPI_CSI_RX_D1P |
| 13 | GND | 28 | GND |
| 14 | MIPI_CAM0_PDN_L_GPIO3_D5 | 29 | MIPI_CSI_RX_CLK0P |
| 15 | GND | 30 | MIPI_CSI_RX_CLK0N |
Multimedia
Video
Video Decoder
- H.265 HEVC/MVC Main10 Profile yuv420@L5.1 up to 4096×2304@60fps
- H.264 AVC/MVC Main10 Profile yuv400/yuv420/yuv422/@L5.1 up to 4096×2304@60fps
- VP9 Profile0/2 yuv420@L5.1 up to 4096×2304@60fps
- VP8 verision2, up to 1920×1088@60fps
- VC1 Simple Profile@low, medium, high levels, Main Profile@low, medium, high levels, Advanced
- Profile@level0~3, up to 1920×1088@60fps
- MPEG-4 Simple Profile@L0~6, Advanced Simple Profile@L0~5, up to 1920×1088@60fps
- PEG-2 Main Profile, low, medium, and high levels, up to 1920×1088@60fps
- MPEG-1 Main Profile, low, medium, and high levels, up to 1920×1088@60fps
- H.263 Profile0, levels 10-70, up to 720×576@60fps
Video Encoder
- H.264/AVC BP/MP/HP@level4.2, up to 1920×1080@60fps
- H.265/HEVC MP@level4.1, up to 1920×1080@60fps (4096×4096@10fps with TILE)
- Support YUV/RGB video source with rotation and mirror
JPEG CODEC
JPEG decoder
- JPEG Baseline interleaved, max resolution up to 8176×8176, performance up to 76 million pixels per second
JPEG encoder
- Baseline Non-progressive
- up to 90 million pixels per second
Display System
Graphics Engine
3D Graphics Engine:
- Mali-G52 1-Core-2EE
- Support OpenGL ES 1.1, 2.0, and 3.2
- Support Vulkan 1.0 and 1.1
- Support OpenCL 2.0 Full Profile
- Support 1600Mpix/s fill rate when 800MHz clock frequency
- Support 38.4GLOPs when 800MHz clock frequency
2D Graphics Engine:
Data format
- Support input of ARGB/RGB888/RGB565/RGB4444/RGB5551/YUV420/YUV422/YUYV；
- Support input of YUV422SP10bit/YUV420SP10bit(YUV-8bits out)
- Supports output of ARGB/RGB888/RGB565/RGB4444/RGB5551/YUV420/YUV422/YUYV；
- Pixel Format conversion, BT.601/BT.709
- Dither operation, Y dither update;
- Max resolution: 8192×8192 source, 4096×4096 destination
Display interface
Display interface
- Supports RGB Parallel Display interface
- Supports BT656/BT1120 interface
- Supports MIPI_DSI interface
Support LVDS interface - Supports HDMI interface
- Supports eDP interface
- Supports EBC interface
- Supports three simultaneous displays in the following interfaces RGB/BT1120
- BT656
- MIPI_DSI_TX
- LVDS
- HDMI
- Edp
MIPI DSI TX interface
- Compatible with MIPI Alliance Interface specification v1.2
- Supports 2-channel DSI
- Supports 4 data lanes per channel
- Supports 2.5Gbps maximum data rate per lane
- Up to 1920×1080@60Hz display output for single MIPI mode and 2560*1440@60Hz for dual-MIPI mode
- Supports RGB(up to 8bit) format
LVDS interface
- Compliant with the TIA/EIA-644-A LVDS specification
- Supports RGB888 and RGB666 input for LVDS interface
- Supports VESA/JEIDA LVDS data format transfer
HDMI TX interface
- Single Physical Layer PHY with support for HDMI1.4 and HDMI2.0 operation
- For HDMI operation, support for the following:
- Up to 10 bits of Deep Color modes
- Up to 1080p@120Hz and 4096×2304@60Hz
- 3-D video formats
- Supports RGB/YUV(up to 10bit) format
- Supports HDCP1.4/2.2
eDP interface
- Supports 1 eDP 1.3 interface
- Up to 4 physical lanes of 2.7Gbps/lane
- Supports Panel Self Refresh(PSR)
- Supports up to 2560×1600@60Hz
- Supports RGB(up to 10bit) format
Precautions for use
- Relative humidity: ≤80%.
- Operation temperature: Commercial field ：0~ 65C； Industrial field: -0~85C
- Keep the Board away from static electricity.
- Keep the Board away from water and other liquids.
- Don’t use long connect wires which may affect performance and image quality.
FCC Statement
This equipment has been tested and found to comply with the limits for a Class B digital device, under part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used by the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
- Reorient or relocate the receiving antenna.
- Increase the separation between the equipment and the receiver.
- Connect the equipment to an outlet on a circuit different from that to which the receiver is connected.
- Consult the dealer or an experienced radio/TV technician for help.
Caution: Any changes or modifications to this device not explicitly approved by the manufacturer could void your authority to operate this equipment.
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions:
- This device may not cause harmful interference, and
- this device must accept any interference received, including interference that may cause undesired operation.
RF Exposure Information
This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20cm between the radiator and your body.
CONTACT
- Room 02-04, 10/F, Block A, Building 8, Shenzhen International Innovation Valley, Dashi Road,
- Nanshan District, Shenzhen, Guangdong, China
- Email:support@geniatech.com Tel: (+ 86) 755 86028588
Documents / Resources
 |
Geniatech SOM3568SMARC Smart Module [pdf] Owner's Manual SOM3568SMARC, SOM3568SMARC Smart Module, Smart Module, Module |
