DIODES PI4IOE5V6408 Low Voltage 8-Bit I2C-Bus I-O Expander Owner's Manual

Contents hide

1 PI4IOE5V6408 Low Voltage 8-Bit I2C-Bus I-O Expander

2 Specifications

3 Product Usage Instructions

3.1 Connection

3.2 Configuration

3.3 Interrupt Feature

4 Frequently Asked Questions (FAQ)

4.1 Q: What is the operating voltage range for the PI4IOE5V6408?

4.2 Q: How can I configure the I/Os on the PI4IOE5V6408?

4.3 Q: What is the purpose of the open-drain interrupt output pin?

4.4 Documents / Resources

4.4.1 References

PI4IOE5V6408 Low Voltage 8-Bit I2C-Bus I-O Expander

Specifications

Product Name: PI4IOE5V6408

Type: Low-voltage Translating 8-bit I2C-bus I/O Expander
Operation Power Supply Voltage: 1.65V to 4.0V

GPIO-port Voltage Range: 1.65V to 4.0V
SDA/SCL Voltage Range: 1.65V to 3.6V

Features: Bidirectional voltage-level translation, I2C-bus
interface, open-drain interrupt output pin

Product Usage Instructions

Connection

1. Connect VDD(I2C_bus) to the VDD of the external SCL/SDA
lines.

2. Determine the voltage level on the GPIO-port by connecting
VDD(P) accordingly.

Configuration

1. At power on, I/Os are configured as inputs.

2. The system master can enable I/Os as inputs or outputs by
writing to the I/O direction bits.

3. Data for each input or output is stored in the corresponding
Input or Output register.

Interrupt Feature

The device has an open-drain interrupt (INT) output pin that
goes LOW when the input state of a GPIO-port changes from the
default register value.

Users can mask interrupts from individual GPIO-ports using the
interrupt masking feature.

Frequently Asked Questions (FAQ)

Q: What is the operating voltage range for the
PI4IOE5V6408?

A: The PI4IOE5V6408 can operate from 1.65V to 4.0V on the
GPIO-port side and 1.65V to 3.6V on the SDA/SCL side.

Q: How can I configure the I/Os on the PI4IOE5V6408?

A: The system master can enable the I/Os as either inputs or
outputs by writing to the I/O direction bits.

Q: What is the purpose of the open-drain interrupt output
pin?

A: The INT pin goes LOW when the input state of a GPIO-port
changes from the default register value, providing an interrupt
indication.

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PI4IOE5V6408

Low-voltage Translating 8-bit I2C-bus I/O Expander

Features

Description

Operation power supply voltage from 1.65V to 4.0V Allows bidirectional voltage-level translation and
GPIO expansion between: 1.8V SCL/SDA and 1.8V, 2.5V, 3.3V Port P 2.5V SCL/SDA and 1.8V, 2.5V, 3.3V Port P 3.3V SCL/SDA and 1.8V, 2.5V, 3.3V Port P Low standby current consumption: 1.5 A typical at 3.3 V VDD 1MHz I2C-bus interface Compliant with the I2C-bus Fast and Standard modes Programmable Pull-up/Pull-down Resistors for GPIO Inputs Software Reset Active LOW open-drain interrupt output Low standby current Latch-up tested (exceeds 100mA) Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Halogen and Antimony Free. “Green” Device (Note 3) For automotive applications requiring specific change control (i.e. parts qualified to AEC-Q100/101/104/200, PPAP capable, and manufactured in IATF 16949 certified facilities), please contact us or your local Diodes representative. https://www.diodes.com/quality/product-definitions/ Packaging (Pb-free & Green): 16-Pin, UQFN1.8 x2.6

The DIODESTM PI4IOE5V6408 is an 8-bit general-purpose I/O expander that provides remote I/O expansion for most microcontroller families via the I2C-bus interface. It provides a simple solution when additional I/Os are needed while keeping interconnections to a minimum, for example, in battery-powered mobile applications for interfacing to sensors, push buttons, keypad, etc.
It can operate from 1.65V to 4V on the GPIO-port side and 1.65V to 3.6V on the SDA/SCL side. This allows the PI4IOE5V6408 to interface with next generation microprocessors and microcontrollers on the SDA/SCL side, where supply levels are dropping down to conserve power.
The bidirectional voltage-level translation in the PI4IOE5V6408 is provided through V . DD(I2C_bus) VDD(I2C_bus) should be connected to the VDD of the external SCL/SDA lines. The voltage level on the GPIO-port of the PI4IOE5V6408 is determined by VDD(P) .
At power on, the I/Os are configured as inputs; however, the system master can enable the I/Os as either inputs or outputs by writing to the I/O direction bits. The data for each input or output is kept in the corresponding Input or Output register. All registers can be read by the system master.
The PI4IOE5V6408 has open-drain interrupt (INT) output pin that goes LOW when the input state of a GPIO-port changes from the input-state default register value. The device also has an interrupt masking feature by which the user can mask the interrupt from an individual GPIO-port.

Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant. 2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, “Green” and Lead-free. 3. Halogen- and Antimony-free “Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000ppm antimony compounds. DIODES is a trademark of Diodes Incorporated in the United States and other countries. The Diodes logo is a registered trademark of Diodes Incorporated in the United States and other countries.

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Pin Configuration

PI4IOE5V6408

Figure 1. UQFN Top View

Pin Description

Pin# Pin Name

INT

VDD(P)

ADDR

10 RESET

SCL

SDA

VDD(I2C_bus)

GND

Description
Active-low interrupt output. Connect to VDD(I2C_bus) through a pull-up resistor.
Supply voltage of PI4IOE5V6408 GPIO-port GPIO-port input/output (push-pull design structure). At power on, P7 is configured as an input. GPIO-port input/output (push-pull design structure). At power on, P6 is configured as an input. GPIO-port input/output (push-pull design structure). At power on, P5 is configured as an input. GPIO-port input/output (push-pull design structure). At power on, P4 is configured as an input. GPIO-port input/output (push-pull design structure). At power on, P3 is configured as an input. GPIO-port input/output (push-pull design structure). At power on, P2 is configured as an input. Address input. Connect directly to VDD(I2C_bus) or ground. Active-low reset input. Connect to VDD(I2C_bus) through a pull-up resistor, if no active connection is used. GPIO-port input/output (push-pull design structure). At power on, P1 is configured as an input. GPIO-port input/output (push-pull design structure). At power on, P0 is configured as an input. Serial clock bus. Connect to VDD(I2C_bus) through a pull-up resistor. Serial data bus. Connect to VDD(I2C_bus) through a pull-up resistor. Supply voltage of I2C bus. Ground

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Maximum Ratings

Power supply ……………………………………………………………………………………….. -0.5V to +4.6V Voltage on an I/O pin (Input / Output)…………………………………………………. -0.5V to +4.0V Input current …………………………………………………………………………………………………….. ±20mA Output current on an I/O pin …………………………………………………………………………… ±50mA Supply current…………………………………………………………………………………………………±100mA Ground supplycurrent……………………………………………………………………………………±100mA Operation temperature …………………………………………………………………………………..-40~85 Storage temperature …………………………………………………………………………………… -65~150 Maximumjunction temperature,Tj (max) ………………………………………………………..125 ESD (HBM) ………………………………………………………………………………………………………….2kV

Recommended Operating Conditions

Symbol Parameter

Conditions

VDD(I2C-bus) I2C-bus supply voltage

VDD(P)

GPIO port supply voltage

VIN

Input voltage on IO pins

VOUT

Output Voltage

PI4IOE5V6408

Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Min. Typ. Max. Unit

1.65

–

3.6

1.65

–

VDD(P)

Static Characteristics

VDD(I2C_bus) = 1.8 V to 3.6 V; GND = 0 V; Temp = -40 °C to +85 °C; unless otherwise specified. Typical values are at Temp = 25 °C.

Symbol Parameter

Condition

Min. Typ.[1] Max.

Unit

Power Supply

VDD(I2C_bus) = 1.8 to 3.6 V; Standby mode

IDD[2]

Supply current

VI on SDA, ADDR and RESET =

VDD(I2C-bus) or GND; VI on P port = VDD(P)

–

or GND; IO = 0 mA; I/O = inputs; fSCL =

0 kHz

VDD(I2C_bus) = 1.8 to 3.6 V; Active mode

1.2

1.5

VI on RESET = VDD(I2C-bus); VI on P

port = VDD(P) or GND; IO = 0 mA; I/O =

–

inputs; fSCL = 400 kHz, continuous

–

300

IOFF

Power off leakage current

–

IIN

Input leakage current

0 VIN VDD(I2C_bus)

-10

–

VPOR

Power-on reset voltage

–

1.25

Input SCL, input/output SDA

VIL

Low level input voltage

VIH

High level input voltage

IOL

Low level output current

Leakage current

VOL = 0.4 V VIN = VDD(I2C_bus) or GND

0.3

-0.5

–

VDD(I2C-

0.7

VDD(I2C-

–

bus)

3.6

bus)

–

-10

–

Input capacitance

VIN = GND

–

Interrupt INT

IOL

Low level output

VOL=0.4V

–

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PI4IOE5V6408

Symbol Parameter current

Condition

Min. Typ.[1] Max.

Unit

Output capacitance

2.1

Select inputs ADDR and RESET

VIL

Low level input voltage

VIH

High level input voltage

Input leakage current

Input capacitance

0.3

-0.5

–

VDD(I2C-

0.7

VDD(I2C-

–

bus)

3.6

bus)

-1

2.4

I/Os

VIL

Low-level input voltage

VIH

High-level input voltage

P0 P7 P0 P7 P port; IOH = -100 A;

-0.5

–

+0.3*VD

D(P)

0.7*VDD

–

4.0

(P)

VDD(P) = 1.8 V

VDD(P) 0.2

–

VDD(P) = 3.6 V

VDD(P) 0.2

–

VOH

High-level output voltage

VDD(P) = 4.0 V

VDD(P) 0.2

–

P port; IOH = -6 mA

VDD(P) = 1.8 V

VDD(P) 0.2

–

VDD(P) = 3.6 V

VDD(P) 0.2

–

P port; IOL = 100 A;

VDD(P) = 1.8 V

–

0.2

VOL

Low-level output voltage

VDD(P) = 3.6 V VDD(P) = 4.0 V P port; IOL = 6 mA

–

0.2

–

0.2

VDD(P) = 1.8 V

–

0.5

VDD(P) = 3.6 V

–

0.45

IOL

Low-level output current

P0 P7

6.0

–

IOH

High-level output current

P0 P7

-6.0

–

IIH

High-level input current

P port; VI = VDD(P); VDD(P) = 1.65 V to 4.0 V

-50

–

IIL

Low-level input current

P port; VI = GND; VDD(P) = 1.65 V to 4.0 V

-50

–

Rpu(int)

Internal pull-up resistance

Input/Output

–

100

–

Rpd(int)

Internal pull-down resistance

Input/Output

–

100

–

Note:

1. Includes all internal circuitry consumption from the VDD(I2C_bus) supply. Does not include the I/O buffers, which are supplied by VDD(P) and are load dependent.

2. IIL and IIH specifications only apply when the outputs are configured with pull-down or pull-up resistors, respectively. Specification value assume VIN
VDD(P)

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PI4IOE5V6408

Dynamic Characteristics

Symbol

Parameter

Standard mode I2C
Min Max

fSCL tBUF tHD;STA tSU;STA tSU;STO tVD;ACK[1] tHD;DAT[2]

SCL clock frequency
Bus free time between a STOP and START condition Hold time (repeated) START condition Set-up time for a repeated START condition
Set-up time for STOP condition
Data valid acknowledge time
Data hold time

100

4.7

–

4.0

–

4.7

–

4.0

–

3.45

–

tVD;DAT

Data valid time

–

3.45

tSU;DAT

Data set-up time

250

–

tLOW

LOW period of the SCL clock

4.7

–

tHIGH

HIGH period of the SCL clock

4.0

–

Fall time of both SDA and SCL signals

–

300

Rise time of both SDA and SCL signals

–

1000

Pulse width of spikes that must

tSP

–

suppressed by the input filter

Interrupt Timing

tV(INT)

Valid time on pin INT

–

Reset Timing

tw(rst) trst_glitch

Reset pulse width Reset recovery time[4]

150

–

150

trst

Reset time

–

150

Note: 1. tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW. 2. tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.

Fast mode I2C

Min Max

400

1.3

–

0.6

–

0.6

–

0.6

–

0.9

–

0.9

100

–

1.3

–

0.6

–

300

–

150

–

150

–

150

Fast mode Plus I2C

Unit

Min

Max

1000 kHz

0.5

–

0.26

–

0.26

–

0.26

–

0.45

–

0.45

–

0.5

–

0.26

–

120

–

120

–

150

–

150

–

150

/RESET

Figure 2: Reset Pulse Duration and Input Glitch Rejection Timing Diagram

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/RESET /INT

PI4IOE5V6408

Figure 3: Reset Pulse Duration and Input Glitch Rejection Timing Diagram

/INT
Figure 4: Time to INT from Change in Input Default State

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PI4IOE5V6408 Block Diagram

PI4IOE5V6408

VDDI2C-BUS

Note: All I/Os are set to inputs at reset.

Figure 5: Block Diagram

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PI4IOE5V6408

Functional Description

a. Device Address
The address of the device is shown below in Table 5. Setting ADDR pin to GND (0) results in B[3:1] bits set as 011, and setting ADDR pin to VDD(I2C_bus) (1) results in B[3:1] bits set as 100.

Table 1: Device Address

ADDR B7 ( MSB )

R / W

The last bit of the device address defines the operation to be performed. A logic 1 selects a read operation, while a logic 0 selects a write operation.

b. Register Map
Following the successful acknowledgment of the address byte, the bus master sends a command byte, which is stored in the Pointer Register in the PI4IOE5V6408. Five bits of this data byte state the operation (read or write) and the internal registers that will be affected. This register can be written or read through the I2C bus. The command byte is sent only during a write transmission.

Table 2: Register Map

Pointer Register Bits

Command bye

B7 B6 B5 B4 B3 B2 B1 B0 (hexadecimal )

Protocol

Power-up default

00 000001

01h

Device ID and Control

R/W 1010 0010

00 000011

03h

I/O Direction

R/W 0000 0000

00 000101 00 000111

05h

Output State

07h

Output Highimpedance

R/W 0000 0000 R/W 1111 1111

00 001001

09h

Input Default State

R/W 0000 0000

00 001011

0Bh

Pull-up/down Enable

R/W 1111 1111

00 001101

0Dh

Pull-up/down Select

R/W 0000 0000

00 001111

0Fh

Input Status

xxxx xxxx

00 010001

11h

Interrupt Mask

R/W 0000 0000

00 010011

13h

Interrupt Status

02h, 04h, 06h, 08h, 0Ah, 0Ch, Reserved OEh, 10h, 12h

R/W xxxx xxxx R/W

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PI4IOE5V6408

c. Register Descriptions
i. Register 01h : Device ID and Control
The Device ID and Control register contains the manufacturer ID and firmware revision. The Control register indicates whether the device has been reset and the default values have been set.
The Reset Interrupt is set B1 = 1 when the device is either reset by the RESET pin, a power on reset, or software reset.
Reset Interrupt is then cleared after being read by the master. A software reset is issued when the master writes B0=1. When reading from B0, the value read will always be 0.

Table 3: Device ID and Control register (address 01h)

Bit

Name

Manufacture ID

Firmware Revision

Default

B1 Reset interrupt
1

B0 Software
reset
R / W

ii. Register 03h : I/O Direction
The I/O Direction Register configures the direction of the I/O pins. If a bit in this register is set to 0, the corresponding port pin is enabled as an input If a bit in this register is set to 1, the corresponding port pin is enabled as an output.

Table 4: I/O Direction register (address 03h)

Bit

Name

Default

iii. Register 05h : Output Port Register
The Output Port Register sets the outgoing logic levels of the pins defined as outputs. When Bx is set to 0, Px = L;When Bx is set to 1, Px = H Bit values in this register have no effect on pins defined as inputs Reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.

Table 5: Output Port Register (address 05h)

Bit

Name

Default

iv. Register 07h : Output High-Impedance
The Output High-Impedance Register determines whether pins set as output are enabled or high-impedance When a bit in this register is set to 0, the corresponding GPIO-port output state follows register the output port register (05h). When a bit in this register is set to 1, the corresponding GPIO-port output is set to high-impedance. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.

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PI4IOE5V6408

Table 6: Output High-Impedance Register (address 07h)

Bit

Name

Default

v. Register 09h : Input Default State
The Input Default State Register sets the default state of the GPIO-port input for generating interrupts. When a bit in this register is set to 0, the default for the corresponding input is set to LOW When a bit in this register is set to 1, the default for the corresponding input is set to HIGH Bit values in this register have no effect on pins defined as outputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the default state, not the actual pin value.

Table 7. Input Default State Register (address 09h)

Bit

Name

Default

vi. Register 0bh : Pull-Up/-Down Enable
The Pull-up/-down Enable Register enables or disables the pull-up/down resistor on the GPIO-port as defined in the Pullup /-down Select Register (0Dh).
When a bit in this register is set to 0, the pull-up/down on the corresponding GPIO is disabled. When a bit in this register is set to 1, the pull-up/down on the corresponding GPIO is enabled.

Table 8. Pull-up/-down Enable Register (address 0Bh)

Bit

Name

Default

vii. Register 0Dh : Pull-Up/-Down Select
The Pull-up/down Select Register allows the user to select either a pull-up or pull-down on the GPIO-port. This register only selects the pull-up/down resistor on the GPIO-port, while the enabling/disabling is controlled by the Pull-up/down Enable Register (0Bh).
When a bit in this register is set to 0, the pull-down on the corresponding GPIO is selected. When a bit in this register is set to 1, the pull-up on the corresponding GPIO is selected.

Table 9. Pull-up/-down Select Register (address 0Dh)

Bit

Name

Default

viii. Register 0Fh : Input Status Register
The Input Status Register reflects the incoming logic levels of the GPIOs set as inputs. The default value, X, is determined by the externally applied logic level. It only acts on read operation. Attempted writes to this register have no effect. For GPIOs set as outputs this register will read LOW.

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Table 10. Input Status Register (address 0Fh)

Bit

Name

Default

ix. Register 11h Interrupt Mask Register
The Interrupt Mask Register controls the generation of an interrupt to the INT pin when the GPIO-port input state changes state.
When a bit in this register is set to 0, an interrupt generated by the interrupt status register causes the INT pin to be asserted LOW.
When a bit in this register is set to 1, the interrupt for the corresponding GPIO is disabled. The corresponding bit in the Interrupt Status Register (13h) will still be asserted.
INT is not affected when GPIO-port is defined as outputs.

Table 11. Interrupt Mask Register (address 11h)

Bit

Name

Default

x. Register 13h Interrupt Status Register
The Interrupt Status Register bit is asserted when the bit changes to a value opposite to the default value defined in the Input Default State Register (09h).
This bit is cleared and the INT pin is de-asserted upon read of this register. The input must be asserted back to the default state before this bit is set again. If the GPIO-port pin is defined as an output, this bit is never set.

Table 12. Interrupt Status Register (address 13h)

Bit

Name

Default

d. I/O Port
When an I/O is configured as an input, the pull-up FET (Q1) and pull-down FET (Q2) are off, which creates a highimpedance input. If the I/O is configured as an output, Q1 or Q2 is enabled depending on the state of the Output Port Register. In this case, there are low impedance paths between the I/O pin and either VDD(P) or GND. The external voltage applied to this I/O pin should not exceed the recommended levels for proper operation. A pull-down FET series with pulldown resistor (Q3) is turned on at power-on to enable the pull-down resistor. Q3 and a pull-up FET series with pull-up resistor (Q4) are enabled accordingly to the Pull-up or Pull-down Select Register and the Pull-up or Pull-down Enable Register. When the GPIO-port is set as an output the input buffers are disabled such that the bus is allowed to float.

e. Power-on Reset
When power is applied to V , DD(I2C_bus) an internal power-on reset holds the PI4IOE5V6408 in a reset condition until VDD(I2C_bus) has reached VPOR . At that point, the reset condition is released and the PI4IOE5V6408 registers will initialize to their default states.

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PI4IOE5V6408
f. Reset Input (RESET)
The RESET input can be asserted to initialize the system while keeping VDD(P) at its operating level. A reset can be accomplished by holding the RESET pin low for a minimum of tW. The PI4IOE5V6408 registers are changed to their default state once RESET is low (0). Only when RESET is high (1), GPIO registers can be accessed by the I2C pin. This input requires a pull-up resistor to VDD(I2C_bus) , if no active connection is used.
g. Software Reset
The PI4IOE5V6408 can be reset by the processor using an I2C write command to change bit 0 of register 01h to a 1. Immediately following this change, the PI4IOE5V6408 resets and all register values return to their default values. In this case, the software reset bit returns to 0 as soon as the reset sequence is completed.
h. Interrupt output (INT)
The INT pin is a LOW-asserted open-drain output and requires an external pull-up resistor. The PI4IOE5V6408 signals an interrupt to the processor when an event occurs, removing the need for the processor to continuously poll the PI4IOE5V6408 registers. Immediately after detecting a change at an input, the PI4IOE5V6408 writes the corresponding bit in the input interrupt status register (13h) and asserts the INT pin by pulling it LOW. The interrupt status register bit remains HIGH until the processor reads the register and clears the bit. If the input pin remains in the non-default state after the interrupt has been serviced, a new interrupt is not generated until after the input state has first returned to its default state and changed back to its non-default state. The PI4IOE5V6408 also contains an Input Status register (0Fh) used to verify the current status of the given input at the time when the interrupt is serviced by the processor. These two registers allow the processor to determine the following information about any input every time the register map is read:
If the input state changed from the default state since the most recent register read; and The current state of the input pin. The interrupt output INT, once asserted, is held LOW until the interrupt is serviced by the processor. This means that the system uses level-sensitive interrupts. Interrupt signaling is asynchronous to the SCL signal.

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PI4IOE5V6408 I2C Read /Write Procedures
Figure 6 and Figure 7 illustrate compatible I2C write and read sequences. The PI4IOE5V6408 does not support burst read modes described in the I2C standard.
Figure 6. I2C Write Sequence
Note : if register is not specified , the master reads from the current register Figure 7. I2C Read Sequence

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Application Design-In Information

PI4IOE5V6408

Figure 8. Typical Application
The SCL and SDA pins must be tied directly to VDD(I2C_bus) because if SCL and SDA are tied to an auxiliary power supply that could be powered on while VDD(I2C_bus) is powered off, then the supply current, ICC, will increase as a result. A. Device address is configured as 86(h) or 87(h) for this example (depending on R/W bit). B. P0,P2,P4 are configured as outputs. C. P1,P3 are configured as inputs. D. P5,P6,P7 are not used.
Part Marking

PI4IOE5V6408
Document Number DS40583 Rev 3-5

www.diodes.com
14

Packaging Mechanical
16-UQFN (ZTA)

PI4IOE5V6408

For latest package info. please check: http://www.diodes.com/design/support/packaging/pericom-packaging/packaging-mechanicals-and-thermal-characteristics/

Ordering Information

Part Numbers

Package Code Package Description

PI4IOE5V6408ZTAEX

ZTA

16-Pin, 1.8×2.6mm (UQFN)

PI4IOE5V6408ZTAEX-13

ZTA

16-pin, 1.8×2.6mm, 13″ packing reel size (UQFN)

Notes:
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant. 2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free,
“Green” and Lead-free. 3. Halogen- and Antimony-free “Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl)
and <1000ppm antimony compounds. 4. I = Industrial 5. E = Pb-free and Green 6. X suffix = Tape/Reel 7. For packaging detail, go to our website at: https://www.diodes.com/assets/MediaList-Attachments/Diodes-Package-Information.pdf

PI4IOE5V6408
Document Number DS40583 Rev 3-5

www.diodes.com
15

PI4IOE5V6408
IMPORTANT NOTICE
1. DIODES INCORPORATED (Diodes) AND ITS SUBSIDIARIES MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO ANY INFORMATION CONTAINED IN THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION).
2. The Information contained herein is for informational purpose only and is provided only to illustrate the operation of Diodes’ products described herein and application examples. Diodes does not assume any liability arising out of the application or use of this document or any product described herein. This document is intended for skilled and technically trained engineering customers and users who design with Diodes’ products. Diodes’ products may be used to facilitate safety-related applications; however, in all instances customers and users are responsible for (a) selecting the appropriate Diodes products for their applications, (b) evaluating the suitability of Diodes’ products for their intended applications, (c) ensuring their applications, which incorporate Diodes’ products, comply the applicable legal and regulatory requirements as well as safety and functional-safety related standards, and (d) ensuring they design with appropriate safeguards (including testing, validation, quality control techniques, redundancy, malfunction prevention, and appropriate treatment for aging degradation) to minimize the risks associated with their applications.
3. Diodes assumes no liability for any application-related information, support, assistance or feedback that may be provided by Diodes from time to time. Any customer or user of this document or products described herein will assume all risks and liabilities associated with such use, and will hold Diodes and all companies whose products are represented herein or on Diodes’ websites, harmless against all damages and liabilities.
4. Products described herein may be covered by one or more United States, international or foreign patents and pending patent applications. Product names and markings noted herein may also be covered by one or more United States, international or foreign trademarks and trademark applications. Diodes does not convey any license under any of its intellectual property rights or the rights of any third parties (including third parties whose products and services may be described in this document or on Diodes’ website) under this document.
5. Diodes’ products are provided subject to Diodes’ Standard Terms and Conditions of Sale (https://www.diodes.com/about/company/terms-and-conditions/terms-and-conditions-of-sales/) or other applicable terms. This document does not alter or expand the applicable warranties provided by Diodes. Diodes does not warrant or accept any liability whatsoever in respect of any products purchased through unauthorized sales channel.
6. Diodes’ products and technology may not be used for or incorporated into any products or systems whose manufacture, use or sale is prohibited under any applicable laws and regulations. Should customers or users use Diodes’ products in contravention of any applicable laws or regulations, or for any unintended or unauthorized application, customers and users will (a) be solely responsible for any damages, losses or penalties arising in connection therewith or as a result thereof, and (b) indemnify and hold Diodes and its representatives and agents harmless against any and all claims, damages, expenses, and attorney fees arising out of, directly or indirectly, any claim relating to any noncompliance with the applicable laws and regulations, as well as any unintended or unauthorized application.
7. While efforts have been made to ensure the information contained in this document is accurate, complete and current, it may contain technical inaccuracies, omissions and typographical errors. Diodes does not warrant that information contained in this document is errorfree and Diodes is under no obligation to update or otherwise correct this information. Notwithstanding the foregoing, Diodes reserves the right to make modifications, enhancements, improvements, corrections or other changes without further notice to this document and any product described herein. This document is written in English but may be translated into multiple languages for reference. Only the English version of this document is the final and determinative format released by Diodes.
8. Any unauthorized copying, modification, distribution, transmission, display or other use of this document (or any portion hereof) is prohibited. Diodes assumes no responsibility for any losses incurred by the customers or users or any third parties arising from any such unauthorized use.
9. This Notice may be periodically updated with the most recent version available at https://www.diodes.com/about/company/terms-andconditions/important-notice
DIODES is a trademark of Diodes Incorporated in the United States and other countries. The Diodes logo is a registered trademark of Diodes Incorporated in the United States and other countries. © 2022 Diodes Incorporated. All Rights Reserved.
www.diodes.com

PI4IOE5V6408
Document Number DS40583 Rev 3-5

www.diodes.com
16

Documents / Resources

DIODES PI4IOE5V6408 Low Voltage 8-Bit I2C-Bus I-O Expander [pdf] Owner's Manual
PI4IOE5V6408, PI4IOE5V6408 Low Voltage 8-Bit I2C-Bus I-O Expander, Low Voltage 8-Bit I2C-Bus I-O Expander, 8-Bit I2C-Bus I-O Expander, I2C-Bus I-O Expander, Expander

References

User Manual

PI4IOE5V6408 Low Voltage 8-Bit I2C-Bus I-O Expander

Specifications

Product Usage Instructions

Connection

Configuration

Interrupt Feature

Frequently Asked Questions (FAQ)

Q: What is the operating voltage range for the
PI4IOE5V6408?

Q: How can I configure the I/Os on the PI4IOE5V6408?

Q: What is the purpose of the open-drain interrupt output
pin?

Documents / Resources

References

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