STM32F10xxx Power Supply Switch
Specifications
- Model: PM0056
- Website: www.st.com
Product Information
The PM0056 is a programming manual providing detailed information about the system architecture, memory model, exception handling, fault handling, and programming hints for synchronization primitives.
Product Usage Instructions
Programmers Model:
- The manual describes the processor mode, privilege levels for software execution, stacks, core registers, exceptions, and interrupts.
Memory Model:
- Details about memory regions, types, attributes, memory system ordering, behavior of memory accesses, bit-banding, memory endianness, and synchronization primitives are provided.
Exception Model:
- Information on exception states, types, handlers, vector table, priorities, interrupt priority grouping, and exception entry/return is included in the manual.
Fault Handling:
- The manual covers fault types, escalation to hard faults, fault status registers, fault address registers, and lockup scenarios.
FAQ
- Q: Where can I find more programming hints?
- A: Additional programming hints can be found in section 2.2.8 of the manual.
- Q: How can I determine fault types?
- A: Fault types and handling information are detailed in section 2.4 of the manual.
“`
PM0056 Programming manual
STM32F10xxx/20xxx/21xxx/L1xxxx Cortex®-M3 programming manual
Introduction
This programming manual provides information for application and system-level software developers. It gives a full description of the STM32F10xxx/20xxx/21xxx/L1xxxx Cortex®-M3 processor programming model, instruction set and core peripherals. The STM32F10xxx/20xxx/21xxx/L1xxxx Cortex®-M3 processor is a high performance 32-bit processor designed for the microcontroller market. It offers significant benefits to developers, including: · Outstanding processing performance combined with a fast interrupt handling · Enhanced system debug with extensive breakpoint and trace capabilities · Efficient processor core, system and memories · Ultra-low-power consumption with integrated sleep modes · Platform security
About this document
PM0056
This document provides the information required for application and system-level software development. It does not provide information on debug components, features, or operation.
This material is for microcontroller software and hardware engineers, including those who have no experience of Arm products.
1.1
Typographical conventions
The typographical conventions used in this document are:
italic < and >
Highlights important notes, introduces special terminology, denotes internal cross-references, and citations.
Enclose replaceable terms for assembler syntax where they appear in code or code fragments. For example:
LDRSB<cond> <Rt>, [<Rn>, #<offset>]
1.2
1.3
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List of abbreviations for registers
The following abbreviations are used in register descriptions:
read/write (rw) Software can read and write to these bits.
read/set (rs)
Software can read as well as set this bit. Writing `0′ has no effect on the bit value.
read-only (r)
Software can only read these bits.
write-only (w)
Software can only write to this bit. Reading the bit returns the reset value.
read/clear (rc_w1) Software can read as well as clear this bit by writing 1. Writing `0′ has no effect on the bit value.
read/clear (rc_w0) Software can read as well as clear this bit by writing 0. Writing `1′ has no effect on the bit value.
toggle (t)
Software can only toggle this bit by writing `1′. Writing `0′ has no effect.
Reserved (Res.) Reserved bit, must be kept at reset value.
About the STM32 Cortex®-M3 processor and core peripherals
The Cortex-M3 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard architecture, making it ideal for demanding embedded applications. The processor delivers exceptional power efficiency through an efficient instruction set and
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About this document
extensively optimized design, providing high-end processing hardware including singlecycle 32×32 multiplication and dedicated hardware division.
Figure 1. STM32 Cortex-M3 implementation
Debug
Serial
access
wire
port
Flash Data viewer
patch watchpoints
Code interface
Bus matrix SRAM and
peripheral interface
1.3.1
ai15994c
To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements tightly-coupled system components that reduce processor area while significantly improving interrupt handling and system debug capabilities. The Cortex-M3 processor implements a version of the Thumb® instruction set, ensuring high code density and reduced program memory requirements. The Cortex-M3 instruction set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers.
The Cortex-M3 processor closely integrates a configurable nested interrupt controller (NVIC), to deliver industry-leading interrupt performance. The NVIC includes a non-maskable interrupt (NMI), and provides up to 256 interrupt priority levels. The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the hardware stacking of registers, and the ability to suspend load-multiple and store-multiple operations. Interrupt handlers do not require any assembler stubs, removing any code overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to another.
To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep sleep function that enables the STM32 to enter STOP or STDBY mode.
System level interface
The Cortex-M3 processor provides multiple interfaces using AMBA® technology to provide high speed, low latency memory accesses. It supports unaligned data accesses and
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1.3.2 1.3.3 1.3.4
implements atomic bit manipulation that enables faster peripheral controls, system spinlocks and thread-safe Boolean data handling.
Integrated configurable debug
The Cortex-M3 processor implements a complete hardware debug solution. This provides high system visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire Debug (SWD) port that is ideal for small package devices.
For system trace the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system events these generate, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data trace, and profiling information through a single pin. The optional Embedded Trace MacrocellTM (ETM) delivers unrivalled instruction trace capture in an area far smaller than traditional trace units, enabling many low cost MCUs to implement full instruction trace for the first time.
Cortex®-M3 processor features and benefits summary
· Tight integration of system peripherals reduces area and development costs · Thumb instruction set combines high code density with 32-bit performance · Code-patch ability for ROM system updates · Power control optimization of system components · Integrated sleep modes for low power consumption · Fast code execution permits slower processor clock or increases sleep mode time · Hardware division and fast multiplier · Deterministic, high-performance interrupt handling for time-critical applications · Extensive debug and trace capabilities:
Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and tracing.
Cortex®-M3 core peripherals
These are:
Nested vectored interrupt controller
The nested vectored interrupt controller (NVIC) is an embedded interrupt controller that supports low latency interrupt processing.
System control block
The system control block (SCB) is the programmers model interface to the processor. It provides system implementation information and system control, including configuration, control, and reporting of system exceptions.
System timer
The system timer, SysTick, is a 24-bit count-down timer. Use this as a Real Time Operating System (RTOS) tick timer or as a simple counter.
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The Cortex®-M3 processor
2.1
2.1.1
2.1.2
Programmers model
This section describes the Cortex-M3 programmers model. In addition to the individual core register descriptions, it contains information about the processor modes and privilege levels for software execution and stacks.
Processor mode and privilege levels for software execution
The processor modes are:
Thread mode Handler mode
Used to execute application software. The processor enters Thread mode when it comes out of reset.
Used to handle exceptions. The processor returns to Thread mode when it has finished exception processing.
The privilege levels for software execution are:
Unprivileged Privileged
The software:
· Has limited access to the MSR and MRS instructions, and cannot use the CPS instruction
· Cannot access the system timer, NVIC, or system control block · Might have restricted access to memory or peripherals.
Unprivileged software executes at the unprivileged level.
The software can use all the instructions and has access to all resources.
Privileged software executes at the privileged level.
In Thread mode, the CONTROL register controls whether software execution is privileged or unprivileged, see CONTROL register on page 21. In Handler mode, software execution is always privileged.
Only privileged software can write to the CONTROL register to change the privilege level for software execution in Thread mode. Unprivileged software can use the SVC instruction to make a supervisor call to transfer control to privileged software.
Stacks
The processor uses a full descending stack. This means the stack pointer indicates the last stacked item on the stack memory. When the processor pushes a new item onto the stack, it decrements the stack pointer and then writes the item to the new memory location. The processor implements two stacks, the main stack and the process stack, with independent copies of the stack pointer, see Stack pointer on page 15.
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In Thread mode, the CONTROL register controls whether the processor uses the main stack or the process stack, see CONTROL register on page 21. In Handler mode, the processor always uses the main stack. The options for processor operations are:
Table 1. Summary of processor mode, execution privilege level, and stack use options
Processor mode
Used to execute
Privilege level for software execution
Stack used
Thread
Applications
Privileged or unprivileged(1) Main stack or process stack(1)
Handler
Exception handlers Always privileged
Main stack
1. See CONTROL register on page 21.
Core registers
Figure 2. Processor core registers
Low registers
High registers Stack pointer Link register Program counter
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 SP (R13) LR (R14) PC (R15)
PSR PRIMASK FAULTMASK BASEPRI CONTROL
General-purpose registers
PSP*
MSB* *Banked version of SP
Program status register Exception mask registers Special registers CONTROL register
MSv48364V1
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Name
Type (1)
Table 2. Core register set summary
Required privilege (2)
Reset value
Description
R0-R12 MSP PSP LR PC PSR
ASPR
read-write Either read-write Privileged read-write Either read-write Either read-write Either read-write Privileged
read-write Either
IPSR
read-only Privileged
EPSR
read-only Privileged
PRIMASK FAULTMASK BASEPRI CONTROL
read-write Privileged read-write Privileged read-write Privileged read-write Privileged
Unknown
General-purpose registers on page 15
See description Stack pointer on page 15
Unknown
Stack pointer on page 15
0xFFFFFFFF Link register on page 15
See description Program counter on page 15
0x01000000 Program status register on page 16
0x00000000
Application program status register on page 17
0x00000000
Interrupt program status register on page 18
0x01000000
Execution program status register on page 19
0x00000000 Priority mask register on page 20
0x00000000 Fault mask register on page 20
0x00000000 Base priority mask register on page 21
0x00000000 CONTROL register on page 21
1. Describes access type during program execution in thread mode and Handler mode. Debug access can differ.
2. An entry of Either means privileged and unprivileged software can access the register.
General-purpose registers
R0-R12 are 32-bit general-purpose registers for data operations.
Stack pointer
The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register indicates the stack pointer to use: · 0 = Main Stack Pointer (MSP). This is the reset value. · 1 = Process Stack Pointer (PSP). On reset, the processor loads the MSP with the value from address 0x00000000.
Link register
The Link Register (LR) is register R14. It stores the return information for subroutines, function calls, and exceptions. On reset, the processor loads the LR value 0xFFFFFFFF.
Program counter
The Program Counter (PC) is register R15. It contains the current program address. Bit[0] is always 0 because instruction fetches must be halfword aligned. On reset, the processor loads the PC with the value of the reset vector, which is at address 0x00000004.
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Program status register
The Program Status Register (PSR) combines: · Application Program Status Register (APSR) · Interrupt Program Status Register (IPSR) · Execution Program Status Register (EPSR)
These registers are mutually exclusive bitfields in the 32-bit PSR. The bit assignments are as shown in Figure 3 and Figure 4.
Figure 3. APSR, IPSR and EPSR bit assignments
31 30 29 28 27 26 25 24 23
16 15
10 9 8
0
APSR N Z C V Q
Reserved
IPSR
Reserved
ISR_NUMBER
EPSR Reserved ICI/IT T
Reserved
ICI/IT
Reserved
MS48365V1
Figure 4. PSR bit assignments
31 30 29 28 27 26 25 24 23
16 15
10 9 8
0
N Z C V Q ICI/IT T
Reserved
ICI/IT
ISR_NUMBER
Reserved
MS48366V1
Access these registers individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS instructions. For example: · Read all of the registers using PSR with the MRS instruction · Write to the APSR using APSR with the MSR instruction. The PSR combinations and attributes are:
Table 3. PSR register combinations
Register
Type
Combination
PSR
read-write(1), (2) APSR, EPSR, and IPSR
IEPSR IAPSR EAPSR
read-only read-write(1) read-write(2)
EPSR and IPSR APSR and IPSR APSR and EPSR
1. The processor ignores writes to the IPSR bits. 2. Reads of the EPSR bits return zero, and the processor ignores writes to the these bits
See the instruction descriptions MRS on page 100 and MSR on page 101 for more information about how to access the program status registers.
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Application program status register
The APSR contains the current state of the condition flags from previous instruction executions. See the register summary in Table 2 on page 15 for its attributes. The bit assignments are:
Table 4. APSR bit definitions
Bits
Description
Bit 31 Bit 30
N: Negative or less than flag: 0: Operation result was positive, zero, greater than, or equal 1: Operation result was negative or less than.
Z: Zero flag: 0: Operation result was not zero 1: Operation result was zero.
Bit 29
C: Carry or borrow flag:
0: Add operation did not result in a carry bit or subtract operation resulted in a borrow bit 1: Add operation resulted in a carry bit or subtract operation did not result in a borrow bit.
Bit 28 Bit 27
V: Overflow flag: 0: Operation did not result in an overflow 1: Operation resulted in an overflow.
Q: Sticky saturation flag: 0: Indicates that saturation has not occurred since reset or since the bit was last cleared to zero 1: Indicates when an SSAT or USAT instruction results in saturation. This bit is cleared to zero by software using an MRS instruction.
Bits 26:0 Reserved.
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Interrupt program status register
The IPSR contains the exception type number of the current Interrupt Service Routine (ISR). See the register summary in Table 2 on page 15 for its attributes. The bit assignments are:
Table 5. IPSR bit definitions
Bits
Description
Bits 31:9 Reserved
Bits 8:0
ISR_NUMBER: This is the number of the current exception: 0: Thread mode 1: Reserved 2: NMI 3: Hard fault 4: Memory management fault 5: Bus fault 6: Usage fault 7: Reserved …. 10: Reserved 11: SVCall 12: Reserved for Debug 13: Reserved 14: PendSV 15: SysTick 16: IRQ0(1) …. …. 83: IRQ67(1) see Exception types on page 32 for more information.
1. See STM32 product reference manual/datasheet for more information on interrupt mapping
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Execution program status register
The EPSR contains the Thumb state bit, and the execution state bits for either the: · If-Then (IT) instruction · Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store
multiple instruction.
See the register summary in Table 2 on page 15 for the EPSR attributes. The bit assignments are:
Table 6. EPSR bit definitions
Bits
Description
Bits 31:27 Bits 26:25, 15:10
Bits 26:25, 15:10
Reserved. ICI: Interruptible-continuable instruction bits See Interruptible-continuable instructions on page 19. IT: Indicates the execution state bits of the IT instruction, see IT on page 94.
Bit 24 Always set to 1.
Bits 23:16 Reserved. Bits 9:0] Reserved.
Attempts to read the EPSR directly through application software using the MSR instruction always return zero. Attempts to write the EPSR using the MSR instruction in application software are ignored. Fault handlers can examine EPSR value in the stacked PSR to indicate the operation that is at fault. See Section 2.3.7: Exception entry and return on page 37
Interruptible-continuable instructions
When an interrupt occurs during the execution of an LDM or STM instruction, the processor: · Stops the load multiple or store multiple instruction operation temporarily · Stores the next register operand in the multiple operation to EPSR bits[15:12].
After servicing the interrupt, the processor: · Returns to the register pointed to by bits[15:12] · Resumes execution of the multiple load or store instruction.
When the EPSR holds ICI execution state, bits[26:25,11:10] are zero.
If-Then block
The If-Then block contains up to four instructions following a 16-bit IT instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. See IT on page 94 for more information.
Exception mask registers
The exception mask registers disable the handling of exceptions by the processor. Disable exceptions where they might impact on timing critical tasks.
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To access the exception mask registers use the MSR and MRS instructions, or the CPS instruction to change the value of PRIMASK or FAULTMASK. See MRS on page 100, MSR on page 101, and CPS on page 98 for more information.
Priority mask register
The PRIMASK register prevents activation of all exceptions with configurable priority. See the register summary in Table 2 on page 15 for its attributes. Figure 5 shows the bit assignments.
Figure 5. PRIMASK bit assignments
31
Bits Bits 31:1 Bit 0
Reserved
10
PRIMASK
MSv39638V1
Table 7. PRIMASK register bit definitions Description
Reserved PRIMASK: 0: No effect 1: Prevents the activation of all exceptions with configurable priority.
Fault mask register
The FAULTMASK register prevents activation of all exceptions except for Non-Maskable Interrupt (NMI). See the register summary in Table 2 on page 15 for its attributes. Figure 6 shows the bit assignments.
Figure 6. FAULTMASK bit assignments
31
10
Reserved
FAULTMASK
MSv39639V1
Table 8. FAULTMASK register bit definitions
Bits
Function
Bits 31:1 Bit 0
Reserved
FAULTMASK: 0: No effect 1: Prevents the activation of all exceptions except for NMI.
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The processor clears the FAULTMASK bit to 0 on exit from any exception handler except the NMI handler.
Base priority mask register
The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with same or lower priority level as the BASEPRI value. See the register summary in Table 2 on page 15 for its attributes. Figure 7 shows the bit assignments.
Figure 7. BASEPRI bit assignments
31 Reserved
87
0
BASEPRI
MSv39640V1
Table 9. BASEPRI register bit assignments
Bits
Function
Bits 31:8 Bits 7:4
Reserved
BASEPRI[7:4] Priority mask bits(1) 0x00: no effect Nonzero: defines the base priority for exception processing. The processor does not process any exception with a priority value greater than or equal to BASEPRI.
Bits 3:0 Reserved
1. This field is similar to the priority fields in the interrupt priority registers. See Interrupt priority registers (NVIC_IPRx) on page 125 for more information. Remember that higher priority field values correspond to lower exception priorities.
CONTROL register
The CONTROL register controls the stack used and the privilege level for software execution when the processor is in Thread mode. See the register summary in Table 2 on page 15 for its attributes. Figure 8 shows the bit assignments.
Figure 8. CONTROL bit assignments
31 Reserved
210
Active stack pointer Thread mode privilege level
MS48367V1
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Table 10. CONTROL register bit definitions
Bits
Function
Bits 31:2 Reserved
Bit 1
ASPSEL: Active stack pointer selection Selects the current stack:
0: MSP is the current stack pointer 1: PSP is the current stack pointer. In Handler mode this bit reads as zero and ignores writes.
Bit 0
TPL: Thread mode privilege level Defines the Thread mode privilege level.
0: Privileged 1: Unprivileged.
The Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer bit of the CONTROL register when in Handler mode. The exception entry and return mechanisms update the CONTROL register.
In an OS environment, it is recommended that threads running in Thread mode use the process stack and the kernel and exception handlers use the main stack.
By default, Thread mode uses the MSP. To switch the stack pointer used in Thread mode to the PSP, use the MSR instruction to set the Active stack pointer bit to 1, see MSR on page 101.
When changing the stack pointer, software must use an ISB instruction immediately after the MSR instruction. This ensures that instructions after the ISB execute using the new stack pointer. See ISB on page 100
Exceptions and interrupts
The Cortex-M3 processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses handler mode to handle all exceptions except for reset. See Exception entry on page 37 and Exception return on page 38 for more information.
The NVIC registers control interrupt handling. See Memory protection unit (MPU) on page 105 for more information.
Data types
The processor: · Supports the following data types:
32-bit words 16-bit halfwords 8-bit bytes · supports 64-bit data transfer instructions. · manages all memory accesses (data memory, instruction memory and Private Peripheral Bus (PPB)) as little-endian. See Memory regions, types and attributes on page 25 for more information.
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The Cortex® microcontroller software interface standard (CMSIS)
For a Cortex-M3 microcontroller system, the Cortex Microcontroller Software Interface Standard (CMSIS) defines: · A common way to:
Access peripheral registers Define exception vectors · The names of: The registers of the core peripherals The core exception vectors · A device-independent interface for RTOS kernels, including a debug channel
The CMSIS includes address definitions and data structures for the core peripherals in the Cortex-M3 processor. It also includes optional interfaces for middleware components comprising a TCP/IP stack and a Flash file system.
CMSIS simplifies software development by enabling the reuse of template code and the combination of CMSIS-compliant software components from various middleware vendors. Software vendors can expand the CMSIS to include their peripheral definitions and access functions for those peripherals.
This document includes the register names defined by the CMSIS, and gives short descriptions of the CMSIS functions that address the processor core and the core peripherals.
This document uses the register short names defined by the CMSIS. In a few cases these differ from the architectural short names that might be used in other documents.
The following sections give more information about the CMSIS: · Section 2.5.4: Power management programming hints on page 43 · Intrinsic functions on page 49 · The CMSIS mapping of the Cortex®-M3 NVIC registers on page 119 · NVIC programming hints on page 127
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2.2
Memory model
This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4 GB of addressable memory.
Figure 9. Memory map
0xFFFFFFFF
Vendor-specific memory
511MB
Private peripheral bus
1.0MB
0xE0100000 0xE00FFFFF
0xE0000000 0xDFFFFFFF
External device 1.0GB
0xA0000000 0x9FFFFFFF
0x43FFFFFF 32MB Bit band alias
0x42000000
0x400FFFFF 0x40000000 1MB Bit band region 0x23FFFFFF
32MB Bit band alias 0x22000000
0x200FFFFF 0x20000000 1MB Bit band region
External RAM 1.0GB
Peripheral SRAM Code
0x60000000 0x5FFFFFFF
0.5GB
0x40000000 0x3FFFFFFF
0.5GB
0x20000000 0x1FFFFFFF
0.5GB
0x00000000
MS48368V1
The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic operations to bit data, see Section 2.2.5: Bit-banding on page 27.
The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral registers, see Section 4.1: About the STM32 core peripherals on page 105.
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2.2.1 2.2.2
Memory regions, types and attributes
The memory map splits the memory map into regions. Each region has a defined memory type, and some regions have additional memory attributes. The memory type and attributes determine the behavior of accesses to the region.
The memory types are:
Normal
The processor can re-order transactions for efficiency, or perform speculative reads.
Device
The processor preserves transaction order relative to other transactions to Device or Strongly-ordered memory.
Strongly-ordered
The processor preserves transaction order relative to all other transactions.
The different ordering requirements for Device and Strongly-ordered memory mean that the memory system can buffer a write to Device memory, but must not buffer a write to Stronglyordered memory.
The additional memory attributes include:
Execute Never (XN)
Means the processor prevents instruction accesses. Any attempt to fetch an instruction from an XN region causes a memory management fault exception.
Memory system ordering of memory accesses
For most memory accesses caused by explicit memory access instructions, the memory system does not guarantee that the order in which the accesses complete matches the program order of the instructions, providing this does not affect the behavior of the instruction sequence. Normally, if correct program execution depends on two memory accesses completing in program order, software must insert a memory barrier instruction between the memory access instructions, see Section 2.2.4: Software ordering of memory accesses on page 26.
However, the memory system does guarantee some ordering of accesses to Device and Strongly-ordered memory. For two memory access instructions A1 and A2, if A1 occurs before A2 in program order, the ordering of the memory accesses caused by two instructions is:
Table 11. Ordering of memory accesses(1) A2
A1
Device access Normal access
Non-shareable Shareable
Strongly ordered access
Normal access
–
–
–
–
Device access, non-shareable
–
<
–
<
Device access, shareable
–
–
<
<
Strongly ordered access
–
<
<
<
1. – means that the memory system does not guarantee the ordering of the accesses. < means that accesses are observed in program order, that is, A1 is always observed before A2.
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Behavior of memory accesses
The behavior of accesses to each region in the memory map is:
Table 12. Memory access behavior
Address range
Memory region
Memory type
XN
Description
0x00000000- 0x1FFFFFFF Code
Normal(1) –
Executable region for program code. You can also put data here.
0x20000000- 0x3FFFFFFF SRAM
Normal(1) –
Executable region for data. You can also put code here.
This region includes bit band and bit band alias areas, see Table 13 on page 28.
0x40000000- 0x5FFFFFFF Peripheral
Device (1)
This region includes bit band and bit XN(1) band alias areas, see Table 14 on
page 28.
0x60000000- 0x9FFFFFFF
External RAM
Normal(1) –
Executable region for data.
0xA0000000- 0xDFFFFFFF
External device
Device(1) XN(1) External Device memory
Private 0xE0000000- 0xE00FFFFF Peripheral
Bus
Stronglyordered (1)
XN (1)
This region includes the NVIC, System timer, and system control block.
Memory 0xE0100000- 0xFFFFFFFF mapped
Device (1)
peripherals
XN (1)
This region includes all the STM32 standard peripherals.
1. See Memory regions, types and attributes on page 25 for more information.
The Code, SRAM, and external RAM regions can hold programs. However, it is recommended that programs always use the Code region. This is because the processor has separate buses that enable instruction fetches and data accesses to occur simultaneously.
Software ordering of memory accesses
The order of instructions in the program flow does not always guarantee the order of the corresponding memory transactions. This is because: · The processor can reorder some memory accesses to improve efficiency, providing this
does not affect the behavior of the instruction sequence. · The processor has multiple bus interfaces · Memory or devices in the memory map have different wait states · Some memory accesses are buffered or speculative.
Section 2.2.2: Memory system ordering of memory accesses on page 25 describes the cases where the memory system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is critical, software must include memory barrier instructions to force that ordering. The processor provides the following memory barrier instructions:
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DMB
The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions complete before subsequent memory transactions. See DMB on page 99.
DSB
The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions complete before subsequent instructions execute. See DSB on page 100.
ISB
The Instruction Synchronization Barrier (ISB) ensures that the effect of all
completed memory transactions is recognizable by subsequent
instructions. See ISB on page 100.
Use memory barrier instructions in, for example:
· Vector table. If the program changes an entry in the vector table, and then enables the corresponding exception, use a DMB instruction between the operations. This ensures that if the exception is taken immediately after being enabled the processor uses the new exception vector.
· Self-modifying code. If a program contains self-modifying code, use an ISB instruction immediately after the code modification in the program. This ensures subsequent instruction execution uses the updated program.
· Memory map switching. If the system contains a memory map switching mechanism, use a DSB instruction after switching the memory map in the program. This ensures subsequent instruction execution uses the updated memory map.
· Dynamic exception priority change. When an exception priority has to change when the exception is pending or active, use DSB instructions after the change. This ensures the change takes effect on completion of the DSB instruction.
· Using a semaphore in multi-master system. If the system contains more than one bus master, for example, if another processor is present in the system, each processor must use a DMB instruction after any semaphore instructions, to ensure other bus masters see the memory transactions in the order in which they were executed.
Memory accesses to Strongly-ordered memory, such as the system control block, do not require the use of DMB instructions.
Bit-banding
A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions.
The memory map has two 32 MB alias regions that map to two 1 MB bit-band regions: · Accesses to the 32 MB SRAM alias region map to the 1 MB SRAM bit-band region, as
shown in Table 13 · Accesses to the 32 MB peripheral alias region map to the 1 MB peripheral bit-band
region, as shown in Table 14.
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Table 13. SRAM memory bit-banding regions
Address range
Memory region
Instruction and data accesses
0x200000000x200FFFFF
0x220000000x23FFFFFF
SRAM bit-band region
Direct accesses to this memory range behave as SRAM memory accesses, but this region is also bit addressable through bit-band alias.
SRAM bit-band alias
Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write. Instruction accesses are not remapped.
Table 14. Peripheral memory bit-banding regions
Address range
Memory region
Instruction and data accesses
0x40000000- Peripheral 0x400FFFFF bit-band region
Direct accesses to this memory range behave as peripheral memory accesses, but this region is also bit addressable through bit-band alias.
0x42000000- Peripheral 0x43FFFFFF bit-band alias
Data accesses to this region are remapped to bit-band region. A write operation is performed as read-modify-write. Instruction accesses are not permitted.
A word access to the SRAM or peripheral bit-band alias regions map to a single bit in the SRAM or peripheral bit-band region.
The following formula shows how the alias region maps onto the bit-band region:
bit_word_offset = (byte_offset x 32) + (bit_number x 4)
bit_word_addr = bit_band_base + bit_word_offset
Where: · Bit_word_offset is the position of the target bit in the bit-band memory region. · Bit_word_addr is the address of the word in the alias memory region that maps to the
targeted bit. · Bit_band_base is the starting address of the alias region. · Byte_offset is the number of the byte in the bit-band region that contains the targeted
bit. · Bit_number is the bit position, 0-7, of the targeted bit.
Figure 10 on page 29 shows examples of bit-band mapping between the SRAM bit-band alias region and the SRAM bit-band region: · The alias word at 0x23FFFFE0 maps to bit[0] of the bit-band byte at
0x200FFFFF: 0x23FFFFE0 = 0x22000000 + (0xFFFFF*32) + (0*4). · The alias word at 0x23FFFFFC maps to bit[7] of the bit-band byte at
0x200FFFFF: 0x23FFFFFC = 0x22000000 + (0xFFFFF*32) + (7*4). · The alias word at 0x22000000 maps to bit[0] of the bit-band byte at
0x20000000: 0x22000000 = 0x22000000 + (0*32) + (0 *4). · The alias word at 0x2200001C maps to bit[7] of the bit-band byte at
0x20000000: 0x2200001C = 0x22000000+ (0*32) + (7*4).
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Figure 10. Bit-band mapping
32MB alias region
0x23FFFFFC 0x23FFFFF8 0x23FFFFF4 0x23FFFFF0 0x23FFFFEC 0x23FFFFE8 0x23FFFFE4 0x23FFFFE0
0x2200001C 0x22000018 0x22000014 0x22000010 0x2200000C 0x22000008 0x22000004 0x22000000
1MB SRAM bit-band region
76543210765432107654321076543210
0x200FFFFF
0x200FFFFE
0x200FFFFD
0x200FFFFC
2.2.6
76543210765432107654321076543210
0x20000003
0x20000002
0x20000001
0x20000000
MS48369V1
Directly accessing an alias region
Writing to a word in the alias region updates a single bit in the bit-band region.
Bit[0] of the value written to a word in the alias region determines the value written to the targeted bit in the bit-band region. Writing a value with bit[0] set to 1 writes a 1 to the bitband bit, and writing a value with bit[0] set to 0 writes a 0 to the bit-band bit.
Bits[31:1] of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as writing 0xFF. Writing 0x00 has the same effect as writing 0x0E.
Reading a word in the alias region: · 0x00000000 indicates that the targeted bit in the bit-band region is set to zero · 0x00000001 indicates that the targeted bit in the bit-band region is set to 1
Directly accessing a bit-band region
Behavior of memory accesses on page 26 describes the behavior of direct byte, halfword, or word accesses to the bit-band regions.
Memory endianness
The processor views memory as a linear collection of bytes numbered in ascending order from zero. For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word.
Little-endian format
In little-endian format, the processor stores the least significant byte of a word at the lowestnumbered byte, and the most significant byte at the highest-numbered byte. See Figure 11 for an example.
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2.2.7
Figure 11. Little-endian example
Memory
7
0
Register
Address A B0
lsbyte
31 24 23 16 15 8 7
0
B3
B2
B1
B0
A+1 B1
A+2 B2
A+3 B3 msbyte
MSv39644V1
Synchronization primitives
The Cortex-M3 instruction set includes pairs of synchronization primitives. These provide a non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory location. Software can use them to perform a guaranteed read-modify-write memory update sequence, or for a semaphore mechanism.
A pair of synchronization primitives comprises:
A Load-Exclusive instruction
Used to read the value of a memory location, requesting exclusive access to that location.
A Store-Exclusive instruction
Used to attempt to write to the same memory location, returning a status bit to a register. If this bit is:
0: it indicates that the thread or process gained exclusive access to the memory, and the write succeeds
1: it indicates that the thread or process did not gain exclusive access to the memory, and no write is performed
The pairs of Load-Exclusive and Store-Exclusive instructions are:
· The word instructions LDREX and STREX
· The halfword instructions LDREXH and STREXH
· The byte instructions LDREXB and STREXB.
Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction.
To perform a guaranteed read-modify-write of a memory location, software must: 1. Use a Load-Exclusive instruction to read the value of the location. 2. Update the value, as required. 3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory
location, and tests the returned status bit. If this bit is: 0: The read-modify-write completed successfully, 1: No write was performed. This indicates that the value returned at step 1 might be out of date. The software must retry the read-modify-write sequence,
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Software can use the synchronization primitives to implement a semaphores as follows: 1. Use a Load-Exclusive instruction to read from the semaphore address to check
whether the semaphore is free. 2. If the semaphore is free, use a Store-Exclusive to write the claim value to the
semaphore address. 3. If the returned status bit from step 2 indicates that the Store-Exclusive succeeded then
the software has claimed the semaphore. However, if the Store-Exclusive failed, another process might have claimed the semaphore after the software performed step 1.
The Cortex-M3 includes an exclusive access monitor, that tags the fact that the processor has executed a Load-Exclusive instruction.
The processor removes its exclusive access tag if: · It executes a CLREX instruction · It executes a Store-Exclusive instruction, regardless of whether the write succeeds. · An exception occurs. This means the processor can resolve semaphore conflicts
between different threads.
For more information about the synchronization primitive instructions, see LDREX and STREX on page 70 and CLREX on page 71.
Programming hints for the synchronization primitives
ANSI C cannot directly generate the exclusive access instructions. Some C compilers provide intrinsic functions for generation of these instructions:
Table 15. C compiler intrinsic functions for exclusive access instructions
Instruction
Intrinsic function
LDREX, LDREXH, or LDREXB unsigned int __ldrex(volatile void *ptr)
STREX, STREXH, or STREXB int __strex(unsigned int val, volatile void *ptr)
CLREX
void __clrex(void)
The actual exclusive access instruction generated depends on the data type of the pointer passed to the intrinsic function. For example, the following C code generates the require LDREXB operation:
__ldrex((volatile char *) 0xFF);
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2.3
2.3.1
Exception model
This section describes the exception model.
Exception states
Each exception is in one of the following states:
2.3.2
Inactive Pending Active
Active and pending
The exception is not active and not pending.
The exception is waiting to be serviced by the processor. An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending.
An exception that is being serviced by the processor but has not completed. Note: An exception handler can interrupt the execution of another
exception handler. In this case both exceptions are in the active state.
The exception is being serviced by the processor and there is a pending exception from the same source.
Exception types
The exception types are:
Reset
Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception. When reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset is deasserted, execution restarts from the address provided by the reset entry in the vector table. Execution restarts as privileged execution in Thread mode.
NMI
A NonMaskable Interrupt (NMI) can be signalled by a peripheral or
triggered by software. This is the highest priority exception other
than reset. It is permanently enabled and has a fixed priority of -2.
NMIs cannot be:
· Masked or prevented from activation by any other exception
· Preempted by any exception other than Reset.
Hard fault
A hard fault is an exception that occurs because of an error during exception processing, or because an exception cannot be managed by any other exception mechanism. Hard faults have a fixed priority of -1, meaning they have higher priority than any exception with configurable priority.
Memory management A memory management fault is an exception that occurs because of
fault
a memory protection related fault. The fixed memory protection
constraints determines this fault, for both instruction and data
memory transactions. This fault is used to abort instruction accesses
to Execute Never (XN) memory regions.
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Bus fault Usage fault
SVCall PendSV SysTick Interrupt (IRQ)
A bus fault is an exception that occurs because of a memory related fault for an instruction or data memory transaction. This might be from an error detected on a bus in the memory system.
A usage fault is an exception that occurs because of a fault related to instruction execution. This includes: · An undefined instruction · An illegal unaligned access · Invalid state on instruction execution · An error on exception return.
The following can cause a usage fault when the core is configured to report them: · An unaligned address on word and halfword memory access · Division by zero
A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS environment, applications can use SVC instructions to access OS kernel functions and device drivers.
PendSV is an interrupt-driven request for system-level service. In an OS environment, use PendSV for context switching when no other exception is active.
A SysTick exception is an exception the system timer generates when it reaches zero. Software can also generate a SysTick exception. In an OS environment, the processor can use this exception as system tick.
A interrupt, or IRQ, is an exception signalled by a peripheral, or generated by a software request. All interrupts are asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor.
Table 16. Properties of the different exception types
Exception
IRQ
number(1) number(1)
Exception type
Priority
Vector address or offset (2)
Activation
1
–
Reset
-3, the highest 0x00000004
Asynchronous
2
-14
NMI
-2
0x00000008
Asynchronous
3
-13
Hard fault
-1
0x0000000C
–
4
-12
Memory management fault
Configurable (3)
0x00000010
Synchronous
5
-11
Bus fault
Configurable(3) 0x00000014
Synchronous when precise, asynchronous when imprecise
6
-10
Usage fault
Configurable(3) 0x00000018
Synchronous
7-10
–
11
-5
SVCall
–
Reserved
Configurable(3) 0x0000002C
Synchronous
12-13
–
–
–
Reserved
–
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Table 16. Properties of the different exception types (continued)
Exception
IRQ
number(1) number(1)
Exception type
Priority
Vector address or offset (2)
Activation
14
-2
PendSV
Configurable(3) 0x00000038
Asynchronous
15
-1
SysTick
Configurable(3) 0x0000003C
Asynchronous
16-83
0-67
Interrupt (IRQ)
Configurable (4)
0x00000040 and above (5)
Asynchronous
1. To simplify the software layer, the CMSIS only uses IRQ numbers and therefore uses negative values for exceptions other than interrupts. The IPSR returns the Exception number, see Interrupt program status register on page 18.
2. See Vector table on page 35 for more information. 3. See System handler priority registers (SHPRx) on page 138. 4. See Interrupt priority registers (NVIC_IPRx) on page 125. 5. Increasing in steps of 4.
2.3.3
For an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions that Table 16 on page 33 shows as having configurable priority, see: · System handler control and state register (SCB_SHCSR) on page 140 · Interrupt clear-enable registers (NVIC_ICERx) on page 121
For more information about hard faults, memory management faults, bus faults, and usage faults, see Section 2.4: Fault handling on page 39.
Exception handlers
The processor handles exceptions using:
Interrupt Service Routines (ISRs) Fault handlers
System handlers
Interrupts IRQ0 to IRQ67 are the exceptions handled by ISRs.
Hard fault, memory management fault, usage fault, bus fault are fault exceptions handled by the fault handlers. NMI, PendSV, SVCall SysTick, and the fault exceptions are all system exceptions that are handled by system handlers.
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2.3.4 2.3.5
Vector table
The vector table contains the reset value of the stack pointer, and the start addresses, also called exception vectors, for all exception handlers. Figure 12 on page 35 shows the order of the exception vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the exception handler is Thumb code.
Figure 12. Vector table
Exception number IRQ number Offset
Vector
83
67
IRQ67
0x014C
.
.
.
.
.
.
.
.
.
0x004C
18
2
IRQ2
0x0048
17
1
IRQ1
0x0044
16
0
IRQ0
0x0040
15
-1
Systick
0x003C
14
-2
PendSV
0x0038
13
Reserved
12
Reserved for Debug
11
-5
SVCall
0x002C
10
9 Reserved
8
7
6
-10
Usage fault
0x0018
5
-11
Bus fault
0x0014
4
-12
Memory management fault
0x0010
3
-13
Hard fault
0x000C
2
-14
NMI
0x0008
1
Reset
0x0004
Initial SP value
0x0000
MSv48370V1
On system reset, the vector table is fixed at address 0x00000000. Privileged software can write to the VTOR to relocate the vector table start address to a different memory location, in the range 0x00000080 to 0x3FFFFF80, see Vector table offset register (SCB_VTOR) on page 133.
Exception priorities
As Table 16 on page 33 shows, all exceptions have an associated priority, with: · A lower priority value indicating a higher priority · Configurable priorities for all exceptions except Reset, Hard fault, and NMI.
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If software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0. For information about configuring exception priorities see · System handler priority registers (SHPRx) on page 138 · Interrupt priority registers (NVIC_IPRx) on page 125
Configurable priority values are in the range 0-15. This means that the Reset, Hard fault, and NMI exceptions, with fixed negative priority values, always have higher priority than any other exception.
2.3.6
For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0].
If multiple pending exceptions have the same priority, the pending exception with the lowest exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is processed before IRQ[1].
When the processor is executing an exception handler, the exception handler is preempted if a higher priority exception occurs. If an exception occurs with the same priority as the exception being handled, the handler is not preempted, irrespective of the exception number. However, the status of the new interrupt changes to pending.
Interrupt priority grouping
To increase priority control in systems with interrupts, the NVIC supports priority grouping. This divides each interrupt priority register entry into two fields: · An upper field that defines the group priority · A lower field that defines a subpriority within the group.
Only the group priority determines preemption of interrupt exceptions. When the processor is executing an interrupt exception handler, another interrupt with the same group priority as the interrupt being handled does not preempt the handler,
If multiple pending interrupts have the same group priority, the subpriority field determines the order in which they are processed. If multiple pending interrupts have the same group priority and subpriority, the interrupt with the lowest IRQ number is processed first.
For information about splitting the interrupt priority fields into group priority and subpriority, see Application interrupt and reset control register (SCB_AIRCR) on page 134.
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2.3.7
Exception entry and return
Descriptions of exception handling use the following terms:
Preemption
When the processor is executing an exception handler, an exception can preempt the exception handler if its priority is higher than the priority of the exception being handled. See Section 2.3.6: Interrupt priority grouping for more information about preemption by an interrupt.
When one exception preempts another, the exceptions are called nested exceptions. See Exception entry on page 37 more information.
Return
This occurs when the exception handler is completed, and:
· There is no pending exception with sufficient priority to be serviced
· The completed exception handler was not handling a latearriving exception.
The processor pops the stack and restores the processor state to the state it had before the interrupt occurred. See Exception return on page 38 for more information.
Tail-chaining
This mechanism speeds up exception servicing. On completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler.
Late-arriving
This mechanism speeds up preemption. If a higher priority exception occurs during state saving for a previous exception, the processor switches to handle the higher priority exception and initiates the vector fetch for that exception. State saving is not affected by late arrival because the state saved is the same for both exceptions. Therefore the state saving continues uninterrupted. The processor can accept a late arriving exception until the first instruction of the exception handler of the original exception enters the execute stage of the processor. On return from the exception handler of the latearriving exception, the normal tail-chaining rules apply.
Exception entry
Exception entry occurs when there is a pending exception with sufficient priority and either: · The processor is in Thread mode · The new exception is of higher priority than the exception being handled, in which case
the new exception preempts the original exception.
When one exception preempts another, the exceptions are nested.
Sufficient priority means the exception has more priority than any limits set by the mask registers, see Exception mask registers on page 19. An exception with less priority than this is pending but is not handled by the processor.
When the processor takes an exception, unless the exception is a tail-chained or a latearriving exception, the processor pushes information onto the current stack. This operation
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is referred as stacking and the structure of eight data words is referred as stack frame. The stack frame contains the following information: · R0-R3, R12 · Return address · PSR · LR.
Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. Unless stack alignment is disabled, the stack frame is aligned to a double-word address. If the STKALIGN bit of the Configuration Control Register (CCR) is set to 1, stack align adjustment is performed during stacking.
The stack frame includes the return address. This is the address of the next instruction in the interrupted program. This value is restored to the PC at exception return so that the interrupted program resumes.
In parallel to the stacking operation, the processor performs a vector fetch that reads the exception handler start address from the vector table. When stacking is complete, the processor starts executing the exception handler. At the same time, the processor writes an EXC_RETURN value to the LR. This indicates which stack pointer corresponds to the stack frame and what operation mode the was processor was in before the entry occurred.
If no higher priority exception occurs during exception entry, the processor starts executing the exception handler and automatically changes the status of the corresponding pending interrupt to active.
If another higher priority exception occurs during exception entry, the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception. This is the late arrival case.
Exception return
Exception return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into the PC: · A POP instruction that includes the PC · A BX instruction with any register. · An LDR or LDM instruction with the PC as the destination
EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value to detect when the processor has completed an exception handler. The lowest four bits of this value provide information on the return stack and processor mode. Table 17 shows the EXC_RETURN[3:0] values with a description of the exception return behavior.
The processor sets EXC_RETURN bits[31:4] to 0xFFFFFFF. When this value is loaded into the PC it indicates to the processor that the exception is complete, and the processor initiates the exception return sequence.
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Table 17. Exception return behavior
EXC_RETURN[3:0]
Description
0bxxx0 0b0001
Reserved.
Return to Handler mode. Exception return gets state from MSP. Execution uses MSP after return.
0b0011 0b01x1
0b1001
Reserved.
Reserved.
Return to Thread mode. Exception return gets state from MSP. Execution uses MSP after return.
0b1101 0b1x11
Return to Thread mode. Exception return gets state from PSP. Execution uses PSP after return.
Reserved.
2.4
2.4.1
Fault handling
Faults are a subset of the exceptions, see Exception model on page 32. The following generate a fault: · A bus error on:
An instruction fetch or vector table load A data access · An internally-detected error such as an undefined instruction or an attempt to change state with a BX instruction · Attempting to execute an instruction from a memory region marked as Non-Executable (XN).
Fault types
Table 18 shows the types of fault, the handler used for the fault, the corresponding fault status register, and the register bit that indicates that the fault has occurred. See Configurable fault status register (SCB_CFSR) on page 142 for more information about the fault status registers.
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Table 18. Faults
Fault
Handler
Bit name
Bus error on a vector read Fault escalated to a hard fault Bus error:
During exception stacking During exception unstacking During instruction prefetch Precise data bus error Imprecise data bus error Attempt to access a coprocessor Undefined instruction Attempt to enter an invalid instruction set state (1) Invalid EXC_RETURN value Illegal unaligned load or store Divide By 0
Hard fault Bus fault
Usage fault
VECTTBL FORCED STKERR UNSTKERR IBUSERR PRECISERR IMPRECISERR NOCP UNDEFINSTR
INVSTATE
INVPC UNALIGNED DIVBYZERO
1. Attempting to use an instruction set other than the Thumb instruction set.
Fault status register Hard fault status register (SCB_HFSR) on page 145 –
Configurable fault status register (SCB_CFSR) on page 142
Configurable fault status register (SCB_CFSR) on page 142
2.4.2
Fault escalation and hard faults
All faults exceptions except for hard fault have configurable exception priority, see System handler priority registers (SHPRx) on page 138. Software can disable execution of the handlers for these faults, see System handler control and state register (SCB_SHCSR) on page 140.
Usually, the exception priority, together with the values of the exception mask registers, determines whether the processor enters the fault handler, and whether a fault handler can preempt another fault handler. as described in Section 2.3: Exception model on page 32.
In some situations, a fault with configurable priority is treated as a hard fault. This is called priority escalation, and the fault is described as escalated to hard fault. Escalation to hard fault occurs when:
· A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard fault occurs because a fault handler cannot preempt itself because it must have the same priority as the current priority level.
· A fault handler causes a fault with the same or lower priority as the fault it is servicing. This is because the handler for the new fault cannot preempt the currently executing fault handler.
· An exception handler causes a fault for which the priority is the same as or lower than the currently executing exception.
· A fault occurs and the handler for that fault is not enabled.
If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not escalate to a hard fault. This means that if a corrupted stack causes a fault, the fault handler executes even though the stack push for the handler failed. The fault handler operates but the stack contents are corrupted.
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Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any exception other than Reset, NMI, or another hard fault.
2.4.3
Fault status registers and fault address registers
The fault status registers indicate the cause of a fault. For bus faults and memory management faults, the fault address register indicates the address accessed by the operation that caused the fault, as shown in Table 19.
Handler Hard fault Memory management fault
Bus fault
Usage fault
Table 19. Fault status and fault address registers
Status register Address register
name
name
Register description
HFSR MMFSR
MMFAR
Hard fault status register (SCB_HFSR) on page 145
Configurable fault status register (SCB_CFSR) on page 142 Memory management fault address register (SCB_MMFAR) on page 147
BFSR UFSR
BFAR –
Configurable fault status register (SCB_CFSR) on page 142 Bus fault address register (SCB_BFAR) on page 147
Configurable fault status register (SCB_CFSR) on page 142
2.4.4
Lockup
The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault handlers. When the processor is in lockup state it does not execute any instructions. The processor remains in lockup state until either: · It is reset · An NMI occurs
If lockup state occurs from the NMI handler a subsequent NMI does not cause the processor to leave lockup state.
2.5
Power management
The STM32 and Cortex-M3 processor sleep modes reduce power consumption:
· Sleep mode stops the processor clock. All other system and peripheral clocks may still be running.
· Deep sleep mode stops most of the STM32 system and peripheral clocks. At product level, this corresponds to either the Stop or the Standby mode. For more details, please refer to the “Power modes” Section in the STM32 reference manual.
The SLEEPDEEP bit of the SCR selects which sleep mode is used, see System control register (SCB_SCR) on page 136. For more information about the behavior of the sleep modes see the STM32 product reference manual.
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2.5.1 2.5.2
This section describes the mechanisms for entering sleep mode, and the conditions for waking up from sleep mode.
Entering sleep mode
This section describes the mechanisms software can use to put the processor into sleep mode.
The system can generate spurious wakeup events, for example a debug operation wakes up the processor. Therefore software must be able to put the processor back into sleep mode after such an event. A program might have an idle loop to put the processor back to sleep mode.
Wait for interrupt
The wait for interrupt instruction, WFI, causes immediate entry to sleep mode. When the processor executes a WFI instruction it stops executing instructions and enters sleep mode. See WFI on page 104 for more information.
Wait for event
The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of an one-bit event register. When the processor executes a WFE instruction, it checks this register: · If the register is 0 the processor stops executing instructions and enters sleep mode · If the register is 1 the processor clears the register to 0 and continues executing
instructions without entering sleep mode.
See WFE on page 103 for more information.
If the event register is 1, this indicate that the processor must not enter sleep mode on execution of a WFE instruction. Typically, this is because an external event signal is asserted, or a processor in the system has executed an SEV instruction, see SEV on page 102. Software cannot access this register directly.
Sleep-on-exit
If the SLEEPONEXIT bit of the SCR is set to 1, when the processor completes the execution of an exception handler it returns to Thread mode and immediately enters sleep mode. Use this mechanism in applications that only require the processor to run when an exception occurs.
Wakeup from sleep mode
The conditions for the processor to wakeup depend on the mechanism that cause it to enter sleep mode.
Wakeup from WFI or sleep-on-exit
Normally, the processor wakes up only when it detects an exception with sufficient priority to cause exception entry.
Some embedded systems might have to execute system restore tasks after the processor wakes up, and before it executes an interrupt handler. To achieve this set the PRIMASK bit to 1 and the FAULTMASK bit to 0. If an interrupt arrives that is enabled and has a higher priority than current exception priority, the processor wakes up but does not execute the
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interrupt handler until the processor sets PRIMASK to zero. For more information about PRIMASK and FAULTMASK see Exception mask registers on page 19.
Wakeup from WFE
The processor wakes up if: · it detects an exception with sufficient priority to cause exception entry · it detects an external event signal, see The external event input on page 43
In addition, if the SEVONPEND bit in the SCR is set to 1, any new pending interrupt triggers an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to cause exception entry. For more information about the SCR see System control register (SCB_SCR) on page 136.
The external event input
The processor provides an external event input signal. This signal can be generated by the up to 16 external input lines, by the PVD, RTC alarm or by the USB wakeup event, configured through the external interrupt/event controller (EXTI).
This signal can wakeup the processor from WFE, or set the internal WFE event register to one to indicate that the processor must not enter sleep mode on a later WFE instruction, see Wait for event on page 42. Fore more details please refer to the STM32 reference manual, section 4.3 Low power modes.
Power management programming hints
ANSI C cannot directly generate the WFI and WFE instructions. The CMSIS provides the following intrinsic functions for these instructions:
void __WFE(void) // Wait for Event
void __WFE(void) // Wait for Interrupt
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3.1
Instruction set summary
The processor implements a version of the thumb instruction set. Table 20 lists the supported instructions.
In Table 20: · Angle brackets, <>, enclose alternative forms of the operand · Braces, {}, enclose optional operands · The operands column is not exhaustive · Op2 is a flexible second operand that can be either a register or a constant · Most instructions can use an optional condition code suffix
For more information on the instructions and operands, see the instruction descriptions.
Mnemonic
Table 20. Cortex-M3 instructions
Operands
Brief description
ADC, ADCS {Rd,} Rn, Op2
Add with carry
ADD, ADDS {Rd,} Rn, Op2
Add
ADD, ADDW {Rd,} Rn, #imm12
Add
ADR
Rd, label
Load PC-relative address
AND, ANDS {Rd,} Rn, Op2
Logical AND
ASR, ASRS Rd, Rm, <Rs|#n>
Arithmetic shift right
B
label
Branch
BFC
Rd, #lsb, #width
Bit field clear
BFI
Rd, Rn, #lsb, #width Bit field insert
BIC, BICS {Rd,} Rn, Op2
Bit clear
BKPT
#imm
Breakpoint
BL
label
Branch with link
BLX
Rm
Branch indirect with link
Flags N,Z,C,V N,Z,C,V N,Z,C,V N,Z,C N,Z,C N,Z,C –
Section
3.5.1 on page 73
3.5.1 on page 73
3.5.1 on page 73
3.4.1 on page 60
3.5.2 on page 75
3.5.3 on page 76
3.8.5 on page 92
3.8.1 on page 89
3.8.1 on page 89
3.5.2 on page 75
3.9.1 on page 98
3.8.5 on page 92
3.8.5 on page 92
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Mnemonic
Table 20. Cortex-M3 instructions (continued)
Operands
Brief description
Flags
BX
Rm
Branch indirect
–
CBNZ
Rn, label
Compare and branch if non zero –
CBZ
Rn, label
Compare and branch if zero
–
CLREX
–
Clear exclusive
–
CLZ
Rd, Rm
Count leading zeros
–
CMN, CMNS Rn, Op2
Compare negative
N,Z,C,V
CMP, CMPS Rn, Op2
CPSID
iflags
CPSIE
iflags
DMB
–
Compare
N,Z,C,V
Change processor state, disable interrupts
–
Change processor state, enable interrupts
–
Data memory barrier
–
DSB
–
Data synchronization barrier
–
EOR, EORS {Rd,} Rn, Op2
Exclusive OR
N,Z,C
ISB
–
Instruction synchronization barrier –
IT
LDM
LDMDB, LDMEA LDMFD, LDMIA
LDR
LDRB, LDRBT
LDRD
Rn{!}, reglist Rn{!}, reglist Rn{!}, reglist Rt, [Rn, #offset]
If-then condition block
–
Load multiple registers, increment after
–
Load multiple registers, decrement before
–
Load multiple registers, increment after
–
Load register with word
–
Rt, [Rn, #offset]
Load register with byte
–
Rt, Rt2, [Rn, #offset] Load register with two bytes
–
LDREX
Rt, [Rn, #offset]
Load register exclusive
–
Section
3.8.5 on page 92
3.8.6 on page 93
3.8.6 on page 93
3.4.9 on page 71
3.5.4 on page 77
3.5.5 on page 78
3.5.5 on page 78
3.9.2 on page 98
3.9.2 on page 98
3.9.4 on page 100
3.9.4 on page 100
3.5.2 on page 75
3.9.5 on page 100
3.8.7 on page 94
3.4.6 on page 67
3.4.6 on page 67
3.4.6 on page 67
3.4 on page 59
3.4 on page 59
3.4.2 on page 61
3.4.8 on page 70
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Mnemonic
Table 20. Cortex-M3 instructions (continued)
Operands
Brief description
Flags
LDREXB
Rt, [Rn]
Load register exclusive with byte –
LDREXH
LDRH, LDRHT
LDRSB, LDRSBT
LDRSH, LDRSHT
Rt, [Rn] Rt, [Rn, #offset] Rt, [Rn, #offset] Rt, [Rn, #offset]
Load register exclusive with halfword
–
Load register with halfword
–
Load register with signed byte
–
Load register with signed halfword –
LDRT
Rt, [Rn, #offset]
Load register with word
–
LSL, LSLS Rd, Rm, <Rs|#n>
Logical shift left
N,Z,C
LSR, LSRS Rd, Rm, <Rs|#n>
MLA
Rd, Rn, Rm, Ra
MLS
Rd, Rn, Rm, Ra
Logical shift right
N,Z,C
Multiply with accumulate, 32-bit result
–
Multiply and subtract, 32-bit result –
MOV, MOVS Rd, Op2
Move
N,Z,C
MOVT
Rd, #imm16
Move top
–
MOVW, MOV Rd, #imm16
MRS
Rd, spec_reg
MSR
spec_reg, Rm
MUL, MULS {Rd,} Rn, Rm
Move 16-bit constant
Move from special register to general register Move from general register to special register
Multiply, 32-bit result
N,Z,C N,Z,C,V N,Z
MVN, MVNS Rd, Op2
Move NOT
N,Z,C
NOP
–
No operation
–
ORN, ORNS {Rd,} Rn, Op2
Logical OR NOT
N,Z,C
ORR, ORRS {Rd,} Rn, Op2
Logical OR
N,Z,C
POP
reglist
Pop registers from stack
–
Section
3.4.8 on page 70
3.4.8 on page 70
3.4 on page 59
3.4 on page 59
3.4 on page 59
3.4 on page 59
3.5.3 on page 76
3.5.3 on page 76
3.6.1 on page 83
3.6.1 on page 83
3.5.6 on page 79
3.5.7 on page 80
3.5.6 on page 79
3.9.6 on page 100
3.9.7 on page 101
3.6.1 on page 83
3.5.6 on page 79
3.9.8 on page 102
3.5.2 on page 75
3.5.2 on page 75
3.4.7 on page 68
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Mnemonic
Table 20. Cortex-M3 instructions (continued)
Operands
Brief description
Flags
PUSH
reglist
Push registers onto stack
–
RBIT
Rd, Rn
Reverse bits
–
REV
Rd, Rn
REV16
Rd, Rn
REVSH
Rd, Rn
ROR, RORS Rd, Rm, <Rs|#n>
Reverse byte order in a word
Reverse byte order in each halfword Reverse byte order in bottom halfword and sign extend
Rotate right
N,Z,C
RRX, RRXS Rd, Rm
Rotate right with extend
N,Z,C
RSB, RSBS {Rd,} Rn, Op2
Reverse subtract
N,Z,C,V
SBC, SBCS {Rd,} Rn, Op2
Subtract with carry
N,Z,C,V
SBFX
Rd, Rn, #lsb, #width Signed bit field extract
–
SDIV
{Rd,} Rn, Rm
Signed divide
–
SEV
SMLAL
SMULL
SSAT
STM STMDB, STMEA STMFD, STMIA STR STRB, STRBT STRD
–
Send event
–
RdLo, RdHi, Rn, Rm
Signed multiply with accumulate (32 x 32 + 64), 64-bit result
–
RdLo, RdHi, Rn, Rm
Signed multiply (32 x 32), 64-bit result
–
Rd, #n, Rm {,shift #s} Signed saturate
Q
Rn{!}, reglist Rn{!}, reglist Rn{!}, reglist
Store multiple registers, increment after
–
Store multiple registers, decrement before
–
Store multiple registers, increment after
–
Rt, [Rn, #offset]
Store register word
–
Rt, [Rn, #offset]
Store register byte
–
Rt, Rt2, [Rn, #offset] Store register two words
–
Section
3.4.7 on page 68
3.5.8 on page 81
3.5.8 on page 81
3.5.8 on page 81
3.5.8 on page 81
3.5.3 on page 76
3.5.3 on page 76
3.5.1 on page 73
3.5.1 on page 73
3.8.2 on page 89
3.6.3 on page 86
3.9.9 on page 102
3.6.2 on page 85
3.6.2 on page 85
3.7.1 on page 87
3.4.6 on page 67
3.4.6 on page 67
3.4.6 on page 67
3.4 on page 59
3.4 on page 59
3.4.2 on page 61
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Mnemonic
Table 20. Cortex-M3 instructions (continued)
Operands
Brief description
Flags
STREX
Rd, Rt, [Rn, #offset] Store register exclusive
–
STREXB
Rd, Rt, [Rn]
Store register exclusive byte
–
STREXH
STRH, STRHT
STRT
Rd, Rt, [Rn] Rt, [Rn, #offset] Rt, [Rn, #offset]
Store register exclusive halfword –
Store register halfword
–
Store register word
–
SUB, SUBS {Rd,} Rn, Op2
Subtract
N,Z,C,V
SUB, SUBW {Rd,} Rn, #imm12
Subtract
N,Z,C,V
SVC
#imm
Supervisor call
–
SXTB
{Rd,} Rm {,ROR #n} Sign extend a byte
–
SXTH
{Rd,} Rm {,ROR #n} Sign extend a halfword
–
TBB
[Rn, Rm]Table branch byte
–
TBH
[Rn, Rm, LSL #1]Table branch halfword
–
TEQ
Rn, Op2
Test equivalence
N,Z,C
TST
Rn, Op2
Test
N,Z,C
UBFX
Rd, Rn, #lsb, #width Unsigned bit field extract
–
UDIV UMLAL UMULL USAT
{Rd,} Rn, Rm
Unsigned divide
–
RdLo, RdHi, Rn, Rm RdLo, RdHi, Rn, Rm
Unsigned multiply with accumulate (32 x 32 + 64), 64-bit result
–
Unsigned multiply (32 x 32), 64-bit result
–
Rd, #n, Rm {,shift #s} Unsigned saturate
Q
UXTB
{Rd,} Rm {,ROR #n} Zero extend a byte
–
UXTH
{Rd,} Rm {,ROR #n} Zero extend a halfword
–
Section
3.4.8 on page 70
3.4.8 on page 70
3.4.8 on page 70
3.4 on page 59
3.4 on page 59
3.5.1 on page 73
3.5.1 on page 73
3.9.10 on page 103
3.8.3 on page 90
3.8.3 on page 90
3.8.8 on page 96
3.8.8 on page 96
3.5.9 on page 82
3.5.9 on page 82
3.8.2 on page 89
3.6.3 on page 86
3.6.2 on page 85
3.6.2 on page 85
3.7.1 on page 87
3.8.3 on page 90
3.8.3 on page 90
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Mnemonic
WFE
–
WFI
–
Table 20. Cortex-M3 instructions (continued)
Operands
Brief description
Flags
Wait for event
–
Wait for interrupt
–
Section
3.9.11 on page 103
3.9.12 on page 104
3.2
Intrinsic functions
ANSI cannot directly access some Cortex-M3 instructions. This section describes intrinsic functions that can generate these instructions, provided by the CMIS and that might be provided by a C compiler. If a C compiler does not support an appropriate intrinsic function, you might have to use an inline assembler to access some instructions.
The CMSIS provides the intrinsic functions listed in Table 21 to generate instructions that ANSI cannot directly access.
Table 21. CMSIS intrinsic functions to generate some Cortex-M3 instructions
Instruction
CMSIS intrinsic function
CPSIE I CPSID I
void __enable_irq(void) void __disable_irq(void)
CPSIE F
void __enable_fault_irq(void)
CPSID F ISB DSB DMB
void __disable_fault_irq(void) void __ISB(void) void __DSB(void) void __DMB(void)
REV
uint32_t __REV(uint32_t int value)
REV16 REVSH RBIT
uint32_t __REV16(uint32_t int value) uint32_t __REVSH(uint32_t int value) uint32_t __RBIT(uint32_t int value)
SEV
void __SEV(void)
WFE WFI
void __WFE(void) void __WFI(void)
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The CMSIS also provides a number of functions for accessing the special registers using MRS and MSR instructions (see Table 22).
Table 22. CMSIS intrinsic functions to access the special registers
Special register
Access
CMSIS function
PRIMASK FAULTMASK
Read Write Read Write
uint32_t __get_PRIMASK (void) void __set_PRIMASK (uint32_t value) uint32_t __get_FAULTMASK (void) void __set_FAULTMASK (uint32_t value)
BASEPRI
Read Write
uint32_t __get_BASEPRI (void) void __set_BASEPRI (uint32_t value)
CONTROL MSP
Read Write Read Write
uint32_t __get_CONTROL (void) void __set_CONTROL (uint32_t value) uint32_t __get_MSP (void) void __set_MSP (uint32_t TopOfMainStack)
PSP
Read Write
uint32_t __get_PSP (void) void __set_PSP (uint32_t TopOfProcStack)
3.3
3.3.1
About the instruction descriptions
The following sections give more information about using the instructions: · Operands on page 50 · Restrictions when using PC or SP on page 51 · Flexible second operand on page 51 · Shift operations on page 52 · Address alignment on page 55 · PC-relative expressions on page 56 · Conditional execution on page 56 · Instruction width selection on page 58.
Operands
An instruction operand can be an Arm register, a constant, or another instruction-specific parameter. Instructions act on the operands and often store the result in a destination register. When there is a destination register in the instruction, it is usually specified before the operands.
Operands in some instructions are flexible in that they can either be a register or a constant (see Flexible second operand).
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3.3.2 3.3.3
Restrictions when using PC or SP
Many instructions have restrictions on whether you can use the program counter (PC) or stack pointer (SP) for the operands or destination register. See instruction descriptions for more information.
Bit[0] of any address written to the PC with a BX, BLX, LDM, LDR, or POP instruction must be 1 for correct execution, because this bit indicates the required instruction set, and the Cortex-M3 processor only supports thumb instructions.
Flexible second operand
Many general data processing instructions have a flexible second operand. This is shown as operand2 in the descriptions of the syntax of each instruction.
Operand2 can be a: · Constant · Register with optional shift
Constant
You specify an operand2 constant in the form #constant, where constant can be: · Any constant that can be produced by shifting an 8-bit value left by any number of bits
within a 32-bit word. · Any constant of the form 0x00XY00XY · Any constant of the form 0xXY00XY00 · Any constant of the form 0xXYXYXYXY
In the constants shown above, X and Y are hexadecimal digits.
In addition, in a small number of instructions, constant can take a wider range of values. These are described in the individual instruction descriptions.
When an operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[31] of the constant, if the constant is greater than 255 and can be produced by shifting an 8-bit value. These instructions do not affect the carry flag if operand2 is any other constant.
Instruction substitution
Your assembler might be able to produce an equivalent instruction in cases where you specify a constant that is not permitted. For example, an assembler might assemble the instruction CMP Rd, #0xFFFFFFFE as the equivalent instruction CMN Rd, #0x2.
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Register with optional shift
An operand2 register is specified in the form Rm {, shift}, where: · Rm is the register holding the data for the second operand · Shift is an optional shift to be applied to Rm. It can be one of:
ASR #n: Arithmetic shift right n bits, 1 n 32 LSL #n: Logical shift left n bits, 1 n 31 LSR #n: Logical shift right n bits, 1 n 32 ROR #n: Rotate right n bits, 1 n 31 RRX: Rotate right one bit, with extend –: If omitted, no shift occurs, equivalent to LSL #0
If you omit the shift, or specify LSL #0, the instruction uses the value in Rm.
If you specify a shift, the shift is applied to the value in Rm, and the resulting 32-bit value is used by the instruction. However, the contents in the register Rm remains unchanged. Specifying a register with shift also updates the carry flag when used with certain instructions. For information on the shift operations and how they affect the carry flag, see Shift operations.
3.3.4 Shift operations
Register shift operations move the bits in a register left or right by a specified number of bits, the shift length. Register shift can be performed: · Directly by the instructions ASR, LSR, LSL, ROR, and RRX. The result is written to a
destination register. · During the calculation of operand2 by the instructions that specify the second operand
as a register with shift (see Flexible second operand on page 51). The result is used by the instruction.
The permitted shift lengths depend on the shift type and the instruction (see the individual instruction description or Flexible second operand). If the shift length is 0, no shift occurs. Register shift operations update the carry flag except when the specified shift length is 0. The following sub-sections describe the various shift operations and how they affect the carry flag. In these descriptions, Rm is the register containing the value to be shifted, and n is the shift length.
ASR
Arithmetic shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-hand 32-n bits of the result. And it copies the original bit[31] of the register into the left-hand n bits of the result (see Figure 13: ASR#3 on page 53). You can use the ASR #n operation to divide the value in the register Rm by 2n, with the result being rounded towards negative-infinity.
When the instruction is ASRS or when ASR #n is used in operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[n-1], of the register Rm.
Note: 1 If n is 32 or more, all the bits in the result are set to the value of bit[31] of Rm. 2 If n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of Rm.
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Figure 13. ASR#3
Carry Flag
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LSR
Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-hand 32-n bits of the result. And it sets the left-hand n bits of the result to 0 (see Figure 14). You can use the LSR #n operation to divide the value in the register Rm by 2n, if the value is regarded as an unsigned integer.
When the instruction is LSRS or when LSR #n is used in operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[n-1], of the register Rm.
Note: 1 If n is 32 or more, then all the bits in the result are cleared to 0. 2 If n is 33 or more and the carry flag is updated, it is updated to 0.
Figure 14. LSR#3
000
Carry Flag
31
543210
MSv39679V1
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LSL
Logical shift left by n bits moves the right-hand 32-n bits of the register Rm, to the left by n places, into the left-hand 32-n bits of the result. And it sets the right-hand n bits of the result to 0 (see Figure 15: LSL#3 on page 54). You can use the LSL #n operation to multiply the value in the register Rm by 2n, if the value is regarded as an unsigned integer or a two’s complement signed integer. Overflow can occur without warning.
When the instruction is LSLS or when LSL #n, with non-zero n, is used in operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[32-n], of the register Rm. These instructions do not affect the carry flag when used with LSL #0.
Note: 1 If n is 32 or more, then all the bits in the result are cleared to 0. 2 If n is 33 or more and the carry flag is updated, it is updated to 0.
Figure 15. LSL#3
000
31
543210
Carry Flag
MSv39678V1
ROR
Rotate right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-hand 32-n bits of the result. It also moves the right-hand n bits of the register into the left-hand n bits of the result (see Figure 16).
When the instruction is RORS or when ROR #n is used in operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit rotation, bit[n-1], of the register Rm.
Note: 1 If n is 32, then the value of the result is same as the value in Rm, and if the carry flag is updated, it is updated to bit[31] of Rm.
2 ROR with shift length, n, more than 32 is the same as ROR with shift length n-32.
Figure 16. ROR #3
Carry Flag
31
543210
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RRX
Rotate right with extend moves the bits of the register Rm to the right by one bit. And it copies the carry flag into bit[31] of the result (see Figure 17).
When the instruction is RRXS or when RRX is used in operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[0] of the register Rm.
Figure 17. RRX #3
Carry Flag
31 30
10
3.3.5
MSv39686V1
Address alignment
An aligned access is an operation where a word-aligned address is used for a word, dual word, or multiple word access, or where a halfword-aligned address is used for a halfword access. Byte accesses are always aligned.
The Cortex-M3 processor supports unaligned access only for the following instructions: · LDR, LDRT · LDRH, LDRHT · LDRSH, LDRSHT · STR, STRT · STRH, STRHT
All other load and store instructions generate a usage fault exception if they perform an unaligned access, and therefore their accesses must be address aligned. For more information about usage faults see Fault handling on page 39.
Unaligned accesses are usually slower than aligned accesses. In addition, some memory regions might not support unaligned accesses. Therefore, Arm recommends that programmers ensure that accesses are aligned. To avoid accidental generation of unaligned accesses, use the UNALIGN_TRP bit in the configuration and control register to trap all unaligned accesses, see Configuration and control register (SCB_CCR) on page 137.
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3.3.6
PC-relative expressions
A PC-relative expression or label is a symbol that represents the address of an instruction or literal data. It is represented in the instruction as the PC value plus or minus a numeric offset. The assembler calculates the required offset from the label and the address of the current instruction. If the offset is too big, the assembler produces an error.
· For the B, BL, CBNZ, and CBZ instructions, the value of the PC is the address of the current instruction plus four bytes.
· For all other instructions that use labels, the value of the PC is the address of the current instruction plus four bytes, with bit[1] of the result cleared to 0 to make it wordaligned.
· Your assembler might permit other syntaxes for PC-relative expressions, such as a label plus or minus a number, or an expression of the form [PC, #number].
3.3.7
Conditional execution
Most data processing instructions can optionally update the condition flags in the application program status register (APSR) according to the result of the operation (see Application program status register on page 17). Some instructions update all flags, and some only update a subset. If a flag is not updated, the original value is preserved. See the instruction descriptions for the flags they affect.
You can execute an instruction conditionally, based on the condition flags set in another instruction: · Immediately after the instruction that updated the flags · After any number of intervening instructions that have not updated the flags
Conditional execution is available by using conditional branches or by adding condition code suffixes to instructions. See Table 23: Condition code suffixes on page 57 for a list of the suffixes to add to instructions to make them conditional instructions. The condition code suffix enables the processor to test a condition based on the flags. If the condition test of a conditional instruction fails, the instruction: · Does not execute · Does not write any value to its destination register · Does not affect any of the flags · Does not generate any exception
Conditional instructions, except for conditional branches, must be inside an If-then instruction block. See IT on page 94 for more information and restrictions when using the IT instruction. Depending on the vendor, the assembler might automatically insert an IT instruction if you have conditional instructions outside the IT block.
Use the CBZ and CBNZ instructions to compare the value of a register against zero and branch on the result.
This section describes: · The condition flags · Condition code suffixes on page 57
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The condition flags
The APSR contains the following condition flags: · N: Set to 1 when the result of the operation is negative, otherwise cleared to 0 · Z: Set to 1 when the result of the operation is zero, otherwise cleared to 0 · C: Set to 1 when the operation results in a carry, otherwise cleared to 0. · V: Set to 1 when the operation causes an overflow, otherwise cleared to 0.
For more information about the APSR see Program status register on page 16.
A carry occurs: · If the result of an addition is greater than or equal to 232 · If the result of a subtraction is positive or zero · As the result of an inline barrel shifter operation in a move or logical instruction Overflow occurs if the result of an add, subtract, or compare is greater than or equal to 231, or less than -231.
Most instructions update the status flags only if the S suffix is specified. See the instruction descriptions for more information.
Condition code suffixes
The instructions that can be conditional have an optional condition code, shown in syntax descriptions as {cond}. Conditional execution requires a preceding IT instruction. An instruction with a condition code is only executed if the condition code flags in the APSR meet the specified condition. Table 23 shows the condition codes to use.
You can use conditional execution with the IT instruction to reduce the number of branch instructions in code.
Table 23 also shows the relationship between condition code suffixes and the N, Z, C, and V flags.
Suffix EQ NE CS or HS CC or LO MI PL VS VC HI LS GE
Table 23. Condition code suffixes
Flags
Meaning
Z = 1
Equal
Z = 0
Not equal
C = 1 C = 0 N = 1
Higher or same, unsigned Lower, unsigned < Negative
N = 0
Positive or zero
V = 1 V = 0 C = 1 and Z = 0 C = 0 or Z = 1
Overflow No overflow Higher, unsigned > Lower or same, unsigned
N = V
Greater than or equal, signed
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Suffix LT GT LE AL
Table 23. Condition code suffixes (continued)
Flags
Meaning
N! =V
Less than, signed <
Z = 0 and N = V Z = 1 and N ! = V Can have any value
Greater than, signed > Less than or equal, signed Always. This is the default when no suffix is specified.
3.3.8
Specific example 1: Absolute value shows the use of a conditional instruction to find the absolute value of a number. R0 = ABS(R1).
Specific example 1: Absolute value
MOVSR0, R1; R0 = R1, setting flags IT MI; IT instruction for the negative condition RSBMIR0, R1, #0; If negative, R0 = -R1
Specific example 2: Compare and update value shows the use of conditional instructions to update the value of R4 if the signed value R0 and R2 are greater than R1 and R3 respectively.
Specific example 2: Compare and update value
CMP R0, R1 ; compare R0 and R1, setting flags ITT GT ; IT instruction for the two GT conditions CMPGT R2, R3; if ‘greater than’, compare R2 and R3, setting flags MOVGT R4, R5 ; if still ‘greater than’, do R4 = R5
Instruction width selection
There are many instructions that can generate either a 16-bit encoding or a 32-bit encoding depending on the operands and destination register specified. For some of these instructions, you can force a specific instruction size by using an instruction width suffix. The .W suffix forces a 32-bit instruction encoding. The .N suffix forces a 16-bit instruction encoding.
If you specify an instruction width suffix and the assembler cannot generate an instruction encoding of the requested width, it generates an error.
In some cases it might be necessary to specify the .W suffix, for example if the operand is the label of an instruction or literal data, as in the case of branch instructions. This is because the assembler might not automatically generate the right size encoding.
To use an instruction width suffix, place it immediately after the instruction mnemonic and condition code, if any. Specific example 3: Instruction width selection shows instructions with the instruction width suffix.
Specific example 3: Instruction width selection
BCS.W label; creates a 32-bit instruction even for a short branch ADDS.W R0, R0, R1; creates a 32-bit instruction even though the same
; operation can be done by a 16-bit instruction
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Memory access instructions
Table 24 shows the memory access instructions:
Table 24. Memory access instructions
Mnemonic
Brief description
Section
ADR CLREX
Load PC-relative address Clear exclusive
ADR on page 60 CLREX on page 71
LDM{mode} Load multiple registers
LDM and STM on page 67
LDR{type} LDR{type} LDR{type}T
Load register using immediate offset LDR and STR, immediate offset on page 61
Load register using register offset
LDR and STR, register offset on page 63
Load register with unprivileged access LDR and STR, unprivileged on page 64
LDR
Load register using PC-relative address LDR, PC-relative on page 65
LDREX{type} Load register exclusive
LDREX and STREX on page 70
POP PUSH STM{mode}
Pop registers from stack Push registers onto stack Store multiple registers
PUSH and POP on page 68 PUSH and POP on page 68 LDM and STM on page 67
STR{type} Store register using immediate offset LDR and STR, immediate offset on page 61
STR{type} Store register using register offset
LDR and STR, register offset on page 63
STR{type}T Store register with unprivileged access LDR and STR, unprivileged on page 64
STREX{type} Store register exclusive
LDREX and STREX on page 70
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3.4.1
Note:
ADR
Load PC-relative address.
Syntax
ADR{cond} Rd, label
where: · `cond’ is an optional condition code (see Conditional execution on page 56) · `Rd’ is the destination register · `label’ is a PC-relative expression (see PC-relative expressions on page 56)
Operation
ADR determines the address by adding an immediate value to the PC. It writes the result to the destination register. ADR produces position-independent code, because the address is PC-relative. If you use ADR to generate a target address for a BX or BLX instruction, you must ensure that bit[0] of the address you generate is set to1 for correct execution. Values of label must be within the range -4095 to 4095 from the address in the PC. You might have to use the .W suffix to get the maximum offset range or to generate addresses that are not word-aligned (see Instruction width selection on page 58).
Restrictions
Rd must be neither SP nor PC.
Condition flags
This instruction does not change the flags.
Examples
ADR R1, TextMessage; write address value of a location labelled as ; TextMessage to R1
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3.4.2
LDR and STR, immediate offset
Load and store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset.
Syntax
op{type}{cond} Rt, [Rn {, #offset}]; immediate offset
op{type}{cond} Rt, [Rn, #offset]!; pre-indexed
op{type}{cond} Rt, [Rn], #offset; post-indexed
opD{cond} Rt, Rt2, [Rn {, #offset}]; immediate offset, two words
opD{cond} Rt, Rt2, [Rn, #offset]!; pre-indexed, two words
opD{cond} Rt, Rt2, [Rn], #offset; post-indexed, two words
where: · `op’ is either LDR (load register) or STR (store register) · `type’ is one of the following:
B: Unsigned byte, zero extends to 32 bits on loads SB: Signed byte, sign extends to 32 bits (LDR only) H: Unsigned halfword, zero extends to 32 bits on loads SH: Signed halfword, sign extends to 32 bits (LDR only) –: Omit, for word · `cond’ is an optional condition code (see Conditional execution on page 56) · `Rt’ is the register to load or store · `Rn’ is the register on which the memory address is based · `offset’ is an offset from Rn. If offset is omitted, the address is the contents of Rn · `Rt2′ is the additional register to load or store for two-word operations
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Operation
LDR instructions load one or two registers with a value from memory. STR instructions store one or two register values to memory.
Load and store instructions with immediate offset can use the following addressing modes: · Offset addressing
The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the address for the memory access. The register Rn is unaltered. The assembly language syntax for this mode is: [Rn, #offset]. · Pre-indexed addressing The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the address for the memory access and written back into the register Rn. The assembly language syntax for this mode is: [Rn, #offset]! · Post-indexed addressing The address obtained from the register Rn is used as the address for the memory access. The offset value is added to or subtracted from the address, and written back into the register Rn. The assembly language syntax for this mode is: [Rn], #offset.
The value to load or store can be a byte, halfword, word, or two words. Bytes and halfwords can either be signed or unsigned (see Address alignment on page 55).
Table 25 shows the range of offsets for immediate, pre-indexed and post-indexed forms.
Table 25. Immediate, pre-indexed and post-indexed offset ranges
Instruction type
Immediate offset
Pre-indexed
Post-indexed
Word, halfword, signed halfword, byte, or signed byte
-255 to 4095
-255 to 255
-255 to 255
Two words
Multiple of 4 in the Multiple of 4 in the Multiple of 4 in the range -1020 to 1020 range -1020 to 1020 range -1020 to 1020
Restrictions
· For load instructions Rt can be SP or PC for word loads only Rt must be different from Rt2 for two-word loads Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms
· When Rt is PC in a word load instruction bit[0] of the loaded value must be 1 for correct execution A branch occurs to the address created by changing bit[0] of the loaded value to 0 If the instruction is conditional, it must be the last instruction in the IT block
· For store instructions Rt can be SP for word stores only Rt must not be PC Rn must not be PC Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms
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3.4.3
Condition flags
These instructions do not change the flags.
Examples
LDRR8, [R10]; loads R8 from the address in R10. LDRNER2, [R5, #960]!; loads (conditionally) R2 from a word
; 960 bytes above the address in R5, and ; increments R5 by 960. STRR2, [R9,#const-struc]; const-struc is an expression evaluating ; to a constant in the range 0-4095. STRHR3, [R4], #4; Store R3 as halfword data into address in ; R4, then increment R4 by 4 LDRD R8, R9, [R3, #0x20]; Load R8 from a word 32 bytes above the ; address in R3, and load R9 from a word 36 ; bytes above the address in R3 STRDR0, R1, [R8], #-16; Store R0 to address in R8, and store R1 to ; a word 4 bytes above the address in R8, ; and then decrement R8 by 16.
LDR and STR, register offset
Load and store with register offset.
Syntax
op{type}{cond} Rt, [Rn, Rm {, LSL #n}]
where: · `op’ is either LDR (load register) or STR (store register) · `type’ is one of the following:
B: Unsigned byte, zero extends to 32 bits on loads SB: Signed byte, sign extends to 32 bits (LDR only) H: Unsigned halfword, zero extends to 32 bits on loads SH: Signed halfword, sign extends to 32 bits (LDR only) –: Omit, for word · `cond’ is an optional condition code (see Conditional execution on page 56) · `Rt’ is the register to load or store · `Rn’ is the register on which the memory address is based · `Rm’ is a register containing a value to be used as the offset · `LSL #n’ is an optional shift, with n in the range 0 to 3
Operation
LDR instructions load a register with a value from memory. STR instructions store a register value into memory.
The memory address to load from or store to is at an offset from the register Rn. The offset is specified by the register Rm and can be shifted left by up to 3 bits using LSL.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords can either be signed or unsigned (see Address alignment on page 55).
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3.4.4
Restrictions
In these instructions: · Rn must not be PC · Rm must be neither SP nor PC · Rt can be SP only for word loads and word stores · Rt can be PC only for word loads
When Rt is PC in a word load instruction: · bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this
halfword-aligned address · If the instruction is conditional, it must be the last instruction in the IT block.
Condition flags
These instructions do not change the flags.
Examples
STRR0, [R5, R1]; store value of R0 into an address equal to ; sum of R5 and R1
LDRSBR0, [R5, R1, LSL #1]; read byte value from an address equal to ; sum of R5 and two times R1, sign extended it ; to a word value and put it in R0
STRR0, [R1, R2, LSL #2]; stores R0 to an address equal to sum of R1 ; and four times R2
LDR and STR, unprivileged
Load and store with unprivileged access.
Syntax
op{type}T{cond} Rt, [Rn {, #offset}]; immediate offset
where: · `op’ is either LDR (load register) or STR (store register) · `type’ is one of the following:
B: Unsigned byte, zero extends to 32 bits on loads SB: Signed byte, sign extends to 32 bits (LDR only) H: Unsigned halfword, zero extends to 32 bits on loads SH: Signed halfword, sign extends to 32 bits (LDR only) –: Omit, for word · `cond’ is an optional condition code (see Conditional execution on page 56) · `Rt’ is the register to load or store · `Rn’ is the register on which the memory address is based · `offset’ is an offset from Rn and can be 0 to 255. If offset is omitted, the address is the value in Rn.
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3.4.5
Operation
These load and store instructions perform the same function as the memory access instructions with immediate offset (see LDR and STR, immediate offset on page 61). The difference is that these instructions have only unprivileged access even when used in privileged software. When used in unprivileged software, these instructions behave in exactly the same way as normal memory access instructions with immediate offset.
Restrictions
In these instructions: · Rn must not be PC · Rt must be neither SP nor PC.
Condition flags
These instructions do not change the flags.
Examples
STRBTEQR4, [R7]; conditionally store least significant byte in ; R4 to an address in R7, with unprivileged access
LDRHTR2, [R2, #8]; load halfword value from an address equal to ; sum of R2 and 8 into R2, with unprivileged access
LDR, PC-relative
Load register from memory.
Syntax
LDR{type}{cond} Rt, label
LDRD{cond} Rt, Rt2, label; load two words
where: · `type’ is one of the following:
B: Unsigned byte, zero extends to 32 bits SB: Signed byte, sign extends to 32 bits H: Unsigned halfword, sign extends to 32 bits SH: Signed halfword, sign extends to 32 bits –: Omit, for word · `cond’ is an optional condition code (see Conditional execution on page 56) · `Rt’ is the register to load or store · `Rt2′ is the second register to load or store · `label’ is a PC-relative expression (see PC-relative expressions on page 56)
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Operation
LDR loads a register with a value from a PC-relative memory address. The memory address is specified by a label or by an offset from the PC.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords can either be signed or unsigned (see Address alignment on page 55).
`label’ must be within a limited range of the current instruction. Table 26 shows the possible offsets between label and the PC.
Table 26. label-PC offset ranges
Instruction type
Offset range
Word, halfword, signed halfword, byte, signed byte Two words
-4095 to 4095 -1020 to 1020
You might have to use the .W suffix to get the maximum offset range (see Instruction width selection on page 58).
Restrictions
In these instructions: · Rt can be SP or PC only for word loads · Rt2 must be neither SP nor PC · Rt must be different from Rt2 When Rt is PC in a word load instruction: · bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this
halfword-aligned address · If the instruction is conditional, it must be the last instruction in the IT block.
Condition flags
These instructions do not change the flags.
Examples
LDRR0, LookUpTable; load R0 with a word of data from an address ; labelled as LookUpTable
LDRSBR7, localdata; load a byte value from an address labelled ; as localdata, sign extend it to a word ; value, and put it in R7
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3.4.6
LDM and STM
Load and store
Documents / Resources
 |
ST STM32F10xxx Power Supply Switch [pdf] Instruction Manual STM32F10xxx, STM32F20xxx, STM32F21xxx, STM32L1xxxx, STM32F10xxx Power Supply Switch, STM32F10xxx, Power Supply Switch, Supply Switch, Switch |