User Guide for NXP models including: FS2600, FS26, AN14492 Safety System Basis Chip, AN14492, Safety System Basis Chip, System Basis Chip, Basis Chip, Chip
10 gen 2025 — This application note is meant to be used as a launching point for software engineers, as a complement or a substitute for NXP's software drivers.
FS26 | Safety System Basis Chip with Low Power, for ASIL D Systems | NXP Semiconductors
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DocumentDocumentAN14492 FS26 software quick start guide Rev. 1.0 -- 10 January 2025 Application note Document information Information Content Keywords FS2600, Safety, SBC, automotive, low power, ASIL B, ASIL D Abstract This application note is meant to be used as a launching point for software engineers, as a complement or a substitute for NXP's software drivers. NXP Semiconductors AN14492 FS26 software quick start guide 1 Introduction This application note is meant to be used as a launching point for software engineers, as a complement or a substitute for NXP's software drivers. This document gives guidance on the implementation of the SPI communication protocol between the MCU and the FS26. It also explains the initialization procedure for the FS26 device and provides an example startup sequence. 1.1 General description This family of devices consists of several versions that are pin-to-pin and software compatible. These versions support a wide range of applications with automotive safety integrity levels (ASIL) B or D, offering choices in number of output rails, output voltage settings, operating frequencies, power-up sequencing, and integrated system-level features. The flexibility of the FS26 system basis chip (SBC) makes it suitable for S32K3 processor-based applications, as well as multivendor processors. Many OTP configurations are available, offering a choice of output voltage settings, operating frequency, powerup sequencing, and input/output configurations to address multiple applications. 1.2 Reference documents Reference documents and various materials are available on the FS26 device web page. The webpage provides more detailed information about specific topics: FS26 data sheet: Information, such as features, functional description, parametric description, register mapping. FS26 Design Guidelines application note: Information such as application schematics, bill of materials, placement and layout guidelines, application validation data including ISO/non-ISO pulses, Electromagnetic Compatibility (EMC). The low-level software driver components are provided as part of the basic enablement for the device, and do not incur an additional charge: FS26 AUTOSAR software drivers: AUTOSAR and ISO 26262-compliant basic start-up drivers for low-level interfaces. Technical documentation is available as part of the software driver package, detailing supported features such as: · SPI access register function and event handling (SBC_FS26) · Watchdog function (WDG_FS26) 2 FS26 initialization flow chart example Figure 1 gives an example of FS26 software initialization. After MCU reset is released (RSTB state goes high), the MCU can start FS26 initialization. The initialization must be done within the dedicated 256 ms INIT_FS window. Running the LBIST is optional (skipped if LBIST_STDBY_OTP[7:0] = C9h) as it is only available for ASIL D FS26 versions. Then the MCU writes INIT safety registers, ending with the INIT cyclic redundancy check (CRC). The first watchdog refresh closes the INIT phase. Therefore, the subsequent watchdog refreshes must be sent according to the watchdog timing configuration. Once the fault error counter is cleared, safety pins FS0B and FS1B can be released. AN14492 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.0 -- 10 January 2025 © 2025 NXP B.V. All rights reserved. Document feedback 2 / 16 NXP Semiconductors AN14492 FS26 software quick start guide An ABIST on demand (ABIST2) can be requested through a SPI command, to allow the system to check the integrity of the safety mechanisms at any point during the Normal mode and to detect potential latent faults when the application is running. Power On Launch LBIST Monitoring Enabled Launch ABIST 1 RSTB Release LBIST passed (LBIST_STATUS) = 0b11 All slots are ON: Normal Mode No UV/OV detected ABIST pass or fail Go to FS_INIT FS_STATE[0:4] = 0b01001 ABIST = OK LBIST = OK LBIST or ABIST fail will prevent safety outputs' release. Possible to go Low Power or restart device INIT_FS Window 256 ms Write all INIT safety registers for specific application FS_I_FSSM, FS_I_WD_CFG, FS_I_OVUV_SAFE_REACTION FS_I_SAFE_INPUTS, etc. Configure WD (Simple or Challenger, window period, duration, etc) FS_I_WD_CFG, FS_WDW_DURATION, etc. Open WD window in FS_WDW_DURATION[15:12] = 0x0000 Close INIT FS with x 1 good Watchdog refresh FS_WD_ANWER[15:0], depending on WD type: Simple or Challenger Go to FS_STATES_FS0B_ASSERT FS_STATES[0:4] = 0b01010 WD Refresh required Decrease FLT_ERR_CNT to 0 with WD_RFR_LIMIT + 1 good WD Refreshes FS_WD_ANWER[15:0], depending on WD type: Simple or Challenger EXIT_DBG_MODE == 1 FS_STATES[14] = 1 Write command to Release FS0B and FS1B RELEASE_FS0B_FS1B[15:0] == 0xB2A5 FS NORMAL MODE FS_STATES[0:4] = 0b01011 Figure 1.FS26 initialization flow chart example SW action Device event Information aaa-058063 AN14492 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.0 -- 10 January 2025 © 2025 NXP B.V. All rights reserved. Document feedback 3 / 16 NXP Semiconductors AN14492 FS26 software quick start guide 3 Startup sequence example (based on flow chart) Table 1.Startup SPI sequence example Register 1 Launch LBIST LBIST_STDBY_ OTP[7:0](0x1F) Read 2 Check LBIST FS_DIAG_ 0b01 BYPASSED SAFETY1[1:0] (0x54) 0b10 FAIL 0b11 OK 3 Monitor Enabled FS_GRL_ 0 No Failure FLAGS[12] (0x40) 1 Failure 4 Launch/Check FS_DIAG_ 0 ABIST1 Fail or ABIST SAFETY1[8] not executed (0x54) 1 ABIST1 Pass 5 RSTB Release FS_STATES[4:0] 0b01000 RSTB (0x57) Release 6 INIT_FS FS_STATES[4:0] 0b01001 INIT_FS (0x57) 7 Configure Init FS_I_FSSM(0x49) Safety Registers FS_I_OVUV_ SAFE_ REACTION(0x42) FS_I_SAFE_ INPUTS(0x47) Write Comment 0x00 LBIST always Applicable for ASIL performed D applications C9h LBIST Bypass only: LBIST from standby mode LBIST_STATUS: (MSB = LBIST_ CHK_PAT_OK, LSB = LBIST_ CHECKER_OK) FS_REG_OVUV_ G: Flags Reporting: VPRE_OV, VPRE_ UV, CORE_ OV, CORE_UV, LDO1_OV, LDO1_ UV, LDO2_OV, LDO2_UV, TRK1_ OV, TRK1_UV, TRK2_OV, TRK2_ UV, REF_OV, REF_UV, EXT_OV, EXT_UV Report ABIST2 status 0x50c1 0x9999 0x238d Actual Sate of the Fail Safe State machine Actual Sate of the Fail Safe State machine Configure error counter limits, error reaction, reset duration, etc Configure reaction of safety machine in case of under or over voltages on regulators. Configure modes, polarity and reactions to FCCU and ERRMON AN14492 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.0 -- 10 January 2025 © 2025 NXP B.V. All rights reserved. Document feedback 4 / 16 NXP Semiconductors Table 1.Startup SPI sequence example...continued Register 8 Configure FS_I_WD_ Watchdog CFG(0x45) Read FS_WDW_ DURATION(0x4B) 10 Close INIT FS FS_WD_ ANWER[15:0](0x4 D) 11 Go to FS_ FS_STATES[0:4] 0b01010. STATES_FS0B_ (0x57) ASSERT 12 Send 7x good WD FS_WD_TOKEN 0x5AB2 refresh (if WD_ (0x4E) ERR_LIMIT = 6 and FLT_ERR_ CNT = 1) FS_WD_ANSWER (0x4D) FS_WD_TOKEN 0x5AB2 (0x4E) FS_WD_ANSWER (0x4D) FS_WD_TOKEN 0x5AB2 (0x4E) FS_WD_ANSWER (0x4D) FS_WD_TOKEN 0x5AB2 (0x4E) FS_WD_ANSWER (0x4D) FS_WD_TOKEN 0x5AB2 (0x4E) FS_WD_ANSWER (0x4D) FS_WD_TOKEN 0x5AB2 (0x4E) FS_WD_ANSWER (0x4D) FS_WD_TOKEN 0x5AB2 (0x4E) FS_WD_ANSWER (0x4D) 13 Leave Debug FS_STATES[14] Mode (0x57) AN14492 FS26 software quick start guide Write 0x4200 0x008B 0x5AB2 0x5AB2 0x5AB2 0x5AB2 0x5AB2 0x5AB2 0x5AB2 0x5AB2 1 Comment Configure WD error counter limit, reaction to error, refresh counter, etc. Configure WD window duration x1 good Watchdog refresh You can verify the closing of INIT_FS state by reading Read watchdog token Watchdog answer is 0x5A2B (default value) Read watchdog token Watchdog answer is 0x5A2B Read watchdog token Watchdog answer is 0x5A2B Read watchdog token Watchdog answer is 0x5A2B Read watchdog token Watchdog answer is 0x5A2B Read watchdog token Watchdog answer is 0x5A2B Read watchdog token Watchdog answer is 0x5A2B EXIT_DBG_MODE AN14492 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.0 -- 10 January 2025 © 2025 NXP B.V. All rights reserved. Document feedback 5 / 16 NXP Semiconductors Table 1.Startup SPI sequence example...continued Register 14 Release FS0B FS_RELEASE_ and FS1B FS0B_FS1B (0x51) 15 FS NORMAL FS_STATES[0:4] MODE Read 0b01011 AN14492 FS26 software quick start guide Write 0xA565 Comment You can verify the release of FS0B and FS1B state AN14492 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.0 -- 10 January 2025 © 2025 NXP B.V. All rights reserved. Document feedback 6 / 16 NXP Semiconductors 4 Register mapping of main logic AN14492 FS26 software quick start guide LEGEND READ/ WRITE READ WRITE Address (Hex) Register Name 15 14 13 00 M_DEVICEID FULL_LAYER_REV [15:13] 01 M_PROGID 02 M_STATUS TWARN_S VDBG_ VOLT_S VBST_ ACTIVE_S 03 M_TSD_FLG TWARN_I 0 0 04 M_TSD_MSK TWARN_M 0 0 05 M_REG_FLG 0 0 0 06 M_REG_MSK 0 0 0 07 M_VSUP_ FLG 0 0 0 08 M_VSUP_ MSK 0 0 0 09 M_WIO_FLG WU_CLR 0 0 0A M_WIO_MSK 0 0 0 0B M_COM_FLG 0 0 0 0C M_COM_MSK 0 0 0 0D M_SYS_CFG 0E M_TSD_CFG 0 0F M_REG_CFG 0 10 M_WIO_CFG 0 11 M_REG_ CTRL1 0 12 M_REG_ CTRL2 0 13 M_AMUX_ CTRL 0 14 M_LDT_CFG1 15 M_LDT_CFG2 16 M_LDT_CFG3 0 17 M_LDT_CTRL 0 18 M_MEMORY0 0 0 0 0 0 0 0 GPIO2LP_ON 0 0 0 0 0 0 12 11 10 9 8 7 6 5 4 3 2 1 0 METAL_LAYER_REV [12:10] PROG_IDH [15:8] VBSTFB_ UV_S WK2_S WK1_S 0 0 0 GPIO2_S 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WUEVENT [11:8] 0 0 0 0 0 0 0 0 0 0 0 0 RETRY_CNT [15:8] 0 0 0 GPIO1 LP_ON 0 0 GPIO2 WUPOL 0 0 0 GPIO1 WUPOL 0 0 0 WAKE2 POL GPIO2HI FAM_ID [9:6] DEV_ID [5:0] PROG_IDL [7:0] GPIO1_S VREF_S VBST_S VPRE_S TRK2_S TRK1_S CORE_S LDO2_S LDO1_S 0 0 GPIO1 TSD_I VPRETSD_I TRK2TSD_I TRK1TSD_I CORETSD_I LDO2TSD_I LDO1TSD_I 0 0 GPIO1 TSD_M VPRETSD_ M TRK2 TSD_M TRK1 TSD_M CORETSD_ M LDO2 TSD_M LDO1 TSD_M VBSTOV_I VPREUVH_I VBSTOC_I VPREOC_I TRK2OC_I TRK1OC_I COREOC_I LDO2OC_I LDO1OC_I VBSTOV_ M VPREUVH_ M VBSTOC_M VPREOC_ M TRK2OC_M TRK1OC_M COREOC_M LDO2OC_M LDO1OC_M 0 0 0 0 0 VBOSUVH_ I VSUPOV_I VSUPUV6_I VSUPUVH_I 0 0 0 0 0 VBOSUVH_ M VSUPOV_M VSUPUV6_ M VSUPUVH_ M LDT_I IO2_I IO1_I WK2_I WK1_I 0 0 0 0 LDT_M IO2_M IO1_M WK2_M WK1_M 0 0 0 0 0 0 MSPI_ CRC_I MSPI_ CLK_I MSPI_ REQ_I 0 0 0 0 0 0 MSPI_ CRC_M MSPI_ CLK_M MSPI_ REQ_M RETRY_ CLR 0 0 INTB_TEST INT_ PWIDTH FSS_FMOD 0 FSS_EN 0 0 0 VPRETDFS TRK2TDFS TRK1TDFS CORETDFS LDO2TDFS LDO1TDFS 0 0 0 0 0 0 0 VREF_PD VBST_TMD WAKE1 POL 0 0 CSBWUEN LDTWUEN GPIO2 WUEN GPIO1 WUEN WK2WUEN WK1WUEN GPIO1HI VREFEN VBSTEN 0 TRK2EN TRK1EN COREEN LDO2EN LDO1EN IO2LO IO1LO VREFDIS VBSTDIS 0 TRK2DIS TRK1DIS COREDIS LDO2DIS LDO1DIS 0 0 0 0 0 0 AMUX_EN AMUX_DIV AMUX LDT_AFTER_RUN [15:0] LDT_WUP_L [15:0] 0 0 0 0 0 0 0 0 0 0 0 MEM0 [15:0] LDT_FNCT [6:4] LDT_WUP_H [7:0] LDT_SEL LDT_MODE LDT_EN LDT_RUN AN14492 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.0 -- 10 January 2025 © 2025 NXP B.V. All rights reserved. Document feedback 7 / 16 NXP Semiconductors LEGEND 19 M_MEMORY1 READ/ WRITE READ WRITE MEM1 [15:0] AN14492 FS26 software quick start guide 5 Register mapping of fail-safe logic Table 2.Register mapping of fail-safe logic Addr Hex Register 15 14 13 12 11 10 Name 40 FS_GRL_ FS_COM_G FS_WD_G FS_IO_G FS_REG_ FS_BIST_G 0 FLAGS OVUV_G 41 FS_I_ VMON_PRE_OV_FS_ OVUV_ REACTION SAFE_ REACTION1 VMON_PRE_UV_FS_ REACTION VMON_CORE_OV_FS_ REACTION 42 FS_I_NOT_ NOT_VMON_PRE_OV_ NOT_VMON_PRE_UV_ NOT_VMON_CORE_OV_ OVUV_ FS_REACTION FS_REACTION FS_REACTION SAFE_ REACTION1 43 FS_I_ VMON_EXT_OV_FS_ OVUV_ REACTION SAFE_ REACTION2 VMON_EXT_UV_FS_ REACTION VMON_REF_OV_FS_ REACTION 44 FS_I_NOT_ NOT_VMON_EXT_OV_ NOT_VMON_EXT_UV_ NOT_VMON_REF_OV_ OVUV_ FS_REACTION FS_REACTION FS_REACTION SAFE_ REACTION2 45 FS_I_WD_ WD_ERR_LIMIT 0 WD_RFR_LIMIT 0 CFG 46 FS_I_NOT_ NOT_WD_ERR_LIMIT 0 WD_CFG NOT_WD_RFR_LIMIT 0 47 FS_I_ FCCU_CFG [15:13] SAFE_ INPUTS FCCU12_ FLT_POL FCCU1_ FLT_POL FCCU2_ FLT_POL 48 FS_I_NOT_ NO_FCCU_CFG [15:13] SAFE_ INPUTS NO_ FCCU12_ FLT_POL NO_ FCCU1_ FLT_POL NO_ FCCU2_ FLT_POL 49 FS_I_FSSM FLT_ERR_CNT_LIMIT 0 [15:14] FLT_ERR_REACTION 0 [12:11] 4A FS_I_NOT_ NO_FLT_ERR_CNT_LIMIT 0 FSSM [15:14] NO_FLT_ERR_REACTION 0 [12:11] 4B FS_WDW_ WDW_PERIOD DURATION 4C FS_NOT_ NO_WDW_PERIOD WDW_ DURATION 0 0 0 0 9 8 7 6 0 0 0 0 VMON_CORE_UV_FS_ REACTION VMON_LDO1_OV_FS_ REACTION 5 4 0 0 VMON_LDO1_UV_FS_ REACTION 3 2 0 0 VMON_LDO2_OV_FS_ REACTION NOT_VMON_CORE_UV_ FS_REACTION NOT_VMON_LDO1_OV_ FS_REACTION NOT_VMON_LDO1_UV_ FS_REACTION NOT_VMON_LDO2_OV_ FS_REACTION VMON_REF_UV_FS_ REACTION VMON_TRK2_OV_FS_ REACTION VMON_TRK2_UV_FS_ REACTION VMON_TRK1_OV_FS_ REACTION NOT_VMON_REF_UV_ FS_REACTION NOT_VMON_TRK2_OV_ FS_REACTION NOT_VMON_TRK2_UV_ FS_REACTION NOT_VMON_TRK1_OV_ FS_REACTION WD_FS_REACTION 0 WD_RFR_CNT [6:4] WD_ERR_CNT [3:0] NOT_WD_FS_REACTION 0 NOT_WD_RFR_CNT [6:4] NOT_WD_ERR_CNT [3:0] FCCU12_ FS_ REACTION FCCU1_FS_ FCCU2_FS_ 0 REACTION REACTION NO_ FCCU12_ FS_ REACTION NO_ NO_ 1 FCCU1_FS_ FCCU2_FS_ REACTION REACTION RSTB_DUR 0 BACKUP_ 0 SAFETY_ PATH_FS0B NO_RSTB_ 0 DUR NO_ 1 BACKUP_ SAFETY_ PATH_FS0B 0 WDW_DC 0 ERRMON_ FLT_ POLARITY ERRMON_ACK_TIME [4:3] ERRMON_ FS_ REACTION NO_ ERRMON_ FLT_ POLARITY NO_ERRMON_ACK_TIME [4:3] NO_ ERRMON_ FS_ REACTION CLK_MON_ DIS8S DIS FLT_ERR_CNT [3:0] NO_CLK_ MON_DIS NO_DIS8S NO_FLT_ERR_CNT [3:0] 0 0 WDW_RECOVERY 0 NO_WDW_DC 0 0 0 NO_WDW_RECOVERY 1 0 0 0 VMON_LDO2_UV_FS_ REACTION NOT_VMON_LDO2_UV_ FS_REACTION VMON_TRK1_UV_FS_ REACTION NOT_VMON_TRK1_UV_ FS_REACTION FCCU12_FILT [1:0] NO_FCCU12_FILT [1:0] AN14492 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.0 -- 10 January 2025 © 2025 NXP B.V. All rights reserved. Document feedback 8 / 16 NXP Semiconductors Table 2.Register mapping of fail-safe logic...continued Addr Hex Register 15 14 13 12 Name 4D FS_WD_ WD_ANSWER [15:0] ANSWER 4E FS_WD_ WD_TOKEN [15:0] TOKEN 4F FS_ABIST_ LAUNCH_ 0 0 0 ON_ ABIST2 DEMAND 50 FS_OVUV_ VPRE_OV VPRE_UV CORE_OV CORE_UV REG_ STATUS 51 FS_ RELEASE_FS0B_FS1B RELEASE_ FS0B_FS1B 52 FS_SAFE_ EXT_RSTB RSTB_DRV RSTB_SNS RSTB_ IOS_1 EVENT 53 FS_SAFE_ 0 0 0 0 IOS_2 54 FS_DIAG_ 0 0 0 0 SAFETY1 55 FS_DIAG_ 0 0 0 0 SAFETY2 56 FS_INTB_ VPRE_M CORE_M LDO1_M LDO2_M MASK 57 FS_STATES 0 EXIT_DBG_ DBG_MODE OTP_ MODE CORRUPT 58 FS_LP_REQ 0 0 0 0 59 FS_LDT_ 0 0 0 0 LPSEL 11 10 9 8 0 0 0 0 LDO1_OV LDO1_UV LDO2_OV LDO2_UV RSTB_DIAG RSTB_REQ FS0B_DRV FS0B_SNS 0 0 FS1B_TDELAY [9:5] 0 BAD_WD_ BAD_WD_ ABIST1_ DATA TIMING PASS 0 0 0 0 TRK1_M TRK2_M REG_ 0 CORRUPT 0 0 0 0 REF_M 0 0 0 EXT_M 0 STBY_ WAKE_UP 0 AN14492 FS26 software quick start guide 7 6 5 4 3 2 1 0 ABIST2_ EXT ABIST2_ REF ABIST2_ TRK2 ABIST2_ TRK1 ABIST2_ LDO2 TRK1_OV TRK1_UV TRK2_OV TRK2_UV REF_OV ABIST2_ LDO1 REF_UV ABIST2_ CORE EXT_OV ABIST2_ VPRE EXT_UV FS0B_DIAG FS0B_REQ FS1B_DRV FS1B_SNS FS1N_DIAG FS1B_REQ GOTO_INIT 0 FS1B_TDUR [4:0] ABIST2_ PASS FCCU12 FCCU1_M 0 ABIST2_ DONE FCCU1 FCCU2_M 0 SPI_FS_ CLK FCCU2 SPI_FS_ REQ FCCU1_RT SPI_FS_ CRC FCCU2_RT FS_OSC_ DRIFT ERRMON_ ACK BAD_WD_M ERRMON_ 0 0 M 0 FS_STATES LBIST_STATUS [1:0] ERRMON 0 ERRMON_ PIN_ STATUS 0 FS_LP_REQ LDT_SEL AN14492 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.0 -- 10 January 2025 © 2025 NXP B.V. All rights reserved. Document feedback 9 / 16 NXP Semiconductors AN14492 FS26 software quick start guide 6 Watchdog answer procedure A watchdog is implemented through the SPI bus to continuously check the microcontroller software activity and its ability to perform basic computing. The FS26 performs this check by waiting for a specific answer from the microcontroller during a predefined period called the watchdog window. The first half of the watchdog window is said to be CLOSED and the second half is said to be OPEN. A good watchdog refresh is a good watchdog answer during the OPEN window. A bad watchdog refresh is a bad watchdog answer during the OPEN window, no watchdog refresh during the OPEN window, or a good watchdog answer during the CLOSED window. After a good or a bad watchdog refresh, a new window period starts immediately for the microcontroller to keep the synchronization with the windowed watchdog. Table 3.Watchdog answer procedure SPI Window watchdog CLOSED OPEN BAD key WD_NOK WD_NOK GOOD key WD_NOK WD_OK None (timeout) NA WD_NOK Timeout watchdog (always open) WD_NOK WD_OK WD_NOK 6.1 Simple watchdog The simple watchdog monitoring feature is enabled for ASIL B devices. The microcontroller can send its own seed in FS_WD_TOKEN register or can use the default value 0x5AB2. This seed must be written in the FS_WD_ANSWER register during the OPEN watchdog window. When the result is right, the watchdog window is restarted. When the result is wrong, the WD error counter is incremented, and the watchdog window is restarted. In simple watchdog configuration, it is impossible to write 0xFFFF and 0x0000 in the FS_WD_TOKEN register. A communication error is reported in case of 0x0000 and 0xFFFF write tentative and the configuration is ignored. 6.2 Challenger watchdog The challenger watchdog monitoring feature is enabled for ASIL D devices. The challenger watchdog is based on a question/answer process with the microcontroller. A 16-bit pseudo-random word is generated by implementing a linear feedback shift register (LFSR) in the FS26. During the initialization phase, the microcontroller can send its own seed for the LFSR, or it can use the default LFSR value generated by the FS26 (0x5AB2), available in the FS_WD_TOKEN register. With the LFSR value, the microcontroller performs a simple calculation based on the formula below and sends the results in the FS_WD_ANSWER register. The result is sent through the SPI bus during the OPEN watchdog window and is verified by the FS26. When the result is right, the watchdog window is restarted and a new LFSR is generated. When the result is wrong, the WD error counter is incremented, the watchdog window is restarted, and the LFSR value is not changed. FS_WD_TOKEN [23:8] x + - NOT / FS_WD_ANSWER [23:8] 4 6 4 Figure 2.Challenger watchdog 4 aaa- 058064 AN14492 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.0 -- 10 January 2025 © 2025 NXP B.V. All rights reserved. Document feedback 10 / 16 NXP Semiconductors AN14492 FS26 software quick start guide 7 Cyclic redundancy check An 8-bit cyclic redundancy check (CRC) is required for each write and read SPI command. Computation of a cyclic redundancy check is derived from the mathematics of polynomial division, modulo two. The CRC polynomial used is x^8+x^4+x^3+x^2+1 (identified by 0x1D) with a SEED value of hexadecimal '0xFF'. C0 C1 C2 C3 C4 C5 C6 C7 T T + T + T + T T T T 1*1 0*X 1*X2 1*X3 1*X4 0*X5 0*X6 0*X7 + 1*X8 Figure 3.Cyclic redundancy check Input data aaa- 058065 8 FS0B/FS1B release procedure The procedure to compute the RELEASE_FS0B_FS1B [15:0] value to release the safety outputs is described in Table 4, illustrating all these steps with an example: 1. Get the FS_WD_TOKEN value. 2. Swap MSB/LSB of the value get in step No. 1. 3. Invert all computed bits at step No. 2. 4. Write bits 12 to 0 computed in step No. 3 into RELEASE_FS0B_FS1B [12:0] register. Bits 15 to 13 are used to select the safety output(s) to release as shown in Table 5. Table 4.Procedure to compute the RELEASE_FS0B_FS1B [15:0] value Step #1 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Read FS_WD_TOKEN register 1 1 1 0 0 10011110000 Step #1 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Reverse LSB/MSB 0 0 0 0 1 11100100111 Step #1 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Complement bits 1 1 1 1 0 00011011000 Step #1 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Write RELEASE_FS0B_FS1B[12:0] 1 0 1 1 0 00011011000 Table 5.RELEASE_FS0B_FS1B bits Bit Symbol 15 to 13 RELEASE_FS0B_FS1B[15:13] Description Bits to select the desired safety output to release 011 Release FS0B only 110 Release FS1B only 101 Release FS0B and FS1B AN14492 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.0 -- 10 January 2025 © 2025 NXP B.V. All rights reserved. Document feedback 11 / 16 NXP Semiconductors 9 Summary of references Documentation [1] FS26 device webpage [2] FS26 design guidelines application note Software resources [3] FS26 AUTOSAR software drivers Evaluation resources [4] FS26 graphical user interface (GUI) [5] Socketed evaluation board [6] Soldered evaluation board AN14492 FS26 software quick start guide AN14492 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.0 -- 10 January 2025 © 2025 NXP B.V. All rights reserved. Document feedback 12 / 16 NXP Semiconductors 10 Revision history Table 6.Revision history Document ID Release date AN14492 v.1.0 10 Jan. 2025 Description Initial version AN14492 FS26 software quick start guide AN14492 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.0 -- 10 January 2025 © 2025 NXP B.V. All rights reserved. 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Accordingly, customer will indemnify and hold NXP harmless from any claims, liabilities, damages and associated costs and expenses (including attorneys' fees) that NXP may incur related to customer's incorporation of any product in a Critical Application. NXP B.V. -- NXP B.V. is not an operating company and it does not distribute or sell products. Trademarks Notice: All referenced brands, product names, service names, and trademarks are the property of their respective owners. NXP -- wordmark and logo are trademarks of NXP B.V. AN14492 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.0 -- 10 January 2025 © 2025 NXP B.V. All rights reserved. Document feedback 14 / 16 NXP Semiconductors AN14492 FS26 software quick start guide Tables Tab. 1. Tab. 2. Tab. 3. Startup SPI sequence example .........................4 Register mapping of fail-safe logic .................... 8 Watchdog answer procedure .......................... 10 Tab. 4. Tab. 5. Tab. 6. Procedure to compute the RELEASE_ FS0B_FS1B [15:0] value .................................11 RELEASE_FS0B_FS1B bits ........................... 11 Revision history ...............................................13 Figures Fig. 1. Fig. 2. FS26 initialization flow chart example ............... 3 Challenger watchdog .......................................10 Fig. 3. Cyclic redundancy check ................................ 11 AN14492 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.0 -- 10 January 2025 © 2025 NXP B.V. All rights reserved. Document feedback 15 / 16 NXP Semiconductors Contents 1 Introduction ...................................................... 2 1.1 General description ............................................2 1.2 Reference documents ........................................2 2 FS26 initialization flow chart example ........... 2 3 Startup sequence example (based on flow chart) ........................................................ 4 4 Register mapping of main logic ..................... 7 5 Register mapping of fail-safe logic ................ 8 6 Watchdog answer procedure ........................10 6.1 Simple watchdog ............................................. 10 6.2 Challenger watchdog ....................................... 10 7 Cyclic redundancy check ..............................11 8 FS0B/FS1B release procedure ..................... 11 9 Summary of references .................................12 10 Revision history .............................................13 Legal information ...........................................14 AN14492 FS26 software quick start guide Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © 2025 NXP B.V. All rights reserved. For more information, please visit: https://www.nxp.com Document feedback Date of release: 10 January 2025 Document identifier: AN14492
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