User Manual Q&AAnswer
Nov 02, 2025 - 01:31 PM
To replace PLLs and DCMs in your Xilinx Spartan 6 design using Libero SoC Design Suite, follow these steps as outlined in the MICROCHIP Xilinx Spartan 6 Example Conversion User Guide:
1. **Select IP Catalog in Libero SoC Design Suite:**
- Open Libero SoC Design Suite and navigate to the IP Catalog.
2. **Create Clock Conditioning Circuit (CCC) for Required Frequencies:**
- Within the IP Catalog, create a Clock Conditioning Circuit (CCC) to generate the required frequencies for your design.
3. **Choose Advanced Tab for Reset:**
- When configuring the CCC, ensure to select the "Advanced" tab for any reset settings or additional configurations.
4. **Replace Individual Clock Buffers (BUFG):**
- Designs often contain instantiated clock buffers. Replace the BUFG instances with the appropriate clock buffer for your target architecture.
- Vendor-specific libraries may need to be updated (e.g., Unisim to smartfusion, smartfusion2, polarfire).
5. **Documentation: Macro Library Guide:**
- Refer to the Macro Library Guide provided for specific instructions on replacing PLLs and DCMs for different architectures.
6. **Replace Block RAM:**
- Create new LSRAM from the IP Catalog and configure it according to your design requirements.
7. **Create Shim:**
- Take the existing port map of Block RAM, create a new HDL file, and adapt the port map of the shim accordingly.
8. **Instantiate LSRAM into Shim:**
- Take the entity declaration from the IP file and connect the shim ports with the instance of LSRAM.
9. **Update Design Hierarchy:**
- Click on "Build Hierarchy" to integrate sources under the root design and ensure proper organization.
10. **Constraints:**
- Double click on "Manage Constraints" to enter timing constraints and create derived constraints as needed.
11. **Constrain Clock Domain Crossings:**
- Ensure proper constraints are in place to manage clock domain crossings effectively.
12. **Assign Pins:**
- Use the Constraints Manager to assign pins either via a table or package to ensure correct connectivity.
13. **Implement Design:**
- Place and route the design, check timing, and perform timing closure to optimize performance.
14. **Create Bitstream:**
- Once all steps are completed, generate the bitstream for programming the FPGA.
15. **Finalize:**
- After completing the above steps, your Xilinx Spartan 6 design should be ready for use. Enjoy the longevity of your new FPGA design.
By following these steps, you can successfully replace PLLs and DCMs in your Xilinx Spartan 6 design using Libero SoC Design Suite.
Add New Comment